mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f7xx_hal_dsi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f7xx_hal_dsi.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of DSI HAL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F7xx_HAL_DSI_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F7xx_HAL_DSI_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
AnnaBridge	171:3a7713b1edbc	45	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	46	#include "stm32f7xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	47
AnnaBridge	171:3a7713b1edbc	48	/** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	49	* @{
AnnaBridge	171:3a7713b1edbc	50	*/
AnnaBridge	171:3a7713b1edbc	51
AnnaBridge	171:3a7713b1edbc	52	/** @defgroup DSI DSI
AnnaBridge	171:3a7713b1edbc	53	* @brief DSI HAL module driver
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/**
AnnaBridge	171:3a7713b1edbc	59	* @brief DSI Init Structure definition
AnnaBridge	171:3a7713b1edbc	60	*/
AnnaBridge	171:3a7713b1edbc	61	typedef struct
AnnaBridge	171:3a7713b1edbc	62	{
AnnaBridge	171:3a7713b1edbc	63	uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
AnnaBridge	171:3a7713b1edbc	64	This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
AnnaBridge	171:3a7713b1edbc	65
AnnaBridge	171:3a7713b1edbc	66	uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
AnnaBridge	171:3a7713b1edbc	67	The values 0 and 1 stop the TX_ESC clock generation */
AnnaBridge	171:3a7713b1edbc	68
AnnaBridge	171:3a7713b1edbc	69	uint32_t NumberOfLanes; /*!< Number of lanes
AnnaBridge	171:3a7713b1edbc	70	This parameter can be any value of @ref DSI_Number_Of_Lanes */
AnnaBridge	171:3a7713b1edbc	71
AnnaBridge	171:3a7713b1edbc	72	}DSI_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	73
AnnaBridge	171:3a7713b1edbc	74	/**
AnnaBridge	171:3a7713b1edbc	75	* @brief DSI PLL Clock structure definition
AnnaBridge	171:3a7713b1edbc	76	*/
AnnaBridge	171:3a7713b1edbc	77	typedef struct
AnnaBridge	171:3a7713b1edbc	78	{
AnnaBridge	171:3a7713b1edbc	79	uint32_t PLLNDIV; /*!< PLL Loop Division Factor
AnnaBridge	171:3a7713b1edbc	80	This parameter must be a value between 10 and 125 */
AnnaBridge	171:3a7713b1edbc	81
AnnaBridge	171:3a7713b1edbc	82	uint32_t PLLIDF; /*!< PLL Input Division Factor
AnnaBridge	171:3a7713b1edbc	83	This parameter can be any value of @ref DSI_PLL_IDF */
AnnaBridge	171:3a7713b1edbc	84
AnnaBridge	171:3a7713b1edbc	85	uint32_t PLLODF; /*!< PLL Output Division Factor
AnnaBridge	171:3a7713b1edbc	86	This parameter can be any value of @ref DSI_PLL_ODF */
AnnaBridge	171:3a7713b1edbc	87
AnnaBridge	171:3a7713b1edbc	88	}DSI_PLLInitTypeDef;
AnnaBridge	171:3a7713b1edbc	89
AnnaBridge	171:3a7713b1edbc	90	/**
AnnaBridge	171:3a7713b1edbc	91	* @brief DSI Video mode configuration
AnnaBridge	171:3a7713b1edbc	92	*/
AnnaBridge	171:3a7713b1edbc	93	typedef struct
AnnaBridge	171:3a7713b1edbc	94	{
AnnaBridge	171:3a7713b1edbc	95	uint32_t VirtualChannelID; /!< Virtual channel ID /
AnnaBridge	171:3a7713b1edbc	96
AnnaBridge	171:3a7713b1edbc	97	uint32_t ColorCoding; /*!< Color coding for LTDC interface
AnnaBridge	171:3a7713b1edbc	98	This parameter can be any value of @ref DSI_Color_Coding */
AnnaBridge	171:3a7713b1edbc	99
AnnaBridge	171:3a7713b1edbc	100	uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
AnnaBridge	171:3a7713b1edbc	101	18-bit configuration).
AnnaBridge	171:3a7713b1edbc	102	This parameter can be any value of @ref DSI_LooselyPacked */
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	uint32_t Mode; /*!< Video mode type
AnnaBridge	171:3a7713b1edbc	105	This parameter can be any value of @ref DSI_Video_Mode_Type */
AnnaBridge	171:3a7713b1edbc	106
AnnaBridge	171:3a7713b1edbc	107	uint32_t PacketSize; /!< Video packet size /
AnnaBridge	171:3a7713b1edbc	108
AnnaBridge	171:3a7713b1edbc	109	uint32_t NumberOfChunks; /!< Number of chunks /
AnnaBridge	171:3a7713b1edbc	110
AnnaBridge	171:3a7713b1edbc	111	uint32_t NullPacketSize; /!< Null packet size /
AnnaBridge	171:3a7713b1edbc	112
AnnaBridge	171:3a7713b1edbc	113	uint32_t HSPolarity; /*!< HSYNC pin polarity
AnnaBridge	171:3a7713b1edbc	114	This parameter can be any value of @ref DSI_HSYNC_Polarity */
AnnaBridge	171:3a7713b1edbc	115
AnnaBridge	171:3a7713b1edbc	116	uint32_t VSPolarity; /*!< VSYNC pin polarity
AnnaBridge	171:3a7713b1edbc	117	This parameter can be any value of @ref DSI_VSYNC_Polarity */
AnnaBridge	171:3a7713b1edbc	118
AnnaBridge	171:3a7713b1edbc	119	uint32_t DEPolarity; /*!< Data Enable pin polarity
AnnaBridge	171:3a7713b1edbc	120	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
AnnaBridge	171:3a7713b1edbc	121
AnnaBridge	171:3a7713b1edbc	122	uint32_t HorizontalSyncActive; /!< Horizontal synchronism active duration (in lane byte clock cycles) /
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	uint32_t HorizontalBackPorch; /!< Horizontal back-porch duration (in lane byte clock cycles) /
AnnaBridge	171:3a7713b1edbc	125
AnnaBridge	171:3a7713b1edbc	126	uint32_t HorizontalLine; /!< Horizontal line duration (in lane byte clock cycles) /
AnnaBridge	171:3a7713b1edbc	127
AnnaBridge	171:3a7713b1edbc	128	uint32_t VerticalSyncActive; /!< Vertical synchronism active duration /
AnnaBridge	171:3a7713b1edbc	129
AnnaBridge	171:3a7713b1edbc	130	uint32_t VerticalBackPorch; /!< Vertical back-porch duration /
AnnaBridge	171:3a7713b1edbc	131
AnnaBridge	171:3a7713b1edbc	132	uint32_t VerticalFrontPorch; /!< Vertical front-porch duration /
AnnaBridge	171:3a7713b1edbc	133
AnnaBridge	171:3a7713b1edbc	134	uint32_t VerticalActive; /!< Vertical active duration /
AnnaBridge	171:3a7713b1edbc	135
AnnaBridge	171:3a7713b1edbc	136	uint32_t LPCommandEnable; /*!< Low-power command enable
AnnaBridge	171:3a7713b1edbc	137	This parameter can be any value of @ref DSI_LP_Command */
AnnaBridge	171:3a7713b1edbc	138
AnnaBridge	171:3a7713b1edbc	139	uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
AnnaBridge	171:3a7713b1edbc	140	can fit in a line during VSA, VBP and VFP regions */
AnnaBridge	171:3a7713b1edbc	141
AnnaBridge	171:3a7713b1edbc	142	uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
AnnaBridge	171:3a7713b1edbc	143	can fit in a line during VACT region */
AnnaBridge	171:3a7713b1edbc	144
AnnaBridge	171:3a7713b1edbc	145	uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
AnnaBridge	171:3a7713b1edbc	146	This parameter can be any value of @ref DSI_LP_HFP */
AnnaBridge	171:3a7713b1edbc	147
AnnaBridge	171:3a7713b1edbc	148	uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
AnnaBridge	171:3a7713b1edbc	149	This parameter can be any value of @ref DSI_LP_HBP */
AnnaBridge	171:3a7713b1edbc	150
AnnaBridge	171:3a7713b1edbc	151	uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
AnnaBridge	171:3a7713b1edbc	152	This parameter can be any value of @ref DSI_LP_VACT */
AnnaBridge	171:3a7713b1edbc	153
AnnaBridge	171:3a7713b1edbc	154	uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
AnnaBridge	171:3a7713b1edbc	155	This parameter can be any value of @ref DSI_LP_VFP */
AnnaBridge	171:3a7713b1edbc	156
AnnaBridge	171:3a7713b1edbc	157	uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
AnnaBridge	171:3a7713b1edbc	158	This parameter can be any value of @ref DSI_LP_VBP */
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
AnnaBridge	171:3a7713b1edbc	161	This parameter can be any value of @ref DSI_LP_VSYNC */
AnnaBridge	171:3a7713b1edbc	162
AnnaBridge	171:3a7713b1edbc	163	uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
AnnaBridge	171:3a7713b1edbc	164	This parameter can be any value of @ref DSI_FBTA_acknowledge */
AnnaBridge	171:3a7713b1edbc	165
AnnaBridge	171:3a7713b1edbc	166	}DSI_VidCfgTypeDef;
AnnaBridge	171:3a7713b1edbc	167
AnnaBridge	171:3a7713b1edbc	168	/**
AnnaBridge	171:3a7713b1edbc	169	* @brief DSI Adapted command mode configuration
AnnaBridge	171:3a7713b1edbc	170	*/
AnnaBridge	171:3a7713b1edbc	171	typedef struct
AnnaBridge	171:3a7713b1edbc	172	{
AnnaBridge	171:3a7713b1edbc	173	uint32_t VirtualChannelID; /!< Virtual channel ID /
AnnaBridge	171:3a7713b1edbc	174
AnnaBridge	171:3a7713b1edbc	175	uint32_t ColorCoding; /*!< Color coding for LTDC interface
AnnaBridge	171:3a7713b1edbc	176	This parameter can be any value of @ref DSI_Color_Coding */
AnnaBridge	171:3a7713b1edbc	177
AnnaBridge	171:3a7713b1edbc	178	uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
AnnaBridge	171:3a7713b1edbc	179	pixels. This parameter can be any value between 0x00 and 0xFFFF */
AnnaBridge	171:3a7713b1edbc	180
AnnaBridge	171:3a7713b1edbc	181	uint32_t TearingEffectSource; /*!< Tearing effect source
AnnaBridge	171:3a7713b1edbc	182	This parameter can be any value of @ref DSI_TearingEffectSource */
AnnaBridge	171:3a7713b1edbc	183
AnnaBridge	171:3a7713b1edbc	184	uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
AnnaBridge	171:3a7713b1edbc	185	This parameter can be any value of @ref DSI_TearingEffectPolarity */
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	uint32_t HSPolarity; /*!< HSYNC pin polarity
AnnaBridge	171:3a7713b1edbc	188	This parameter can be any value of @ref DSI_HSYNC_Polarity */
AnnaBridge	171:3a7713b1edbc	189
AnnaBridge	171:3a7713b1edbc	190	uint32_t VSPolarity; /*!< VSYNC pin polarity
AnnaBridge	171:3a7713b1edbc	191	This parameter can be any value of @ref DSI_VSYNC_Polarity */
AnnaBridge	171:3a7713b1edbc	192
AnnaBridge	171:3a7713b1edbc	193	uint32_t DEPolarity; /*!< Data Enable pin polarity
AnnaBridge	171:3a7713b1edbc	194	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
AnnaBridge	171:3a7713b1edbc	195
AnnaBridge	171:3a7713b1edbc	196	uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
AnnaBridge	171:3a7713b1edbc	197	This parameter can be any value of @ref DSI_Vsync_Polarity */
AnnaBridge	171:3a7713b1edbc	198
AnnaBridge	171:3a7713b1edbc	199	uint32_t AutomaticRefresh; /*!< Automatic refresh mode
AnnaBridge	171:3a7713b1edbc	200	This parameter can be any value of @ref DSI_AutomaticRefresh */
AnnaBridge	171:3a7713b1edbc	201
AnnaBridge	171:3a7713b1edbc	202	uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
AnnaBridge	171:3a7713b1edbc	203	This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
AnnaBridge	171:3a7713b1edbc	204
AnnaBridge	171:3a7713b1edbc	205	}DSI_CmdCfgTypeDef;
AnnaBridge	171:3a7713b1edbc	206
AnnaBridge	171:3a7713b1edbc	207	/**
AnnaBridge	171:3a7713b1edbc	208	* @brief DSI command transmission mode configuration
AnnaBridge	171:3a7713b1edbc	209	*/
AnnaBridge	171:3a7713b1edbc	210	typedef struct
AnnaBridge	171:3a7713b1edbc	211	{
AnnaBridge	171:3a7713b1edbc	212	uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
AnnaBridge	171:3a7713b1edbc	213	This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
AnnaBridge	171:3a7713b1edbc	214
AnnaBridge	171:3a7713b1edbc	215	uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
AnnaBridge	171:3a7713b1edbc	216	This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
AnnaBridge	171:3a7713b1edbc	217
AnnaBridge	171:3a7713b1edbc	218	uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
AnnaBridge	171:3a7713b1edbc	219	This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
AnnaBridge	171:3a7713b1edbc	220
AnnaBridge	171:3a7713b1edbc	221	uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
AnnaBridge	171:3a7713b1edbc	222	This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
AnnaBridge	171:3a7713b1edbc	223
AnnaBridge	171:3a7713b1edbc	224	uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
AnnaBridge	171:3a7713b1edbc	225	This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
AnnaBridge	171:3a7713b1edbc	226
AnnaBridge	171:3a7713b1edbc	227	uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
AnnaBridge	171:3a7713b1edbc	228	This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
AnnaBridge	171:3a7713b1edbc	229
AnnaBridge	171:3a7713b1edbc	230	uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
AnnaBridge	171:3a7713b1edbc	231	This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
AnnaBridge	171:3a7713b1edbc	232
AnnaBridge	171:3a7713b1edbc	233	uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
AnnaBridge	171:3a7713b1edbc	234	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
AnnaBridge	171:3a7713b1edbc	235
AnnaBridge	171:3a7713b1edbc	236	uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
AnnaBridge	171:3a7713b1edbc	237	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
AnnaBridge	171:3a7713b1edbc	238
AnnaBridge	171:3a7713b1edbc	239	uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
AnnaBridge	171:3a7713b1edbc	240	This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
AnnaBridge	171:3a7713b1edbc	241
AnnaBridge	171:3a7713b1edbc	242	uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
AnnaBridge	171:3a7713b1edbc	243	This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
AnnaBridge	171:3a7713b1edbc	244
AnnaBridge	171:3a7713b1edbc	245	uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
AnnaBridge	171:3a7713b1edbc	246	This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
AnnaBridge	171:3a7713b1edbc	247
AnnaBridge	171:3a7713b1edbc	248	uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
AnnaBridge	171:3a7713b1edbc	249	This parameter can be any value of @ref DSI_AcknowledgeRequest */
AnnaBridge	171:3a7713b1edbc	250
AnnaBridge	171:3a7713b1edbc	251	}DSI_LPCmdTypeDef;
AnnaBridge	171:3a7713b1edbc	252
AnnaBridge	171:3a7713b1edbc	253	/**
AnnaBridge	171:3a7713b1edbc	254	* @brief DSI PHY Timings definition
AnnaBridge	171:3a7713b1edbc	255	*/
AnnaBridge	171:3a7713b1edbc	256	typedef struct
AnnaBridge	171:3a7713b1edbc	257	{
AnnaBridge	171:3a7713b1edbc	258	uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
AnnaBridge	171:3a7713b1edbc	259	to low-power transmission */
AnnaBridge	171:3a7713b1edbc	260
AnnaBridge	171:3a7713b1edbc	261	uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
AnnaBridge	171:3a7713b1edbc	262	to high-speed transmission */
AnnaBridge	171:3a7713b1edbc	263
AnnaBridge	171:3a7713b1edbc	264	uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
AnnaBridge	171:3a7713b1edbc	265	to low-power transmission */
AnnaBridge	171:3a7713b1edbc	266
AnnaBridge	171:3a7713b1edbc	267	uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
AnnaBridge	171:3a7713b1edbc	268	to high-speed transmission */
AnnaBridge	171:3a7713b1edbc	269
AnnaBridge	171:3a7713b1edbc	270	uint32_t DataLaneMaxReadTime; /!< The maximum time required to perform a read command /
AnnaBridge	171:3a7713b1edbc	271
AnnaBridge	171:3a7713b1edbc	272	uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
AnnaBridge	171:3a7713b1edbc	273	Stop state */
AnnaBridge	171:3a7713b1edbc	274
AnnaBridge	171:3a7713b1edbc	275	}DSI_PHY_TimerTypeDef;
AnnaBridge	171:3a7713b1edbc	276
AnnaBridge	171:3a7713b1edbc	277	/**
AnnaBridge	171:3a7713b1edbc	278	* @brief DSI HOST Timeouts definition
AnnaBridge	171:3a7713b1edbc	279	*/
AnnaBridge	171:3a7713b1edbc	280	typedef struct
AnnaBridge	171:3a7713b1edbc	281	{
AnnaBridge	171:3a7713b1edbc	282	uint32_t TimeoutCkdiv; /!< Time-out clock division /
AnnaBridge	171:3a7713b1edbc	283
AnnaBridge	171:3a7713b1edbc	284	uint32_t HighSpeedTransmissionTimeout; /!< High-speed transmission time-out /
AnnaBridge	171:3a7713b1edbc	285
AnnaBridge	171:3a7713b1edbc	286	uint32_t LowPowerReceptionTimeout; /!< Low-power reception time-out /
AnnaBridge	171:3a7713b1edbc	287
AnnaBridge	171:3a7713b1edbc	288	uint32_t HighSpeedReadTimeout; /!< High-speed read time-out /
AnnaBridge	171:3a7713b1edbc	289
AnnaBridge	171:3a7713b1edbc	290	uint32_t LowPowerReadTimeout; /!< Low-power read time-out /
AnnaBridge	171:3a7713b1edbc	291
AnnaBridge	171:3a7713b1edbc	292	uint32_t HighSpeedWriteTimeout; /!< High-speed write time-out /
AnnaBridge	171:3a7713b1edbc	293
AnnaBridge	171:3a7713b1edbc	294	uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
AnnaBridge	171:3a7713b1edbc	295	This parameter can be any value of @ref DSI_HS_PrespMode */
AnnaBridge	171:3a7713b1edbc	296
AnnaBridge	171:3a7713b1edbc	297	uint32_t LowPowerWriteTimeout; /!< Low-speed write time-out /
AnnaBridge	171:3a7713b1edbc	298
AnnaBridge	171:3a7713b1edbc	299	uint32_t BTATimeout; /!< BTA time-out /
AnnaBridge	171:3a7713b1edbc	300
AnnaBridge	171:3a7713b1edbc	301	}DSI_HOST_TimeoutTypeDef;
AnnaBridge	171:3a7713b1edbc	302
AnnaBridge	171:3a7713b1edbc	303	/**
AnnaBridge	171:3a7713b1edbc	304	* @brief DSI States Structure definition
AnnaBridge	171:3a7713b1edbc	305	*/
AnnaBridge	171:3a7713b1edbc	306	typedef enum
AnnaBridge	171:3a7713b1edbc	307	{
AnnaBridge	171:3a7713b1edbc	308	HAL_DSI_STATE_RESET = 0x00U,
AnnaBridge	171:3a7713b1edbc	309	HAL_DSI_STATE_READY = 0x01U,
AnnaBridge	171:3a7713b1edbc	310	HAL_DSI_STATE_ERROR = 0x02U,
AnnaBridge	171:3a7713b1edbc	311	HAL_DSI_STATE_BUSY = 0x03U,
AnnaBridge	171:3a7713b1edbc	312	HAL_DSI_STATE_TIMEOUT = 0x04U
AnnaBridge	171:3a7713b1edbc	313	}HAL_DSI_StateTypeDef;
AnnaBridge	171:3a7713b1edbc	314
AnnaBridge	171:3a7713b1edbc	315	/**
AnnaBridge	171:3a7713b1edbc	316	* @brief DSI Handle Structure definition
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318	typedef struct
AnnaBridge	171:3a7713b1edbc	319	{
AnnaBridge	171:3a7713b1edbc	320	DSI_TypeDef Instance; /!< Register base address */
AnnaBridge	171:3a7713b1edbc	321	DSI_InitTypeDef Init; /!< DSI required parameters /
AnnaBridge	171:3a7713b1edbc	322	HAL_LockTypeDef Lock; /!< DSI peripheral status /
AnnaBridge	171:3a7713b1edbc	323	__IO HAL_DSI_StateTypeDef State; /!< DSI communication state /
AnnaBridge	171:3a7713b1edbc	324	__IO uint32_t ErrorCode; /!< DSI Error code /
AnnaBridge	171:3a7713b1edbc	325	uint32_t ErrorMsk; /!< DSI Error monitoring mask /
AnnaBridge	171:3a7713b1edbc	326	}DSI_HandleTypeDef;
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	329	/** @defgroup DSI_DCS_Command DSI DCS Command
AnnaBridge	171:3a7713b1edbc	330	* @{
AnnaBridge	171:3a7713b1edbc	331	*/
AnnaBridge	171:3a7713b1edbc	332	#define DSI_ENTER_IDLE_MODE 0x39U
AnnaBridge	171:3a7713b1edbc	333	#define DSI_ENTER_INVERT_MODE 0x21U
AnnaBridge	171:3a7713b1edbc	334	#define DSI_ENTER_NORMAL_MODE 0x13U
AnnaBridge	171:3a7713b1edbc	335	#define DSI_ENTER_PARTIAL_MODE 0x12U
AnnaBridge	171:3a7713b1edbc	336	#define DSI_ENTER_SLEEP_MODE 0x10U
AnnaBridge	171:3a7713b1edbc	337	#define DSI_EXIT_IDLE_MODE 0x38U
AnnaBridge	171:3a7713b1edbc	338	#define DSI_EXIT_INVERT_MODE 0x20U
AnnaBridge	171:3a7713b1edbc	339	#define DSI_EXIT_SLEEP_MODE 0x11U
AnnaBridge	171:3a7713b1edbc	340	#define DSI_GET_3D_CONTROL 0x3FU
AnnaBridge	171:3a7713b1edbc	341	#define DSI_GET_ADDRESS_MODE 0x0BU
AnnaBridge	171:3a7713b1edbc	342	#define DSI_GET_BLUE_CHANNEL 0x08U
AnnaBridge	171:3a7713b1edbc	343	#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
AnnaBridge	171:3a7713b1edbc	344	#define DSI_GET_DISPLAY_MODE 0x0DU
AnnaBridge	171:3a7713b1edbc	345	#define DSI_GET_GREEN_CHANNEL 0x07U
AnnaBridge	171:3a7713b1edbc	346	#define DSI_GET_PIXEL_FORMAT 0x0CU
AnnaBridge	171:3a7713b1edbc	347	#define DSI_GET_POWER_MODE 0x0AU
AnnaBridge	171:3a7713b1edbc	348	#define DSI_GET_RED_CHANNEL 0x06U
AnnaBridge	171:3a7713b1edbc	349	#define DSI_GET_SCANLINE 0x45U
AnnaBridge	171:3a7713b1edbc	350	#define DSI_GET_SIGNAL_MODE 0x0EU
AnnaBridge	171:3a7713b1edbc	351	#define DSI_NOP 0x00U
AnnaBridge	171:3a7713b1edbc	352	#define DSI_READ_DDB_CONTINUE 0xA8U
AnnaBridge	171:3a7713b1edbc	353	#define DSI_READ_DDB_START 0xA1U
AnnaBridge	171:3a7713b1edbc	354	#define DSI_READ_MEMORY_CONTINUE 0x3EU
AnnaBridge	171:3a7713b1edbc	355	#define DSI_READ_MEMORY_START 0x2EU
AnnaBridge	171:3a7713b1edbc	356	#define DSI_SET_3D_CONTROL 0x3DU
AnnaBridge	171:3a7713b1edbc	357	#define DSI_SET_ADDRESS_MODE 0x36U
AnnaBridge	171:3a7713b1edbc	358	#define DSI_SET_COLUMN_ADDRESS 0x2AU
AnnaBridge	171:3a7713b1edbc	359	#define DSI_SET_DISPLAY_OFF 0x28U
AnnaBridge	171:3a7713b1edbc	360	#define DSI_SET_DISPLAY_ON 0x29U
AnnaBridge	171:3a7713b1edbc	361	#define DSI_SET_GAMMA_CURVE 0x26U
AnnaBridge	171:3a7713b1edbc	362	#define DSI_SET_PAGE_ADDRESS 0x2BU
AnnaBridge	171:3a7713b1edbc	363	#define DSI_SET_PARTIAL_COLUMNS 0x31U
AnnaBridge	171:3a7713b1edbc	364	#define DSI_SET_PARTIAL_ROWS 0x30U
AnnaBridge	171:3a7713b1edbc	365	#define DSI_SET_PIXEL_FORMAT 0x3AU
AnnaBridge	171:3a7713b1edbc	366	#define DSI_SET_SCROLL_AREA 0x33U
AnnaBridge	171:3a7713b1edbc	367	#define DSI_SET_SCROLL_START 0x37U
AnnaBridge	171:3a7713b1edbc	368	#define DSI_SET_TEAR_OFF 0x34U
AnnaBridge	171:3a7713b1edbc	369	#define DSI_SET_TEAR_ON 0x35U
AnnaBridge	171:3a7713b1edbc	370	#define DSI_SET_TEAR_SCANLINE 0x44U
AnnaBridge	171:3a7713b1edbc	371	#define DSI_SET_VSYNC_TIMING 0x40U
AnnaBridge	171:3a7713b1edbc	372	#define DSI_SOFT_RESET 0x01U
AnnaBridge	171:3a7713b1edbc	373	#define DSI_WRITE_LUT 0x2DU
AnnaBridge	171:3a7713b1edbc	374	#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
AnnaBridge	171:3a7713b1edbc	375	#define DSI_WRITE_MEMORY_START 0x2CU
AnnaBridge	171:3a7713b1edbc	376	/**
AnnaBridge	171:3a7713b1edbc	377	* @}
AnnaBridge	171:3a7713b1edbc	378	*/
AnnaBridge	171:3a7713b1edbc	379
AnnaBridge	171:3a7713b1edbc	380	/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
AnnaBridge	171:3a7713b1edbc	381	* @{
AnnaBridge	171:3a7713b1edbc	382	*/
AnnaBridge	171:3a7713b1edbc	383	#define DSI_VID_MODE_NB_PULSES 0U
AnnaBridge	171:3a7713b1edbc	384	#define DSI_VID_MODE_NB_EVENTS 1U
AnnaBridge	171:3a7713b1edbc	385	#define DSI_VID_MODE_BURST 2U
AnnaBridge	171:3a7713b1edbc	386	/**
AnnaBridge	171:3a7713b1edbc	387	* @}
AnnaBridge	171:3a7713b1edbc	388	*/
AnnaBridge	171:3a7713b1edbc	389
AnnaBridge	171:3a7713b1edbc	390	/** @defgroup DSI_Color_Mode DSI Color Mode
AnnaBridge	171:3a7713b1edbc	391	* @{
AnnaBridge	171:3a7713b1edbc	392	*/
AnnaBridge	171:3a7713b1edbc	393	#define DSI_COLOR_MODE_FULL 0U
AnnaBridge	171:3a7713b1edbc	394	#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
AnnaBridge	171:3a7713b1edbc	395	/**
AnnaBridge	171:3a7713b1edbc	396	* @}
AnnaBridge	171:3a7713b1edbc	397	*/
AnnaBridge	171:3a7713b1edbc	398
AnnaBridge	171:3a7713b1edbc	399	/** @defgroup DSI_ShutDown DSI ShutDown
AnnaBridge	171:3a7713b1edbc	400	* @{
AnnaBridge	171:3a7713b1edbc	401	*/
AnnaBridge	171:3a7713b1edbc	402	#define DSI_DISPLAY_ON 0U
AnnaBridge	171:3a7713b1edbc	403	#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
AnnaBridge	171:3a7713b1edbc	404	/**
AnnaBridge	171:3a7713b1edbc	405	* @}
AnnaBridge	171:3a7713b1edbc	406	*/
AnnaBridge	171:3a7713b1edbc	407
AnnaBridge	171:3a7713b1edbc	408	/** @defgroup DSI_LP_Command DSI LP Command
AnnaBridge	171:3a7713b1edbc	409	* @{
AnnaBridge	171:3a7713b1edbc	410	*/
AnnaBridge	171:3a7713b1edbc	411	#define DSI_LP_COMMAND_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	412	#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
AnnaBridge	171:3a7713b1edbc	413	/**
AnnaBridge	171:3a7713b1edbc	414	* @}
AnnaBridge	171:3a7713b1edbc	415	*/
AnnaBridge	171:3a7713b1edbc	416
AnnaBridge	171:3a7713b1edbc	417	/** @defgroup DSI_LP_HFP DSI LP HFP
AnnaBridge	171:3a7713b1edbc	418	* @{
AnnaBridge	171:3a7713b1edbc	419	*/
AnnaBridge	171:3a7713b1edbc	420	#define DSI_LP_HFP_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	421	#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
AnnaBridge	171:3a7713b1edbc	422	/**
AnnaBridge	171:3a7713b1edbc	423	* @}
AnnaBridge	171:3a7713b1edbc	424	*/
AnnaBridge	171:3a7713b1edbc	425
AnnaBridge	171:3a7713b1edbc	426	/** @defgroup DSI_LP_HBP DSI LP HBP
AnnaBridge	171:3a7713b1edbc	427	* @{
AnnaBridge	171:3a7713b1edbc	428	*/
AnnaBridge	171:3a7713b1edbc	429	#define DSI_LP_HBP_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	430	#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
AnnaBridge	171:3a7713b1edbc	431	/**
AnnaBridge	171:3a7713b1edbc	432	* @}
AnnaBridge	171:3a7713b1edbc	433	*/
AnnaBridge	171:3a7713b1edbc	434
AnnaBridge	171:3a7713b1edbc	435	/** @defgroup DSI_LP_VACT DSI LP VACT
AnnaBridge	171:3a7713b1edbc	436	* @{
AnnaBridge	171:3a7713b1edbc	437	*/
AnnaBridge	171:3a7713b1edbc	438	#define DSI_LP_VACT_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	439	#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
AnnaBridge	171:3a7713b1edbc	440	/**
AnnaBridge	171:3a7713b1edbc	441	* @}
AnnaBridge	171:3a7713b1edbc	442	*/
AnnaBridge	171:3a7713b1edbc	443
AnnaBridge	171:3a7713b1edbc	444	/** @defgroup DSI_LP_VFP DSI LP VFP
AnnaBridge	171:3a7713b1edbc	445	* @{
AnnaBridge	171:3a7713b1edbc	446	*/
AnnaBridge	171:3a7713b1edbc	447	#define DSI_LP_VFP_DISABLE 0
AnnaBridge	171:3a7713b1edbc	448	#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
AnnaBridge	171:3a7713b1edbc	449	/**
AnnaBridge	171:3a7713b1edbc	450	* @}
AnnaBridge	171:3a7713b1edbc	451	*/
AnnaBridge	171:3a7713b1edbc	452
AnnaBridge	171:3a7713b1edbc	453	/** @defgroup DSI_LP_VBP DSI LP VBP
AnnaBridge	171:3a7713b1edbc	454	* @{
AnnaBridge	171:3a7713b1edbc	455	*/
AnnaBridge	171:3a7713b1edbc	456	#define DSI_LP_VBP_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	457	#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
AnnaBridge	171:3a7713b1edbc	458	/**
AnnaBridge	171:3a7713b1edbc	459	* @}
AnnaBridge	171:3a7713b1edbc	460	*/
AnnaBridge	171:3a7713b1edbc	461
AnnaBridge	171:3a7713b1edbc	462	/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
AnnaBridge	171:3a7713b1edbc	463	* @{
AnnaBridge	171:3a7713b1edbc	464	*/
AnnaBridge	171:3a7713b1edbc	465	#define DSI_LP_VSYNC_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	466	#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
AnnaBridge	171:3a7713b1edbc	467	/**
AnnaBridge	171:3a7713b1edbc	468	* @}
AnnaBridge	171:3a7713b1edbc	469	*/
AnnaBridge	171:3a7713b1edbc	470
AnnaBridge	171:3a7713b1edbc	471	/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
AnnaBridge	171:3a7713b1edbc	472	* @{
AnnaBridge	171:3a7713b1edbc	473	*/
AnnaBridge	171:3a7713b1edbc	474	#define DSI_FBTAA_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	475	#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
AnnaBridge	171:3a7713b1edbc	476	/**
AnnaBridge	171:3a7713b1edbc	477	* @}
AnnaBridge	171:3a7713b1edbc	478	*/
AnnaBridge	171:3a7713b1edbc	479
AnnaBridge	171:3a7713b1edbc	480	/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
AnnaBridge	171:3a7713b1edbc	481	* @{
AnnaBridge	171:3a7713b1edbc	482	*/
AnnaBridge	171:3a7713b1edbc	483	#define DSI_TE_DSILINK 0U
AnnaBridge	171:3a7713b1edbc	484	#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
AnnaBridge	171:3a7713b1edbc	485	/**
AnnaBridge	171:3a7713b1edbc	486	* @}
AnnaBridge	171:3a7713b1edbc	487	*/
AnnaBridge	171:3a7713b1edbc	488
AnnaBridge	171:3a7713b1edbc	489	/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
AnnaBridge	171:3a7713b1edbc	490	* @{
AnnaBridge	171:3a7713b1edbc	491	*/
AnnaBridge	171:3a7713b1edbc	492	#define DSI_TE_RISING_EDGE 0U
AnnaBridge	171:3a7713b1edbc	493	#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
AnnaBridge	171:3a7713b1edbc	494	/**
AnnaBridge	171:3a7713b1edbc	495	* @}
AnnaBridge	171:3a7713b1edbc	496	*/
AnnaBridge	171:3a7713b1edbc	497
AnnaBridge	171:3a7713b1edbc	498	/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
AnnaBridge	171:3a7713b1edbc	499	* @{
AnnaBridge	171:3a7713b1edbc	500	*/
AnnaBridge	171:3a7713b1edbc	501	#define DSI_VSYNC_FALLING 0U
AnnaBridge	171:3a7713b1edbc	502	#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
AnnaBridge	171:3a7713b1edbc	503	/**
AnnaBridge	171:3a7713b1edbc	504	* @}
AnnaBridge	171:3a7713b1edbc	505	*/
AnnaBridge	171:3a7713b1edbc	506
AnnaBridge	171:3a7713b1edbc	507	/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
AnnaBridge	171:3a7713b1edbc	508	* @{
AnnaBridge	171:3a7713b1edbc	509	*/
AnnaBridge	171:3a7713b1edbc	510	#define DSI_AR_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	511	#define DSI_AR_ENABLE DSI_WCFGR_AR
AnnaBridge	171:3a7713b1edbc	512	/**
AnnaBridge	171:3a7713b1edbc	513	* @}
AnnaBridge	171:3a7713b1edbc	514	*/
AnnaBridge	171:3a7713b1edbc	515
AnnaBridge	171:3a7713b1edbc	516	/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
AnnaBridge	171:3a7713b1edbc	517	* @{
AnnaBridge	171:3a7713b1edbc	518	*/
AnnaBridge	171:3a7713b1edbc	519	#define DSI_TE_ACKNOWLEDGE_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	520	#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
AnnaBridge	171:3a7713b1edbc	521	/**
AnnaBridge	171:3a7713b1edbc	522	* @}
AnnaBridge	171:3a7713b1edbc	523	*/
AnnaBridge	171:3a7713b1edbc	524
AnnaBridge	171:3a7713b1edbc	525	/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
AnnaBridge	171:3a7713b1edbc	526	* @{
AnnaBridge	171:3a7713b1edbc	527	*/
AnnaBridge	171:3a7713b1edbc	528	#define DSI_ACKNOWLEDGE_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	529	#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
AnnaBridge	171:3a7713b1edbc	530	/**
AnnaBridge	171:3a7713b1edbc	531	* @}
AnnaBridge	171:3a7713b1edbc	532	*/
AnnaBridge	171:3a7713b1edbc	533
AnnaBridge	171:3a7713b1edbc	534	/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
AnnaBridge	171:3a7713b1edbc	535	* @{
AnnaBridge	171:3a7713b1edbc	536	*/
AnnaBridge	171:3a7713b1edbc	537	#define DSI_LP_GSW0P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	538	#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
AnnaBridge	171:3a7713b1edbc	539	/**
AnnaBridge	171:3a7713b1edbc	540	* @}
AnnaBridge	171:3a7713b1edbc	541	*/
AnnaBridge	171:3a7713b1edbc	542
AnnaBridge	171:3a7713b1edbc	543	/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
AnnaBridge	171:3a7713b1edbc	544	* @{
AnnaBridge	171:3a7713b1edbc	545	*/
AnnaBridge	171:3a7713b1edbc	546	#define DSI_LP_GSW1P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	547	#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
AnnaBridge	171:3a7713b1edbc	548	/**
AnnaBridge	171:3a7713b1edbc	549	* @}
AnnaBridge	171:3a7713b1edbc	550	*/
AnnaBridge	171:3a7713b1edbc	551
AnnaBridge	171:3a7713b1edbc	552	/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
AnnaBridge	171:3a7713b1edbc	553	* @{
AnnaBridge	171:3a7713b1edbc	554	*/
AnnaBridge	171:3a7713b1edbc	555	#define DSI_LP_GSW2P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	556	#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
AnnaBridge	171:3a7713b1edbc	557	/**
AnnaBridge	171:3a7713b1edbc	558	* @}
AnnaBridge	171:3a7713b1edbc	559	*/
AnnaBridge	171:3a7713b1edbc	560
AnnaBridge	171:3a7713b1edbc	561	/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
AnnaBridge	171:3a7713b1edbc	562	* @{
AnnaBridge	171:3a7713b1edbc	563	*/
AnnaBridge	171:3a7713b1edbc	564	#define DSI_LP_GSR0P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	565	#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
AnnaBridge	171:3a7713b1edbc	566	/**
AnnaBridge	171:3a7713b1edbc	567	* @}
AnnaBridge	171:3a7713b1edbc	568	*/
AnnaBridge	171:3a7713b1edbc	569
AnnaBridge	171:3a7713b1edbc	570	/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
AnnaBridge	171:3a7713b1edbc	571	* @{
AnnaBridge	171:3a7713b1edbc	572	*/
AnnaBridge	171:3a7713b1edbc	573	#define DSI_LP_GSR1P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	574	#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
AnnaBridge	171:3a7713b1edbc	575	/**
AnnaBridge	171:3a7713b1edbc	576	* @}
AnnaBridge	171:3a7713b1edbc	577	*/
AnnaBridge	171:3a7713b1edbc	578
AnnaBridge	171:3a7713b1edbc	579	/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
AnnaBridge	171:3a7713b1edbc	580	* @{
AnnaBridge	171:3a7713b1edbc	581	*/
AnnaBridge	171:3a7713b1edbc	582	#define DSI_LP_GSR2P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	583	#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
AnnaBridge	171:3a7713b1edbc	584	/**
AnnaBridge	171:3a7713b1edbc	585	* @}
AnnaBridge	171:3a7713b1edbc	586	*/
AnnaBridge	171:3a7713b1edbc	587
AnnaBridge	171:3a7713b1edbc	588	/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
AnnaBridge	171:3a7713b1edbc	589	* @{
AnnaBridge	171:3a7713b1edbc	590	*/
AnnaBridge	171:3a7713b1edbc	591	#define DSI_LP_GLW_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	592	#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
AnnaBridge	171:3a7713b1edbc	593	/**
AnnaBridge	171:3a7713b1edbc	594	* @}
AnnaBridge	171:3a7713b1edbc	595	*/
AnnaBridge	171:3a7713b1edbc	596
AnnaBridge	171:3a7713b1edbc	597	/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
AnnaBridge	171:3a7713b1edbc	598	* @{
AnnaBridge	171:3a7713b1edbc	599	*/
AnnaBridge	171:3a7713b1edbc	600	#define DSI_LP_DSW0P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	601	#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
AnnaBridge	171:3a7713b1edbc	602	/**
AnnaBridge	171:3a7713b1edbc	603	* @}
AnnaBridge	171:3a7713b1edbc	604	*/
AnnaBridge	171:3a7713b1edbc	605
AnnaBridge	171:3a7713b1edbc	606	/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
AnnaBridge	171:3a7713b1edbc	607	* @{
AnnaBridge	171:3a7713b1edbc	608	*/
AnnaBridge	171:3a7713b1edbc	609	#define DSI_LP_DSW1P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	610	#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
AnnaBridge	171:3a7713b1edbc	611	/**
AnnaBridge	171:3a7713b1edbc	612	* @}
AnnaBridge	171:3a7713b1edbc	613	*/
AnnaBridge	171:3a7713b1edbc	614
AnnaBridge	171:3a7713b1edbc	615	/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
AnnaBridge	171:3a7713b1edbc	616	* @{
AnnaBridge	171:3a7713b1edbc	617	*/
AnnaBridge	171:3a7713b1edbc	618	#define DSI_LP_DSR0P_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	619	#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
AnnaBridge	171:3a7713b1edbc	620	/**
AnnaBridge	171:3a7713b1edbc	621	* @}
AnnaBridge	171:3a7713b1edbc	622	*/
AnnaBridge	171:3a7713b1edbc	623
AnnaBridge	171:3a7713b1edbc	624	/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
AnnaBridge	171:3a7713b1edbc	625	* @{
AnnaBridge	171:3a7713b1edbc	626	*/
AnnaBridge	171:3a7713b1edbc	627	#define DSI_LP_DLW_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	628	#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
AnnaBridge	171:3a7713b1edbc	629	/**
AnnaBridge	171:3a7713b1edbc	630	* @}
AnnaBridge	171:3a7713b1edbc	631	*/
AnnaBridge	171:3a7713b1edbc	632
AnnaBridge	171:3a7713b1edbc	633	/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
AnnaBridge	171:3a7713b1edbc	634	* @{
AnnaBridge	171:3a7713b1edbc	635	*/
AnnaBridge	171:3a7713b1edbc	636	#define DSI_LP_MRDP_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	637	#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
AnnaBridge	171:3a7713b1edbc	638	/**
AnnaBridge	171:3a7713b1edbc	639	* @}
AnnaBridge	171:3a7713b1edbc	640	*/
AnnaBridge	171:3a7713b1edbc	641
AnnaBridge	171:3a7713b1edbc	642	/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
AnnaBridge	171:3a7713b1edbc	643	* @{
AnnaBridge	171:3a7713b1edbc	644	*/
AnnaBridge	171:3a7713b1edbc	645	#define DSI_HS_PM_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	646	#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
AnnaBridge	171:3a7713b1edbc	647	/**
AnnaBridge	171:3a7713b1edbc	648	* @}
AnnaBridge	171:3a7713b1edbc	649	*/
AnnaBridge	171:3a7713b1edbc	650
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
AnnaBridge	171:3a7713b1edbc	653	* @{
AnnaBridge	171:3a7713b1edbc	654	*/
AnnaBridge	171:3a7713b1edbc	655	#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	656	#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
AnnaBridge	171:3a7713b1edbc	657	/**
AnnaBridge	171:3a7713b1edbc	658	* @}
AnnaBridge	171:3a7713b1edbc	659	*/
AnnaBridge	171:3a7713b1edbc	660
AnnaBridge	171:3a7713b1edbc	661	/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
AnnaBridge	171:3a7713b1edbc	662	* @{
AnnaBridge	171:3a7713b1edbc	663	*/
AnnaBridge	171:3a7713b1edbc	664	#define DSI_ONE_DATA_LANE 0U
AnnaBridge	171:3a7713b1edbc	665	#define DSI_TWO_DATA_LANES 1U
AnnaBridge	171:3a7713b1edbc	666	/**
AnnaBridge	171:3a7713b1edbc	667	* @}
AnnaBridge	171:3a7713b1edbc	668	*/
AnnaBridge	171:3a7713b1edbc	669
AnnaBridge	171:3a7713b1edbc	670	/** @defgroup DSI_FlowControl DSI Flow Control
AnnaBridge	171:3a7713b1edbc	671	* @{
AnnaBridge	171:3a7713b1edbc	672	*/
AnnaBridge	171:3a7713b1edbc	673	#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
AnnaBridge	171:3a7713b1edbc	674	#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
AnnaBridge	171:3a7713b1edbc	675	#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
AnnaBridge	171:3a7713b1edbc	676	#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
AnnaBridge	171:3a7713b1edbc	677	#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
AnnaBridge	171:3a7713b1edbc	678	#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX \| DSI_FLOW_CONTROL_ECC_RX \| \
AnnaBridge	171:3a7713b1edbc	679	DSI_FLOW_CONTROL_BTA \| DSI_FLOW_CONTROL_EOTP_RX \| \
AnnaBridge	171:3a7713b1edbc	680	DSI_FLOW_CONTROL_EOTP_TX)
AnnaBridge	171:3a7713b1edbc	681	/**
AnnaBridge	171:3a7713b1edbc	682	* @}
AnnaBridge	171:3a7713b1edbc	683	*/
AnnaBridge	171:3a7713b1edbc	684
AnnaBridge	171:3a7713b1edbc	685	/** @defgroup DSI_Color_Coding DSI Color Coding
AnnaBridge	171:3a7713b1edbc	686	* @{
AnnaBridge	171:3a7713b1edbc	687	*/
AnnaBridge	171:3a7713b1edbc	688	#define DSI_RGB565 ((uint32_t)0x00000000U) /!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration /
AnnaBridge	171:3a7713b1edbc	689	#define DSI_RGB666 ((uint32_t)0x00000003U) /!< The value 0x00000004 can also be used for the RGB666 color mode configuration /
AnnaBridge	171:3a7713b1edbc	690	#define DSI_RGB888 ((uint32_t)0x00000005U)
AnnaBridge	171:3a7713b1edbc	691	/**
AnnaBridge	171:3a7713b1edbc	692	* @}
AnnaBridge	171:3a7713b1edbc	693	*/
AnnaBridge	171:3a7713b1edbc	694
AnnaBridge	171:3a7713b1edbc	695	/** @defgroup DSI_LooselyPacked DSI Loosely Packed
AnnaBridge	171:3a7713b1edbc	696	* @{
AnnaBridge	171:3a7713b1edbc	697	*/
AnnaBridge	171:3a7713b1edbc	698	#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
AnnaBridge	171:3a7713b1edbc	699	#define DSI_LOOSELY_PACKED_DISABLE 0U
AnnaBridge	171:3a7713b1edbc	700	/**
AnnaBridge	171:3a7713b1edbc	701	* @}
AnnaBridge	171:3a7713b1edbc	702	*/
AnnaBridge	171:3a7713b1edbc	703
AnnaBridge	171:3a7713b1edbc	704	/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
AnnaBridge	171:3a7713b1edbc	705	* @{
AnnaBridge	171:3a7713b1edbc	706	*/
AnnaBridge	171:3a7713b1edbc	707	#define DSI_HSYNC_ACTIVE_HIGH 0U
AnnaBridge	171:3a7713b1edbc	708	#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
AnnaBridge	171:3a7713b1edbc	709	/**
AnnaBridge	171:3a7713b1edbc	710	* @}
AnnaBridge	171:3a7713b1edbc	711	*/
AnnaBridge	171:3a7713b1edbc	712
AnnaBridge	171:3a7713b1edbc	713	/** @defgroup DSI_VSYNC_Polarity DSI VSYNC Polarity
AnnaBridge	171:3a7713b1edbc	714	* @{
AnnaBridge	171:3a7713b1edbc	715	*/
AnnaBridge	171:3a7713b1edbc	716	#define DSI_VSYNC_ACTIVE_HIGH 0U
AnnaBridge	171:3a7713b1edbc	717	#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
AnnaBridge	171:3a7713b1edbc	718	/**
AnnaBridge	171:3a7713b1edbc	719	* @}
AnnaBridge	171:3a7713b1edbc	720	*/
AnnaBridge	171:3a7713b1edbc	721
AnnaBridge	171:3a7713b1edbc	722	/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
AnnaBridge	171:3a7713b1edbc	723	* @{
AnnaBridge	171:3a7713b1edbc	724	*/
AnnaBridge	171:3a7713b1edbc	725	#define DSI_DATA_ENABLE_ACTIVE_HIGH 0U
AnnaBridge	171:3a7713b1edbc	726	#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
AnnaBridge	171:3a7713b1edbc	727	/**
AnnaBridge	171:3a7713b1edbc	728	* @}
AnnaBridge	171:3a7713b1edbc	729	*/
AnnaBridge	171:3a7713b1edbc	730
AnnaBridge	171:3a7713b1edbc	731	/** @defgroup DSI_PLL_IDF DSI PLL IDF
AnnaBridge	171:3a7713b1edbc	732	* @{
AnnaBridge	171:3a7713b1edbc	733	*/
AnnaBridge	171:3a7713b1edbc	734	#define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	735	#define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	736	#define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003U)
AnnaBridge	171:3a7713b1edbc	737	#define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	738	#define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005U)
AnnaBridge	171:3a7713b1edbc	739	#define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006U)
AnnaBridge	171:3a7713b1edbc	740	#define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007U)
AnnaBridge	171:3a7713b1edbc	741	/**
AnnaBridge	171:3a7713b1edbc	742	* @}
AnnaBridge	171:3a7713b1edbc	743	*/
AnnaBridge	171:3a7713b1edbc	744
AnnaBridge	171:3a7713b1edbc	745	/** @defgroup DSI_PLL_ODF DSI PLL ODF
AnnaBridge	171:3a7713b1edbc	746	* @{
AnnaBridge	171:3a7713b1edbc	747	*/
AnnaBridge	171:3a7713b1edbc	748	#define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	749	#define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	750	#define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	751	#define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003U)
AnnaBridge	171:3a7713b1edbc	752	/**
AnnaBridge	171:3a7713b1edbc	753	* @}
AnnaBridge	171:3a7713b1edbc	754	*/
AnnaBridge	171:3a7713b1edbc	755
AnnaBridge	171:3a7713b1edbc	756	/** @defgroup DSI_Flags DSI Flags
AnnaBridge	171:3a7713b1edbc	757	* @{
AnnaBridge	171:3a7713b1edbc	758	*/
AnnaBridge	171:3a7713b1edbc	759	#define DSI_FLAG_TE DSI_WISR_TEIF
AnnaBridge	171:3a7713b1edbc	760	#define DSI_FLAG_ER DSI_WISR_ERIF
AnnaBridge	171:3a7713b1edbc	761	#define DSI_FLAG_BUSY DSI_WISR_BUSY
AnnaBridge	171:3a7713b1edbc	762	#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
AnnaBridge	171:3a7713b1edbc	763	#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
AnnaBridge	171:3a7713b1edbc	764	#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
AnnaBridge	171:3a7713b1edbc	765	#define DSI_FLAG_RRS DSI_WISR_RRS
AnnaBridge	171:3a7713b1edbc	766	#define DSI_FLAG_RR DSI_WISR_RRIF
AnnaBridge	171:3a7713b1edbc	767	/**
AnnaBridge	171:3a7713b1edbc	768	* @}
AnnaBridge	171:3a7713b1edbc	769	*/
AnnaBridge	171:3a7713b1edbc	770
AnnaBridge	171:3a7713b1edbc	771	/** @defgroup DSI_Interrupts DSI Interrupts
AnnaBridge	171:3a7713b1edbc	772	* @{
AnnaBridge	171:3a7713b1edbc	773	*/
AnnaBridge	171:3a7713b1edbc	774	#define DSI_IT_TE DSI_WIER_TEIE
AnnaBridge	171:3a7713b1edbc	775	#define DSI_IT_ER DSI_WIER_ERIE
AnnaBridge	171:3a7713b1edbc	776	#define DSI_IT_PLLL DSI_WIER_PLLLIE
AnnaBridge	171:3a7713b1edbc	777	#define DSI_IT_PLLU DSI_WIER_PLLUIE
AnnaBridge	171:3a7713b1edbc	778	#define DSI_IT_RR DSI_WIER_RRIE
AnnaBridge	171:3a7713b1edbc	779	/**
AnnaBridge	171:3a7713b1edbc	780	* @}
AnnaBridge	171:3a7713b1edbc	781	*/
AnnaBridge	171:3a7713b1edbc	782
AnnaBridge	171:3a7713b1edbc	783	/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
AnnaBridge	171:3a7713b1edbc	784	* @{
AnnaBridge	171:3a7713b1edbc	785	*/
AnnaBridge	171:3a7713b1edbc	786	#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005U) /!< DCS short write, no parameters /
AnnaBridge	171:3a7713b1edbc	787	#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015U) /!< DCS short write, one parameter /
AnnaBridge	171:3a7713b1edbc	788	#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003U) /!< Generic short write, no parameters /
AnnaBridge	171:3a7713b1edbc	789	#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013U) /!< Generic short write, one parameter /
AnnaBridge	171:3a7713b1edbc	790	#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023U) /!< Generic short write, two parameters /
AnnaBridge	171:3a7713b1edbc	791	/**
AnnaBridge	171:3a7713b1edbc	792	* @}
AnnaBridge	171:3a7713b1edbc	793	*/
AnnaBridge	171:3a7713b1edbc	794
AnnaBridge	171:3a7713b1edbc	795	/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
AnnaBridge	171:3a7713b1edbc	796	* @{
AnnaBridge	171:3a7713b1edbc	797	*/
AnnaBridge	171:3a7713b1edbc	798	#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039U) /!< DCS long write /
AnnaBridge	171:3a7713b1edbc	799	#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029U) /!< Generic long write /
AnnaBridge	171:3a7713b1edbc	800	/**
AnnaBridge	171:3a7713b1edbc	801	* @}
AnnaBridge	171:3a7713b1edbc	802	*/
AnnaBridge	171:3a7713b1edbc	803
AnnaBridge	171:3a7713b1edbc	804	/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
AnnaBridge	171:3a7713b1edbc	805	* @{
AnnaBridge	171:3a7713b1edbc	806	*/
AnnaBridge	171:3a7713b1edbc	807	#define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006U) /!< DCS short read /
AnnaBridge	171:3a7713b1edbc	808	#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004U) /!< Generic short read, no parameters /
AnnaBridge	171:3a7713b1edbc	809	#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014U) /!< Generic short read, one parameter /
AnnaBridge	171:3a7713b1edbc	810	#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024U) /!< Generic short read, two parameters /
AnnaBridge	171:3a7713b1edbc	811	/**
AnnaBridge	171:3a7713b1edbc	812	* @}
AnnaBridge	171:3a7713b1edbc	813	*/
AnnaBridge	171:3a7713b1edbc	814
AnnaBridge	171:3a7713b1edbc	815	/** @defgroup DSI_Error_Data_Type DSI Error Data Type
AnnaBridge	171:3a7713b1edbc	816	* @{
AnnaBridge	171:3a7713b1edbc	817	*/
AnnaBridge	171:3a7713b1edbc	818	#define HAL_DSI_ERROR_NONE 0
AnnaBridge	171:3a7713b1edbc	819	#define HAL_DSI_ERROR_ACK ((uint32_t)0x00000001U) /!< acknowledge errors /
AnnaBridge	171:3a7713b1edbc	820	#define HAL_DSI_ERROR_PHY ((uint32_t)0x00000002U) /!< PHY related errors /
AnnaBridge	171:3a7713b1edbc	821	#define HAL_DSI_ERROR_TX ((uint32_t)0x00000004U) /!< transmission error /
AnnaBridge	171:3a7713b1edbc	822	#define HAL_DSI_ERROR_RX ((uint32_t)0x00000008U) /!< reception error /
AnnaBridge	171:3a7713b1edbc	823	#define HAL_DSI_ERROR_ECC ((uint32_t)0x00000010U) /!< ECC errors /
AnnaBridge	171:3a7713b1edbc	824	#define HAL_DSI_ERROR_CRC ((uint32_t)0x00000020U) /!< CRC error /
AnnaBridge	171:3a7713b1edbc	825	#define HAL_DSI_ERROR_PSE ((uint32_t)0x00000040U) /!< Packet Size error /
AnnaBridge	171:3a7713b1edbc	826	#define HAL_DSI_ERROR_EOT ((uint32_t)0x00000080U) /!< End Of Transmission error /
AnnaBridge	171:3a7713b1edbc	827	#define HAL_DSI_ERROR_OVF ((uint32_t)0x00000100U) /!< FIFO overflow error /
AnnaBridge	171:3a7713b1edbc	828	#define HAL_DSI_ERROR_GEN ((uint32_t)0x00000200U) /!< Generic FIFO related errors /
AnnaBridge	171:3a7713b1edbc	829	/**
AnnaBridge	171:3a7713b1edbc	830	* @}
AnnaBridge	171:3a7713b1edbc	831	*/
AnnaBridge	171:3a7713b1edbc	832
AnnaBridge	171:3a7713b1edbc	833	/** @defgroup DSI_Lane_Group DSI Lane Group
AnnaBridge	171:3a7713b1edbc	834	* @{
AnnaBridge	171:3a7713b1edbc	835	*/
AnnaBridge	171:3a7713b1edbc	836	#define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	837	#define DSI_DATA_LANES ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	838	/**
AnnaBridge	171:3a7713b1edbc	839	* @}
AnnaBridge	171:3a7713b1edbc	840	*/
AnnaBridge	171:3a7713b1edbc	841
AnnaBridge	171:3a7713b1edbc	842	/** @defgroup DSI_Communication_Delay DSI Communication Delay
AnnaBridge	171:3a7713b1edbc	843	* @{
AnnaBridge	171:3a7713b1edbc	844	*/
AnnaBridge	171:3a7713b1edbc	845	#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	846	#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	847	#define DSI_HS_DELAY ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	848	/**
AnnaBridge	171:3a7713b1edbc	849	* @}
AnnaBridge	171:3a7713b1edbc	850	*/
AnnaBridge	171:3a7713b1edbc	851
AnnaBridge	171:3a7713b1edbc	852	/** @defgroup DSI_CustomLane DSI CustomLane
AnnaBridge	171:3a7713b1edbc	853	* @{
AnnaBridge	171:3a7713b1edbc	854	*/
AnnaBridge	171:3a7713b1edbc	855	#define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	856	#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	857	/**
AnnaBridge	171:3a7713b1edbc	858	* @}
AnnaBridge	171:3a7713b1edbc	859	*/
AnnaBridge	171:3a7713b1edbc	860
AnnaBridge	171:3a7713b1edbc	861	/** @defgroup DSI_Lane_Select DSI Lane Select
AnnaBridge	171:3a7713b1edbc	862	* @{
AnnaBridge	171:3a7713b1edbc	863	*/
AnnaBridge	171:3a7713b1edbc	864	#define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	865	#define DSI_DATA_LANE0 ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	866	#define DSI_DATA_LANE1 ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	867	/**
AnnaBridge	171:3a7713b1edbc	868	* @}
AnnaBridge	171:3a7713b1edbc	869	*/
AnnaBridge	171:3a7713b1edbc	870
AnnaBridge	171:3a7713b1edbc	871	/** @defgroup DSI_PHY_Timing DSI PHY Timing
AnnaBridge	171:3a7713b1edbc	872	* @{
AnnaBridge	171:3a7713b1edbc	873	*/
AnnaBridge	171:3a7713b1edbc	874	#define DSI_TCLK_POST ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	875	#define DSI_TLPX_CLK ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	876	#define DSI_THS_EXIT ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	877	#define DSI_TLPX_DATA ((uint32_t)0x00000003U)
AnnaBridge	171:3a7713b1edbc	878	#define DSI_THS_ZERO ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	879	#define DSI_THS_TRAIL ((uint32_t)0x00000005U)
AnnaBridge	171:3a7713b1edbc	880	#define DSI_THS_PREPARE ((uint32_t)0x00000006U)
AnnaBridge	171:3a7713b1edbc	881	#define DSI_TCLK_ZERO ((uint32_t)0x00000007U)
AnnaBridge	171:3a7713b1edbc	882	#define DSI_TCLK_PREPARE ((uint32_t)0x00000008U)
AnnaBridge	171:3a7713b1edbc	883	/**
AnnaBridge	171:3a7713b1edbc	884	* @}
AnnaBridge	171:3a7713b1edbc	885	*/
AnnaBridge	171:3a7713b1edbc	886
AnnaBridge	171:3a7713b1edbc	887	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	888	/**
AnnaBridge	171:3a7713b1edbc	889	* @brief Enables the DSI host.
AnnaBridge	171:3a7713b1edbc	890	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	891	* @retval None.
AnnaBridge	171:3a7713b1edbc	892	*/
AnnaBridge	171:3a7713b1edbc	893	#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= DSI_CR_EN)
AnnaBridge	171:3a7713b1edbc	894
AnnaBridge	171:3a7713b1edbc	895	/**
AnnaBridge	171:3a7713b1edbc	896	* @brief Disables the DSI host.
AnnaBridge	171:3a7713b1edbc	897	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	898	* @retval None.
AnnaBridge	171:3a7713b1edbc	899	*/
AnnaBridge	171:3a7713b1edbc	900	#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)
AnnaBridge	171:3a7713b1edbc	901
AnnaBridge	171:3a7713b1edbc	902	/**
AnnaBridge	171:3a7713b1edbc	903	* @brief Enables the DSI wrapper.
AnnaBridge	171:3a7713b1edbc	904	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	905	* @retval None.
AnnaBridge	171:3a7713b1edbc	906	*/
AnnaBridge	171:3a7713b1edbc	907	#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR \|= DSI_WCR_DSIEN)
AnnaBridge	171:3a7713b1edbc	908
AnnaBridge	171:3a7713b1edbc	909	/**
AnnaBridge	171:3a7713b1edbc	910	* @brief Disable the DSI wrapper.
AnnaBridge	171:3a7713b1edbc	911	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	912	* @retval None.
AnnaBridge	171:3a7713b1edbc	913	*/
AnnaBridge	171:3a7713b1edbc	914	#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)
AnnaBridge	171:3a7713b1edbc	915
AnnaBridge	171:3a7713b1edbc	916	/**
AnnaBridge	171:3a7713b1edbc	917	* @brief Enables the DSI PLL.
AnnaBridge	171:3a7713b1edbc	918	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	919	* @retval None.
AnnaBridge	171:3a7713b1edbc	920	*/
AnnaBridge	171:3a7713b1edbc	921	#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR \|= DSI_WRPCR_PLLEN)
AnnaBridge	171:3a7713b1edbc	922
AnnaBridge	171:3a7713b1edbc	923	/**
AnnaBridge	171:3a7713b1edbc	924	* @brief Disables the DSI PLL.
AnnaBridge	171:3a7713b1edbc	925	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	926	* @retval None.
AnnaBridge	171:3a7713b1edbc	927	*/
AnnaBridge	171:3a7713b1edbc	928	#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)
AnnaBridge	171:3a7713b1edbc	929
AnnaBridge	171:3a7713b1edbc	930	/**
AnnaBridge	171:3a7713b1edbc	931	* @brief Enables the DSI regulator.
AnnaBridge	171:3a7713b1edbc	932	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	933	* @retval None.
AnnaBridge	171:3a7713b1edbc	934	*/
AnnaBridge	171:3a7713b1edbc	935	#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR \|= DSI_WRPCR_REGEN)
AnnaBridge	171:3a7713b1edbc	936
AnnaBridge	171:3a7713b1edbc	937	/**
AnnaBridge	171:3a7713b1edbc	938	* @brief Disables the DSI regulator.
AnnaBridge	171:3a7713b1edbc	939	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	940	* @retval None.
AnnaBridge	171:3a7713b1edbc	941	*/
AnnaBridge	171:3a7713b1edbc	942	#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)
AnnaBridge	171:3a7713b1edbc	943
AnnaBridge	171:3a7713b1edbc	944	/**
AnnaBridge	171:3a7713b1edbc	945	* @brief Get the DSI pending flags.
AnnaBridge	171:3a7713b1edbc	946	* @param __HANDLE__ DSI handle.
AnnaBridge	171:3a7713b1edbc	947	* @param __FLAG__ Get the specified flag.
AnnaBridge	171:3a7713b1edbc	948	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	949	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
AnnaBridge	171:3a7713b1edbc	950	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
AnnaBridge	171:3a7713b1edbc	951	* @arg DSI_FLAG_BUSY : Busy Flag
AnnaBridge	171:3a7713b1edbc	952	* @arg DSI_FLAG_PLLLS: PLL Lock Status
AnnaBridge	171:3a7713b1edbc	953	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
AnnaBridge	171:3a7713b1edbc	954	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
AnnaBridge	171:3a7713b1edbc	955	* @arg DSI_FLAG_RRS : Regulator Ready Flag
AnnaBridge	171:3a7713b1edbc	956	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
AnnaBridge	171:3a7713b1edbc	957	* @retval The state of FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	958	*/
AnnaBridge	171:3a7713b1edbc	959	#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
AnnaBridge	171:3a7713b1edbc	960
AnnaBridge	171:3a7713b1edbc	961	/**
AnnaBridge	171:3a7713b1edbc	962	* @brief Clears the DSI pending flags.
AnnaBridge	171:3a7713b1edbc	963	* @param __HANDLE__ DSI handle.
AnnaBridge	171:3a7713b1edbc	964	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	171:3a7713b1edbc	965	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	966	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
AnnaBridge	171:3a7713b1edbc	967	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
AnnaBridge	171:3a7713b1edbc	968	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
AnnaBridge	171:3a7713b1edbc	969	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
AnnaBridge	171:3a7713b1edbc	970	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
AnnaBridge	171:3a7713b1edbc	971	* @retval None
AnnaBridge	171:3a7713b1edbc	972	*/
AnnaBridge	171:3a7713b1edbc	973	#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
AnnaBridge	171:3a7713b1edbc	974
AnnaBridge	171:3a7713b1edbc	975	/**
AnnaBridge	171:3a7713b1edbc	976	* @brief Enables the specified DSI interrupts.
AnnaBridge	171:3a7713b1edbc	977	* @param __HANDLE__ DSI handle.
AnnaBridge	171:3a7713b1edbc	978	* @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
AnnaBridge	171:3a7713b1edbc	979	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	980	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	171:3a7713b1edbc	981	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	171:3a7713b1edbc	982	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	171:3a7713b1edbc	983	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	171:3a7713b1edbc	984	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	171:3a7713b1edbc	985	* @retval None
AnnaBridge	171:3a7713b1edbc	986	*/
AnnaBridge	171:3a7713b1edbc	987	#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	988
AnnaBridge	171:3a7713b1edbc	989	/**
AnnaBridge	171:3a7713b1edbc	990	* @brief Disables the specified DSI interrupts.
AnnaBridge	171:3a7713b1edbc	991	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	992	* @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
AnnaBridge	171:3a7713b1edbc	993	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	994	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	171:3a7713b1edbc	995	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	171:3a7713b1edbc	996	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	171:3a7713b1edbc	997	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	171:3a7713b1edbc	998	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	171:3a7713b1edbc	999	* @retval None
AnnaBridge	171:3a7713b1edbc	1000	*/
AnnaBridge	171:3a7713b1edbc	1001	#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1002
AnnaBridge	171:3a7713b1edbc	1003	/**
AnnaBridge	171:3a7713b1edbc	1004	* @brief Checks whether the specified DSI interrupt has occurred or not.
AnnaBridge	171:3a7713b1edbc	1005	* @param __HANDLE__ DSI handle
AnnaBridge	171:3a7713b1edbc	1006	* @param __INTERRUPT__ specifies the DSI interrupt source to check.
AnnaBridge	171:3a7713b1edbc	1007	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1008	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	171:3a7713b1edbc	1009	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	171:3a7713b1edbc	1010	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	171:3a7713b1edbc	1011	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	171:3a7713b1edbc	1012	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	171:3a7713b1edbc	1013	* @retval The state of INTERRUPT (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1014	*/
AnnaBridge	171:3a7713b1edbc	1015	#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1016
AnnaBridge	171:3a7713b1edbc	1017	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1018	/** @defgroup DSI_Exported_Functions DSI Exported Functions
AnnaBridge	171:3a7713b1edbc	1019	* @{
AnnaBridge	171:3a7713b1edbc	1020	*/
AnnaBridge	171:3a7713b1edbc	1021	HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef hdsi, DSI_PLLInitTypeDef PLLInit);
AnnaBridge	171:3a7713b1edbc	1022	HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1023	void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1024	void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1025
AnnaBridge	171:3a7713b1edbc	1026	void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1027	void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1028	void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1029	void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1030
AnnaBridge	171:3a7713b1edbc	1031	HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
AnnaBridge	171:3a7713b1edbc	1032	HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef hdsi, DSI_VidCfgTypeDef VidCfg);
AnnaBridge	171:3a7713b1edbc	1033	HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef hdsi, DSI_CmdCfgTypeDef CmdCfg);
AnnaBridge	171:3a7713b1edbc	1034	HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef hdsi, DSI_LPCmdTypeDef LPCmd);
AnnaBridge	171:3a7713b1edbc	1035	HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
AnnaBridge	171:3a7713b1edbc	1036	HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef hdsi, DSI_PHY_TimerTypeDef PhyTimers);
AnnaBridge	171:3a7713b1edbc	1037	HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef hdsi, DSI_HOST_TimeoutTypeDef HostTimeouts);
AnnaBridge	171:3a7713b1edbc	1038	HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1039	HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1040	HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1041	HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
AnnaBridge	171:3a7713b1edbc	1042	HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
AnnaBridge	171:3a7713b1edbc	1043	HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
AnnaBridge	171:3a7713b1edbc	1044	uint32_t ChannelID,
AnnaBridge	171:3a7713b1edbc	1045	uint32_t Mode,
AnnaBridge	171:3a7713b1edbc	1046	uint32_t Param1,
AnnaBridge	171:3a7713b1edbc	1047	uint32_t Param2);
AnnaBridge	171:3a7713b1edbc	1048	HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
AnnaBridge	171:3a7713b1edbc	1049	uint32_t ChannelID,
AnnaBridge	171:3a7713b1edbc	1050	uint32_t Mode,
AnnaBridge	171:3a7713b1edbc	1051	uint32_t NbParams,
AnnaBridge	171:3a7713b1edbc	1052	uint32_t Param1,
AnnaBridge	171:3a7713b1edbc	1053	uint8_t* ParametersTable);
AnnaBridge	171:3a7713b1edbc	1054	HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
AnnaBridge	171:3a7713b1edbc	1055	uint32_t ChannelNbr,
AnnaBridge	171:3a7713b1edbc	1056	uint8_t* Array,
AnnaBridge	171:3a7713b1edbc	1057	uint32_t Size,
AnnaBridge	171:3a7713b1edbc	1058	uint32_t Mode,
AnnaBridge	171:3a7713b1edbc	1059	uint32_t DCSCmd,
AnnaBridge	171:3a7713b1edbc	1060	uint8_t* ParametersTable);
AnnaBridge	171:3a7713b1edbc	1061	HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1062	HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1063	HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1064	HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1065
AnnaBridge	171:3a7713b1edbc	1066	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
AnnaBridge	171:3a7713b1edbc	1067	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1068
AnnaBridge	171:3a7713b1edbc	1069	HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
AnnaBridge	171:3a7713b1edbc	1070	HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
AnnaBridge	171:3a7713b1edbc	1071	HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	171:3a7713b1edbc	1072	HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
AnnaBridge	171:3a7713b1edbc	1073	HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
AnnaBridge	171:3a7713b1edbc	1074	HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
AnnaBridge	171:3a7713b1edbc	1075	HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	171:3a7713b1edbc	1076	HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	171:3a7713b1edbc	1077	HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	171:3a7713b1edbc	1078	HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	171:3a7713b1edbc	1079
AnnaBridge	171:3a7713b1edbc	1080	uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1081	HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
AnnaBridge	171:3a7713b1edbc	1082	HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
AnnaBridge	171:3a7713b1edbc	1083	/**
AnnaBridge	171:3a7713b1edbc	1084	* @}
AnnaBridge	171:3a7713b1edbc	1085	*/
AnnaBridge	171:3a7713b1edbc	1086
AnnaBridge	171:3a7713b1edbc	1087	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1088	/** @defgroup DSI_Private_Types DSI Private Types
AnnaBridge	171:3a7713b1edbc	1089	* @{
AnnaBridge	171:3a7713b1edbc	1090	*/
AnnaBridge	171:3a7713b1edbc	1091
AnnaBridge	171:3a7713b1edbc	1092	/**
AnnaBridge	171:3a7713b1edbc	1093	* @}
AnnaBridge	171:3a7713b1edbc	1094	*/
AnnaBridge	171:3a7713b1edbc	1095
AnnaBridge	171:3a7713b1edbc	1096	/* Private defines -----------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1097	/** @defgroup DSI_Private_Defines DSI Private Defines
AnnaBridge	171:3a7713b1edbc	1098	* @{
AnnaBridge	171:3a7713b1edbc	1099	*/
AnnaBridge	171:3a7713b1edbc	1100
AnnaBridge	171:3a7713b1edbc	1101	/**
AnnaBridge	171:3a7713b1edbc	1102	* @}
AnnaBridge	171:3a7713b1edbc	1103	*/
AnnaBridge	171:3a7713b1edbc	1104
AnnaBridge	171:3a7713b1edbc	1105	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1106	/** @defgroup DSI_Private_Variables DSI Private Variables
AnnaBridge	171:3a7713b1edbc	1107	* @{
AnnaBridge	171:3a7713b1edbc	1108	*/
AnnaBridge	171:3a7713b1edbc	1109
AnnaBridge	171:3a7713b1edbc	1110	/**
AnnaBridge	171:3a7713b1edbc	1111	* @}
AnnaBridge	171:3a7713b1edbc	1112	*/
AnnaBridge	171:3a7713b1edbc	1113
AnnaBridge	171:3a7713b1edbc	1114	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1115	/** @defgroup DSI_Private_Constants DSI Private Constants
AnnaBridge	171:3a7713b1edbc	1116	* @{
AnnaBridge	171:3a7713b1edbc	1117	*/
AnnaBridge	171:3a7713b1edbc	1118	#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037) /!< Maximum return packet configuration /
AnnaBridge	171:3a7713b1edbc	1119	/**
AnnaBridge	171:3a7713b1edbc	1120	* @}
AnnaBridge	171:3a7713b1edbc	1121	*/
AnnaBridge	171:3a7713b1edbc	1122
AnnaBridge	171:3a7713b1edbc	1123	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1124	/** @defgroup DSI_Private_Macros DSI Private Macros
AnnaBridge	171:3a7713b1edbc	1125	* @{
AnnaBridge	171:3a7713b1edbc	1126	*/
AnnaBridge	171:3a7713b1edbc	1127	#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
AnnaBridge	171:3a7713b1edbc	1128	#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) \|\| \
AnnaBridge	171:3a7713b1edbc	1129	((IDF) == DSI_PLL_IN_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	1130	((IDF) == DSI_PLL_IN_DIV3) \|\| \
AnnaBridge	171:3a7713b1edbc	1131	((IDF) == DSI_PLL_IN_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	1132	((IDF) == DSI_PLL_IN_DIV5) \|\| \
AnnaBridge	171:3a7713b1edbc	1133	((IDF) == DSI_PLL_IN_DIV6) \|\| \
AnnaBridge	171:3a7713b1edbc	1134	((IDF) == DSI_PLL_IN_DIV7))
AnnaBridge	171:3a7713b1edbc	1135	#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) \|\| \
AnnaBridge	171:3a7713b1edbc	1136	((ODF) == DSI_PLL_OUT_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	1137	((ODF) == DSI_PLL_OUT_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	1138	((ODF) == DSI_PLL_OUT_DIV8))
AnnaBridge	171:3a7713b1edbc	1139	#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) \|\| ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
AnnaBridge	171:3a7713b1edbc	1140	#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) \|\| ((NumberOfLanes) == DSI_TWO_DATA_LANES))
AnnaBridge	171:3a7713b1edbc	1141	#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) \| DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
AnnaBridge	171:3a7713b1edbc	1142	#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5)
AnnaBridge	171:3a7713b1edbc	1143	#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) \|\| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
AnnaBridge	171:3a7713b1edbc	1144	#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) \|\| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
AnnaBridge	171:3a7713b1edbc	1145	#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) \|\| ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
AnnaBridge	171:3a7713b1edbc	1146	#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) \|\| ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
AnnaBridge	171:3a7713b1edbc	1147	#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) \|\| \
AnnaBridge	171:3a7713b1edbc	1148	((VideoModeType) == DSI_VID_MODE_NB_EVENTS) \|\| \
AnnaBridge	171:3a7713b1edbc	1149	((VideoModeType) == DSI_VID_MODE_BURST))
AnnaBridge	171:3a7713b1edbc	1150	#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) \|\| ((ColorMode) == DSI_COLOR_MODE_EIGHT))
AnnaBridge	171:3a7713b1edbc	1151	#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) \|\| ((ShutDown) == DSI_DISPLAY_OFF))
AnnaBridge	171:3a7713b1edbc	1152	#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) \|\| ((LPCommand) == DSI_LP_COMMAND_ENABLE))
AnnaBridge	171:3a7713b1edbc	1153	#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) \|\| ((LPHFP) == DSI_LP_HFP_ENABLE))
AnnaBridge	171:3a7713b1edbc	1154	#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) \|\| ((LPHBP) == DSI_LP_HBP_ENABLE))
AnnaBridge	171:3a7713b1edbc	1155	#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) \|\| ((LPVActive) == DSI_LP_VACT_ENABLE))
AnnaBridge	171:3a7713b1edbc	1156	#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) \|\| ((LPVFP) == DSI_LP_VFP_ENABLE))
AnnaBridge	171:3a7713b1edbc	1157	#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) \|\| ((LPVBP) == DSI_LP_VBP_ENABLE))
AnnaBridge	171:3a7713b1edbc	1158	#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) \|\| ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
AnnaBridge	171:3a7713b1edbc	1159	#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) \|\| ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
AnnaBridge	171:3a7713b1edbc	1160	#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) \|\| ((TESource) == DSI_TE_EXTERNAL))
AnnaBridge	171:3a7713b1edbc	1161	#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) \|\| ((TEPolarity) == DSI_TE_FALLING_EDGE))
AnnaBridge	171:3a7713b1edbc	1162	#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) \|\| ((AutomaticRefresh) == DSI_AR_ENABLE))
AnnaBridge	171:3a7713b1edbc	1163	#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) \|\| ((VSPolarity) == DSI_VSYNC_RISING))
AnnaBridge	171:3a7713b1edbc	1164	#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) \|\| ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
AnnaBridge	171:3a7713b1edbc	1165	#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) \|\| ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
AnnaBridge	171:3a7713b1edbc	1166	#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) \|\| ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1167	#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) \|\| ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1168	#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) \|\| ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1169	#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) \|\| ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1170	#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) \|\| ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1171	#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) \|\| ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1172	#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) \|\| ((LP_GLW) == DSI_LP_GLW_ENABLE))
AnnaBridge	171:3a7713b1edbc	1173	#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) \|\| ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1174	#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) \|\| ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1175	#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) \|\| ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
AnnaBridge	171:3a7713b1edbc	1176	#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) \|\| ((LP_DLW) == DSI_LP_DLW_ENABLE))
AnnaBridge	171:3a7713b1edbc	1177	#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) \|\| ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
AnnaBridge	171:3a7713b1edbc	1178	#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) \|\| \
AnnaBridge	171:3a7713b1edbc	1179	((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) \|\| \
AnnaBridge	171:3a7713b1edbc	1180	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) \|\| \
AnnaBridge	171:3a7713b1edbc	1181	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) \|\| \
AnnaBridge	171:3a7713b1edbc	1182	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
AnnaBridge	171:3a7713b1edbc	1183	#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) \|\| \
AnnaBridge	171:3a7713b1edbc	1184	((MODE) == DSI_GEN_LONG_PKT_WRITE))
AnnaBridge	171:3a7713b1edbc	1185	#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) \|\| \
AnnaBridge	171:3a7713b1edbc	1186	((MODE) == DSI_GEN_SHORT_PKT_READ_P0) \|\| \
AnnaBridge	171:3a7713b1edbc	1187	((MODE) == DSI_GEN_SHORT_PKT_READ_P1) \|\| \
AnnaBridge	171:3a7713b1edbc	1188	((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
AnnaBridge	171:3a7713b1edbc	1189	#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) \|\| ((CommDelay) == DSI_SLEW_RATE_LPTX) \|\| ((CommDelay) == DSI_HS_DELAY))
AnnaBridge	171:3a7713b1edbc	1190	#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANES))
AnnaBridge	171:3a7713b1edbc	1191	#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) \|\| ((CustomLane) == DSI_INVERT_HS_SIGNAL))
AnnaBridge	171:3a7713b1edbc	1192	#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANE0) \|\| ((Lane) == DSI_DATA_LANE1))
AnnaBridge	171:3a7713b1edbc	1193	#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) \|\| \
AnnaBridge	171:3a7713b1edbc	1194	((Timing) == DSI_TLPX_CLK ) \|\| \
AnnaBridge	171:3a7713b1edbc	1195	((Timing) == DSI_THS_EXIT ) \|\| \
AnnaBridge	171:3a7713b1edbc	1196	((Timing) == DSI_TLPX_DATA ) \|\| \
AnnaBridge	171:3a7713b1edbc	1197	((Timing) == DSI_THS_ZERO ) \|\| \
AnnaBridge	171:3a7713b1edbc	1198	((Timing) == DSI_THS_TRAIL ) \|\| \
AnnaBridge	171:3a7713b1edbc	1199	((Timing) == DSI_THS_PREPARE ) \|\| \
AnnaBridge	171:3a7713b1edbc	1200	((Timing) == DSI_TCLK_ZERO ) \|\| \
AnnaBridge	171:3a7713b1edbc	1201	((Timing) == DSI_TCLK_PREPARE))
AnnaBridge	171:3a7713b1edbc	1202
AnnaBridge	171:3a7713b1edbc	1203	/**
AnnaBridge	171:3a7713b1edbc	1204	* @}
AnnaBridge	171:3a7713b1edbc	1205	*/
AnnaBridge	171:3a7713b1edbc	1206
AnnaBridge	171:3a7713b1edbc	1207	/* Private functions prototypes ----------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1208	/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
AnnaBridge	171:3a7713b1edbc	1209	* @{
AnnaBridge	171:3a7713b1edbc	1210	*/
AnnaBridge	171:3a7713b1edbc	1211
AnnaBridge	171:3a7713b1edbc	1212	/**
AnnaBridge	171:3a7713b1edbc	1213	* @}
AnnaBridge	171:3a7713b1edbc	1214	*/
AnnaBridge	171:3a7713b1edbc	1215
AnnaBridge	171:3a7713b1edbc	1216	/* Private functions ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1217	/** @defgroup DSI_Private_Functions DSI Private Functions
AnnaBridge	171:3a7713b1edbc	1218	* @{
AnnaBridge	171:3a7713b1edbc	1219	*/
AnnaBridge	171:3a7713b1edbc	1220
AnnaBridge	171:3a7713b1edbc	1221	/**
AnnaBridge	171:3a7713b1edbc	1222	* @}
AnnaBridge	171:3a7713b1edbc	1223	*/
AnnaBridge	171:3a7713b1edbc	1224
AnnaBridge	171:3a7713b1edbc	1225	/**
AnnaBridge	171:3a7713b1edbc	1226	* @}
AnnaBridge	171:3a7713b1edbc	1227	*/
AnnaBridge	171:3a7713b1edbc	1228
AnnaBridge	171:3a7713b1edbc	1229	/**
AnnaBridge	171:3a7713b1edbc	1230	* @}
AnnaBridge	171:3a7713b1edbc	1231	*/
AnnaBridge	171:3a7713b1edbc	1232	#endif /STM32F769xx \| STM32F779xx /
AnnaBridge	171:3a7713b1edbc	1233
AnnaBridge	171:3a7713b1edbc	1234	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1235	}
AnnaBridge	171:3a7713b1edbc	1236	#endif
AnnaBridge	171:3a7713b1edbc	1237
AnnaBridge	171:3a7713b1edbc	1238	#endif /* __STM32F7xx_HAL_DSI_H */
AnnaBridge	171:3a7713b1edbc	1239
AnnaBridge	171:3a7713b1edbc	1240	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/