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TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f7xx_hal_dac.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_dac.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of DAC HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_DAC_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_DAC_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup DAC |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup DAC_Exported_Types DAC Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 58 | */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | |
| AnnaBridge | 171:3a7713b1edbc | 60 | /** |
| AnnaBridge | 171:3a7713b1edbc | 61 | * @brief HAL State structures definition |
| AnnaBridge | 171:3a7713b1edbc | 62 | */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | typedef enum |
| AnnaBridge | 171:3a7713b1edbc | 64 | { |
| AnnaBridge | 171:3a7713b1edbc | 65 | HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | }HAL_DAC_StateTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 71 | |
| AnnaBridge | 171:3a7713b1edbc | 72 | /** |
| AnnaBridge | 171:3a7713b1edbc | 73 | * @brief DAC handle Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 74 | */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 76 | { |
| AnnaBridge | 171:3a7713b1edbc | 77 | DAC_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | |
| AnnaBridge | 171:3a7713b1edbc | 81 | HAL_LockTypeDef Lock; /*!< DAC locking object */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | |
| AnnaBridge | 171:3a7713b1edbc | 83 | DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | |
| AnnaBridge | 171:3a7713b1edbc | 85 | DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | __IO uint32_t ErrorCode; /*!< DAC Error code */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | |
| AnnaBridge | 171:3a7713b1edbc | 89 | }DAC_HandleTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 90 | |
| AnnaBridge | 171:3a7713b1edbc | 91 | /** |
| AnnaBridge | 171:3a7713b1edbc | 92 | * @brief DAC Configuration regular Channel structure definition |
| AnnaBridge | 171:3a7713b1edbc | 93 | */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 95 | { |
| AnnaBridge | 171:3a7713b1edbc | 96 | uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. |
| AnnaBridge | 171:3a7713b1edbc | 97 | This parameter can be a value of @ref DAC_trigger_selection */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | |
| AnnaBridge | 171:3a7713b1edbc | 99 | uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 100 | This parameter can be a value of @ref DAC_output_buffer */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | }DAC_ChannelConfTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 102 | /** |
| AnnaBridge | 171:3a7713b1edbc | 103 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 104 | */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | |
| AnnaBridge | 171:3a7713b1edbc | 106 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 107 | /** @defgroup DAC_Exported_Constants DAC Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 108 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 109 | */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | |
| AnnaBridge | 171:3a7713b1edbc | 111 | /** @defgroup DAC_Error_Code DAC Error Code |
| AnnaBridge | 171:3a7713b1edbc | 112 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 113 | */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | /** |
| AnnaBridge | 171:3a7713b1edbc | 119 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 120 | */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | |
| AnnaBridge | 171:3a7713b1edbc | 122 | /** @defgroup DAC_trigger_selection DAC Trigger Selection |
| AnnaBridge | 171:3a7713b1edbc | 123 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 124 | */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register |
| AnnaBridge | 171:3a7713b1edbc | 127 | has been loaded, and not by external trigger */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | /** |
| AnnaBridge | 171:3a7713b1edbc | 138 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 139 | */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | |
| AnnaBridge | 171:3a7713b1edbc | 141 | /** @defgroup DAC_output_buffer DAC Output Buffer |
| AnnaBridge | 171:3a7713b1edbc | 142 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 143 | */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) |
| AnnaBridge | 171:3a7713b1edbc | 146 | /** |
| AnnaBridge | 171:3a7713b1edbc | 147 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 148 | */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | |
| AnnaBridge | 171:3a7713b1edbc | 150 | /** @defgroup DAC_Channel_selection DAC Channel Selection |
| AnnaBridge | 171:3a7713b1edbc | 151 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 152 | */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define DAC_CHANNEL_1 ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define DAC_CHANNEL_2 ((uint32_t)0x00000010U) |
| AnnaBridge | 171:3a7713b1edbc | 155 | /** |
| AnnaBridge | 171:3a7713b1edbc | 156 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 157 | */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | |
| AnnaBridge | 171:3a7713b1edbc | 159 | /** @defgroup DAC_data_alignment DAC Data Alignment |
| AnnaBridge | 171:3a7713b1edbc | 160 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 161 | */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define DAC_ALIGN_12B_R ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define DAC_ALIGN_12B_L ((uint32_t)0x00000004U) |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define DAC_ALIGN_8B_R ((uint32_t)0x00000008U) |
| AnnaBridge | 171:3a7713b1edbc | 165 | /** |
| AnnaBridge | 171:3a7713b1edbc | 166 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 167 | */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | |
| AnnaBridge | 171:3a7713b1edbc | 169 | /** @defgroup DAC_flags_definition DAC Flags Definition |
| AnnaBridge | 171:3a7713b1edbc | 170 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 171 | */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) |
| AnnaBridge | 171:3a7713b1edbc | 174 | /** |
| AnnaBridge | 171:3a7713b1edbc | 175 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 176 | */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | |
| AnnaBridge | 171:3a7713b1edbc | 178 | /** @defgroup DAC_IT_definition DAC IT Definition |
| AnnaBridge | 171:3a7713b1edbc | 179 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 180 | */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) |
| AnnaBridge | 171:3a7713b1edbc | 183 | /** |
| AnnaBridge | 171:3a7713b1edbc | 184 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 185 | */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | |
| AnnaBridge | 171:3a7713b1edbc | 187 | /** |
| AnnaBridge | 171:3a7713b1edbc | 188 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 189 | */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | |
| AnnaBridge | 171:3a7713b1edbc | 191 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 192 | /** @defgroup DAC_Exported_Macros DAC Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 193 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 194 | */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | |
| AnnaBridge | 171:3a7713b1edbc | 196 | /** @brief Reset DAC handle state |
| AnnaBridge | 171:3a7713b1edbc | 197 | * @param __HANDLE__ specifies the DAC handle. |
| AnnaBridge | 171:3a7713b1edbc | 198 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 199 | */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) |
| AnnaBridge | 171:3a7713b1edbc | 201 | |
| AnnaBridge | 171:3a7713b1edbc | 202 | /** @brief Enable the DAC channel |
| AnnaBridge | 171:3a7713b1edbc | 203 | * @param __HANDLE__ specifies the DAC handle. |
| AnnaBridge | 171:3a7713b1edbc | 204 | * @param __DAC_CHANNEL__ specifies the DAC channel |
| AnnaBridge | 171:3a7713b1edbc | 205 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 206 | */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \ |
| AnnaBridge | 171:3a7713b1edbc | 208 | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__))) |
| AnnaBridge | 171:3a7713b1edbc | 209 | |
| AnnaBridge | 171:3a7713b1edbc | 210 | /** @brief Disable the DAC channel |
| AnnaBridge | 171:3a7713b1edbc | 211 | * @param __HANDLE__ specifies the DAC handle |
| AnnaBridge | 171:3a7713b1edbc | 212 | * @param __DAC_CHANNEL__ specifies the DAC channel. |
| AnnaBridge | 171:3a7713b1edbc | 213 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 214 | */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \ |
| AnnaBridge | 171:3a7713b1edbc | 216 | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__))) |
| AnnaBridge | 171:3a7713b1edbc | 217 | |
| AnnaBridge | 171:3a7713b1edbc | 218 | |
| AnnaBridge | 171:3a7713b1edbc | 219 | /** @brief Enable the DAC interrupt |
| AnnaBridge | 171:3a7713b1edbc | 220 | * @param __HANDLE__ specifies the DAC handle |
| AnnaBridge | 171:3a7713b1edbc | 221 | * @param __INTERRUPT__ specifies the DAC interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 222 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 223 | */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 225 | |
| AnnaBridge | 171:3a7713b1edbc | 226 | /** @brief Disable the DAC interrupt |
| AnnaBridge | 171:3a7713b1edbc | 227 | * @param __HANDLE__ specifies the DAC handle |
| AnnaBridge | 171:3a7713b1edbc | 228 | * @param __INTERRUPT__ specifies the DAC interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 229 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 230 | */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 232 | |
| AnnaBridge | 171:3a7713b1edbc | 233 | /** @brief Checks if the specified DAC interrupt source is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 234 | * @param __HANDLE__ DAC handle |
| AnnaBridge | 171:3a7713b1edbc | 235 | * @param __INTERRUPT__ DAC interrupt source to check |
| AnnaBridge | 171:3a7713b1edbc | 236 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 237 | * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt |
| AnnaBridge | 171:3a7713b1edbc | 238 | * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt |
| AnnaBridge | 171:3a7713b1edbc | 239 | * @retval State of interruption (SET or RESET) |
| AnnaBridge | 171:3a7713b1edbc | 240 | */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 242 | |
| AnnaBridge | 171:3a7713b1edbc | 243 | /** @brief Get the selected DAC's flag status. |
| AnnaBridge | 171:3a7713b1edbc | 244 | * @param __HANDLE__ specifies the DAC handle. |
| AnnaBridge | 171:3a7713b1edbc | 245 | * @param __FLAG__ specifies the flag to clear. |
| AnnaBridge | 171:3a7713b1edbc | 246 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 247 | * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag |
| AnnaBridge | 171:3a7713b1edbc | 248 | * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag |
| AnnaBridge | 171:3a7713b1edbc | 249 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 250 | */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 252 | |
| AnnaBridge | 171:3a7713b1edbc | 253 | /** @brief Clear the DAC's flag. |
| AnnaBridge | 171:3a7713b1edbc | 254 | * @param __HANDLE__ specifies the DAC handle. |
| AnnaBridge | 171:3a7713b1edbc | 255 | * @param __FLAG__ specifies the flag to clear. |
| AnnaBridge | 171:3a7713b1edbc | 256 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 257 | * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag |
| AnnaBridge | 171:3a7713b1edbc | 258 | * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag |
| AnnaBridge | 171:3a7713b1edbc | 259 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 260 | */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 262 | /** |
| AnnaBridge | 171:3a7713b1edbc | 263 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 264 | */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | |
| AnnaBridge | 171:3a7713b1edbc | 266 | /* Include DAC HAL Extension module */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | #include "stm32f7xx_hal_dac_ex.h" |
| AnnaBridge | 171:3a7713b1edbc | 268 | |
| AnnaBridge | 171:3a7713b1edbc | 269 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 270 | /** @addtogroup DAC_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 271 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 272 | */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | |
| AnnaBridge | 171:3a7713b1edbc | 274 | /** @addtogroup DAC_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 275 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 276 | */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | /* Initialization/de-initialization functions *********************************/ |
| AnnaBridge | 171:3a7713b1edbc | 278 | HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 171:3a7713b1edbc | 279 | HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 171:3a7713b1edbc | 280 | void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 171:3a7713b1edbc | 281 | void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 171:3a7713b1edbc | 282 | /** |
| AnnaBridge | 171:3a7713b1edbc | 283 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 284 | */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | |
| AnnaBridge | 171:3a7713b1edbc | 286 | /** @addtogroup DAC_Exported_Functions_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 287 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 288 | */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | /* I/O operation functions ****************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 290 | HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 291 | HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 292 | HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); |
| AnnaBridge | 171:3a7713b1edbc | 293 | HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 294 | uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 295 | /** |
| AnnaBridge | 171:3a7713b1edbc | 296 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 297 | */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | |
| AnnaBridge | 171:3a7713b1edbc | 299 | /** @addtogroup DAC_Exported_Functions_Group3 |
| AnnaBridge | 171:3a7713b1edbc | 300 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 301 | */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 303 | HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 304 | HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); |
| AnnaBridge | 171:3a7713b1edbc | 305 | /** |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 307 | */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | |
| AnnaBridge | 171:3a7713b1edbc | 309 | /** @addtogroup DAC_Exported_Functions_Group4 |
| AnnaBridge | 171:3a7713b1edbc | 310 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 311 | */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | /* Peripheral State functions *************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 313 | HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 171:3a7713b1edbc | 314 | void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 171:3a7713b1edbc | 315 | uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 171:3a7713b1edbc | 316 | |
| AnnaBridge | 171:3a7713b1edbc | 317 | void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 171:3a7713b1edbc | 318 | void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 171:3a7713b1edbc | 319 | void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 171:3a7713b1edbc | 320 | void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 171:3a7713b1edbc | 321 | /** |
| AnnaBridge | 171:3a7713b1edbc | 322 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 323 | */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | |
| AnnaBridge | 171:3a7713b1edbc | 325 | /** |
| AnnaBridge | 171:3a7713b1edbc | 326 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 327 | */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 329 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 330 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 331 | /** @defgroup DAC_Private_Constants DAC Private Constants |
| AnnaBridge | 171:3a7713b1edbc | 332 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 333 | */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | |
| AnnaBridge | 171:3a7713b1edbc | 335 | /** |
| AnnaBridge | 171:3a7713b1edbc | 336 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 337 | */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | |
| AnnaBridge | 171:3a7713b1edbc | 339 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 340 | /** @defgroup DAC_Private_Macros DAC Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 342 | */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ |
| AnnaBridge | 171:3a7713b1edbc | 345 | ((ALIGN) == DAC_ALIGN_12B_L) || \ |
| AnnaBridge | 171:3a7713b1edbc | 346 | ((ALIGN) == DAC_ALIGN_8B_R)) |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 348 | ((CHANNEL) == DAC_CHANNEL_2)) |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 350 | ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 351 | |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 353 | ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ |
| AnnaBridge | 171:3a7713b1edbc | 354 | ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ |
| AnnaBridge | 171:3a7713b1edbc | 355 | ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ |
| AnnaBridge | 171:3a7713b1edbc | 356 | ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ |
| AnnaBridge | 171:3a7713b1edbc | 357 | ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ |
| AnnaBridge | 171:3a7713b1edbc | 358 | ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ |
| AnnaBridge | 171:3a7713b1edbc | 359 | ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ |
| AnnaBridge | 171:3a7713b1edbc | 360 | ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) |
| AnnaBridge | 171:3a7713b1edbc | 361 | |
| AnnaBridge | 171:3a7713b1edbc | 362 | /** @brief Set DHR12R1 alignment |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @param __ALIGNMENT__ specifies the DAC alignment |
| AnnaBridge | 171:3a7713b1edbc | 364 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 365 | */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__)) |
| AnnaBridge | 171:3a7713b1edbc | 367 | |
| AnnaBridge | 171:3a7713b1edbc | 368 | /** @brief Set DHR12R2 alignment |
| AnnaBridge | 171:3a7713b1edbc | 369 | * @param __ALIGNMENT__ specifies the DAC alignment |
| AnnaBridge | 171:3a7713b1edbc | 370 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 371 | */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) |
| AnnaBridge | 171:3a7713b1edbc | 373 | |
| AnnaBridge | 171:3a7713b1edbc | 374 | /** @brief Set DHR12RD alignment |
| AnnaBridge | 171:3a7713b1edbc | 375 | * @param __ALIGNMENT__ specifies the DAC alignment |
| AnnaBridge | 171:3a7713b1edbc | 376 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 377 | */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__)) |
| AnnaBridge | 171:3a7713b1edbc | 379 | |
| AnnaBridge | 171:3a7713b1edbc | 380 | /** |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 382 | */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | |
| AnnaBridge | 171:3a7713b1edbc | 384 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 385 | /** @defgroup DAC_Private_Functions DAC Private Functions |
| AnnaBridge | 171:3a7713b1edbc | 386 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 387 | */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | /** |
| AnnaBridge | 171:3a7713b1edbc | 389 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 390 | */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | |
| AnnaBridge | 171:3a7713b1edbc | 392 | /** |
| AnnaBridge | 171:3a7713b1edbc | 393 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 394 | */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | |
| AnnaBridge | 171:3a7713b1edbc | 396 | /** |
| AnnaBridge | 171:3a7713b1edbc | 397 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 398 | */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | |
| AnnaBridge | 171:3a7713b1edbc | 400 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 401 | } |
| AnnaBridge | 171:3a7713b1edbc | 402 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 403 | |
| AnnaBridge | 171:3a7713b1edbc | 404 | #endif /*__STM32F7xx_HAL_DAC_H */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | |
| AnnaBridge | 171:3a7713b1edbc | 406 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
