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TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f7xx_hal_cortex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f7xx_hal_cortex.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of CORTEX HAL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F7xx_HAL_CORTEX_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F7xx_HAL_CORTEX_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f7xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/** @addtogroup CORTEX
AnnaBridge	171:3a7713b1edbc	52	* @{
AnnaBridge	171:3a7713b1edbc	53	*/
AnnaBridge	171:3a7713b1edbc	54	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	55	/** @defgroup CORTEX_Exported_Types Cortex Exported Types
AnnaBridge	171:3a7713b1edbc	56	* @{
AnnaBridge	171:3a7713b1edbc	57	*/
AnnaBridge	171:3a7713b1edbc	58
AnnaBridge	171:3a7713b1edbc	59	#if (__MPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	60	/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
AnnaBridge	171:3a7713b1edbc	61	* @brief MPU Region initialization structure
AnnaBridge	171:3a7713b1edbc	62	* @{
AnnaBridge	171:3a7713b1edbc	63	*/
AnnaBridge	171:3a7713b1edbc	64	typedef struct
AnnaBridge	171:3a7713b1edbc	65	{
AnnaBridge	171:3a7713b1edbc	66	uint8_t Enable; /*!< Specifies the status of the region.
AnnaBridge	171:3a7713b1edbc	67	This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
AnnaBridge	171:3a7713b1edbc	68	uint8_t Number; /*!< Specifies the number of the region to protect.
AnnaBridge	171:3a7713b1edbc	69	This parameter can be a value of @ref CORTEX_MPU_Region_Number */
AnnaBridge	171:3a7713b1edbc	70	uint32_t BaseAddress; /!< Specifies the base address of the region to protect. /
AnnaBridge	171:3a7713b1edbc	71	uint8_t Size; /*!< Specifies the size of the region to protect.
AnnaBridge	171:3a7713b1edbc	72	This parameter can be a value of @ref CORTEX_MPU_Region_Size */
AnnaBridge	171:3a7713b1edbc	73	uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
AnnaBridge	171:3a7713b1edbc	74	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge	171:3a7713b1edbc	75	uint8_t TypeExtField; /*!< Specifies the TEX field level.
AnnaBridge	171:3a7713b1edbc	76	This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
AnnaBridge	171:3a7713b1edbc	77	uint8_t AccessPermission; /*!< Specifies the region access permission type.
AnnaBridge	171:3a7713b1edbc	78	This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
AnnaBridge	171:3a7713b1edbc	79	uint8_t DisableExec; /*!< Specifies the instruction access status.
AnnaBridge	171:3a7713b1edbc	80	This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
AnnaBridge	171:3a7713b1edbc	81	uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
AnnaBridge	171:3a7713b1edbc	82	This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
AnnaBridge	171:3a7713b1edbc	83	uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
AnnaBridge	171:3a7713b1edbc	84	This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
AnnaBridge	171:3a7713b1edbc	85	uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
AnnaBridge	171:3a7713b1edbc	86	This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
AnnaBridge	171:3a7713b1edbc	87	}MPU_Region_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	88	/**
AnnaBridge	171:3a7713b1edbc	89	* @}
AnnaBridge	171:3a7713b1edbc	90	*/
AnnaBridge	171:3a7713b1edbc	91	#endif /* __MPU_PRESENT */
AnnaBridge	171:3a7713b1edbc	92
AnnaBridge	171:3a7713b1edbc	93	/**
AnnaBridge	171:3a7713b1edbc	94	* @}
AnnaBridge	171:3a7713b1edbc	95	*/
AnnaBridge	171:3a7713b1edbc	96
AnnaBridge	171:3a7713b1edbc	97	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	98
AnnaBridge	171:3a7713b1edbc	99	/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
AnnaBridge	171:3a7713b1edbc	100	* @{
AnnaBridge	171:3a7713b1edbc	101	*/
AnnaBridge	171:3a7713b1edbc	102
AnnaBridge	171:3a7713b1edbc	103	/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
AnnaBridge	171:3a7713b1edbc	104	* @{
AnnaBridge	171:3a7713b1edbc	105	*/
AnnaBridge	171:3a7713b1edbc	106	#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
AnnaBridge	171:3a7713b1edbc	107	4 bits for subpriority */
AnnaBridge	171:3a7713b1edbc	108	#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
AnnaBridge	171:3a7713b1edbc	109	3 bits for subpriority */
AnnaBridge	171:3a7713b1edbc	110	#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
AnnaBridge	171:3a7713b1edbc	111	2 bits for subpriority */
AnnaBridge	171:3a7713b1edbc	112	#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
AnnaBridge	171:3a7713b1edbc	113	1 bits for subpriority */
AnnaBridge	171:3a7713b1edbc	114	#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
AnnaBridge	171:3a7713b1edbc	115	0 bits for subpriority */
AnnaBridge	171:3a7713b1edbc	116	/**
AnnaBridge	171:3a7713b1edbc	117	* @}
AnnaBridge	171:3a7713b1edbc	118	*/
AnnaBridge	171:3a7713b1edbc	119
AnnaBridge	171:3a7713b1edbc	120	/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
AnnaBridge	171:3a7713b1edbc	121	* @{
AnnaBridge	171:3a7713b1edbc	122	*/
AnnaBridge	171:3a7713b1edbc	123	#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	124	#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	125
AnnaBridge	171:3a7713b1edbc	126	/**
AnnaBridge	171:3a7713b1edbc	127	* @}
AnnaBridge	171:3a7713b1edbc	128	*/
AnnaBridge	171:3a7713b1edbc	129
AnnaBridge	171:3a7713b1edbc	130	#if (__MPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	131	/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
AnnaBridge	171:3a7713b1edbc	132	* @{
AnnaBridge	171:3a7713b1edbc	133	*/
AnnaBridge	171:3a7713b1edbc	134	#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	135	#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	136	#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	137	#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
AnnaBridge	171:3a7713b1edbc	138	/**
AnnaBridge	171:3a7713b1edbc	139	* @}
AnnaBridge	171:3a7713b1edbc	140	*/
AnnaBridge	171:3a7713b1edbc	141
AnnaBridge	171:3a7713b1edbc	142	/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
AnnaBridge	171:3a7713b1edbc	143	* @{
AnnaBridge	171:3a7713b1edbc	144	*/
AnnaBridge	171:3a7713b1edbc	145	#define MPU_REGION_ENABLE ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	146	#define MPU_REGION_DISABLE ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	147	/**
AnnaBridge	171:3a7713b1edbc	148	* @}
AnnaBridge	171:3a7713b1edbc	149	*/
AnnaBridge	171:3a7713b1edbc	150
AnnaBridge	171:3a7713b1edbc	151	/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
AnnaBridge	171:3a7713b1edbc	152	* @{
AnnaBridge	171:3a7713b1edbc	153	*/
AnnaBridge	171:3a7713b1edbc	154	#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	155	#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	156	/**
AnnaBridge	171:3a7713b1edbc	157	* @}
AnnaBridge	171:3a7713b1edbc	158	*/
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
AnnaBridge	171:3a7713b1edbc	161	* @{
AnnaBridge	171:3a7713b1edbc	162	*/
AnnaBridge	171:3a7713b1edbc	163	#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	164	#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	165	/**
AnnaBridge	171:3a7713b1edbc	166	* @}
AnnaBridge	171:3a7713b1edbc	167	*/
AnnaBridge	171:3a7713b1edbc	168
AnnaBridge	171:3a7713b1edbc	169	/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
AnnaBridge	171:3a7713b1edbc	170	* @{
AnnaBridge	171:3a7713b1edbc	171	*/
AnnaBridge	171:3a7713b1edbc	172	#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	173	#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	174	/**
AnnaBridge	171:3a7713b1edbc	175	* @}
AnnaBridge	171:3a7713b1edbc	176	*/
AnnaBridge	171:3a7713b1edbc	177
AnnaBridge	171:3a7713b1edbc	178	/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
AnnaBridge	171:3a7713b1edbc	179	* @{
AnnaBridge	171:3a7713b1edbc	180	*/
AnnaBridge	171:3a7713b1edbc	181	#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	182	#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	183	/**
AnnaBridge	171:3a7713b1edbc	184	* @}
AnnaBridge	171:3a7713b1edbc	185	*/
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
AnnaBridge	171:3a7713b1edbc	188	* @{
AnnaBridge	171:3a7713b1edbc	189	*/
AnnaBridge	171:3a7713b1edbc	190	#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	191	#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	192	#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
AnnaBridge	171:3a7713b1edbc	193	/**
AnnaBridge	171:3a7713b1edbc	194	* @}
AnnaBridge	171:3a7713b1edbc	195	*/
AnnaBridge	171:3a7713b1edbc	196
AnnaBridge	171:3a7713b1edbc	197	/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
AnnaBridge	171:3a7713b1edbc	198	* @{
AnnaBridge	171:3a7713b1edbc	199	*/
AnnaBridge	171:3a7713b1edbc	200	#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
AnnaBridge	171:3a7713b1edbc	201	#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
AnnaBridge	171:3a7713b1edbc	202	#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
AnnaBridge	171:3a7713b1edbc	203	#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
AnnaBridge	171:3a7713b1edbc	204	#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
AnnaBridge	171:3a7713b1edbc	205	#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
AnnaBridge	171:3a7713b1edbc	206	#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
AnnaBridge	171:3a7713b1edbc	207	#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
AnnaBridge	171:3a7713b1edbc	208	#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
AnnaBridge	171:3a7713b1edbc	209	#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
AnnaBridge	171:3a7713b1edbc	210	#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
AnnaBridge	171:3a7713b1edbc	211	#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
AnnaBridge	171:3a7713b1edbc	212	#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
AnnaBridge	171:3a7713b1edbc	213	#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
AnnaBridge	171:3a7713b1edbc	214	#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
AnnaBridge	171:3a7713b1edbc	215	#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
AnnaBridge	171:3a7713b1edbc	216	#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
AnnaBridge	171:3a7713b1edbc	217	#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
AnnaBridge	171:3a7713b1edbc	218	#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
AnnaBridge	171:3a7713b1edbc	219	#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
AnnaBridge	171:3a7713b1edbc	220	#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
AnnaBridge	171:3a7713b1edbc	221	#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
AnnaBridge	171:3a7713b1edbc	222	#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
AnnaBridge	171:3a7713b1edbc	223	#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
AnnaBridge	171:3a7713b1edbc	224	#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
AnnaBridge	171:3a7713b1edbc	225	#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
AnnaBridge	171:3a7713b1edbc	226	#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
AnnaBridge	171:3a7713b1edbc	227	#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
AnnaBridge	171:3a7713b1edbc	228	/**
AnnaBridge	171:3a7713b1edbc	229	* @}
AnnaBridge	171:3a7713b1edbc	230	*/
AnnaBridge	171:3a7713b1edbc	231
AnnaBridge	171:3a7713b1edbc	232	/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
AnnaBridge	171:3a7713b1edbc	233	* @{
AnnaBridge	171:3a7713b1edbc	234	*/
AnnaBridge	171:3a7713b1edbc	235	#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	236	#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	237	#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
AnnaBridge	171:3a7713b1edbc	238	#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
AnnaBridge	171:3a7713b1edbc	239	#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
AnnaBridge	171:3a7713b1edbc	240	#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
AnnaBridge	171:3a7713b1edbc	241	/**
AnnaBridge	171:3a7713b1edbc	242	* @}
AnnaBridge	171:3a7713b1edbc	243	*/
AnnaBridge	171:3a7713b1edbc	244
AnnaBridge	171:3a7713b1edbc	245	/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
AnnaBridge	171:3a7713b1edbc	246	* @{
AnnaBridge	171:3a7713b1edbc	247	*/
AnnaBridge	171:3a7713b1edbc	248	#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	249	#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	250	#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
AnnaBridge	171:3a7713b1edbc	251	#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
AnnaBridge	171:3a7713b1edbc	252	#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
AnnaBridge	171:3a7713b1edbc	253	#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
AnnaBridge	171:3a7713b1edbc	254	#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
AnnaBridge	171:3a7713b1edbc	255	#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
AnnaBridge	171:3a7713b1edbc	256	/**
AnnaBridge	171:3a7713b1edbc	257	* @}
AnnaBridge	171:3a7713b1edbc	258	*/
AnnaBridge	171:3a7713b1edbc	259	#endif /* __MPU_PRESENT */
AnnaBridge	171:3a7713b1edbc	260
AnnaBridge	171:3a7713b1edbc	261	/**
AnnaBridge	171:3a7713b1edbc	262	* @}
AnnaBridge	171:3a7713b1edbc	263	*/
AnnaBridge	171:3a7713b1edbc	264
AnnaBridge	171:3a7713b1edbc	265
AnnaBridge	171:3a7713b1edbc	266	/* Exported Macros -----------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	267
AnnaBridge	171:3a7713b1edbc	268	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	269	/** @addtogroup CORTEX_Exported_Functions
AnnaBridge	171:3a7713b1edbc	270	* @{
AnnaBridge	171:3a7713b1edbc	271	*/
AnnaBridge	171:3a7713b1edbc	272
AnnaBridge	171:3a7713b1edbc	273	/** @addtogroup CORTEX_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	274	* @{
AnnaBridge	171:3a7713b1edbc	275	*/
AnnaBridge	171:3a7713b1edbc	276	/* Initialization and de-initialization functions *****************************/
AnnaBridge	171:3a7713b1edbc	277	void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
AnnaBridge	171:3a7713b1edbc	278	void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
AnnaBridge	171:3a7713b1edbc	279	void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
AnnaBridge	171:3a7713b1edbc	280	void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
AnnaBridge	171:3a7713b1edbc	281	void HAL_NVIC_SystemReset(void);
AnnaBridge	171:3a7713b1edbc	282	uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
AnnaBridge	171:3a7713b1edbc	283	/**
AnnaBridge	171:3a7713b1edbc	284	* @}
AnnaBridge	171:3a7713b1edbc	285	*/
AnnaBridge	171:3a7713b1edbc	286
AnnaBridge	171:3a7713b1edbc	287	/** @addtogroup CORTEX_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	288	* @{
AnnaBridge	171:3a7713b1edbc	289	*/
AnnaBridge	171:3a7713b1edbc	290	/* Peripheral Control functions ***********************************************/
AnnaBridge	171:3a7713b1edbc	291	#if (__MPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	292	void HAL_MPU_Enable(uint32_t MPU_Control);
AnnaBridge	171:3a7713b1edbc	293	void HAL_MPU_Disable(void);
AnnaBridge	171:3a7713b1edbc	294	void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
AnnaBridge	171:3a7713b1edbc	295	#endif /* __MPU_PRESENT */
AnnaBridge	171:3a7713b1edbc	296	uint32_t HAL_NVIC_GetPriorityGrouping(void);
AnnaBridge	171:3a7713b1edbc	297	void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
AnnaBridge	171:3a7713b1edbc	298	uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
AnnaBridge	171:3a7713b1edbc	299	void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
AnnaBridge	171:3a7713b1edbc	300	void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
AnnaBridge	171:3a7713b1edbc	301	uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
AnnaBridge	171:3a7713b1edbc	302	void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
AnnaBridge	171:3a7713b1edbc	303	void HAL_SYSTICK_IRQHandler(void);
AnnaBridge	171:3a7713b1edbc	304	void HAL_SYSTICK_Callback(void);
AnnaBridge	171:3a7713b1edbc	305	/**
AnnaBridge	171:3a7713b1edbc	306	* @}
AnnaBridge	171:3a7713b1edbc	307	*/
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309	/**
AnnaBridge	171:3a7713b1edbc	310	* @}
AnnaBridge	171:3a7713b1edbc	311	*/
AnnaBridge	171:3a7713b1edbc	312
AnnaBridge	171:3a7713b1edbc	313	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	314	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	315	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	316	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	317	/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
AnnaBridge	171:3a7713b1edbc	318	* @{
AnnaBridge	171:3a7713b1edbc	319	*/
AnnaBridge	171:3a7713b1edbc	320	#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) \|\| \
AnnaBridge	171:3a7713b1edbc	321	((GROUP) == NVIC_PRIORITYGROUP_1) \|\| \
AnnaBridge	171:3a7713b1edbc	322	((GROUP) == NVIC_PRIORITYGROUP_2) \|\| \
AnnaBridge	171:3a7713b1edbc	323	((GROUP) == NVIC_PRIORITYGROUP_3) \|\| \
AnnaBridge	171:3a7713b1edbc	324	((GROUP) == NVIC_PRIORITYGROUP_4))
AnnaBridge	171:3a7713b1edbc	325
AnnaBridge	171:3a7713b1edbc	326	#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
AnnaBridge	171:3a7713b1edbc	329
AnnaBridge	171:3a7713b1edbc	330	#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
AnnaBridge	171:3a7713b1edbc	331
AnnaBridge	171:3a7713b1edbc	332	#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) \|\| \
AnnaBridge	171:3a7713b1edbc	333	((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
AnnaBridge	171:3a7713b1edbc	334
AnnaBridge	171:3a7713b1edbc	335	#if (__MPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	336	#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	337	((STATE) == MPU_REGION_DISABLE))
AnnaBridge	171:3a7713b1edbc	338
AnnaBridge	171:3a7713b1edbc	339	#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	340	((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
AnnaBridge	171:3a7713b1edbc	341
AnnaBridge	171:3a7713b1edbc	342	#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	343	((STATE) == MPU_ACCESS_NOT_SHAREABLE))
AnnaBridge	171:3a7713b1edbc	344
AnnaBridge	171:3a7713b1edbc	345	#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	346	((STATE) == MPU_ACCESS_NOT_CACHEABLE))
AnnaBridge	171:3a7713b1edbc	347
AnnaBridge	171:3a7713b1edbc	348	#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	349	((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
AnnaBridge	171:3a7713b1edbc	350
AnnaBridge	171:3a7713b1edbc	351	#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) \|\| \
AnnaBridge	171:3a7713b1edbc	352	((TYPE) == MPU_TEX_LEVEL1) \|\| \
AnnaBridge	171:3a7713b1edbc	353	((TYPE) == MPU_TEX_LEVEL2))
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) \|\| \
AnnaBridge	171:3a7713b1edbc	356	((TYPE) == MPU_REGION_PRIV_RW) \|\| \
AnnaBridge	171:3a7713b1edbc	357	((TYPE) == MPU_REGION_PRIV_RW_URO) \|\| \
AnnaBridge	171:3a7713b1edbc	358	((TYPE) == MPU_REGION_FULL_ACCESS) \|\| \
AnnaBridge	171:3a7713b1edbc	359	((TYPE) == MPU_REGION_PRIV_RO) \|\| \
AnnaBridge	171:3a7713b1edbc	360	((TYPE) == MPU_REGION_PRIV_RO_URO))
AnnaBridge	171:3a7713b1edbc	361
AnnaBridge	171:3a7713b1edbc	362	#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) \|\| \
AnnaBridge	171:3a7713b1edbc	363	((NUMBER) == MPU_REGION_NUMBER1) \|\| \
AnnaBridge	171:3a7713b1edbc	364	((NUMBER) == MPU_REGION_NUMBER2) \|\| \
AnnaBridge	171:3a7713b1edbc	365	((NUMBER) == MPU_REGION_NUMBER3) \|\| \
AnnaBridge	171:3a7713b1edbc	366	((NUMBER) == MPU_REGION_NUMBER4) \|\| \
AnnaBridge	171:3a7713b1edbc	367	((NUMBER) == MPU_REGION_NUMBER5) \|\| \
AnnaBridge	171:3a7713b1edbc	368	((NUMBER) == MPU_REGION_NUMBER6) \|\| \
AnnaBridge	171:3a7713b1edbc	369	((NUMBER) == MPU_REGION_NUMBER7))
AnnaBridge	171:3a7713b1edbc	370
AnnaBridge	171:3a7713b1edbc	371	#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) \|\| \
AnnaBridge	171:3a7713b1edbc	372	((SIZE) == MPU_REGION_SIZE_64B) \|\| \
AnnaBridge	171:3a7713b1edbc	373	((SIZE) == MPU_REGION_SIZE_128B) \|\| \
AnnaBridge	171:3a7713b1edbc	374	((SIZE) == MPU_REGION_SIZE_256B) \|\| \
AnnaBridge	171:3a7713b1edbc	375	((SIZE) == MPU_REGION_SIZE_512B) \|\| \
AnnaBridge	171:3a7713b1edbc	376	((SIZE) == MPU_REGION_SIZE_1KB) \|\| \
AnnaBridge	171:3a7713b1edbc	377	((SIZE) == MPU_REGION_SIZE_2KB) \|\| \
AnnaBridge	171:3a7713b1edbc	378	((SIZE) == MPU_REGION_SIZE_4KB) \|\| \
AnnaBridge	171:3a7713b1edbc	379	((SIZE) == MPU_REGION_SIZE_8KB) \|\| \
AnnaBridge	171:3a7713b1edbc	380	((SIZE) == MPU_REGION_SIZE_16KB) \|\| \
AnnaBridge	171:3a7713b1edbc	381	((SIZE) == MPU_REGION_SIZE_32KB) \|\| \
AnnaBridge	171:3a7713b1edbc	382	((SIZE) == MPU_REGION_SIZE_64KB) \|\| \
AnnaBridge	171:3a7713b1edbc	383	((SIZE) == MPU_REGION_SIZE_128KB) \|\| \
AnnaBridge	171:3a7713b1edbc	384	((SIZE) == MPU_REGION_SIZE_256KB) \|\| \
AnnaBridge	171:3a7713b1edbc	385	((SIZE) == MPU_REGION_SIZE_512KB) \|\| \
AnnaBridge	171:3a7713b1edbc	386	((SIZE) == MPU_REGION_SIZE_1MB) \|\| \
AnnaBridge	171:3a7713b1edbc	387	((SIZE) == MPU_REGION_SIZE_2MB) \|\| \
AnnaBridge	171:3a7713b1edbc	388	((SIZE) == MPU_REGION_SIZE_4MB) \|\| \
AnnaBridge	171:3a7713b1edbc	389	((SIZE) == MPU_REGION_SIZE_8MB) \|\| \
AnnaBridge	171:3a7713b1edbc	390	((SIZE) == MPU_REGION_SIZE_16MB) \|\| \
AnnaBridge	171:3a7713b1edbc	391	((SIZE) == MPU_REGION_SIZE_32MB) \|\| \
AnnaBridge	171:3a7713b1edbc	392	((SIZE) == MPU_REGION_SIZE_64MB) \|\| \
AnnaBridge	171:3a7713b1edbc	393	((SIZE) == MPU_REGION_SIZE_128MB) \|\| \
AnnaBridge	171:3a7713b1edbc	394	((SIZE) == MPU_REGION_SIZE_256MB) \|\| \
AnnaBridge	171:3a7713b1edbc	395	((SIZE) == MPU_REGION_SIZE_512MB) \|\| \
AnnaBridge	171:3a7713b1edbc	396	((SIZE) == MPU_REGION_SIZE_1GB) \|\| \
AnnaBridge	171:3a7713b1edbc	397	((SIZE) == MPU_REGION_SIZE_2GB) \|\| \
AnnaBridge	171:3a7713b1edbc	398	((SIZE) == MPU_REGION_SIZE_4GB))
AnnaBridge	171:3a7713b1edbc	399
AnnaBridge	171:3a7713b1edbc	400	#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
AnnaBridge	171:3a7713b1edbc	401	#endif /* __MPU_PRESENT */
AnnaBridge	171:3a7713b1edbc	402
AnnaBridge	171:3a7713b1edbc	403	/**
AnnaBridge	171:3a7713b1edbc	404	* @}
AnnaBridge	171:3a7713b1edbc	405	*/
AnnaBridge	171:3a7713b1edbc	406
AnnaBridge	171:3a7713b1edbc	407	/**
AnnaBridge	171:3a7713b1edbc	408	* @}
AnnaBridge	171:3a7713b1edbc	409	*/
AnnaBridge	171:3a7713b1edbc	410
AnnaBridge	171:3a7713b1edbc	411	/**
AnnaBridge	171:3a7713b1edbc	412	* @}
AnnaBridge	171:3a7713b1edbc	413	*/
AnnaBridge	171:3a7713b1edbc	414
AnnaBridge	171:3a7713b1edbc	415	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	416	}
AnnaBridge	171:3a7713b1edbc	417	#endif
AnnaBridge	171:3a7713b1edbc	418
AnnaBridge	171:3a7713b1edbc	419	#endif /* __STM32F7xx_HAL_CORTEX_H */
AnnaBridge	171:3a7713b1edbc	420
AnnaBridge	171:3a7713b1edbc	421
AnnaBridge	171:3a7713b1edbc	422	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/