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TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f746xx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f746xx.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * This file contains:
AnnaBridge 171:3a7713b1edbc 8 * - Data structures and the address mapping for all peripherals
AnnaBridge 171:3a7713b1edbc 9 * - Peripheral's registers declarations and bits definition
AnnaBridge 171:3a7713b1edbc 10 * - Macros to access peripheral’s registers hardware
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 13 * @attention
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 18 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 19 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 20 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 22 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 23 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 25 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 26 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 38 *
AnnaBridge 171:3a7713b1edbc 39 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 40 */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /** @addtogroup CMSIS_Device
AnnaBridge 171:3a7713b1edbc 43 * @{
AnnaBridge 171:3a7713b1edbc 44 */
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /** @addtogroup stm32f746xx
AnnaBridge 171:3a7713b1edbc 47 * @{
AnnaBridge 171:3a7713b1edbc 48 */
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 #ifndef __STM32F746xx_H
AnnaBridge 171:3a7713b1edbc 51 #define __STM32F746xx_H
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 54 extern "C" {
AnnaBridge 171:3a7713b1edbc 55 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
AnnaBridge 171:3a7713b1edbc 63 * in @ref Library_configuration_section
AnnaBridge 171:3a7713b1edbc 64 */
AnnaBridge 171:3a7713b1edbc 65 typedef enum
AnnaBridge 171:3a7713b1edbc 66 {
AnnaBridge 171:3a7713b1edbc 67 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 171:3a7713b1edbc 68 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 69 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 70 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 71 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 72 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 73 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 74 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 75 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 76 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 171:3a7713b1edbc 77 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 171:3a7713b1edbc 78 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 171:3a7713b1edbc 79 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 171:3a7713b1edbc 80 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 171:3a7713b1edbc 81 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 171:3a7713b1edbc 82 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 171:3a7713b1edbc 83 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 171:3a7713b1edbc 84 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 171:3a7713b1edbc 85 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 171:3a7713b1edbc 86 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 171:3a7713b1edbc 87 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 171:3a7713b1edbc 88 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
AnnaBridge 171:3a7713b1edbc 89 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 90 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 91 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 92 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 93 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 94 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
AnnaBridge 171:3a7713b1edbc 95 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
AnnaBridge 171:3a7713b1edbc 96 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
AnnaBridge 171:3a7713b1edbc 97 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
AnnaBridge 171:3a7713b1edbc 98 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
AnnaBridge 171:3a7713b1edbc 99 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
AnnaBridge 171:3a7713b1edbc 100 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 171:3a7713b1edbc 101 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
AnnaBridge 171:3a7713b1edbc 102 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
AnnaBridge 171:3a7713b1edbc 103 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
AnnaBridge 171:3a7713b1edbc 104 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 171:3a7713b1edbc 105 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 106 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 107 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 108 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 109 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 110 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 111 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 112 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 113 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 114 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 115 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 116 USART3_IRQn = 39, /*!< USART3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 117 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 171:3a7713b1edbc 118 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 171:3a7713b1edbc 119 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
AnnaBridge 171:3a7713b1edbc 120 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
AnnaBridge 171:3a7713b1edbc 121 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
AnnaBridge 171:3a7713b1edbc 122 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
AnnaBridge 171:3a7713b1edbc 123 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
AnnaBridge 171:3a7713b1edbc 124 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
AnnaBridge 171:3a7713b1edbc 125 FMC_IRQn = 48, /*!< FMC global Interrupt */
AnnaBridge 171:3a7713b1edbc 126 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 127 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 128 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 129 UART4_IRQn = 52, /*!< UART4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 130 UART5_IRQn = 53, /*!< UART5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 131 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
AnnaBridge 171:3a7713b1edbc 132 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
AnnaBridge 171:3a7713b1edbc 133 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
AnnaBridge 171:3a7713b1edbc 134 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 135 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 136 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 137 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 138 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
AnnaBridge 171:3a7713b1edbc 139 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
AnnaBridge 171:3a7713b1edbc 140 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
AnnaBridge 171:3a7713b1edbc 141 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
AnnaBridge 171:3a7713b1edbc 142 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
AnnaBridge 171:3a7713b1edbc 143 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
AnnaBridge 171:3a7713b1edbc 144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
AnnaBridge 171:3a7713b1edbc 145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
AnnaBridge 171:3a7713b1edbc 146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
AnnaBridge 171:3a7713b1edbc 147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
AnnaBridge 171:3a7713b1edbc 148 USART6_IRQn = 71, /*!< USART6 global interrupt */
AnnaBridge 171:3a7713b1edbc 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
AnnaBridge 171:3a7713b1edbc 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 171:3a7713b1edbc 151 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
AnnaBridge 171:3a7713b1edbc 152 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
AnnaBridge 171:3a7713b1edbc 153 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
AnnaBridge 171:3a7713b1edbc 154 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
AnnaBridge 171:3a7713b1edbc 155 DCMI_IRQn = 78, /*!< DCMI global interrupt */
AnnaBridge 171:3a7713b1edbc 156 RNG_IRQn = 80, /*!< RNG global interrupt */
AnnaBridge 171:3a7713b1edbc 157 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 171:3a7713b1edbc 158 UART7_IRQn = 82, /*!< UART7 global interrupt */
AnnaBridge 171:3a7713b1edbc 159 UART8_IRQn = 83, /*!< UART8 global interrupt */
AnnaBridge 171:3a7713b1edbc 160 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 161 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 162 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
AnnaBridge 171:3a7713b1edbc 163 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 164 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
AnnaBridge 171:3a7713b1edbc 165 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
AnnaBridge 171:3a7713b1edbc 166 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
AnnaBridge 171:3a7713b1edbc 167 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 168 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
AnnaBridge 171:3a7713b1edbc 169 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
AnnaBridge 171:3a7713b1edbc 170 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
AnnaBridge 171:3a7713b1edbc 171 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 172 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 173 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
AnnaBridge 171:3a7713b1edbc 174 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /**
AnnaBridge 171:3a7713b1edbc 177 * @}
AnnaBridge 171:3a7713b1edbc 178 */
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 /**
AnnaBridge 171:3a7713b1edbc 181 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
AnnaBridge 171:3a7713b1edbc 182 */
AnnaBridge 171:3a7713b1edbc 183 #define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */
AnnaBridge 171:3a7713b1edbc 184 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
AnnaBridge 171:3a7713b1edbc 185 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
AnnaBridge 171:3a7713b1edbc 186 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 187 #define __FPU_PRESENT 1 /*!< FPU present */
AnnaBridge 171:3a7713b1edbc 188 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
AnnaBridge 171:3a7713b1edbc 189 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
AnnaBridge 171:3a7713b1edbc 190 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 #include "system_stm32f7xx.h"
AnnaBridge 171:3a7713b1edbc 194 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /** @addtogroup Peripheral_registers_structures
AnnaBridge 171:3a7713b1edbc 197 * @{
AnnaBridge 171:3a7713b1edbc 198 */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /**
AnnaBridge 171:3a7713b1edbc 201 * @brief Analog to Digital Converter
AnnaBridge 171:3a7713b1edbc 202 */
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 typedef struct
AnnaBridge 171:3a7713b1edbc 205 {
AnnaBridge 171:3a7713b1edbc 206 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 207 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 208 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 209 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 212 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 213 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 214 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 215 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 216 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 217 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 218 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 219 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 220 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
AnnaBridge 171:3a7713b1edbc 221 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 222 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 223 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 226 } ADC_TypeDef;
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 typedef struct
AnnaBridge 171:3a7713b1edbc 229 {
AnnaBridge 171:3a7713b1edbc 230 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
AnnaBridge 171:3a7713b1edbc 231 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
AnnaBridge 171:3a7713b1edbc 232 __IO uint32_t CDR; /*!< ADC common regular data register for dual
AnnaBridge 171:3a7713b1edbc 233 AND triple modes, Address offset: ADC1 base address + 0x308 */
AnnaBridge 171:3a7713b1edbc 234 } ADC_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237 /**
AnnaBridge 171:3a7713b1edbc 238 * @brief Controller Area Network TxMailBox
AnnaBridge 171:3a7713b1edbc 239 */
AnnaBridge 171:3a7713b1edbc 240
AnnaBridge 171:3a7713b1edbc 241 typedef struct
AnnaBridge 171:3a7713b1edbc 242 {
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
AnnaBridge 171:3a7713b1edbc 245 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
AnnaBridge 171:3a7713b1edbc 246 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
AnnaBridge 171:3a7713b1edbc 247 } CAN_TxMailBox_TypeDef;
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 /**
AnnaBridge 171:3a7713b1edbc 250 * @brief Controller Area Network FIFOMailBox
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 typedef struct
AnnaBridge 171:3a7713b1edbc 254 {
AnnaBridge 171:3a7713b1edbc 255 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
AnnaBridge 171:3a7713b1edbc 256 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
AnnaBridge 171:3a7713b1edbc 257 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
AnnaBridge 171:3a7713b1edbc 258 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
AnnaBridge 171:3a7713b1edbc 259 } CAN_FIFOMailBox_TypeDef;
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 /**
AnnaBridge 171:3a7713b1edbc 262 * @brief Controller Area Network FilterRegister
AnnaBridge 171:3a7713b1edbc 263 */
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 typedef struct
AnnaBridge 171:3a7713b1edbc 266 {
AnnaBridge 171:3a7713b1edbc 267 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
AnnaBridge 171:3a7713b1edbc 268 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
AnnaBridge 171:3a7713b1edbc 269 } CAN_FilterRegister_TypeDef;
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271 /**
AnnaBridge 171:3a7713b1edbc 272 * @brief Controller Area Network
AnnaBridge 171:3a7713b1edbc 273 */
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 typedef struct
AnnaBridge 171:3a7713b1edbc 276 {
AnnaBridge 171:3a7713b1edbc 277 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 278 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 279 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 280 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 281 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 282 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 283 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 284 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 285 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
AnnaBridge 171:3a7713b1edbc 286 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
AnnaBridge 171:3a7713b1edbc 287 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
AnnaBridge 171:3a7713b1edbc 288 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
AnnaBridge 171:3a7713b1edbc 289 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 290 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
AnnaBridge 171:3a7713b1edbc 291 uint32_t RESERVED2; /*!< Reserved, 0x208 */
AnnaBridge 171:3a7713b1edbc 292 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
AnnaBridge 171:3a7713b1edbc 293 uint32_t RESERVED3; /*!< Reserved, 0x210 */
AnnaBridge 171:3a7713b1edbc 294 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
AnnaBridge 171:3a7713b1edbc 295 uint32_t RESERVED4; /*!< Reserved, 0x218 */
AnnaBridge 171:3a7713b1edbc 296 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
AnnaBridge 171:3a7713b1edbc 297 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
AnnaBridge 171:3a7713b1edbc 298 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
AnnaBridge 171:3a7713b1edbc 299 } CAN_TypeDef;
AnnaBridge 171:3a7713b1edbc 300
AnnaBridge 171:3a7713b1edbc 301 /**
AnnaBridge 171:3a7713b1edbc 302 * @brief HDMI-CEC
AnnaBridge 171:3a7713b1edbc 303 */
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 typedef struct
AnnaBridge 171:3a7713b1edbc 306 {
AnnaBridge 171:3a7713b1edbc 307 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
AnnaBridge 171:3a7713b1edbc 308 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
AnnaBridge 171:3a7713b1edbc 309 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
AnnaBridge 171:3a7713b1edbc 310 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
AnnaBridge 171:3a7713b1edbc 311 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
AnnaBridge 171:3a7713b1edbc 312 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
AnnaBridge 171:3a7713b1edbc 313 }CEC_TypeDef;
AnnaBridge 171:3a7713b1edbc 314
AnnaBridge 171:3a7713b1edbc 315 /**
AnnaBridge 171:3a7713b1edbc 316 * @brief CRC calculation unit
AnnaBridge 171:3a7713b1edbc 317 */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 typedef struct
AnnaBridge 171:3a7713b1edbc 320 {
AnnaBridge 171:3a7713b1edbc 321 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 322 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 323 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 171:3a7713b1edbc 324 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 171:3a7713b1edbc 325 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 326 uint32_t RESERVED2; /*!< Reserved, 0x0C */
AnnaBridge 171:3a7713b1edbc 327 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 328 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 329 } CRC_TypeDef;
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 /**
AnnaBridge 171:3a7713b1edbc 332 * @brief Digital to Analog Converter
AnnaBridge 171:3a7713b1edbc 333 */
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 typedef struct
AnnaBridge 171:3a7713b1edbc 336 {
AnnaBridge 171:3a7713b1edbc 337 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 338 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 339 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 341 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 342 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 343 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 348 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 349 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 350 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 351 } DAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 /**
AnnaBridge 171:3a7713b1edbc 355 * @brief Debug MCU
AnnaBridge 171:3a7713b1edbc 356 */
AnnaBridge 171:3a7713b1edbc 357
AnnaBridge 171:3a7713b1edbc 358 typedef struct
AnnaBridge 171:3a7713b1edbc 359 {
AnnaBridge 171:3a7713b1edbc 360 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 361 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 362 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 363 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 364 }DBGMCU_TypeDef;
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 /**
AnnaBridge 171:3a7713b1edbc 367 * @brief DCMI
AnnaBridge 171:3a7713b1edbc 368 */
AnnaBridge 171:3a7713b1edbc 369
AnnaBridge 171:3a7713b1edbc 370 typedef struct
AnnaBridge 171:3a7713b1edbc 371 {
AnnaBridge 171:3a7713b1edbc 372 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 373 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 374 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 375 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 376 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 377 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 378 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 379 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 380 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 381 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 382 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 383 } DCMI_TypeDef;
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 /**
AnnaBridge 171:3a7713b1edbc 386 * @brief DMA Controller
AnnaBridge 171:3a7713b1edbc 387 */
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 typedef struct
AnnaBridge 171:3a7713b1edbc 390 {
AnnaBridge 171:3a7713b1edbc 391 __IO uint32_t CR; /*!< DMA stream x configuration register */
AnnaBridge 171:3a7713b1edbc 392 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
AnnaBridge 171:3a7713b1edbc 393 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
AnnaBridge 171:3a7713b1edbc 394 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
AnnaBridge 171:3a7713b1edbc 395 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
AnnaBridge 171:3a7713b1edbc 396 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
AnnaBridge 171:3a7713b1edbc 397 } DMA_Stream_TypeDef;
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399 typedef struct
AnnaBridge 171:3a7713b1edbc 400 {
AnnaBridge 171:3a7713b1edbc 401 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 402 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 403 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 404 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 405 } DMA_TypeDef;
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /**
AnnaBridge 171:3a7713b1edbc 408 * @brief DMA2D Controller
AnnaBridge 171:3a7713b1edbc 409 */
AnnaBridge 171:3a7713b1edbc 410
AnnaBridge 171:3a7713b1edbc 411 typedef struct
AnnaBridge 171:3a7713b1edbc 412 {
AnnaBridge 171:3a7713b1edbc 413 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 414 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 415 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 416 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 417 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 418 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 419 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 420 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 421 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 422 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 423 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 424 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 425 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 426 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 427 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 428 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 429 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 430 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 431 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 432 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 433 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
AnnaBridge 171:3a7713b1edbc 434 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
AnnaBridge 171:3a7713b1edbc 435 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
AnnaBridge 171:3a7713b1edbc 436 } DMA2D_TypeDef;
AnnaBridge 171:3a7713b1edbc 437
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 /**
AnnaBridge 171:3a7713b1edbc 440 * @brief Ethernet MAC
AnnaBridge 171:3a7713b1edbc 441 */
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 typedef struct
AnnaBridge 171:3a7713b1edbc 444 {
AnnaBridge 171:3a7713b1edbc 445 __IO uint32_t MACCR;
AnnaBridge 171:3a7713b1edbc 446 __IO uint32_t MACFFR;
AnnaBridge 171:3a7713b1edbc 447 __IO uint32_t MACHTHR;
AnnaBridge 171:3a7713b1edbc 448 __IO uint32_t MACHTLR;
AnnaBridge 171:3a7713b1edbc 449 __IO uint32_t MACMIIAR;
AnnaBridge 171:3a7713b1edbc 450 __IO uint32_t MACMIIDR;
AnnaBridge 171:3a7713b1edbc 451 __IO uint32_t MACFCR;
AnnaBridge 171:3a7713b1edbc 452 __IO uint32_t MACVLANTR; /* 8 */
AnnaBridge 171:3a7713b1edbc 453 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 454 __IO uint32_t MACRWUFFR; /* 11 */
AnnaBridge 171:3a7713b1edbc 455 __IO uint32_t MACPMTCSR;
AnnaBridge 171:3a7713b1edbc 456 uint32_t RESERVED1;
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t MACDBGR;
AnnaBridge 171:3a7713b1edbc 458 __IO uint32_t MACSR; /* 15 */
AnnaBridge 171:3a7713b1edbc 459 __IO uint32_t MACIMR;
AnnaBridge 171:3a7713b1edbc 460 __IO uint32_t MACA0HR;
AnnaBridge 171:3a7713b1edbc 461 __IO uint32_t MACA0LR;
AnnaBridge 171:3a7713b1edbc 462 __IO uint32_t MACA1HR;
AnnaBridge 171:3a7713b1edbc 463 __IO uint32_t MACA1LR;
AnnaBridge 171:3a7713b1edbc 464 __IO uint32_t MACA2HR;
AnnaBridge 171:3a7713b1edbc 465 __IO uint32_t MACA2LR;
AnnaBridge 171:3a7713b1edbc 466 __IO uint32_t MACA3HR;
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t MACA3LR; /* 24 */
AnnaBridge 171:3a7713b1edbc 468 uint32_t RESERVED2[40];
AnnaBridge 171:3a7713b1edbc 469 __IO uint32_t MMCCR; /* 65 */
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t MMCRIR;
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t MMCTIR;
AnnaBridge 171:3a7713b1edbc 472 __IO uint32_t MMCRIMR;
AnnaBridge 171:3a7713b1edbc 473 __IO uint32_t MMCTIMR; /* 69 */
AnnaBridge 171:3a7713b1edbc 474 uint32_t RESERVED3[14];
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t MMCTGFSCCR; /* 84 */
AnnaBridge 171:3a7713b1edbc 476 __IO uint32_t MMCTGFMSCCR;
AnnaBridge 171:3a7713b1edbc 477 uint32_t RESERVED4[5];
AnnaBridge 171:3a7713b1edbc 478 __IO uint32_t MMCTGFCR;
AnnaBridge 171:3a7713b1edbc 479 uint32_t RESERVED5[10];
AnnaBridge 171:3a7713b1edbc 480 __IO uint32_t MMCRFCECR;
AnnaBridge 171:3a7713b1edbc 481 __IO uint32_t MMCRFAECR;
AnnaBridge 171:3a7713b1edbc 482 uint32_t RESERVED6[10];
AnnaBridge 171:3a7713b1edbc 483 __IO uint32_t MMCRGUFCR;
AnnaBridge 171:3a7713b1edbc 484 uint32_t RESERVED7[334];
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t PTPTSCR;
AnnaBridge 171:3a7713b1edbc 486 __IO uint32_t PTPSSIR;
AnnaBridge 171:3a7713b1edbc 487 __IO uint32_t PTPTSHR;
AnnaBridge 171:3a7713b1edbc 488 __IO uint32_t PTPTSLR;
AnnaBridge 171:3a7713b1edbc 489 __IO uint32_t PTPTSHUR;
AnnaBridge 171:3a7713b1edbc 490 __IO uint32_t PTPTSLUR;
AnnaBridge 171:3a7713b1edbc 491 __IO uint32_t PTPTSAR;
AnnaBridge 171:3a7713b1edbc 492 __IO uint32_t PTPTTHR;
AnnaBridge 171:3a7713b1edbc 493 __IO uint32_t PTPTTLR;
AnnaBridge 171:3a7713b1edbc 494 __IO uint32_t RESERVED8;
AnnaBridge 171:3a7713b1edbc 495 __IO uint32_t PTPTSSR;
AnnaBridge 171:3a7713b1edbc 496 uint32_t RESERVED9[565];
AnnaBridge 171:3a7713b1edbc 497 __IO uint32_t DMABMR;
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t DMATPDR;
AnnaBridge 171:3a7713b1edbc 499 __IO uint32_t DMARPDR;
AnnaBridge 171:3a7713b1edbc 500 __IO uint32_t DMARDLAR;
AnnaBridge 171:3a7713b1edbc 501 __IO uint32_t DMATDLAR;
AnnaBridge 171:3a7713b1edbc 502 __IO uint32_t DMASR;
AnnaBridge 171:3a7713b1edbc 503 __IO uint32_t DMAOMR;
AnnaBridge 171:3a7713b1edbc 504 __IO uint32_t DMAIER;
AnnaBridge 171:3a7713b1edbc 505 __IO uint32_t DMAMFBOCR;
AnnaBridge 171:3a7713b1edbc 506 __IO uint32_t DMARSWTR;
AnnaBridge 171:3a7713b1edbc 507 uint32_t RESERVED10[8];
AnnaBridge 171:3a7713b1edbc 508 __IO uint32_t DMACHTDR;
AnnaBridge 171:3a7713b1edbc 509 __IO uint32_t DMACHRDR;
AnnaBridge 171:3a7713b1edbc 510 __IO uint32_t DMACHTBAR;
AnnaBridge 171:3a7713b1edbc 511 __IO uint32_t DMACHRBAR;
AnnaBridge 171:3a7713b1edbc 512 } ETH_TypeDef;
AnnaBridge 171:3a7713b1edbc 513
AnnaBridge 171:3a7713b1edbc 514 /**
AnnaBridge 171:3a7713b1edbc 515 * @brief External Interrupt/Event Controller
AnnaBridge 171:3a7713b1edbc 516 */
AnnaBridge 171:3a7713b1edbc 517
AnnaBridge 171:3a7713b1edbc 518 typedef struct
AnnaBridge 171:3a7713b1edbc 519 {
AnnaBridge 171:3a7713b1edbc 520 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 521 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 523 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 524 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 525 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 526 } EXTI_TypeDef;
AnnaBridge 171:3a7713b1edbc 527
AnnaBridge 171:3a7713b1edbc 528 /**
AnnaBridge 171:3a7713b1edbc 529 * @brief FLASH Registers
AnnaBridge 171:3a7713b1edbc 530 */
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 typedef struct
AnnaBridge 171:3a7713b1edbc 533 {
AnnaBridge 171:3a7713b1edbc 534 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 535 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 536 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 537 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 538 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 539 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 540 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 541 } FLASH_TypeDef;
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544
AnnaBridge 171:3a7713b1edbc 545 /**
AnnaBridge 171:3a7713b1edbc 546 * @brief Flexible Memory Controller
AnnaBridge 171:3a7713b1edbc 547 */
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 typedef struct
AnnaBridge 171:3a7713b1edbc 550 {
AnnaBridge 171:3a7713b1edbc 551 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
AnnaBridge 171:3a7713b1edbc 552 } FMC_Bank1_TypeDef;
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /**
AnnaBridge 171:3a7713b1edbc 555 * @brief Flexible Memory Controller Bank1E
AnnaBridge 171:3a7713b1edbc 556 */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 typedef struct
AnnaBridge 171:3a7713b1edbc 559 {
AnnaBridge 171:3a7713b1edbc 560 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
AnnaBridge 171:3a7713b1edbc 561 } FMC_Bank1E_TypeDef;
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 /**
AnnaBridge 171:3a7713b1edbc 564 * @brief Flexible Memory Controller Bank3
AnnaBridge 171:3a7713b1edbc 565 */
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 typedef struct
AnnaBridge 171:3a7713b1edbc 568 {
AnnaBridge 171:3a7713b1edbc 569 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 570 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 571 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 572 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 573 uint32_t RESERVED0; /*!< Reserved, 0x90 */
AnnaBridge 171:3a7713b1edbc 574 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 575 } FMC_Bank3_TypeDef;
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577 /**
AnnaBridge 171:3a7713b1edbc 578 * @brief Flexible Memory Controller Bank5_6
AnnaBridge 171:3a7713b1edbc 579 */
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 typedef struct
AnnaBridge 171:3a7713b1edbc 582 {
AnnaBridge 171:3a7713b1edbc 583 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
AnnaBridge 171:3a7713b1edbc 584 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
AnnaBridge 171:3a7713b1edbc 585 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
AnnaBridge 171:3a7713b1edbc 586 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
AnnaBridge 171:3a7713b1edbc 587 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
AnnaBridge 171:3a7713b1edbc 588 } FMC_Bank5_6_TypeDef;
AnnaBridge 171:3a7713b1edbc 589
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 /**
AnnaBridge 171:3a7713b1edbc 592 * @brief General Purpose I/O
AnnaBridge 171:3a7713b1edbc 593 */
AnnaBridge 171:3a7713b1edbc 594
AnnaBridge 171:3a7713b1edbc 595 typedef struct
AnnaBridge 171:3a7713b1edbc 596 {
AnnaBridge 171:3a7713b1edbc 597 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 598 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 599 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 600 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 601 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 602 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 603 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 604 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 605 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 171:3a7713b1edbc 606 } GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 /**
AnnaBridge 171:3a7713b1edbc 609 * @brief System configuration controller
AnnaBridge 171:3a7713b1edbc 610 */
AnnaBridge 171:3a7713b1edbc 611
AnnaBridge 171:3a7713b1edbc 612 typedef struct
AnnaBridge 171:3a7713b1edbc 613 {
AnnaBridge 171:3a7713b1edbc 614 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 615 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 616 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 171:3a7713b1edbc 617 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
AnnaBridge 171:3a7713b1edbc 618 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 619 } SYSCFG_TypeDef;
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 /**
AnnaBridge 171:3a7713b1edbc 622 * @brief Inter-integrated Circuit Interface
AnnaBridge 171:3a7713b1edbc 623 */
AnnaBridge 171:3a7713b1edbc 624
AnnaBridge 171:3a7713b1edbc 625 typedef struct
AnnaBridge 171:3a7713b1edbc 626 {
AnnaBridge 171:3a7713b1edbc 627 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 628 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 629 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 630 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 631 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 632 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 633 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 634 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 635 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 636 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 637 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 638 } I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 /**
AnnaBridge 171:3a7713b1edbc 641 * @brief Independent WATCHDOG
AnnaBridge 171:3a7713b1edbc 642 */
AnnaBridge 171:3a7713b1edbc 643
AnnaBridge 171:3a7713b1edbc 644 typedef struct
AnnaBridge 171:3a7713b1edbc 645 {
AnnaBridge 171:3a7713b1edbc 646 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 647 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 648 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 649 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 650 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 651 } IWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 652
AnnaBridge 171:3a7713b1edbc 653
AnnaBridge 171:3a7713b1edbc 654 /**
AnnaBridge 171:3a7713b1edbc 655 * @brief LCD-TFT Display Controller
AnnaBridge 171:3a7713b1edbc 656 */
AnnaBridge 171:3a7713b1edbc 657
AnnaBridge 171:3a7713b1edbc 658 typedef struct
AnnaBridge 171:3a7713b1edbc 659 {
AnnaBridge 171:3a7713b1edbc 660 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
AnnaBridge 171:3a7713b1edbc 661 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 662 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 663 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 664 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 665 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 666 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
AnnaBridge 171:3a7713b1edbc 667 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 668 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
AnnaBridge 171:3a7713b1edbc 669 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 670 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
AnnaBridge 171:3a7713b1edbc 671 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 672 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 673 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 674 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 675 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 676 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 677 } LTDC_TypeDef;
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 /**
AnnaBridge 171:3a7713b1edbc 680 * @brief LCD-TFT Display layer x Controller
AnnaBridge 171:3a7713b1edbc 681 */
AnnaBridge 171:3a7713b1edbc 682
AnnaBridge 171:3a7713b1edbc 683 typedef struct
AnnaBridge 171:3a7713b1edbc 684 {
AnnaBridge 171:3a7713b1edbc 685 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 686 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 687 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 688 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 689 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 690 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 691 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 692 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 693 uint32_t RESERVED0[2]; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 694 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 695 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 696 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 697 uint32_t RESERVED1[3]; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 698 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
AnnaBridge 171:3a7713b1edbc 699
AnnaBridge 171:3a7713b1edbc 700 } LTDC_Layer_TypeDef;
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702 /**
AnnaBridge 171:3a7713b1edbc 703 * @brief Power Control
AnnaBridge 171:3a7713b1edbc 704 */
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 typedef struct
AnnaBridge 171:3a7713b1edbc 707 {
AnnaBridge 171:3a7713b1edbc 708 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 709 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 710 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 711 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 712 } PWR_TypeDef;
AnnaBridge 171:3a7713b1edbc 713
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 /**
AnnaBridge 171:3a7713b1edbc 716 * @brief Reset and Clock Control
AnnaBridge 171:3a7713b1edbc 717 */
AnnaBridge 171:3a7713b1edbc 718
AnnaBridge 171:3a7713b1edbc 719 typedef struct
AnnaBridge 171:3a7713b1edbc 720 {
AnnaBridge 171:3a7713b1edbc 721 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 722 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 723 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 724 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 725 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 726 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 727 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 728 uint32_t RESERVED0; /*!< Reserved, 0x1C */
AnnaBridge 171:3a7713b1edbc 729 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 730 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 731 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
AnnaBridge 171:3a7713b1edbc 732 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 733 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 734 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 735 uint32_t RESERVED2; /*!< Reserved, 0x3C */
AnnaBridge 171:3a7713b1edbc 736 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 737 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 738 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
AnnaBridge 171:3a7713b1edbc 739 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 740 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 741 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 742 uint32_t RESERVED4; /*!< Reserved, 0x5C */
AnnaBridge 171:3a7713b1edbc 743 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 744 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 745 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
AnnaBridge 171:3a7713b1edbc 746 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 747 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 748 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
AnnaBridge 171:3a7713b1edbc 749 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 750 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 751 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 752 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 753 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 754
AnnaBridge 171:3a7713b1edbc 755 } RCC_TypeDef;
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 /**
AnnaBridge 171:3a7713b1edbc 758 * @brief Real-Time Clock
AnnaBridge 171:3a7713b1edbc 759 */
AnnaBridge 171:3a7713b1edbc 760
AnnaBridge 171:3a7713b1edbc 761 typedef struct
AnnaBridge 171:3a7713b1edbc 762 {
AnnaBridge 171:3a7713b1edbc 763 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 764 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 765 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 766 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 767 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 768 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 769 uint32_t reserved; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 770 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 771 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 772 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 773 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 774 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 775 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 776 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 777 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 778 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 779 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 780 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 781 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 782 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 783 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 784 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 785 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 786 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 787 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 788 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 789 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 790 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 791 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 792 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 793 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 794 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 795 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 796 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 797 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 798 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 799 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 800 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 801 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 802 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 803 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 804 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 805 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 806 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 807 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 808 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 809 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
AnnaBridge 171:3a7713b1edbc 810 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
AnnaBridge 171:3a7713b1edbc 811 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 812 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 813 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
AnnaBridge 171:3a7713b1edbc 814 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
AnnaBridge 171:3a7713b1edbc 815 } RTC_TypeDef;
AnnaBridge 171:3a7713b1edbc 816
AnnaBridge 171:3a7713b1edbc 817
AnnaBridge 171:3a7713b1edbc 818 /**
AnnaBridge 171:3a7713b1edbc 819 * @brief Serial Audio Interface
AnnaBridge 171:3a7713b1edbc 820 */
AnnaBridge 171:3a7713b1edbc 821
AnnaBridge 171:3a7713b1edbc 822 typedef struct
AnnaBridge 171:3a7713b1edbc 823 {
AnnaBridge 171:3a7713b1edbc 824 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 825 } SAI_TypeDef;
AnnaBridge 171:3a7713b1edbc 826
AnnaBridge 171:3a7713b1edbc 827 typedef struct
AnnaBridge 171:3a7713b1edbc 828 {
AnnaBridge 171:3a7713b1edbc 829 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 830 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 831 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 832 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 833 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 834 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 835 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 836 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 837 } SAI_Block_TypeDef;
AnnaBridge 171:3a7713b1edbc 838
AnnaBridge 171:3a7713b1edbc 839 /**
AnnaBridge 171:3a7713b1edbc 840 * @brief SPDIF-RX Interface
AnnaBridge 171:3a7713b1edbc 841 */
AnnaBridge 171:3a7713b1edbc 842
AnnaBridge 171:3a7713b1edbc 843 typedef struct
AnnaBridge 171:3a7713b1edbc 844 {
AnnaBridge 171:3a7713b1edbc 845 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 846 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 847 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 848 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 849 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 850 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 851 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 852 } SPDIFRX_TypeDef;
AnnaBridge 171:3a7713b1edbc 853
AnnaBridge 171:3a7713b1edbc 854 /**
AnnaBridge 171:3a7713b1edbc 855 * @brief SD host Interface
AnnaBridge 171:3a7713b1edbc 856 */
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 typedef struct
AnnaBridge 171:3a7713b1edbc 859 {
AnnaBridge 171:3a7713b1edbc 860 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 861 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 862 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 863 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 864 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 865 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 866 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 867 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 868 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 869 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 870 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 871 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 872 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 873 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 874 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 875 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 876 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
AnnaBridge 171:3a7713b1edbc 877 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 878 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
AnnaBridge 171:3a7713b1edbc 879 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 880 } SDMMC_TypeDef;
AnnaBridge 171:3a7713b1edbc 881
AnnaBridge 171:3a7713b1edbc 882 /**
AnnaBridge 171:3a7713b1edbc 883 * @brief Serial Peripheral Interface
AnnaBridge 171:3a7713b1edbc 884 */
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886 typedef struct
AnnaBridge 171:3a7713b1edbc 887 {
AnnaBridge 171:3a7713b1edbc 888 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 889 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 890 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 891 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 892 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 893 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 894 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 895 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 896 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 897 } SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 898
AnnaBridge 171:3a7713b1edbc 899 /**
AnnaBridge 171:3a7713b1edbc 900 * @brief QUAD Serial Peripheral Interface
AnnaBridge 171:3a7713b1edbc 901 */
AnnaBridge 171:3a7713b1edbc 902
AnnaBridge 171:3a7713b1edbc 903 typedef struct
AnnaBridge 171:3a7713b1edbc 904 {
AnnaBridge 171:3a7713b1edbc 905 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 906 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 907 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 908 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 909 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 910 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 911 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 912 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 913 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 914 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 915 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 916 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 917 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 918 } QUADSPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 919
AnnaBridge 171:3a7713b1edbc 920 /**
AnnaBridge 171:3a7713b1edbc 921 * @brief TIM
AnnaBridge 171:3a7713b1edbc 922 */
AnnaBridge 171:3a7713b1edbc 923
AnnaBridge 171:3a7713b1edbc 924 typedef struct
AnnaBridge 171:3a7713b1edbc 925 {
AnnaBridge 171:3a7713b1edbc 926 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 927 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 928 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 929 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 930 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 931 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 932 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 933 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 934 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 935 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 936 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 937 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 938 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 939 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 940 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 941 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 942 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 943 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 944 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 945 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 946 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 947 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 948 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 949 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 950
AnnaBridge 171:3a7713b1edbc 951 } TIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 952
AnnaBridge 171:3a7713b1edbc 953 /**
AnnaBridge 171:3a7713b1edbc 954 * @brief LPTIMIMER
AnnaBridge 171:3a7713b1edbc 955 */
AnnaBridge 171:3a7713b1edbc 956 typedef struct
AnnaBridge 171:3a7713b1edbc 957 {
AnnaBridge 171:3a7713b1edbc 958 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 959 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 960 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 961 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 962 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 963 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 964 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 965 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 966 } LPTIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 967
AnnaBridge 171:3a7713b1edbc 968
AnnaBridge 171:3a7713b1edbc 969 /**
AnnaBridge 171:3a7713b1edbc 970 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 171:3a7713b1edbc 971 */
AnnaBridge 171:3a7713b1edbc 972
AnnaBridge 171:3a7713b1edbc 973 typedef struct
AnnaBridge 171:3a7713b1edbc 974 {
AnnaBridge 171:3a7713b1edbc 975 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 976 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 977 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 978 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 979 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 980 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 981 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 982 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 983 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 984 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 985 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 986 } USART_TypeDef;
AnnaBridge 171:3a7713b1edbc 987
AnnaBridge 171:3a7713b1edbc 988
AnnaBridge 171:3a7713b1edbc 989 /**
AnnaBridge 171:3a7713b1edbc 990 * @brief Window WATCHDOG
AnnaBridge 171:3a7713b1edbc 991 */
AnnaBridge 171:3a7713b1edbc 992
AnnaBridge 171:3a7713b1edbc 993 typedef struct
AnnaBridge 171:3a7713b1edbc 994 {
AnnaBridge 171:3a7713b1edbc 995 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 996 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 997 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 998 } WWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 999
AnnaBridge 171:3a7713b1edbc 1000
AnnaBridge 171:3a7713b1edbc 1001 /**
AnnaBridge 171:3a7713b1edbc 1002 * @brief RNG
AnnaBridge 171:3a7713b1edbc 1003 */
AnnaBridge 171:3a7713b1edbc 1004
AnnaBridge 171:3a7713b1edbc 1005 typedef struct
AnnaBridge 171:3a7713b1edbc 1006 {
AnnaBridge 171:3a7713b1edbc 1007 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 1008 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 1009 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 1010 } RNG_TypeDef;
AnnaBridge 171:3a7713b1edbc 1011
AnnaBridge 171:3a7713b1edbc 1012 /**
AnnaBridge 171:3a7713b1edbc 1013 * @}
AnnaBridge 171:3a7713b1edbc 1014 */
AnnaBridge 171:3a7713b1edbc 1015
AnnaBridge 171:3a7713b1edbc 1016 /**
AnnaBridge 171:3a7713b1edbc 1017 * @brief USB_OTG_Core_Registers
AnnaBridge 171:3a7713b1edbc 1018 */
AnnaBridge 171:3a7713b1edbc 1019 typedef struct
AnnaBridge 171:3a7713b1edbc 1020 {
AnnaBridge 171:3a7713b1edbc 1021 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 171:3a7713b1edbc 1022 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 171:3a7713b1edbc 1023 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 171:3a7713b1edbc 1024 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 171:3a7713b1edbc 1025 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 171:3a7713b1edbc 1026 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 171:3a7713b1edbc 1027 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 171:3a7713b1edbc 1028 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 171:3a7713b1edbc 1029 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 171:3a7713b1edbc 1030 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 171:3a7713b1edbc 1031 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 171:3a7713b1edbc 1032 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 171:3a7713b1edbc 1033 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 171:3a7713b1edbc 1034 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 171:3a7713b1edbc 1035 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 171:3a7713b1edbc 1036 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
AnnaBridge 171:3a7713b1edbc 1037 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
AnnaBridge 171:3a7713b1edbc 1038 uint32_t Reserved6; /*!< Reserved 050h */
AnnaBridge 171:3a7713b1edbc 1039 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
AnnaBridge 171:3a7713b1edbc 1040 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
AnnaBridge 171:3a7713b1edbc 1041 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
AnnaBridge 171:3a7713b1edbc 1042 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
AnnaBridge 171:3a7713b1edbc 1043 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
AnnaBridge 171:3a7713b1edbc 1044 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 171:3a7713b1edbc 1045 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 171:3a7713b1edbc 1046 } USB_OTG_GlobalTypeDef;
AnnaBridge 171:3a7713b1edbc 1047
AnnaBridge 171:3a7713b1edbc 1048
AnnaBridge 171:3a7713b1edbc 1049 /**
AnnaBridge 171:3a7713b1edbc 1050 * @brief USB_OTG_device_Registers
AnnaBridge 171:3a7713b1edbc 1051 */
AnnaBridge 171:3a7713b1edbc 1052 typedef struct
AnnaBridge 171:3a7713b1edbc 1053 {
AnnaBridge 171:3a7713b1edbc 1054 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 171:3a7713b1edbc 1055 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 171:3a7713b1edbc 1056 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 171:3a7713b1edbc 1057 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 171:3a7713b1edbc 1058 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 171:3a7713b1edbc 1059 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 171:3a7713b1edbc 1060 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 171:3a7713b1edbc 1061 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 171:3a7713b1edbc 1062 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 171:3a7713b1edbc 1063 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 171:3a7713b1edbc 1064 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 171:3a7713b1edbc 1065 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 171:3a7713b1edbc 1066 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 171:3a7713b1edbc 1067 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 171:3a7713b1edbc 1068 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 171:3a7713b1edbc 1069 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 171:3a7713b1edbc 1070 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 171:3a7713b1edbc 1071 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 171:3a7713b1edbc 1072 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 171:3a7713b1edbc 1073 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 171:3a7713b1edbc 1074 } USB_OTG_DeviceTypeDef;
AnnaBridge 171:3a7713b1edbc 1075
AnnaBridge 171:3a7713b1edbc 1076
AnnaBridge 171:3a7713b1edbc 1077 /**
AnnaBridge 171:3a7713b1edbc 1078 * @brief USB_OTG_IN_Endpoint-Specific_Register
AnnaBridge 171:3a7713b1edbc 1079 */
AnnaBridge 171:3a7713b1edbc 1080 typedef struct
AnnaBridge 171:3a7713b1edbc 1081 {
AnnaBridge 171:3a7713b1edbc 1082 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 171:3a7713b1edbc 1083 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 171:3a7713b1edbc 1084 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 171:3a7713b1edbc 1085 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 171:3a7713b1edbc 1086 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 171:3a7713b1edbc 1087 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 171:3a7713b1edbc 1088 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 171:3a7713b1edbc 1089 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 171:3a7713b1edbc 1090 } USB_OTG_INEndpointTypeDef;
AnnaBridge 171:3a7713b1edbc 1091
AnnaBridge 171:3a7713b1edbc 1092
AnnaBridge 171:3a7713b1edbc 1093 /**
AnnaBridge 171:3a7713b1edbc 1094 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
AnnaBridge 171:3a7713b1edbc 1095 */
AnnaBridge 171:3a7713b1edbc 1096 typedef struct
AnnaBridge 171:3a7713b1edbc 1097 {
AnnaBridge 171:3a7713b1edbc 1098 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 171:3a7713b1edbc 1099 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 171:3a7713b1edbc 1100 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 171:3a7713b1edbc 1101 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 171:3a7713b1edbc 1102 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 171:3a7713b1edbc 1103 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 171:3a7713b1edbc 1104 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 171:3a7713b1edbc 1105 } USB_OTG_OUTEndpointTypeDef;
AnnaBridge 171:3a7713b1edbc 1106
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 /**
AnnaBridge 171:3a7713b1edbc 1109 * @brief USB_OTG_Host_Mode_Register_Structures
AnnaBridge 171:3a7713b1edbc 1110 */
AnnaBridge 171:3a7713b1edbc 1111 typedef struct
AnnaBridge 171:3a7713b1edbc 1112 {
AnnaBridge 171:3a7713b1edbc 1113 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 171:3a7713b1edbc 1114 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 171:3a7713b1edbc 1115 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 171:3a7713b1edbc 1116 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 171:3a7713b1edbc 1117 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 171:3a7713b1edbc 1118 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 171:3a7713b1edbc 1119 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 171:3a7713b1edbc 1120 } USB_OTG_HostTypeDef;
AnnaBridge 171:3a7713b1edbc 1121
AnnaBridge 171:3a7713b1edbc 1122 /**
AnnaBridge 171:3a7713b1edbc 1123 * @brief USB_OTG_Host_Channel_Specific_Registers
AnnaBridge 171:3a7713b1edbc 1124 */
AnnaBridge 171:3a7713b1edbc 1125 typedef struct
AnnaBridge 171:3a7713b1edbc 1126 {
AnnaBridge 171:3a7713b1edbc 1127 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 171:3a7713b1edbc 1128 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 171:3a7713b1edbc 1129 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 171:3a7713b1edbc 1130 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 171:3a7713b1edbc 1131 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 171:3a7713b1edbc 1132 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 171:3a7713b1edbc 1133 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 1134 } USB_OTG_HostChannelTypeDef;
AnnaBridge 171:3a7713b1edbc 1135 /**
AnnaBridge 171:3a7713b1edbc 1136 * @}
AnnaBridge 171:3a7713b1edbc 1137 */
AnnaBridge 171:3a7713b1edbc 1138
AnnaBridge 171:3a7713b1edbc 1139
AnnaBridge 171:3a7713b1edbc 1140
AnnaBridge 171:3a7713b1edbc 1141
AnnaBridge 171:3a7713b1edbc 1142 /** @addtogroup Peripheral_memory_map
AnnaBridge 171:3a7713b1edbc 1143 * @{
AnnaBridge 171:3a7713b1edbc 1144 */
AnnaBridge 171:3a7713b1edbc 1145 #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
AnnaBridge 171:3a7713b1edbc 1146 #define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */
AnnaBridge 171:3a7713b1edbc 1147 #define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
AnnaBridge 171:3a7713b1edbc 1148 #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */
AnnaBridge 171:3a7713b1edbc 1149 #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
AnnaBridge 171:3a7713b1edbc 1150 #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
AnnaBridge 171:3a7713b1edbc 1151 #define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
AnnaBridge 171:3a7713b1edbc 1152 #define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
AnnaBridge 171:3a7713b1edbc 1153 #define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
AnnaBridge 171:3a7713b1edbc 1154 #define SRAM1_BASE 0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
AnnaBridge 171:3a7713b1edbc 1155 #define SRAM2_BASE 0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
AnnaBridge 171:3a7713b1edbc 1156 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
AnnaBridge 171:3a7713b1edbc 1157 #define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */
AnnaBridge 171:3a7713b1edbc 1158 #define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */
AnnaBridge 171:3a7713b1edbc 1159
AnnaBridge 171:3a7713b1edbc 1160 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 1161 #define FLASH_BASE FLASHAXI_BASE
AnnaBridge 171:3a7713b1edbc 1162
AnnaBridge 171:3a7713b1edbc 1163 /*!< Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 1164 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 171:3a7713b1edbc 1165 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 171:3a7713b1edbc 1166 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 171:3a7713b1edbc 1167 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
AnnaBridge 171:3a7713b1edbc 1168
AnnaBridge 171:3a7713b1edbc 1169 /*!< APB1 peripherals */
AnnaBridge 171:3a7713b1edbc 1170 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 1171 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
AnnaBridge 171:3a7713b1edbc 1172 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
AnnaBridge 171:3a7713b1edbc 1173 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
AnnaBridge 171:3a7713b1edbc 1174 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
AnnaBridge 171:3a7713b1edbc 1175 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
AnnaBridge 171:3a7713b1edbc 1176 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
AnnaBridge 171:3a7713b1edbc 1177 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
AnnaBridge 171:3a7713b1edbc 1178 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
AnnaBridge 171:3a7713b1edbc 1179 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
AnnaBridge 171:3a7713b1edbc 1180 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
AnnaBridge 171:3a7713b1edbc 1181 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
AnnaBridge 171:3a7713b1edbc 1182 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 1183 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
AnnaBridge 171:3a7713b1edbc 1184 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
AnnaBridge 171:3a7713b1edbc 1185 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
AnnaBridge 171:3a7713b1edbc 1186 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
AnnaBridge 171:3a7713b1edbc 1187 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
AnnaBridge 171:3a7713b1edbc 1188 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
AnnaBridge 171:3a7713b1edbc 1189 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
AnnaBridge 171:3a7713b1edbc 1190 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
AnnaBridge 171:3a7713b1edbc 1191 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
AnnaBridge 171:3a7713b1edbc 1192 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
AnnaBridge 171:3a7713b1edbc 1193 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
AnnaBridge 171:3a7713b1edbc 1194 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
AnnaBridge 171:3a7713b1edbc 1195 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
AnnaBridge 171:3a7713b1edbc 1196 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
AnnaBridge 171:3a7713b1edbc 1197 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
AnnaBridge 171:3a7713b1edbc 1198 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
AnnaBridge 171:3a7713b1edbc 1199 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
AnnaBridge 171:3a7713b1edbc 1200 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
AnnaBridge 171:3a7713b1edbc 1201
AnnaBridge 171:3a7713b1edbc 1202 /*!< APB2 peripherals */
AnnaBridge 171:3a7713b1edbc 1203 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 1204 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
AnnaBridge 171:3a7713b1edbc 1205 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
AnnaBridge 171:3a7713b1edbc 1206 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
AnnaBridge 171:3a7713b1edbc 1207 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
AnnaBridge 171:3a7713b1edbc 1208 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
AnnaBridge 171:3a7713b1edbc 1209 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
AnnaBridge 171:3a7713b1edbc 1210 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 171:3a7713b1edbc 1211 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
AnnaBridge 171:3a7713b1edbc 1212 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 1213 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
AnnaBridge 171:3a7713b1edbc 1214 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
AnnaBridge 171:3a7713b1edbc 1215 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
AnnaBridge 171:3a7713b1edbc 1216 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
AnnaBridge 171:3a7713b1edbc 1217 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
AnnaBridge 171:3a7713b1edbc 1218 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
AnnaBridge 171:3a7713b1edbc 1219 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
AnnaBridge 171:3a7713b1edbc 1220 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
AnnaBridge 171:3a7713b1edbc 1221 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
AnnaBridge 171:3a7713b1edbc 1222 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
AnnaBridge 171:3a7713b1edbc 1223 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
AnnaBridge 171:3a7713b1edbc 1224 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
AnnaBridge 171:3a7713b1edbc 1225 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
AnnaBridge 171:3a7713b1edbc 1226 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
AnnaBridge 171:3a7713b1edbc 1227 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
AnnaBridge 171:3a7713b1edbc 1228 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
AnnaBridge 171:3a7713b1edbc 1229 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
AnnaBridge 171:3a7713b1edbc 1230 /*!< AHB1 peripherals */
AnnaBridge 171:3a7713b1edbc 1231 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 1232 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
AnnaBridge 171:3a7713b1edbc 1233 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
AnnaBridge 171:3a7713b1edbc 1234 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
AnnaBridge 171:3a7713b1edbc 1235 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
AnnaBridge 171:3a7713b1edbc 1236 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
AnnaBridge 171:3a7713b1edbc 1237 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
AnnaBridge 171:3a7713b1edbc 1238 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
AnnaBridge 171:3a7713b1edbc 1239 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
AnnaBridge 171:3a7713b1edbc 1240 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
AnnaBridge 171:3a7713b1edbc 1241 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
AnnaBridge 171:3a7713b1edbc 1242 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
AnnaBridge 171:3a7713b1edbc 1243 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
AnnaBridge 171:3a7713b1edbc 1244 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
AnnaBridge 171:3a7713b1edbc 1245 #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
AnnaBridge 171:3a7713b1edbc 1246 #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
AnnaBridge 171:3a7713b1edbc 1247 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
AnnaBridge 171:3a7713b1edbc 1248 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 1249 #define PACKAGESIZE_BASE PACKAGE_BASE
AnnaBridge 171:3a7713b1edbc 1250
AnnaBridge 171:3a7713b1edbc 1251 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
AnnaBridge 171:3a7713b1edbc 1252 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
AnnaBridge 171:3a7713b1edbc 1253 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
AnnaBridge 171:3a7713b1edbc 1254 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
AnnaBridge 171:3a7713b1edbc 1255 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
AnnaBridge 171:3a7713b1edbc 1256 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
AnnaBridge 171:3a7713b1edbc 1257 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
AnnaBridge 171:3a7713b1edbc 1258 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
AnnaBridge 171:3a7713b1edbc 1259 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
AnnaBridge 171:3a7713b1edbc 1260 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
AnnaBridge 171:3a7713b1edbc 1261 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
AnnaBridge 171:3a7713b1edbc 1262 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
AnnaBridge 171:3a7713b1edbc 1263 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
AnnaBridge 171:3a7713b1edbc 1264 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
AnnaBridge 171:3a7713b1edbc 1265 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
AnnaBridge 171:3a7713b1edbc 1266 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
AnnaBridge 171:3a7713b1edbc 1267 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
AnnaBridge 171:3a7713b1edbc 1268 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
AnnaBridge 171:3a7713b1edbc 1269 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
AnnaBridge 171:3a7713b1edbc 1270 #define ETH_MAC_BASE (ETH_BASE)
AnnaBridge 171:3a7713b1edbc 1271 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
AnnaBridge 171:3a7713b1edbc 1272 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
AnnaBridge 171:3a7713b1edbc 1273 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
AnnaBridge 171:3a7713b1edbc 1274 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
AnnaBridge 171:3a7713b1edbc 1275 /*!< AHB2 peripherals */
AnnaBridge 171:3a7713b1edbc 1276 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
AnnaBridge 171:3a7713b1edbc 1277 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
AnnaBridge 171:3a7713b1edbc 1278 /*!< FMC Bankx registers base address */
AnnaBridge 171:3a7713b1edbc 1279 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
AnnaBridge 171:3a7713b1edbc 1280 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
AnnaBridge 171:3a7713b1edbc 1281 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
AnnaBridge 171:3a7713b1edbc 1282 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
AnnaBridge 171:3a7713b1edbc 1283
AnnaBridge 171:3a7713b1edbc 1284 /* Debug MCU registers base address */
AnnaBridge 171:3a7713b1edbc 1285 #define DBGMCU_BASE 0xE0042000U
AnnaBridge 171:3a7713b1edbc 1286
AnnaBridge 171:3a7713b1edbc 1287 /*!< USB registers base address */
AnnaBridge 171:3a7713b1edbc 1288 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
AnnaBridge 171:3a7713b1edbc 1289 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
AnnaBridge 171:3a7713b1edbc 1290
AnnaBridge 171:3a7713b1edbc 1291 #define USB_OTG_GLOBAL_BASE 0x000U
AnnaBridge 171:3a7713b1edbc 1292 #define USB_OTG_DEVICE_BASE 0x800U
AnnaBridge 171:3a7713b1edbc 1293 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
AnnaBridge 171:3a7713b1edbc 1294 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
AnnaBridge 171:3a7713b1edbc 1295 #define USB_OTG_EP_REG_SIZE 0x20U
AnnaBridge 171:3a7713b1edbc 1296 #define USB_OTG_HOST_BASE 0x400U
AnnaBridge 171:3a7713b1edbc 1297 #define USB_OTG_HOST_PORT_BASE 0x440U
AnnaBridge 171:3a7713b1edbc 1298 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
AnnaBridge 171:3a7713b1edbc 1299 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
AnnaBridge 171:3a7713b1edbc 1300 #define USB_OTG_PCGCCTL_BASE 0xE00U
AnnaBridge 171:3a7713b1edbc 1301 #define USB_OTG_FIFO_BASE 0x1000U
AnnaBridge 171:3a7713b1edbc 1302 #define USB_OTG_FIFO_SIZE 0x1000U
AnnaBridge 171:3a7713b1edbc 1303
AnnaBridge 171:3a7713b1edbc 1304 /**
AnnaBridge 171:3a7713b1edbc 1305 * @}
AnnaBridge 171:3a7713b1edbc 1306 */
AnnaBridge 171:3a7713b1edbc 1307
AnnaBridge 171:3a7713b1edbc 1308 /** @addtogroup Peripheral_declaration
AnnaBridge 171:3a7713b1edbc 1309 * @{
AnnaBridge 171:3a7713b1edbc 1310 */
AnnaBridge 171:3a7713b1edbc 1311 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 171:3a7713b1edbc 1312 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 171:3a7713b1edbc 1313 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
AnnaBridge 171:3a7713b1edbc 1314 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 171:3a7713b1edbc 1315 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 171:3a7713b1edbc 1316 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 171:3a7713b1edbc 1317 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
AnnaBridge 171:3a7713b1edbc 1318 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
AnnaBridge 171:3a7713b1edbc 1319 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
AnnaBridge 171:3a7713b1edbc 1320 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
AnnaBridge 171:3a7713b1edbc 1321 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 171:3a7713b1edbc 1322 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 171:3a7713b1edbc 1323 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 171:3a7713b1edbc 1324 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 171:3a7713b1edbc 1325 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 171:3a7713b1edbc 1326 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
AnnaBridge 171:3a7713b1edbc 1327 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 171:3a7713b1edbc 1328 #define USART3 ((USART_TypeDef *) USART3_BASE)
AnnaBridge 171:3a7713b1edbc 1329 #define UART4 ((USART_TypeDef *) UART4_BASE)
AnnaBridge 171:3a7713b1edbc 1330 #define UART5 ((USART_TypeDef *) UART5_BASE)
AnnaBridge 171:3a7713b1edbc 1331 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 1332 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 171:3a7713b1edbc 1333 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 171:3a7713b1edbc 1334 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
AnnaBridge 171:3a7713b1edbc 1335 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
AnnaBridge 171:3a7713b1edbc 1336 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
AnnaBridge 171:3a7713b1edbc 1337 #define CEC ((CEC_TypeDef *) CEC_BASE)
AnnaBridge 171:3a7713b1edbc 1338 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 171:3a7713b1edbc 1339 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 171:3a7713b1edbc 1340 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
AnnaBridge 171:3a7713b1edbc 1341 #define UART7 ((USART_TypeDef *) UART7_BASE)
AnnaBridge 171:3a7713b1edbc 1342 #define UART8 ((USART_TypeDef *) UART8_BASE)
AnnaBridge 171:3a7713b1edbc 1343 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 171:3a7713b1edbc 1344 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
AnnaBridge 171:3a7713b1edbc 1345 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 171:3a7713b1edbc 1346 #define USART6 ((USART_TypeDef *) USART6_BASE)
AnnaBridge 171:3a7713b1edbc 1347 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
AnnaBridge 171:3a7713b1edbc 1348 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 171:3a7713b1edbc 1349 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
AnnaBridge 171:3a7713b1edbc 1350 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
AnnaBridge 171:3a7713b1edbc 1351 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
AnnaBridge 171:3a7713b1edbc 1352 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
AnnaBridge 171:3a7713b1edbc 1353 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 1354 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
AnnaBridge 171:3a7713b1edbc 1355 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 171:3a7713b1edbc 1356 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 171:3a7713b1edbc 1357 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
AnnaBridge 171:3a7713b1edbc 1358 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
AnnaBridge 171:3a7713b1edbc 1359 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
AnnaBridge 171:3a7713b1edbc 1360 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
AnnaBridge 171:3a7713b1edbc 1361 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
AnnaBridge 171:3a7713b1edbc 1362 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
AnnaBridge 171:3a7713b1edbc 1363 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
AnnaBridge 171:3a7713b1edbc 1364 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
AnnaBridge 171:3a7713b1edbc 1365 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
AnnaBridge 171:3a7713b1edbc 1366 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
AnnaBridge 171:3a7713b1edbc 1367 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
AnnaBridge 171:3a7713b1edbc 1368 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
AnnaBridge 171:3a7713b1edbc 1369 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
AnnaBridge 171:3a7713b1edbc 1370 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
AnnaBridge 171:3a7713b1edbc 1371 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 1372 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 1373 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 1374 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 171:3a7713b1edbc 1375 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 171:3a7713b1edbc 1376 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
AnnaBridge 171:3a7713b1edbc 1377 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
AnnaBridge 171:3a7713b1edbc 1378 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 171:3a7713b1edbc 1379 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
AnnaBridge 171:3a7713b1edbc 1380 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
AnnaBridge 171:3a7713b1edbc 1381 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
AnnaBridge 171:3a7713b1edbc 1382 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 171:3a7713b1edbc 1383 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 171:3a7713b1edbc 1384 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 171:3a7713b1edbc 1385 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 171:3a7713b1edbc 1386 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
AnnaBridge 171:3a7713b1edbc 1387 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
AnnaBridge 171:3a7713b1edbc 1388 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
AnnaBridge 171:3a7713b1edbc 1389 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
AnnaBridge 171:3a7713b1edbc 1390 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
AnnaBridge 171:3a7713b1edbc 1391 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
AnnaBridge 171:3a7713b1edbc 1392 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
AnnaBridge 171:3a7713b1edbc 1393 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
AnnaBridge 171:3a7713b1edbc 1394 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 171:3a7713b1edbc 1395 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
AnnaBridge 171:3a7713b1edbc 1396 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
AnnaBridge 171:3a7713b1edbc 1397 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
AnnaBridge 171:3a7713b1edbc 1398 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
AnnaBridge 171:3a7713b1edbc 1399 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
AnnaBridge 171:3a7713b1edbc 1400 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
AnnaBridge 171:3a7713b1edbc 1401 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
AnnaBridge 171:3a7713b1edbc 1402 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
AnnaBridge 171:3a7713b1edbc 1403 #define ETH ((ETH_TypeDef *) ETH_BASE)
AnnaBridge 171:3a7713b1edbc 1404 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
AnnaBridge 171:3a7713b1edbc 1405 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
AnnaBridge 171:3a7713b1edbc 1406 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 171:3a7713b1edbc 1407 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
AnnaBridge 171:3a7713b1edbc 1408 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
AnnaBridge 171:3a7713b1edbc 1409 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
AnnaBridge 171:3a7713b1edbc 1410 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
AnnaBridge 171:3a7713b1edbc 1411 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
AnnaBridge 171:3a7713b1edbc 1412 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 171:3a7713b1edbc 1413 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
AnnaBridge 171:3a7713b1edbc 1414 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
AnnaBridge 171:3a7713b1edbc 1415
AnnaBridge 171:3a7713b1edbc 1416 /**
AnnaBridge 171:3a7713b1edbc 1417 * @}
AnnaBridge 171:3a7713b1edbc 1418 */
AnnaBridge 171:3a7713b1edbc 1419
AnnaBridge 171:3a7713b1edbc 1420 /** @addtogroup Exported_constants
AnnaBridge 171:3a7713b1edbc 1421 * @{
AnnaBridge 171:3a7713b1edbc 1422 */
AnnaBridge 171:3a7713b1edbc 1423
AnnaBridge 171:3a7713b1edbc 1424 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 171:3a7713b1edbc 1425 * @{
AnnaBridge 171:3a7713b1edbc 1426 */
AnnaBridge 171:3a7713b1edbc 1427
AnnaBridge 171:3a7713b1edbc 1428 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1429 /* Peripheral Registers_Bits_Definition */
AnnaBridge 171:3a7713b1edbc 1430 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1431
AnnaBridge 171:3a7713b1edbc 1432 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1433 /* */
AnnaBridge 171:3a7713b1edbc 1434 /* Analog to Digital Converter */
AnnaBridge 171:3a7713b1edbc 1435 /* */
AnnaBridge 171:3a7713b1edbc 1436 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1437 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 171:3a7713b1edbc 1438 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1439 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1440 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
AnnaBridge 171:3a7713b1edbc 1441 #define ADC_SR_EOC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1442 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1443 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
AnnaBridge 171:3a7713b1edbc 1444 #define ADC_SR_JEOC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1445 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1446 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
AnnaBridge 171:3a7713b1edbc 1447 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1448 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1449 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
AnnaBridge 171:3a7713b1edbc 1450 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1451 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1452 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
AnnaBridge 171:3a7713b1edbc 1453 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1454 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1455 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 171:3a7713b1edbc 1456
AnnaBridge 171:3a7713b1edbc 1457 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 1458 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1459 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1460 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 171:3a7713b1edbc 1461 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1462 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1463 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1464 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1465 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1466 #define ADC_CR1_EOCIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1467 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1468 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
AnnaBridge 171:3a7713b1edbc 1469 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1470 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1471 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 171:3a7713b1edbc 1472 #define ADC_CR1_JEOCIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1473 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1474 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
AnnaBridge 171:3a7713b1edbc 1475 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1476 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1477 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
AnnaBridge 171:3a7713b1edbc 1478 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1479 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1480 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 171:3a7713b1edbc 1481 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1482 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1483 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
AnnaBridge 171:3a7713b1edbc 1484 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1485 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1486 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
AnnaBridge 171:3a7713b1edbc 1487 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1488 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1489 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
AnnaBridge 171:3a7713b1edbc 1490 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1491 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 1492 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 171:3a7713b1edbc 1493 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1494 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1495 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1496 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1497 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1498 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
AnnaBridge 171:3a7713b1edbc 1499 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1500 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1501 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
AnnaBridge 171:3a7713b1edbc 1502 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1503 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 1504 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
AnnaBridge 171:3a7713b1edbc 1505 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1506 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1507 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1508 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1509 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
AnnaBridge 171:3a7713b1edbc 1510
AnnaBridge 171:3a7713b1edbc 1511 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 1512 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1513 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1514 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
AnnaBridge 171:3a7713b1edbc 1515 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1516 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1517 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
AnnaBridge 171:3a7713b1edbc 1518 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1519 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1520 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
AnnaBridge 171:3a7713b1edbc 1521 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1522 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1523 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
AnnaBridge 171:3a7713b1edbc 1524 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1525 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1526 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
AnnaBridge 171:3a7713b1edbc 1527 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1528 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1529 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
AnnaBridge 171:3a7713b1edbc 1530 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1531 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 1532 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 171:3a7713b1edbc 1533 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1534 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1535 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1536 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1537 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1538 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 1539 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 171:3a7713b1edbc 1540 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1541 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1542 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1543 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1544 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
AnnaBridge 171:3a7713b1edbc 1545 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1546 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 1547 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 171:3a7713b1edbc 1548 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1549 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1550 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1551 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1552 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 1553 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 1554 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 171:3a7713b1edbc 1555 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1556 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1557 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 171:3a7713b1edbc 1558 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1559 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
AnnaBridge 171:3a7713b1edbc 1560
AnnaBridge 171:3a7713b1edbc 1561 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1562 #define ADC_SMPR1_SMP10_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1563 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1564 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1565 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1566 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1567 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1568 #define ADC_SMPR1_SMP11_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1569 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1570 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1571 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1572 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1573 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1574 #define ADC_SMPR1_SMP12_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1575 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1576 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1577 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1578 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1579 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1580 #define ADC_SMPR1_SMP13_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1581 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1582 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1583 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1584 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1585 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1586 #define ADC_SMPR1_SMP14_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1587 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1588 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1589 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1590 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1591 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1592 #define ADC_SMPR1_SMP15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1593 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1594 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1595 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1596 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1597 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1598 #define ADC_SMPR1_SMP16_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1599 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1600 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1601 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1602 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1603 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1604 #define ADC_SMPR1_SMP17_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1605 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1606 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1607 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1608 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1609 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1610 #define ADC_SMPR1_SMP18_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1611 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 1612 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1613 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1614 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1615 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1616
AnnaBridge 171:3a7713b1edbc 1617 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1618 #define ADC_SMPR2_SMP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1619 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1620 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1621 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1622 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1623 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1624 #define ADC_SMPR2_SMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1625 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1626 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1627 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1628 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1629 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1630 #define ADC_SMPR2_SMP2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1631 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1632 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1633 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1634 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1635 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1636 #define ADC_SMPR2_SMP3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1637 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1638 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1639 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1640 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1641 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1642 #define ADC_SMPR2_SMP4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1643 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1644 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1645 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1646 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1647 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1648 #define ADC_SMPR2_SMP5_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1649 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1650 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1651 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1652 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1653 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1654 #define ADC_SMPR2_SMP6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1655 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1656 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1657 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1658 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1659 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1660 #define ADC_SMPR2_SMP7_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1661 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1662 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1663 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1664 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1665 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1666 #define ADC_SMPR2_SMP8_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1667 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 1668 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1669 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1670 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1671 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1672 #define ADC_SMPR2_SMP9_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1673 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 171:3a7713b1edbc 1674 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 171:3a7713b1edbc 1675 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1676 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1677 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1678
AnnaBridge 171:3a7713b1edbc 1679 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1680 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1681 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1682 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
AnnaBridge 171:3a7713b1edbc 1683
AnnaBridge 171:3a7713b1edbc 1684 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1685 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1686 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1687 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
AnnaBridge 171:3a7713b1edbc 1688
AnnaBridge 171:3a7713b1edbc 1689 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1690 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1691 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1692 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
AnnaBridge 171:3a7713b1edbc 1693
AnnaBridge 171:3a7713b1edbc 1694 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 171:3a7713b1edbc 1695 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1696 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1697 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
AnnaBridge 171:3a7713b1edbc 1698
AnnaBridge 171:3a7713b1edbc 1699 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 171:3a7713b1edbc 1700 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1701 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1702 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
AnnaBridge 171:3a7713b1edbc 1703
AnnaBridge 171:3a7713b1edbc 1704 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 171:3a7713b1edbc 1705 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1706 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1707 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
AnnaBridge 171:3a7713b1edbc 1708
AnnaBridge 171:3a7713b1edbc 1709 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1710 #define ADC_SQR1_SQ13_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1711 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1712 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1713 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1714 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1715 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1716 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1717 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1718 #define ADC_SQR1_SQ14_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1719 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1720 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1721 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1722 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1723 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1724 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1725 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1726 #define ADC_SQR1_SQ15_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1727 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1728 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1729 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1730 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1731 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1732 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1733 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1734 #define ADC_SQR1_SQ16_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1735 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1736 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1737 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1738 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1739 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1740 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1741 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1742 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1743 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 1744 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 171:3a7713b1edbc 1745 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1746 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1747 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1748 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1749
AnnaBridge 171:3a7713b1edbc 1750 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1751 #define ADC_SQR2_SQ7_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1752 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1753 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1754 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1755 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1756 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1757 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1758 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1759 #define ADC_SQR2_SQ8_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1760 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1761 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1762 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1763 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1764 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1765 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1766 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1767 #define ADC_SQR2_SQ9_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1768 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1769 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1770 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1771 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1772 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1773 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1774 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1775 #define ADC_SQR2_SQ10_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1776 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1777 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1778 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1779 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1780 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1781 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1782 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1783 #define ADC_SQR2_SQ11_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1784 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1785 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1786 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1787 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1788 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1789 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1790 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1791 #define ADC_SQR2_SQ12_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1792 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 171:3a7713b1edbc 1793 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1794 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1795 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1796 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1797 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1798 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1799
AnnaBridge 171:3a7713b1edbc 1800 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1801 #define ADC_SQR3_SQ1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1802 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1803 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1804 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1805 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1806 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1807 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1808 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1809 #define ADC_SQR3_SQ2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1810 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1811 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1812 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1813 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1814 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1815 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1816 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1817 #define ADC_SQR3_SQ3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1818 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1819 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1820 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1821 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1822 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1823 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1824 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1825 #define ADC_SQR3_SQ4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1826 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1827 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1828 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1829 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1830 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1831 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1832 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1833 #define ADC_SQR3_SQ5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1834 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1835 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1836 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1837 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1838 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1839 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1840 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1841 #define ADC_SQR3_SQ6_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1842 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 171:3a7713b1edbc 1843 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 171:3a7713b1edbc 1844 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1845 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1846 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1847 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1848 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1849
AnnaBridge 171:3a7713b1edbc 1850 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 171:3a7713b1edbc 1851 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1852 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1853 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 171:3a7713b1edbc 1854 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1855 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1856 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1857 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1858 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1859 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1860 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1861 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 171:3a7713b1edbc 1862 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1863 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1864 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1865 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1866 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1867 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1868 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1869 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 171:3a7713b1edbc 1870 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1871 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1872 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1873 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1874 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1875 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1876 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1877 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 171:3a7713b1edbc 1878 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1879 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1880 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1881 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1882 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1883 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1884 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 1885 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 171:3a7713b1edbc 1886 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1887 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1888
AnnaBridge 171:3a7713b1edbc 1889 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1890 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
AnnaBridge 171:3a7713b1edbc 1891
AnnaBridge 171:3a7713b1edbc 1892 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1893 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
AnnaBridge 171:3a7713b1edbc 1894
AnnaBridge 171:3a7713b1edbc 1895 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1896 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
AnnaBridge 171:3a7713b1edbc 1897
AnnaBridge 171:3a7713b1edbc 1898 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 171:3a7713b1edbc 1899 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
AnnaBridge 171:3a7713b1edbc 1900
AnnaBridge 171:3a7713b1edbc 1901 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 171:3a7713b1edbc 1902 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1903 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1904 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
AnnaBridge 171:3a7713b1edbc 1905 #define ADC_DR_ADC2DATA_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1906 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 1907 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
AnnaBridge 171:3a7713b1edbc 1908
AnnaBridge 171:3a7713b1edbc 1909 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 171:3a7713b1edbc 1910 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1911 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1912 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
AnnaBridge 171:3a7713b1edbc 1913 #define ADC_CSR_EOC1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1914 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1915 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
AnnaBridge 171:3a7713b1edbc 1916 #define ADC_CSR_JEOC1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1917 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1918 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
AnnaBridge 171:3a7713b1edbc 1919 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1920 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1921 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
AnnaBridge 171:3a7713b1edbc 1922 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1923 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1924 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
AnnaBridge 171:3a7713b1edbc 1925 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1926 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1927 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */
AnnaBridge 171:3a7713b1edbc 1928 #define ADC_CSR_AWD2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1929 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1930 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
AnnaBridge 171:3a7713b1edbc 1931 #define ADC_CSR_EOC2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1932 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1933 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
AnnaBridge 171:3a7713b1edbc 1934 #define ADC_CSR_JEOC2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1935 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1936 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
AnnaBridge 171:3a7713b1edbc 1937 #define ADC_CSR_JSTRT2_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1938 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1939 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
AnnaBridge 171:3a7713b1edbc 1940 #define ADC_CSR_STRT2_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1941 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1942 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
AnnaBridge 171:3a7713b1edbc 1943 #define ADC_CSR_OVR2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1944 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1945 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */
AnnaBridge 171:3a7713b1edbc 1946 #define ADC_CSR_AWD3_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1947 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1948 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
AnnaBridge 171:3a7713b1edbc 1949 #define ADC_CSR_EOC3_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1950 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1951 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
AnnaBridge 171:3a7713b1edbc 1952 #define ADC_CSR_JEOC3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1953 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1954 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
AnnaBridge 171:3a7713b1edbc 1955 #define ADC_CSR_JSTRT3_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1956 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1957 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
AnnaBridge 171:3a7713b1edbc 1958 #define ADC_CSR_STRT3_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1959 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1960 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
AnnaBridge 171:3a7713b1edbc 1961 #define ADC_CSR_OVR3_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1962 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1963 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */
AnnaBridge 171:3a7713b1edbc 1964
AnnaBridge 171:3a7713b1edbc 1965 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 1966 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
AnnaBridge 171:3a7713b1edbc 1967 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
AnnaBridge 171:3a7713b1edbc 1968 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
AnnaBridge 171:3a7713b1edbc 1969
AnnaBridge 171:3a7713b1edbc 1970
AnnaBridge 171:3a7713b1edbc 1971 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 1972 #define ADC_CCR_MULTI_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1973 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1974 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 171:3a7713b1edbc 1975 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1976 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1977 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1978 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1979 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1980 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1981 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 1982 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 171:3a7713b1edbc 1983 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1984 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1985 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1986 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1987 #define ADC_CCR_DDS_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1988 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1989 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 171:3a7713b1edbc 1990 #define ADC_CCR_DMA_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1991 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 1992 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 171:3a7713b1edbc 1993 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1994 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1995 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1996 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 1997 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 171:3a7713b1edbc 1998 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1999 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2000 #define ADC_CCR_VBATE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2001 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2002 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
AnnaBridge 171:3a7713b1edbc 2003 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2004 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2005 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
AnnaBridge 171:3a7713b1edbc 2006
AnnaBridge 171:3a7713b1edbc 2007 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 171:3a7713b1edbc 2008 #define ADC_CDR_DATA1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2009 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2010 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
AnnaBridge 171:3a7713b1edbc 2011 #define ADC_CDR_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2012 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2013 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
AnnaBridge 171:3a7713b1edbc 2014
AnnaBridge 171:3a7713b1edbc 2015 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 2016 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
AnnaBridge 171:3a7713b1edbc 2017 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
AnnaBridge 171:3a7713b1edbc 2018
AnnaBridge 171:3a7713b1edbc 2019 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2020 /* */
AnnaBridge 171:3a7713b1edbc 2021 /* Controller Area Network */
AnnaBridge 171:3a7713b1edbc 2022 /* */
AnnaBridge 171:3a7713b1edbc 2023 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2024 /*!<CAN control and status registers */
AnnaBridge 171:3a7713b1edbc 2025 /******************* Bit definition for CAN_MCR register ********************/
AnnaBridge 171:3a7713b1edbc 2026 #define CAN_MCR_INRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2027 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2028 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
AnnaBridge 171:3a7713b1edbc 2029 #define CAN_MCR_SLEEP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2030 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2031 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
AnnaBridge 171:3a7713b1edbc 2032 #define CAN_MCR_TXFP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2033 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2034 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
AnnaBridge 171:3a7713b1edbc 2035 #define CAN_MCR_RFLM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2036 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2037 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
AnnaBridge 171:3a7713b1edbc 2038 #define CAN_MCR_NART_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2039 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2040 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
AnnaBridge 171:3a7713b1edbc 2041 #define CAN_MCR_AWUM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2042 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2043 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
AnnaBridge 171:3a7713b1edbc 2044 #define CAN_MCR_ABOM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2045 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2046 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
AnnaBridge 171:3a7713b1edbc 2047 #define CAN_MCR_TTCM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2048 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2049 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
AnnaBridge 171:3a7713b1edbc 2050 #define CAN_MCR_RESET_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2051 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2052 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
AnnaBridge 171:3a7713b1edbc 2053
AnnaBridge 171:3a7713b1edbc 2054 /******************* Bit definition for CAN_MSR register ********************/
AnnaBridge 171:3a7713b1edbc 2055 #define CAN_MSR_INAK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2056 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2057 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
AnnaBridge 171:3a7713b1edbc 2058 #define CAN_MSR_SLAK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2059 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2060 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
AnnaBridge 171:3a7713b1edbc 2061 #define CAN_MSR_ERRI_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2062 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2063 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
AnnaBridge 171:3a7713b1edbc 2064 #define CAN_MSR_WKUI_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2065 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2066 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 2067 #define CAN_MSR_SLAKI_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2068 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2069 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
AnnaBridge 171:3a7713b1edbc 2070 #define CAN_MSR_TXM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2071 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2072 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
AnnaBridge 171:3a7713b1edbc 2073 #define CAN_MSR_RXM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2074 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2075 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
AnnaBridge 171:3a7713b1edbc 2076 #define CAN_MSR_SAMP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2077 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2078 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
AnnaBridge 171:3a7713b1edbc 2079 #define CAN_MSR_RX_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2080 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2081 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
AnnaBridge 171:3a7713b1edbc 2082
AnnaBridge 171:3a7713b1edbc 2083 /******************* Bit definition for CAN_TSR register ********************/
AnnaBridge 171:3a7713b1edbc 2084 #define CAN_TSR_RQCP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2085 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2086 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2087 #define CAN_TSR_TXOK0_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2088 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2089 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2090 #define CAN_TSR_ALST0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2091 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2092 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2093 #define CAN_TSR_TERR0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2094 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2095 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2096 #define CAN_TSR_ABRQ0_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2097 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2098 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2099 #define CAN_TSR_RQCP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2100 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2101 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2102 #define CAN_TSR_TXOK1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2103 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2104 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2105 #define CAN_TSR_ALST1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2106 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2107 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2108 #define CAN_TSR_TERR1_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2109 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2110 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2111 #define CAN_TSR_ABRQ1_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2112 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2113 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
AnnaBridge 171:3a7713b1edbc 2114 #define CAN_TSR_RQCP2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2115 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2116 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
AnnaBridge 171:3a7713b1edbc 2117 #define CAN_TSR_TXOK2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2118 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2119 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2120 #define CAN_TSR_ALST2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2121 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2122 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2123 #define CAN_TSR_TERR2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2124 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2125 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2126 #define CAN_TSR_ABRQ2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2127 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2128 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2129 #define CAN_TSR_CODE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2130 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2131 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
AnnaBridge 171:3a7713b1edbc 2132
AnnaBridge 171:3a7713b1edbc 2133 #define CAN_TSR_TME_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2134 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
AnnaBridge 171:3a7713b1edbc 2135 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
AnnaBridge 171:3a7713b1edbc 2136 #define CAN_TSR_TME0_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2137 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2138 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
AnnaBridge 171:3a7713b1edbc 2139 #define CAN_TSR_TME1_Pos (27U)
AnnaBridge 171:3a7713b1edbc 2140 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2141 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
AnnaBridge 171:3a7713b1edbc 2142 #define CAN_TSR_TME2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2143 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2144 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
AnnaBridge 171:3a7713b1edbc 2145
AnnaBridge 171:3a7713b1edbc 2146 #define CAN_TSR_LOW_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2147 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
AnnaBridge 171:3a7713b1edbc 2148 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
AnnaBridge 171:3a7713b1edbc 2149 #define CAN_TSR_LOW0_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2150 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2151 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
AnnaBridge 171:3a7713b1edbc 2152 #define CAN_TSR_LOW1_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2153 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2154 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
AnnaBridge 171:3a7713b1edbc 2155 #define CAN_TSR_LOW2_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2156 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2157 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2158
AnnaBridge 171:3a7713b1edbc 2159 /******************* Bit definition for CAN_RF0R register *******************/
AnnaBridge 171:3a7713b1edbc 2160 #define CAN_RF0R_FMP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2161 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2162 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
AnnaBridge 171:3a7713b1edbc 2163 #define CAN_RF0R_FULL0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2164 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2165 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
AnnaBridge 171:3a7713b1edbc 2166 #define CAN_RF0R_FOVR0_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2167 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2168 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
AnnaBridge 171:3a7713b1edbc 2169 #define CAN_RF0R_RFOM0_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2170 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2171 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
AnnaBridge 171:3a7713b1edbc 2172
AnnaBridge 171:3a7713b1edbc 2173 /******************* Bit definition for CAN_RF1R register *******************/
AnnaBridge 171:3a7713b1edbc 2174 #define CAN_RF1R_FMP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2175 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2176 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
AnnaBridge 171:3a7713b1edbc 2177 #define CAN_RF1R_FULL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2178 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2179 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
AnnaBridge 171:3a7713b1edbc 2180 #define CAN_RF1R_FOVR1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2181 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2182 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
AnnaBridge 171:3a7713b1edbc 2183 #define CAN_RF1R_RFOM1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2184 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2185 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
AnnaBridge 171:3a7713b1edbc 2186
AnnaBridge 171:3a7713b1edbc 2187 /******************** Bit definition for CAN_IER register *******************/
AnnaBridge 171:3a7713b1edbc 2188 #define CAN_IER_TMEIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2189 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2190 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2191 #define CAN_IER_FMPIE0_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2192 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2193 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2194 #define CAN_IER_FFIE0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2195 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2196 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2197 #define CAN_IER_FOVIE0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2198 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2199 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2200 #define CAN_IER_FMPIE1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2201 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2202 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2203 #define CAN_IER_FFIE1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2204 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2205 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2206 #define CAN_IER_FOVIE1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2207 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2208 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2209 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2210 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2211 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2212 #define CAN_IER_EPVIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2213 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2214 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2215 #define CAN_IER_BOFIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2216 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2217 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2218 #define CAN_IER_LECIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2219 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2220 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2221 #define CAN_IER_ERRIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2222 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2223 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2224 #define CAN_IER_WKUIE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2225 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2226 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2227 #define CAN_IER_SLKIE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2228 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2229 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2230
AnnaBridge 171:3a7713b1edbc 2231 /******************** Bit definition for CAN_ESR register *******************/
AnnaBridge 171:3a7713b1edbc 2232 #define CAN_ESR_EWGF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2233 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2234 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
AnnaBridge 171:3a7713b1edbc 2235 #define CAN_ESR_EPVF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2236 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2237 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
AnnaBridge 171:3a7713b1edbc 2238 #define CAN_ESR_BOFF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2239 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2240 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
AnnaBridge 171:3a7713b1edbc 2241
AnnaBridge 171:3a7713b1edbc 2242 #define CAN_ESR_LEC_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2243 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 2244 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
AnnaBridge 171:3a7713b1edbc 2245 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2246 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2247 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2248
AnnaBridge 171:3a7713b1edbc 2249 #define CAN_ESR_TEC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2250 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2251 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
AnnaBridge 171:3a7713b1edbc 2252 #define CAN_ESR_REC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2253 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2254 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
AnnaBridge 171:3a7713b1edbc 2255
AnnaBridge 171:3a7713b1edbc 2256 /******************* Bit definition for CAN_BTR register ********************/
AnnaBridge 171:3a7713b1edbc 2257 #define CAN_BTR_BRP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2258 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 2259 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
AnnaBridge 171:3a7713b1edbc 2260 #define CAN_BTR_TS1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2261 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 2262 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
AnnaBridge 171:3a7713b1edbc 2263 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2264 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2265 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2266 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2267 #define CAN_BTR_TS2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2268 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
AnnaBridge 171:3a7713b1edbc 2269 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
AnnaBridge 171:3a7713b1edbc 2270 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2271 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2272 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2273 #define CAN_BTR_SJW_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2274 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2275 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
AnnaBridge 171:3a7713b1edbc 2276 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2277 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2278 #define CAN_BTR_LBKM_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2279 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2280 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
AnnaBridge 171:3a7713b1edbc 2281 #define CAN_BTR_SILM_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2282 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2283 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
AnnaBridge 171:3a7713b1edbc 2284
AnnaBridge 171:3a7713b1edbc 2285 /*!<Mailbox registers */
AnnaBridge 171:3a7713b1edbc 2286 /****************** Bit definition for CAN_TI0R register ********************/
AnnaBridge 171:3a7713b1edbc 2287 #define CAN_TI0R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2288 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2289 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2290 #define CAN_TI0R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2291 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2292 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2293 #define CAN_TI0R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2294 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2295 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2296 #define CAN_TI0R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2297 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2298 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2299 #define CAN_TI0R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2300 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2301 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2302
AnnaBridge 171:3a7713b1edbc 2303 /****************** Bit definition for CAN_TDT0R register *******************/
AnnaBridge 171:3a7713b1edbc 2304 #define CAN_TDT0R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2305 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2306 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2307 #define CAN_TDT0R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2308 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2309 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2310 #define CAN_TDT0R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2311 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2312 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2313
AnnaBridge 171:3a7713b1edbc 2314 /****************** Bit definition for CAN_TDL0R register *******************/
AnnaBridge 171:3a7713b1edbc 2315 #define CAN_TDL0R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2316 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2317 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2318 #define CAN_TDL0R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2319 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2320 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2321 #define CAN_TDL0R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2322 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2323 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2324 #define CAN_TDL0R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2325 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2326 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2327
AnnaBridge 171:3a7713b1edbc 2328 /****************** Bit definition for CAN_TDH0R register *******************/
AnnaBridge 171:3a7713b1edbc 2329 #define CAN_TDH0R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2330 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2331 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2332 #define CAN_TDH0R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2333 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2334 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2335 #define CAN_TDH0R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2336 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2337 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2338 #define CAN_TDH0R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2339 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2340 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2341
AnnaBridge 171:3a7713b1edbc 2342 /******************* Bit definition for CAN_TI1R register *******************/
AnnaBridge 171:3a7713b1edbc 2343 #define CAN_TI1R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2344 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2345 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2346 #define CAN_TI1R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2347 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2348 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2349 #define CAN_TI1R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2350 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2351 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2352 #define CAN_TI1R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2353 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2354 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2355 #define CAN_TI1R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2356 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2357 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2358
AnnaBridge 171:3a7713b1edbc 2359 /******************* Bit definition for CAN_TDT1R register ******************/
AnnaBridge 171:3a7713b1edbc 2360 #define CAN_TDT1R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2361 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2362 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2363 #define CAN_TDT1R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2364 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2365 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2366 #define CAN_TDT1R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2367 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2368 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2369
AnnaBridge 171:3a7713b1edbc 2370 /******************* Bit definition for CAN_TDL1R register ******************/
AnnaBridge 171:3a7713b1edbc 2371 #define CAN_TDL1R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2372 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2373 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2374 #define CAN_TDL1R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2375 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2376 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2377 #define CAN_TDL1R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2378 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2379 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2380 #define CAN_TDL1R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2381 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2382 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2383
AnnaBridge 171:3a7713b1edbc 2384 /******************* Bit definition for CAN_TDH1R register ******************/
AnnaBridge 171:3a7713b1edbc 2385 #define CAN_TDH1R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2386 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2387 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2388 #define CAN_TDH1R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2389 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2390 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2391 #define CAN_TDH1R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2392 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2393 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2394 #define CAN_TDH1R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2395 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2396 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2397
AnnaBridge 171:3a7713b1edbc 2398 /******************* Bit definition for CAN_TI2R register *******************/
AnnaBridge 171:3a7713b1edbc 2399 #define CAN_TI2R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2400 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2401 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2402 #define CAN_TI2R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2403 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2404 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2405 #define CAN_TI2R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2406 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2407 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2408 #define CAN_TI2R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2409 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2410 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
AnnaBridge 171:3a7713b1edbc 2411 #define CAN_TI2R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2412 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2413 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2414
AnnaBridge 171:3a7713b1edbc 2415 /******************* Bit definition for CAN_TDT2R register ******************/
AnnaBridge 171:3a7713b1edbc 2416 #define CAN_TDT2R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2417 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2418 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2419 #define CAN_TDT2R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2420 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2421 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2422 #define CAN_TDT2R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2423 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2424 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2425
AnnaBridge 171:3a7713b1edbc 2426 /******************* Bit definition for CAN_TDL2R register ******************/
AnnaBridge 171:3a7713b1edbc 2427 #define CAN_TDL2R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2428 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2429 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2430 #define CAN_TDL2R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2431 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2432 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2433 #define CAN_TDL2R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2434 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2435 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2436 #define CAN_TDL2R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2437 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2438 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2439
AnnaBridge 171:3a7713b1edbc 2440 /******************* Bit definition for CAN_TDH2R register ******************/
AnnaBridge 171:3a7713b1edbc 2441 #define CAN_TDH2R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2442 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2443 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2444 #define CAN_TDH2R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2445 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2446 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2447 #define CAN_TDH2R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2448 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2449 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2450 #define CAN_TDH2R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2451 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2452 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2453
AnnaBridge 171:3a7713b1edbc 2454 /******************* Bit definition for CAN_RI0R register *******************/
AnnaBridge 171:3a7713b1edbc 2455 #define CAN_RI0R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2456 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2457 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2458 #define CAN_RI0R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2459 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2460 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2461 #define CAN_RI0R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2462 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2463 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2464 #define CAN_RI0R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2465 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2466 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2467
AnnaBridge 171:3a7713b1edbc 2468 /******************* Bit definition for CAN_RDT0R register ******************/
AnnaBridge 171:3a7713b1edbc 2469 #define CAN_RDT0R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2470 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2471 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2472 #define CAN_RDT0R_FMI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2473 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2474 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 171:3a7713b1edbc 2475 #define CAN_RDT0R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2476 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2477 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2478
AnnaBridge 171:3a7713b1edbc 2479 /******************* Bit definition for CAN_RDL0R register ******************/
AnnaBridge 171:3a7713b1edbc 2480 #define CAN_RDL0R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2481 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2482 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2483 #define CAN_RDL0R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2484 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2485 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2486 #define CAN_RDL0R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2487 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2488 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2489 #define CAN_RDL0R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2490 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2491 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2492
AnnaBridge 171:3a7713b1edbc 2493 /******************* Bit definition for CAN_RDH0R register ******************/
AnnaBridge 171:3a7713b1edbc 2494 #define CAN_RDH0R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2495 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2496 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2497 #define CAN_RDH0R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2498 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2499 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2500 #define CAN_RDH0R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2501 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2502 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2503 #define CAN_RDH0R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2504 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2505 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2506
AnnaBridge 171:3a7713b1edbc 2507 /******************* Bit definition for CAN_RI1R register *******************/
AnnaBridge 171:3a7713b1edbc 2508 #define CAN_RI1R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2509 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2510 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2511 #define CAN_RI1R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2512 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2513 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2514 #define CAN_RI1R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2515 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2516 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
AnnaBridge 171:3a7713b1edbc 2517 #define CAN_RI1R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2518 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2519 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2520
AnnaBridge 171:3a7713b1edbc 2521 /******************* Bit definition for CAN_RDT1R register ******************/
AnnaBridge 171:3a7713b1edbc 2522 #define CAN_RDT1R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2523 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2524 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2525 #define CAN_RDT1R_FMI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2526 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2527 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 171:3a7713b1edbc 2528 #define CAN_RDT1R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2529 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2530 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2531
AnnaBridge 171:3a7713b1edbc 2532 /******************* Bit definition for CAN_RDL1R register ******************/
AnnaBridge 171:3a7713b1edbc 2533 #define CAN_RDL1R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2534 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2535 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2536 #define CAN_RDL1R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2537 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2538 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2539 #define CAN_RDL1R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2540 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2541 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2542 #define CAN_RDL1R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2543 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2544 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2545
AnnaBridge 171:3a7713b1edbc 2546 /******************* Bit definition for CAN_RDH1R register ******************/
AnnaBridge 171:3a7713b1edbc 2547 #define CAN_RDH1R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2548 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2549 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2550 #define CAN_RDH1R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2551 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2552 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2553 #define CAN_RDH1R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2554 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2555 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2556 #define CAN_RDH1R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2557 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2558 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2559
AnnaBridge 171:3a7713b1edbc 2560 /*!<CAN filter registers */
AnnaBridge 171:3a7713b1edbc 2561 /******************* Bit definition for CAN_FMR register ********************/
AnnaBridge 171:3a7713b1edbc 2562 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
AnnaBridge 171:3a7713b1edbc 2563 #define CAN_FMR_CAN2SB_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2564 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
AnnaBridge 171:3a7713b1edbc 2565 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
AnnaBridge 171:3a7713b1edbc 2566
AnnaBridge 171:3a7713b1edbc 2567 /******************* Bit definition for CAN_FM1R register *******************/
AnnaBridge 171:3a7713b1edbc 2568 #define CAN_FM1R_FBM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2569 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 2570 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
AnnaBridge 171:3a7713b1edbc 2571 #define CAN_FM1R_FBM0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2572 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2573 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
AnnaBridge 171:3a7713b1edbc 2574 #define CAN_FM1R_FBM1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2575 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2576 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
AnnaBridge 171:3a7713b1edbc 2577 #define CAN_FM1R_FBM2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2578 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2579 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
AnnaBridge 171:3a7713b1edbc 2580 #define CAN_FM1R_FBM3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2581 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2582 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
AnnaBridge 171:3a7713b1edbc 2583 #define CAN_FM1R_FBM4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2584 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2585 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
AnnaBridge 171:3a7713b1edbc 2586 #define CAN_FM1R_FBM5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2587 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2588 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
AnnaBridge 171:3a7713b1edbc 2589 #define CAN_FM1R_FBM6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2590 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2591 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
AnnaBridge 171:3a7713b1edbc 2592 #define CAN_FM1R_FBM7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2593 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2594 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
AnnaBridge 171:3a7713b1edbc 2595 #define CAN_FM1R_FBM8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2596 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2597 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
AnnaBridge 171:3a7713b1edbc 2598 #define CAN_FM1R_FBM9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2599 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2600 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
AnnaBridge 171:3a7713b1edbc 2601 #define CAN_FM1R_FBM10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2602 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2603 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
AnnaBridge 171:3a7713b1edbc 2604 #define CAN_FM1R_FBM11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2605 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2606 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
AnnaBridge 171:3a7713b1edbc 2607 #define CAN_FM1R_FBM12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2608 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2609 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
AnnaBridge 171:3a7713b1edbc 2610 #define CAN_FM1R_FBM13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2611 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2612 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
AnnaBridge 171:3a7713b1edbc 2613
AnnaBridge 171:3a7713b1edbc 2614 /******************* Bit definition for CAN_FS1R register *******************/
AnnaBridge 171:3a7713b1edbc 2615 #define CAN_FS1R_FSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2616 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 2617 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
AnnaBridge 171:3a7713b1edbc 2618 #define CAN_FS1R_FSC0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2619 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2620 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
AnnaBridge 171:3a7713b1edbc 2621 #define CAN_FS1R_FSC1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2622 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2623 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
AnnaBridge 171:3a7713b1edbc 2624 #define CAN_FS1R_FSC2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2625 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2626 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
AnnaBridge 171:3a7713b1edbc 2627 #define CAN_FS1R_FSC3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2628 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2629 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
AnnaBridge 171:3a7713b1edbc 2630 #define CAN_FS1R_FSC4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2631 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2632 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
AnnaBridge 171:3a7713b1edbc 2633 #define CAN_FS1R_FSC5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2634 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2635 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
AnnaBridge 171:3a7713b1edbc 2636 #define CAN_FS1R_FSC6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2637 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2638 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
AnnaBridge 171:3a7713b1edbc 2639 #define CAN_FS1R_FSC7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2640 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2641 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
AnnaBridge 171:3a7713b1edbc 2642 #define CAN_FS1R_FSC8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2643 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2644 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
AnnaBridge 171:3a7713b1edbc 2645 #define CAN_FS1R_FSC9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2646 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2647 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
AnnaBridge 171:3a7713b1edbc 2648 #define CAN_FS1R_FSC10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2649 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2650 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
AnnaBridge 171:3a7713b1edbc 2651 #define CAN_FS1R_FSC11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2652 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2653 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
AnnaBridge 171:3a7713b1edbc 2654 #define CAN_FS1R_FSC12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2655 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2656 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
AnnaBridge 171:3a7713b1edbc 2657 #define CAN_FS1R_FSC13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2658 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2659 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
AnnaBridge 171:3a7713b1edbc 2660
AnnaBridge 171:3a7713b1edbc 2661 /****************** Bit definition for CAN_FFA1R register *******************/
AnnaBridge 171:3a7713b1edbc 2662 #define CAN_FFA1R_FFA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2663 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 2664 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
AnnaBridge 171:3a7713b1edbc 2665 #define CAN_FFA1R_FFA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2666 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2667 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
AnnaBridge 171:3a7713b1edbc 2668 #define CAN_FFA1R_FFA1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2669 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2670 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
AnnaBridge 171:3a7713b1edbc 2671 #define CAN_FFA1R_FFA2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2672 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2673 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
AnnaBridge 171:3a7713b1edbc 2674 #define CAN_FFA1R_FFA3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2675 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2676 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
AnnaBridge 171:3a7713b1edbc 2677 #define CAN_FFA1R_FFA4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2678 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2679 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
AnnaBridge 171:3a7713b1edbc 2680 #define CAN_FFA1R_FFA5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2681 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2682 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
AnnaBridge 171:3a7713b1edbc 2683 #define CAN_FFA1R_FFA6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2684 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2685 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
AnnaBridge 171:3a7713b1edbc 2686 #define CAN_FFA1R_FFA7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2687 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2688 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
AnnaBridge 171:3a7713b1edbc 2689 #define CAN_FFA1R_FFA8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2690 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2691 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
AnnaBridge 171:3a7713b1edbc 2692 #define CAN_FFA1R_FFA9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2693 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2694 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
AnnaBridge 171:3a7713b1edbc 2695 #define CAN_FFA1R_FFA10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2696 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2697 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
AnnaBridge 171:3a7713b1edbc 2698 #define CAN_FFA1R_FFA11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2699 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2700 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
AnnaBridge 171:3a7713b1edbc 2701 #define CAN_FFA1R_FFA12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2702 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2703 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
AnnaBridge 171:3a7713b1edbc 2704 #define CAN_FFA1R_FFA13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2705 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2706 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
AnnaBridge 171:3a7713b1edbc 2707
AnnaBridge 171:3a7713b1edbc 2708 /******************* Bit definition for CAN_FA1R register *******************/
AnnaBridge 171:3a7713b1edbc 2709 #define CAN_FA1R_FACT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2710 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 2711 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
AnnaBridge 171:3a7713b1edbc 2712 #define CAN_FA1R_FACT0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2713 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2714 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
AnnaBridge 171:3a7713b1edbc 2715 #define CAN_FA1R_FACT1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2716 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2717 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
AnnaBridge 171:3a7713b1edbc 2718 #define CAN_FA1R_FACT2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2719 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2720 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
AnnaBridge 171:3a7713b1edbc 2721 #define CAN_FA1R_FACT3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2722 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2723 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
AnnaBridge 171:3a7713b1edbc 2724 #define CAN_FA1R_FACT4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2725 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2726 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
AnnaBridge 171:3a7713b1edbc 2727 #define CAN_FA1R_FACT5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2728 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2729 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
AnnaBridge 171:3a7713b1edbc 2730 #define CAN_FA1R_FACT6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2731 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2732 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
AnnaBridge 171:3a7713b1edbc 2733 #define CAN_FA1R_FACT7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2734 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2735 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
AnnaBridge 171:3a7713b1edbc 2736 #define CAN_FA1R_FACT8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2737 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2738 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
AnnaBridge 171:3a7713b1edbc 2739 #define CAN_FA1R_FACT9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2740 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2741 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
AnnaBridge 171:3a7713b1edbc 2742 #define CAN_FA1R_FACT10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2743 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2744 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
AnnaBridge 171:3a7713b1edbc 2745 #define CAN_FA1R_FACT11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2746 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2747 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
AnnaBridge 171:3a7713b1edbc 2748 #define CAN_FA1R_FACT12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2749 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2750 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
AnnaBridge 171:3a7713b1edbc 2751 #define CAN_FA1R_FACT13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2752 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2753 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
AnnaBridge 171:3a7713b1edbc 2754
AnnaBridge 171:3a7713b1edbc 2755 /******************* Bit definition for CAN_F0R1 register *******************/
AnnaBridge 171:3a7713b1edbc 2756 #define CAN_F0R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2757 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2758 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 2759 #define CAN_F0R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2760 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2761 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 2762 #define CAN_F0R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2763 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2764 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 2765 #define CAN_F0R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2766 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2767 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 2768 #define CAN_F0R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2769 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2770 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 2771 #define CAN_F0R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2772 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2773 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 2774 #define CAN_F0R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2775 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2776 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 2777 #define CAN_F0R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2778 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2779 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 2780 #define CAN_F0R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2781 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2782 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 2783 #define CAN_F0R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2784 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2785 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 2786 #define CAN_F0R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2787 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2788 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 2789 #define CAN_F0R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2790 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2791 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 2792 #define CAN_F0R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2793 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2794 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 2795 #define CAN_F0R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2796 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2797 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 2798 #define CAN_F0R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2799 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2800 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 2801 #define CAN_F0R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2802 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2803 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 2804 #define CAN_F0R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2805 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2806 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 2807 #define CAN_F0R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2808 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2809 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 2810 #define CAN_F0R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2811 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2812 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 2813 #define CAN_F0R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2814 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2815 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 2816 #define CAN_F0R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2817 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2818 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 2819 #define CAN_F0R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2820 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2821 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 2822 #define CAN_F0R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2823 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2824 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 2825 #define CAN_F0R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2826 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2827 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 2828 #define CAN_F0R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2829 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2830 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 2831 #define CAN_F0R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2832 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2833 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 2834 #define CAN_F0R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2835 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2836 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 2837 #define CAN_F0R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 2838 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2839 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 2840 #define CAN_F0R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2841 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2842 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 2843 #define CAN_F0R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2844 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2845 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 2846 #define CAN_F0R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2847 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2848 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 2849 #define CAN_F0R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2850 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2851 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 2852
AnnaBridge 171:3a7713b1edbc 2853 /******************* Bit definition for CAN_F1R1 register *******************/
AnnaBridge 171:3a7713b1edbc 2854 #define CAN_F1R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2855 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2856 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 2857 #define CAN_F1R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2858 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2859 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 2860 #define CAN_F1R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2861 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2862 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 2863 #define CAN_F1R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2864 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2865 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 2866 #define CAN_F1R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2867 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2868 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 2869 #define CAN_F1R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2870 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2871 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 2872 #define CAN_F1R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2873 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2874 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 2875 #define CAN_F1R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2876 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2877 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 2878 #define CAN_F1R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2879 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2880 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 2881 #define CAN_F1R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2882 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2883 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 2884 #define CAN_F1R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2885 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2886 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 2887 #define CAN_F1R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2888 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2889 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 2890 #define CAN_F1R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2891 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2892 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 2893 #define CAN_F1R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2894 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2895 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 2896 #define CAN_F1R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2897 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2898 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 2899 #define CAN_F1R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2900 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2901 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 2902 #define CAN_F1R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2903 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2904 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 2905 #define CAN_F1R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2906 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2907 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 2908 #define CAN_F1R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2909 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2910 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 2911 #define CAN_F1R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2912 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2913 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 2914 #define CAN_F1R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2915 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2916 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 2917 #define CAN_F1R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2918 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2919 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 2920 #define CAN_F1R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2921 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2922 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 2923 #define CAN_F1R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2924 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2925 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 2926 #define CAN_F1R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2927 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2928 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 2929 #define CAN_F1R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2930 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2931 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 2932 #define CAN_F1R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2933 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2934 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 2935 #define CAN_F1R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 2936 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2937 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 2938 #define CAN_F1R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2939 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2940 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 2941 #define CAN_F1R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2942 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2943 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 2944 #define CAN_F1R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2945 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2946 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 2947 #define CAN_F1R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2948 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2949 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 2950
AnnaBridge 171:3a7713b1edbc 2951 /******************* Bit definition for CAN_F2R1 register *******************/
AnnaBridge 171:3a7713b1edbc 2952 #define CAN_F2R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2953 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2954 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 2955 #define CAN_F2R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2956 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2957 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 2958 #define CAN_F2R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2959 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2960 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 2961 #define CAN_F2R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2962 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2963 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 2964 #define CAN_F2R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2965 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2966 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 2967 #define CAN_F2R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2968 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2969 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 2970 #define CAN_F2R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2971 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2972 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 2973 #define CAN_F2R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2974 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2975 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 2976 #define CAN_F2R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2977 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2978 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 2979 #define CAN_F2R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2980 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2981 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 2982 #define CAN_F2R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2983 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2984 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 2985 #define CAN_F2R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2986 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2987 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 2988 #define CAN_F2R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2989 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2990 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 2991 #define CAN_F2R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2992 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2993 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 2994 #define CAN_F2R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2995 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2996 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 2997 #define CAN_F2R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2998 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2999 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3000 #define CAN_F2R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3001 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3002 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3003 #define CAN_F2R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3004 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3005 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3006 #define CAN_F2R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3007 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3008 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3009 #define CAN_F2R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3010 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3011 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3012 #define CAN_F2R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3013 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3014 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3015 #define CAN_F2R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3016 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3017 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3018 #define CAN_F2R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3019 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3020 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3021 #define CAN_F2R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3022 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3023 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3024 #define CAN_F2R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3025 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3026 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3027 #define CAN_F2R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3028 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3029 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3030 #define CAN_F2R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3031 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3032 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3033 #define CAN_F2R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3034 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3035 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3036 #define CAN_F2R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3037 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3038 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3039 #define CAN_F2R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3040 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3041 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3042 #define CAN_F2R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3043 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3044 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3045 #define CAN_F2R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3046 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3047 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3048
AnnaBridge 171:3a7713b1edbc 3049 /******************* Bit definition for CAN_F3R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3050 #define CAN_F3R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3051 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3052 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3053 #define CAN_F3R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3054 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3055 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3056 #define CAN_F3R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3057 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3058 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3059 #define CAN_F3R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3060 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3061 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3062 #define CAN_F3R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3063 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3064 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3065 #define CAN_F3R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3066 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3067 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3068 #define CAN_F3R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3069 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3070 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3071 #define CAN_F3R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3072 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3073 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3074 #define CAN_F3R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3075 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3076 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3077 #define CAN_F3R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3078 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3079 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3080 #define CAN_F3R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3081 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3082 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3083 #define CAN_F3R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3084 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3085 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3086 #define CAN_F3R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3087 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3088 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3089 #define CAN_F3R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3090 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3091 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3092 #define CAN_F3R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3093 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3094 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3095 #define CAN_F3R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3096 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3097 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3098 #define CAN_F3R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3099 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3100 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3101 #define CAN_F3R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3102 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3103 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3104 #define CAN_F3R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3105 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3106 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3107 #define CAN_F3R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3108 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3109 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3110 #define CAN_F3R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3111 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3112 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3113 #define CAN_F3R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3114 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3115 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3116 #define CAN_F3R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3117 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3118 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3119 #define CAN_F3R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3120 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3121 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3122 #define CAN_F3R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3123 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3124 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3125 #define CAN_F3R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3126 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3127 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3128 #define CAN_F3R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3129 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3130 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3131 #define CAN_F3R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3132 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3133 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3134 #define CAN_F3R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3135 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3136 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3137 #define CAN_F3R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3138 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3139 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3140 #define CAN_F3R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3141 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3142 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3143 #define CAN_F3R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3144 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3145 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3146
AnnaBridge 171:3a7713b1edbc 3147 /******************* Bit definition for CAN_F4R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3148 #define CAN_F4R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3149 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3150 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3151 #define CAN_F4R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3152 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3153 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3154 #define CAN_F4R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3155 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3156 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3157 #define CAN_F4R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3158 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3159 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3160 #define CAN_F4R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3161 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3162 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3163 #define CAN_F4R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3164 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3165 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3166 #define CAN_F4R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3167 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3168 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3169 #define CAN_F4R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3170 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3171 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3172 #define CAN_F4R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3173 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3174 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3175 #define CAN_F4R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3176 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3177 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3178 #define CAN_F4R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3179 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3180 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3181 #define CAN_F4R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3182 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3183 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3184 #define CAN_F4R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3185 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3186 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3187 #define CAN_F4R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3188 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3189 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3190 #define CAN_F4R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3191 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3192 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3193 #define CAN_F4R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3194 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3195 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3196 #define CAN_F4R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3197 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3198 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3199 #define CAN_F4R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3200 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3201 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3202 #define CAN_F4R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3203 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3204 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3205 #define CAN_F4R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3206 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3207 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3208 #define CAN_F4R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3209 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3210 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3211 #define CAN_F4R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3212 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3213 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3214 #define CAN_F4R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3215 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3216 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3217 #define CAN_F4R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3218 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3219 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3220 #define CAN_F4R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3221 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3222 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3223 #define CAN_F4R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3224 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3225 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3226 #define CAN_F4R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3227 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3228 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3229 #define CAN_F4R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3230 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3231 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3232 #define CAN_F4R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3233 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3234 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3235 #define CAN_F4R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3236 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3237 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3238 #define CAN_F4R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3239 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3240 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3241 #define CAN_F4R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3242 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3243 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3244
AnnaBridge 171:3a7713b1edbc 3245 /******************* Bit definition for CAN_F5R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3246 #define CAN_F5R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3247 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3248 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3249 #define CAN_F5R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3250 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3251 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3252 #define CAN_F5R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3253 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3254 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3255 #define CAN_F5R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3256 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3257 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3258 #define CAN_F5R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3259 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3260 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3261 #define CAN_F5R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3262 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3263 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3264 #define CAN_F5R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3265 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3266 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3267 #define CAN_F5R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3268 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3269 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3270 #define CAN_F5R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3271 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3272 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3273 #define CAN_F5R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3274 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3275 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3276 #define CAN_F5R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3277 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3278 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3279 #define CAN_F5R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3280 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3281 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3282 #define CAN_F5R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3283 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3284 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3285 #define CAN_F5R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3286 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3287 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3288 #define CAN_F5R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3289 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3290 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3291 #define CAN_F5R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3292 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3293 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3294 #define CAN_F5R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3295 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3296 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3297 #define CAN_F5R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3298 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3299 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3300 #define CAN_F5R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3301 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3302 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3303 #define CAN_F5R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3304 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3305 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3306 #define CAN_F5R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3307 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3308 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3309 #define CAN_F5R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3310 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3311 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3312 #define CAN_F5R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3313 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3314 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3315 #define CAN_F5R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3316 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3317 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3318 #define CAN_F5R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3319 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3320 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3321 #define CAN_F5R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3322 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3323 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3324 #define CAN_F5R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3325 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3326 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3327 #define CAN_F5R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3328 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3329 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3330 #define CAN_F5R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3331 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3332 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3333 #define CAN_F5R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3334 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3335 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3336 #define CAN_F5R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3337 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3338 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3339 #define CAN_F5R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3340 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3341 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3342
AnnaBridge 171:3a7713b1edbc 3343 /******************* Bit definition for CAN_F6R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3344 #define CAN_F6R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3345 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3346 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3347 #define CAN_F6R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3348 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3349 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3350 #define CAN_F6R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3351 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3352 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3353 #define CAN_F6R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3354 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3355 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3356 #define CAN_F6R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3357 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3358 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3359 #define CAN_F6R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3360 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3361 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3362 #define CAN_F6R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3363 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3364 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3365 #define CAN_F6R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3366 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3367 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3368 #define CAN_F6R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3369 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3370 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3371 #define CAN_F6R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3372 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3373 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3374 #define CAN_F6R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3375 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3376 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3377 #define CAN_F6R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3378 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3379 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3380 #define CAN_F6R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3381 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3382 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3383 #define CAN_F6R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3384 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3385 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3386 #define CAN_F6R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3387 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3388 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3389 #define CAN_F6R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3390 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3391 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3392 #define CAN_F6R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3393 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3394 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3395 #define CAN_F6R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3396 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3397 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3398 #define CAN_F6R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3399 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3400 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3401 #define CAN_F6R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3402 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3403 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3404 #define CAN_F6R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3405 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3406 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3407 #define CAN_F6R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3408 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3409 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3410 #define CAN_F6R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3411 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3412 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3413 #define CAN_F6R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3414 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3415 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3416 #define CAN_F6R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3417 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3418 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3419 #define CAN_F6R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3420 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3421 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3422 #define CAN_F6R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3423 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3424 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3425 #define CAN_F6R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3426 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3427 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3428 #define CAN_F6R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3429 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3430 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3431 #define CAN_F6R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3432 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3433 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3434 #define CAN_F6R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3435 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3436 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3437 #define CAN_F6R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3438 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3439 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3440
AnnaBridge 171:3a7713b1edbc 3441 /******************* Bit definition for CAN_F7R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3442 #define CAN_F7R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3443 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3444 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3445 #define CAN_F7R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3446 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3447 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3448 #define CAN_F7R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3449 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3450 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3451 #define CAN_F7R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3452 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3453 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3454 #define CAN_F7R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3455 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3456 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3457 #define CAN_F7R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3458 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3459 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3460 #define CAN_F7R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3461 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3462 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3463 #define CAN_F7R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3464 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3465 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3466 #define CAN_F7R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3467 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3468 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3469 #define CAN_F7R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3470 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3471 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3472 #define CAN_F7R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3473 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3474 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3475 #define CAN_F7R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3476 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3477 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3478 #define CAN_F7R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3479 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3480 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3481 #define CAN_F7R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3482 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3483 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3484 #define CAN_F7R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3485 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3486 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3487 #define CAN_F7R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3488 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3489 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3490 #define CAN_F7R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3491 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3492 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3493 #define CAN_F7R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3494 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3495 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3496 #define CAN_F7R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3497 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3498 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3499 #define CAN_F7R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3500 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3501 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3502 #define CAN_F7R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3503 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3504 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3505 #define CAN_F7R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3506 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3507 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3508 #define CAN_F7R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3509 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3510 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3511 #define CAN_F7R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3512 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3513 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3514 #define CAN_F7R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3515 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3516 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3517 #define CAN_F7R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3518 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3519 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3520 #define CAN_F7R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3521 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3522 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3523 #define CAN_F7R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3524 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3525 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3526 #define CAN_F7R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3527 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3528 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3529 #define CAN_F7R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3530 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3531 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3532 #define CAN_F7R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3533 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3534 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3535 #define CAN_F7R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3536 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3537 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3538
AnnaBridge 171:3a7713b1edbc 3539 /******************* Bit definition for CAN_F8R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3540 #define CAN_F8R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3541 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3542 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3543 #define CAN_F8R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3544 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3545 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3546 #define CAN_F8R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3547 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3548 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3549 #define CAN_F8R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3550 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3551 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3552 #define CAN_F8R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3553 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3554 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3555 #define CAN_F8R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3556 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3557 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3558 #define CAN_F8R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3559 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3560 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3561 #define CAN_F8R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3562 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3563 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3564 #define CAN_F8R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3565 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3566 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3567 #define CAN_F8R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3568 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3569 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3570 #define CAN_F8R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3571 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3572 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3573 #define CAN_F8R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3574 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3575 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3576 #define CAN_F8R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3577 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3578 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3579 #define CAN_F8R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3580 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3581 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3582 #define CAN_F8R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3583 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3584 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3585 #define CAN_F8R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3586 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3587 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3588 #define CAN_F8R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3589 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3590 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3591 #define CAN_F8R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3592 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3593 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3594 #define CAN_F8R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3595 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3596 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3597 #define CAN_F8R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3598 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3599 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3600 #define CAN_F8R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3601 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3602 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3603 #define CAN_F8R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3604 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3605 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3606 #define CAN_F8R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3607 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3608 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3609 #define CAN_F8R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3610 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3611 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3612 #define CAN_F8R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3613 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3614 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3615 #define CAN_F8R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3616 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3617 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3618 #define CAN_F8R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3619 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3620 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3621 #define CAN_F8R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3622 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3623 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3624 #define CAN_F8R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3625 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3626 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3627 #define CAN_F8R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3628 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3629 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3630 #define CAN_F8R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3631 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3632 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3633 #define CAN_F8R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3634 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3635 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3636
AnnaBridge 171:3a7713b1edbc 3637 /******************* Bit definition for CAN_F9R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3638 #define CAN_F9R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3639 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3640 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3641 #define CAN_F9R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3642 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3643 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3644 #define CAN_F9R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3645 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3646 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3647 #define CAN_F9R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3648 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3649 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3650 #define CAN_F9R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3651 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3652 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3653 #define CAN_F9R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3654 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3655 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3656 #define CAN_F9R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3657 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3658 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3659 #define CAN_F9R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3660 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3661 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3662 #define CAN_F9R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3663 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3664 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3665 #define CAN_F9R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3666 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3667 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3668 #define CAN_F9R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3669 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3670 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3671 #define CAN_F9R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3672 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3673 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3674 #define CAN_F9R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3675 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3676 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3677 #define CAN_F9R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3678 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3679 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3680 #define CAN_F9R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3681 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3682 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3683 #define CAN_F9R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3684 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3685 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3686 #define CAN_F9R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3687 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3688 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3689 #define CAN_F9R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3690 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3691 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3692 #define CAN_F9R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3693 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3694 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3695 #define CAN_F9R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3696 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3697 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3698 #define CAN_F9R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3699 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3700 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3701 #define CAN_F9R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3702 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3703 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3704 #define CAN_F9R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3705 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3706 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3707 #define CAN_F9R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3708 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3709 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3710 #define CAN_F9R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3711 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3712 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3713 #define CAN_F9R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3714 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3715 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3716 #define CAN_F9R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3717 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3718 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3719 #define CAN_F9R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3720 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3721 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3722 #define CAN_F9R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3723 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3724 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3725 #define CAN_F9R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3726 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3727 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3728 #define CAN_F9R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3729 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3730 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3731 #define CAN_F9R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3732 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3733 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3734
AnnaBridge 171:3a7713b1edbc 3735 /******************* Bit definition for CAN_F10R1 register ******************/
AnnaBridge 171:3a7713b1edbc 3736 #define CAN_F10R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3737 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3738 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3739 #define CAN_F10R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3740 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3741 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3742 #define CAN_F10R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3743 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3744 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3745 #define CAN_F10R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3746 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3747 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3748 #define CAN_F10R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3749 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3750 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3751 #define CAN_F10R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3752 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3753 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3754 #define CAN_F10R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3755 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3756 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3757 #define CAN_F10R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3758 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3759 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3760 #define CAN_F10R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3761 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3762 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3763 #define CAN_F10R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3764 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3765 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3766 #define CAN_F10R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3767 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3768 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3769 #define CAN_F10R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3770 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3771 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3772 #define CAN_F10R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3773 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3774 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3775 #define CAN_F10R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3776 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3777 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3778 #define CAN_F10R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3779 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3780 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3781 #define CAN_F10R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3782 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3783 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3784 #define CAN_F10R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3785 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3786 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3787 #define CAN_F10R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3788 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3789 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3790 #define CAN_F10R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3791 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3792 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3793 #define CAN_F10R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3794 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3795 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3796 #define CAN_F10R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3797 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3798 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3799 #define CAN_F10R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3800 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3801 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3802 #define CAN_F10R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3803 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3804 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3805 #define CAN_F10R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3806 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3807 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3808 #define CAN_F10R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3809 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3810 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3811 #define CAN_F10R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3812 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3813 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3814 #define CAN_F10R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3815 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3816 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3817 #define CAN_F10R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3818 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3819 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3820 #define CAN_F10R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3821 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3822 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3823 #define CAN_F10R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3824 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3825 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3826 #define CAN_F10R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3827 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3828 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3829 #define CAN_F10R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3830 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3831 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3832
AnnaBridge 171:3a7713b1edbc 3833 /******************* Bit definition for CAN_F11R1 register ******************/
AnnaBridge 171:3a7713b1edbc 3834 #define CAN_F11R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3835 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3836 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3837 #define CAN_F11R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3838 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3839 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3840 #define CAN_F11R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3841 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3842 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3843 #define CAN_F11R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3844 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3845 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3846 #define CAN_F11R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3847 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3848 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3849 #define CAN_F11R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3850 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3851 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3852 #define CAN_F11R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3853 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3854 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3855 #define CAN_F11R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3856 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3857 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3858 #define CAN_F11R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3859 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3860 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3861 #define CAN_F11R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3862 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3863 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3864 #define CAN_F11R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3865 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3866 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3867 #define CAN_F11R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3868 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3869 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3870 #define CAN_F11R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3871 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3872 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3873 #define CAN_F11R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3874 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3875 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3876 #define CAN_F11R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3877 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3878 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3879 #define CAN_F11R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3880 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3881 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3882 #define CAN_F11R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3883 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3884 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3885 #define CAN_F11R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3886 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3887 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3888 #define CAN_F11R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3889 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3890 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3891 #define CAN_F11R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3892 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3893 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3894 #define CAN_F11R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3895 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3896 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3897 #define CAN_F11R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3898 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3899 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3900 #define CAN_F11R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3901 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3902 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3903 #define CAN_F11R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3904 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3905 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3906 #define CAN_F11R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3907 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3908 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3909 #define CAN_F11R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3910 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3911 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3912 #define CAN_F11R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3913 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3914 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3915 #define CAN_F11R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3916 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3917 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3918 #define CAN_F11R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3919 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3920 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3921 #define CAN_F11R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3922 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3923 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3924 #define CAN_F11R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3925 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3926 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3927 #define CAN_F11R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3928 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3929 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3930
AnnaBridge 171:3a7713b1edbc 3931 /******************* Bit definition for CAN_F12R1 register ******************/
AnnaBridge 171:3a7713b1edbc 3932 #define CAN_F12R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3933 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3934 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3935 #define CAN_F12R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3936 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3937 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3938 #define CAN_F12R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3939 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3940 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3941 #define CAN_F12R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3942 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3943 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3944 #define CAN_F12R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3945 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3946 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3947 #define CAN_F12R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3948 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3949 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3950 #define CAN_F12R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3951 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3952 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3953 #define CAN_F12R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3954 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3955 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3956 #define CAN_F12R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3957 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3958 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3959 #define CAN_F12R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3960 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3961 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3962 #define CAN_F12R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3963 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3964 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3965 #define CAN_F12R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3966 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3967 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3968 #define CAN_F12R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3969 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3970 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3971 #define CAN_F12R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3972 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3973 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3974 #define CAN_F12R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3975 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3976 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3977 #define CAN_F12R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3978 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3979 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3980 #define CAN_F12R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3981 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3982 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3983 #define CAN_F12R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3984 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3985 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3986 #define CAN_F12R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3987 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3988 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3989 #define CAN_F12R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3990 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3991 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3992 #define CAN_F12R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3993 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3994 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3995 #define CAN_F12R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3996 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3997 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3998 #define CAN_F12R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3999 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4000 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4001 #define CAN_F12R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4002 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4003 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4004 #define CAN_F12R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4005 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4006 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4007 #define CAN_F12R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4008 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4009 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4010 #define CAN_F12R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4011 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4012 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4013 #define CAN_F12R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4014 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4015 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4016 #define CAN_F12R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4017 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4018 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4019 #define CAN_F12R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4020 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4021 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4022 #define CAN_F12R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4023 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4024 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4025 #define CAN_F12R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4026 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4027 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4028
AnnaBridge 171:3a7713b1edbc 4029 /******************* Bit definition for CAN_F13R1 register ******************/
AnnaBridge 171:3a7713b1edbc 4030 #define CAN_F13R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4031 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4032 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4033 #define CAN_F13R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4034 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4035 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4036 #define CAN_F13R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4037 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4038 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4039 #define CAN_F13R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4040 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4041 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4042 #define CAN_F13R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4043 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4044 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4045 #define CAN_F13R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4046 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4047 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4048 #define CAN_F13R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4049 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4050 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4051 #define CAN_F13R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4052 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4053 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4054 #define CAN_F13R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4055 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4056 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4057 #define CAN_F13R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4058 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4059 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4060 #define CAN_F13R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4061 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4062 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4063 #define CAN_F13R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4064 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4065 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4066 #define CAN_F13R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4067 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4068 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4069 #define CAN_F13R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4070 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4071 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4072 #define CAN_F13R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4073 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4074 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4075 #define CAN_F13R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4076 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4077 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4078 #define CAN_F13R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4079 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4080 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4081 #define CAN_F13R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4082 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4083 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4084 #define CAN_F13R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4085 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4086 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4087 #define CAN_F13R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4088 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4089 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4090 #define CAN_F13R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4091 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4092 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4093 #define CAN_F13R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4094 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4095 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4096 #define CAN_F13R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4097 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4098 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4099 #define CAN_F13R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4100 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4101 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4102 #define CAN_F13R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4103 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4104 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4105 #define CAN_F13R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4106 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4107 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4108 #define CAN_F13R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4109 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4110 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4111 #define CAN_F13R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4112 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4113 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4114 #define CAN_F13R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4115 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4116 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4117 #define CAN_F13R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4118 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4119 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4120 #define CAN_F13R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4121 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4122 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4123 #define CAN_F13R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4124 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4125 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4126
AnnaBridge 171:3a7713b1edbc 4127 /******************* Bit definition for CAN_F0R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4128 #define CAN_F0R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4129 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4130 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4131 #define CAN_F0R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4132 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4133 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4134 #define CAN_F0R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4135 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4136 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4137 #define CAN_F0R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4138 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4139 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4140 #define CAN_F0R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4141 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4142 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4143 #define CAN_F0R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4144 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4145 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4146 #define CAN_F0R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4147 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4148 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4149 #define CAN_F0R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4150 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4151 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4152 #define CAN_F0R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4153 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4154 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4155 #define CAN_F0R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4156 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4157 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4158 #define CAN_F0R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4159 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4160 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4161 #define CAN_F0R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4162 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4163 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4164 #define CAN_F0R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4165 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4166 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4167 #define CAN_F0R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4168 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4169 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4170 #define CAN_F0R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4171 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4172 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4173 #define CAN_F0R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4174 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4175 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4176 #define CAN_F0R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4177 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4178 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4179 #define CAN_F0R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4180 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4181 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4182 #define CAN_F0R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4183 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4184 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4185 #define CAN_F0R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4186 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4187 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4188 #define CAN_F0R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4189 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4190 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4191 #define CAN_F0R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4192 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4193 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4194 #define CAN_F0R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4195 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4196 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4197 #define CAN_F0R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4198 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4199 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4200 #define CAN_F0R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4201 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4202 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4203 #define CAN_F0R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4204 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4205 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4206 #define CAN_F0R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4207 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4208 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4209 #define CAN_F0R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4210 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4211 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4212 #define CAN_F0R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4213 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4214 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4215 #define CAN_F0R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4216 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4217 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4218 #define CAN_F0R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4219 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4220 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4221 #define CAN_F0R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4222 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4223 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4224
AnnaBridge 171:3a7713b1edbc 4225 /******************* Bit definition for CAN_F1R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4226 #define CAN_F1R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4227 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4228 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4229 #define CAN_F1R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4230 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4231 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4232 #define CAN_F1R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4233 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4234 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4235 #define CAN_F1R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4236 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4237 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4238 #define CAN_F1R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4239 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4240 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4241 #define CAN_F1R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4242 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4243 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4244 #define CAN_F1R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4245 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4246 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4247 #define CAN_F1R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4248 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4249 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4250 #define CAN_F1R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4251 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4252 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4253 #define CAN_F1R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4254 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4255 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4256 #define CAN_F1R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4257 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4258 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4259 #define CAN_F1R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4260 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4261 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4262 #define CAN_F1R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4263 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4264 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4265 #define CAN_F1R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4266 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4267 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4268 #define CAN_F1R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4269 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4270 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4271 #define CAN_F1R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4272 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4273 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4274 #define CAN_F1R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4275 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4276 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4277 #define CAN_F1R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4278 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4279 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4280 #define CAN_F1R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4281 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4282 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4283 #define CAN_F1R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4284 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4285 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4286 #define CAN_F1R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4287 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4288 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4289 #define CAN_F1R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4290 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4291 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4292 #define CAN_F1R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4293 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4294 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4295 #define CAN_F1R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4296 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4297 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4298 #define CAN_F1R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4299 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4300 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4301 #define CAN_F1R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4302 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4303 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4304 #define CAN_F1R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4305 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4306 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4307 #define CAN_F1R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4308 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4309 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4310 #define CAN_F1R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4311 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4312 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4313 #define CAN_F1R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4314 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4315 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4316 #define CAN_F1R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4317 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4318 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4319 #define CAN_F1R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4320 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4321 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4322
AnnaBridge 171:3a7713b1edbc 4323 /******************* Bit definition for CAN_F2R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4324 #define CAN_F2R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4325 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4326 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4327 #define CAN_F2R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4328 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4329 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4330 #define CAN_F2R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4331 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4332 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4333 #define CAN_F2R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4334 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4335 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4336 #define CAN_F2R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4337 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4338 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4339 #define CAN_F2R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4340 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4341 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4342 #define CAN_F2R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4343 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4344 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4345 #define CAN_F2R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4346 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4347 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4348 #define CAN_F2R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4349 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4350 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4351 #define CAN_F2R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4352 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4353 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4354 #define CAN_F2R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4355 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4356 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4357 #define CAN_F2R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4358 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4359 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4360 #define CAN_F2R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4361 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4362 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4363 #define CAN_F2R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4364 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4365 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4366 #define CAN_F2R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4367 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4368 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4369 #define CAN_F2R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4370 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4371 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4372 #define CAN_F2R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4373 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4374 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4375 #define CAN_F2R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4376 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4377 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4378 #define CAN_F2R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4379 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4380 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4381 #define CAN_F2R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4382 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4383 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4384 #define CAN_F2R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4385 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4386 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4387 #define CAN_F2R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4388 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4389 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4390 #define CAN_F2R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4391 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4392 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4393 #define CAN_F2R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4394 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4395 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4396 #define CAN_F2R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4397 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4398 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4399 #define CAN_F2R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4400 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4401 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4402 #define CAN_F2R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4403 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4404 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4405 #define CAN_F2R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4406 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4407 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4408 #define CAN_F2R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4409 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4410 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4411 #define CAN_F2R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4412 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4413 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4414 #define CAN_F2R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4415 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4416 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4417 #define CAN_F2R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4418 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4419 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4420
AnnaBridge 171:3a7713b1edbc 4421 /******************* Bit definition for CAN_F3R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4422 #define CAN_F3R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4423 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4424 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4425 #define CAN_F3R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4426 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4427 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4428 #define CAN_F3R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4429 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4430 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4431 #define CAN_F3R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4432 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4433 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4434 #define CAN_F3R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4435 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4436 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4437 #define CAN_F3R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4438 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4439 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4440 #define CAN_F3R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4441 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4442 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4443 #define CAN_F3R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4444 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4445 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4446 #define CAN_F3R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4447 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4448 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4449 #define CAN_F3R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4450 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4451 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4452 #define CAN_F3R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4453 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4454 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4455 #define CAN_F3R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4456 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4457 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4458 #define CAN_F3R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4459 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4460 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4461 #define CAN_F3R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4462 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4463 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4464 #define CAN_F3R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4465 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4466 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4467 #define CAN_F3R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4468 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4469 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4470 #define CAN_F3R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4471 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4472 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4473 #define CAN_F3R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4474 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4475 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4476 #define CAN_F3R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4477 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4478 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4479 #define CAN_F3R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4480 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4481 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4482 #define CAN_F3R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4483 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4484 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4485 #define CAN_F3R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4486 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4487 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4488 #define CAN_F3R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4489 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4490 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4491 #define CAN_F3R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4492 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4493 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4494 #define CAN_F3R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4495 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4496 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4497 #define CAN_F3R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4498 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4499 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4500 #define CAN_F3R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4501 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4502 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4503 #define CAN_F3R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4504 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4505 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4506 #define CAN_F3R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4507 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4508 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4509 #define CAN_F3R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4510 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4511 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4512 #define CAN_F3R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4513 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4514 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4515 #define CAN_F3R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4516 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4517 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4518
AnnaBridge 171:3a7713b1edbc 4519 /******************* Bit definition for CAN_F4R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4520 #define CAN_F4R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4521 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4522 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4523 #define CAN_F4R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4524 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4525 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4526 #define CAN_F4R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4527 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4528 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4529 #define CAN_F4R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4530 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4531 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4532 #define CAN_F4R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4533 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4534 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4535 #define CAN_F4R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4536 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4537 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4538 #define CAN_F4R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4539 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4540 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4541 #define CAN_F4R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4542 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4543 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4544 #define CAN_F4R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4545 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4546 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4547 #define CAN_F4R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4548 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4549 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4550 #define CAN_F4R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4551 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4552 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4553 #define CAN_F4R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4554 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4555 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4556 #define CAN_F4R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4557 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4558 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4559 #define CAN_F4R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4560 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4561 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4562 #define CAN_F4R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4563 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4564 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4565 #define CAN_F4R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4566 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4567 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4568 #define CAN_F4R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4569 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4570 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4571 #define CAN_F4R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4572 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4573 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4574 #define CAN_F4R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4575 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4576 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4577 #define CAN_F4R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4578 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4579 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4580 #define CAN_F4R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4581 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4582 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4583 #define CAN_F4R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4584 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4585 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4586 #define CAN_F4R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4587 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4588 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4589 #define CAN_F4R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4590 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4591 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4592 #define CAN_F4R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4593 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4594 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4595 #define CAN_F4R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4596 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4597 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4598 #define CAN_F4R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4599 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4600 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4601 #define CAN_F4R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4602 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4603 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4604 #define CAN_F4R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4605 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4606 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4607 #define CAN_F4R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4608 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4609 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4610 #define CAN_F4R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4611 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4612 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4613 #define CAN_F4R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4614 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4615 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4616
AnnaBridge 171:3a7713b1edbc 4617 /******************* Bit definition for CAN_F5R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4618 #define CAN_F5R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4619 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4620 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4621 #define CAN_F5R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4622 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4623 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4624 #define CAN_F5R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4625 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4626 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4627 #define CAN_F5R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4628 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4629 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4630 #define CAN_F5R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4631 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4632 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4633 #define CAN_F5R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4634 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4635 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4636 #define CAN_F5R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4637 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4638 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4639 #define CAN_F5R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4640 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4641 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4642 #define CAN_F5R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4643 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4644 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4645 #define CAN_F5R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4646 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4647 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4648 #define CAN_F5R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4649 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4650 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4651 #define CAN_F5R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4652 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4653 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4654 #define CAN_F5R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4655 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4656 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4657 #define CAN_F5R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4658 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4659 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4660 #define CAN_F5R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4661 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4662 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4663 #define CAN_F5R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4664 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4665 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4666 #define CAN_F5R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4667 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4668 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4669 #define CAN_F5R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4670 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4671 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4672 #define CAN_F5R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4673 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4674 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4675 #define CAN_F5R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4676 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4677 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4678 #define CAN_F5R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4679 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4680 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4681 #define CAN_F5R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4682 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4683 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4684 #define CAN_F5R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4685 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4686 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4687 #define CAN_F5R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4688 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4689 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4690 #define CAN_F5R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4691 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4692 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4693 #define CAN_F5R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4694 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4695 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4696 #define CAN_F5R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4697 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4698 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4699 #define CAN_F5R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4700 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4701 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4702 #define CAN_F5R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4703 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4704 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4705 #define CAN_F5R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4706 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4707 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4708 #define CAN_F5R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4709 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4710 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4711 #define CAN_F5R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4712 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4713 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4714
AnnaBridge 171:3a7713b1edbc 4715 /******************* Bit definition for CAN_F6R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4716 #define CAN_F6R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4717 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4718 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4719 #define CAN_F6R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4720 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4721 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4722 #define CAN_F6R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4723 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4724 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4725 #define CAN_F6R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4726 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4727 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4728 #define CAN_F6R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4729 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4730 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4731 #define CAN_F6R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4732 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4733 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4734 #define CAN_F6R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4735 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4736 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4737 #define CAN_F6R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4738 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4739 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4740 #define CAN_F6R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4741 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4742 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4743 #define CAN_F6R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4744 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4745 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4746 #define CAN_F6R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4747 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4748 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4749 #define CAN_F6R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4750 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4751 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4752 #define CAN_F6R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4753 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4754 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4755 #define CAN_F6R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4756 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4757 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4758 #define CAN_F6R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4759 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4760 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4761 #define CAN_F6R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4762 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4763 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4764 #define CAN_F6R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4765 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4766 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4767 #define CAN_F6R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4768 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4769 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4770 #define CAN_F6R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4771 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4772 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4773 #define CAN_F6R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4774 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4775 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4776 #define CAN_F6R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4777 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4778 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4779 #define CAN_F6R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4780 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4781 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4782 #define CAN_F6R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4783 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4784 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4785 #define CAN_F6R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4786 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4787 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4788 #define CAN_F6R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4789 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4790 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4791 #define CAN_F6R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4792 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4793 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4794 #define CAN_F6R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4795 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4796 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4797 #define CAN_F6R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4798 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4799 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4800 #define CAN_F6R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4801 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4802 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4803 #define CAN_F6R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4804 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4805 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4806 #define CAN_F6R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4807 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4808 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4809 #define CAN_F6R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4810 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4811 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4812
AnnaBridge 171:3a7713b1edbc 4813 /******************* Bit definition for CAN_F7R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4814 #define CAN_F7R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4815 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4816 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4817 #define CAN_F7R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4818 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4819 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4820 #define CAN_F7R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4821 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4822 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4823 #define CAN_F7R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4824 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4825 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4826 #define CAN_F7R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4827 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4828 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4829 #define CAN_F7R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4830 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4831 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4832 #define CAN_F7R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4833 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4834 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4835 #define CAN_F7R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4836 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4837 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4838 #define CAN_F7R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4839 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4840 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4841 #define CAN_F7R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4842 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4843 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4844 #define CAN_F7R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4845 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4846 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4847 #define CAN_F7R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4848 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4849 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4850 #define CAN_F7R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4851 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4852 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4853 #define CAN_F7R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4854 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4855 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4856 #define CAN_F7R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4857 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4858 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4859 #define CAN_F7R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4860 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4861 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4862 #define CAN_F7R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4863 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4864 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4865 #define CAN_F7R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4866 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4867 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4868 #define CAN_F7R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4869 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4870 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4871 #define CAN_F7R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4872 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4873 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4874 #define CAN_F7R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4875 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4876 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4877 #define CAN_F7R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4878 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4879 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4880 #define CAN_F7R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4881 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4882 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4883 #define CAN_F7R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4884 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4885 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4886 #define CAN_F7R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4887 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4888 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4889 #define CAN_F7R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4890 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4891 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4892 #define CAN_F7R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4893 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4894 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4895 #define CAN_F7R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4896 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4897 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4898 #define CAN_F7R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4899 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4900 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4901 #define CAN_F7R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4902 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4903 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4904 #define CAN_F7R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4905 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4906 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4907 #define CAN_F7R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4908 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4909 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4910
AnnaBridge 171:3a7713b1edbc 4911 /******************* Bit definition for CAN_F8R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4912 #define CAN_F8R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4913 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4914 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4915 #define CAN_F8R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4916 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4917 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4918 #define CAN_F8R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4919 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4920 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4921 #define CAN_F8R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4922 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4923 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4924 #define CAN_F8R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4925 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4926 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4927 #define CAN_F8R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4928 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4929 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4930 #define CAN_F8R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4931 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4932 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4933 #define CAN_F8R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4934 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4935 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4936 #define CAN_F8R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4937 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4938 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4939 #define CAN_F8R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4940 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4941 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4942 #define CAN_F8R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4943 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4944 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4945 #define CAN_F8R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4946 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4947 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4948 #define CAN_F8R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4949 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4950 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4951 #define CAN_F8R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4952 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4953 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4954 #define CAN_F8R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4955 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4956 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4957 #define CAN_F8R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4958 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4959 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4960 #define CAN_F8R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4961 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4962 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4963 #define CAN_F8R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4964 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4965 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4966 #define CAN_F8R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4967 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4968 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4969 #define CAN_F8R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4970 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4971 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4972 #define CAN_F8R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4973 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4974 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4975 #define CAN_F8R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4976 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4977 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4978 #define CAN_F8R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4979 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4980 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4981 #define CAN_F8R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4982 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4983 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4984 #define CAN_F8R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4985 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4986 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4987 #define CAN_F8R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4988 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4989 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4990 #define CAN_F8R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4991 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4992 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4993 #define CAN_F8R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4994 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4995 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4996 #define CAN_F8R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4997 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4998 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4999 #define CAN_F8R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5000 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5001 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5002 #define CAN_F8R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5003 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5004 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5005 #define CAN_F8R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5006 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5007 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5008
AnnaBridge 171:3a7713b1edbc 5009 /******************* Bit definition for CAN_F9R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5010 #define CAN_F9R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5011 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5012 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5013 #define CAN_F9R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5014 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5015 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5016 #define CAN_F9R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5017 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5018 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5019 #define CAN_F9R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5020 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5021 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5022 #define CAN_F9R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5023 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5024 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5025 #define CAN_F9R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5026 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5027 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5028 #define CAN_F9R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5029 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5030 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5031 #define CAN_F9R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5032 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5033 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5034 #define CAN_F9R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5035 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5036 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5037 #define CAN_F9R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5038 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5039 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5040 #define CAN_F9R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5041 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5042 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5043 #define CAN_F9R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5044 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5045 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5046 #define CAN_F9R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5047 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5048 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5049 #define CAN_F9R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5050 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5051 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5052 #define CAN_F9R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5053 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5054 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5055 #define CAN_F9R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5056 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5057 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5058 #define CAN_F9R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5059 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5060 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5061 #define CAN_F9R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5062 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5063 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5064 #define CAN_F9R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5065 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5066 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5067 #define CAN_F9R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5068 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5069 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5070 #define CAN_F9R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5071 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5072 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5073 #define CAN_F9R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5074 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5075 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5076 #define CAN_F9R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5077 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5078 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5079 #define CAN_F9R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5080 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5081 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5082 #define CAN_F9R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5083 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5084 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5085 #define CAN_F9R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5086 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5087 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5088 #define CAN_F9R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5089 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5090 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5091 #define CAN_F9R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5092 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5093 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5094 #define CAN_F9R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5095 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5096 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5097 #define CAN_F9R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5098 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5099 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5100 #define CAN_F9R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5101 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5102 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5103 #define CAN_F9R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5104 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5105 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5106
AnnaBridge 171:3a7713b1edbc 5107 /******************* Bit definition for CAN_F10R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5108 #define CAN_F10R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5109 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5110 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5111 #define CAN_F10R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5112 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5113 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5114 #define CAN_F10R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5115 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5116 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5117 #define CAN_F10R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5118 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5119 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5120 #define CAN_F10R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5121 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5122 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5123 #define CAN_F10R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5124 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5125 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5126 #define CAN_F10R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5127 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5128 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5129 #define CAN_F10R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5130 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5131 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5132 #define CAN_F10R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5133 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5134 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5135 #define CAN_F10R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5136 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5137 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5138 #define CAN_F10R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5139 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5140 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5141 #define CAN_F10R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5142 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5143 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5144 #define CAN_F10R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5145 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5146 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5147 #define CAN_F10R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5148 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5149 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5150 #define CAN_F10R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5151 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5152 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5153 #define CAN_F10R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5154 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5155 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5156 #define CAN_F10R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5157 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5158 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5159 #define CAN_F10R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5160 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5161 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5162 #define CAN_F10R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5163 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5164 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5165 #define CAN_F10R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5166 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5167 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5168 #define CAN_F10R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5169 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5170 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5171 #define CAN_F10R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5172 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5173 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5174 #define CAN_F10R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5175 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5176 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5177 #define CAN_F10R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5178 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5179 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5180 #define CAN_F10R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5181 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5182 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5183 #define CAN_F10R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5184 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5185 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5186 #define CAN_F10R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5187 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5188 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5189 #define CAN_F10R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5190 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5191 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5192 #define CAN_F10R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5193 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5194 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5195 #define CAN_F10R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5196 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5197 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5198 #define CAN_F10R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5199 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5200 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5201 #define CAN_F10R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5202 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5203 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5204
AnnaBridge 171:3a7713b1edbc 5205 /******************* Bit definition for CAN_F11R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5206 #define CAN_F11R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5207 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5208 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5209 #define CAN_F11R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5210 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5211 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5212 #define CAN_F11R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5213 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5214 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5215 #define CAN_F11R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5216 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5217 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5218 #define CAN_F11R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5219 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5220 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5221 #define CAN_F11R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5222 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5223 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5224 #define CAN_F11R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5225 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5226 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5227 #define CAN_F11R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5228 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5229 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5230 #define CAN_F11R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5231 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5232 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5233 #define CAN_F11R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5234 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5235 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5236 #define CAN_F11R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5237 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5238 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5239 #define CAN_F11R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5240 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5241 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5242 #define CAN_F11R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5243 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5244 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5245 #define CAN_F11R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5246 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5247 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5248 #define CAN_F11R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5249 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5250 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5251 #define CAN_F11R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5252 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5253 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5254 #define CAN_F11R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5255 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5256 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5257 #define CAN_F11R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5258 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5259 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5260 #define CAN_F11R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5261 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5262 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5263 #define CAN_F11R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5264 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5265 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5266 #define CAN_F11R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5267 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5268 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5269 #define CAN_F11R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5270 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5271 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5272 #define CAN_F11R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5273 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5274 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5275 #define CAN_F11R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5276 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5277 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5278 #define CAN_F11R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5279 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5280 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5281 #define CAN_F11R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5282 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5283 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5284 #define CAN_F11R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5285 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5286 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5287 #define CAN_F11R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5288 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5289 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5290 #define CAN_F11R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5291 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5292 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5293 #define CAN_F11R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5294 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5295 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5296 #define CAN_F11R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5297 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5298 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5299 #define CAN_F11R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5300 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5301 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5302
AnnaBridge 171:3a7713b1edbc 5303 /******************* Bit definition for CAN_F12R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5304 #define CAN_F12R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5305 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5306 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5307 #define CAN_F12R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5308 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5309 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5310 #define CAN_F12R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5311 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5312 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5313 #define CAN_F12R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5314 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5315 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5316 #define CAN_F12R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5317 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5318 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5319 #define CAN_F12R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5320 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5321 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5322 #define CAN_F12R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5323 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5324 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5325 #define CAN_F12R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5326 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5327 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5328 #define CAN_F12R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5329 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5330 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5331 #define CAN_F12R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5332 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5333 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5334 #define CAN_F12R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5335 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5336 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5337 #define CAN_F12R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5338 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5339 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5340 #define CAN_F12R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5341 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5342 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5343 #define CAN_F12R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5344 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5345 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5346 #define CAN_F12R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5347 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5348 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5349 #define CAN_F12R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5350 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5351 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5352 #define CAN_F12R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5353 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5354 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5355 #define CAN_F12R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5356 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5357 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5358 #define CAN_F12R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5359 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5360 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5361 #define CAN_F12R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5362 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5363 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5364 #define CAN_F12R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5365 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5366 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5367 #define CAN_F12R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5368 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5369 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5370 #define CAN_F12R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5371 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5372 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5373 #define CAN_F12R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5374 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5375 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5376 #define CAN_F12R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5377 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5378 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5379 #define CAN_F12R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5380 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5381 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5382 #define CAN_F12R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5383 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5384 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5385 #define CAN_F12R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5386 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5387 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5388 #define CAN_F12R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5389 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5390 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5391 #define CAN_F12R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5392 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5393 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5394 #define CAN_F12R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5395 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5396 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5397 #define CAN_F12R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5398 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5399 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5400
AnnaBridge 171:3a7713b1edbc 5401 /******************* Bit definition for CAN_F13R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5402 #define CAN_F13R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5403 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5404 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5405 #define CAN_F13R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5406 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5407 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5408 #define CAN_F13R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5409 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5410 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5411 #define CAN_F13R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5412 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5413 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5414 #define CAN_F13R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5415 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5416 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5417 #define CAN_F13R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5418 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5419 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5420 #define CAN_F13R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5421 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5422 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5423 #define CAN_F13R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5424 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5425 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5426 #define CAN_F13R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5427 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5428 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5429 #define CAN_F13R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5430 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5431 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5432 #define CAN_F13R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5433 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5434 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5435 #define CAN_F13R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5436 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5437 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5438 #define CAN_F13R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5439 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5440 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5441 #define CAN_F13R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5442 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5443 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5444 #define CAN_F13R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5445 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5446 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5447 #define CAN_F13R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5448 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5449 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5450 #define CAN_F13R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5451 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5452 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5453 #define CAN_F13R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5454 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5455 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5456 #define CAN_F13R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5457 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5458 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5459 #define CAN_F13R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5460 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5461 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5462 #define CAN_F13R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5463 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5464 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5465 #define CAN_F13R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5466 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5467 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5468 #define CAN_F13R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5469 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5470 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5471 #define CAN_F13R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5472 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5473 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5474 #define CAN_F13R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5475 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5476 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5477 #define CAN_F13R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5478 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5479 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5480 #define CAN_F13R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5481 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5482 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5483 #define CAN_F13R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5484 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5485 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5486 #define CAN_F13R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5487 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5488 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5489 #define CAN_F13R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5490 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5491 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5492 #define CAN_F13R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5493 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5494 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5495 #define CAN_F13R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5496 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5497 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5498
AnnaBridge 171:3a7713b1edbc 5499 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5500 /* */
AnnaBridge 171:3a7713b1edbc 5501 /* HDMI-CEC (CEC) */
AnnaBridge 171:3a7713b1edbc 5502 /* */
AnnaBridge 171:3a7713b1edbc 5503 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5504
AnnaBridge 171:3a7713b1edbc 5505 /******************* Bit definition for CEC_CR register *********************/
AnnaBridge 171:3a7713b1edbc 5506 #define CEC_CR_CECEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5507 #define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5508 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
AnnaBridge 171:3a7713b1edbc 5509 #define CEC_CR_TXSOM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5510 #define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5511 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
AnnaBridge 171:3a7713b1edbc 5512 #define CEC_CR_TXEOM_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5513 #define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5514 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
AnnaBridge 171:3a7713b1edbc 5515
AnnaBridge 171:3a7713b1edbc 5516 /******************* Bit definition for CEC_CFGR register *******************/
AnnaBridge 171:3a7713b1edbc 5517 #define CEC_CFGR_SFT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5518 #define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 5519 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
AnnaBridge 171:3a7713b1edbc 5520 #define CEC_CFGR_RXTOL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5521 #define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5522 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
AnnaBridge 171:3a7713b1edbc 5523 #define CEC_CFGR_BRESTP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5524 #define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5525 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
AnnaBridge 171:3a7713b1edbc 5526 #define CEC_CFGR_BREGEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5527 #define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5528 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
AnnaBridge 171:3a7713b1edbc 5529 #define CEC_CFGR_LBPEGEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5530 #define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5531 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Period Error generation */
AnnaBridge 171:3a7713b1edbc 5532 #define CEC_CFGR_BRDNOGEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5533 #define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5534 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast no Error generation */
AnnaBridge 171:3a7713b1edbc 5535 #define CEC_CFGR_SFTOPT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5536 #define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5537 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
AnnaBridge 171:3a7713b1edbc 5538 #define CEC_CFGR_OAR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5539 #define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
AnnaBridge 171:3a7713b1edbc 5540 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
AnnaBridge 171:3a7713b1edbc 5541 #define CEC_CFGR_LSTN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5542 #define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5543 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
AnnaBridge 171:3a7713b1edbc 5544
AnnaBridge 171:3a7713b1edbc 5545 /******************* Bit definition for CEC_TXDR register *******************/
AnnaBridge 171:3a7713b1edbc 5546 #define CEC_TXDR_TXD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5547 #define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5548 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
AnnaBridge 171:3a7713b1edbc 5549
AnnaBridge 171:3a7713b1edbc 5550 /******************* Bit definition for CEC_RXDR register *******************/
AnnaBridge 171:3a7713b1edbc 5551 #define CEC_TXDR_RXD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5552 #define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5553 #define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
AnnaBridge 171:3a7713b1edbc 5554
AnnaBridge 171:3a7713b1edbc 5555 /******************* Bit definition for CEC_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 5556 #define CEC_ISR_RXBR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5557 #define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5558 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
AnnaBridge 171:3a7713b1edbc 5559 #define CEC_ISR_RXEND_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5560 #define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5561 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
AnnaBridge 171:3a7713b1edbc 5562 #define CEC_ISR_RXOVR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5563 #define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5564 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
AnnaBridge 171:3a7713b1edbc 5565 #define CEC_ISR_BRE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5566 #define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5567 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
AnnaBridge 171:3a7713b1edbc 5568 #define CEC_ISR_SBPE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5569 #define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5570 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
AnnaBridge 171:3a7713b1edbc 5571 #define CEC_ISR_LBPE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5572 #define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5573 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
AnnaBridge 171:3a7713b1edbc 5574 #define CEC_ISR_RXACKE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5575 #define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5576 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
AnnaBridge 171:3a7713b1edbc 5577 #define CEC_ISR_ARBLST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5578 #define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5579 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
AnnaBridge 171:3a7713b1edbc 5580 #define CEC_ISR_TXBR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5581 #define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5582 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
AnnaBridge 171:3a7713b1edbc 5583 #define CEC_ISR_TXEND_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5584 #define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5585 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
AnnaBridge 171:3a7713b1edbc 5586 #define CEC_ISR_TXUDR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5587 #define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5588 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
AnnaBridge 171:3a7713b1edbc 5589 #define CEC_ISR_TXERR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5590 #define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5591 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
AnnaBridge 171:3a7713b1edbc 5592 #define CEC_ISR_TXACKE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5593 #define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5594 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
AnnaBridge 171:3a7713b1edbc 5595
AnnaBridge 171:3a7713b1edbc 5596 /******************* Bit definition for CEC_IER register ********************/
AnnaBridge 171:3a7713b1edbc 5597 #define CEC_IER_RXBRIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5598 #define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5599 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
AnnaBridge 171:3a7713b1edbc 5600 #define CEC_IER_RXENDIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5601 #define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5602 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
AnnaBridge 171:3a7713b1edbc 5603 #define CEC_IER_RXOVRIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5604 #define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5605 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
AnnaBridge 171:3a7713b1edbc 5606 #define CEC_IER_BREIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5607 #define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5608 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
AnnaBridge 171:3a7713b1edbc 5609 #define CEC_IER_SBPEIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5610 #define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5611 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
AnnaBridge 171:3a7713b1edbc 5612 #define CEC_IER_LBPEIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5613 #define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5614 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
AnnaBridge 171:3a7713b1edbc 5615 #define CEC_IER_RXACKEIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5616 #define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5617 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
AnnaBridge 171:3a7713b1edbc 5618 #define CEC_IER_ARBLSTIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5619 #define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5620 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
AnnaBridge 171:3a7713b1edbc 5621 #define CEC_IER_TXBRIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5622 #define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5623 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
AnnaBridge 171:3a7713b1edbc 5624 #define CEC_IER_TXENDIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5625 #define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5626 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
AnnaBridge 171:3a7713b1edbc 5627 #define CEC_IER_TXUDRIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5628 #define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5629 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
AnnaBridge 171:3a7713b1edbc 5630 #define CEC_IER_TXERRIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5631 #define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5632 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
AnnaBridge 171:3a7713b1edbc 5633 #define CEC_IER_TXACKEIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5634 #define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5635 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
AnnaBridge 171:3a7713b1edbc 5636
AnnaBridge 171:3a7713b1edbc 5637 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5638 /* */
AnnaBridge 171:3a7713b1edbc 5639 /* CRC calculation unit */
AnnaBridge 171:3a7713b1edbc 5640 /* */
AnnaBridge 171:3a7713b1edbc 5641 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5642 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 171:3a7713b1edbc 5643 #define CRC_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5644 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5645 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 171:3a7713b1edbc 5646
AnnaBridge 171:3a7713b1edbc 5647 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 171:3a7713b1edbc 5648 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5649 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5650 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
AnnaBridge 171:3a7713b1edbc 5651
AnnaBridge 171:3a7713b1edbc 5652 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 5653 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5654 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5655 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
AnnaBridge 171:3a7713b1edbc 5656 #define CRC_CR_POLYSIZE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5657 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 5658 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
AnnaBridge 171:3a7713b1edbc 5659 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5660 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5661 #define CRC_CR_REV_IN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5662 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 5663 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
AnnaBridge 171:3a7713b1edbc 5664 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5665 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5666 #define CRC_CR_REV_OUT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5667 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5668 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
AnnaBridge 171:3a7713b1edbc 5669
AnnaBridge 171:3a7713b1edbc 5670 /******************* Bit definition for CRC_INIT register *******************/
AnnaBridge 171:3a7713b1edbc 5671 #define CRC_INIT_INIT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5672 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5673 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
AnnaBridge 171:3a7713b1edbc 5674
AnnaBridge 171:3a7713b1edbc 5675 /******************* Bit definition for CRC_POL register ********************/
AnnaBridge 171:3a7713b1edbc 5676 #define CRC_POL_POL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5677 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5678 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
AnnaBridge 171:3a7713b1edbc 5679
AnnaBridge 171:3a7713b1edbc 5680
AnnaBridge 171:3a7713b1edbc 5681 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5682 /* */
AnnaBridge 171:3a7713b1edbc 5683 /* Digital to Analog Converter */
AnnaBridge 171:3a7713b1edbc 5684 /* */
AnnaBridge 171:3a7713b1edbc 5685 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5686 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 5687 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5688 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5689 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 171:3a7713b1edbc 5690 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5691 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5692 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
AnnaBridge 171:3a7713b1edbc 5693 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5694 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5695 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 171:3a7713b1edbc 5696 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5697 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 5698 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 5699 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5700 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5701 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5702 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5703 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 5704 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
AnnaBridge 171:3a7713b1edbc 5705 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5706 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5707 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5708 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5709 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 5710 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5711 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5712 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5713 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5714 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5715 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5716 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 171:3a7713b1edbc 5717 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5718 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5719 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable */
AnnaBridge 171:3a7713b1edbc 5720 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5721 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5722 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 171:3a7713b1edbc 5723 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5724 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5725 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
AnnaBridge 171:3a7713b1edbc 5726 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5727 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5728 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 171:3a7713b1edbc 5729 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5730 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 171:3a7713b1edbc 5731 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 5732 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5733 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5734 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5735 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5736 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 5737 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 5738 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5739 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5740 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5741 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5742 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 5743 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5744 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5745 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5746 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5747 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5748 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5749 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enable */
AnnaBridge 171:3a7713b1edbc 5750 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5751 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5752 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
AnnaBridge 171:3a7713b1edbc 5753
AnnaBridge 171:3a7713b1edbc 5754 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 171:3a7713b1edbc 5755 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5756 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5757 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 171:3a7713b1edbc 5758 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5759 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5760 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
AnnaBridge 171:3a7713b1edbc 5761
AnnaBridge 171:3a7713b1edbc 5762 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 171:3a7713b1edbc 5763 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5764 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5765 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5766
AnnaBridge 171:3a7713b1edbc 5767 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 171:3a7713b1edbc 5768 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5769 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 5770 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 5771
AnnaBridge 171:3a7713b1edbc 5772 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 171:3a7713b1edbc 5773 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5774 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5775 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5776
AnnaBridge 171:3a7713b1edbc 5777 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5778 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5779 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5780 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5781
AnnaBridge 171:3a7713b1edbc 5782 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 171:3a7713b1edbc 5783 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5784 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 5785 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 5786
AnnaBridge 171:3a7713b1edbc 5787 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5788 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5789 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5790 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5791
AnnaBridge 171:3a7713b1edbc 5792 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 171:3a7713b1edbc 5793 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5794 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5795 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5796 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5797 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 5798 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5799
AnnaBridge 171:3a7713b1edbc 5800 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 171:3a7713b1edbc 5801 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5802 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 5803 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 5804 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5805 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 171:3a7713b1edbc 5806 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 5807
AnnaBridge 171:3a7713b1edbc 5808 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 171:3a7713b1edbc 5809 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5810 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5811 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5812 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5813 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 5814 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 5815
AnnaBridge 171:3a7713b1edbc 5816 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 171:3a7713b1edbc 5817 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5818 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5819 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
AnnaBridge 171:3a7713b1edbc 5820
AnnaBridge 171:3a7713b1edbc 5821 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 171:3a7713b1edbc 5822 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5823 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 5824 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
AnnaBridge 171:3a7713b1edbc 5825
AnnaBridge 171:3a7713b1edbc 5826 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 171:3a7713b1edbc 5827 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5828 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5829 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 5830 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5831 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5832 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 5833
AnnaBridge 171:3a7713b1edbc 5834
AnnaBridge 171:3a7713b1edbc 5835 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5836 /* */
AnnaBridge 171:3a7713b1edbc 5837 /* Debug MCU */
AnnaBridge 171:3a7713b1edbc 5838 /* */
AnnaBridge 171:3a7713b1edbc 5839 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5840
AnnaBridge 171:3a7713b1edbc 5841 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5842 /* */
AnnaBridge 171:3a7713b1edbc 5843 /* DCMI */
AnnaBridge 171:3a7713b1edbc 5844 /* */
AnnaBridge 171:3a7713b1edbc 5845 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5846 /******************** Bits definition for DCMI_CR register ******************/
AnnaBridge 171:3a7713b1edbc 5847 #define DCMI_CR_CAPTURE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5848 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5849 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
AnnaBridge 171:3a7713b1edbc 5850 #define DCMI_CR_CM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5851 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5852 #define DCMI_CR_CM DCMI_CR_CM_Msk
AnnaBridge 171:3a7713b1edbc 5853 #define DCMI_CR_CROP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5854 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5855 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
AnnaBridge 171:3a7713b1edbc 5856 #define DCMI_CR_JPEG_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5857 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5858 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
AnnaBridge 171:3a7713b1edbc 5859 #define DCMI_CR_ESS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5860 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5861 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
AnnaBridge 171:3a7713b1edbc 5862 #define DCMI_CR_PCKPOL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5863 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5864 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
AnnaBridge 171:3a7713b1edbc 5865 #define DCMI_CR_HSPOL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5866 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5867 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
AnnaBridge 171:3a7713b1edbc 5868 #define DCMI_CR_VSPOL_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5869 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5870 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
AnnaBridge 171:3a7713b1edbc 5871 #define DCMI_CR_FCRC_0 0x00000100U
AnnaBridge 171:3a7713b1edbc 5872 #define DCMI_CR_FCRC_1 0x00000200U
AnnaBridge 171:3a7713b1edbc 5873 #define DCMI_CR_EDM_0 0x00000400U
AnnaBridge 171:3a7713b1edbc 5874 #define DCMI_CR_EDM_1 0x00000800U
AnnaBridge 171:3a7713b1edbc 5875 #define DCMI_CR_CRE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5876 #define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5877 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
AnnaBridge 171:3a7713b1edbc 5878 #define DCMI_CR_ENABLE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5879 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5880 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
AnnaBridge 171:3a7713b1edbc 5881 #define DCMI_CR_BSM_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5882 #define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 5883 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
AnnaBridge 171:3a7713b1edbc 5884 #define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5885 #define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5886 #define DCMI_CR_OEBS_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5887 #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5888 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
AnnaBridge 171:3a7713b1edbc 5889 #define DCMI_CR_LSM_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5890 #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5891 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
AnnaBridge 171:3a7713b1edbc 5892 #define DCMI_CR_OELS_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5893 #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5894 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
AnnaBridge 171:3a7713b1edbc 5895
AnnaBridge 171:3a7713b1edbc 5896 /******************** Bits definition for DCMI_SR register ******************/
AnnaBridge 171:3a7713b1edbc 5897 #define DCMI_SR_HSYNC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5898 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5899 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
AnnaBridge 171:3a7713b1edbc 5900 #define DCMI_SR_VSYNC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5901 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5902 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
AnnaBridge 171:3a7713b1edbc 5903 #define DCMI_SR_FNE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5904 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5905 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
AnnaBridge 171:3a7713b1edbc 5906
AnnaBridge 171:3a7713b1edbc 5907 /******************** Bits definition for DCMI_RIS register ****************/
AnnaBridge 171:3a7713b1edbc 5908 #define DCMI_RIS_FRAME_RIS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5909 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5910 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
AnnaBridge 171:3a7713b1edbc 5911 #define DCMI_RIS_OVR_RIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5912 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5913 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
AnnaBridge 171:3a7713b1edbc 5914 #define DCMI_RIS_ERR_RIS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5915 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5916 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
AnnaBridge 171:3a7713b1edbc 5917 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5918 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5919 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
AnnaBridge 171:3a7713b1edbc 5920 #define DCMI_RIS_LINE_RIS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5921 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5922 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
AnnaBridge 171:3a7713b1edbc 5923
AnnaBridge 171:3a7713b1edbc 5924 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5925 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
AnnaBridge 171:3a7713b1edbc 5926 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
AnnaBridge 171:3a7713b1edbc 5927 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
AnnaBridge 171:3a7713b1edbc 5928 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
AnnaBridge 171:3a7713b1edbc 5929 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
AnnaBridge 171:3a7713b1edbc 5930
AnnaBridge 171:3a7713b1edbc 5931 /******************** Bits definition for DCMI_IER register *****************/
AnnaBridge 171:3a7713b1edbc 5932 #define DCMI_IER_FRAME_IE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5933 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5934 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
AnnaBridge 171:3a7713b1edbc 5935 #define DCMI_IER_OVR_IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5936 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5937 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
AnnaBridge 171:3a7713b1edbc 5938 #define DCMI_IER_ERR_IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5939 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5940 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
AnnaBridge 171:3a7713b1edbc 5941 #define DCMI_IER_VSYNC_IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5942 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5943 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
AnnaBridge 171:3a7713b1edbc 5944 #define DCMI_IER_LINE_IE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5945 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5946 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
AnnaBridge 171:3a7713b1edbc 5947
AnnaBridge 171:3a7713b1edbc 5948 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 5949 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
AnnaBridge 171:3a7713b1edbc 5950
AnnaBridge 171:3a7713b1edbc 5951 /******************** Bits definition for DCMI_MIS register *****************/
AnnaBridge 171:3a7713b1edbc 5952 #define DCMI_MIS_FRAME_MIS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5953 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5954 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
AnnaBridge 171:3a7713b1edbc 5955 #define DCMI_MIS_OVR_MIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5956 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5957 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
AnnaBridge 171:3a7713b1edbc 5958 #define DCMI_MIS_ERR_MIS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5959 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5960 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
AnnaBridge 171:3a7713b1edbc 5961 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5962 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5963 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
AnnaBridge 171:3a7713b1edbc 5964 #define DCMI_MIS_LINE_MIS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5965 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5966 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
AnnaBridge 171:3a7713b1edbc 5967
AnnaBridge 171:3a7713b1edbc 5968 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5969 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
AnnaBridge 171:3a7713b1edbc 5970 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
AnnaBridge 171:3a7713b1edbc 5971 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
AnnaBridge 171:3a7713b1edbc 5972 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
AnnaBridge 171:3a7713b1edbc 5973 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
AnnaBridge 171:3a7713b1edbc 5974
AnnaBridge 171:3a7713b1edbc 5975 /******************** Bits definition for DCMI_ICR register *****************/
AnnaBridge 171:3a7713b1edbc 5976 #define DCMI_ICR_FRAME_ISC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5977 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5978 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
AnnaBridge 171:3a7713b1edbc 5979 #define DCMI_ICR_OVR_ISC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5980 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5981 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
AnnaBridge 171:3a7713b1edbc 5982 #define DCMI_ICR_ERR_ISC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5983 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5984 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
AnnaBridge 171:3a7713b1edbc 5985 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5986 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5987 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
AnnaBridge 171:3a7713b1edbc 5988 #define DCMI_ICR_LINE_ISC_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5989 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5990 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
AnnaBridge 171:3a7713b1edbc 5991
AnnaBridge 171:3a7713b1edbc 5992 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5993 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
AnnaBridge 171:3a7713b1edbc 5994
AnnaBridge 171:3a7713b1edbc 5995 /******************** Bits definition for DCMI_ESCR register ******************/
AnnaBridge 171:3a7713b1edbc 5996 #define DCMI_ESCR_FSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5997 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5998 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
AnnaBridge 171:3a7713b1edbc 5999 #define DCMI_ESCR_LSC_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6000 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6001 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
AnnaBridge 171:3a7713b1edbc 6002 #define DCMI_ESCR_LEC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6003 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 6004 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
AnnaBridge 171:3a7713b1edbc 6005 #define DCMI_ESCR_FEC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6006 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 6007 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
AnnaBridge 171:3a7713b1edbc 6008
AnnaBridge 171:3a7713b1edbc 6009 /******************** Bits definition for DCMI_ESUR register ******************/
AnnaBridge 171:3a7713b1edbc 6010 #define DCMI_ESUR_FSU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6011 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6012 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
AnnaBridge 171:3a7713b1edbc 6013 #define DCMI_ESUR_LSU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6014 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6015 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
AnnaBridge 171:3a7713b1edbc 6016 #define DCMI_ESUR_LEU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6017 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 6018 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
AnnaBridge 171:3a7713b1edbc 6019 #define DCMI_ESUR_FEU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6020 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 6021 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
AnnaBridge 171:3a7713b1edbc 6022
AnnaBridge 171:3a7713b1edbc 6023 /******************** Bits definition for DCMI_CWSTRT register ******************/
AnnaBridge 171:3a7713b1edbc 6024 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6025 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 6026 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
AnnaBridge 171:3a7713b1edbc 6027 #define DCMI_CWSTRT_VST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6028 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
AnnaBridge 171:3a7713b1edbc 6029 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
AnnaBridge 171:3a7713b1edbc 6030
AnnaBridge 171:3a7713b1edbc 6031 /******************** Bits definition for DCMI_CWSIZE register ******************/
AnnaBridge 171:3a7713b1edbc 6032 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6033 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 6034 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
AnnaBridge 171:3a7713b1edbc 6035 #define DCMI_CWSIZE_VLINE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6036 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
AnnaBridge 171:3a7713b1edbc 6037 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
AnnaBridge 171:3a7713b1edbc 6038
AnnaBridge 171:3a7713b1edbc 6039 /******************** Bits definition for DCMI_DR register ******************/
AnnaBridge 171:3a7713b1edbc 6040 #define DCMI_DR_BYTE0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6041 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6042 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
AnnaBridge 171:3a7713b1edbc 6043 #define DCMI_DR_BYTE1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6044 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6045 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
AnnaBridge 171:3a7713b1edbc 6046 #define DCMI_DR_BYTE2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6047 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 6048 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
AnnaBridge 171:3a7713b1edbc 6049 #define DCMI_DR_BYTE3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6050 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 6051 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
AnnaBridge 171:3a7713b1edbc 6052
AnnaBridge 171:3a7713b1edbc 6053 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6054 /* */
AnnaBridge 171:3a7713b1edbc 6055 /* DMA Controller */
AnnaBridge 171:3a7713b1edbc 6056 /* */
AnnaBridge 171:3a7713b1edbc 6057 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6058 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 171:3a7713b1edbc 6059 #define DMA_SxCR_CHSEL_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6060 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
AnnaBridge 171:3a7713b1edbc 6061 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
AnnaBridge 171:3a7713b1edbc 6062 #define DMA_SxCR_CHSEL_0 (0x1U << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6063 #define DMA_SxCR_CHSEL_1 (0x2U << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6064 #define DMA_SxCR_CHSEL_2 (0x4U << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6065 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6066 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 171:3a7713b1edbc 6067 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
AnnaBridge 171:3a7713b1edbc 6068 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6069 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6070 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6071 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 6072 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
AnnaBridge 171:3a7713b1edbc 6073 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6074 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6075 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6076 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6077 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
AnnaBridge 171:3a7713b1edbc 6078 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6079 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6080 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
AnnaBridge 171:3a7713b1edbc 6081 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6082 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 6083 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
AnnaBridge 171:3a7713b1edbc 6084 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6085 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6086 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6087 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6088 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
AnnaBridge 171:3a7713b1edbc 6089 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6090 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 6091 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
AnnaBridge 171:3a7713b1edbc 6092 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6093 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6094 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6095 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 6096 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
AnnaBridge 171:3a7713b1edbc 6097 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6098 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6099 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6100 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6101 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
AnnaBridge 171:3a7713b1edbc 6102 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6103 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6104 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
AnnaBridge 171:3a7713b1edbc 6105 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6106 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6107 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
AnnaBridge 171:3a7713b1edbc 6108 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6109 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 6110 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
AnnaBridge 171:3a7713b1edbc 6111 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6112 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6113 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6114 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6115 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
AnnaBridge 171:3a7713b1edbc 6116 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6117 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6118 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
AnnaBridge 171:3a7713b1edbc 6119 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6120 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6121 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
AnnaBridge 171:3a7713b1edbc 6122 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6123 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6124 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
AnnaBridge 171:3a7713b1edbc 6125 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6126 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6127 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
AnnaBridge 171:3a7713b1edbc 6128 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6129 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6130 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
AnnaBridge 171:3a7713b1edbc 6131
AnnaBridge 171:3a7713b1edbc 6132 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 171:3a7713b1edbc 6133 #define DMA_SxNDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6134 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6135 #define DMA_SxNDT DMA_SxNDT_Msk
AnnaBridge 171:3a7713b1edbc 6136 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6137 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6138 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6139 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6140 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6141 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6142 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6143 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6144 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6145 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6146 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6147 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6148 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6149 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6150 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6151 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6152
AnnaBridge 171:3a7713b1edbc 6153 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 171:3a7713b1edbc 6154 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6155 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6156 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
AnnaBridge 171:3a7713b1edbc 6157 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6158 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 6159 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
AnnaBridge 171:3a7713b1edbc 6160 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6161 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6162 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6163 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6164 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6165 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
AnnaBridge 171:3a7713b1edbc 6166 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6167 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 6168 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
AnnaBridge 171:3a7713b1edbc 6169 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6170 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6171
AnnaBridge 171:3a7713b1edbc 6172 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 171:3a7713b1edbc 6173 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6174 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6175 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
AnnaBridge 171:3a7713b1edbc 6176 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6177 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6178 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
AnnaBridge 171:3a7713b1edbc 6179 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6180 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6181 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
AnnaBridge 171:3a7713b1edbc 6182 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6183 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6184 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
AnnaBridge 171:3a7713b1edbc 6185 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6186 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6187 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
AnnaBridge 171:3a7713b1edbc 6188 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6189 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6190 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
AnnaBridge 171:3a7713b1edbc 6191 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6192 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6193 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
AnnaBridge 171:3a7713b1edbc 6194 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6195 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6196 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
AnnaBridge 171:3a7713b1edbc 6197 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6198 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6199 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
AnnaBridge 171:3a7713b1edbc 6200 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6201 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6202 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
AnnaBridge 171:3a7713b1edbc 6203 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6204 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6205 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
AnnaBridge 171:3a7713b1edbc 6206 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6207 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6208 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
AnnaBridge 171:3a7713b1edbc 6209 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6210 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6211 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
AnnaBridge 171:3a7713b1edbc 6212 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6213 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6214 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
AnnaBridge 171:3a7713b1edbc 6215 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6216 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6217 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
AnnaBridge 171:3a7713b1edbc 6218 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6219 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6220 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
AnnaBridge 171:3a7713b1edbc 6221 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6222 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6223 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
AnnaBridge 171:3a7713b1edbc 6224 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6225 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6226 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
AnnaBridge 171:3a7713b1edbc 6227 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6228 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6229 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
AnnaBridge 171:3a7713b1edbc 6230 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6231 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6232 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
AnnaBridge 171:3a7713b1edbc 6233
AnnaBridge 171:3a7713b1edbc 6234 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 171:3a7713b1edbc 6235 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6236 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6237 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
AnnaBridge 171:3a7713b1edbc 6238 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6239 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6240 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
AnnaBridge 171:3a7713b1edbc 6241 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6242 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6243 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
AnnaBridge 171:3a7713b1edbc 6244 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6245 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6246 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
AnnaBridge 171:3a7713b1edbc 6247 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6248 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6249 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
AnnaBridge 171:3a7713b1edbc 6250 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6251 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6252 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
AnnaBridge 171:3a7713b1edbc 6253 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6254 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6255 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
AnnaBridge 171:3a7713b1edbc 6256 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6257 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6258 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
AnnaBridge 171:3a7713b1edbc 6259 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6260 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6261 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
AnnaBridge 171:3a7713b1edbc 6262 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6263 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6264 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
AnnaBridge 171:3a7713b1edbc 6265 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6266 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6267 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
AnnaBridge 171:3a7713b1edbc 6268 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6269 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6270 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
AnnaBridge 171:3a7713b1edbc 6271 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6272 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6273 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
AnnaBridge 171:3a7713b1edbc 6274 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6275 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6276 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
AnnaBridge 171:3a7713b1edbc 6277 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6278 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6279 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
AnnaBridge 171:3a7713b1edbc 6280 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6281 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6282 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
AnnaBridge 171:3a7713b1edbc 6283 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6284 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6285 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
AnnaBridge 171:3a7713b1edbc 6286 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6287 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6288 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
AnnaBridge 171:3a7713b1edbc 6289 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6290 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6291 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
AnnaBridge 171:3a7713b1edbc 6292 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6293 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6294 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
AnnaBridge 171:3a7713b1edbc 6295
AnnaBridge 171:3a7713b1edbc 6296 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 171:3a7713b1edbc 6297 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6298 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6299 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
AnnaBridge 171:3a7713b1edbc 6300 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6301 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6302 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
AnnaBridge 171:3a7713b1edbc 6303 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6304 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6305 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
AnnaBridge 171:3a7713b1edbc 6306 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6307 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6308 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
AnnaBridge 171:3a7713b1edbc 6309 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6310 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6311 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
AnnaBridge 171:3a7713b1edbc 6312 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6313 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6314 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
AnnaBridge 171:3a7713b1edbc 6315 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6316 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6317 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
AnnaBridge 171:3a7713b1edbc 6318 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6319 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6320 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
AnnaBridge 171:3a7713b1edbc 6321 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6322 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6323 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
AnnaBridge 171:3a7713b1edbc 6324 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6325 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6326 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
AnnaBridge 171:3a7713b1edbc 6327 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6328 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6329 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
AnnaBridge 171:3a7713b1edbc 6330 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6331 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6332 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
AnnaBridge 171:3a7713b1edbc 6333 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6334 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6335 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
AnnaBridge 171:3a7713b1edbc 6336 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6337 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6338 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
AnnaBridge 171:3a7713b1edbc 6339 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6340 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6341 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
AnnaBridge 171:3a7713b1edbc 6342 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6343 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6344 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
AnnaBridge 171:3a7713b1edbc 6345 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6346 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6347 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
AnnaBridge 171:3a7713b1edbc 6348 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6349 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6350 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
AnnaBridge 171:3a7713b1edbc 6351 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6352 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6353 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
AnnaBridge 171:3a7713b1edbc 6354 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6355 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6356 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
AnnaBridge 171:3a7713b1edbc 6357
AnnaBridge 171:3a7713b1edbc 6358 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 171:3a7713b1edbc 6359 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6360 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6361 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
AnnaBridge 171:3a7713b1edbc 6362 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6363 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6364 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
AnnaBridge 171:3a7713b1edbc 6365 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6366 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6367 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
AnnaBridge 171:3a7713b1edbc 6368 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6369 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6370 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
AnnaBridge 171:3a7713b1edbc 6371 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6372 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6373 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
AnnaBridge 171:3a7713b1edbc 6374 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6375 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6376 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
AnnaBridge 171:3a7713b1edbc 6377 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6378 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6379 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
AnnaBridge 171:3a7713b1edbc 6380 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6381 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6382 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
AnnaBridge 171:3a7713b1edbc 6383 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6384 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6385 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
AnnaBridge 171:3a7713b1edbc 6386 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6387 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6388 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
AnnaBridge 171:3a7713b1edbc 6389 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6390 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6391 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
AnnaBridge 171:3a7713b1edbc 6392 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6393 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6394 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
AnnaBridge 171:3a7713b1edbc 6395 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6396 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6397 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
AnnaBridge 171:3a7713b1edbc 6398 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6399 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6400 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
AnnaBridge 171:3a7713b1edbc 6401 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6402 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6403 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
AnnaBridge 171:3a7713b1edbc 6404 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6405 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6406 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
AnnaBridge 171:3a7713b1edbc 6407 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6408 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6409 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
AnnaBridge 171:3a7713b1edbc 6410 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6411 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6412 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
AnnaBridge 171:3a7713b1edbc 6413 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6414 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6415 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
AnnaBridge 171:3a7713b1edbc 6416 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6417 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6418 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
AnnaBridge 171:3a7713b1edbc 6419
AnnaBridge 171:3a7713b1edbc 6420 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 171:3a7713b1edbc 6421 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6422 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6423 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 6424
AnnaBridge 171:3a7713b1edbc 6425 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 171:3a7713b1edbc 6426 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6427 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6428 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6429
AnnaBridge 171:3a7713b1edbc 6430 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 171:3a7713b1edbc 6431 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6432 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6433 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6434
AnnaBridge 171:3a7713b1edbc 6435 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6436 /* */
AnnaBridge 171:3a7713b1edbc 6437 /* AHB Master DMA2D Controller (DMA2D) */
AnnaBridge 171:3a7713b1edbc 6438 /* */
AnnaBridge 171:3a7713b1edbc 6439 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6440 /******************** Bit definition for DMA2D_CR register ******************/
AnnaBridge 171:3a7713b1edbc 6441
AnnaBridge 171:3a7713b1edbc 6442 #define DMA2D_CR_START_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6443 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6444 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
AnnaBridge 171:3a7713b1edbc 6445 #define DMA2D_CR_SUSP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6446 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6447 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
AnnaBridge 171:3a7713b1edbc 6448 #define DMA2D_CR_ABORT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6449 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6450 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
AnnaBridge 171:3a7713b1edbc 6451 #define DMA2D_CR_TEIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6452 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6453 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6454 #define DMA2D_CR_TCIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6455 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6456 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6457 #define DMA2D_CR_TWIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6458 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6459 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6460 #define DMA2D_CR_CAEIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6461 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6462 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6463 #define DMA2D_CR_CTCIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6464 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6465 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6466 #define DMA2D_CR_CEIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6467 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6468 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 6469 #define DMA2D_CR_MODE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6470 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 6471 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
AnnaBridge 171:3a7713b1edbc 6472 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6473 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6474
AnnaBridge 171:3a7713b1edbc 6475 /******************** Bit definition for DMA2D_ISR register *****************/
AnnaBridge 171:3a7713b1edbc 6476
AnnaBridge 171:3a7713b1edbc 6477 #define DMA2D_ISR_TEIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6478 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6479 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6480 #define DMA2D_ISR_TCIF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6481 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6482 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6483 #define DMA2D_ISR_TWIF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6484 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6485 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6486 #define DMA2D_ISR_CAEIF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6487 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6488 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6489 #define DMA2D_ISR_CTCIF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6490 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6491 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6492 #define DMA2D_ISR_CEIF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6493 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6494 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6495
AnnaBridge 171:3a7713b1edbc 6496 /******************** Bit definition for DMA2D_IFCR register ****************/
AnnaBridge 171:3a7713b1edbc 6497
AnnaBridge 171:3a7713b1edbc 6498 #define DMA2D_IFCR_CTEIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6499 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6500 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6501 #define DMA2D_IFCR_CTCIF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6502 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6503 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6504 #define DMA2D_IFCR_CTWIF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6505 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6506 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6507 #define DMA2D_IFCR_CAECIF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6508 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6509 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6510 #define DMA2D_IFCR_CCTCIF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6511 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6512 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6513 #define DMA2D_IFCR_CCEIF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6514 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6515 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6516
AnnaBridge 171:3a7713b1edbc 6517 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 6518 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6519 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6520 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6521 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6522 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6523 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6524
AnnaBridge 171:3a7713b1edbc 6525 /******************** Bit definition for DMA2D_FGMAR register ***************/
AnnaBridge 171:3a7713b1edbc 6526
AnnaBridge 171:3a7713b1edbc 6527 #define DMA2D_FGMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6528 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6529 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6530
AnnaBridge 171:3a7713b1edbc 6531 /******************** Bit definition for DMA2D_FGOR register ****************/
AnnaBridge 171:3a7713b1edbc 6532
AnnaBridge 171:3a7713b1edbc 6533 #define DMA2D_FGOR_LO_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6534 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 6535 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
AnnaBridge 171:3a7713b1edbc 6536
AnnaBridge 171:3a7713b1edbc 6537 /******************** Bit definition for DMA2D_BGMAR register ***************/
AnnaBridge 171:3a7713b1edbc 6538
AnnaBridge 171:3a7713b1edbc 6539 #define DMA2D_BGMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6540 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6541 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6542
AnnaBridge 171:3a7713b1edbc 6543 /******************** Bit definition for DMA2D_BGOR register ****************/
AnnaBridge 171:3a7713b1edbc 6544
AnnaBridge 171:3a7713b1edbc 6545 #define DMA2D_BGOR_LO_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6546 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 6547 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
AnnaBridge 171:3a7713b1edbc 6548
AnnaBridge 171:3a7713b1edbc 6549 /******************** Bit definition for DMA2D_FGPFCCR register *************/
AnnaBridge 171:3a7713b1edbc 6550
AnnaBridge 171:3a7713b1edbc 6551 #define DMA2D_FGPFCCR_CM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6552 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 6553 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
AnnaBridge 171:3a7713b1edbc 6554 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6555 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6556 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6557 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6558 #define DMA2D_FGPFCCR_CCM_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6559 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6560 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
AnnaBridge 171:3a7713b1edbc 6561 #define DMA2D_FGPFCCR_START_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6562 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6563 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
AnnaBridge 171:3a7713b1edbc 6564 #define DMA2D_FGPFCCR_CS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6565 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6566 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
AnnaBridge 171:3a7713b1edbc 6567 #define DMA2D_FGPFCCR_AM_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6568 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 6569 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
AnnaBridge 171:3a7713b1edbc 6570 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6571 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6572 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6573 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 6574 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
AnnaBridge 171:3a7713b1edbc 6575
AnnaBridge 171:3a7713b1edbc 6576 /******************** Bit definition for DMA2D_FGCOLR register **************/
AnnaBridge 171:3a7713b1edbc 6577
AnnaBridge 171:3a7713b1edbc 6578 #define DMA2D_FGCOLR_BLUE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6579 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6580 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
AnnaBridge 171:3a7713b1edbc 6581 #define DMA2D_FGCOLR_GREEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6582 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6583 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
AnnaBridge 171:3a7713b1edbc 6584 #define DMA2D_FGCOLR_RED_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6585 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 6586 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
AnnaBridge 171:3a7713b1edbc 6587
AnnaBridge 171:3a7713b1edbc 6588 /******************** Bit definition for DMA2D_BGPFCCR register *************/
AnnaBridge 171:3a7713b1edbc 6589
AnnaBridge 171:3a7713b1edbc 6590 #define DMA2D_BGPFCCR_CM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6591 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 6592 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
AnnaBridge 171:3a7713b1edbc 6593 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6594 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6595 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6596 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
AnnaBridge 171:3a7713b1edbc 6597 #define DMA2D_BGPFCCR_CCM_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6598 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6599 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
AnnaBridge 171:3a7713b1edbc 6600 #define DMA2D_BGPFCCR_START_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6601 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6602 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
AnnaBridge 171:3a7713b1edbc 6603 #define DMA2D_BGPFCCR_CS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6604 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6605 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
AnnaBridge 171:3a7713b1edbc 6606 #define DMA2D_BGPFCCR_AM_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6607 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 6608 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
AnnaBridge 171:3a7713b1edbc 6609 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6610 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6611 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6612 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 6613 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
AnnaBridge 171:3a7713b1edbc 6614
AnnaBridge 171:3a7713b1edbc 6615 /******************** Bit definition for DMA2D_BGCOLR register **************/
AnnaBridge 171:3a7713b1edbc 6616
AnnaBridge 171:3a7713b1edbc 6617 #define DMA2D_BGCOLR_BLUE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6618 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6619 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
AnnaBridge 171:3a7713b1edbc 6620 #define DMA2D_BGCOLR_GREEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6621 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6622 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
AnnaBridge 171:3a7713b1edbc 6623 #define DMA2D_BGCOLR_RED_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6624 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 6625 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
AnnaBridge 171:3a7713b1edbc 6626
AnnaBridge 171:3a7713b1edbc 6627 /******************** Bit definition for DMA2D_FGCMAR register **************/
AnnaBridge 171:3a7713b1edbc 6628
AnnaBridge 171:3a7713b1edbc 6629 #define DMA2D_FGCMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6630 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6631 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6632
AnnaBridge 171:3a7713b1edbc 6633 /******************** Bit definition for DMA2D_BGCMAR register **************/
AnnaBridge 171:3a7713b1edbc 6634
AnnaBridge 171:3a7713b1edbc 6635 #define DMA2D_BGCMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6636 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6637 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6638
AnnaBridge 171:3a7713b1edbc 6639 /******************** Bit definition for DMA2D_OPFCCR register **************/
AnnaBridge 171:3a7713b1edbc 6640
AnnaBridge 171:3a7713b1edbc 6641 #define DMA2D_OPFCCR_CM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6642 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 6643 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
AnnaBridge 171:3a7713b1edbc 6644 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6645 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6646 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6647
AnnaBridge 171:3a7713b1edbc 6648 /******************** Bit definition for DMA2D_OCOLR register ***************/
AnnaBridge 171:3a7713b1edbc 6649
AnnaBridge 171:3a7713b1edbc 6650 /*!<Mode_ARGB8888/RGB888 */
AnnaBridge 171:3a7713b1edbc 6651
AnnaBridge 171:3a7713b1edbc 6652 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
AnnaBridge 171:3a7713b1edbc 6653 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
AnnaBridge 171:3a7713b1edbc 6654 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
AnnaBridge 171:3a7713b1edbc 6655 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
AnnaBridge 171:3a7713b1edbc 6656
AnnaBridge 171:3a7713b1edbc 6657 /*!<Mode_RGB565 */
AnnaBridge 171:3a7713b1edbc 6658 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
AnnaBridge 171:3a7713b1edbc 6659 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
AnnaBridge 171:3a7713b1edbc 6660 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
AnnaBridge 171:3a7713b1edbc 6661
AnnaBridge 171:3a7713b1edbc 6662 /*!<Mode_ARGB1555 */
AnnaBridge 171:3a7713b1edbc 6663 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
AnnaBridge 171:3a7713b1edbc 6664 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
AnnaBridge 171:3a7713b1edbc 6665 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
AnnaBridge 171:3a7713b1edbc 6666 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
AnnaBridge 171:3a7713b1edbc 6667
AnnaBridge 171:3a7713b1edbc 6668 /*!<Mode_ARGB4444 */
AnnaBridge 171:3a7713b1edbc 6669 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
AnnaBridge 171:3a7713b1edbc 6670 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
AnnaBridge 171:3a7713b1edbc 6671 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
AnnaBridge 171:3a7713b1edbc 6672 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
AnnaBridge 171:3a7713b1edbc 6673
AnnaBridge 171:3a7713b1edbc 6674 /******************** Bit definition for DMA2D_OMAR register ****************/
AnnaBridge 171:3a7713b1edbc 6675
AnnaBridge 171:3a7713b1edbc 6676 #define DMA2D_OMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6677 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6678 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6679
AnnaBridge 171:3a7713b1edbc 6680 /******************** Bit definition for DMA2D_OOR register *****************/
AnnaBridge 171:3a7713b1edbc 6681
AnnaBridge 171:3a7713b1edbc 6682 #define DMA2D_OOR_LO_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6683 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 6684 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
AnnaBridge 171:3a7713b1edbc 6685
AnnaBridge 171:3a7713b1edbc 6686 /******************** Bit definition for DMA2D_NLR register *****************/
AnnaBridge 171:3a7713b1edbc 6687
AnnaBridge 171:3a7713b1edbc 6688 #define DMA2D_NLR_NL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6689 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6690 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
AnnaBridge 171:3a7713b1edbc 6691 #define DMA2D_NLR_PL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6692 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
AnnaBridge 171:3a7713b1edbc 6693 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
AnnaBridge 171:3a7713b1edbc 6694
AnnaBridge 171:3a7713b1edbc 6695 /******************** Bit definition for DMA2D_LWR register *****************/
AnnaBridge 171:3a7713b1edbc 6696
AnnaBridge 171:3a7713b1edbc 6697 #define DMA2D_LWR_LW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6698 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6699 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
AnnaBridge 171:3a7713b1edbc 6700
AnnaBridge 171:3a7713b1edbc 6701 /******************** Bit definition for DMA2D_AMTCR register ***************/
AnnaBridge 171:3a7713b1edbc 6702
AnnaBridge 171:3a7713b1edbc 6703 #define DMA2D_AMTCR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6704 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6705 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
AnnaBridge 171:3a7713b1edbc 6706 #define DMA2D_AMTCR_DT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6707 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6708 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
AnnaBridge 171:3a7713b1edbc 6709
AnnaBridge 171:3a7713b1edbc 6710
AnnaBridge 171:3a7713b1edbc 6711 /******************** Bit definition for DMA2D_FGCLUT register **************/
AnnaBridge 171:3a7713b1edbc 6712
AnnaBridge 171:3a7713b1edbc 6713 /******************** Bit definition for DMA2D_BGCLUT register **************/
AnnaBridge 171:3a7713b1edbc 6714
AnnaBridge 171:3a7713b1edbc 6715 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6716 /* */
AnnaBridge 171:3a7713b1edbc 6717 /* External Interrupt/Event Controller */
AnnaBridge 171:3a7713b1edbc 6718 /* */
AnnaBridge 171:3a7713b1edbc 6719 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6720 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 171:3a7713b1edbc 6721 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6722 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6723 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 6724 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6725 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6726 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 6727 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6728 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6729 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 6730 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6731 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6732 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 6733 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6734 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6735 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 6736 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6737 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6738 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 6739 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6740 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6741 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 6742 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6743 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6744 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 6745 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6746 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6747 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 6748 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6749 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6750 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 6751 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6752 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6753 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 6754 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6755 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6756 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 6757 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6758 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6759 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 6760 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6761 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6762 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 6763 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6764 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6765 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 6766 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6767 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6768 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 6769 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6770 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6771 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 6772 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6773 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6774 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 6775 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6776 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6777 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 6778 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6779 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6780 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 6781 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6782 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6783 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 6784 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6785 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6786 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 6787 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6788 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6789 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 6790 #define EXTI_IMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6791 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6792 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 6793
AnnaBridge 171:3a7713b1edbc 6794 /* Reference Defines */
AnnaBridge 171:3a7713b1edbc 6795 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 171:3a7713b1edbc 6796 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 171:3a7713b1edbc 6797 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 171:3a7713b1edbc 6798 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 171:3a7713b1edbc 6799 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 171:3a7713b1edbc 6800 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 171:3a7713b1edbc 6801 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 171:3a7713b1edbc 6802 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 171:3a7713b1edbc 6803 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 171:3a7713b1edbc 6804 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 171:3a7713b1edbc 6805 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 171:3a7713b1edbc 6806 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 171:3a7713b1edbc 6807 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 171:3a7713b1edbc 6808 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 171:3a7713b1edbc 6809 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 171:3a7713b1edbc 6810 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 171:3a7713b1edbc 6811 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 171:3a7713b1edbc 6812 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 171:3a7713b1edbc 6813 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 171:3a7713b1edbc 6814 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 171:3a7713b1edbc 6815 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 171:3a7713b1edbc 6816 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 171:3a7713b1edbc 6817 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 171:3a7713b1edbc 6818 #define EXTI_IMR_IM23 EXTI_IMR_MR23
AnnaBridge 171:3a7713b1edbc 6819
AnnaBridge 171:3a7713b1edbc 6820 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6821 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 6822 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 171:3a7713b1edbc 6823
AnnaBridge 171:3a7713b1edbc 6824 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 171:3a7713b1edbc 6825 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6826 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6827 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 6828 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6829 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6830 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 6831 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6832 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6833 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 6834 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6835 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6836 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 6837 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6838 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6839 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 6840 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6841 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6842 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 6843 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6844 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6845 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 6846 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6847 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6848 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 6849 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6850 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6851 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 6852 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6853 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6854 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 6855 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6856 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6857 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 6858 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6859 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6860 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 6861 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6862 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6863 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 6864 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6865 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6866 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 6867 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6868 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6869 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 6870 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6871 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6872 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 6873 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6874 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6875 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 6876 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6877 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6878 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 6879 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6880 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6881 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 6882 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6883 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6884 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 6885 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6886 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6887 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 6888 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6889 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6890 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 6891 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6892 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6893 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 6894 #define EXTI_EMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6895 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6896 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 6897
AnnaBridge 171:3a7713b1edbc 6898 /* Reference Defines */
AnnaBridge 171:3a7713b1edbc 6899 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 171:3a7713b1edbc 6900 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 171:3a7713b1edbc 6901 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 171:3a7713b1edbc 6902 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 171:3a7713b1edbc 6903 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 171:3a7713b1edbc 6904 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 171:3a7713b1edbc 6905 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 171:3a7713b1edbc 6906 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 171:3a7713b1edbc 6907 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 171:3a7713b1edbc 6908 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 171:3a7713b1edbc 6909 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 171:3a7713b1edbc 6910 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 171:3a7713b1edbc 6911 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 171:3a7713b1edbc 6912 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 171:3a7713b1edbc 6913 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 171:3a7713b1edbc 6914 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 171:3a7713b1edbc 6915 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 171:3a7713b1edbc 6916 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 171:3a7713b1edbc 6917 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 171:3a7713b1edbc 6918 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 171:3a7713b1edbc 6919 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 171:3a7713b1edbc 6920 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 171:3a7713b1edbc 6921 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 171:3a7713b1edbc 6922 #define EXTI_EMR_EM23 EXTI_EMR_MR23
AnnaBridge 171:3a7713b1edbc 6923
AnnaBridge 171:3a7713b1edbc 6924
AnnaBridge 171:3a7713b1edbc 6925 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 171:3a7713b1edbc 6926 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6927 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6928 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 6929 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6930 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6931 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 6932 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6933 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6934 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 6935 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6936 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6937 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 6938 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6939 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6940 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 6941 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6942 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6943 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 6944 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6945 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6946 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 6947 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6948 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6949 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 6950 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6951 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6952 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 6953 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6954 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6955 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 6956 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6957 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6958 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 6959 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6960 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6961 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 6962 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6963 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6964 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 6965 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6966 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6967 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 6968 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6969 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6970 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 6971 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6972 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6973 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 6974 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6975 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6976 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 6977 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6978 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6979 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 6980 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6981 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6982 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 171:3a7713b1edbc 6983 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6984 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6985 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 6986 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6987 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6988 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 6989 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6990 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6991 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 6992 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6993 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6994 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 6995 #define EXTI_RTSR_TR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6996 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6997 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
AnnaBridge 171:3a7713b1edbc 6998
AnnaBridge 171:3a7713b1edbc 6999 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 171:3a7713b1edbc 7000 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7001 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7002 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 7003 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7004 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7005 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 7006 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7007 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7008 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 7009 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7010 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7011 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 7012 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7013 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7014 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 7015 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7016 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7017 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 7018 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7019 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7020 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 7021 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7022 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7023 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 7024 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7025 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7026 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 7027 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7028 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7029 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 7030 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7031 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7032 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 7033 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7034 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7035 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 7036 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7037 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7038 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 7039 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7040 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7041 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 7042 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7043 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7044 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 7045 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7046 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7047 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 7048 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7049 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7050 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 7051 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 7052 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7053 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 7054 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7055 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7056 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 171:3a7713b1edbc 7057 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7058 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7059 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 7060 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7061 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7062 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 7063 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 7064 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7065 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 7066 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7067 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7068 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 7069 #define EXTI_FTSR_TR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 7070 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7071 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
AnnaBridge 171:3a7713b1edbc 7072
AnnaBridge 171:3a7713b1edbc 7073 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 171:3a7713b1edbc 7074 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7075 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7076 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 171:3a7713b1edbc 7077 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7078 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7079 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 171:3a7713b1edbc 7080 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7081 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7082 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 171:3a7713b1edbc 7083 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7084 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7085 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 171:3a7713b1edbc 7086 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7087 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7088 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 171:3a7713b1edbc 7089 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7090 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7091 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 171:3a7713b1edbc 7092 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7093 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7094 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 171:3a7713b1edbc 7095 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7096 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7097 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 171:3a7713b1edbc 7098 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7099 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7100 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 171:3a7713b1edbc 7101 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7102 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7103 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 171:3a7713b1edbc 7104 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7105 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7106 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 171:3a7713b1edbc 7107 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7108 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7109 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 171:3a7713b1edbc 7110 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7111 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7112 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 171:3a7713b1edbc 7113 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7114 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7115 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 171:3a7713b1edbc 7116 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7117 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7118 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 171:3a7713b1edbc 7119 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7120 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7121 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 171:3a7713b1edbc 7122 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7123 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7124 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 171:3a7713b1edbc 7125 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 7126 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7127 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 171:3a7713b1edbc 7128 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7129 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7130 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 171:3a7713b1edbc 7131 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7132 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7133 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 171:3a7713b1edbc 7134 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7135 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7136 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 171:3a7713b1edbc 7137 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 7138 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7139 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 171:3a7713b1edbc 7140 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7141 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7142 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 171:3a7713b1edbc 7143 #define EXTI_SWIER_SWIER23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 7144 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7145 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
AnnaBridge 171:3a7713b1edbc 7146
AnnaBridge 171:3a7713b1edbc 7147 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 171:3a7713b1edbc 7148 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7149 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7150 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 171:3a7713b1edbc 7151 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7152 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7153 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 171:3a7713b1edbc 7154 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7155 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7156 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 171:3a7713b1edbc 7157 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7158 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7159 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 171:3a7713b1edbc 7160 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7161 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7162 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 171:3a7713b1edbc 7163 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7164 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7165 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 171:3a7713b1edbc 7166 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7167 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7168 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 171:3a7713b1edbc 7169 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7170 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7171 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 171:3a7713b1edbc 7172 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7173 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7174 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 171:3a7713b1edbc 7175 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7176 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7177 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 171:3a7713b1edbc 7178 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7179 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7180 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 171:3a7713b1edbc 7181 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7182 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7183 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 171:3a7713b1edbc 7184 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7185 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7186 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 171:3a7713b1edbc 7187 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7188 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7189 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 171:3a7713b1edbc 7190 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7191 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7192 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 171:3a7713b1edbc 7193 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7194 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7195 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 171:3a7713b1edbc 7196 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7197 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7198 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 171:3a7713b1edbc 7199 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 7200 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7201 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 171:3a7713b1edbc 7202 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7203 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7204 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 171:3a7713b1edbc 7205 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7206 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7207 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 171:3a7713b1edbc 7208 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7209 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7210 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 171:3a7713b1edbc 7211 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 7212 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7213 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 171:3a7713b1edbc 7214 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7215 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7216 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
AnnaBridge 171:3a7713b1edbc 7217 #define EXTI_PR_PR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 7218 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7219 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
AnnaBridge 171:3a7713b1edbc 7220
AnnaBridge 171:3a7713b1edbc 7221 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7222 /* */
AnnaBridge 171:3a7713b1edbc 7223 /* FLASH */
AnnaBridge 171:3a7713b1edbc 7224 /* */
AnnaBridge 171:3a7713b1edbc 7225 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7226 /*
AnnaBridge 171:3a7713b1edbc 7227 * @brief FLASH Total Sectors Number
AnnaBridge 171:3a7713b1edbc 7228 */
AnnaBridge 171:3a7713b1edbc 7229 #define FLASH_SECTOR_TOTAL 8
AnnaBridge 171:3a7713b1edbc 7230
AnnaBridge 171:3a7713b1edbc 7231 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 171:3a7713b1edbc 7232 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7233 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7234 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 171:3a7713b1edbc 7235 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 171:3a7713b1edbc 7236 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 171:3a7713b1edbc 7237 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 171:3a7713b1edbc 7238 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 171:3a7713b1edbc 7239 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 171:3a7713b1edbc 7240 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 171:3a7713b1edbc 7241 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 171:3a7713b1edbc 7242 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 171:3a7713b1edbc 7243 #define FLASH_ACR_LATENCY_8WS 0x00000008U
AnnaBridge 171:3a7713b1edbc 7244 #define FLASH_ACR_LATENCY_9WS 0x00000009U
AnnaBridge 171:3a7713b1edbc 7245 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
AnnaBridge 171:3a7713b1edbc 7246 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
AnnaBridge 171:3a7713b1edbc 7247 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
AnnaBridge 171:3a7713b1edbc 7248 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
AnnaBridge 171:3a7713b1edbc 7249 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
AnnaBridge 171:3a7713b1edbc 7250 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
AnnaBridge 171:3a7713b1edbc 7251 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7252 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7253 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 171:3a7713b1edbc 7254 #define FLASH_ACR_ARTEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7255 #define FLASH_ACR_ARTEN_Msk (0x1U << FLASH_ACR_ARTEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7256 #define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
AnnaBridge 171:3a7713b1edbc 7257 #define FLASH_ACR_ARTRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7258 #define FLASH_ACR_ARTRST_Msk (0x1U << FLASH_ACR_ARTRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7259 #define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
AnnaBridge 171:3a7713b1edbc 7260
AnnaBridge 171:3a7713b1edbc 7261 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 171:3a7713b1edbc 7262 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7263 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7264 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 171:3a7713b1edbc 7265 #define FLASH_SR_OPERR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7266 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7267 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
AnnaBridge 171:3a7713b1edbc 7268 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7269 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7270 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 171:3a7713b1edbc 7271 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7272 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7273 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 171:3a7713b1edbc 7274 #define FLASH_SR_PGPERR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7275 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7276 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
AnnaBridge 171:3a7713b1edbc 7277 #define FLASH_SR_ERSERR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7278 #define FLASH_SR_ERSERR_Msk (0x1U << FLASH_SR_ERSERR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7279 #define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
AnnaBridge 171:3a7713b1edbc 7280 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7281 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7282 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
AnnaBridge 171:3a7713b1edbc 7283
AnnaBridge 171:3a7713b1edbc 7284 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 171:3a7713b1edbc 7285 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7286 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7287 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 171:3a7713b1edbc 7288 #define FLASH_CR_SER_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7289 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7290 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 171:3a7713b1edbc 7291 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7292 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7293 #define FLASH_CR_MER FLASH_CR_MER_Msk
AnnaBridge 171:3a7713b1edbc 7294 #define FLASH_CR_SNB_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7295 #define FLASH_CR_SNB_Msk (0xFU << FLASH_CR_SNB_Pos) /*!< 0x00000078 */
AnnaBridge 171:3a7713b1edbc 7296 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 171:3a7713b1edbc 7297 #define FLASH_CR_SNB_0 0x00000008U
AnnaBridge 171:3a7713b1edbc 7298 #define FLASH_CR_SNB_1 0x00000010U
AnnaBridge 171:3a7713b1edbc 7299 #define FLASH_CR_SNB_2 0x00000020U
AnnaBridge 171:3a7713b1edbc 7300 #define FLASH_CR_SNB_3 0x00000040U
AnnaBridge 171:3a7713b1edbc 7301 #define FLASH_CR_PSIZE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7302 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 7303 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 171:3a7713b1edbc 7304 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7305 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7306 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7307 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7308 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 171:3a7713b1edbc 7309 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7310 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7311 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 171:3a7713b1edbc 7312 #define FLASH_CR_ERRIE_Pos (25U)
AnnaBridge 171:3a7713b1edbc 7313 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7314 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
AnnaBridge 171:3a7713b1edbc 7315 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 7316 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7317 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
AnnaBridge 171:3a7713b1edbc 7318
AnnaBridge 171:3a7713b1edbc 7319 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 171:3a7713b1edbc 7320 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7321 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7322 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 171:3a7713b1edbc 7323 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7324 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7325 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
AnnaBridge 171:3a7713b1edbc 7326 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7327 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7328 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
AnnaBridge 171:3a7713b1edbc 7329 #define FLASH_OPTCR_BOR_LEV_0 (0x1U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7330 #define FLASH_OPTCR_BOR_LEV_1 (0x2U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7331 #define FLASH_OPTCR_WWDG_SW_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7332 #define FLASH_OPTCR_WWDG_SW_Msk (0x1U << FLASH_OPTCR_WWDG_SW_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7333 #define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
AnnaBridge 171:3a7713b1edbc 7334 #define FLASH_OPTCR_IWDG_SW_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7335 #define FLASH_OPTCR_IWDG_SW_Msk (0x1U << FLASH_OPTCR_IWDG_SW_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7336 #define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
AnnaBridge 171:3a7713b1edbc 7337 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7338 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7339 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7340 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7341 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7342 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
AnnaBridge 171:3a7713b1edbc 7343 #define FLASH_OPTCR_RDP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7344 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7345 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
AnnaBridge 171:3a7713b1edbc 7346 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7347 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7348 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7349 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7350 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7351 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7352 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7353 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7354 #define FLASH_OPTCR_nWRP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7355 #define FLASH_OPTCR_nWRP_Msk (0xFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 7356 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
AnnaBridge 171:3a7713b1edbc 7357 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 171:3a7713b1edbc 7358 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 171:3a7713b1edbc 7359 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 171:3a7713b1edbc 7360 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 171:3a7713b1edbc 7361 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 171:3a7713b1edbc 7362 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 171:3a7713b1edbc 7363 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 171:3a7713b1edbc 7364 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 171:3a7713b1edbc 7365 #define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7366 #define FLASH_OPTCR_IWDG_STDBY_Msk (0x1U << FLASH_OPTCR_IWDG_STDBY_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7367 #define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
AnnaBridge 171:3a7713b1edbc 7368 #define FLASH_OPTCR_IWDG_STOP_Pos (31U)
AnnaBridge 171:3a7713b1edbc 7369 #define FLASH_OPTCR_IWDG_STOP_Msk (0x1U << FLASH_OPTCR_IWDG_STOP_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7370 #define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 7371
AnnaBridge 171:3a7713b1edbc 7372 /******************* Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 171:3a7713b1edbc 7373 #define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7374 #define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFU << FLASH_OPTCR1_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7375 #define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
AnnaBridge 171:3a7713b1edbc 7376 #define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7377 #define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFU << FLASH_OPTCR1_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 7378 #define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
AnnaBridge 171:3a7713b1edbc 7379
AnnaBridge 171:3a7713b1edbc 7380
AnnaBridge 171:3a7713b1edbc 7381 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7382 /* */
AnnaBridge 171:3a7713b1edbc 7383 /* Flexible Memory Controller */
AnnaBridge 171:3a7713b1edbc 7384 /* */
AnnaBridge 171:3a7713b1edbc 7385 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7386 /****************** Bit definition for FMC_BCR1 register *******************/
AnnaBridge 171:3a7713b1edbc 7387 #define FMC_BCR1_MBKEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7388 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7389 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 171:3a7713b1edbc 7390 #define FMC_BCR1_MUXEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7391 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7392 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 171:3a7713b1edbc 7393 #define FMC_BCR1_MTYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7394 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7395 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 171:3a7713b1edbc 7396 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7397 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7398 #define FMC_BCR1_MWID_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7399 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7400 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 171:3a7713b1edbc 7401 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7402 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7403 #define FMC_BCR1_FACCEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7404 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7405 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 171:3a7713b1edbc 7406 #define FMC_BCR1_BURSTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7407 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7408 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 171:3a7713b1edbc 7409 #define FMC_BCR1_WAITPOL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7410 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7411 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 171:3a7713b1edbc 7412 #define FMC_BCR1_WRAPMOD_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7413 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7414 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 171:3a7713b1edbc 7415 #define FMC_BCR1_WAITCFG_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7416 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7417 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 171:3a7713b1edbc 7418 #define FMC_BCR1_WREN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7419 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7420 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
AnnaBridge 171:3a7713b1edbc 7421 #define FMC_BCR1_WAITEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7422 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7423 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 171:3a7713b1edbc 7424 #define FMC_BCR1_EXTMOD_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7425 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7426 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 171:3a7713b1edbc 7427 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7428 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7429 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 171:3a7713b1edbc 7430 #define FMC_BCR1_CPSIZE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7431 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 7432 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 171:3a7713b1edbc 7433 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7434 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7435 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7436 #define FMC_BCR1_CBURSTRW_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7437 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7438 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 171:3a7713b1edbc 7439 #define FMC_BCR1_CCLKEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7440 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7441 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
AnnaBridge 171:3a7713b1edbc 7442 #define FMC_BCR1_WFDIS_Pos (21U)
AnnaBridge 171:3a7713b1edbc 7443 #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7444 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
AnnaBridge 171:3a7713b1edbc 7445
AnnaBridge 171:3a7713b1edbc 7446 /****************** Bit definition for FMC_BCR2 register *******************/
AnnaBridge 171:3a7713b1edbc 7447 #define FMC_BCR2_MBKEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7448 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7449 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 171:3a7713b1edbc 7450 #define FMC_BCR2_MUXEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7451 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7452 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 171:3a7713b1edbc 7453 #define FMC_BCR2_MTYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7454 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7455 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 171:3a7713b1edbc 7456 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7457 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7458 #define FMC_BCR2_MWID_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7459 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7460 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 171:3a7713b1edbc 7461 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7462 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7463 #define FMC_BCR2_FACCEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7464 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7465 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 171:3a7713b1edbc 7466 #define FMC_BCR2_BURSTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7467 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7468 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 171:3a7713b1edbc 7469 #define FMC_BCR2_WAITPOL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7470 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7471 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 171:3a7713b1edbc 7472 #define FMC_BCR2_WRAPMOD_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7473 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7474 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 171:3a7713b1edbc 7475 #define FMC_BCR2_WAITCFG_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7476 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7477 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 171:3a7713b1edbc 7478 #define FMC_BCR2_WREN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7479 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7480 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
AnnaBridge 171:3a7713b1edbc 7481 #define FMC_BCR2_WAITEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7482 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7483 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 171:3a7713b1edbc 7484 #define FMC_BCR2_EXTMOD_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7485 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7486 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 171:3a7713b1edbc 7487 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7488 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7489 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 171:3a7713b1edbc 7490 #define FMC_BCR2_CPSIZE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7491 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 7492 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 171:3a7713b1edbc 7493 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7494 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7495 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7496 #define FMC_BCR2_CBURSTRW_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7497 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7498 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 171:3a7713b1edbc 7499
AnnaBridge 171:3a7713b1edbc 7500 /****************** Bit definition for FMC_BCR3 register *******************/
AnnaBridge 171:3a7713b1edbc 7501 #define FMC_BCR3_MBKEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7502 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7503 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 171:3a7713b1edbc 7504 #define FMC_BCR3_MUXEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7505 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7506 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 171:3a7713b1edbc 7507 #define FMC_BCR3_MTYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7508 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7509 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 171:3a7713b1edbc 7510 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7511 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7512 #define FMC_BCR3_MWID_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7513 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7514 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 171:3a7713b1edbc 7515 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7516 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7517 #define FMC_BCR3_FACCEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7518 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7519 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 171:3a7713b1edbc 7520 #define FMC_BCR3_BURSTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7521 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7522 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 171:3a7713b1edbc 7523 #define FMC_BCR3_WAITPOL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7524 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7525 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 171:3a7713b1edbc 7526 #define FMC_BCR3_WRAPMOD_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7527 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7528 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 171:3a7713b1edbc 7529 #define FMC_BCR3_WAITCFG_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7530 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7531 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 171:3a7713b1edbc 7532 #define FMC_BCR3_WREN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7533 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7534 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
AnnaBridge 171:3a7713b1edbc 7535 #define FMC_BCR3_WAITEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7536 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7537 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 171:3a7713b1edbc 7538 #define FMC_BCR3_EXTMOD_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7539 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7540 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 171:3a7713b1edbc 7541 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7542 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7543 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 171:3a7713b1edbc 7544 #define FMC_BCR3_CPSIZE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7545 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 7546 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 171:3a7713b1edbc 7547 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7548 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7549 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7550 #define FMC_BCR3_CBURSTRW_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7551 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7552 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 171:3a7713b1edbc 7553
AnnaBridge 171:3a7713b1edbc 7554 /****************** Bit definition for FMC_BCR4 register *******************/
AnnaBridge 171:3a7713b1edbc 7555 #define FMC_BCR4_MBKEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7556 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7557 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 171:3a7713b1edbc 7558 #define FMC_BCR4_MUXEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7559 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7560 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 171:3a7713b1edbc 7561 #define FMC_BCR4_MTYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7562 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7563 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 171:3a7713b1edbc 7564 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7565 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7566 #define FMC_BCR4_MWID_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7567 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7568 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 171:3a7713b1edbc 7569 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7570 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7571 #define FMC_BCR4_FACCEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7572 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7573 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 171:3a7713b1edbc 7574 #define FMC_BCR4_BURSTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7575 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7576 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 171:3a7713b1edbc 7577 #define FMC_BCR4_WAITPOL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7578 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7579 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 171:3a7713b1edbc 7580 #define FMC_BCR4_WRAPMOD_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7581 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7582 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 171:3a7713b1edbc 7583 #define FMC_BCR4_WAITCFG_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7584 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7585 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 171:3a7713b1edbc 7586 #define FMC_BCR4_WREN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7587 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7588 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
AnnaBridge 171:3a7713b1edbc 7589 #define FMC_BCR4_WAITEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7590 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7591 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 171:3a7713b1edbc 7592 #define FMC_BCR4_EXTMOD_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7593 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7594 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 171:3a7713b1edbc 7595 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7596 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7597 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 171:3a7713b1edbc 7598 #define FMC_BCR4_CPSIZE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7599 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 7600 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 171:3a7713b1edbc 7601 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7602 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7603 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7604 #define FMC_BCR4_CBURSTRW_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7605 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7606 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 171:3a7713b1edbc 7607
AnnaBridge 171:3a7713b1edbc 7608 /****************** Bit definition for FMC_BTR1 register ******************/
AnnaBridge 171:3a7713b1edbc 7609 #define FMC_BTR1_ADDSET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7610 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7611 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 171:3a7713b1edbc 7612 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7613 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7614 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7615 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7616 #define FMC_BTR1_ADDHLD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7617 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7618 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 171:3a7713b1edbc 7619 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7620 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7621 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7622 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7623 #define FMC_BTR1_DATAST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7624 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7625 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 171:3a7713b1edbc 7626 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7627 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7628 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7629 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7630 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7631 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7632 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7633 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7634 #define FMC_BTR1_BUSTURN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7635 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7636 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 171:3a7713b1edbc 7637 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7638 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7639 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7640 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7641 #define FMC_BTR1_CLKDIV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7642 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 7643 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 171:3a7713b1edbc 7644 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7645 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7646 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7647 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7648 #define FMC_BTR1_DATLAT_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7649 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 7650 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 171:3a7713b1edbc 7651 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7652 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7653 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7654 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7655 #define FMC_BTR1_ACCMOD_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7656 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7657 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 171:3a7713b1edbc 7658 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7659 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7660
AnnaBridge 171:3a7713b1edbc 7661 /****************** Bit definition for FMC_BTR2 register *******************/
AnnaBridge 171:3a7713b1edbc 7662 #define FMC_BTR2_ADDSET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7663 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7664 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 171:3a7713b1edbc 7665 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7666 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7667 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7668 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7669 #define FMC_BTR2_ADDHLD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7670 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7671 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 171:3a7713b1edbc 7672 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7673 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7674 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7675 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7676 #define FMC_BTR2_DATAST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7677 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7678 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 171:3a7713b1edbc 7679 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7680 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7681 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7682 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7683 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7684 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7685 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7686 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7687 #define FMC_BTR2_BUSTURN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7688 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7689 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 171:3a7713b1edbc 7690 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7691 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7692 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7693 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7694 #define FMC_BTR2_CLKDIV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7695 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 7696 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 171:3a7713b1edbc 7697 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7698 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7699 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7700 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7701 #define FMC_BTR2_DATLAT_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7702 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 7703 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 171:3a7713b1edbc 7704 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7705 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7706 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7707 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7708 #define FMC_BTR2_ACCMOD_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7709 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7710 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 171:3a7713b1edbc 7711 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7712 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7713
AnnaBridge 171:3a7713b1edbc 7714 /******************* Bit definition for FMC_BTR3 register *******************/
AnnaBridge 171:3a7713b1edbc 7715 #define FMC_BTR3_ADDSET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7716 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7717 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 171:3a7713b1edbc 7718 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7719 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7720 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7721 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7722 #define FMC_BTR3_ADDHLD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7723 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7724 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 171:3a7713b1edbc 7725 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7726 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7727 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7728 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7729 #define FMC_BTR3_DATAST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7730 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7731 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 171:3a7713b1edbc 7732 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7733 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7734 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7735 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7736 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7737 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7738 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7739 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7740 #define FMC_BTR3_BUSTURN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7741 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7742 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 171:3a7713b1edbc 7743 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7744 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7745 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7746 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7747 #define FMC_BTR3_CLKDIV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7748 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 7749 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 171:3a7713b1edbc 7750 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7751 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7752 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7753 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7754 #define FMC_BTR3_DATLAT_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7755 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 7756 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 171:3a7713b1edbc 7757 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7758 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7759 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7760 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7761 #define FMC_BTR3_ACCMOD_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7762 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7763 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 171:3a7713b1edbc 7764 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7765 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7766
AnnaBridge 171:3a7713b1edbc 7767 /****************** Bit definition for FMC_BTR4 register *******************/
AnnaBridge 171:3a7713b1edbc 7768 #define FMC_BTR4_ADDSET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7769 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7770 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 171:3a7713b1edbc 7771 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7772 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7773 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7774 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7775 #define FMC_BTR4_ADDHLD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7776 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7777 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 171:3a7713b1edbc 7778 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7779 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7780 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7781 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7782 #define FMC_BTR4_DATAST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7783 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7784 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 171:3a7713b1edbc 7785 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7786 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7787 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7788 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7789 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7790 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7791 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7792 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7793 #define FMC_BTR4_BUSTURN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7794 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7795 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 171:3a7713b1edbc 7796 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7797 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7798 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7799 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7800 #define FMC_BTR4_CLKDIV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7801 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 7802 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 171:3a7713b1edbc 7803 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7804 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7805 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7806 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7807 #define FMC_BTR4_DATLAT_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7808 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 7809 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 171:3a7713b1edbc 7810 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7811 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7812 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7813 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7814 #define FMC_BTR4_ACCMOD_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7815 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7816 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 171:3a7713b1edbc 7817 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7818 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7819
AnnaBridge 171:3a7713b1edbc 7820 /****************** Bit definition for FMC_BWTR1 register ******************/
AnnaBridge 171:3a7713b1edbc 7821 #define FMC_BWTR1_ADDSET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7822 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7823 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 171:3a7713b1edbc 7824 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7825 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7826 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7827 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7828 #define FMC_BWTR1_ADDHLD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7829 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7830 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 171:3a7713b1edbc 7831 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7832 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7833 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7834 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7835 #define FMC_BWTR1_DATAST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7836 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7837 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 171:3a7713b1edbc 7838 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7839 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7840 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7841 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7842 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7843 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7844 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7845 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7846 #define FMC_BWTR1_BUSTURN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7847 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7848 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 171:3a7713b1edbc 7849 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7850 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7851 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7852 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7853 #define FMC_BWTR1_ACCMOD_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7854 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7855 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 171:3a7713b1edbc 7856 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7857 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7858
AnnaBridge 171:3a7713b1edbc 7859 /****************** Bit definition for FMC_BWTR2 register ******************/
AnnaBridge 171:3a7713b1edbc 7860 #define FMC_BWTR2_ADDSET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7861 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7862 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 171:3a7713b1edbc 7863 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7864 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7865 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7866 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7867 #define FMC_BWTR2_ADDHLD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7868 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7869 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 171:3a7713b1edbc 7870 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7871 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7872 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7873 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7874 #define FMC_BWTR2_DATAST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7875 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7876 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 171:3a7713b1edbc 7877 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7878 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7879 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7880 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7881 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7882 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7883 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7884 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7885 #define FMC_BWTR2_BUSTURN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7886 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7887 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 171:3a7713b1edbc 7888 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7889 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7890 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7891 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7892 #define FMC_BWTR2_ACCMOD_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7893 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7894 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 171:3a7713b1edbc 7895 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7896 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7897
AnnaBridge 171:3a7713b1edbc 7898 /****************** Bit definition for FMC_BWTR3 register ******************/
AnnaBridge 171:3a7713b1edbc 7899 #define FMC_BWTR3_ADDSET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7900 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7901 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 171:3a7713b1edbc 7902 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7903 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7904 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7905 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7906 #define FMC_BWTR3_ADDHLD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7907 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7908 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 171:3a7713b1edbc 7909 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7910 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7911 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7912 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7913 #define FMC_BWTR3_DATAST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7914 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7915 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 171:3a7713b1edbc 7916 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7917 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7918 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7919 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7920 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7921 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7922 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7923 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7924 #define FMC_BWTR3_BUSTURN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7925 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7926 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 171:3a7713b1edbc 7927 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7928 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7929 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7930 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7931 #define FMC_BWTR3_ACCMOD_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7932 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7933 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 171:3a7713b1edbc 7934 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7935 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7936
AnnaBridge 171:3a7713b1edbc 7937 /****************** Bit definition for FMC_BWTR4 register ******************/
AnnaBridge 171:3a7713b1edbc 7938 #define FMC_BWTR4_ADDSET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7939 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7940 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 171:3a7713b1edbc 7941 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7942 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7943 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7944 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7945 #define FMC_BWTR4_ADDHLD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7946 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 7947 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 171:3a7713b1edbc 7948 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7949 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7950 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7951 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7952 #define FMC_BWTR4_DATAST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7953 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7954 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 171:3a7713b1edbc 7955 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7956 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7957 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7958 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7959 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7960 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7961 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7962 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7963 #define FMC_BWTR4_BUSTURN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7964 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 7965 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 171:3a7713b1edbc 7966 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7967 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7968 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7969 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7970 #define FMC_BWTR4_ACCMOD_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7971 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7972 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 171:3a7713b1edbc 7973 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7974 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7975
AnnaBridge 171:3a7713b1edbc 7976 /****************** Bit definition for FMC_PCR register *******************/
AnnaBridge 171:3a7713b1edbc 7977 #define FMC_PCR_PWAITEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7978 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7979 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 171:3a7713b1edbc 7980 #define FMC_PCR_PBKEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7981 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7982 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 171:3a7713b1edbc 7983 #define FMC_PCR_PTYP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7984 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7985 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
AnnaBridge 171:3a7713b1edbc 7986 #define FMC_PCR_PWID_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7987 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7988 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 171:3a7713b1edbc 7989 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7990 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7991 #define FMC_PCR_ECCEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7992 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7993 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 171:3a7713b1edbc 7994 #define FMC_PCR_TCLR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7995 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 171:3a7713b1edbc 7996 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 171:3a7713b1edbc 7997 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7998 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7999 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8000 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8001 #define FMC_PCR_TAR_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8002 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 171:3a7713b1edbc 8003 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 171:3a7713b1edbc 8004 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8005 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8006 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8007 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8008 #define FMC_PCR_ECCPS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8009 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 8010 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
AnnaBridge 171:3a7713b1edbc 8011 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8012 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8013 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8014
AnnaBridge 171:3a7713b1edbc 8015 /******************* Bit definition for FMC_SR register *******************/
AnnaBridge 171:3a7713b1edbc 8016 #define FMC_SR_IRS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8017 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8018 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 171:3a7713b1edbc 8019 #define FMC_SR_ILS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8020 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8021 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 171:3a7713b1edbc 8022 #define FMC_SR_IFS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8023 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8024 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 171:3a7713b1edbc 8025 #define FMC_SR_IREN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8026 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8027 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 171:3a7713b1edbc 8028 #define FMC_SR_ILEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8029 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8030 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 171:3a7713b1edbc 8031 #define FMC_SR_IFEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8032 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8033 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 171:3a7713b1edbc 8034 #define FMC_SR_FEMPT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8035 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8036 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
AnnaBridge 171:3a7713b1edbc 8037
AnnaBridge 171:3a7713b1edbc 8038 /****************** Bit definition for FMC_PMEM register ******************/
AnnaBridge 171:3a7713b1edbc 8039 #define FMC_PMEM_MEMSET3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8040 #define FMC_PMEM_MEMSET3_Msk (0xFFU << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 8041 #define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
AnnaBridge 171:3a7713b1edbc 8042 #define FMC_PMEM_MEMSET3_0 (0x01U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8043 #define FMC_PMEM_MEMSET3_1 (0x02U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8044 #define FMC_PMEM_MEMSET3_2 (0x04U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8045 #define FMC_PMEM_MEMSET3_3 (0x08U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8046 #define FMC_PMEM_MEMSET3_4 (0x10U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8047 #define FMC_PMEM_MEMSET3_5 (0x20U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8048 #define FMC_PMEM_MEMSET3_6 (0x40U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8049 #define FMC_PMEM_MEMSET3_7 (0x80U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8050 #define FMC_PMEM_MEMWAIT3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8051 #define FMC_PMEM_MEMWAIT3_Msk (0xFFU << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 8052 #define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
AnnaBridge 171:3a7713b1edbc 8053 #define FMC_PMEM_MEMWAIT3_0 (0x01U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8054 #define FMC_PMEM_MEMWAIT3_1 (0x02U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8055 #define FMC_PMEM_MEMWAIT3_2 (0x04U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8056 #define FMC_PMEM_MEMWAIT3_3 (0x08U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8057 #define FMC_PMEM_MEMWAIT3_4 (0x10U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8058 #define FMC_PMEM_MEMWAIT3_5 (0x20U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8059 #define FMC_PMEM_MEMWAIT3_6 (0x40U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8060 #define FMC_PMEM_MEMWAIT3_7 (0x80U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8061 #define FMC_PMEM_MEMHOLD3_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8062 #define FMC_PMEM_MEMHOLD3_Msk (0xFFU << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 8063 #define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
AnnaBridge 171:3a7713b1edbc 8064 #define FMC_PMEM_MEMHOLD3_0 (0x01U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8065 #define FMC_PMEM_MEMHOLD3_1 (0x02U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8066 #define FMC_PMEM_MEMHOLD3_2 (0x04U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8067 #define FMC_PMEM_MEMHOLD3_3 (0x08U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8068 #define FMC_PMEM_MEMHOLD3_4 (0x10U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8069 #define FMC_PMEM_MEMHOLD3_5 (0x20U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8070 #define FMC_PMEM_MEMHOLD3_6 (0x40U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8071 #define FMC_PMEM_MEMHOLD3_7 (0x80U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8072 #define FMC_PMEM_MEMHIZ3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8073 #define FMC_PMEM_MEMHIZ3_Msk (0xFFU << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 8074 #define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
AnnaBridge 171:3a7713b1edbc 8075 #define FMC_PMEM_MEMHIZ3_0 (0x01U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8076 #define FMC_PMEM_MEMHIZ3_1 (0x02U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8077 #define FMC_PMEM_MEMHIZ3_2 (0x04U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8078 #define FMC_PMEM_MEMHIZ3_3 (0x08U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8079 #define FMC_PMEM_MEMHIZ3_4 (0x10U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8080 #define FMC_PMEM_MEMHIZ3_5 (0x20U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8081 #define FMC_PMEM_MEMHIZ3_6 (0x40U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8082 #define FMC_PMEM_MEMHIZ3_7 (0x80U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8083
AnnaBridge 171:3a7713b1edbc 8084 /****************** Bit definition for FMC_PATT register ******************/
AnnaBridge 171:3a7713b1edbc 8085 #define FMC_PATT_ATTSET3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8086 #define FMC_PATT_ATTSET3_Msk (0xFFU << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 8087 #define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
AnnaBridge 171:3a7713b1edbc 8088 #define FMC_PATT_ATTSET3_0 (0x01U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8089 #define FMC_PATT_ATTSET3_1 (0x02U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8090 #define FMC_PATT_ATTSET3_2 (0x04U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8091 #define FMC_PATT_ATTSET3_3 (0x08U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8092 #define FMC_PATT_ATTSET3_4 (0x10U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8093 #define FMC_PATT_ATTSET3_5 (0x20U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8094 #define FMC_PATT_ATTSET3_6 (0x40U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8095 #define FMC_PATT_ATTSET3_7 (0x80U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8096 #define FMC_PATT_ATTWAIT3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8097 #define FMC_PATT_ATTWAIT3_Msk (0xFFU << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 8098 #define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
AnnaBridge 171:3a7713b1edbc 8099 #define FMC_PATT_ATTWAIT3_0 (0x01U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8100 #define FMC_PATT_ATTWAIT3_1 (0x02U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8101 #define FMC_PATT_ATTWAIT3_2 (0x04U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8102 #define FMC_PATT_ATTWAIT3_3 (0x08U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8103 #define FMC_PATT_ATTWAIT3_4 (0x10U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8104 #define FMC_PATT_ATTWAIT3_5 (0x20U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8105 #define FMC_PATT_ATTWAIT3_6 (0x40U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8106 #define FMC_PATT_ATTWAIT3_7 (0x80U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8107 #define FMC_PATT_ATTHOLD3_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8108 #define FMC_PATT_ATTHOLD3_Msk (0xFFU << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 8109 #define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
AnnaBridge 171:3a7713b1edbc 8110 #define FMC_PATT_ATTHOLD3_0 (0x01U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8111 #define FMC_PATT_ATTHOLD3_1 (0x02U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8112 #define FMC_PATT_ATTHOLD3_2 (0x04U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8113 #define FMC_PATT_ATTHOLD3_3 (0x08U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8114 #define FMC_PATT_ATTHOLD3_4 (0x10U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8115 #define FMC_PATT_ATTHOLD3_5 (0x20U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8116 #define FMC_PATT_ATTHOLD3_6 (0x40U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8117 #define FMC_PATT_ATTHOLD3_7 (0x80U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8118 #define FMC_PATT_ATTHIZ3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8119 #define FMC_PATT_ATTHIZ3_Msk (0xFFU << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 8120 #define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
AnnaBridge 171:3a7713b1edbc 8121 #define FMC_PATT_ATTHIZ3_0 (0x01U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8122 #define FMC_PATT_ATTHIZ3_1 (0x02U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8123 #define FMC_PATT_ATTHIZ3_2 (0x04U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8124 #define FMC_PATT_ATTHIZ3_3 (0x08U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8125 #define FMC_PATT_ATTHIZ3_4 (0x10U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8126 #define FMC_PATT_ATTHIZ3_5 (0x20U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8127 #define FMC_PATT_ATTHIZ3_6 (0x40U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8128 #define FMC_PATT_ATTHIZ3_7 (0x80U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8129
AnnaBridge 171:3a7713b1edbc 8130 /****************** Bit definition for FMC_ECCR register ******************/
AnnaBridge 171:3a7713b1edbc 8131 #define FMC_ECCR_ECC3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8132 #define FMC_ECCR_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR_ECC3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8133 #define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk /*!<ECC result */
AnnaBridge 171:3a7713b1edbc 8134
AnnaBridge 171:3a7713b1edbc 8135 /****************** Bit definition for FMC_SDCR1 register ******************/
AnnaBridge 171:3a7713b1edbc 8136 #define FMC_SDCR1_NC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8137 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 8138 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 171:3a7713b1edbc 8139 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8140 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8141 #define FMC_SDCR1_NR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8142 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 8143 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 171:3a7713b1edbc 8144 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8145 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8146 #define FMC_SDCR1_MWID_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8147 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 8148 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 171:3a7713b1edbc 8149 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8150 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8151 #define FMC_SDCR1_NB_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8152 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8153 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
AnnaBridge 171:3a7713b1edbc 8154 #define FMC_SDCR1_CAS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8155 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 8156 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 171:3a7713b1edbc 8157 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8158 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8159 #define FMC_SDCR1_WP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8160 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8161 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
AnnaBridge 171:3a7713b1edbc 8162 #define FMC_SDCR1_SDCLK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8163 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 8164 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
AnnaBridge 171:3a7713b1edbc 8165 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8166 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8167 #define FMC_SDCR1_RBURST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8168 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8169 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
AnnaBridge 171:3a7713b1edbc 8170 #define FMC_SDCR1_RPIPE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8171 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 8172 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
AnnaBridge 171:3a7713b1edbc 8173 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8174 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8175
AnnaBridge 171:3a7713b1edbc 8176 /****************** Bit definition for FMC_SDCR2 register ******************/
AnnaBridge 171:3a7713b1edbc 8177 #define FMC_SDCR2_NC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8178 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 8179 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 171:3a7713b1edbc 8180 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8181 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8182 #define FMC_SDCR2_NR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8183 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 8184 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 171:3a7713b1edbc 8185 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8186 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8187 #define FMC_SDCR2_MWID_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8188 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 8189 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 171:3a7713b1edbc 8190 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8191 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8192 #define FMC_SDCR2_NB_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8193 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8194 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
AnnaBridge 171:3a7713b1edbc 8195 #define FMC_SDCR2_CAS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8196 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 8197 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 171:3a7713b1edbc 8198 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8199 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8200 #define FMC_SDCR2_WP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8201 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8202 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
AnnaBridge 171:3a7713b1edbc 8203 #define FMC_SDCR2_SDCLK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8204 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 8205 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
AnnaBridge 171:3a7713b1edbc 8206 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8207 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8208 #define FMC_SDCR2_RBURST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8209 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8210 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
AnnaBridge 171:3a7713b1edbc 8211 #define FMC_SDCR2_RPIPE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8212 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 8213 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
AnnaBridge 171:3a7713b1edbc 8214 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8215 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8216
AnnaBridge 171:3a7713b1edbc 8217 /****************** Bit definition for FMC_SDTR1 register ******************/
AnnaBridge 171:3a7713b1edbc 8218 #define FMC_SDTR1_TMRD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8219 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 8220 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 171:3a7713b1edbc 8221 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8222 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8223 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8224 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8225 #define FMC_SDTR1_TXSR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8226 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 8227 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 171:3a7713b1edbc 8228 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8229 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8230 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8231 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8232 #define FMC_SDTR1_TRAS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8233 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 8234 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 171:3a7713b1edbc 8235 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8236 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8237 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8238 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8239 #define FMC_SDTR1_TRC_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8240 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 8241 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 171:3a7713b1edbc 8242 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8243 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8244 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8245 #define FMC_SDTR1_TWR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8246 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 8247 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 171:3a7713b1edbc 8248 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8249 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8250 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8251 #define FMC_SDTR1_TRP_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8252 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 8253 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 171:3a7713b1edbc 8254 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8255 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8256 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8257 #define FMC_SDTR1_TRCD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8258 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 8259 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 171:3a7713b1edbc 8260 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8261 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8262 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8263
AnnaBridge 171:3a7713b1edbc 8264 /****************** Bit definition for FMC_SDTR2 register ******************/
AnnaBridge 171:3a7713b1edbc 8265 #define FMC_SDTR2_TMRD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8266 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 8267 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 171:3a7713b1edbc 8268 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8269 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8270 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8271 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8272 #define FMC_SDTR2_TXSR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8273 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 8274 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 171:3a7713b1edbc 8275 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8276 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8277 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8278 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8279 #define FMC_SDTR2_TRAS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8280 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 8281 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 171:3a7713b1edbc 8282 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8283 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8284 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8285 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8286 #define FMC_SDTR2_TRC_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8287 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 8288 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 171:3a7713b1edbc 8289 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8290 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8291 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8292 #define FMC_SDTR2_TWR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8293 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 8294 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 171:3a7713b1edbc 8295 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8296 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8297 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8298 #define FMC_SDTR2_TRP_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8299 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 8300 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 171:3a7713b1edbc 8301 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8302 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8303 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8304 #define FMC_SDTR2_TRCD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8305 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 8306 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 171:3a7713b1edbc 8307 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8308 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8309 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8310
AnnaBridge 171:3a7713b1edbc 8311 /****************** Bit definition for FMC_SDCMR register ******************/
AnnaBridge 171:3a7713b1edbc 8312 #define FMC_SDCMR_MODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8313 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 8314 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
AnnaBridge 171:3a7713b1edbc 8315 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8316 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8317 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8318 #define FMC_SDCMR_CTB2_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8319 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8320 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
AnnaBridge 171:3a7713b1edbc 8321 #define FMC_SDCMR_CTB1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8322 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8323 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
AnnaBridge 171:3a7713b1edbc 8324 #define FMC_SDCMR_NRFS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8325 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
AnnaBridge 171:3a7713b1edbc 8326 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
AnnaBridge 171:3a7713b1edbc 8327 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8328 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8329 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8330 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8331 #define FMC_SDCMR_MRD_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8332 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
AnnaBridge 171:3a7713b1edbc 8333 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
AnnaBridge 171:3a7713b1edbc 8334
AnnaBridge 171:3a7713b1edbc 8335 /****************** Bit definition for FMC_SDRTR register ******************/
AnnaBridge 171:3a7713b1edbc 8336 #define FMC_SDRTR_CRE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8337 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8338 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
AnnaBridge 171:3a7713b1edbc 8339 #define FMC_SDRTR_COUNT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8340 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
AnnaBridge 171:3a7713b1edbc 8341 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
AnnaBridge 171:3a7713b1edbc 8342 #define FMC_SDRTR_REIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8343 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8344 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
AnnaBridge 171:3a7713b1edbc 8345
AnnaBridge 171:3a7713b1edbc 8346 /****************** Bit definition for FMC_SDSR register ******************/
AnnaBridge 171:3a7713b1edbc 8347 #define FMC_SDSR_RE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8348 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8349 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
AnnaBridge 171:3a7713b1edbc 8350 #define FMC_SDSR_MODES1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8351 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 8352 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
AnnaBridge 171:3a7713b1edbc 8353 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8354 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8355 #define FMC_SDSR_MODES2_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8356 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 8357 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
AnnaBridge 171:3a7713b1edbc 8358 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8359 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8360 #define FMC_SDSR_BUSY_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8361 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8362 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
AnnaBridge 171:3a7713b1edbc 8363
AnnaBridge 171:3a7713b1edbc 8364 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8365 /* */
AnnaBridge 171:3a7713b1edbc 8366 /* General Purpose I/O */
AnnaBridge 171:3a7713b1edbc 8367 /* */
AnnaBridge 171:3a7713b1edbc 8368 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8369 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 171:3a7713b1edbc 8370 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8371 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 8372 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 171:3a7713b1edbc 8373 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8374 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8375 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8376 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 8377 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 171:3a7713b1edbc 8378 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8379 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8380 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8381 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 8382 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 171:3a7713b1edbc 8383 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8384 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8385 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8386 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 8387 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 171:3a7713b1edbc 8388 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8389 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8390 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8391 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 8392 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 171:3a7713b1edbc 8393 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8394 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8395 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8396 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 8397 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 171:3a7713b1edbc 8398 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8399 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8400 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8401 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 8402 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 171:3a7713b1edbc 8403 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8404 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8405 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8406 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 8407 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 171:3a7713b1edbc 8408 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8409 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8410 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8411 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 8412 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 171:3a7713b1edbc 8413 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8414 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8415 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8416 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 8417 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 171:3a7713b1edbc 8418 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8419 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8420 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8421 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 8422 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 171:3a7713b1edbc 8423 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8424 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8425 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8426 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 8427 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 171:3a7713b1edbc 8428 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8429 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8430 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8431 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 8432 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 171:3a7713b1edbc 8433 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8434 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8435 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8436 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 8437 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 171:3a7713b1edbc 8438 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8439 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8440 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8441 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 8442 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 171:3a7713b1edbc 8443 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8444 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8445 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8446 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 8447 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 171:3a7713b1edbc 8448 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8449 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8450
AnnaBridge 171:3a7713b1edbc 8451 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 171:3a7713b1edbc 8452 #define GPIO_OTYPER_OT_0 0x00000001U
AnnaBridge 171:3a7713b1edbc 8453 #define GPIO_OTYPER_OT_1 0x00000002U
AnnaBridge 171:3a7713b1edbc 8454 #define GPIO_OTYPER_OT_2 0x00000004U
AnnaBridge 171:3a7713b1edbc 8455 #define GPIO_OTYPER_OT_3 0x00000008U
AnnaBridge 171:3a7713b1edbc 8456 #define GPIO_OTYPER_OT_4 0x00000010U
AnnaBridge 171:3a7713b1edbc 8457 #define GPIO_OTYPER_OT_5 0x00000020U
AnnaBridge 171:3a7713b1edbc 8458 #define GPIO_OTYPER_OT_6 0x00000040U
AnnaBridge 171:3a7713b1edbc 8459 #define GPIO_OTYPER_OT_7 0x00000080U
AnnaBridge 171:3a7713b1edbc 8460 #define GPIO_OTYPER_OT_8 0x00000100U
AnnaBridge 171:3a7713b1edbc 8461 #define GPIO_OTYPER_OT_9 0x00000200U
AnnaBridge 171:3a7713b1edbc 8462 #define GPIO_OTYPER_OT_10 0x00000400U
AnnaBridge 171:3a7713b1edbc 8463 #define GPIO_OTYPER_OT_11 0x00000800U
AnnaBridge 171:3a7713b1edbc 8464 #define GPIO_OTYPER_OT_12 0x00001000U
AnnaBridge 171:3a7713b1edbc 8465 #define GPIO_OTYPER_OT_13 0x00002000U
AnnaBridge 171:3a7713b1edbc 8466 #define GPIO_OTYPER_OT_14 0x00004000U
AnnaBridge 171:3a7713b1edbc 8467 #define GPIO_OTYPER_OT_15 0x00008000U
AnnaBridge 171:3a7713b1edbc 8468
AnnaBridge 171:3a7713b1edbc 8469 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 171:3a7713b1edbc 8470 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8471 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 8472 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
AnnaBridge 171:3a7713b1edbc 8473 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8474 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8475 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8476 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 8477 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
AnnaBridge 171:3a7713b1edbc 8478 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8479 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8480 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8481 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 8482 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
AnnaBridge 171:3a7713b1edbc 8483 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8484 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8485 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8486 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 8487 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
AnnaBridge 171:3a7713b1edbc 8488 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8489 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8490 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8491 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 8492 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
AnnaBridge 171:3a7713b1edbc 8493 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8494 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8495 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8496 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 8497 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
AnnaBridge 171:3a7713b1edbc 8498 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8499 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8500 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8501 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 8502 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
AnnaBridge 171:3a7713b1edbc 8503 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8504 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8505 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8506 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 8507 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
AnnaBridge 171:3a7713b1edbc 8508 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8509 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8510 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8511 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 8512 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
AnnaBridge 171:3a7713b1edbc 8513 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8514 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8515 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8516 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 8517 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
AnnaBridge 171:3a7713b1edbc 8518 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8519 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8520 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8521 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 8522 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
AnnaBridge 171:3a7713b1edbc 8523 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8524 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8525 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8526 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 8527 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
AnnaBridge 171:3a7713b1edbc 8528 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8529 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8530 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8531 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 8532 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
AnnaBridge 171:3a7713b1edbc 8533 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8534 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8535 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8536 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 8537 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
AnnaBridge 171:3a7713b1edbc 8538 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8539 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8540 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8541 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 8542 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
AnnaBridge 171:3a7713b1edbc 8543 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8544 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8545 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8546 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 8547 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
AnnaBridge 171:3a7713b1edbc 8548 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8549 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8550
AnnaBridge 171:3a7713b1edbc 8551 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 171:3a7713b1edbc 8552 #define GPIO_PUPDR_PUPDR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8553 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 8554 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
AnnaBridge 171:3a7713b1edbc 8555 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8556 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8557 #define GPIO_PUPDR_PUPDR1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8558 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 8559 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
AnnaBridge 171:3a7713b1edbc 8560 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8561 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8562 #define GPIO_PUPDR_PUPDR2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8563 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 8564 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
AnnaBridge 171:3a7713b1edbc 8565 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8566 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8567 #define GPIO_PUPDR_PUPDR3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8568 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 8569 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
AnnaBridge 171:3a7713b1edbc 8570 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8571 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8572 #define GPIO_PUPDR_PUPDR4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8573 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 8574 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
AnnaBridge 171:3a7713b1edbc 8575 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8576 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8577 #define GPIO_PUPDR_PUPDR5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8578 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 8579 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
AnnaBridge 171:3a7713b1edbc 8580 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8581 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8582 #define GPIO_PUPDR_PUPDR6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8583 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 8584 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
AnnaBridge 171:3a7713b1edbc 8585 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8586 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8587 #define GPIO_PUPDR_PUPDR7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8588 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 8589 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
AnnaBridge 171:3a7713b1edbc 8590 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8591 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8592 #define GPIO_PUPDR_PUPDR8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8593 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 8594 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
AnnaBridge 171:3a7713b1edbc 8595 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8596 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8597 #define GPIO_PUPDR_PUPDR9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8598 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 8599 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
AnnaBridge 171:3a7713b1edbc 8600 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8601 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8602 #define GPIO_PUPDR_PUPDR10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8603 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 8604 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
AnnaBridge 171:3a7713b1edbc 8605 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8606 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8607 #define GPIO_PUPDR_PUPDR11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8608 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 8609 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
AnnaBridge 171:3a7713b1edbc 8610 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8611 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8612 #define GPIO_PUPDR_PUPDR12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8613 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 8614 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
AnnaBridge 171:3a7713b1edbc 8615 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8616 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8617 #define GPIO_PUPDR_PUPDR13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8618 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 8619 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
AnnaBridge 171:3a7713b1edbc 8620 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8621 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8622 #define GPIO_PUPDR_PUPDR14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8623 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 8624 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
AnnaBridge 171:3a7713b1edbc 8625 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8626 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8627 #define GPIO_PUPDR_PUPDR15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8628 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 8629 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
AnnaBridge 171:3a7713b1edbc 8630 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8631 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8632
AnnaBridge 171:3a7713b1edbc 8633 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 171:3a7713b1edbc 8634 #define GPIO_IDR_IDR_0 0x00000001U
AnnaBridge 171:3a7713b1edbc 8635 #define GPIO_IDR_IDR_1 0x00000002U
AnnaBridge 171:3a7713b1edbc 8636 #define GPIO_IDR_IDR_2 0x00000004U
AnnaBridge 171:3a7713b1edbc 8637 #define GPIO_IDR_IDR_3 0x00000008U
AnnaBridge 171:3a7713b1edbc 8638 #define GPIO_IDR_IDR_4 0x00000010U
AnnaBridge 171:3a7713b1edbc 8639 #define GPIO_IDR_IDR_5 0x00000020U
AnnaBridge 171:3a7713b1edbc 8640 #define GPIO_IDR_IDR_6 0x00000040U
AnnaBridge 171:3a7713b1edbc 8641 #define GPIO_IDR_IDR_7 0x00000080U
AnnaBridge 171:3a7713b1edbc 8642 #define GPIO_IDR_IDR_8 0x00000100U
AnnaBridge 171:3a7713b1edbc 8643 #define GPIO_IDR_IDR_9 0x00000200U
AnnaBridge 171:3a7713b1edbc 8644 #define GPIO_IDR_IDR_10 0x00000400U
AnnaBridge 171:3a7713b1edbc 8645 #define GPIO_IDR_IDR_11 0x00000800U
AnnaBridge 171:3a7713b1edbc 8646 #define GPIO_IDR_IDR_12 0x00001000U
AnnaBridge 171:3a7713b1edbc 8647 #define GPIO_IDR_IDR_13 0x00002000U
AnnaBridge 171:3a7713b1edbc 8648 #define GPIO_IDR_IDR_14 0x00004000U
AnnaBridge 171:3a7713b1edbc 8649 #define GPIO_IDR_IDR_15 0x00008000U
AnnaBridge 171:3a7713b1edbc 8650
AnnaBridge 171:3a7713b1edbc 8651 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 171:3a7713b1edbc 8652 #define GPIO_ODR_ODR_0 0x00000001U
AnnaBridge 171:3a7713b1edbc 8653 #define GPIO_ODR_ODR_1 0x00000002U
AnnaBridge 171:3a7713b1edbc 8654 #define GPIO_ODR_ODR_2 0x00000004U
AnnaBridge 171:3a7713b1edbc 8655 #define GPIO_ODR_ODR_3 0x00000008U
AnnaBridge 171:3a7713b1edbc 8656 #define GPIO_ODR_ODR_4 0x00000010U
AnnaBridge 171:3a7713b1edbc 8657 #define GPIO_ODR_ODR_5 0x00000020U
AnnaBridge 171:3a7713b1edbc 8658 #define GPIO_ODR_ODR_6 0x00000040U
AnnaBridge 171:3a7713b1edbc 8659 #define GPIO_ODR_ODR_7 0x00000080U
AnnaBridge 171:3a7713b1edbc 8660 #define GPIO_ODR_ODR_8 0x00000100U
AnnaBridge 171:3a7713b1edbc 8661 #define GPIO_ODR_ODR_9 0x00000200U
AnnaBridge 171:3a7713b1edbc 8662 #define GPIO_ODR_ODR_10 0x00000400U
AnnaBridge 171:3a7713b1edbc 8663 #define GPIO_ODR_ODR_11 0x00000800U
AnnaBridge 171:3a7713b1edbc 8664 #define GPIO_ODR_ODR_12 0x00001000U
AnnaBridge 171:3a7713b1edbc 8665 #define GPIO_ODR_ODR_13 0x00002000U
AnnaBridge 171:3a7713b1edbc 8666 #define GPIO_ODR_ODR_14 0x00004000U
AnnaBridge 171:3a7713b1edbc 8667 #define GPIO_ODR_ODR_15 0x00008000U
AnnaBridge 171:3a7713b1edbc 8668
AnnaBridge 171:3a7713b1edbc 8669 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 171:3a7713b1edbc 8670 #define GPIO_BSRR_BS_0 0x00000001U
AnnaBridge 171:3a7713b1edbc 8671 #define GPIO_BSRR_BS_1 0x00000002U
AnnaBridge 171:3a7713b1edbc 8672 #define GPIO_BSRR_BS_2 0x00000004U
AnnaBridge 171:3a7713b1edbc 8673 #define GPIO_BSRR_BS_3 0x00000008U
AnnaBridge 171:3a7713b1edbc 8674 #define GPIO_BSRR_BS_4 0x00000010U
AnnaBridge 171:3a7713b1edbc 8675 #define GPIO_BSRR_BS_5 0x00000020U
AnnaBridge 171:3a7713b1edbc 8676 #define GPIO_BSRR_BS_6 0x00000040U
AnnaBridge 171:3a7713b1edbc 8677 #define GPIO_BSRR_BS_7 0x00000080U
AnnaBridge 171:3a7713b1edbc 8678 #define GPIO_BSRR_BS_8 0x00000100U
AnnaBridge 171:3a7713b1edbc 8679 #define GPIO_BSRR_BS_9 0x00000200U
AnnaBridge 171:3a7713b1edbc 8680 #define GPIO_BSRR_BS_10 0x00000400U
AnnaBridge 171:3a7713b1edbc 8681 #define GPIO_BSRR_BS_11 0x00000800U
AnnaBridge 171:3a7713b1edbc 8682 #define GPIO_BSRR_BS_12 0x00001000U
AnnaBridge 171:3a7713b1edbc 8683 #define GPIO_BSRR_BS_13 0x00002000U
AnnaBridge 171:3a7713b1edbc 8684 #define GPIO_BSRR_BS_14 0x00004000U
AnnaBridge 171:3a7713b1edbc 8685 #define GPIO_BSRR_BS_15 0x00008000U
AnnaBridge 171:3a7713b1edbc 8686 #define GPIO_BSRR_BR_0 0x00010000U
AnnaBridge 171:3a7713b1edbc 8687 #define GPIO_BSRR_BR_1 0x00020000U
AnnaBridge 171:3a7713b1edbc 8688 #define GPIO_BSRR_BR_2 0x00040000U
AnnaBridge 171:3a7713b1edbc 8689 #define GPIO_BSRR_BR_3 0x00080000U
AnnaBridge 171:3a7713b1edbc 8690 #define GPIO_BSRR_BR_4 0x00100000U
AnnaBridge 171:3a7713b1edbc 8691 #define GPIO_BSRR_BR_5 0x00200000U
AnnaBridge 171:3a7713b1edbc 8692 #define GPIO_BSRR_BR_6 0x00400000U
AnnaBridge 171:3a7713b1edbc 8693 #define GPIO_BSRR_BR_7 0x00800000U
AnnaBridge 171:3a7713b1edbc 8694 #define GPIO_BSRR_BR_8 0x01000000U
AnnaBridge 171:3a7713b1edbc 8695 #define GPIO_BSRR_BR_9 0x02000000U
AnnaBridge 171:3a7713b1edbc 8696 #define GPIO_BSRR_BR_10 0x04000000U
AnnaBridge 171:3a7713b1edbc 8697 #define GPIO_BSRR_BR_11 0x08000000U
AnnaBridge 171:3a7713b1edbc 8698 #define GPIO_BSRR_BR_12 0x10000000U
AnnaBridge 171:3a7713b1edbc 8699 #define GPIO_BSRR_BR_13 0x20000000U
AnnaBridge 171:3a7713b1edbc 8700 #define GPIO_BSRR_BR_14 0x40000000U
AnnaBridge 171:3a7713b1edbc 8701 #define GPIO_BSRR_BR_15 0x80000000U
AnnaBridge 171:3a7713b1edbc 8702
AnnaBridge 171:3a7713b1edbc 8703 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 171:3a7713b1edbc 8704 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8705 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8706 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 171:3a7713b1edbc 8707 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8708 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8709 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 171:3a7713b1edbc 8710 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8711 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8712 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 171:3a7713b1edbc 8713 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8714 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8715 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 171:3a7713b1edbc 8716 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8717 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8718 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 171:3a7713b1edbc 8719 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8720 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8721 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 171:3a7713b1edbc 8722 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8723 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8724 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 171:3a7713b1edbc 8725 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8726 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8727 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 171:3a7713b1edbc 8728 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8729 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8730 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 171:3a7713b1edbc 8731 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8732 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8733 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 171:3a7713b1edbc 8734 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8735 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8736 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 171:3a7713b1edbc 8737 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8738 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8739 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 171:3a7713b1edbc 8740 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8741 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8742 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 171:3a7713b1edbc 8743 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8744 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8745 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 171:3a7713b1edbc 8746 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8747 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8748 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 171:3a7713b1edbc 8749 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8750 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8751 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 171:3a7713b1edbc 8752 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8753 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8754 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 171:3a7713b1edbc 8755
AnnaBridge 171:3a7713b1edbc 8756 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 171:3a7713b1edbc 8757 #define GPIO_AFRL_AFRL0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8758 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 8759 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
AnnaBridge 171:3a7713b1edbc 8760 #define GPIO_AFRL_AFRL0_0 (0x1U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8761 #define GPIO_AFRL_AFRL0_1 (0x2U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8762 #define GPIO_AFRL_AFRL0_2 (0x4U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8763 #define GPIO_AFRL_AFRL0_3 (0x8U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8764 #define GPIO_AFRL_AFRL1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8765 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 8766 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
AnnaBridge 171:3a7713b1edbc 8767 #define GPIO_AFRL_AFRL1_0 (0x1U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8768 #define GPIO_AFRL_AFRL1_1 (0x2U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8769 #define GPIO_AFRL_AFRL1_2 (0x4U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8770 #define GPIO_AFRL_AFRL1_3 (0x8U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8771 #define GPIO_AFRL_AFRL2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8772 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 8773 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
AnnaBridge 171:3a7713b1edbc 8774 #define GPIO_AFRL_AFRL2_0 (0x1U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8775 #define GPIO_AFRL_AFRL2_1 (0x2U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8776 #define GPIO_AFRL_AFRL2_2 (0x4U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8777 #define GPIO_AFRL_AFRL2_3 (0x8U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8778 #define GPIO_AFRL_AFRL3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8779 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 8780 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
AnnaBridge 171:3a7713b1edbc 8781 #define GPIO_AFRL_AFRL3_0 (0x1U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8782 #define GPIO_AFRL_AFRL3_1 (0x2U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8783 #define GPIO_AFRL_AFRL3_2 (0x4U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8784 #define GPIO_AFRL_AFRL3_3 (0x8U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8785 #define GPIO_AFRL_AFRL4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8786 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 8787 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
AnnaBridge 171:3a7713b1edbc 8788 #define GPIO_AFRL_AFRL4_0 (0x1U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8789 #define GPIO_AFRL_AFRL4_1 (0x2U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8790 #define GPIO_AFRL_AFRL4_2 (0x4U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8791 #define GPIO_AFRL_AFRL4_3 (0x8U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8792 #define GPIO_AFRL_AFRL5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8793 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 8794 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
AnnaBridge 171:3a7713b1edbc 8795 #define GPIO_AFRL_AFRL5_0 (0x1U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8796 #define GPIO_AFRL_AFRL5_1 (0x2U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8797 #define GPIO_AFRL_AFRL5_2 (0x4U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8798 #define GPIO_AFRL_AFRL5_3 (0x8U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8799 #define GPIO_AFRL_AFRL6_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8800 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 8801 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
AnnaBridge 171:3a7713b1edbc 8802 #define GPIO_AFRL_AFRL6_0 (0x1U << GPIO_AFRL_AFRL6_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8803 #define GPIO_AFRL_AFRL6_1 (0x2U << GPIO_AFRL_AFRL6_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8804 #define GPIO_AFRL_AFRL6_2 (0x4U << GPIO_AFRL_AFRL6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8805 #define GPIO_AFRL_AFRL6_3 (0x8U << GPIO_AFRL_AFRL6_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8806 #define GPIO_AFRL_AFRL7_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8807 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 8808 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
AnnaBridge 171:3a7713b1edbc 8809 #define GPIO_AFRL_AFRL7_0 (0x1U << GPIO_AFRL_AFRL7_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8810 #define GPIO_AFRL_AFRL7_1 (0x2U << GPIO_AFRL_AFRL7_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8811 #define GPIO_AFRL_AFRL7_2 (0x4U << GPIO_AFRL_AFRL7_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8812 #define GPIO_AFRL_AFRL7_3 (0x8U << GPIO_AFRL_AFRL7_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8813
AnnaBridge 171:3a7713b1edbc 8814 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 171:3a7713b1edbc 8815 #define GPIO_AFRH_AFRH0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8816 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 8817 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
AnnaBridge 171:3a7713b1edbc 8818 #define GPIO_AFRH_AFRH0_0 (0x1U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8819 #define GPIO_AFRH_AFRH0_1 (0x2U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8820 #define GPIO_AFRH_AFRH0_2 (0x4U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8821 #define GPIO_AFRH_AFRH0_3 (0x8U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8822 #define GPIO_AFRH_AFRH1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8823 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 8824 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
AnnaBridge 171:3a7713b1edbc 8825 #define GPIO_AFRH_AFRH1_0 (0x1U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8826 #define GPIO_AFRH_AFRH1_1 (0x2U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8827 #define GPIO_AFRH_AFRH1_2 (0x4U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8828 #define GPIO_AFRH_AFRH1_3 (0x8U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8829 #define GPIO_AFRH_AFRH2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8830 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 8831 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
AnnaBridge 171:3a7713b1edbc 8832 #define GPIO_AFRH_AFRH2_0 (0x1U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8833 #define GPIO_AFRH_AFRH2_1 (0x2U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8834 #define GPIO_AFRH_AFRH2_2 (0x4U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8835 #define GPIO_AFRH_AFRH2_3 (0x8U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8836 #define GPIO_AFRH_AFRH3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8837 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 8838 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
AnnaBridge 171:3a7713b1edbc 8839 #define GPIO_AFRH_AFRH3_0 (0x1U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8840 #define GPIO_AFRH_AFRH3_1 (0x2U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8841 #define GPIO_AFRH_AFRH3_2 (0x4U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8842 #define GPIO_AFRH_AFRH3_3 (0x8U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8843 #define GPIO_AFRH_AFRH4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8844 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 8845 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
AnnaBridge 171:3a7713b1edbc 8846 #define GPIO_AFRH_AFRH4_0 (0x1U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8847 #define GPIO_AFRH_AFRH4_1 (0x2U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8848 #define GPIO_AFRH_AFRH4_2 (0x4U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8849 #define GPIO_AFRH_AFRH4_3 (0x8U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8850 #define GPIO_AFRH_AFRH5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8851 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 8852 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
AnnaBridge 171:3a7713b1edbc 8853 #define GPIO_AFRH_AFRH5_0 (0x1U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8854 #define GPIO_AFRH_AFRH5_1 (0x2U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8855 #define GPIO_AFRH_AFRH5_2 (0x4U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8856 #define GPIO_AFRH_AFRH5_3 (0x8U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8857 #define GPIO_AFRH_AFRH6_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8858 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 8859 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
AnnaBridge 171:3a7713b1edbc 8860 #define GPIO_AFRH_AFRH6_0 (0x1U << GPIO_AFRH_AFRH6_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8861 #define GPIO_AFRH_AFRH6_1 (0x2U << GPIO_AFRH_AFRH6_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8862 #define GPIO_AFRH_AFRH6_2 (0x4U << GPIO_AFRH_AFRH6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8863 #define GPIO_AFRH_AFRH6_3 (0x8U << GPIO_AFRH_AFRH6_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8864 #define GPIO_AFRH_AFRH7_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8865 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 8866 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
AnnaBridge 171:3a7713b1edbc 8867 #define GPIO_AFRH_AFRH7_0 (0x1U << GPIO_AFRH_AFRH7_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8868 #define GPIO_AFRH_AFRH7_1 (0x2U << GPIO_AFRH_AFRH7_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8869 #define GPIO_AFRH_AFRH7_2 (0x4U << GPIO_AFRH_AFRH7_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8870 #define GPIO_AFRH_AFRH7_3 (0x8U << GPIO_AFRH_AFRH7_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8871
AnnaBridge 171:3a7713b1edbc 8872
AnnaBridge 171:3a7713b1edbc 8873 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8874 /* */
AnnaBridge 171:3a7713b1edbc 8875 /* Inter-integrated Circuit Interface (I2C) */
AnnaBridge 171:3a7713b1edbc 8876 /* */
AnnaBridge 171:3a7713b1edbc 8877 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8878 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 8879 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8880 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8881 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
AnnaBridge 171:3a7713b1edbc 8882 #define I2C_CR1_TXIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8883 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8884 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
AnnaBridge 171:3a7713b1edbc 8885 #define I2C_CR1_RXIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8886 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8887 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
AnnaBridge 171:3a7713b1edbc 8888 #define I2C_CR1_ADDRIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8889 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8890 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
AnnaBridge 171:3a7713b1edbc 8891 #define I2C_CR1_NACKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8892 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8893 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
AnnaBridge 171:3a7713b1edbc 8894 #define I2C_CR1_STOPIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8895 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8896 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 8897 #define I2C_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8898 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8899 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 8900 #define I2C_CR1_ERRIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8901 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8902 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
AnnaBridge 171:3a7713b1edbc 8903 #define I2C_CR1_DNF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8904 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 8905 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
AnnaBridge 171:3a7713b1edbc 8906 #define I2C_CR1_ANFOFF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8907 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8908 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
AnnaBridge 171:3a7713b1edbc 8909 #define I2C_CR1_TXDMAEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8910 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8911 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
AnnaBridge 171:3a7713b1edbc 8912 #define I2C_CR1_RXDMAEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8913 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8914 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
AnnaBridge 171:3a7713b1edbc 8915 #define I2C_CR1_SBC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8916 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8917 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
AnnaBridge 171:3a7713b1edbc 8918 #define I2C_CR1_NOSTRETCH_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8919 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8920 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
AnnaBridge 171:3a7713b1edbc 8921 #define I2C_CR1_GCEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8922 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8923 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
AnnaBridge 171:3a7713b1edbc 8924 #define I2C_CR1_SMBHEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8925 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8926 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
AnnaBridge 171:3a7713b1edbc 8927 #define I2C_CR1_SMBDEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8928 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8929 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
AnnaBridge 171:3a7713b1edbc 8930 #define I2C_CR1_ALERTEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8931 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8932 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
AnnaBridge 171:3a7713b1edbc 8933 #define I2C_CR1_PECEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 8934 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8935 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
AnnaBridge 171:3a7713b1edbc 8936
AnnaBridge 171:3a7713b1edbc 8937 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 8938 #define I2C_CR1_DFN I2C_CR1_DNF /*!< Digital noise filter */
AnnaBridge 171:3a7713b1edbc 8939
AnnaBridge 171:3a7713b1edbc 8940 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 8941 #define I2C_CR2_SADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8942 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8943 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
AnnaBridge 171:3a7713b1edbc 8944 #define I2C_CR2_RD_WRN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8945 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8946 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
AnnaBridge 171:3a7713b1edbc 8947 #define I2C_CR2_ADD10_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8948 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8949 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
AnnaBridge 171:3a7713b1edbc 8950 #define I2C_CR2_HEAD10R_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8951 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8952 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 171:3a7713b1edbc 8953 #define I2C_CR2_START_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8954 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8955 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
AnnaBridge 171:3a7713b1edbc 8956 #define I2C_CR2_STOP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8957 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8958 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
AnnaBridge 171:3a7713b1edbc 8959 #define I2C_CR2_NACK_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8960 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8961 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
AnnaBridge 171:3a7713b1edbc 8962 #define I2C_CR2_NBYTES_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8963 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 8964 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
AnnaBridge 171:3a7713b1edbc 8965 #define I2C_CR2_RELOAD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8966 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8967 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
AnnaBridge 171:3a7713b1edbc 8968 #define I2C_CR2_AUTOEND_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8969 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8970 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
AnnaBridge 171:3a7713b1edbc 8971 #define I2C_CR2_PECBYTE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8972 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8973 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
AnnaBridge 171:3a7713b1edbc 8974
AnnaBridge 171:3a7713b1edbc 8975 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 171:3a7713b1edbc 8976 #define I2C_OAR1_OA1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8977 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8978 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
AnnaBridge 171:3a7713b1edbc 8979 #define I2C_OAR1_OA1MODE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8980 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8981 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
AnnaBridge 171:3a7713b1edbc 8982 #define I2C_OAR1_OA1EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8983 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8984 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
AnnaBridge 171:3a7713b1edbc 8985
AnnaBridge 171:3a7713b1edbc 8986 /******************* Bit definition for I2C_OAR2 register ******************/
AnnaBridge 171:3a7713b1edbc 8987 #define I2C_OAR2_OA2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8988 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
AnnaBridge 171:3a7713b1edbc 8989 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
AnnaBridge 171:3a7713b1edbc 8990 #define I2C_OAR2_OA2MSK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8991 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 8992 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
AnnaBridge 171:3a7713b1edbc 8993 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
AnnaBridge 171:3a7713b1edbc 8994 #define I2C_OAR2_OA2MASK01_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8995 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8996 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
AnnaBridge 171:3a7713b1edbc 8997 #define I2C_OAR2_OA2MASK02_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8998 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8999 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
AnnaBridge 171:3a7713b1edbc 9000 #define I2C_OAR2_OA2MASK03_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9001 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 9002 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
AnnaBridge 171:3a7713b1edbc 9003 #define I2C_OAR2_OA2MASK04_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9004 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9005 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
AnnaBridge 171:3a7713b1edbc 9006 #define I2C_OAR2_OA2MASK05_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9007 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
AnnaBridge 171:3a7713b1edbc 9008 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
AnnaBridge 171:3a7713b1edbc 9009 #define I2C_OAR2_OA2MASK06_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9010 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 9011 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
AnnaBridge 171:3a7713b1edbc 9012 #define I2C_OAR2_OA2MASK07_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9013 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 9014 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
AnnaBridge 171:3a7713b1edbc 9015 #define I2C_OAR2_OA2EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9016 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9017 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
AnnaBridge 171:3a7713b1edbc 9018
AnnaBridge 171:3a7713b1edbc 9019 /******************* Bit definition for I2C_TIMINGR register *******************/
AnnaBridge 171:3a7713b1edbc 9020 #define I2C_TIMINGR_SCLL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9021 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9022 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
AnnaBridge 171:3a7713b1edbc 9023 #define I2C_TIMINGR_SCLH_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9024 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 9025 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
AnnaBridge 171:3a7713b1edbc 9026 #define I2C_TIMINGR_SDADEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9027 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 9028 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
AnnaBridge 171:3a7713b1edbc 9029 #define I2C_TIMINGR_SCLDEL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9030 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 9031 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
AnnaBridge 171:3a7713b1edbc 9032 #define I2C_TIMINGR_PRESC_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9033 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 9034 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
AnnaBridge 171:3a7713b1edbc 9035
AnnaBridge 171:3a7713b1edbc 9036 /******************* Bit definition for I2C_TIMEOUTR register *******************/
AnnaBridge 171:3a7713b1edbc 9037 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9038 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 9039 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
AnnaBridge 171:3a7713b1edbc 9040 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9041 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9042 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
AnnaBridge 171:3a7713b1edbc 9043 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9044 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9045 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
AnnaBridge 171:3a7713b1edbc 9046 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9047 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 9048 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
AnnaBridge 171:3a7713b1edbc 9049 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9050 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9051 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
AnnaBridge 171:3a7713b1edbc 9052
AnnaBridge 171:3a7713b1edbc 9053 /****************** Bit definition for I2C_ISR register *********************/
AnnaBridge 171:3a7713b1edbc 9054 #define I2C_ISR_TXE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9055 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9056 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
AnnaBridge 171:3a7713b1edbc 9057 #define I2C_ISR_TXIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9058 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9059 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
AnnaBridge 171:3a7713b1edbc 9060 #define I2C_ISR_RXNE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9061 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9062 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
AnnaBridge 171:3a7713b1edbc 9063 #define I2C_ISR_ADDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9064 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9065 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
AnnaBridge 171:3a7713b1edbc 9066 #define I2C_ISR_NACKF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9067 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9068 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
AnnaBridge 171:3a7713b1edbc 9069 #define I2C_ISR_STOPF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9070 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9071 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
AnnaBridge 171:3a7713b1edbc 9072 #define I2C_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9073 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9074 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
AnnaBridge 171:3a7713b1edbc 9075 #define I2C_ISR_TCR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9076 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9077 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
AnnaBridge 171:3a7713b1edbc 9078 #define I2C_ISR_BERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9079 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9080 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
AnnaBridge 171:3a7713b1edbc 9081 #define I2C_ISR_ARLO_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9082 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9083 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
AnnaBridge 171:3a7713b1edbc 9084 #define I2C_ISR_OVR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9085 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9086 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 171:3a7713b1edbc 9087 #define I2C_ISR_PECERR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9088 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9089 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
AnnaBridge 171:3a7713b1edbc 9090 #define I2C_ISR_TIMEOUT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9091 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9092 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
AnnaBridge 171:3a7713b1edbc 9093 #define I2C_ISR_ALERT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9094 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9095 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
AnnaBridge 171:3a7713b1edbc 9096 #define I2C_ISR_BUSY_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9097 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9098 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
AnnaBridge 171:3a7713b1edbc 9099 #define I2C_ISR_DIR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9100 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9101 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
AnnaBridge 171:3a7713b1edbc 9102 #define I2C_ISR_ADDCODE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9103 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
AnnaBridge 171:3a7713b1edbc 9104 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
AnnaBridge 171:3a7713b1edbc 9105
AnnaBridge 171:3a7713b1edbc 9106 /****************** Bit definition for I2C_ICR register *********************/
AnnaBridge 171:3a7713b1edbc 9107 #define I2C_ICR_ADDRCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9108 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9109 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
AnnaBridge 171:3a7713b1edbc 9110 #define I2C_ICR_NACKCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9111 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9112 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
AnnaBridge 171:3a7713b1edbc 9113 #define I2C_ICR_STOPCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9114 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9115 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
AnnaBridge 171:3a7713b1edbc 9116 #define I2C_ICR_BERRCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9117 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9118 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
AnnaBridge 171:3a7713b1edbc 9119 #define I2C_ICR_ARLOCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9120 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9121 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
AnnaBridge 171:3a7713b1edbc 9122 #define I2C_ICR_OVRCF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9123 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9124 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
AnnaBridge 171:3a7713b1edbc 9125 #define I2C_ICR_PECCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9126 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9127 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
AnnaBridge 171:3a7713b1edbc 9128 #define I2C_ICR_TIMOUTCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9129 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9130 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
AnnaBridge 171:3a7713b1edbc 9131 #define I2C_ICR_ALERTCF_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9132 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9133 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
AnnaBridge 171:3a7713b1edbc 9134
AnnaBridge 171:3a7713b1edbc 9135 /****************** Bit definition for I2C_PECR register *********************/
AnnaBridge 171:3a7713b1edbc 9136 #define I2C_PECR_PEC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9137 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9138 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
AnnaBridge 171:3a7713b1edbc 9139
AnnaBridge 171:3a7713b1edbc 9140 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 171:3a7713b1edbc 9141 #define I2C_RXDR_RXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9142 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9143 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
AnnaBridge 171:3a7713b1edbc 9144
AnnaBridge 171:3a7713b1edbc 9145 /****************** Bit definition for I2C_TXDR register *********************/
AnnaBridge 171:3a7713b1edbc 9146 #define I2C_TXDR_TXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9147 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9148 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
AnnaBridge 171:3a7713b1edbc 9149
AnnaBridge 171:3a7713b1edbc 9150
AnnaBridge 171:3a7713b1edbc 9151 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9152 /* */
AnnaBridge 171:3a7713b1edbc 9153 /* Independent WATCHDOG */
AnnaBridge 171:3a7713b1edbc 9154 /* */
AnnaBridge 171:3a7713b1edbc 9155 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9156 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 171:3a7713b1edbc 9157 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9158 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 9159 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
AnnaBridge 171:3a7713b1edbc 9160
AnnaBridge 171:3a7713b1edbc 9161 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 171:3a7713b1edbc 9162 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9163 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 9164 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 171:3a7713b1edbc 9165 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 171:3a7713b1edbc 9166 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 171:3a7713b1edbc 9167 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
AnnaBridge 171:3a7713b1edbc 9168
AnnaBridge 171:3a7713b1edbc 9169 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 171:3a7713b1edbc 9170 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9171 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 9172 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
AnnaBridge 171:3a7713b1edbc 9173
AnnaBridge 171:3a7713b1edbc 9174 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 9175 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9176 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9177 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
AnnaBridge 171:3a7713b1edbc 9178 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9179 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9180 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
AnnaBridge 171:3a7713b1edbc 9181 #define IWDG_SR_WVU_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9182 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9183 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
AnnaBridge 171:3a7713b1edbc 9184
AnnaBridge 171:3a7713b1edbc 9185 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 171:3a7713b1edbc 9186 #define IWDG_WINR_WIN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9187 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 9188 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
AnnaBridge 171:3a7713b1edbc 9189
AnnaBridge 171:3a7713b1edbc 9190 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9191 /* */
AnnaBridge 171:3a7713b1edbc 9192 /* LCD-TFT Display Controller (LTDC) */
AnnaBridge 171:3a7713b1edbc 9193 /* */
AnnaBridge 171:3a7713b1edbc 9194 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9195
AnnaBridge 171:3a7713b1edbc 9196 /******************** Bit definition for LTDC_SSCR register *****************/
AnnaBridge 171:3a7713b1edbc 9197
AnnaBridge 171:3a7713b1edbc 9198 #define LTDC_SSCR_VSH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9199 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 9200 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
AnnaBridge 171:3a7713b1edbc 9201 #define LTDC_SSCR_HSW_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9202 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 9203 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
AnnaBridge 171:3a7713b1edbc 9204
AnnaBridge 171:3a7713b1edbc 9205 /******************** Bit definition for LTDC_BPCR register *****************/
AnnaBridge 171:3a7713b1edbc 9206
AnnaBridge 171:3a7713b1edbc 9207 #define LTDC_BPCR_AVBP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9208 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 9209 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
AnnaBridge 171:3a7713b1edbc 9210 #define LTDC_BPCR_AHBP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9211 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 9212 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
AnnaBridge 171:3a7713b1edbc 9213
AnnaBridge 171:3a7713b1edbc 9214 /******************** Bit definition for LTDC_AWCR register *****************/
AnnaBridge 171:3a7713b1edbc 9215
AnnaBridge 171:3a7713b1edbc 9216 #define LTDC_AWCR_AAH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9217 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 9218 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
AnnaBridge 171:3a7713b1edbc 9219 #define LTDC_AWCR_AAW_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9220 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 9221 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
AnnaBridge 171:3a7713b1edbc 9222
AnnaBridge 171:3a7713b1edbc 9223 /******************** Bit definition for LTDC_TWCR register *****************/
AnnaBridge 171:3a7713b1edbc 9224
AnnaBridge 171:3a7713b1edbc 9225 #define LTDC_TWCR_TOTALH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9226 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 9227 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
AnnaBridge 171:3a7713b1edbc 9228 #define LTDC_TWCR_TOTALW_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9229 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 9230 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
AnnaBridge 171:3a7713b1edbc 9231
AnnaBridge 171:3a7713b1edbc 9232 /******************** Bit definition for LTDC_GCR register ******************/
AnnaBridge 171:3a7713b1edbc 9233
AnnaBridge 171:3a7713b1edbc 9234 #define LTDC_GCR_LTDCEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9235 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9236 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
AnnaBridge 171:3a7713b1edbc 9237 #define LTDC_GCR_DBW_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9238 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 9239 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
AnnaBridge 171:3a7713b1edbc 9240 #define LTDC_GCR_DGW_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9241 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 9242 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
AnnaBridge 171:3a7713b1edbc 9243 #define LTDC_GCR_DRW_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9244 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 9245 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
AnnaBridge 171:3a7713b1edbc 9246 #define LTDC_GCR_DEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9247 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9248 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
AnnaBridge 171:3a7713b1edbc 9249 #define LTDC_GCR_PCPOL_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9250 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9251 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
AnnaBridge 171:3a7713b1edbc 9252 #define LTDC_GCR_DEPOL_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9253 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9254 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
AnnaBridge 171:3a7713b1edbc 9255 #define LTDC_GCR_VSPOL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9256 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9257 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
AnnaBridge 171:3a7713b1edbc 9258 #define LTDC_GCR_HSPOL_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9259 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9260 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
AnnaBridge 171:3a7713b1edbc 9261
AnnaBridge 171:3a7713b1edbc 9262 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 9263 #define LTDC_GCR_DTEN LTDC_GCR_DEN
AnnaBridge 171:3a7713b1edbc 9264
AnnaBridge 171:3a7713b1edbc 9265 /******************** Bit definition for LTDC_SRCR register *****************/
AnnaBridge 171:3a7713b1edbc 9266
AnnaBridge 171:3a7713b1edbc 9267 #define LTDC_SRCR_IMR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9268 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9269 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
AnnaBridge 171:3a7713b1edbc 9270 #define LTDC_SRCR_VBR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9271 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9272 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
AnnaBridge 171:3a7713b1edbc 9273
AnnaBridge 171:3a7713b1edbc 9274 /******************** Bit definition for LTDC_BCCR register *****************/
AnnaBridge 171:3a7713b1edbc 9275
AnnaBridge 171:3a7713b1edbc 9276 #define LTDC_BCCR_BCBLUE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9277 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9278 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
AnnaBridge 171:3a7713b1edbc 9279 #define LTDC_BCCR_BCGREEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9280 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 9281 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
AnnaBridge 171:3a7713b1edbc 9282 #define LTDC_BCCR_BCRED_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9283 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 9284 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
AnnaBridge 171:3a7713b1edbc 9285
AnnaBridge 171:3a7713b1edbc 9286 /******************** Bit definition for LTDC_IER register ******************/
AnnaBridge 171:3a7713b1edbc 9287
AnnaBridge 171:3a7713b1edbc 9288 #define LTDC_IER_LIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9289 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9290 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 9291 #define LTDC_IER_FUIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9292 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9293 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 9294 #define LTDC_IER_TERRIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9295 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9296 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 9297 #define LTDC_IER_RRIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9298 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9299 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
AnnaBridge 171:3a7713b1edbc 9300
AnnaBridge 171:3a7713b1edbc 9301 /******************** Bit definition for LTDC_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 9302
AnnaBridge 171:3a7713b1edbc 9303 #define LTDC_ISR_LIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9304 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9305 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 9306 #define LTDC_ISR_FUIF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9307 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9308 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 9309 #define LTDC_ISR_TERRIF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9310 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9311 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 9312 #define LTDC_ISR_RRIF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9313 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9314 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
AnnaBridge 171:3a7713b1edbc 9315
AnnaBridge 171:3a7713b1edbc 9316 /******************** Bit definition for LTDC_ICR register ******************/
AnnaBridge 171:3a7713b1edbc 9317
AnnaBridge 171:3a7713b1edbc 9318 #define LTDC_ICR_CLIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9319 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9320 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 9321 #define LTDC_ICR_CFUIF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9322 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9323 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 9324 #define LTDC_ICR_CTERRIF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9325 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9326 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 9327 #define LTDC_ICR_CRRIF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9328 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9329 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
AnnaBridge 171:3a7713b1edbc 9330
AnnaBridge 171:3a7713b1edbc 9331 /******************** Bit definition for LTDC_LIPCR register ****************/
AnnaBridge 171:3a7713b1edbc 9332
AnnaBridge 171:3a7713b1edbc 9333 #define LTDC_LIPCR_LIPOS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9334 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 9335 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
AnnaBridge 171:3a7713b1edbc 9336
AnnaBridge 171:3a7713b1edbc 9337 /******************** Bit definition for LTDC_CPSR register *****************/
AnnaBridge 171:3a7713b1edbc 9338
AnnaBridge 171:3a7713b1edbc 9339 #define LTDC_CPSR_CYPOS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9340 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 9341 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
AnnaBridge 171:3a7713b1edbc 9342 #define LTDC_CPSR_CXPOS_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9343 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 9344 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
AnnaBridge 171:3a7713b1edbc 9345
AnnaBridge 171:3a7713b1edbc 9346 /******************** Bit definition for LTDC_CDSR register *****************/
AnnaBridge 171:3a7713b1edbc 9347
AnnaBridge 171:3a7713b1edbc 9348 #define LTDC_CDSR_VDES_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9349 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9350 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
AnnaBridge 171:3a7713b1edbc 9351 #define LTDC_CDSR_HDES_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9352 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9353 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
AnnaBridge 171:3a7713b1edbc 9354 #define LTDC_CDSR_VSYNCS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9355 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9356 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
AnnaBridge 171:3a7713b1edbc 9357 #define LTDC_CDSR_HSYNCS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9358 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9359 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
AnnaBridge 171:3a7713b1edbc 9360
AnnaBridge 171:3a7713b1edbc 9361 /******************** Bit definition for LTDC_LxCR register *****************/
AnnaBridge 171:3a7713b1edbc 9362
AnnaBridge 171:3a7713b1edbc 9363 #define LTDC_LxCR_LEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9364 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9365 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
AnnaBridge 171:3a7713b1edbc 9366 #define LTDC_LxCR_COLKEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9367 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9368 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
AnnaBridge 171:3a7713b1edbc 9369 #define LTDC_LxCR_CLUTEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9370 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9371 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
AnnaBridge 171:3a7713b1edbc 9372
AnnaBridge 171:3a7713b1edbc 9373 /******************** Bit definition for LTDC_LxWHPCR register **************/
AnnaBridge 171:3a7713b1edbc 9374
AnnaBridge 171:3a7713b1edbc 9375 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9376 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 9377 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
AnnaBridge 171:3a7713b1edbc 9378 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9379 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 9380 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
AnnaBridge 171:3a7713b1edbc 9381
AnnaBridge 171:3a7713b1edbc 9382 /******************** Bit definition for LTDC_LxWVPCR register **************/
AnnaBridge 171:3a7713b1edbc 9383
AnnaBridge 171:3a7713b1edbc 9384 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9385 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 9386 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
AnnaBridge 171:3a7713b1edbc 9387 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9388 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 9389 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
AnnaBridge 171:3a7713b1edbc 9390
AnnaBridge 171:3a7713b1edbc 9391 /******************** Bit definition for LTDC_LxCKCR register ***************/
AnnaBridge 171:3a7713b1edbc 9392
AnnaBridge 171:3a7713b1edbc 9393 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9394 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9395 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
AnnaBridge 171:3a7713b1edbc 9396 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9397 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 9398 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
AnnaBridge 171:3a7713b1edbc 9399 #define LTDC_LxCKCR_CKRED_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9400 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 9401 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
AnnaBridge 171:3a7713b1edbc 9402
AnnaBridge 171:3a7713b1edbc 9403 /******************** Bit definition for LTDC_LxPFCR register ***************/
AnnaBridge 171:3a7713b1edbc 9404
AnnaBridge 171:3a7713b1edbc 9405 #define LTDC_LxPFCR_PF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9406 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 9407 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
AnnaBridge 171:3a7713b1edbc 9408
AnnaBridge 171:3a7713b1edbc 9409 /******************** Bit definition for LTDC_LxCACR register ***************/
AnnaBridge 171:3a7713b1edbc 9410
AnnaBridge 171:3a7713b1edbc 9411 #define LTDC_LxCACR_CONSTA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9412 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9413 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
AnnaBridge 171:3a7713b1edbc 9414
AnnaBridge 171:3a7713b1edbc 9415 /******************** Bit definition for LTDC_LxDCCR register ***************/
AnnaBridge 171:3a7713b1edbc 9416
AnnaBridge 171:3a7713b1edbc 9417 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9418 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9419 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
AnnaBridge 171:3a7713b1edbc 9420 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9421 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 9422 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
AnnaBridge 171:3a7713b1edbc 9423 #define LTDC_LxDCCR_DCRED_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9424 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 9425 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
AnnaBridge 171:3a7713b1edbc 9426 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9427 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 9428 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
AnnaBridge 171:3a7713b1edbc 9429
AnnaBridge 171:3a7713b1edbc 9430 /******************** Bit definition for LTDC_LxBFCR register ***************/
AnnaBridge 171:3a7713b1edbc 9431
AnnaBridge 171:3a7713b1edbc 9432 #define LTDC_LxBFCR_BF2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9433 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 9434 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
AnnaBridge 171:3a7713b1edbc 9435 #define LTDC_LxBFCR_BF1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9436 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 9437 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
AnnaBridge 171:3a7713b1edbc 9438
AnnaBridge 171:3a7713b1edbc 9439 /******************** Bit definition for LTDC_LxCFBAR register **************/
AnnaBridge 171:3a7713b1edbc 9440
AnnaBridge 171:3a7713b1edbc 9441 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9442 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 9443 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
AnnaBridge 171:3a7713b1edbc 9444
AnnaBridge 171:3a7713b1edbc 9445 /******************** Bit definition for LTDC_LxCFBLR register **************/
AnnaBridge 171:3a7713b1edbc 9446
AnnaBridge 171:3a7713b1edbc 9447 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9448 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
AnnaBridge 171:3a7713b1edbc 9449 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
AnnaBridge 171:3a7713b1edbc 9450 #define LTDC_LxCFBLR_CFBP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9451 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
AnnaBridge 171:3a7713b1edbc 9452 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
AnnaBridge 171:3a7713b1edbc 9453
AnnaBridge 171:3a7713b1edbc 9454 /******************** Bit definition for LTDC_LxCFBLNR register *************/
AnnaBridge 171:3a7713b1edbc 9455
AnnaBridge 171:3a7713b1edbc 9456 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9457 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 9458 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
AnnaBridge 171:3a7713b1edbc 9459
AnnaBridge 171:3a7713b1edbc 9460 /******************** Bit definition for LTDC_LxCLUTWR register *************/
AnnaBridge 171:3a7713b1edbc 9461
AnnaBridge 171:3a7713b1edbc 9462 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9463 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9464 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
AnnaBridge 171:3a7713b1edbc 9465 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9466 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 9467 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
AnnaBridge 171:3a7713b1edbc 9468 #define LTDC_LxCLUTWR_RED_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9469 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 9470 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
AnnaBridge 171:3a7713b1edbc 9471 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9472 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 9473 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
AnnaBridge 171:3a7713b1edbc 9474
AnnaBridge 171:3a7713b1edbc 9475 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9476 /* */
AnnaBridge 171:3a7713b1edbc 9477 /* Power Control */
AnnaBridge 171:3a7713b1edbc 9478 /* */
AnnaBridge 171:3a7713b1edbc 9479 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9480 /******************** Bit definition for PWR_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 9481 #define PWR_CR1_LPDS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9482 #define PWR_CR1_LPDS_Msk (0x1U << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9483 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low-Power Deepsleep */
AnnaBridge 171:3a7713b1edbc 9484 #define PWR_CR1_PDDS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9485 #define PWR_CR1_PDDS_Msk (0x1U << PWR_CR1_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9486 #define PWR_CR1_PDDS PWR_CR1_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 171:3a7713b1edbc 9487 #define PWR_CR1_CSBF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9488 #define PWR_CR1_CSBF_Msk (0x1U << PWR_CR1_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9489 #define PWR_CR1_CSBF PWR_CR1_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 171:3a7713b1edbc 9490 #define PWR_CR1_PVDE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9491 #define PWR_CR1_PVDE_Msk (0x1U << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9492 #define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 171:3a7713b1edbc 9493 #define PWR_CR1_PLS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9494 #define PWR_CR1_PLS_Msk (0x7U << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 9495 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 171:3a7713b1edbc 9496 #define PWR_CR1_PLS_0 (0x1U << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9497 #define PWR_CR1_PLS_1 (0x2U << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9498 #define PWR_CR1_PLS_2 (0x4U << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9499
AnnaBridge 171:3a7713b1edbc 9500 /*!< PVD level configuration */
AnnaBridge 171:3a7713b1edbc 9501 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 171:3a7713b1edbc 9502 #define PWR_CR1_PLS_LEV1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9503 #define PWR_CR1_PLS_LEV1_Msk (0x1U << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9504 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
AnnaBridge 171:3a7713b1edbc 9505 #define PWR_CR1_PLS_LEV2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9506 #define PWR_CR1_PLS_LEV2_Msk (0x1U << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9507 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
AnnaBridge 171:3a7713b1edbc 9508 #define PWR_CR1_PLS_LEV3_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9509 #define PWR_CR1_PLS_LEV3_Msk (0x3U << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 9510 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
AnnaBridge 171:3a7713b1edbc 9511 #define PWR_CR1_PLS_LEV4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9512 #define PWR_CR1_PLS_LEV4_Msk (0x1U << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9513 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
AnnaBridge 171:3a7713b1edbc 9514 #define PWR_CR1_PLS_LEV5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9515 #define PWR_CR1_PLS_LEV5_Msk (0x5U << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
AnnaBridge 171:3a7713b1edbc 9516 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
AnnaBridge 171:3a7713b1edbc 9517 #define PWR_CR1_PLS_LEV6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9518 #define PWR_CR1_PLS_LEV6_Msk (0x3U << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 9519 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
AnnaBridge 171:3a7713b1edbc 9520 #define PWR_CR1_PLS_LEV7_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9521 #define PWR_CR1_PLS_LEV7_Msk (0x7U << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 9522 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
AnnaBridge 171:3a7713b1edbc 9523 #define PWR_CR1_DBP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9524 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9525 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 171:3a7713b1edbc 9526 #define PWR_CR1_FPDS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9527 #define PWR_CR1_FPDS_Msk (0x1U << PWR_CR1_FPDS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9528 #define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down in Stop mode */
AnnaBridge 171:3a7713b1edbc 9529 #define PWR_CR1_LPUDS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9530 #define PWR_CR1_LPUDS_Msk (0x1U << PWR_CR1_LPUDS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9531 #define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk /*!< Low-power regulator in deepsleep under-drive mode */
AnnaBridge 171:3a7713b1edbc 9532 #define PWR_CR1_MRUDS_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9533 #define PWR_CR1_MRUDS_Msk (0x1U << PWR_CR1_MRUDS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9534 #define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk /*!< Main regulator in deepsleep under-drive mode */
AnnaBridge 171:3a7713b1edbc 9535 #define PWR_CR1_ADCDC1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9536 #define PWR_CR1_ADCDC1_Msk (0x1U << PWR_CR1_ADCDC1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9537 #define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 171:3a7713b1edbc 9538 #define PWR_CR1_VOS_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9539 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 9540 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 171:3a7713b1edbc 9541 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9542 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9543 #define PWR_CR1_ODEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9544 #define PWR_CR1_ODEN_Msk (0x1U << PWR_CR1_ODEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9545 #define PWR_CR1_ODEN PWR_CR1_ODEN_Msk /*!< Over Drive enable */
AnnaBridge 171:3a7713b1edbc 9546 #define PWR_CR1_ODSWEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9547 #define PWR_CR1_ODSWEN_Msk (0x1U << PWR_CR1_ODSWEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9548 #define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk /*!< Over Drive switch enabled */
AnnaBridge 171:3a7713b1edbc 9549 #define PWR_CR1_UDEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9550 #define PWR_CR1_UDEN_Msk (0x3U << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 9551 #define PWR_CR1_UDEN PWR_CR1_UDEN_Msk /*!< Under Drive enable in stop mode */
AnnaBridge 171:3a7713b1edbc 9552 #define PWR_CR1_UDEN_0 (0x1U << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9553 #define PWR_CR1_UDEN_1 (0x2U << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9554
AnnaBridge 171:3a7713b1edbc 9555 /******************* Bit definition for PWR_CSR1 register ********************/
AnnaBridge 171:3a7713b1edbc 9556 #define PWR_CSR1_WUIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9557 #define PWR_CSR1_WUIF_Msk (0x1U << PWR_CSR1_WUIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9558 #define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk /*!< Wake up internal Flag */
AnnaBridge 171:3a7713b1edbc 9559 #define PWR_CSR1_SBF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9560 #define PWR_CSR1_SBF_Msk (0x1U << PWR_CSR1_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9561 #define PWR_CSR1_SBF PWR_CSR1_SBF_Msk /*!< Standby Flag */
AnnaBridge 171:3a7713b1edbc 9562 #define PWR_CSR1_PVDO_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9563 #define PWR_CSR1_PVDO_Msk (0x1U << PWR_CSR1_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9564 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< PVD Output */
AnnaBridge 171:3a7713b1edbc 9565 #define PWR_CSR1_BRR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9566 #define PWR_CSR1_BRR_Msk (0x1U << PWR_CSR1_BRR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9567 #define PWR_CSR1_BRR PWR_CSR1_BRR_Msk /*!< Backup regulator ready */
AnnaBridge 171:3a7713b1edbc 9568 #define PWR_CSR1_EIWUP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9569 #define PWR_CSR1_EIWUP_Msk (0x1U << PWR_CSR1_EIWUP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9570 #define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk /*!< Enable internal wakeup */
AnnaBridge 171:3a7713b1edbc 9571 #define PWR_CSR1_BRE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9572 #define PWR_CSR1_BRE_Msk (0x1U << PWR_CSR1_BRE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9573 #define PWR_CSR1_BRE PWR_CSR1_BRE_Msk /*!< Backup regulator enable */
AnnaBridge 171:3a7713b1edbc 9574 #define PWR_CSR1_VOSRDY_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9575 #define PWR_CSR1_VOSRDY_Msk (0x1U << PWR_CSR1_VOSRDY_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9576 #define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
AnnaBridge 171:3a7713b1edbc 9577 #define PWR_CSR1_ODRDY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9578 #define PWR_CSR1_ODRDY_Msk (0x1U << PWR_CSR1_ODRDY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9579 #define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk /*!< Over Drive generator ready */
AnnaBridge 171:3a7713b1edbc 9580 #define PWR_CSR1_ODSWRDY_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9581 #define PWR_CSR1_ODSWRDY_Msk (0x1U << PWR_CSR1_ODSWRDY_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9582 #define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk /*!< Over Drive Switch ready */
AnnaBridge 171:3a7713b1edbc 9583 #define PWR_CSR1_UDRDY_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9584 #define PWR_CSR1_UDRDY_Msk (0x3U << PWR_CSR1_UDRDY_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 9585 #define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk /*!< Under Drive ready */
AnnaBridge 171:3a7713b1edbc 9586
AnnaBridge 171:3a7713b1edbc 9587 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 9588 #define PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY
AnnaBridge 171:3a7713b1edbc 9589
AnnaBridge 171:3a7713b1edbc 9590 /******************** Bit definition for PWR_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 9591 #define PWR_CR2_CWUPF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9592 #define PWR_CR2_CWUPF1_Msk (0x1U << PWR_CR2_CWUPF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9593 #define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk /*!< Clear Wakeup Pin Flag for PA0 */
AnnaBridge 171:3a7713b1edbc 9594 #define PWR_CR2_CWUPF2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9595 #define PWR_CR2_CWUPF2_Msk (0x1U << PWR_CR2_CWUPF2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9596 #define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk /*!< Clear Wakeup Pin Flag for PA2 */
AnnaBridge 171:3a7713b1edbc 9597 #define PWR_CR2_CWUPF3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9598 #define PWR_CR2_CWUPF3_Msk (0x1U << PWR_CR2_CWUPF3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9599 #define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk /*!< Clear Wakeup Pin Flag for PC1 */
AnnaBridge 171:3a7713b1edbc 9600 #define PWR_CR2_CWUPF4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9601 #define PWR_CR2_CWUPF4_Msk (0x1U << PWR_CR2_CWUPF4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9602 #define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk /*!< Clear Wakeup Pin Flag for PC13 */
AnnaBridge 171:3a7713b1edbc 9603 #define PWR_CR2_CWUPF5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9604 #define PWR_CR2_CWUPF5_Msk (0x1U << PWR_CR2_CWUPF5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9605 #define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk /*!< Clear Wakeup Pin Flag for PI8 */
AnnaBridge 171:3a7713b1edbc 9606 #define PWR_CR2_CWUPF6_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9607 #define PWR_CR2_CWUPF6_Msk (0x1U << PWR_CR2_CWUPF6_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9608 #define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk /*!< Clear Wakeup Pin Flag for PI11 */
AnnaBridge 171:3a7713b1edbc 9609 #define PWR_CR2_WUPP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9610 #define PWR_CR2_WUPP1_Msk (0x1U << PWR_CR2_WUPP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9611 #define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk /*!< Wakeup Pin Polarity bit for PA0 */
AnnaBridge 171:3a7713b1edbc 9612 #define PWR_CR2_WUPP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9613 #define PWR_CR2_WUPP2_Msk (0x1U << PWR_CR2_WUPP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9614 #define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk /*!< Wakeup Pin Polarity bit for PA2 */
AnnaBridge 171:3a7713b1edbc 9615 #define PWR_CR2_WUPP3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9616 #define PWR_CR2_WUPP3_Msk (0x1U << PWR_CR2_WUPP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9617 #define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk /*!< Wakeup Pin Polarity bit for PC1 */
AnnaBridge 171:3a7713b1edbc 9618 #define PWR_CR2_WUPP4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9619 #define PWR_CR2_WUPP4_Msk (0x1U << PWR_CR2_WUPP4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9620 #define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk /*!< Wakeup Pin Polarity bit for PC13 */
AnnaBridge 171:3a7713b1edbc 9621 #define PWR_CR2_WUPP5_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9622 #define PWR_CR2_WUPP5_Msk (0x1U << PWR_CR2_WUPP5_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9623 #define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk /*!< Wakeup Pin Polarity bit for PI8 */
AnnaBridge 171:3a7713b1edbc 9624 #define PWR_CR2_WUPP6_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9625 #define PWR_CR2_WUPP6_Msk (0x1U << PWR_CR2_WUPP6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9626 #define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk /*!< Wakeup Pin Polarity bit for PI11 */
AnnaBridge 171:3a7713b1edbc 9627
AnnaBridge 171:3a7713b1edbc 9628 /******************* Bit definition for PWR_CSR2 register ********************/
AnnaBridge 171:3a7713b1edbc 9629 #define PWR_CSR2_WUPF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9630 #define PWR_CSR2_WUPF1_Msk (0x1U << PWR_CSR2_WUPF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9631 #define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk /*!< Wakeup Pin Flag for PA0 */
AnnaBridge 171:3a7713b1edbc 9632 #define PWR_CSR2_WUPF2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9633 #define PWR_CSR2_WUPF2_Msk (0x1U << PWR_CSR2_WUPF2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9634 #define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk /*!< Wakeup Pin Flag for PA2 */
AnnaBridge 171:3a7713b1edbc 9635 #define PWR_CSR2_WUPF3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9636 #define PWR_CSR2_WUPF3_Msk (0x1U << PWR_CSR2_WUPF3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9637 #define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk /*!< Wakeup Pin Flag for PC1 */
AnnaBridge 171:3a7713b1edbc 9638 #define PWR_CSR2_WUPF4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9639 #define PWR_CSR2_WUPF4_Msk (0x1U << PWR_CSR2_WUPF4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9640 #define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk /*!< Wakeup Pin Flag for PC13 */
AnnaBridge 171:3a7713b1edbc 9641 #define PWR_CSR2_WUPF5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9642 #define PWR_CSR2_WUPF5_Msk (0x1U << PWR_CSR2_WUPF5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9643 #define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk /*!< Wakeup Pin Flag for PI8 */
AnnaBridge 171:3a7713b1edbc 9644 #define PWR_CSR2_WUPF6_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9645 #define PWR_CSR2_WUPF6_Msk (0x1U << PWR_CSR2_WUPF6_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9646 #define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk /*!< Wakeup Pin Flag for PI11 */
AnnaBridge 171:3a7713b1edbc 9647 #define PWR_CSR2_EWUP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9648 #define PWR_CSR2_EWUP1_Msk (0x1U << PWR_CSR2_EWUP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9649 #define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk /*!< Enable Wakeup Pin PA0 */
AnnaBridge 171:3a7713b1edbc 9650 #define PWR_CSR2_EWUP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9651 #define PWR_CSR2_EWUP2_Msk (0x1U << PWR_CSR2_EWUP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9652 #define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk /*!< Enable Wakeup Pin PA2 */
AnnaBridge 171:3a7713b1edbc 9653 #define PWR_CSR2_EWUP3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9654 #define PWR_CSR2_EWUP3_Msk (0x1U << PWR_CSR2_EWUP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9655 #define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk /*!< Enable Wakeup Pin PC1 */
AnnaBridge 171:3a7713b1edbc 9656 #define PWR_CSR2_EWUP4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9657 #define PWR_CSR2_EWUP4_Msk (0x1U << PWR_CSR2_EWUP4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9658 #define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk /*!< Enable Wakeup Pin PC13 */
AnnaBridge 171:3a7713b1edbc 9659 #define PWR_CSR2_EWUP5_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9660 #define PWR_CSR2_EWUP5_Msk (0x1U << PWR_CSR2_EWUP5_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9661 #define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk /*!< Enable Wakeup Pin PI8 */
AnnaBridge 171:3a7713b1edbc 9662 #define PWR_CSR2_EWUP6_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9663 #define PWR_CSR2_EWUP6_Msk (0x1U << PWR_CSR2_EWUP6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9664 #define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk /*!< Enable Wakeup Pin PI11 */
AnnaBridge 171:3a7713b1edbc 9665
AnnaBridge 171:3a7713b1edbc 9666 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9667 /* */
AnnaBridge 171:3a7713b1edbc 9668 /* QUADSPI */
AnnaBridge 171:3a7713b1edbc 9669 /* */
AnnaBridge 171:3a7713b1edbc 9670 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9671 /* QUADSPI IP version */
AnnaBridge 171:3a7713b1edbc 9672 #define QSPI1_V1_0
AnnaBridge 171:3a7713b1edbc 9673 /***************** Bit definition for QUADSPI_CR register *******************/
AnnaBridge 171:3a7713b1edbc 9674 #define QUADSPI_CR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9675 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9676 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
AnnaBridge 171:3a7713b1edbc 9677 #define QUADSPI_CR_ABORT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9678 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9679 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
AnnaBridge 171:3a7713b1edbc 9680 #define QUADSPI_CR_DMAEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9681 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9682 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
AnnaBridge 171:3a7713b1edbc 9683 #define QUADSPI_CR_TCEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9684 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9685 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
AnnaBridge 171:3a7713b1edbc 9686 #define QUADSPI_CR_SSHIFT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9687 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9688 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
AnnaBridge 171:3a7713b1edbc 9689 #define QUADSPI_CR_DFM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9690 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9691 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
AnnaBridge 171:3a7713b1edbc 9692 #define QUADSPI_CR_FSEL_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9693 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9694 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
AnnaBridge 171:3a7713b1edbc 9695 #define QUADSPI_CR_FTHRES_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9696 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 9697 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
AnnaBridge 171:3a7713b1edbc 9698 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9699 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9700 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9701 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9702 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9703 #define QUADSPI_CR_TEIE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9704 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9705 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 9706 #define QUADSPI_CR_TCIE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9707 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9708 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 9709 #define QUADSPI_CR_FTIE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9710 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9711 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 9712 #define QUADSPI_CR_SMIE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9713 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9714 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 9715 #define QUADSPI_CR_TOIE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9716 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9717 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 9718 #define QUADSPI_CR_APMS_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9719 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9720 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 9721 #define QUADSPI_CR_PMM_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9722 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9723 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
AnnaBridge 171:3a7713b1edbc 9724 #define QUADSPI_CR_PRESCALER_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9725 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 9726 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
AnnaBridge 171:3a7713b1edbc 9727 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9728 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9729 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9730 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9731 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9732 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9733 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9734 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9735
AnnaBridge 171:3a7713b1edbc 9736 /***************** Bit definition for QUADSPI_DCR register ******************/
AnnaBridge 171:3a7713b1edbc 9737 #define QUADSPI_DCR_CKMODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9738 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9739 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
AnnaBridge 171:3a7713b1edbc 9740 #define QUADSPI_DCR_CSHT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9741 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 9742 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
AnnaBridge 171:3a7713b1edbc 9743 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9744 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9745 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9746 #define QUADSPI_DCR_FSIZE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9747 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 9748 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
AnnaBridge 171:3a7713b1edbc 9749 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9750 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9751 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9752 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9753 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9754
AnnaBridge 171:3a7713b1edbc 9755 /****************** Bit definition for QUADSPI_SR register *******************/
AnnaBridge 171:3a7713b1edbc 9756 #define QUADSPI_SR_TEF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9757 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9758 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
AnnaBridge 171:3a7713b1edbc 9759 #define QUADSPI_SR_TCF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9760 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9761 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
AnnaBridge 171:3a7713b1edbc 9762 #define QUADSPI_SR_FTF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9763 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9764 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
AnnaBridge 171:3a7713b1edbc 9765 #define QUADSPI_SR_SMF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9766 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9767 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
AnnaBridge 171:3a7713b1edbc 9768 #define QUADSPI_SR_TOF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9769 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9770 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
AnnaBridge 171:3a7713b1edbc 9771 #define QUADSPI_SR_BUSY_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9772 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9773 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
AnnaBridge 171:3a7713b1edbc 9774 #define QUADSPI_SR_FLEVEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9775 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 9776 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
AnnaBridge 171:3a7713b1edbc 9777 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9778 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9779 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9780 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9781 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9782
AnnaBridge 171:3a7713b1edbc 9783 /****************** Bit definition for QUADSPI_FCR register ******************/
AnnaBridge 171:3a7713b1edbc 9784 #define QUADSPI_FCR_CTEF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9785 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9786 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
AnnaBridge 171:3a7713b1edbc 9787 #define QUADSPI_FCR_CTCF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9788 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9789 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
AnnaBridge 171:3a7713b1edbc 9790 #define QUADSPI_FCR_CSMF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9791 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9792 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
AnnaBridge 171:3a7713b1edbc 9793 #define QUADSPI_FCR_CTOF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9794 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9795 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
AnnaBridge 171:3a7713b1edbc 9796
AnnaBridge 171:3a7713b1edbc 9797 /****************** Bit definition for QUADSPI_DLR register ******************/
AnnaBridge 171:3a7713b1edbc 9798 #define QUADSPI_DLR_DL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9799 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 9800 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
AnnaBridge 171:3a7713b1edbc 9801
AnnaBridge 171:3a7713b1edbc 9802 /****************** Bit definition for QUADSPI_CCR register ******************/
AnnaBridge 171:3a7713b1edbc 9803 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9804 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 9805 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
AnnaBridge 171:3a7713b1edbc 9806 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9807 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9808 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9809 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9810 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9811 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9812 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9813 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9814 #define QUADSPI_CCR_IMODE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9815 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 9816 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
AnnaBridge 171:3a7713b1edbc 9817 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9818 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9819 #define QUADSPI_CCR_ADMODE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9820 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 9821 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
AnnaBridge 171:3a7713b1edbc 9822 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9823 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9824 #define QUADSPI_CCR_ADSIZE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9825 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 9826 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
AnnaBridge 171:3a7713b1edbc 9827 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9828 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9829 #define QUADSPI_CCR_ABMODE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9830 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 9831 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
AnnaBridge 171:3a7713b1edbc 9832 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9833 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9834 #define QUADSPI_CCR_ABSIZE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9835 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 9836 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
AnnaBridge 171:3a7713b1edbc 9837 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9838 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9839 #define QUADSPI_CCR_DCYC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9840 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
AnnaBridge 171:3a7713b1edbc 9841 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
AnnaBridge 171:3a7713b1edbc 9842 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9843 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9844 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9845 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9846 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9847 #define QUADSPI_CCR_DMODE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9848 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 9849 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
AnnaBridge 171:3a7713b1edbc 9850 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9851 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9852 #define QUADSPI_CCR_FMODE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9853 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 9854 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
AnnaBridge 171:3a7713b1edbc 9855 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9856 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9857 #define QUADSPI_CCR_SIOO_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9858 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9859 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
AnnaBridge 171:3a7713b1edbc 9860 #define QUADSPI_CCR_DHHC_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9861 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9862 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
AnnaBridge 171:3a7713b1edbc 9863 #define QUADSPI_CCR_DDRM_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9864 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9865 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
AnnaBridge 171:3a7713b1edbc 9866 /****************** Bit definition for QUADSPI_AR register *******************/
AnnaBridge 171:3a7713b1edbc 9867 #define QUADSPI_AR_ADDRESS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9868 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 9869 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
AnnaBridge 171:3a7713b1edbc 9870
AnnaBridge 171:3a7713b1edbc 9871 /****************** Bit definition for QUADSPI_ABR register ******************/
AnnaBridge 171:3a7713b1edbc 9872 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9873 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 9874 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
AnnaBridge 171:3a7713b1edbc 9875
AnnaBridge 171:3a7713b1edbc 9876 /****************** Bit definition for QUADSPI_DR register *******************/
AnnaBridge 171:3a7713b1edbc 9877 #define QUADSPI_DR_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9878 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 9879 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
AnnaBridge 171:3a7713b1edbc 9880
AnnaBridge 171:3a7713b1edbc 9881 /****************** Bit definition for QUADSPI_PSMKR register ****************/
AnnaBridge 171:3a7713b1edbc 9882 #define QUADSPI_PSMKR_MASK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9883 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 9884 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
AnnaBridge 171:3a7713b1edbc 9885
AnnaBridge 171:3a7713b1edbc 9886 /****************** Bit definition for QUADSPI_PSMAR register ****************/
AnnaBridge 171:3a7713b1edbc 9887 #define QUADSPI_PSMAR_MATCH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9888 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 9889 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
AnnaBridge 171:3a7713b1edbc 9890
AnnaBridge 171:3a7713b1edbc 9891 /****************** Bit definition for QUADSPI_PIR register *****************/
AnnaBridge 171:3a7713b1edbc 9892 #define QUADSPI_PIR_INTERVAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9893 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 9894 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
AnnaBridge 171:3a7713b1edbc 9895
AnnaBridge 171:3a7713b1edbc 9896 /****************** Bit definition for QUADSPI_LPTR register *****************/
AnnaBridge 171:3a7713b1edbc 9897 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9898 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 9899 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
AnnaBridge 171:3a7713b1edbc 9900
AnnaBridge 171:3a7713b1edbc 9901 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9902 /* */
AnnaBridge 171:3a7713b1edbc 9903 /* Reset and Clock Control */
AnnaBridge 171:3a7713b1edbc 9904 /* */
AnnaBridge 171:3a7713b1edbc 9905 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9906 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 9907 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9908 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9909 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 171:3a7713b1edbc 9910 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9911 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9912 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 171:3a7713b1edbc 9913 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9914 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 171:3a7713b1edbc 9915 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 171:3a7713b1edbc 9916 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9917 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9918 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9919 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9920 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9921 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9922 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 9923 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 171:3a7713b1edbc 9924 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9925 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9926 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9927 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9928 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9929 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9930 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9931 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9932 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9933 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9934 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 171:3a7713b1edbc 9935 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9936 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9937 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 171:3a7713b1edbc 9938 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9939 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9940 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 171:3a7713b1edbc 9941 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9942 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9943 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 171:3a7713b1edbc 9944 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9945 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9946 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 171:3a7713b1edbc 9947 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9948 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9949 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 171:3a7713b1edbc 9950 #define RCC_CR_PLLI2SON_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9951 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9952 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
AnnaBridge 171:3a7713b1edbc 9953 #define RCC_CR_PLLI2SRDY_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9954 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9955 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
AnnaBridge 171:3a7713b1edbc 9956 #define RCC_CR_PLLSAION_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9957 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9958 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
AnnaBridge 171:3a7713b1edbc 9959 #define RCC_CR_PLLSAIRDY_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9960 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9961 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
AnnaBridge 171:3a7713b1edbc 9962
AnnaBridge 171:3a7713b1edbc 9963 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 171:3a7713b1edbc 9964 #define RCC_PLLCFGR_PLLM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9965 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 9966 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 171:3a7713b1edbc 9967 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9968 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9969 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9970 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9971 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9972 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9973 #define RCC_PLLCFGR_PLLN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9974 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
AnnaBridge 171:3a7713b1edbc 9975 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 171:3a7713b1edbc 9976 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9977 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9978 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9979 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9980 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9981 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9982 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9983 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9984 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9985 #define RCC_PLLCFGR_PLLP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9986 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 9987 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 171:3a7713b1edbc 9988 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9989 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9990 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9991 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9992 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 171:3a7713b1edbc 9993 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9994 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9995 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
AnnaBridge 171:3a7713b1edbc 9996 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 171:3a7713b1edbc 9997 #define RCC_PLLCFGR_PLLQ_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9998 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 9999 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 171:3a7713b1edbc 10000 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10001 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10002 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10003 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10004
AnnaBridge 171:3a7713b1edbc 10005
AnnaBridge 171:3a7713b1edbc 10006 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 171:3a7713b1edbc 10007 /*!< SW configuration */
AnnaBridge 171:3a7713b1edbc 10008 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10009 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 10010 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 171:3a7713b1edbc 10011 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10012 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10013 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 171:3a7713b1edbc 10014 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 171:3a7713b1edbc 10015 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
AnnaBridge 171:3a7713b1edbc 10016
AnnaBridge 171:3a7713b1edbc 10017 /*!< SWS configuration */
AnnaBridge 171:3a7713b1edbc 10018 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10019 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 10020 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 171:3a7713b1edbc 10021 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10022 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10023 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 10024 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 10025 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
AnnaBridge 171:3a7713b1edbc 10026
AnnaBridge 171:3a7713b1edbc 10027 /*!< HPRE configuration */
AnnaBridge 171:3a7713b1edbc 10028 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10029 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 10030 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 171:3a7713b1edbc 10031 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10032 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10033 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10034 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10035
AnnaBridge 171:3a7713b1edbc 10036 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 171:3a7713b1edbc 10037 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 10038 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 10039 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 10040 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 10041 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 171:3a7713b1edbc 10042 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 171:3a7713b1edbc 10043 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 171:3a7713b1edbc 10044 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
AnnaBridge 171:3a7713b1edbc 10045
AnnaBridge 171:3a7713b1edbc 10046 /*!< PPRE1 configuration */
AnnaBridge 171:3a7713b1edbc 10047 #define RCC_CFGR_PPRE1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10048 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
AnnaBridge 171:3a7713b1edbc 10049 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 171:3a7713b1edbc 10050 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10051 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10052 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10053
AnnaBridge 171:3a7713b1edbc 10054 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 10055 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 10056 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 10057 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 10058 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 10059
AnnaBridge 171:3a7713b1edbc 10060 /*!< PPRE2 configuration */
AnnaBridge 171:3a7713b1edbc 10061 #define RCC_CFGR_PPRE2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10062 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 10063 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 171:3a7713b1edbc 10064 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10065 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10066 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10067
AnnaBridge 171:3a7713b1edbc 10068 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 10069 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 10070 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 10071 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 10072 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 10073
AnnaBridge 171:3a7713b1edbc 10074 /*!< RTCPRE configuration */
AnnaBridge 171:3a7713b1edbc 10075 #define RCC_CFGR_RTCPRE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10076 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 10077 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
AnnaBridge 171:3a7713b1edbc 10078 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10079 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10080 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10081 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10082 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10083
AnnaBridge 171:3a7713b1edbc 10084 /*!< MCO1 configuration */
AnnaBridge 171:3a7713b1edbc 10085 #define RCC_CFGR_MCO1_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10086 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 10087 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
AnnaBridge 171:3a7713b1edbc 10088 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10089 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10090
AnnaBridge 171:3a7713b1edbc 10091 #define RCC_CFGR_I2SSRC_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10092 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10093 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
AnnaBridge 171:3a7713b1edbc 10094
AnnaBridge 171:3a7713b1edbc 10095 #define RCC_CFGR_MCO1PRE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10096 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 10097 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
AnnaBridge 171:3a7713b1edbc 10098 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10099 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10100 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10101
AnnaBridge 171:3a7713b1edbc 10102 #define RCC_CFGR_MCO2PRE_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10103 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
AnnaBridge 171:3a7713b1edbc 10104 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
AnnaBridge 171:3a7713b1edbc 10105 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10106 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10107 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10108
AnnaBridge 171:3a7713b1edbc 10109 #define RCC_CFGR_MCO2_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10110 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 10111 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
AnnaBridge 171:3a7713b1edbc 10112 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10113 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10114
AnnaBridge 171:3a7713b1edbc 10115 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 171:3a7713b1edbc 10116 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10117 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10118 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
AnnaBridge 171:3a7713b1edbc 10119 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10120 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10121 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
AnnaBridge 171:3a7713b1edbc 10122 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10123 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10124 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
AnnaBridge 171:3a7713b1edbc 10125 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10126 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10127 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
AnnaBridge 171:3a7713b1edbc 10128 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10129 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10130 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
AnnaBridge 171:3a7713b1edbc 10131 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10132 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10133 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
AnnaBridge 171:3a7713b1edbc 10134 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10135 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10136 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
AnnaBridge 171:3a7713b1edbc 10137 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10138 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10139 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
AnnaBridge 171:3a7713b1edbc 10140 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10141 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10142 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 10143 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10144 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10145 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
AnnaBridge 171:3a7713b1edbc 10146 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10147 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10148 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 10149 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10150 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10151 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
AnnaBridge 171:3a7713b1edbc 10152 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10153 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10154 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 10155 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10156 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10157 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 10158 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10159 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10160 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
AnnaBridge 171:3a7713b1edbc 10161 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10162 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10163 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
AnnaBridge 171:3a7713b1edbc 10164 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10165 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10166 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
AnnaBridge 171:3a7713b1edbc 10167 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10168 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10169 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
AnnaBridge 171:3a7713b1edbc 10170 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10171 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10172 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
AnnaBridge 171:3a7713b1edbc 10173 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10174 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10175 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
AnnaBridge 171:3a7713b1edbc 10176 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10177 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10178 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
AnnaBridge 171:3a7713b1edbc 10179 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10180 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10181 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
AnnaBridge 171:3a7713b1edbc 10182 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10183 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10184 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
AnnaBridge 171:3a7713b1edbc 10185
AnnaBridge 171:3a7713b1edbc 10186 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 171:3a7713b1edbc 10187 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10188 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10189 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
AnnaBridge 171:3a7713b1edbc 10190 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10191 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10192 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
AnnaBridge 171:3a7713b1edbc 10193 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10194 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10195 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
AnnaBridge 171:3a7713b1edbc 10196 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10197 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10198 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
AnnaBridge 171:3a7713b1edbc 10199 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10200 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10201 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
AnnaBridge 171:3a7713b1edbc 10202 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10203 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10204 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
AnnaBridge 171:3a7713b1edbc 10205 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10206 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10207 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
AnnaBridge 171:3a7713b1edbc 10208 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10209 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10210 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
AnnaBridge 171:3a7713b1edbc 10211 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10212 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10213 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
AnnaBridge 171:3a7713b1edbc 10214 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10215 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10216 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
AnnaBridge 171:3a7713b1edbc 10217 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10218 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10219 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
AnnaBridge 171:3a7713b1edbc 10220 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10221 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10222 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 171:3a7713b1edbc 10223 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10224 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10225 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 171:3a7713b1edbc 10226 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10227 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10228 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 171:3a7713b1edbc 10229 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10230 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10231 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
AnnaBridge 171:3a7713b1edbc 10232 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10233 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10234 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
AnnaBridge 171:3a7713b1edbc 10235 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10236 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10237 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
AnnaBridge 171:3a7713b1edbc 10238
AnnaBridge 171:3a7713b1edbc 10239 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 171:3a7713b1edbc 10240 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10241 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10242 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
AnnaBridge 171:3a7713b1edbc 10243 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10244 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10245 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
AnnaBridge 171:3a7713b1edbc 10246 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10247 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10248 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
AnnaBridge 171:3a7713b1edbc 10249
AnnaBridge 171:3a7713b1edbc 10250 /******************** Bit definition for RCC_AHB3RSTR register **************/
AnnaBridge 171:3a7713b1edbc 10251
AnnaBridge 171:3a7713b1edbc 10252 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10253 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10254 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
AnnaBridge 171:3a7713b1edbc 10255 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10256 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10257 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
AnnaBridge 171:3a7713b1edbc 10258
AnnaBridge 171:3a7713b1edbc 10259 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 171:3a7713b1edbc 10260 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10261 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10262 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
AnnaBridge 171:3a7713b1edbc 10263 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10264 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10265 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
AnnaBridge 171:3a7713b1edbc 10266 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10267 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10268 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
AnnaBridge 171:3a7713b1edbc 10269 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10270 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10271 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
AnnaBridge 171:3a7713b1edbc 10272 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10273 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10274 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
AnnaBridge 171:3a7713b1edbc 10275 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10276 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10277 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
AnnaBridge 171:3a7713b1edbc 10278 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10279 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10280 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
AnnaBridge 171:3a7713b1edbc 10281 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10282 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10283 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
AnnaBridge 171:3a7713b1edbc 10284 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10285 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10286 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
AnnaBridge 171:3a7713b1edbc 10287 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10288 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10289 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
AnnaBridge 171:3a7713b1edbc 10290 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10291 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10292 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
AnnaBridge 171:3a7713b1edbc 10293 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10294 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10295 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
AnnaBridge 171:3a7713b1edbc 10296 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10297 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10298 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
AnnaBridge 171:3a7713b1edbc 10299 #define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10300 #define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1U << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10301 #define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
AnnaBridge 171:3a7713b1edbc 10302 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10303 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10304 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
AnnaBridge 171:3a7713b1edbc 10305 #define RCC_APB1RSTR_USART3RST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10306 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10307 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
AnnaBridge 171:3a7713b1edbc 10308 #define RCC_APB1RSTR_UART4RST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10309 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10310 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
AnnaBridge 171:3a7713b1edbc 10311 #define RCC_APB1RSTR_UART5RST_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10312 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10313 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
AnnaBridge 171:3a7713b1edbc 10314 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10315 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10316 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
AnnaBridge 171:3a7713b1edbc 10317 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10318 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10319 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
AnnaBridge 171:3a7713b1edbc 10320 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10321 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10322 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
AnnaBridge 171:3a7713b1edbc 10323 #define RCC_APB1RSTR_I2C4RST_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10324 #define RCC_APB1RSTR_I2C4RST_Msk (0x1U << RCC_APB1RSTR_I2C4RST_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10325 #define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk
AnnaBridge 171:3a7713b1edbc 10326 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10327 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10328 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
AnnaBridge 171:3a7713b1edbc 10329 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10330 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10331 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
AnnaBridge 171:3a7713b1edbc 10332 #define RCC_APB1RSTR_CECRST_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10333 #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10334 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
AnnaBridge 171:3a7713b1edbc 10335 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10336 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10337 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
AnnaBridge 171:3a7713b1edbc 10338 #define RCC_APB1RSTR_DACRST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10339 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10340 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
AnnaBridge 171:3a7713b1edbc 10341 #define RCC_APB1RSTR_UART7RST_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10342 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10343 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
AnnaBridge 171:3a7713b1edbc 10344 #define RCC_APB1RSTR_UART8RST_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10345 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10346 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
AnnaBridge 171:3a7713b1edbc 10347
AnnaBridge 171:3a7713b1edbc 10348 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 171:3a7713b1edbc 10349 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10350 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10351 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 171:3a7713b1edbc 10352 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10353 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10354 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
AnnaBridge 171:3a7713b1edbc 10355 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10356 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10357 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 171:3a7713b1edbc 10358 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10359 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10360 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 171:3a7713b1edbc 10361 #define RCC_APB2RSTR_ADCRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10362 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10363 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
AnnaBridge 171:3a7713b1edbc 10364 #define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10365 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10366 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
AnnaBridge 171:3a7713b1edbc 10367 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10368 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10369 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 171:3a7713b1edbc 10370 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10371 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10372 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
AnnaBridge 171:3a7713b1edbc 10373 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10374 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10375 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 171:3a7713b1edbc 10376 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10377 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10378 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
AnnaBridge 171:3a7713b1edbc 10379 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10380 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10381 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
AnnaBridge 171:3a7713b1edbc 10382 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10383 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10384 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
AnnaBridge 171:3a7713b1edbc 10385 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10386 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10387 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
AnnaBridge 171:3a7713b1edbc 10388 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10389 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10390 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
AnnaBridge 171:3a7713b1edbc 10391 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10392 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10393 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
AnnaBridge 171:3a7713b1edbc 10394 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10395 #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10396 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
AnnaBridge 171:3a7713b1edbc 10397 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10398 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10399 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
AnnaBridge 171:3a7713b1edbc 10400
AnnaBridge 171:3a7713b1edbc 10401 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 171:3a7713b1edbc 10402 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10403 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10404 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
AnnaBridge 171:3a7713b1edbc 10405 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10406 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10407 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
AnnaBridge 171:3a7713b1edbc 10408 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10409 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10410 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
AnnaBridge 171:3a7713b1edbc 10411 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10412 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10413 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
AnnaBridge 171:3a7713b1edbc 10414 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10415 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10416 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
AnnaBridge 171:3a7713b1edbc 10417 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10418 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10419 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
AnnaBridge 171:3a7713b1edbc 10420 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10421 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10422 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
AnnaBridge 171:3a7713b1edbc 10423 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10424 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10425 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
AnnaBridge 171:3a7713b1edbc 10426 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10427 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10428 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
AnnaBridge 171:3a7713b1edbc 10429 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10430 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10431 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
AnnaBridge 171:3a7713b1edbc 10432 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10433 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10434 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
AnnaBridge 171:3a7713b1edbc 10435 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10436 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10437 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 171:3a7713b1edbc 10438 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10439 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10440 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
AnnaBridge 171:3a7713b1edbc 10441 #define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10442 #define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1U << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10443 #define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
AnnaBridge 171:3a7713b1edbc 10444 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10445 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10446 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 171:3a7713b1edbc 10447 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10448 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10449 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 171:3a7713b1edbc 10450 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10451 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10452 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
AnnaBridge 171:3a7713b1edbc 10453 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10454 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10455 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
AnnaBridge 171:3a7713b1edbc 10456 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10457 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10458 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
AnnaBridge 171:3a7713b1edbc 10459 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10460 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10461 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
AnnaBridge 171:3a7713b1edbc 10462 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10463 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10464 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
AnnaBridge 171:3a7713b1edbc 10465 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10466 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10467 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
AnnaBridge 171:3a7713b1edbc 10468 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10469 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10470 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
AnnaBridge 171:3a7713b1edbc 10471
AnnaBridge 171:3a7713b1edbc 10472 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 171:3a7713b1edbc 10473 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10474 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10475 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
AnnaBridge 171:3a7713b1edbc 10476 #define RCC_AHB2ENR_RNGEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10477 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10478 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
AnnaBridge 171:3a7713b1edbc 10479 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10480 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10481 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
AnnaBridge 171:3a7713b1edbc 10482
AnnaBridge 171:3a7713b1edbc 10483 /******************** Bit definition for RCC_AHB3ENR register ***************/
AnnaBridge 171:3a7713b1edbc 10484 #define RCC_AHB3ENR_FMCEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10485 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10486 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
AnnaBridge 171:3a7713b1edbc 10487 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10488 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10489 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
AnnaBridge 171:3a7713b1edbc 10490
AnnaBridge 171:3a7713b1edbc 10491 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 171:3a7713b1edbc 10492 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10493 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10494 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
AnnaBridge 171:3a7713b1edbc 10495 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10496 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10497 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
AnnaBridge 171:3a7713b1edbc 10498 #define RCC_APB1ENR_TIM4EN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10499 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10500 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
AnnaBridge 171:3a7713b1edbc 10501 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10502 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10503 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
AnnaBridge 171:3a7713b1edbc 10504 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10505 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10506 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
AnnaBridge 171:3a7713b1edbc 10507 #define RCC_APB1ENR_TIM7EN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10508 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10509 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
AnnaBridge 171:3a7713b1edbc 10510 #define RCC_APB1ENR_TIM12EN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10511 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10512 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
AnnaBridge 171:3a7713b1edbc 10513 #define RCC_APB1ENR_TIM13EN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10514 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10515 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
AnnaBridge 171:3a7713b1edbc 10516 #define RCC_APB1ENR_TIM14EN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10517 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10518 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
AnnaBridge 171:3a7713b1edbc 10519 #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10520 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10521 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
AnnaBridge 171:3a7713b1edbc 10522 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10523 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10524 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
AnnaBridge 171:3a7713b1edbc 10525 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10526 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10527 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
AnnaBridge 171:3a7713b1edbc 10528 #define RCC_APB1ENR_SPI3EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10529 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10530 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
AnnaBridge 171:3a7713b1edbc 10531 #define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10532 #define RCC_APB1ENR_SPDIFRXEN_Msk (0x1U << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10533 #define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
AnnaBridge 171:3a7713b1edbc 10534 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10535 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10536 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
AnnaBridge 171:3a7713b1edbc 10537 #define RCC_APB1ENR_USART3EN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10538 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10539 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
AnnaBridge 171:3a7713b1edbc 10540 #define RCC_APB1ENR_UART4EN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10541 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10542 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
AnnaBridge 171:3a7713b1edbc 10543 #define RCC_APB1ENR_UART5EN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10544 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10545 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
AnnaBridge 171:3a7713b1edbc 10546 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10547 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10548 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
AnnaBridge 171:3a7713b1edbc 10549 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10550 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10551 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
AnnaBridge 171:3a7713b1edbc 10552 #define RCC_APB1ENR_I2C3EN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10553 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10554 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
AnnaBridge 171:3a7713b1edbc 10555 #define RCC_APB1ENR_I2C4EN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10556 #define RCC_APB1ENR_I2C4EN_Msk (0x1U << RCC_APB1ENR_I2C4EN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10557 #define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk
AnnaBridge 171:3a7713b1edbc 10558 #define RCC_APB1ENR_CAN1EN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10559 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10560 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
AnnaBridge 171:3a7713b1edbc 10561 #define RCC_APB1ENR_CAN2EN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10562 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10563 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
AnnaBridge 171:3a7713b1edbc 10564 #define RCC_APB1ENR_CECEN_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10565 #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10566 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
AnnaBridge 171:3a7713b1edbc 10567 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10568 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10569 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
AnnaBridge 171:3a7713b1edbc 10570 #define RCC_APB1ENR_DACEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10571 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10572 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
AnnaBridge 171:3a7713b1edbc 10573 #define RCC_APB1ENR_UART7EN_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10574 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10575 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
AnnaBridge 171:3a7713b1edbc 10576 #define RCC_APB1ENR_UART8EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10577 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10578 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
AnnaBridge 171:3a7713b1edbc 10579
AnnaBridge 171:3a7713b1edbc 10580 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 171:3a7713b1edbc 10581 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10582 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10583 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 171:3a7713b1edbc 10584 #define RCC_APB2ENR_TIM8EN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10585 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10586 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
AnnaBridge 171:3a7713b1edbc 10587 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10588 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10589 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 171:3a7713b1edbc 10590 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10591 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10592 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 171:3a7713b1edbc 10593 #define RCC_APB2ENR_ADC1EN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10594 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10595 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
AnnaBridge 171:3a7713b1edbc 10596 #define RCC_APB2ENR_ADC2EN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10597 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10598 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
AnnaBridge 171:3a7713b1edbc 10599 #define RCC_APB2ENR_ADC3EN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10600 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10601 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
AnnaBridge 171:3a7713b1edbc 10602 #define RCC_APB2ENR_SDMMC1EN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10603 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10604 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
AnnaBridge 171:3a7713b1edbc 10605 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10606 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10607 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 171:3a7713b1edbc 10608 #define RCC_APB2ENR_SPI4EN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10609 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10610 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
AnnaBridge 171:3a7713b1edbc 10611 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10612 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10613 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 171:3a7713b1edbc 10614 #define RCC_APB2ENR_TIM9EN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10615 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10616 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
AnnaBridge 171:3a7713b1edbc 10617 #define RCC_APB2ENR_TIM10EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10618 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10619 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
AnnaBridge 171:3a7713b1edbc 10620 #define RCC_APB2ENR_TIM11EN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10621 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10622 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
AnnaBridge 171:3a7713b1edbc 10623 #define RCC_APB2ENR_SPI5EN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10624 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10625 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
AnnaBridge 171:3a7713b1edbc 10626 #define RCC_APB2ENR_SPI6EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10627 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10628 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
AnnaBridge 171:3a7713b1edbc 10629 #define RCC_APB2ENR_SAI1EN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10630 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10631 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
AnnaBridge 171:3a7713b1edbc 10632 #define RCC_APB2ENR_SAI2EN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10633 #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10634 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
AnnaBridge 171:3a7713b1edbc 10635 #define RCC_APB2ENR_LTDCEN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10636 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10637 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
AnnaBridge 171:3a7713b1edbc 10638
AnnaBridge 171:3a7713b1edbc 10639 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 171:3a7713b1edbc 10640 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10641 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10642 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
AnnaBridge 171:3a7713b1edbc 10643 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10644 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10645 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10646 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10647 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10648 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10649 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10650 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10651 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10652 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10653 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10654 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
AnnaBridge 171:3a7713b1edbc 10655 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10656 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10657 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10658 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10659 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10660 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10661 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10662 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10663 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10664 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10665 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10666 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
AnnaBridge 171:3a7713b1edbc 10667 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10668 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10669 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10670 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10671 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10672 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10673 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10674 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10675 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10676 #define RCC_AHB1LPENR_AXILPEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10677 #define RCC_AHB1LPENR_AXILPEN_Msk (0x1U << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10678 #define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
AnnaBridge 171:3a7713b1edbc 10679 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10680 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10681 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10682 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10683 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10684 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10685 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10686 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10687 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10688 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10689 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10690 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10691 #define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10692 #define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1U << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10693 #define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10694 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10695 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10696 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10697 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10698 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10699 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10700 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10701 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10702 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10703 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10704 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10705 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10706 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10707 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10708 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10709 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10710 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10711 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10712 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10713 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10714 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10715 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10716 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10717 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10718 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10719 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10720 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
AnnaBridge 171:3a7713b1edbc 10721
AnnaBridge 171:3a7713b1edbc 10722 /******************** Bit definition for RCC_AHB2LPENR register *************/
AnnaBridge 171:3a7713b1edbc 10723 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10724 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10725 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
AnnaBridge 171:3a7713b1edbc 10726 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10727 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10728 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10729 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10730 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10731 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10732
AnnaBridge 171:3a7713b1edbc 10733 /******************** Bit definition for RCC_AHB3LPENR register *************/
AnnaBridge 171:3a7713b1edbc 10734 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10735 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10736 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10737 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10738 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10739 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
AnnaBridge 171:3a7713b1edbc 10740 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 171:3a7713b1edbc 10741 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10742 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10743 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10744 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10745 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10746 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10747 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10748 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10749 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10750 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10751 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10752 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10753 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10754 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10755 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10756 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10757 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10758 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10759 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10760 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10761 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10762 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10763 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10764 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10765 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10766 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10767 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10768 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10769 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10770 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10771 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10772 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10773 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10774 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10775 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10776 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10777 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10778 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10779 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10780 #define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10781 #define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1U << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10782 #define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10783 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10784 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10785 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10786 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10787 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10788 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10789 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10790 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10791 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10792 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10793 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10794 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10795 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10796 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10797 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10798 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10799 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10800 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10801 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10802 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10803 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10804 #define RCC_APB1LPENR_I2C4LPEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10805 #define RCC_APB1LPENR_I2C4LPEN_Msk (0x1U << RCC_APB1LPENR_I2C4LPEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10806 #define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10807 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10808 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10809 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10810 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10811 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10812 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10813 #define RCC_APB1LPENR_CECLPEN_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10814 #define RCC_APB1LPENR_CECLPEN_Msk (0x1U << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10815 #define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10816 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10817 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10818 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10819 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10820 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10821 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10822 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10823 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10824 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10825 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10826 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10827 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10828
AnnaBridge 171:3a7713b1edbc 10829 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 171:3a7713b1edbc 10830 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10831 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10832 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10833 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10834 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10835 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10836 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10837 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10838 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10839 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10840 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10841 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10842 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10843 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10844 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10845 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10846 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10847 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10848 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10849 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10850 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10851 #define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10852 #define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1U << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10853 #define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10854 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10855 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10856 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10857 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10858 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10859 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10860 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10861 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10862 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10863 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10864 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10865 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10866 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10867 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10868 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10869 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10870 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10871 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10872 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10873 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10874 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10875 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10876 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10877 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10878 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10879 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10880 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10881 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10882 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10883 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
AnnaBridge 171:3a7713b1edbc 10884 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10885 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10886 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
AnnaBridge 171:3a7713b1edbc 10887
AnnaBridge 171:3a7713b1edbc 10888 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 171:3a7713b1edbc 10889 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10890 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10891 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 171:3a7713b1edbc 10892 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10893 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10894 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 171:3a7713b1edbc 10895 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10896 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10897 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 171:3a7713b1edbc 10898 #define RCC_BDCR_LSEDRV_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10899 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 10900 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
AnnaBridge 171:3a7713b1edbc 10901 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10902 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10903 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10904 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 10905 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 171:3a7713b1edbc 10906 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10907 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10908 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10909 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10910 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 171:3a7713b1edbc 10911 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10912 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10913 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
AnnaBridge 171:3a7713b1edbc 10914
AnnaBridge 171:3a7713b1edbc 10915 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 171:3a7713b1edbc 10916 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10917 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10918 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 171:3a7713b1edbc 10919 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10920 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10921 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 171:3a7713b1edbc 10922 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10923 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10924 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 171:3a7713b1edbc 10925 #define RCC_CSR_BORRSTF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10926 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10927 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
AnnaBridge 171:3a7713b1edbc 10928 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10929 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10930 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 171:3a7713b1edbc 10931 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10932 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10933 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
AnnaBridge 171:3a7713b1edbc 10934 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10935 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10936 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 171:3a7713b1edbc 10937 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10938 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10939 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 171:3a7713b1edbc 10940 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10941 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10942 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 171:3a7713b1edbc 10943 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10944 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10945 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 171:3a7713b1edbc 10946
AnnaBridge 171:3a7713b1edbc 10947 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 171:3a7713b1edbc 10948 #define RCC_SSCGR_MODPER_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10949 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
AnnaBridge 171:3a7713b1edbc 10950 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
AnnaBridge 171:3a7713b1edbc 10951 #define RCC_SSCGR_INCSTEP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10952 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
AnnaBridge 171:3a7713b1edbc 10953 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
AnnaBridge 171:3a7713b1edbc 10954 #define RCC_SSCGR_SPREADSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10955 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10956 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
AnnaBridge 171:3a7713b1edbc 10957 #define RCC_SSCGR_SSCGEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10958 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10959 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
AnnaBridge 171:3a7713b1edbc 10960
AnnaBridge 171:3a7713b1edbc 10961 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
AnnaBridge 171:3a7713b1edbc 10962 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10963 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
AnnaBridge 171:3a7713b1edbc 10964 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
AnnaBridge 171:3a7713b1edbc 10965 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10966 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10967 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10968 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10969 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10970 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10971 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10972 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10973 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10974 #define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10975 #define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 10976 #define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
AnnaBridge 171:3a7713b1edbc 10977 #define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10978 #define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10979 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10980 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 10981 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
AnnaBridge 171:3a7713b1edbc 10982 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10983 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10984 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10985 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10986 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10987 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
AnnaBridge 171:3a7713b1edbc 10988 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
AnnaBridge 171:3a7713b1edbc 10989 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10990 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10991 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10992
AnnaBridge 171:3a7713b1edbc 10993 /******************** Bit definition for RCC_PLLSAICFGR register ************/
AnnaBridge 171:3a7713b1edbc 10994 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10995 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
AnnaBridge 171:3a7713b1edbc 10996 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
AnnaBridge 171:3a7713b1edbc 10997 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10998 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10999 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11000 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11001 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11002 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11003 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11004 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11005 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11006 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11007 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 11008 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
AnnaBridge 171:3a7713b1edbc 11009 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11010 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11011 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11012 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 11013 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
AnnaBridge 171:3a7713b1edbc 11014 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11015 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11016 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11017 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 11018 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11019 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
AnnaBridge 171:3a7713b1edbc 11020 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
AnnaBridge 171:3a7713b1edbc 11021 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11022 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11023 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 11024
AnnaBridge 171:3a7713b1edbc 11025 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
AnnaBridge 171:3a7713b1edbc 11026 #define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11027 #define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 11028 #define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
AnnaBridge 171:3a7713b1edbc 11029 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11030 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11031 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11032 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11033 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11034
AnnaBridge 171:3a7713b1edbc 11035 #define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11036 #define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 11037 #define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
AnnaBridge 171:3a7713b1edbc 11038 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11039 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11040 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11041 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11042 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11043
AnnaBridge 171:3a7713b1edbc 11044 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11045 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 11046 #define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk
AnnaBridge 171:3a7713b1edbc 11047 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11048 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11049
AnnaBridge 171:3a7713b1edbc 11050 #define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11051 #define RCC_DCKCFGR1_SAI1SEL_Msk (0x3U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 11052 #define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
AnnaBridge 171:3a7713b1edbc 11053 #define RCC_DCKCFGR1_SAI1SEL_0 (0x1U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11054 #define RCC_DCKCFGR1_SAI1SEL_1 (0x2U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11055
AnnaBridge 171:3a7713b1edbc 11056 #define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11057 #define RCC_DCKCFGR1_SAI2SEL_Msk (0x3U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 11058 #define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
AnnaBridge 171:3a7713b1edbc 11059 #define RCC_DCKCFGR1_SAI2SEL_0 (0x1U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11060 #define RCC_DCKCFGR1_SAI2SEL_1 (0x2U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11061
AnnaBridge 171:3a7713b1edbc 11062 #define RCC_DCKCFGR1_TIMPRE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11063 #define RCC_DCKCFGR1_TIMPRE_Msk (0x1U << RCC_DCKCFGR1_TIMPRE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11064 #define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
AnnaBridge 171:3a7713b1edbc 11065
AnnaBridge 171:3a7713b1edbc 11066 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
AnnaBridge 171:3a7713b1edbc 11067 #define RCC_DCKCFGR2_USART1SEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11068 #define RCC_DCKCFGR2_USART1SEL_Msk (0x3U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 11069 #define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
AnnaBridge 171:3a7713b1edbc 11070 #define RCC_DCKCFGR2_USART1SEL_0 (0x1U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11071 #define RCC_DCKCFGR2_USART1SEL_1 (0x2U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11072 #define RCC_DCKCFGR2_USART2SEL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11073 #define RCC_DCKCFGR2_USART2SEL_Msk (0x3U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 11074 #define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
AnnaBridge 171:3a7713b1edbc 11075 #define RCC_DCKCFGR2_USART2SEL_0 (0x1U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11076 #define RCC_DCKCFGR2_USART2SEL_1 (0x2U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11077 #define RCC_DCKCFGR2_USART3SEL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11078 #define RCC_DCKCFGR2_USART3SEL_Msk (0x3U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 11079 #define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
AnnaBridge 171:3a7713b1edbc 11080 #define RCC_DCKCFGR2_USART3SEL_0 (0x1U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11081 #define RCC_DCKCFGR2_USART3SEL_1 (0x2U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11082 #define RCC_DCKCFGR2_UART4SEL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11083 #define RCC_DCKCFGR2_UART4SEL_Msk (0x3U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 11084 #define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
AnnaBridge 171:3a7713b1edbc 11085 #define RCC_DCKCFGR2_UART4SEL_0 (0x1U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11086 #define RCC_DCKCFGR2_UART4SEL_1 (0x2U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11087 #define RCC_DCKCFGR2_UART5SEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11088 #define RCC_DCKCFGR2_UART5SEL_Msk (0x3U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 11089 #define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
AnnaBridge 171:3a7713b1edbc 11090 #define RCC_DCKCFGR2_UART5SEL_0 (0x1U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11091 #define RCC_DCKCFGR2_UART5SEL_1 (0x2U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11092 #define RCC_DCKCFGR2_USART6SEL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11093 #define RCC_DCKCFGR2_USART6SEL_Msk (0x3U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 11094 #define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
AnnaBridge 171:3a7713b1edbc 11095 #define RCC_DCKCFGR2_USART6SEL_0 (0x1U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11096 #define RCC_DCKCFGR2_USART6SEL_1 (0x2U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11097 #define RCC_DCKCFGR2_UART7SEL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11098 #define RCC_DCKCFGR2_UART7SEL_Msk (0x3U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 11099 #define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
AnnaBridge 171:3a7713b1edbc 11100 #define RCC_DCKCFGR2_UART7SEL_0 (0x1U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11101 #define RCC_DCKCFGR2_UART7SEL_1 (0x2U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11102 #define RCC_DCKCFGR2_UART8SEL_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11103 #define RCC_DCKCFGR2_UART8SEL_Msk (0x3U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 11104 #define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
AnnaBridge 171:3a7713b1edbc 11105 #define RCC_DCKCFGR2_UART8SEL_0 (0x1U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11106 #define RCC_DCKCFGR2_UART8SEL_1 (0x2U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11107 #define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11108 #define RCC_DCKCFGR2_I2C1SEL_Msk (0x3U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 11109 #define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
AnnaBridge 171:3a7713b1edbc 11110 #define RCC_DCKCFGR2_I2C1SEL_0 (0x1U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11111 #define RCC_DCKCFGR2_I2C1SEL_1 (0x2U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11112 #define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11113 #define RCC_DCKCFGR2_I2C2SEL_Msk (0x3U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 11114 #define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
AnnaBridge 171:3a7713b1edbc 11115 #define RCC_DCKCFGR2_I2C2SEL_0 (0x1U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11116 #define RCC_DCKCFGR2_I2C2SEL_1 (0x2U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11117 #define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11118 #define RCC_DCKCFGR2_I2C3SEL_Msk (0x3U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 11119 #define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
AnnaBridge 171:3a7713b1edbc 11120 #define RCC_DCKCFGR2_I2C3SEL_0 (0x1U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11121 #define RCC_DCKCFGR2_I2C3SEL_1 (0x2U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11122 #define RCC_DCKCFGR2_I2C4SEL_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11123 #define RCC_DCKCFGR2_I2C4SEL_Msk (0x3U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 11124 #define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk
AnnaBridge 171:3a7713b1edbc 11125 #define RCC_DCKCFGR2_I2C4SEL_0 (0x1U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11126 #define RCC_DCKCFGR2_I2C4SEL_1 (0x2U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11127 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11128 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 11129 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
AnnaBridge 171:3a7713b1edbc 11130 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11131 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11132 #define RCC_DCKCFGR2_CECSEL_Pos (26U)
AnnaBridge 171:3a7713b1edbc 11133 #define RCC_DCKCFGR2_CECSEL_Msk (0x1U << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11134 #define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
AnnaBridge 171:3a7713b1edbc 11135 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
AnnaBridge 171:3a7713b1edbc 11136 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 11137 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
AnnaBridge 171:3a7713b1edbc 11138 #define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11139 #define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1U << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11140 #define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
AnnaBridge 171:3a7713b1edbc 11141
AnnaBridge 171:3a7713b1edbc 11142 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11143 /* */
AnnaBridge 171:3a7713b1edbc 11144 /* RNG */
AnnaBridge 171:3a7713b1edbc 11145 /* */
AnnaBridge 171:3a7713b1edbc 11146 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11147 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 171:3a7713b1edbc 11148 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11149 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11150 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 171:3a7713b1edbc 11151 #define RNG_CR_IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11152 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11153 #define RNG_CR_IE RNG_CR_IE_Msk
AnnaBridge 171:3a7713b1edbc 11154
AnnaBridge 171:3a7713b1edbc 11155 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 171:3a7713b1edbc 11156 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11157 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11158 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 171:3a7713b1edbc 11159 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11160 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11161 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 171:3a7713b1edbc 11162 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11163 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11164 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 171:3a7713b1edbc 11165 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11166 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11167 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 171:3a7713b1edbc 11168 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11169 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11170 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
AnnaBridge 171:3a7713b1edbc 11171
AnnaBridge 171:3a7713b1edbc 11172 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11173 /* */
AnnaBridge 171:3a7713b1edbc 11174 /* Real-Time Clock (RTC) */
AnnaBridge 171:3a7713b1edbc 11175 /* */
AnnaBridge 171:3a7713b1edbc 11176 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11177 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 171:3a7713b1edbc 11178 #define RTC_TR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11179 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11180 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 171:3a7713b1edbc 11181 #define RTC_TR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11182 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 11183 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 171:3a7713b1edbc 11184 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11185 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11186 #define RTC_TR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11187 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 11188 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 171:3a7713b1edbc 11189 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11190 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11191 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11192 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11193 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11194 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11195 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 11196 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11197 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11198 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11199 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11200 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11201 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 11202 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11203 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11204 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11205 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11206 #define RTC_TR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11207 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11208 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 171:3a7713b1edbc 11209 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11210 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11211 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11212 #define RTC_TR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11213 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11214 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 171:3a7713b1edbc 11215 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11216 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11217 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11218 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11219
AnnaBridge 171:3a7713b1edbc 11220 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 171:3a7713b1edbc 11221 #define RTC_DR_YT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11222 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 11223 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 171:3a7713b1edbc 11224 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11225 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11226 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11227 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11228 #define RTC_DR_YU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11229 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 11230 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 171:3a7713b1edbc 11231 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11232 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11233 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11234 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11235 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11236 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 11237 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 11238 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11239 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11240 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11241 #define RTC_DR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11242 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11243 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 171:3a7713b1edbc 11244 #define RTC_DR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11245 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11246 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 171:3a7713b1edbc 11247 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11248 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11249 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11250 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11251 #define RTC_DR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11252 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 11253 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 171:3a7713b1edbc 11254 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11255 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11256 #define RTC_DR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11257 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11258 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 171:3a7713b1edbc 11259 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11260 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11261 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11262 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11263
AnnaBridge 171:3a7713b1edbc 11264 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 171:3a7713b1edbc 11265 #define RTC_CR_ITSE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11266 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11267 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
AnnaBridge 171:3a7713b1edbc 11268 #define RTC_CR_COE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 11269 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11270 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 171:3a7713b1edbc 11271 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 11272 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 11273 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 171:3a7713b1edbc 11274 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11275 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11276 #define RTC_CR_POL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11277 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11278 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 171:3a7713b1edbc 11279 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 171:3a7713b1edbc 11280 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11281 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 171:3a7713b1edbc 11282 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11283 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11284 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 11285 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11286 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11287 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 171:3a7713b1edbc 11288 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11289 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11290 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 171:3a7713b1edbc 11291 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11292 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11293 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 171:3a7713b1edbc 11294 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11295 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11296 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 171:3a7713b1edbc 11297 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11298 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11299 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 171:3a7713b1edbc 11300 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11301 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11302 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 171:3a7713b1edbc 11303 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11304 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11305 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 171:3a7713b1edbc 11306 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11307 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11308 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 171:3a7713b1edbc 11309 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11310 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11311 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 171:3a7713b1edbc 11312 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11313 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11314 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 171:3a7713b1edbc 11315 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11316 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11317 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 171:3a7713b1edbc 11318 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11319 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11320 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 171:3a7713b1edbc 11321 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11322 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11323 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 171:3a7713b1edbc 11324 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11325 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11326 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 171:3a7713b1edbc 11327 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11328 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 11329 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 171:3a7713b1edbc 11330 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11331 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11332 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11333
AnnaBridge 171:3a7713b1edbc 11334 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 11335 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 171:3a7713b1edbc 11336
AnnaBridge 171:3a7713b1edbc 11337 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 11338 #define RTC_ISR_ITSF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11339 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11340 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
AnnaBridge 171:3a7713b1edbc 11341 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11342 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11343 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 171:3a7713b1edbc 11344 #define RTC_ISR_TAMP3F_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11345 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11346 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
AnnaBridge 171:3a7713b1edbc 11347 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11348 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11349 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 171:3a7713b1edbc 11350 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11351 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11352 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 171:3a7713b1edbc 11353 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11354 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11355 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 171:3a7713b1edbc 11356 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11357 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11358 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 171:3a7713b1edbc 11359 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11360 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11361 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 171:3a7713b1edbc 11362 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11363 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11364 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 171:3a7713b1edbc 11365 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11366 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11367 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 171:3a7713b1edbc 11368 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11369 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11370 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 171:3a7713b1edbc 11371 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11372 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11373 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 171:3a7713b1edbc 11374 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11375 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11376 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 171:3a7713b1edbc 11377 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11378 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11379 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 171:3a7713b1edbc 11380 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11381 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11382 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 171:3a7713b1edbc 11383 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11384 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11385 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 171:3a7713b1edbc 11386 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11387 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11388 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 171:3a7713b1edbc 11389 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11390 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11391 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 171:3a7713b1edbc 11392
AnnaBridge 171:3a7713b1edbc 11393 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 171:3a7713b1edbc 11394 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11395 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 171:3a7713b1edbc 11396 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 171:3a7713b1edbc 11397 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11398 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 11399 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 171:3a7713b1edbc 11400
AnnaBridge 171:3a7713b1edbc 11401 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 171:3a7713b1edbc 11402 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11403 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 11404 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 171:3a7713b1edbc 11405
AnnaBridge 171:3a7713b1edbc 11406 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 171:3a7713b1edbc 11407 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 11408 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 11409 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 11410 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 11411 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 11412 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 11413 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11414 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 11415 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 171:3a7713b1edbc 11416 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11417 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11418 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11419 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 11420 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 171:3a7713b1edbc 11421 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11422 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11423 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11424 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 11425 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 11426 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11427 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 11428 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11429 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11430 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 171:3a7713b1edbc 11431 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11432 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 11433 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 171:3a7713b1edbc 11434 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11435 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11436 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11437 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 11438 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 171:3a7713b1edbc 11439 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11440 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11441 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11442 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11443 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11444 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11445 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 11446 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11447 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11448 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 11449 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11450 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11451 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11452 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11453 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11454 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 11455 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11456 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11457 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11458 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11459 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11460 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11461 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 11462 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11463 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11464 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 171:3a7713b1edbc 11465 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11466 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11467 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11468 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11469 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11470 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 171:3a7713b1edbc 11471 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11472 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11473 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11474 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11475
AnnaBridge 171:3a7713b1edbc 11476 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 171:3a7713b1edbc 11477 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 11478 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 11479 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 11480 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 11481 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 11482 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 11483 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11484 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 11485 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 171:3a7713b1edbc 11486 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11487 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11488 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11489 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 11490 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 171:3a7713b1edbc 11491 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11492 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11493 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11494 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 11495 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 11496 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11497 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 11498 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11499 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11500 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 171:3a7713b1edbc 11501 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11502 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 11503 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 171:3a7713b1edbc 11504 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11505 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11506 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11507 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 11508 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 171:3a7713b1edbc 11509 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11510 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11511 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11512 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11513 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11514 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11515 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 11516 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11517 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11518 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 11519 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11520 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11521 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11522 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11523 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11524 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 11525 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11526 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11527 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11528 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11529 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11530 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11531 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 11532 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11533 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11534 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 171:3a7713b1edbc 11535 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11536 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11537 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11538 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11539 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11540 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 171:3a7713b1edbc 11541 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11542 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11543 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11544 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11545
AnnaBridge 171:3a7713b1edbc 11546 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 171:3a7713b1edbc 11547 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11548 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 11549 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 171:3a7713b1edbc 11550
AnnaBridge 171:3a7713b1edbc 11551 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 171:3a7713b1edbc 11552 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11553 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 11554 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 11555
AnnaBridge 171:3a7713b1edbc 11556 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 171:3a7713b1edbc 11557 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11558 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 11559 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 171:3a7713b1edbc 11560 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 171:3a7713b1edbc 11561 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 11562 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 171:3a7713b1edbc 11563
AnnaBridge 171:3a7713b1edbc 11564 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 171:3a7713b1edbc 11565 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11566 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11567 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 171:3a7713b1edbc 11568 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11569 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 11570 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 171:3a7713b1edbc 11571 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11572 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11573 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11574 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 11575 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 171:3a7713b1edbc 11576 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11577 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11578 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11579 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11580 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11581 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11582 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 11583 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11584 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11585 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11586 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11587 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11588 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 11589 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11590 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11591 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11592 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11593 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11594 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11595 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 171:3a7713b1edbc 11596 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11597 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11598 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11599 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11600 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11601 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 171:3a7713b1edbc 11602 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11603 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11604 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11605 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11606
AnnaBridge 171:3a7713b1edbc 11607 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 171:3a7713b1edbc 11608 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11609 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 11610 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 11611 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11612 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11613 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11614 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11615 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11616 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 171:3a7713b1edbc 11617 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11618 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11619 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 171:3a7713b1edbc 11620 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11621 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11622 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11623 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11624 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11625 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 11626 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 171:3a7713b1edbc 11627 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11628 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11629 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11630 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11631 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 171:3a7713b1edbc 11632 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11633 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11634 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11635 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11636
AnnaBridge 171:3a7713b1edbc 11637 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 171:3a7713b1edbc 11638 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11639 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 11640 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 11641
AnnaBridge 171:3a7713b1edbc 11642 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 171:3a7713b1edbc 11643 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11644 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11645 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 171:3a7713b1edbc 11646 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11647 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11648 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 171:3a7713b1edbc 11649 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11650 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11651 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 171:3a7713b1edbc 11652 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11653 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 11654 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 171:3a7713b1edbc 11655 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11656 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11657 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11658 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11659 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11660 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11661 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11662 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11663 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11664
AnnaBridge 171:3a7713b1edbc 11665 /******************** Bits definition for RTC_TAMPCR register ****************/
AnnaBridge 171:3a7713b1edbc 11666 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11667 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11668 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
AnnaBridge 171:3a7713b1edbc 11669 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 11670 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11671 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
AnnaBridge 171:3a7713b1edbc 11672 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11673 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11674 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
AnnaBridge 171:3a7713b1edbc 11675 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
AnnaBridge 171:3a7713b1edbc 11676 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11677 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
AnnaBridge 171:3a7713b1edbc 11678 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11679 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11680 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
AnnaBridge 171:3a7713b1edbc 11681 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 11682 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11683 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
AnnaBridge 171:3a7713b1edbc 11684 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11685 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11686 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
AnnaBridge 171:3a7713b1edbc 11687 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11688 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11689 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
AnnaBridge 171:3a7713b1edbc 11690 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11691 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11692 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
AnnaBridge 171:3a7713b1edbc 11693 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11694 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11695 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
AnnaBridge 171:3a7713b1edbc 11696 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11697 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 11698 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
AnnaBridge 171:3a7713b1edbc 11699 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11700 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11701 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11702 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 11703 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
AnnaBridge 171:3a7713b1edbc 11704 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11705 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11706 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11707 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 11708 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
AnnaBridge 171:3a7713b1edbc 11709 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11710 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11711 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11712 #define RTC_TAMPCR_TAMPTS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11713 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11714 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
AnnaBridge 171:3a7713b1edbc 11715 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11716 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11717 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
AnnaBridge 171:3a7713b1edbc 11718 #define RTC_TAMPCR_TAMP3E_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11719 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11720 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
AnnaBridge 171:3a7713b1edbc 11721 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11722 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11723 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
AnnaBridge 171:3a7713b1edbc 11724 #define RTC_TAMPCR_TAMP2E_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11725 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11726 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
AnnaBridge 171:3a7713b1edbc 11727 #define RTC_TAMPCR_TAMPIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11728 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11729 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
AnnaBridge 171:3a7713b1edbc 11730 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11731 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11732 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
AnnaBridge 171:3a7713b1edbc 11733 #define RTC_TAMPCR_TAMP1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11734 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11735 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
AnnaBridge 171:3a7713b1edbc 11736
AnnaBridge 171:3a7713b1edbc 11737 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 11738 #define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG
AnnaBridge 171:3a7713b1edbc 11739 #define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG
AnnaBridge 171:3a7713b1edbc 11740 #define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG
AnnaBridge 171:3a7713b1edbc 11741
AnnaBridge 171:3a7713b1edbc 11742 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 171:3a7713b1edbc 11743 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11744 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 11745 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 11746 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11747 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11748 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11749 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 11750 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11751 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 11752 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 11753
AnnaBridge 171:3a7713b1edbc 11754 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 171:3a7713b1edbc 11755 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11756 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 11757 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 11758 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11759 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11760 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11761 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 11762 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11763 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 11764 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 11765
AnnaBridge 171:3a7713b1edbc 11766 /******************** Bits definition for RTC_OR register ****************/
AnnaBridge 171:3a7713b1edbc 11767 #define RTC_OR_TSINSEL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11768 #define RTC_OR_TSINSEL_Msk (0x3U << RTC_OR_TSINSEL_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 11769 #define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
AnnaBridge 171:3a7713b1edbc 11770 #define RTC_OR_TSINSEL_0 (0x1U << RTC_OR_TSINSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11771 #define RTC_OR_TSINSEL_1 (0x2U << RTC_OR_TSINSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11772 #define RTC_OR_ALARMOUTTYPE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11773 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11774 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
AnnaBridge 171:3a7713b1edbc 11775 /* Legacy defines*/
AnnaBridge 171:3a7713b1edbc 11776 #define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
AnnaBridge 171:3a7713b1edbc 11777
AnnaBridge 171:3a7713b1edbc 11778 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 171:3a7713b1edbc 11779 #define RTC_BKP0R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11780 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11781 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 171:3a7713b1edbc 11782
AnnaBridge 171:3a7713b1edbc 11783 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 171:3a7713b1edbc 11784 #define RTC_BKP1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11785 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11786 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 171:3a7713b1edbc 11787
AnnaBridge 171:3a7713b1edbc 11788 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 171:3a7713b1edbc 11789 #define RTC_BKP2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11790 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11791 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 171:3a7713b1edbc 11792
AnnaBridge 171:3a7713b1edbc 11793 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 171:3a7713b1edbc 11794 #define RTC_BKP3R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11795 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11796 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 171:3a7713b1edbc 11797
AnnaBridge 171:3a7713b1edbc 11798 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 171:3a7713b1edbc 11799 #define RTC_BKP4R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11800 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11801 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 171:3a7713b1edbc 11802
AnnaBridge 171:3a7713b1edbc 11803 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 171:3a7713b1edbc 11804 #define RTC_BKP5R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11805 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11806 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 171:3a7713b1edbc 11807
AnnaBridge 171:3a7713b1edbc 11808 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 171:3a7713b1edbc 11809 #define RTC_BKP6R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11810 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11811 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 171:3a7713b1edbc 11812
AnnaBridge 171:3a7713b1edbc 11813 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 171:3a7713b1edbc 11814 #define RTC_BKP7R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11815 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11816 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 171:3a7713b1edbc 11817
AnnaBridge 171:3a7713b1edbc 11818 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 171:3a7713b1edbc 11819 #define RTC_BKP8R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11820 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11821 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 171:3a7713b1edbc 11822
AnnaBridge 171:3a7713b1edbc 11823 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 171:3a7713b1edbc 11824 #define RTC_BKP9R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11825 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11826 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 171:3a7713b1edbc 11827
AnnaBridge 171:3a7713b1edbc 11828 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 171:3a7713b1edbc 11829 #define RTC_BKP10R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11830 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11831 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 171:3a7713b1edbc 11832
AnnaBridge 171:3a7713b1edbc 11833 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 171:3a7713b1edbc 11834 #define RTC_BKP11R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11835 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11836 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 171:3a7713b1edbc 11837
AnnaBridge 171:3a7713b1edbc 11838 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 171:3a7713b1edbc 11839 #define RTC_BKP12R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11840 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11841 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 171:3a7713b1edbc 11842
AnnaBridge 171:3a7713b1edbc 11843 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 171:3a7713b1edbc 11844 #define RTC_BKP13R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11845 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11846 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 171:3a7713b1edbc 11847
AnnaBridge 171:3a7713b1edbc 11848 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 171:3a7713b1edbc 11849 #define RTC_BKP14R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11850 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11851 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 171:3a7713b1edbc 11852
AnnaBridge 171:3a7713b1edbc 11853 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 171:3a7713b1edbc 11854 #define RTC_BKP15R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11855 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11856 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 171:3a7713b1edbc 11857
AnnaBridge 171:3a7713b1edbc 11858 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 171:3a7713b1edbc 11859 #define RTC_BKP16R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11860 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11861 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 171:3a7713b1edbc 11862
AnnaBridge 171:3a7713b1edbc 11863 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 171:3a7713b1edbc 11864 #define RTC_BKP17R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11865 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11866 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 171:3a7713b1edbc 11867
AnnaBridge 171:3a7713b1edbc 11868 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 171:3a7713b1edbc 11869 #define RTC_BKP18R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11870 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11871 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 171:3a7713b1edbc 11872
AnnaBridge 171:3a7713b1edbc 11873 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 171:3a7713b1edbc 11874 #define RTC_BKP19R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11875 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11876 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 171:3a7713b1edbc 11877
AnnaBridge 171:3a7713b1edbc 11878 /******************** Bits definition for RTC_BKP20R register ***************/
AnnaBridge 171:3a7713b1edbc 11879 #define RTC_BKP20R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11880 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11881 #define RTC_BKP20R RTC_BKP20R_Msk
AnnaBridge 171:3a7713b1edbc 11882
AnnaBridge 171:3a7713b1edbc 11883 /******************** Bits definition for RTC_BKP21R register ***************/
AnnaBridge 171:3a7713b1edbc 11884 #define RTC_BKP21R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11885 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11886 #define RTC_BKP21R RTC_BKP21R_Msk
AnnaBridge 171:3a7713b1edbc 11887
AnnaBridge 171:3a7713b1edbc 11888 /******************** Bits definition for RTC_BKP22R register ***************/
AnnaBridge 171:3a7713b1edbc 11889 #define RTC_BKP22R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11890 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11891 #define RTC_BKP22R RTC_BKP22R_Msk
AnnaBridge 171:3a7713b1edbc 11892
AnnaBridge 171:3a7713b1edbc 11893 /******************** Bits definition for RTC_BKP23R register ***************/
AnnaBridge 171:3a7713b1edbc 11894 #define RTC_BKP23R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11895 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11896 #define RTC_BKP23R RTC_BKP23R_Msk
AnnaBridge 171:3a7713b1edbc 11897
AnnaBridge 171:3a7713b1edbc 11898 /******************** Bits definition for RTC_BKP24R register ***************/
AnnaBridge 171:3a7713b1edbc 11899 #define RTC_BKP24R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11900 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11901 #define RTC_BKP24R RTC_BKP24R_Msk
AnnaBridge 171:3a7713b1edbc 11902
AnnaBridge 171:3a7713b1edbc 11903 /******************** Bits definition for RTC_BKP25R register ***************/
AnnaBridge 171:3a7713b1edbc 11904 #define RTC_BKP25R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11905 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11906 #define RTC_BKP25R RTC_BKP25R_Msk
AnnaBridge 171:3a7713b1edbc 11907
AnnaBridge 171:3a7713b1edbc 11908 /******************** Bits definition for RTC_BKP26R register ***************/
AnnaBridge 171:3a7713b1edbc 11909 #define RTC_BKP26R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11910 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11911 #define RTC_BKP26R RTC_BKP26R_Msk
AnnaBridge 171:3a7713b1edbc 11912
AnnaBridge 171:3a7713b1edbc 11913 /******************** Bits definition for RTC_BKP27R register ***************/
AnnaBridge 171:3a7713b1edbc 11914 #define RTC_BKP27R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11915 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11916 #define RTC_BKP27R RTC_BKP27R_Msk
AnnaBridge 171:3a7713b1edbc 11917
AnnaBridge 171:3a7713b1edbc 11918 /******************** Bits definition for RTC_BKP28R register ***************/
AnnaBridge 171:3a7713b1edbc 11919 #define RTC_BKP28R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11920 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11921 #define RTC_BKP28R RTC_BKP28R_Msk
AnnaBridge 171:3a7713b1edbc 11922
AnnaBridge 171:3a7713b1edbc 11923 /******************** Bits definition for RTC_BKP29R register ***************/
AnnaBridge 171:3a7713b1edbc 11924 #define RTC_BKP29R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11925 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11926 #define RTC_BKP29R RTC_BKP29R_Msk
AnnaBridge 171:3a7713b1edbc 11927
AnnaBridge 171:3a7713b1edbc 11928 /******************** Bits definition for RTC_BKP30R register ***************/
AnnaBridge 171:3a7713b1edbc 11929 #define RTC_BKP30R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11930 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11931 #define RTC_BKP30R RTC_BKP30R_Msk
AnnaBridge 171:3a7713b1edbc 11932
AnnaBridge 171:3a7713b1edbc 11933 /******************** Bits definition for RTC_BKP31R register ***************/
AnnaBridge 171:3a7713b1edbc 11934 #define RTC_BKP31R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11935 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 11936 #define RTC_BKP31R RTC_BKP31R_Msk
AnnaBridge 171:3a7713b1edbc 11937
AnnaBridge 171:3a7713b1edbc 11938 /******************** Number of backup registers ******************************/
AnnaBridge 171:3a7713b1edbc 11939 #define RTC_BKP_NUMBER 0x00000020U
AnnaBridge 171:3a7713b1edbc 11940
AnnaBridge 171:3a7713b1edbc 11941 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11942 /* */
AnnaBridge 171:3a7713b1edbc 11943 /* Serial Audio Interface */
AnnaBridge 171:3a7713b1edbc 11944 /* */
AnnaBridge 171:3a7713b1edbc 11945 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11946 /******************** Bit definition for SAI_GCR register *******************/
AnnaBridge 171:3a7713b1edbc 11947 #define SAI_GCR_SYNCIN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11948 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 11949 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
AnnaBridge 171:3a7713b1edbc 11950 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11951 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11952
AnnaBridge 171:3a7713b1edbc 11953 #define SAI_GCR_SYNCOUT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11954 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 11955 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
AnnaBridge 171:3a7713b1edbc 11956 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11957 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11958
AnnaBridge 171:3a7713b1edbc 11959 /******************* Bit definition for SAI_xCR1 register *******************/
AnnaBridge 171:3a7713b1edbc 11960 #define SAI_xCR1_MODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11961 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 11962 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
AnnaBridge 171:3a7713b1edbc 11963 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11964 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11965
AnnaBridge 171:3a7713b1edbc 11966 #define SAI_xCR1_PRTCFG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11967 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 11968 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
AnnaBridge 171:3a7713b1edbc 11969 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11970 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11971
AnnaBridge 171:3a7713b1edbc 11972 #define SAI_xCR1_DS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11973 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 11974 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
AnnaBridge 171:3a7713b1edbc 11975 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11976 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11977 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11978
AnnaBridge 171:3a7713b1edbc 11979 #define SAI_xCR1_LSBFIRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11980 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11981 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
AnnaBridge 171:3a7713b1edbc 11982 #define SAI_xCR1_CKSTR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11983 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11984 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
AnnaBridge 171:3a7713b1edbc 11985
AnnaBridge 171:3a7713b1edbc 11986 #define SAI_xCR1_SYNCEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11987 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 11988 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
AnnaBridge 171:3a7713b1edbc 11989 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11990 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11991
AnnaBridge 171:3a7713b1edbc 11992 #define SAI_xCR1_MONO_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11993 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11994 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
AnnaBridge 171:3a7713b1edbc 11995 #define SAI_xCR1_OUTDRIV_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11996 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11997 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
AnnaBridge 171:3a7713b1edbc 11998 #define SAI_xCR1_SAIEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11999 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12000 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
AnnaBridge 171:3a7713b1edbc 12001 #define SAI_xCR1_DMAEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12002 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12003 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
AnnaBridge 171:3a7713b1edbc 12004 #define SAI_xCR1_NODIV_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12005 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12006 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
AnnaBridge 171:3a7713b1edbc 12007
AnnaBridge 171:3a7713b1edbc 12008 #define SAI_xCR1_MCKDIV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12009 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 12010 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
AnnaBridge 171:3a7713b1edbc 12011 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12012 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12013 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12014 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12015
AnnaBridge 171:3a7713b1edbc 12016 /******************* Bit definition for SAI_xCR2 register *******************/
AnnaBridge 171:3a7713b1edbc 12017 #define SAI_xCR2_FTH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12018 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 12019 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
AnnaBridge 171:3a7713b1edbc 12020 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12021 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12022 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12023
AnnaBridge 171:3a7713b1edbc 12024 #define SAI_xCR2_FFLUSH_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12025 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12026 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
AnnaBridge 171:3a7713b1edbc 12027 #define SAI_xCR2_TRIS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12028 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12029 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
AnnaBridge 171:3a7713b1edbc 12030 #define SAI_xCR2_MUTE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12031 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12032 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
AnnaBridge 171:3a7713b1edbc 12033 #define SAI_xCR2_MUTEVAL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12034 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12035 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
AnnaBridge 171:3a7713b1edbc 12036
AnnaBridge 171:3a7713b1edbc 12037 #define SAI_xCR2_MUTECNT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12038 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
AnnaBridge 171:3a7713b1edbc 12039 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
AnnaBridge 171:3a7713b1edbc 12040 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12041 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12042 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12043 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12044 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12045 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12046
AnnaBridge 171:3a7713b1edbc 12047 #define SAI_xCR2_CPL_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12048 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12049 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
AnnaBridge 171:3a7713b1edbc 12050
AnnaBridge 171:3a7713b1edbc 12051 #define SAI_xCR2_COMP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12052 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 12053 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
AnnaBridge 171:3a7713b1edbc 12054 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12055 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12056
AnnaBridge 171:3a7713b1edbc 12057 /****************** Bit definition for SAI_xFRCR register *******************/
AnnaBridge 171:3a7713b1edbc 12058 #define SAI_xFRCR_FRL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12059 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 12060 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
AnnaBridge 171:3a7713b1edbc 12061 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12062 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12063 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12064 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12065 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12066 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12067 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12068 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12069
AnnaBridge 171:3a7713b1edbc 12070 #define SAI_xFRCR_FSALL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12071 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
AnnaBridge 171:3a7713b1edbc 12072 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
AnnaBridge 171:3a7713b1edbc 12073 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12074 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12075 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12076 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12077 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12078 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12079 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12080
AnnaBridge 171:3a7713b1edbc 12081 #define SAI_xFRCR_FSDEF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12082 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12083 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
AnnaBridge 171:3a7713b1edbc 12084 #define SAI_xFRCR_FSPOL_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12085 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12086 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
AnnaBridge 171:3a7713b1edbc 12087 #define SAI_xFRCR_FSOFF_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12088 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12089 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
AnnaBridge 171:3a7713b1edbc 12090
AnnaBridge 171:3a7713b1edbc 12091 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 12092 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
AnnaBridge 171:3a7713b1edbc 12093
AnnaBridge 171:3a7713b1edbc 12094 /****************** Bit definition for SAI_xSLOTR register *******************/
AnnaBridge 171:3a7713b1edbc 12095 #define SAI_xSLOTR_FBOFF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12096 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 12097 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
AnnaBridge 171:3a7713b1edbc 12098 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12099 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12100 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12101 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12102 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12103
AnnaBridge 171:3a7713b1edbc 12104 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12105 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 12106 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
AnnaBridge 171:3a7713b1edbc 12107 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12108 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12109
AnnaBridge 171:3a7713b1edbc 12110 #define SAI_xSLOTR_NBSLOT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12111 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12112 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
AnnaBridge 171:3a7713b1edbc 12113 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12114 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12115 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12116 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12117
AnnaBridge 171:3a7713b1edbc 12118 #define SAI_xSLOTR_SLOTEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12119 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 12120 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
AnnaBridge 171:3a7713b1edbc 12121
AnnaBridge 171:3a7713b1edbc 12122 /******************* Bit definition for SAI_xIMR register *******************/
AnnaBridge 171:3a7713b1edbc 12123 #define SAI_xIMR_OVRUDRIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12124 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12125 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
AnnaBridge 171:3a7713b1edbc 12126 #define SAI_xIMR_MUTEDETIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12127 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12128 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 12129 #define SAI_xIMR_WCKCFGIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12130 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12131 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
AnnaBridge 171:3a7713b1edbc 12132 #define SAI_xIMR_FREQIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12133 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12134 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
AnnaBridge 171:3a7713b1edbc 12135 #define SAI_xIMR_CNRDYIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12136 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12137 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
AnnaBridge 171:3a7713b1edbc 12138 #define SAI_xIMR_AFSDETIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12139 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12140 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 12141 #define SAI_xIMR_LFSDETIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12142 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12143 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 12144
AnnaBridge 171:3a7713b1edbc 12145 /******************** Bit definition for SAI_xSR register *******************/
AnnaBridge 171:3a7713b1edbc 12146 #define SAI_xSR_OVRUDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12147 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12148 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
AnnaBridge 171:3a7713b1edbc 12149 #define SAI_xSR_MUTEDET_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12150 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12151 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
AnnaBridge 171:3a7713b1edbc 12152 #define SAI_xSR_WCKCFG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12153 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12154 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
AnnaBridge 171:3a7713b1edbc 12155 #define SAI_xSR_FREQ_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12156 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12157 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
AnnaBridge 171:3a7713b1edbc 12158 #define SAI_xSR_CNRDY_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12159 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12160 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
AnnaBridge 171:3a7713b1edbc 12161 #define SAI_xSR_AFSDET_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12162 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12163 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
AnnaBridge 171:3a7713b1edbc 12164 #define SAI_xSR_LFSDET_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12165 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12166 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
AnnaBridge 171:3a7713b1edbc 12167
AnnaBridge 171:3a7713b1edbc 12168 #define SAI_xSR_FLVL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12169 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 12170 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
AnnaBridge 171:3a7713b1edbc 12171 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12172 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12173 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12174
AnnaBridge 171:3a7713b1edbc 12175 /****************** Bit definition for SAI_xCLRFR register ******************/
AnnaBridge 171:3a7713b1edbc 12176 #define SAI_xCLRFR_COVRUDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12177 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12178 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
AnnaBridge 171:3a7713b1edbc 12179 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12180 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12181 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
AnnaBridge 171:3a7713b1edbc 12182 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12183 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12184 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
AnnaBridge 171:3a7713b1edbc 12185 #define SAI_xCLRFR_CFREQ_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12186 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12187 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
AnnaBridge 171:3a7713b1edbc 12188 #define SAI_xCLRFR_CCNRDY_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12189 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12190 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
AnnaBridge 171:3a7713b1edbc 12191 #define SAI_xCLRFR_CAFSDET_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12192 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12193 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
AnnaBridge 171:3a7713b1edbc 12194 #define SAI_xCLRFR_CLFSDET_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12195 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12196 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
AnnaBridge 171:3a7713b1edbc 12197
AnnaBridge 171:3a7713b1edbc 12198 /****************** Bit definition for SAI_xDR register *********************/
AnnaBridge 171:3a7713b1edbc 12199 #define SAI_xDR_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12200 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12201 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
AnnaBridge 171:3a7713b1edbc 12202
AnnaBridge 171:3a7713b1edbc 12203 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12204 /* */
AnnaBridge 171:3a7713b1edbc 12205 /* SPDIF-RX Interface */
AnnaBridge 171:3a7713b1edbc 12206 /* */
AnnaBridge 171:3a7713b1edbc 12207 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12208 /******************** Bit definition for SPDIF_CR register *******************/
AnnaBridge 171:3a7713b1edbc 12209 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12210 #define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 12211 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
AnnaBridge 171:3a7713b1edbc 12212 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12213 #define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12214 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
AnnaBridge 171:3a7713b1edbc 12215 #define SPDIFRX_CR_RXSTEO_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12216 #define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12217 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
AnnaBridge 171:3a7713b1edbc 12218 #define SPDIFRX_CR_DRFMT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12219 #define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 12220 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
AnnaBridge 171:3a7713b1edbc 12221 #define SPDIFRX_CR_PMSK_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12222 #define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12223 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
AnnaBridge 171:3a7713b1edbc 12224 #define SPDIFRX_CR_VMSK_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12225 #define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12226 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
AnnaBridge 171:3a7713b1edbc 12227 #define SPDIFRX_CR_CUMSK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12228 #define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12229 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
AnnaBridge 171:3a7713b1edbc 12230 #define SPDIFRX_CR_PTMSK_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12231 #define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12232 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
AnnaBridge 171:3a7713b1edbc 12233 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12234 #define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12235 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
AnnaBridge 171:3a7713b1edbc 12236 #define SPDIFRX_CR_CHSEL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12237 #define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12238 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
AnnaBridge 171:3a7713b1edbc 12239 #define SPDIFRX_CR_NBTR_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12240 #define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 12241 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
AnnaBridge 171:3a7713b1edbc 12242 #define SPDIFRX_CR_WFA_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12243 #define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12244 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
AnnaBridge 171:3a7713b1edbc 12245 #define SPDIFRX_CR_INSEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12246 #define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 12247 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
AnnaBridge 171:3a7713b1edbc 12248
AnnaBridge 171:3a7713b1edbc 12249 /******************* Bit definition for SPDIFRX_IMR register *******************/
AnnaBridge 171:3a7713b1edbc 12250 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12251 #define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12252 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
AnnaBridge 171:3a7713b1edbc 12253 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12254 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12255 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12256 #define SPDIFRX_IMR_PERRIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12257 #define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12258 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
AnnaBridge 171:3a7713b1edbc 12259 #define SPDIFRX_IMR_OVRIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12260 #define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12261 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12262 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12263 #define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12264 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12265 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12266 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12267 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
AnnaBridge 171:3a7713b1edbc 12268 #define SPDIFRX_IMR_IFEIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12269 #define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12270 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12271
AnnaBridge 171:3a7713b1edbc 12272 /******************* Bit definition for SPDIFRX_SR register *******************/
AnnaBridge 171:3a7713b1edbc 12273 #define SPDIFRX_SR_RXNE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12274 #define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12275 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
AnnaBridge 171:3a7713b1edbc 12276 #define SPDIFRX_SR_CSRNE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12277 #define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12278 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
AnnaBridge 171:3a7713b1edbc 12279 #define SPDIFRX_SR_PERR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12280 #define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12281 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
AnnaBridge 171:3a7713b1edbc 12282 #define SPDIFRX_SR_OVR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12283 #define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12284 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
AnnaBridge 171:3a7713b1edbc 12285 #define SPDIFRX_SR_SBD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12286 #define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12287 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
AnnaBridge 171:3a7713b1edbc 12288 #define SPDIFRX_SR_SYNCD_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12289 #define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12290 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
AnnaBridge 171:3a7713b1edbc 12291 #define SPDIFRX_SR_FERR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12292 #define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12293 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
AnnaBridge 171:3a7713b1edbc 12294 #define SPDIFRX_SR_SERR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12295 #define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12296 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
AnnaBridge 171:3a7713b1edbc 12297 #define SPDIFRX_SR_TERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12298 #define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12299 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
AnnaBridge 171:3a7713b1edbc 12300 #define SPDIFRX_SR_WIDTH5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12301 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
AnnaBridge 171:3a7713b1edbc 12302 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
AnnaBridge 171:3a7713b1edbc 12303
AnnaBridge 171:3a7713b1edbc 12304 /******************* Bit definition for SPDIFRX_IFCR register *******************/
AnnaBridge 171:3a7713b1edbc 12305 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12306 #define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12307 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
AnnaBridge 171:3a7713b1edbc 12308 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12309 #define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12310 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
AnnaBridge 171:3a7713b1edbc 12311 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12312 #define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12313 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
AnnaBridge 171:3a7713b1edbc 12314 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12315 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12316 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
AnnaBridge 171:3a7713b1edbc 12317
AnnaBridge 171:3a7713b1edbc 12318 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
AnnaBridge 171:3a7713b1edbc 12319 #define SPDIFRX_DR0_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12320 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 12321 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
AnnaBridge 171:3a7713b1edbc 12322 #define SPDIFRX_DR0_PE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12323 #define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12324 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
AnnaBridge 171:3a7713b1edbc 12325 #define SPDIFRX_DR0_V_Pos (25U)
AnnaBridge 171:3a7713b1edbc 12326 #define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12327 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
AnnaBridge 171:3a7713b1edbc 12328 #define SPDIFRX_DR0_U_Pos (26U)
AnnaBridge 171:3a7713b1edbc 12329 #define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12330 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
AnnaBridge 171:3a7713b1edbc 12331 #define SPDIFRX_DR0_C_Pos (27U)
AnnaBridge 171:3a7713b1edbc 12332 #define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12333 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
AnnaBridge 171:3a7713b1edbc 12334 #define SPDIFRX_DR0_PT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 12335 #define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 12336 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
AnnaBridge 171:3a7713b1edbc 12337
AnnaBridge 171:3a7713b1edbc 12338 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
AnnaBridge 171:3a7713b1edbc 12339 #define SPDIFRX_DR1_DR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12340 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 171:3a7713b1edbc 12341 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
AnnaBridge 171:3a7713b1edbc 12342 #define SPDIFRX_DR1_PT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12343 #define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 12344 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
AnnaBridge 171:3a7713b1edbc 12345 #define SPDIFRX_DR1_C_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12346 #define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12347 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
AnnaBridge 171:3a7713b1edbc 12348 #define SPDIFRX_DR1_U_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12349 #define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12350 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
AnnaBridge 171:3a7713b1edbc 12351 #define SPDIFRX_DR1_V_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12352 #define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12353 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
AnnaBridge 171:3a7713b1edbc 12354 #define SPDIFRX_DR1_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12355 #define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12356 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
AnnaBridge 171:3a7713b1edbc 12357
AnnaBridge 171:3a7713b1edbc 12358 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
AnnaBridge 171:3a7713b1edbc 12359 #define SPDIFRX_DR1_DRNL1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12360 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 12361 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
AnnaBridge 171:3a7713b1edbc 12362 #define SPDIFRX_DR1_DRNL2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12363 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12364 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
AnnaBridge 171:3a7713b1edbc 12365
AnnaBridge 171:3a7713b1edbc 12366 /******************* Bit definition for SPDIFRX_CSR register *******************/
AnnaBridge 171:3a7713b1edbc 12367 #define SPDIFRX_CSR_USR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12368 #define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12369 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
AnnaBridge 171:3a7713b1edbc 12370 #define SPDIFRX_CSR_CS_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12371 #define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 12372 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
AnnaBridge 171:3a7713b1edbc 12373 #define SPDIFRX_CSR_SOB_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12374 #define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12375 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
AnnaBridge 171:3a7713b1edbc 12376
AnnaBridge 171:3a7713b1edbc 12377 /******************* Bit definition for SPDIFRX_DIR register *******************/
AnnaBridge 171:3a7713b1edbc 12378 #define SPDIFRX_DIR_THI_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12379 #define SPDIFRX_DIR_THI_Msk (0x13FFU << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */
AnnaBridge 171:3a7713b1edbc 12380 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
AnnaBridge 171:3a7713b1edbc 12381 #define SPDIFRX_DIR_TLO_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12382 #define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
AnnaBridge 171:3a7713b1edbc 12383 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
AnnaBridge 171:3a7713b1edbc 12384
AnnaBridge 171:3a7713b1edbc 12385 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12386 /* */
AnnaBridge 171:3a7713b1edbc 12387 /* SD host Interface */
AnnaBridge 171:3a7713b1edbc 12388 /* */
AnnaBridge 171:3a7713b1edbc 12389 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12390 /****************** Bit definition for SDMMC_POWER register ******************/
AnnaBridge 171:3a7713b1edbc 12391 #define SDMMC_POWER_PWRCTRL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12392 #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 12393 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 171:3a7713b1edbc 12394 #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x01 */
AnnaBridge 171:3a7713b1edbc 12395 #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x02 */
AnnaBridge 171:3a7713b1edbc 12396
AnnaBridge 171:3a7713b1edbc 12397 /****************** Bit definition for SDMMC_CLKCR register ******************/
AnnaBridge 171:3a7713b1edbc 12398 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12399 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 12400 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
AnnaBridge 171:3a7713b1edbc 12401 #define SDMMC_CLKCR_CLKEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12402 #define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12403 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
AnnaBridge 171:3a7713b1edbc 12404 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12405 #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12406 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
AnnaBridge 171:3a7713b1edbc 12407 #define SDMMC_CLKCR_BYPASS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12408 #define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12409 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
AnnaBridge 171:3a7713b1edbc 12410
AnnaBridge 171:3a7713b1edbc 12411 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12412 #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 12413 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 171:3a7713b1edbc 12414 #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 12415 #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 12416
AnnaBridge 171:3a7713b1edbc 12417 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12418 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12419 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
AnnaBridge 171:3a7713b1edbc 12420 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12421 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12422 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
AnnaBridge 171:3a7713b1edbc 12423
AnnaBridge 171:3a7713b1edbc 12424 /******************* Bit definition for SDMMC_ARG register *******************/
AnnaBridge 171:3a7713b1edbc 12425 #define SDMMC_ARG_CMDARG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12426 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12427 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
AnnaBridge 171:3a7713b1edbc 12428
AnnaBridge 171:3a7713b1edbc 12429 /******************* Bit definition for SDMMC_CMD register *******************/
AnnaBridge 171:3a7713b1edbc 12430 #define SDMMC_CMD_CMDINDEX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12431 #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 12432 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
AnnaBridge 171:3a7713b1edbc 12433
AnnaBridge 171:3a7713b1edbc 12434 #define SDMMC_CMD_WAITRESP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12435 #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 12436 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 171:3a7713b1edbc 12437 #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 12438 #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 12439
AnnaBridge 171:3a7713b1edbc 12440 #define SDMMC_CMD_WAITINT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12441 #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12442 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
AnnaBridge 171:3a7713b1edbc 12443 #define SDMMC_CMD_WAITPEND_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12444 #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12445 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 171:3a7713b1edbc 12446 #define SDMMC_CMD_CPSMEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12447 #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12448 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 171:3a7713b1edbc 12449 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12450 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12451 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
AnnaBridge 171:3a7713b1edbc 12452
AnnaBridge 171:3a7713b1edbc 12453 /***************** Bit definition for SDMMC_RESPCMD register *****************/
AnnaBridge 171:3a7713b1edbc 12454 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12455 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 12456 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
AnnaBridge 171:3a7713b1edbc 12457
AnnaBridge 171:3a7713b1edbc 12458 /****************** Bit definition for SDMMC_RESP0 register ******************/
AnnaBridge 171:3a7713b1edbc 12459 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12460 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12461 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
AnnaBridge 171:3a7713b1edbc 12462
AnnaBridge 171:3a7713b1edbc 12463 /****************** Bit definition for SDMMC_RESP1 register ******************/
AnnaBridge 171:3a7713b1edbc 12464 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12465 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12466 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
AnnaBridge 171:3a7713b1edbc 12467
AnnaBridge 171:3a7713b1edbc 12468 /****************** Bit definition for SDMMC_RESP2 register ******************/
AnnaBridge 171:3a7713b1edbc 12469 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12470 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12471 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
AnnaBridge 171:3a7713b1edbc 12472
AnnaBridge 171:3a7713b1edbc 12473 /****************** Bit definition for SDMMC_RESP3 register ******************/
AnnaBridge 171:3a7713b1edbc 12474 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12475 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12476 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
AnnaBridge 171:3a7713b1edbc 12477
AnnaBridge 171:3a7713b1edbc 12478 /****************** Bit definition for SDMMC_RESP4 register ******************/
AnnaBridge 171:3a7713b1edbc 12479 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12480 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12481 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
AnnaBridge 171:3a7713b1edbc 12482
AnnaBridge 171:3a7713b1edbc 12483 /****************** Bit definition for SDMMC_DTIMER register *****************/
AnnaBridge 171:3a7713b1edbc 12484 #define SDMMC_DTIMER_DATATIME_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12485 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12486 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
AnnaBridge 171:3a7713b1edbc 12487
AnnaBridge 171:3a7713b1edbc 12488 /****************** Bit definition for SDMMC_DLEN register *******************/
AnnaBridge 171:3a7713b1edbc 12489 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12490 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
AnnaBridge 171:3a7713b1edbc 12491 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
AnnaBridge 171:3a7713b1edbc 12492
AnnaBridge 171:3a7713b1edbc 12493 /****************** Bit definition for SDMMC_DCTRL register ******************/
AnnaBridge 171:3a7713b1edbc 12494 #define SDMMC_DCTRL_DTEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12495 #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12496 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
AnnaBridge 171:3a7713b1edbc 12497 #define SDMMC_DCTRL_DTDIR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12498 #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12499 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
AnnaBridge 171:3a7713b1edbc 12500 #define SDMMC_DCTRL_DTMODE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12501 #define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12502 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
AnnaBridge 171:3a7713b1edbc 12503 #define SDMMC_DCTRL_DMAEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12504 #define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12505 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
AnnaBridge 171:3a7713b1edbc 12506
AnnaBridge 171:3a7713b1edbc 12507 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12508 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 12509 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 171:3a7713b1edbc 12510 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 12511 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 12512 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 12513 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 12514
AnnaBridge 171:3a7713b1edbc 12515 #define SDMMC_DCTRL_RWSTART_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12516 #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12517 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
AnnaBridge 171:3a7713b1edbc 12518 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12519 #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12520 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
AnnaBridge 171:3a7713b1edbc 12521 #define SDMMC_DCTRL_RWMOD_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12522 #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12523 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
AnnaBridge 171:3a7713b1edbc 12524 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12525 #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12526 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
AnnaBridge 171:3a7713b1edbc 12527
AnnaBridge 171:3a7713b1edbc 12528 /****************** Bit definition for SDMMC_DCOUNT register *****************/
AnnaBridge 171:3a7713b1edbc 12529 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12530 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
AnnaBridge 171:3a7713b1edbc 12531 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
AnnaBridge 171:3a7713b1edbc 12532
AnnaBridge 171:3a7713b1edbc 12533 /****************** Bit definition for SDMMC_STA registe ********************/
AnnaBridge 171:3a7713b1edbc 12534 #define SDMMC_STA_CCRCFAIL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12535 #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12536 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
AnnaBridge 171:3a7713b1edbc 12537 #define SDMMC_STA_DCRCFAIL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12538 #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12539 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
AnnaBridge 171:3a7713b1edbc 12540 #define SDMMC_STA_CTIMEOUT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12541 #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12542 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
AnnaBridge 171:3a7713b1edbc 12543 #define SDMMC_STA_DTIMEOUT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12544 #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12545 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
AnnaBridge 171:3a7713b1edbc 12546 #define SDMMC_STA_TXUNDERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12547 #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12548 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
AnnaBridge 171:3a7713b1edbc 12549 #define SDMMC_STA_RXOVERR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12550 #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12551 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
AnnaBridge 171:3a7713b1edbc 12552 #define SDMMC_STA_CMDREND_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12553 #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12554 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
AnnaBridge 171:3a7713b1edbc 12555 #define SDMMC_STA_CMDSENT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12556 #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12557 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
AnnaBridge 171:3a7713b1edbc 12558 #define SDMMC_STA_DATAEND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12559 #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12560 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 171:3a7713b1edbc 12561 #define SDMMC_STA_DBCKEND_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12562 #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12563 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
AnnaBridge 171:3a7713b1edbc 12564 #define SDMMC_STA_CMDACT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12565 #define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12566 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
AnnaBridge 171:3a7713b1edbc 12567 #define SDMMC_STA_TXACT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12568 #define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12569 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
AnnaBridge 171:3a7713b1edbc 12570 #define SDMMC_STA_RXACT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12571 #define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12572 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
AnnaBridge 171:3a7713b1edbc 12573 #define SDMMC_STA_TXFIFOHE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12574 #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12575 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 171:3a7713b1edbc 12576 #define SDMMC_STA_RXFIFOHF_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12577 #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12578 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 171:3a7713b1edbc 12579 #define SDMMC_STA_TXFIFOF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12580 #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12581 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
AnnaBridge 171:3a7713b1edbc 12582 #define SDMMC_STA_RXFIFOF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12583 #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12584 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
AnnaBridge 171:3a7713b1edbc 12585 #define SDMMC_STA_TXFIFOE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12586 #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12587 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
AnnaBridge 171:3a7713b1edbc 12588 #define SDMMC_STA_RXFIFOE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12589 #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12590 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
AnnaBridge 171:3a7713b1edbc 12591 #define SDMMC_STA_TXDAVL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12592 #define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12593 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
AnnaBridge 171:3a7713b1edbc 12594 #define SDMMC_STA_RXDAVL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 12595 #define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12596 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
AnnaBridge 171:3a7713b1edbc 12597 #define SDMMC_STA_SDIOIT_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12598 #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12599 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDMMC interrupt received */
AnnaBridge 171:3a7713b1edbc 12600
AnnaBridge 171:3a7713b1edbc 12601 /******************* Bit definition for SDMMC_ICR register *******************/
AnnaBridge 171:3a7713b1edbc 12602 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12603 #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12604 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
AnnaBridge 171:3a7713b1edbc 12605 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12606 #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12607 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
AnnaBridge 171:3a7713b1edbc 12608 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12609 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12610 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
AnnaBridge 171:3a7713b1edbc 12611 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12612 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12613 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
AnnaBridge 171:3a7713b1edbc 12614 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12615 #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12616 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
AnnaBridge 171:3a7713b1edbc 12617 #define SDMMC_ICR_RXOVERRC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12618 #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12619 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
AnnaBridge 171:3a7713b1edbc 12620 #define SDMMC_ICR_CMDRENDC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12621 #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12622 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
AnnaBridge 171:3a7713b1edbc 12623 #define SDMMC_ICR_CMDSENTC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12624 #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12625 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
AnnaBridge 171:3a7713b1edbc 12626 #define SDMMC_ICR_DATAENDC_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12627 #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12628 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
AnnaBridge 171:3a7713b1edbc 12629 #define SDMMC_ICR_DBCKENDC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12630 #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12631 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
AnnaBridge 171:3a7713b1edbc 12632 #define SDMMC_ICR_SDIOITC_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12633 #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12634 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDMMCIT flag clear bit */
AnnaBridge 171:3a7713b1edbc 12635
AnnaBridge 171:3a7713b1edbc 12636 /****************** Bit definition for SDMMC_MASK register *******************/
AnnaBridge 171:3a7713b1edbc 12637 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12638 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12639 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12640 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12641 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12642 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12643 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12644 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12645 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12646 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12647 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12648 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12649 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12650 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12651 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12652 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12653 #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12654 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12655 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12656 #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12657 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12658 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12659 #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12660 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12661 #define SDMMC_MASK_DATAENDIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12662 #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12663 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12664 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12665 #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12666 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12667 #define SDMMC_MASK_CMDACTIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12668 #define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12669 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12670 #define SDMMC_MASK_TXACTIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12671 #define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12672 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12673 #define SDMMC_MASK_RXACTIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12674 #define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12675 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
AnnaBridge 171:3a7713b1edbc 12676 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12677 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12678 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12679 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12680 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12681 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12682 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12683 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12684 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12685 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12686 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12687 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12688 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12689 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12690 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12691 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12692 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12693 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12694 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12695 #define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12696 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12697 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
AnnaBridge 171:3a7713b1edbc 12698 #define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12699 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12700 #define SDMMC_MASK_SDIOITIE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12701 #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12702 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12703
AnnaBridge 171:3a7713b1edbc 12704 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
AnnaBridge 171:3a7713b1edbc 12705 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12706 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 12707 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
AnnaBridge 171:3a7713b1edbc 12708
AnnaBridge 171:3a7713b1edbc 12709 /****************** Bit definition for SDMMC_FIFO register *******************/
AnnaBridge 171:3a7713b1edbc 12710 #define SDMMC_FIFO_FIFODATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12711 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12712 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
AnnaBridge 171:3a7713b1edbc 12713
AnnaBridge 171:3a7713b1edbc 12714 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12715 /* */
AnnaBridge 171:3a7713b1edbc 12716 /* Serial Peripheral Interface (SPI) */
AnnaBridge 171:3a7713b1edbc 12717 /* */
AnnaBridge 171:3a7713b1edbc 12718 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12719 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 12720 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12721 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12722 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 12723 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12724 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12725 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 12726 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12727 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12728 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
AnnaBridge 171:3a7713b1edbc 12729 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12730 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 12731 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
AnnaBridge 171:3a7713b1edbc 12732 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12733 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12734 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12735 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12736 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12737 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
AnnaBridge 171:3a7713b1edbc 12738 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12739 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12740 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
AnnaBridge 171:3a7713b1edbc 12741 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12742 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12743 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
AnnaBridge 171:3a7713b1edbc 12744 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12745 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12746 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
AnnaBridge 171:3a7713b1edbc 12747 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12748 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12749 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
AnnaBridge 171:3a7713b1edbc 12750 #define SPI_CR1_CRCL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12751 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12752 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
AnnaBridge 171:3a7713b1edbc 12753 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12754 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12755 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
AnnaBridge 171:3a7713b1edbc 12756 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12757 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12758 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
AnnaBridge 171:3a7713b1edbc 12759 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12760 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12761 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
AnnaBridge 171:3a7713b1edbc 12762 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12763 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12764 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
AnnaBridge 171:3a7713b1edbc 12765
AnnaBridge 171:3a7713b1edbc 12766 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 12767 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12768 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12769 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 12770 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12771 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12772 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 12773 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12774 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12775 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
AnnaBridge 171:3a7713b1edbc 12776 #define SPI_CR2_NSSP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12777 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12778 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
AnnaBridge 171:3a7713b1edbc 12779 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12780 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12781 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
AnnaBridge 171:3a7713b1edbc 12782 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12783 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12784 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12785 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12786 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12787 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12788 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12789 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12790 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12791 #define SPI_CR2_DS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12792 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12793 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
AnnaBridge 171:3a7713b1edbc 12794 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12795 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12796 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12797 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12798 #define SPI_CR2_FRXTH_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12799 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12800 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
AnnaBridge 171:3a7713b1edbc 12801 #define SPI_CR2_LDMARX_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12802 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12803 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
AnnaBridge 171:3a7713b1edbc 12804 #define SPI_CR2_LDMATX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12805 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12806 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
AnnaBridge 171:3a7713b1edbc 12807
AnnaBridge 171:3a7713b1edbc 12808 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 171:3a7713b1edbc 12809 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12810 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12811 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
AnnaBridge 171:3a7713b1edbc 12812 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12813 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12814 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
AnnaBridge 171:3a7713b1edbc 12815 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12816 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12817 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
AnnaBridge 171:3a7713b1edbc 12818 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12819 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12820 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
AnnaBridge 171:3a7713b1edbc 12821 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12822 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12823 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
AnnaBridge 171:3a7713b1edbc 12824 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12825 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12826 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
AnnaBridge 171:3a7713b1edbc 12827 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12828 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12829 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
AnnaBridge 171:3a7713b1edbc 12830 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12831 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12832 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
AnnaBridge 171:3a7713b1edbc 12833 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12834 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12835 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
AnnaBridge 171:3a7713b1edbc 12836 #define SPI_SR_FRLVL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12837 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 12838 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
AnnaBridge 171:3a7713b1edbc 12839 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12840 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12841 #define SPI_SR_FTLVL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12842 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 12843 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
AnnaBridge 171:3a7713b1edbc 12844 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12845 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12846
AnnaBridge 171:3a7713b1edbc 12847 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 171:3a7713b1edbc 12848 #define SPI_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12849 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12850 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
AnnaBridge 171:3a7713b1edbc 12851
AnnaBridge 171:3a7713b1edbc 12852 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 171:3a7713b1edbc 12853 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12854 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12855 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
AnnaBridge 171:3a7713b1edbc 12856
AnnaBridge 171:3a7713b1edbc 12857 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 12858 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12859 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12860 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
AnnaBridge 171:3a7713b1edbc 12861
AnnaBridge 171:3a7713b1edbc 12862 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 12863 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12864 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12865 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
AnnaBridge 171:3a7713b1edbc 12866
AnnaBridge 171:3a7713b1edbc 12867 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 171:3a7713b1edbc 12868 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12869 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12870 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 171:3a7713b1edbc 12871 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12872 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 12873 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 171:3a7713b1edbc 12874 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12875 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12876 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12877 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12878 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 171:3a7713b1edbc 12879 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12880 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 12881 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 171:3a7713b1edbc 12882 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12883 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12884 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12885 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12886 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 171:3a7713b1edbc 12887 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12888 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 12889 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 171:3a7713b1edbc 12890 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12891 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12892 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12893 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12894 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 171:3a7713b1edbc 12895 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12896 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12897 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 171:3a7713b1edbc 12898 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12899 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12900 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
AnnaBridge 171:3a7713b1edbc 12901
AnnaBridge 171:3a7713b1edbc 12902 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 171:3a7713b1edbc 12903 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12904 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 12905 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 171:3a7713b1edbc 12906 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12907 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12908 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 171:3a7713b1edbc 12909 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12910 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12911 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 171:3a7713b1edbc 12912
AnnaBridge 171:3a7713b1edbc 12913
AnnaBridge 171:3a7713b1edbc 12914 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12915 /* */
AnnaBridge 171:3a7713b1edbc 12916 /* SYSCFG */
AnnaBridge 171:3a7713b1edbc 12917 /* */
AnnaBridge 171:3a7713b1edbc 12918 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12919 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 171:3a7713b1edbc 12920 #define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12921 #define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1U << SYSCFG_MEMRMP_MEM_BOOT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12922 #define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk /*!< Boot information after Reset */
AnnaBridge 171:3a7713b1edbc 12923
AnnaBridge 171:3a7713b1edbc 12924
AnnaBridge 171:3a7713b1edbc 12925 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12926 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 12927 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC Memory Mapping swapping */
AnnaBridge 171:3a7713b1edbc 12928 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12929 #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12930
AnnaBridge 171:3a7713b1edbc 12931 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 171:3a7713b1edbc 12932
AnnaBridge 171:3a7713b1edbc 12933 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12934 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 12935 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 171:3a7713b1edbc 12936 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12937 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12938 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 171:3a7713b1edbc 12939 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12940 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12941 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 171:3a7713b1edbc 12942 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12943 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12944 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 171:3a7713b1edbc 12945
AnnaBridge 171:3a7713b1edbc 12946 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12947 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12948 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
AnnaBridge 171:3a7713b1edbc 12949
AnnaBridge 171:3a7713b1edbc 12950 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 171:3a7713b1edbc 12951 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12952 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12953 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 171:3a7713b1edbc 12954 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12955 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 12956 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 171:3a7713b1edbc 12957 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12958 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12959 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 171:3a7713b1edbc 12960 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12961 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 12962 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 171:3a7713b1edbc 12963 /**
AnnaBridge 171:3a7713b1edbc 12964 * @brief EXTI0 configuration
AnnaBridge 171:3a7713b1edbc 12965 */
AnnaBridge 171:3a7713b1edbc 12966 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 171:3a7713b1edbc 12967 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 171:3a7713b1edbc 12968 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 171:3a7713b1edbc 12969 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
AnnaBridge 171:3a7713b1edbc 12970 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
AnnaBridge 171:3a7713b1edbc 12971 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
AnnaBridge 171:3a7713b1edbc 12972 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
AnnaBridge 171:3a7713b1edbc 12973 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 171:3a7713b1edbc 12974 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
AnnaBridge 171:3a7713b1edbc 12975 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
AnnaBridge 171:3a7713b1edbc 12976 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
AnnaBridge 171:3a7713b1edbc 12977
AnnaBridge 171:3a7713b1edbc 12978 /**
AnnaBridge 171:3a7713b1edbc 12979 * @brief EXTI1 configuration
AnnaBridge 171:3a7713b1edbc 12980 */
AnnaBridge 171:3a7713b1edbc 12981 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 171:3a7713b1edbc 12982 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 171:3a7713b1edbc 12983 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 171:3a7713b1edbc 12984 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
AnnaBridge 171:3a7713b1edbc 12985 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
AnnaBridge 171:3a7713b1edbc 12986 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
AnnaBridge 171:3a7713b1edbc 12987 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
AnnaBridge 171:3a7713b1edbc 12988 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 171:3a7713b1edbc 12989 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
AnnaBridge 171:3a7713b1edbc 12990 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
AnnaBridge 171:3a7713b1edbc 12991 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
AnnaBridge 171:3a7713b1edbc 12992
AnnaBridge 171:3a7713b1edbc 12993 /**
AnnaBridge 171:3a7713b1edbc 12994 * @brief EXTI2 configuration
AnnaBridge 171:3a7713b1edbc 12995 */
AnnaBridge 171:3a7713b1edbc 12996 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 171:3a7713b1edbc 12997 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 171:3a7713b1edbc 12998 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 171:3a7713b1edbc 12999 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
AnnaBridge 171:3a7713b1edbc 13000 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
AnnaBridge 171:3a7713b1edbc 13001 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
AnnaBridge 171:3a7713b1edbc 13002 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
AnnaBridge 171:3a7713b1edbc 13003 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 171:3a7713b1edbc 13004 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
AnnaBridge 171:3a7713b1edbc 13005 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
AnnaBridge 171:3a7713b1edbc 13006 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
AnnaBridge 171:3a7713b1edbc 13007
AnnaBridge 171:3a7713b1edbc 13008 /**
AnnaBridge 171:3a7713b1edbc 13009 * @brief EXTI3 configuration
AnnaBridge 171:3a7713b1edbc 13010 */
AnnaBridge 171:3a7713b1edbc 13011 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 171:3a7713b1edbc 13012 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 171:3a7713b1edbc 13013 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 171:3a7713b1edbc 13014 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
AnnaBridge 171:3a7713b1edbc 13015 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
AnnaBridge 171:3a7713b1edbc 13016 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
AnnaBridge 171:3a7713b1edbc 13017 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
AnnaBridge 171:3a7713b1edbc 13018 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
AnnaBridge 171:3a7713b1edbc 13019 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
AnnaBridge 171:3a7713b1edbc 13020 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
AnnaBridge 171:3a7713b1edbc 13021 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
AnnaBridge 171:3a7713b1edbc 13022
AnnaBridge 171:3a7713b1edbc 13023 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 171:3a7713b1edbc 13024 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13025 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 13026 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 171:3a7713b1edbc 13027 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13028 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 13029 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 171:3a7713b1edbc 13030 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13031 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 13032 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 171:3a7713b1edbc 13033 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13034 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 13035 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 171:3a7713b1edbc 13036 /**
AnnaBridge 171:3a7713b1edbc 13037 * @brief EXTI4 configuration
AnnaBridge 171:3a7713b1edbc 13038 */
AnnaBridge 171:3a7713b1edbc 13039 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 171:3a7713b1edbc 13040 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 171:3a7713b1edbc 13041 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 171:3a7713b1edbc 13042 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
AnnaBridge 171:3a7713b1edbc 13043 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
AnnaBridge 171:3a7713b1edbc 13044 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
AnnaBridge 171:3a7713b1edbc 13045 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
AnnaBridge 171:3a7713b1edbc 13046 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 171:3a7713b1edbc 13047 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
AnnaBridge 171:3a7713b1edbc 13048 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
AnnaBridge 171:3a7713b1edbc 13049 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
AnnaBridge 171:3a7713b1edbc 13050
AnnaBridge 171:3a7713b1edbc 13051 /**
AnnaBridge 171:3a7713b1edbc 13052 * @brief EXTI5 configuration
AnnaBridge 171:3a7713b1edbc 13053 */
AnnaBridge 171:3a7713b1edbc 13054 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 171:3a7713b1edbc 13055 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 171:3a7713b1edbc 13056 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 171:3a7713b1edbc 13057 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
AnnaBridge 171:3a7713b1edbc 13058 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
AnnaBridge 171:3a7713b1edbc 13059 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
AnnaBridge 171:3a7713b1edbc 13060 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
AnnaBridge 171:3a7713b1edbc 13061 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 171:3a7713b1edbc 13062 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
AnnaBridge 171:3a7713b1edbc 13063 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
AnnaBridge 171:3a7713b1edbc 13064 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
AnnaBridge 171:3a7713b1edbc 13065
AnnaBridge 171:3a7713b1edbc 13066 /**
AnnaBridge 171:3a7713b1edbc 13067 * @brief EXTI6 configuration
AnnaBridge 171:3a7713b1edbc 13068 */
AnnaBridge 171:3a7713b1edbc 13069 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 171:3a7713b1edbc 13070 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 171:3a7713b1edbc 13071 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 171:3a7713b1edbc 13072 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
AnnaBridge 171:3a7713b1edbc 13073 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
AnnaBridge 171:3a7713b1edbc 13074 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
AnnaBridge 171:3a7713b1edbc 13075 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
AnnaBridge 171:3a7713b1edbc 13076 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 171:3a7713b1edbc 13077 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
AnnaBridge 171:3a7713b1edbc 13078 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
AnnaBridge 171:3a7713b1edbc 13079 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
AnnaBridge 171:3a7713b1edbc 13080
AnnaBridge 171:3a7713b1edbc 13081 /**
AnnaBridge 171:3a7713b1edbc 13082 * @brief EXTI7 configuration
AnnaBridge 171:3a7713b1edbc 13083 */
AnnaBridge 171:3a7713b1edbc 13084 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 171:3a7713b1edbc 13085 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 171:3a7713b1edbc 13086 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 171:3a7713b1edbc 13087 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
AnnaBridge 171:3a7713b1edbc 13088 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
AnnaBridge 171:3a7713b1edbc 13089 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
AnnaBridge 171:3a7713b1edbc 13090 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
AnnaBridge 171:3a7713b1edbc 13091 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
AnnaBridge 171:3a7713b1edbc 13092 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
AnnaBridge 171:3a7713b1edbc 13093 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
AnnaBridge 171:3a7713b1edbc 13094 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
AnnaBridge 171:3a7713b1edbc 13095
AnnaBridge 171:3a7713b1edbc 13096 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 171:3a7713b1edbc 13097 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13098 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 13099 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 171:3a7713b1edbc 13100 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13101 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 13102 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 171:3a7713b1edbc 13103 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13104 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 13105 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 171:3a7713b1edbc 13106 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13107 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 13108 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 171:3a7713b1edbc 13109
AnnaBridge 171:3a7713b1edbc 13110 /**
AnnaBridge 171:3a7713b1edbc 13111 * @brief EXTI8 configuration
AnnaBridge 171:3a7713b1edbc 13112 */
AnnaBridge 171:3a7713b1edbc 13113 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 171:3a7713b1edbc 13114 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 171:3a7713b1edbc 13115 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 171:3a7713b1edbc 13116 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
AnnaBridge 171:3a7713b1edbc 13117 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
AnnaBridge 171:3a7713b1edbc 13118 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
AnnaBridge 171:3a7713b1edbc 13119 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
AnnaBridge 171:3a7713b1edbc 13120 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 171:3a7713b1edbc 13121 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
AnnaBridge 171:3a7713b1edbc 13122 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
AnnaBridge 171:3a7713b1edbc 13123
AnnaBridge 171:3a7713b1edbc 13124 /**
AnnaBridge 171:3a7713b1edbc 13125 * @brief EXTI9 configuration
AnnaBridge 171:3a7713b1edbc 13126 */
AnnaBridge 171:3a7713b1edbc 13127 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 171:3a7713b1edbc 13128 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 171:3a7713b1edbc 13129 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 171:3a7713b1edbc 13130 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
AnnaBridge 171:3a7713b1edbc 13131 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
AnnaBridge 171:3a7713b1edbc 13132 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
AnnaBridge 171:3a7713b1edbc 13133 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
AnnaBridge 171:3a7713b1edbc 13134 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 171:3a7713b1edbc 13135 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
AnnaBridge 171:3a7713b1edbc 13136 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
AnnaBridge 171:3a7713b1edbc 13137
AnnaBridge 171:3a7713b1edbc 13138 /**
AnnaBridge 171:3a7713b1edbc 13139 * @brief EXTI10 configuration
AnnaBridge 171:3a7713b1edbc 13140 */
AnnaBridge 171:3a7713b1edbc 13141 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 171:3a7713b1edbc 13142 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 171:3a7713b1edbc 13143 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 171:3a7713b1edbc 13144 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
AnnaBridge 171:3a7713b1edbc 13145 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
AnnaBridge 171:3a7713b1edbc 13146 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
AnnaBridge 171:3a7713b1edbc 13147 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
AnnaBridge 171:3a7713b1edbc 13148 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 171:3a7713b1edbc 13149 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
AnnaBridge 171:3a7713b1edbc 13150 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
AnnaBridge 171:3a7713b1edbc 13151
AnnaBridge 171:3a7713b1edbc 13152 /**
AnnaBridge 171:3a7713b1edbc 13153 * @brief EXTI11 configuration
AnnaBridge 171:3a7713b1edbc 13154 */
AnnaBridge 171:3a7713b1edbc 13155 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 171:3a7713b1edbc 13156 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 171:3a7713b1edbc 13157 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 171:3a7713b1edbc 13158 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
AnnaBridge 171:3a7713b1edbc 13159 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
AnnaBridge 171:3a7713b1edbc 13160 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
AnnaBridge 171:3a7713b1edbc 13161 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
AnnaBridge 171:3a7713b1edbc 13162 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
AnnaBridge 171:3a7713b1edbc 13163 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
AnnaBridge 171:3a7713b1edbc 13164 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
AnnaBridge 171:3a7713b1edbc 13165
AnnaBridge 171:3a7713b1edbc 13166
AnnaBridge 171:3a7713b1edbc 13167 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 171:3a7713b1edbc 13168 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13169 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 13170 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 171:3a7713b1edbc 13171 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13172 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 13173 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 171:3a7713b1edbc 13174 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13175 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 13176 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 171:3a7713b1edbc 13177 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13178 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 13179 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 171:3a7713b1edbc 13180 /**
AnnaBridge 171:3a7713b1edbc 13181 * @brief EXTI12 configuration
AnnaBridge 171:3a7713b1edbc 13182 */
AnnaBridge 171:3a7713b1edbc 13183 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 171:3a7713b1edbc 13184 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 171:3a7713b1edbc 13185 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 171:3a7713b1edbc 13186 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
AnnaBridge 171:3a7713b1edbc 13187 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
AnnaBridge 171:3a7713b1edbc 13188 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
AnnaBridge 171:3a7713b1edbc 13189 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
AnnaBridge 171:3a7713b1edbc 13190 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 171:3a7713b1edbc 13191 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
AnnaBridge 171:3a7713b1edbc 13192 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
AnnaBridge 171:3a7713b1edbc 13193
AnnaBridge 171:3a7713b1edbc 13194 /**
AnnaBridge 171:3a7713b1edbc 13195 * @brief EXTI13 configuration
AnnaBridge 171:3a7713b1edbc 13196 */
AnnaBridge 171:3a7713b1edbc 13197 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 171:3a7713b1edbc 13198 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 171:3a7713b1edbc 13199 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 171:3a7713b1edbc 13200 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
AnnaBridge 171:3a7713b1edbc 13201 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
AnnaBridge 171:3a7713b1edbc 13202 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
AnnaBridge 171:3a7713b1edbc 13203 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
AnnaBridge 171:3a7713b1edbc 13204 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 171:3a7713b1edbc 13205 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
AnnaBridge 171:3a7713b1edbc 13206 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
AnnaBridge 171:3a7713b1edbc 13207
AnnaBridge 171:3a7713b1edbc 13208 /**
AnnaBridge 171:3a7713b1edbc 13209 * @brief EXTI14 configuration
AnnaBridge 171:3a7713b1edbc 13210 */
AnnaBridge 171:3a7713b1edbc 13211 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 171:3a7713b1edbc 13212 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 171:3a7713b1edbc 13213 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 171:3a7713b1edbc 13214 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
AnnaBridge 171:3a7713b1edbc 13215 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
AnnaBridge 171:3a7713b1edbc 13216 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
AnnaBridge 171:3a7713b1edbc 13217 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
AnnaBridge 171:3a7713b1edbc 13218 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 171:3a7713b1edbc 13219 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
AnnaBridge 171:3a7713b1edbc 13220 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
AnnaBridge 171:3a7713b1edbc 13221
AnnaBridge 171:3a7713b1edbc 13222 /**
AnnaBridge 171:3a7713b1edbc 13223 * @brief EXTI15 configuration
AnnaBridge 171:3a7713b1edbc 13224 */
AnnaBridge 171:3a7713b1edbc 13225 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 171:3a7713b1edbc 13226 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 171:3a7713b1edbc 13227 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 171:3a7713b1edbc 13228 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
AnnaBridge 171:3a7713b1edbc 13229 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
AnnaBridge 171:3a7713b1edbc 13230 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
AnnaBridge 171:3a7713b1edbc 13231 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
AnnaBridge 171:3a7713b1edbc 13232 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 171:3a7713b1edbc 13233 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
AnnaBridge 171:3a7713b1edbc 13234 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
AnnaBridge 171:3a7713b1edbc 13235
AnnaBridge 171:3a7713b1edbc 13236
AnnaBridge 171:3a7713b1edbc 13237 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 171:3a7713b1edbc 13238 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13239 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13240 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell power-down */
AnnaBridge 171:3a7713b1edbc 13241 #define SYSCFG_CMPCR_READY_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13242 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13243 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell ready flag */
AnnaBridge 171:3a7713b1edbc 13244
AnnaBridge 171:3a7713b1edbc 13245 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13246 /* */
AnnaBridge 171:3a7713b1edbc 13247 /* TIM */
AnnaBridge 171:3a7713b1edbc 13248 /* */
AnnaBridge 171:3a7713b1edbc 13249 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13250 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 13251 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13252 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13253 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 171:3a7713b1edbc 13254 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13255 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13256 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 171:3a7713b1edbc 13257 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13258 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13259 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 171:3a7713b1edbc 13260 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13261 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13262 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 171:3a7713b1edbc 13263 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13264 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13265 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 171:3a7713b1edbc 13266
AnnaBridge 171:3a7713b1edbc 13267 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13268 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 13269 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 171:3a7713b1edbc 13270 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 13271 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 13272
AnnaBridge 171:3a7713b1edbc 13273 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13274 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13275 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 171:3a7713b1edbc 13276
AnnaBridge 171:3a7713b1edbc 13277 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13278 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 13279 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 171:3a7713b1edbc 13280 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 13281 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 13282 #define TIM_CR1_UIFREMAP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13283 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13284 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<UIF status bit */
AnnaBridge 171:3a7713b1edbc 13285
AnnaBridge 171:3a7713b1edbc 13286 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 13287 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13288 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13289 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 171:3a7713b1edbc 13290 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13291 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13292 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 171:3a7713b1edbc 13293 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13294 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13295 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 171:3a7713b1edbc 13296
AnnaBridge 171:3a7713b1edbc 13297 #define TIM_CR2_OIS5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13298 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13299 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 13300 #define TIM_CR2_OIS6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13301 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13302 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 13303
AnnaBridge 171:3a7713b1edbc 13304 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13305 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 13306 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 13307 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 13308 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 13309 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 13310
AnnaBridge 171:3a7713b1edbc 13311 #define TIM_CR2_MMS2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13312 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 13313 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 13314 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13315 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13316 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13317 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13318
AnnaBridge 171:3a7713b1edbc 13319 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13320 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13321 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 171:3a7713b1edbc 13322 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13323 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13324 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 171:3a7713b1edbc 13325 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13326 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13327 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 171:3a7713b1edbc 13328 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13329 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13330 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 171:3a7713b1edbc 13331 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13332 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13333 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 171:3a7713b1edbc 13334 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13335 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13336 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 171:3a7713b1edbc 13337 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13338 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13339 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 171:3a7713b1edbc 13340 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13341 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13342 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 13343
AnnaBridge 171:3a7713b1edbc 13344 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 171:3a7713b1edbc 13345 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13346 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
AnnaBridge 171:3a7713b1edbc 13347 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 171:3a7713b1edbc 13348 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13349 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13350 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13351 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13352
AnnaBridge 171:3a7713b1edbc 13353 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13354 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 13355 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 171:3a7713b1edbc 13356 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 13357 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 13358 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 13359
AnnaBridge 171:3a7713b1edbc 13360 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13361 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13362 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 171:3a7713b1edbc 13363
AnnaBridge 171:3a7713b1edbc 13364 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13365 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 13366 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 171:3a7713b1edbc 13367 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 13368 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 13369 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 13370 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 13371
AnnaBridge 171:3a7713b1edbc 13372 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13373 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 13374 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 171:3a7713b1edbc 13375 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 13376 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 13377
AnnaBridge 171:3a7713b1edbc 13378 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13379 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13380 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 171:3a7713b1edbc 13381 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13382 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13383 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 171:3a7713b1edbc 13384
AnnaBridge 171:3a7713b1edbc 13385 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 171:3a7713b1edbc 13386 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13387 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13388 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 171:3a7713b1edbc 13389 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13390 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13391 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 13392 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13393 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13394 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 13395 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13396 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13397 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 13398 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13399 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13400 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 13401 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13402 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13403 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 171:3a7713b1edbc 13404 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13405 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13406 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 171:3a7713b1edbc 13407 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13408 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13409 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 171:3a7713b1edbc 13410 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13411 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13412 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 171:3a7713b1edbc 13413 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13414 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13415 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 171:3a7713b1edbc 13416 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13417 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13418 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 171:3a7713b1edbc 13419 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13420 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13421 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 171:3a7713b1edbc 13422 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13423 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13424 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 171:3a7713b1edbc 13425 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13426 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13427 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 171:3a7713b1edbc 13428 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13429 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13430 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 171:3a7713b1edbc 13431
AnnaBridge 171:3a7713b1edbc 13432 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 171:3a7713b1edbc 13433 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13434 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13435 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13436 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13437 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13438 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13439 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13440 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13441 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13442 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13443 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13444 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13445 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13446 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13447 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13448 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13449 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13450 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13451 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13452 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13453 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13454 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13455 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13456 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13457 #define TIM_SR_B2IF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13458 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13459 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13460 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13461 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13462 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 13463 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13464 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13465 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 13466 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13467 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13468 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 13469 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13470 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13471 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 13472 #define TIM_SR_SBIF_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13473 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13474 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13475 #define TIM_SR_CC5IF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13476 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13477 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13478 #define TIM_SR_CC6IF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13479 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13480 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13481
AnnaBridge 171:3a7713b1edbc 13482 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 171:3a7713b1edbc 13483 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13484 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13485 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 171:3a7713b1edbc 13486 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13487 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13488 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 171:3a7713b1edbc 13489 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13490 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13491 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 171:3a7713b1edbc 13492 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13493 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13494 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 171:3a7713b1edbc 13495 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13496 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13497 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 171:3a7713b1edbc 13498 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13499 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13500 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 171:3a7713b1edbc 13501 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13502 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13503 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 171:3a7713b1edbc 13504 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13505 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13506 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 171:3a7713b1edbc 13507 #define TIM_EGR_B2G_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13508 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13509 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break2 Generation */
AnnaBridge 171:3a7713b1edbc 13510
AnnaBridge 171:3a7713b1edbc 13511 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 171:3a7713b1edbc 13512 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13513 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 13514 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 171:3a7713b1edbc 13515 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13516 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13517
AnnaBridge 171:3a7713b1edbc 13518 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13519 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13520 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 171:3a7713b1edbc 13521 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13522 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13523 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 171:3a7713b1edbc 13524
AnnaBridge 171:3a7713b1edbc 13525 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13526 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 13527 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 171:3a7713b1edbc 13528 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13529 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13530 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13531 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13532
AnnaBridge 171:3a7713b1edbc 13533 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13534 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13535 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 171:3a7713b1edbc 13536
AnnaBridge 171:3a7713b1edbc 13537 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13538 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 13539 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 171:3a7713b1edbc 13540 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13541 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13542
AnnaBridge 171:3a7713b1edbc 13543 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13544 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13545 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 171:3a7713b1edbc 13546 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13547 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13548 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 171:3a7713b1edbc 13549
AnnaBridge 171:3a7713b1edbc 13550 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13551 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 13552 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 171:3a7713b1edbc 13553 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13554 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13555 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13556 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13557
AnnaBridge 171:3a7713b1edbc 13558 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13559 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13560 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13561
AnnaBridge 171:3a7713b1edbc 13562 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 13563
AnnaBridge 171:3a7713b1edbc 13564 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13565 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 13566 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 171:3a7713b1edbc 13567 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 13568 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 13569
AnnaBridge 171:3a7713b1edbc 13570 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13571 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 13572 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 171:3a7713b1edbc 13573 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 13574 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 13575 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 13576 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 13577
AnnaBridge 171:3a7713b1edbc 13578 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13579 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 13580 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 171:3a7713b1edbc 13581 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 13582 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 13583
AnnaBridge 171:3a7713b1edbc 13584 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13585 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 13586 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 171:3a7713b1edbc 13587 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 13588 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 13589 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
AnnaBridge 171:3a7713b1edbc 13590 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
AnnaBridge 171:3a7713b1edbc 13591
AnnaBridge 171:3a7713b1edbc 13592 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 171:3a7713b1edbc 13593 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13594 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 13595 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 171:3a7713b1edbc 13596 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13597 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13598
AnnaBridge 171:3a7713b1edbc 13599 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13600 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13601 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 171:3a7713b1edbc 13602 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13603 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13604 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 171:3a7713b1edbc 13605
AnnaBridge 171:3a7713b1edbc 13606 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13607 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 13608 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 171:3a7713b1edbc 13609 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13610 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13611 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13612 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13613
AnnaBridge 171:3a7713b1edbc 13614
AnnaBridge 171:3a7713b1edbc 13615
AnnaBridge 171:3a7713b1edbc 13616 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13617 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13618 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13619
AnnaBridge 171:3a7713b1edbc 13620 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13621 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 13622 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 171:3a7713b1edbc 13623 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13624 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13625
AnnaBridge 171:3a7713b1edbc 13626 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13627 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13628 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 171:3a7713b1edbc 13629 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13630 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13631 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 171:3a7713b1edbc 13632
AnnaBridge 171:3a7713b1edbc 13633 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13634 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 13635 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 171:3a7713b1edbc 13636 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13637 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13638 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13639 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13640
AnnaBridge 171:3a7713b1edbc 13641 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13642 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13643 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13644
AnnaBridge 171:3a7713b1edbc 13645 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 13646
AnnaBridge 171:3a7713b1edbc 13647 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13648 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 13649 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 171:3a7713b1edbc 13650 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 13651 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 13652
AnnaBridge 171:3a7713b1edbc 13653 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13654 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 13655 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 171:3a7713b1edbc 13656 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 13657 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 13658 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 13659 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 13660
AnnaBridge 171:3a7713b1edbc 13661 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13662 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 13663 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 171:3a7713b1edbc 13664 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 13665 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 13666
AnnaBridge 171:3a7713b1edbc 13667 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13668 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 13669 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 171:3a7713b1edbc 13670 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 13671 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
AnnaBridge 171:3a7713b1edbc 13672 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
AnnaBridge 171:3a7713b1edbc 13673 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
AnnaBridge 171:3a7713b1edbc 13674
AnnaBridge 171:3a7713b1edbc 13675 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 171:3a7713b1edbc 13676 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13677 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13678 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 171:3a7713b1edbc 13679 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13680 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13681 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 171:3a7713b1edbc 13682 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13683 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13684 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 13685 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13686 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13687 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 13688 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13689 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13690 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 171:3a7713b1edbc 13691 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13692 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13693 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 171:3a7713b1edbc 13694 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13695 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13696 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 13697 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13698 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13699 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 13700 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13701 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13702 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 171:3a7713b1edbc 13703 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13704 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13705 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 171:3a7713b1edbc 13706 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13707 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13708 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 13709 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13710 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13711 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 13712 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13713 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13714 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 171:3a7713b1edbc 13715 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13716 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13717 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 171:3a7713b1edbc 13718 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13719 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13720 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 13721 #define TIM_CCER_CC5E_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13722 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13723 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
AnnaBridge 171:3a7713b1edbc 13724 #define TIM_CCER_CC5P_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13725 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13726 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
AnnaBridge 171:3a7713b1edbc 13727 #define TIM_CCER_CC6E_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13728 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13729 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
AnnaBridge 171:3a7713b1edbc 13730 #define TIM_CCER_CC6P_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13731 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13732 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
AnnaBridge 171:3a7713b1edbc 13733
AnnaBridge 171:3a7713b1edbc 13734
AnnaBridge 171:3a7713b1edbc 13735 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 171:3a7713b1edbc 13736 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13737 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 13738 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 171:3a7713b1edbc 13739 #define TIM_CNT_UIFCPY_Pos (31U)
AnnaBridge 171:3a7713b1edbc 13740 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 13741 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
AnnaBridge 171:3a7713b1edbc 13742
AnnaBridge 171:3a7713b1edbc 13743 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 171:3a7713b1edbc 13744 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13745 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13746 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 171:3a7713b1edbc 13747
AnnaBridge 171:3a7713b1edbc 13748 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 171:3a7713b1edbc 13749 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13750 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 13751 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 171:3a7713b1edbc 13752
AnnaBridge 171:3a7713b1edbc 13753 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 171:3a7713b1edbc 13754 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13755 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13756 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 171:3a7713b1edbc 13757
AnnaBridge 171:3a7713b1edbc 13758 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 171:3a7713b1edbc 13759 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13760 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13761 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 171:3a7713b1edbc 13762
AnnaBridge 171:3a7713b1edbc 13763 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 171:3a7713b1edbc 13764 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13765 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13766 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 171:3a7713b1edbc 13767
AnnaBridge 171:3a7713b1edbc 13768 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 171:3a7713b1edbc 13769 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13770 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13771 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 171:3a7713b1edbc 13772
AnnaBridge 171:3a7713b1edbc 13773 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 171:3a7713b1edbc 13774 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13775 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13776 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 171:3a7713b1edbc 13777
AnnaBridge 171:3a7713b1edbc 13778 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 171:3a7713b1edbc 13779 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13780 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 13781 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 171:3a7713b1edbc 13782 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13783 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13784 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13785 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13786 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13787 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13788 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13789 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13790
AnnaBridge 171:3a7713b1edbc 13791 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13792 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 13793 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 171:3a7713b1edbc 13794 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13795 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13796
AnnaBridge 171:3a7713b1edbc 13797 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13798 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13799 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 171:3a7713b1edbc 13800 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13801 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13802 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 171:3a7713b1edbc 13803 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13804 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13805 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 171:3a7713b1edbc 13806 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13807 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13808 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 171:3a7713b1edbc 13809 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13810 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13811 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 171:3a7713b1edbc 13812 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13813 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13814 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 171:3a7713b1edbc 13815 #define TIM_BDTR_BKF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13816 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 13817 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
AnnaBridge 171:3a7713b1edbc 13818 #define TIM_BDTR_BK2F_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13819 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 13820 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
AnnaBridge 171:3a7713b1edbc 13821 #define TIM_BDTR_BK2E_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13822 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13823 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
AnnaBridge 171:3a7713b1edbc 13824 #define TIM_BDTR_BK2P_Pos (25U)
AnnaBridge 171:3a7713b1edbc 13825 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13826 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
AnnaBridge 171:3a7713b1edbc 13827
AnnaBridge 171:3a7713b1edbc 13828 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 171:3a7713b1edbc 13829 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13830 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 13831 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 171:3a7713b1edbc 13832 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 13833 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 13834 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 13835 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 13836 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 13837
AnnaBridge 171:3a7713b1edbc 13838 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13839 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 13840 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 171:3a7713b1edbc 13841 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 13842 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
AnnaBridge 171:3a7713b1edbc 13843 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 13844 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 13845 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
AnnaBridge 171:3a7713b1edbc 13846
AnnaBridge 171:3a7713b1edbc 13847 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 171:3a7713b1edbc 13848 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13849 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13850 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 171:3a7713b1edbc 13851
AnnaBridge 171:3a7713b1edbc 13852 /******************* Bit definition for TIM_OR regiter *********************/
AnnaBridge 171:3a7713b1edbc 13853 #define TIM_OR_TI4_RMP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13854 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 13855 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 171:3a7713b1edbc 13856 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 13857 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 13858 #define TIM_OR_ITR1_RMP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13859 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 13860 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
AnnaBridge 171:3a7713b1edbc 13861 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
AnnaBridge 171:3a7713b1edbc 13862 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
AnnaBridge 171:3a7713b1edbc 13863
AnnaBridge 171:3a7713b1edbc 13864 /******************* Bit definition for TIM2_OR register *******************/
AnnaBridge 171:3a7713b1edbc 13865 #define TIM2_OR_ITR1_RMP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13866 #define TIM2_OR_ITR1_RMP_Msk (0x3U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 13867 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
AnnaBridge 171:3a7713b1edbc 13868 #define TIM2_OR_ITR1_RMP_0 (0x1U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13869 #define TIM2_OR_ITR1_RMP_1 (0x2U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13870
AnnaBridge 171:3a7713b1edbc 13871 /******************* Bit definition for TIM5_OR register *******************/
AnnaBridge 171:3a7713b1edbc 13872 #define TIM5_OR_TI4_RMP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13873 #define TIM5_OR_TI4_RMP_Msk (0x3U << TIM5_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 13874 #define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */
AnnaBridge 171:3a7713b1edbc 13875 #define TIM5_OR_TI4_RMP_0 (0x1U << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13876 #define TIM5_OR_TI4_RMP_1 (0x2U << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13877
AnnaBridge 171:3a7713b1edbc 13878 /******************* Bit definition for TIM11_OR register *******************/
AnnaBridge 171:3a7713b1edbc 13879 #define TIM11_OR_TI1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13880 #define TIM11_OR_TI1_RMP_Msk (0x3U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 13881 #define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
AnnaBridge 171:3a7713b1edbc 13882 #define TIM11_OR_TI1_RMP_0 (0x1U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13883 #define TIM11_OR_TI1_RMP_1 (0x2U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13884
AnnaBridge 171:3a7713b1edbc 13885 /****************** Bit definition for TIM_CCMR3 register *******************/
AnnaBridge 171:3a7713b1edbc 13886 #define TIM_CCMR3_OC5FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13887 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13888 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
AnnaBridge 171:3a7713b1edbc 13889 #define TIM_CCMR3_OC5PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13890 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13891 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
AnnaBridge 171:3a7713b1edbc 13892
AnnaBridge 171:3a7713b1edbc 13893 #define TIM_CCMR3_OC5M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13894 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 13895 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
AnnaBridge 171:3a7713b1edbc 13896 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13897 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13898 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13899 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13900
AnnaBridge 171:3a7713b1edbc 13901 #define TIM_CCMR3_OC5CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13902 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13903 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13904
AnnaBridge 171:3a7713b1edbc 13905 #define TIM_CCMR3_OC6FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13906 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13907 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 171:3a7713b1edbc 13908 #define TIM_CCMR3_OC6PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13909 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13910 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 171:3a7713b1edbc 13911
AnnaBridge 171:3a7713b1edbc 13912 #define TIM_CCMR3_OC6M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13913 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 13914 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 171:3a7713b1edbc 13915 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13916 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13917 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13918 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13919
AnnaBridge 171:3a7713b1edbc 13920 #define TIM_CCMR3_OC6CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13921 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13922 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13923
AnnaBridge 171:3a7713b1edbc 13924 /******************* Bit definition for TIM_CCR5 register *******************/
AnnaBridge 171:3a7713b1edbc 13925 #define TIM_CCR5_CCR5_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13926 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 13927 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
AnnaBridge 171:3a7713b1edbc 13928 #define TIM_CCR5_GC5C1_Pos (29U)
AnnaBridge 171:3a7713b1edbc 13929 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 13930 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
AnnaBridge 171:3a7713b1edbc 13931 #define TIM_CCR5_GC5C2_Pos (30U)
AnnaBridge 171:3a7713b1edbc 13932 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 13933 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
AnnaBridge 171:3a7713b1edbc 13934 #define TIM_CCR5_GC5C3_Pos (31U)
AnnaBridge 171:3a7713b1edbc 13935 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 13936 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
AnnaBridge 171:3a7713b1edbc 13937
AnnaBridge 171:3a7713b1edbc 13938 /******************* Bit definition for TIM_CCR6 register *******************/
AnnaBridge 171:3a7713b1edbc 13939 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
AnnaBridge 171:3a7713b1edbc 13940
AnnaBridge 171:3a7713b1edbc 13941
AnnaBridge 171:3a7713b1edbc 13942 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13943 /* */
AnnaBridge 171:3a7713b1edbc 13944 /* Low Power Timer (LPTIM) */
AnnaBridge 171:3a7713b1edbc 13945 /* */
AnnaBridge 171:3a7713b1edbc 13946 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13947 /****************** Bit definition for LPTIM_ISR register *******************/
AnnaBridge 171:3a7713b1edbc 13948 #define LPTIM_ISR_CMPM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13949 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13950 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
AnnaBridge 171:3a7713b1edbc 13951 #define LPTIM_ISR_ARRM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13952 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13953 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
AnnaBridge 171:3a7713b1edbc 13954 #define LPTIM_ISR_EXTTRIG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13955 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13956 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
AnnaBridge 171:3a7713b1edbc 13957 #define LPTIM_ISR_CMPOK_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13958 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13959 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
AnnaBridge 171:3a7713b1edbc 13960 #define LPTIM_ISR_ARROK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13961 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13962 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
AnnaBridge 171:3a7713b1edbc 13963 #define LPTIM_ISR_UP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13964 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13965 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
AnnaBridge 171:3a7713b1edbc 13966 #define LPTIM_ISR_DOWN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13967 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13968 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
AnnaBridge 171:3a7713b1edbc 13969
AnnaBridge 171:3a7713b1edbc 13970 /****************** Bit definition for LPTIM_ICR register *******************/
AnnaBridge 171:3a7713b1edbc 13971 #define LPTIM_ICR_CMPMCF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13972 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13973 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
AnnaBridge 171:3a7713b1edbc 13974 #define LPTIM_ICR_ARRMCF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13975 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13976 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
AnnaBridge 171:3a7713b1edbc 13977 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13978 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13979 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
AnnaBridge 171:3a7713b1edbc 13980 #define LPTIM_ICR_CMPOKCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13981 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13982 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
AnnaBridge 171:3a7713b1edbc 13983 #define LPTIM_ICR_ARROKCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13984 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13985 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
AnnaBridge 171:3a7713b1edbc 13986 #define LPTIM_ICR_UPCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13987 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13988 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
AnnaBridge 171:3a7713b1edbc 13989 #define LPTIM_ICR_DOWNCF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13990 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13991 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
AnnaBridge 171:3a7713b1edbc 13992
AnnaBridge 171:3a7713b1edbc 13993 /****************** Bit definition for LPTIM_IER register *******************/
AnnaBridge 171:3a7713b1edbc 13994 #define LPTIM_IER_CMPMIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13995 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13996 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 13997 #define LPTIM_IER_ARRMIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13998 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13999 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14000 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14001 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14002 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14003 #define LPTIM_IER_CMPOKIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14004 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14005 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14006 #define LPTIM_IER_ARROKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14007 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14008 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14009 #define LPTIM_IER_UPIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14010 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14011 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14012 #define LPTIM_IER_DOWNIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14013 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14014 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14015
AnnaBridge 171:3a7713b1edbc 14016 /****************** Bit definition for LPTIM_CFGR register*******************/
AnnaBridge 171:3a7713b1edbc 14017 #define LPTIM_CFGR_CKSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14018 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14019 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
AnnaBridge 171:3a7713b1edbc 14020
AnnaBridge 171:3a7713b1edbc 14021 #define LPTIM_CFGR_CKPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14022 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 14023 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
AnnaBridge 171:3a7713b1edbc 14024 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14025 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14026
AnnaBridge 171:3a7713b1edbc 14027 #define LPTIM_CFGR_CKFLT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14028 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 14029 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
AnnaBridge 171:3a7713b1edbc 14030 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14031 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14032
AnnaBridge 171:3a7713b1edbc 14033 #define LPTIM_CFGR_TRGFLT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14034 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 14035 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
AnnaBridge 171:3a7713b1edbc 14036 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14037 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14038
AnnaBridge 171:3a7713b1edbc 14039 #define LPTIM_CFGR_PRESC_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14040 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 14041 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
AnnaBridge 171:3a7713b1edbc 14042 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14043 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14044 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14045
AnnaBridge 171:3a7713b1edbc 14046 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
AnnaBridge 171:3a7713b1edbc 14047 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 14048 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
AnnaBridge 171:3a7713b1edbc 14049 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14050 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14051 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14052
AnnaBridge 171:3a7713b1edbc 14053 #define LPTIM_CFGR_TRIGEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14054 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
AnnaBridge 171:3a7713b1edbc 14055 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
AnnaBridge 171:3a7713b1edbc 14056 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14057 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14058
AnnaBridge 171:3a7713b1edbc 14059 #define LPTIM_CFGR_TIMOUT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 14060 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14061 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
AnnaBridge 171:3a7713b1edbc 14062 #define LPTIM_CFGR_WAVE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14063 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14064 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
AnnaBridge 171:3a7713b1edbc 14065 #define LPTIM_CFGR_WAVPOL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14066 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14067 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
AnnaBridge 171:3a7713b1edbc 14068 #define LPTIM_CFGR_PRELOAD_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14069 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14070 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
AnnaBridge 171:3a7713b1edbc 14071 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 14072 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14073 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
AnnaBridge 171:3a7713b1edbc 14074 #define LPTIM_CFGR_ENC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14075 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 14076 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
AnnaBridge 171:3a7713b1edbc 14077
AnnaBridge 171:3a7713b1edbc 14078 /****************** Bit definition for LPTIM_CR register ********************/
AnnaBridge 171:3a7713b1edbc 14079 #define LPTIM_CR_ENABLE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14080 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14081 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
AnnaBridge 171:3a7713b1edbc 14082 #define LPTIM_CR_SNGSTRT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14083 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14084 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
AnnaBridge 171:3a7713b1edbc 14085 #define LPTIM_CR_CNTSTRT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14086 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14087 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
AnnaBridge 171:3a7713b1edbc 14088
AnnaBridge 171:3a7713b1edbc 14089 /****************** Bit definition for LPTIM_CMP register *******************/
AnnaBridge 171:3a7713b1edbc 14090 #define LPTIM_CMP_CMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14091 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 14092 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
AnnaBridge 171:3a7713b1edbc 14093
AnnaBridge 171:3a7713b1edbc 14094 /****************** Bit definition for LPTIM_ARR register *******************/
AnnaBridge 171:3a7713b1edbc 14095 #define LPTIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14096 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 14097 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
AnnaBridge 171:3a7713b1edbc 14098
AnnaBridge 171:3a7713b1edbc 14099 /****************** Bit definition for LPTIM_CNT register *******************/
AnnaBridge 171:3a7713b1edbc 14100 #define LPTIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14101 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 14102 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
AnnaBridge 171:3a7713b1edbc 14103 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14104 /* */
AnnaBridge 171:3a7713b1edbc 14105 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
AnnaBridge 171:3a7713b1edbc 14106 /* */
AnnaBridge 171:3a7713b1edbc 14107 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14108 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 14109 #define USART_CR1_UE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14110 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14111 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
AnnaBridge 171:3a7713b1edbc 14112 #define USART_CR1_RE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14113 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14114 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
AnnaBridge 171:3a7713b1edbc 14115 #define USART_CR1_TE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14116 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14117 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 14118 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14119 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14120 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14121 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14122 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14123 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14124 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14125 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14126 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14127 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14128 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14129 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14130 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14131 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14132 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14133 #define USART_CR1_PS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14134 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14135 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
AnnaBridge 171:3a7713b1edbc 14136 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14137 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14138 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
AnnaBridge 171:3a7713b1edbc 14139 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14140 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14141 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
AnnaBridge 171:3a7713b1edbc 14142 #define USART_CR1_M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14143 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
AnnaBridge 171:3a7713b1edbc 14144 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
AnnaBridge 171:3a7713b1edbc 14145 #define USART_CR1_M0 (0x00001U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14146 #define USART_CR1_MME_Pos (13U)
AnnaBridge 171:3a7713b1edbc 14147 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14148 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
AnnaBridge 171:3a7713b1edbc 14149 #define USART_CR1_CMIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14150 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14151 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
AnnaBridge 171:3a7713b1edbc 14152 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14153 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14154 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
AnnaBridge 171:3a7713b1edbc 14155 #define USART_CR1_DEDT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14156 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 14157 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
AnnaBridge 171:3a7713b1edbc 14158 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14159 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14160 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14161 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14162 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14163 #define USART_CR1_DEAT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14164 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
AnnaBridge 171:3a7713b1edbc 14165 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
AnnaBridge 171:3a7713b1edbc 14166 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14167 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14168 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14169 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 14170 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 14171 #define USART_CR1_RTOIE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 14172 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 14173 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
AnnaBridge 171:3a7713b1edbc 14174 #define USART_CR1_EOBIE_Pos (27U)
AnnaBridge 171:3a7713b1edbc 14175 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 14176 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
AnnaBridge 171:3a7713b1edbc 14177 #define USART_CR1_M1 0x10000000U /*!< Word length - Bit 1 */
AnnaBridge 171:3a7713b1edbc 14178
AnnaBridge 171:3a7713b1edbc 14179 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 14180 #define USART_CR1_M_0 USART_CR1_M0 /*!< Word length - Bit 0 */
AnnaBridge 171:3a7713b1edbc 14181 #define USART_CR1_M_1 USART_CR1_M1 /*!< Word length - Bit 1 */
AnnaBridge 171:3a7713b1edbc 14182
AnnaBridge 171:3a7713b1edbc 14183 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 14184 #define USART_CR2_ADDM7_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14185 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14186 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
AnnaBridge 171:3a7713b1edbc 14187 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14188 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14189 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
AnnaBridge 171:3a7713b1edbc 14190 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14191 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14192 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14193 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14194 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14195 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
AnnaBridge 171:3a7713b1edbc 14196 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14197 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14198 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 14199 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14200 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14201 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 14202 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14203 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14204 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
AnnaBridge 171:3a7713b1edbc 14205 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14206 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 14207 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
AnnaBridge 171:3a7713b1edbc 14208 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14209 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14210 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14211 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14212 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
AnnaBridge 171:3a7713b1edbc 14213 #define USART_CR2_SWAP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14214 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14215 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
AnnaBridge 171:3a7713b1edbc 14216 #define USART_CR2_RXINV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14217 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14218 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
AnnaBridge 171:3a7713b1edbc 14219 #define USART_CR2_TXINV_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14220 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14221 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
AnnaBridge 171:3a7713b1edbc 14222 #define USART_CR2_DATAINV_Pos (18U)
AnnaBridge 171:3a7713b1edbc 14223 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14224 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
AnnaBridge 171:3a7713b1edbc 14225 #define USART_CR2_MSBFIRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 14226 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14227 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
AnnaBridge 171:3a7713b1edbc 14228 #define USART_CR2_ABREN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14229 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14230 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable */
AnnaBridge 171:3a7713b1edbc 14231 #define USART_CR2_ABRMODE_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14232 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 14233 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
AnnaBridge 171:3a7713b1edbc 14234 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14235 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14236 #define USART_CR2_RTOEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 14237 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14238 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
AnnaBridge 171:3a7713b1edbc 14239 #define USART_CR2_ADD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14240 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 14241 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
AnnaBridge 171:3a7713b1edbc 14242
AnnaBridge 171:3a7713b1edbc 14243 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 171:3a7713b1edbc 14244 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14245 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14246 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14247 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14248 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14249 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
AnnaBridge 171:3a7713b1edbc 14250 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14251 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14252 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
AnnaBridge 171:3a7713b1edbc 14253 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14254 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14255 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
AnnaBridge 171:3a7713b1edbc 14256 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14257 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14258 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
AnnaBridge 171:3a7713b1edbc 14259 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14260 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14261 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
AnnaBridge 171:3a7713b1edbc 14262 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14263 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14264 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
AnnaBridge 171:3a7713b1edbc 14265 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14266 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14267 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
AnnaBridge 171:3a7713b1edbc 14268 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14269 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14270 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
AnnaBridge 171:3a7713b1edbc 14271 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14272 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14273 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
AnnaBridge 171:3a7713b1edbc 14274 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14275 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14276 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14277 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14278 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14279 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
AnnaBridge 171:3a7713b1edbc 14280 #define USART_CR3_OVRDIS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14281 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14282 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
AnnaBridge 171:3a7713b1edbc 14283 #define USART_CR3_DDRE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 14284 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14285 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
AnnaBridge 171:3a7713b1edbc 14286 #define USART_CR3_DEM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14287 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14288 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
AnnaBridge 171:3a7713b1edbc 14289 #define USART_CR3_DEP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14290 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14291 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
AnnaBridge 171:3a7713b1edbc 14292 #define USART_CR3_SCARCNT_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14293 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 14294 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
AnnaBridge 171:3a7713b1edbc 14295 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14296 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14297 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14298
AnnaBridge 171:3a7713b1edbc 14299 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 171:3a7713b1edbc 14300 #define USART_BRR_DIV_FRACTION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14301 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 14302 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
AnnaBridge 171:3a7713b1edbc 14303 #define USART_BRR_DIV_MANTISSA_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14304 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 14305 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
AnnaBridge 171:3a7713b1edbc 14306
AnnaBridge 171:3a7713b1edbc 14307 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 171:3a7713b1edbc 14308 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14309 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 14310 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
AnnaBridge 171:3a7713b1edbc 14311 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14312 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 14313 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
AnnaBridge 171:3a7713b1edbc 14314
AnnaBridge 171:3a7713b1edbc 14315
AnnaBridge 171:3a7713b1edbc 14316 /******************* Bit definition for USART_RTOR register *****************/
AnnaBridge 171:3a7713b1edbc 14317 #define USART_RTOR_RTO_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14318 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 14319 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
AnnaBridge 171:3a7713b1edbc 14320 #define USART_RTOR_BLEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14321 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 14322 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
AnnaBridge 171:3a7713b1edbc 14323
AnnaBridge 171:3a7713b1edbc 14324 /******************* Bit definition for USART_RQR register ******************/
AnnaBridge 171:3a7713b1edbc 14325 #define USART_RQR_ABRRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14326 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14327 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
AnnaBridge 171:3a7713b1edbc 14328 #define USART_RQR_SBKRQ_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14329 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14330 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
AnnaBridge 171:3a7713b1edbc 14331 #define USART_RQR_MMRQ_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14332 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14333 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
AnnaBridge 171:3a7713b1edbc 14334 #define USART_RQR_RXFRQ_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14335 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14336 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
AnnaBridge 171:3a7713b1edbc 14337 #define USART_RQR_TXFRQ_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14338 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14339 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
AnnaBridge 171:3a7713b1edbc 14340
AnnaBridge 171:3a7713b1edbc 14341 /******************* Bit definition for USART_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 14342 #define USART_ISR_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14343 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14344 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
AnnaBridge 171:3a7713b1edbc 14345 #define USART_ISR_FE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14346 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14347 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
AnnaBridge 171:3a7713b1edbc 14348 #define USART_ISR_NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14349 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14350 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
AnnaBridge 171:3a7713b1edbc 14351 #define USART_ISR_ORE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14352 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14353 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
AnnaBridge 171:3a7713b1edbc 14354 #define USART_ISR_IDLE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14355 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14356 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
AnnaBridge 171:3a7713b1edbc 14357 #define USART_ISR_RXNE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14358 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14359 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
AnnaBridge 171:3a7713b1edbc 14360 #define USART_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14361 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14362 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
AnnaBridge 171:3a7713b1edbc 14363 #define USART_ISR_TXE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14364 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14365 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
AnnaBridge 171:3a7713b1edbc 14366 #define USART_ISR_LBDF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14367 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14368 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
AnnaBridge 171:3a7713b1edbc 14369 #define USART_ISR_CTSIF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14370 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14371 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
AnnaBridge 171:3a7713b1edbc 14372 #define USART_ISR_CTS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14373 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14374 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
AnnaBridge 171:3a7713b1edbc 14375 #define USART_ISR_RTOF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14376 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14377 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
AnnaBridge 171:3a7713b1edbc 14378 #define USART_ISR_EOBF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14379 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14380 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
AnnaBridge 171:3a7713b1edbc 14381 #define USART_ISR_ABRE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14382 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14383 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
AnnaBridge 171:3a7713b1edbc 14384 #define USART_ISR_ABRF_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14385 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14386 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
AnnaBridge 171:3a7713b1edbc 14387 #define USART_ISR_BUSY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14388 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14389 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
AnnaBridge 171:3a7713b1edbc 14390 #define USART_ISR_CMF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14391 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14392 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
AnnaBridge 171:3a7713b1edbc 14393 #define USART_ISR_SBKF_Pos (18U)
AnnaBridge 171:3a7713b1edbc 14394 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14395 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
AnnaBridge 171:3a7713b1edbc 14396 #define USART_ISR_RWU_Pos (19U)
AnnaBridge 171:3a7713b1edbc 14397 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14398 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
AnnaBridge 171:3a7713b1edbc 14399 #define USART_ISR_TEACK_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14400 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14401 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
AnnaBridge 171:3a7713b1edbc 14402 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 14403 #define USART_ISR_LBD USART_ISR_LBDF
AnnaBridge 171:3a7713b1edbc 14404
AnnaBridge 171:3a7713b1edbc 14405 /******************* Bit definition for USART_ICR register ******************/
AnnaBridge 171:3a7713b1edbc 14406 #define USART_ICR_PECF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14407 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14408 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 14409 #define USART_ICR_FECF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14410 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14411 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 14412 #define USART_ICR_NCF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14413 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14414 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 14415 #define USART_ICR_ORECF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14416 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14417 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 14418 #define USART_ICR_IDLECF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14419 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14420 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 14421 #define USART_ICR_TCCF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14422 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14423 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
AnnaBridge 171:3a7713b1edbc 14424 #define USART_ICR_LBDCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14425 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14426 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
AnnaBridge 171:3a7713b1edbc 14427 #define USART_ICR_CTSCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14428 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14429 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
AnnaBridge 171:3a7713b1edbc 14430 #define USART_ICR_RTOCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14431 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14432 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
AnnaBridge 171:3a7713b1edbc 14433 #define USART_ICR_EOBCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14434 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14435 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
AnnaBridge 171:3a7713b1edbc 14436 #define USART_ICR_CMCF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14437 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14438 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
AnnaBridge 171:3a7713b1edbc 14439
AnnaBridge 171:3a7713b1edbc 14440 /******************* Bit definition for USART_RDR register ******************/
AnnaBridge 171:3a7713b1edbc 14441 #define USART_RDR_RDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14442 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 14443 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
AnnaBridge 171:3a7713b1edbc 14444
AnnaBridge 171:3a7713b1edbc 14445 /******************* Bit definition for USART_TDR register ******************/
AnnaBridge 171:3a7713b1edbc 14446 #define USART_TDR_TDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14447 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 14448 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
AnnaBridge 171:3a7713b1edbc 14449
AnnaBridge 171:3a7713b1edbc 14450 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14451 /* */
AnnaBridge 171:3a7713b1edbc 14452 /* Window WATCHDOG */
AnnaBridge 171:3a7713b1edbc 14453 /* */
AnnaBridge 171:3a7713b1edbc 14454 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14455 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 171:3a7713b1edbc 14456 #define WWDG_CR_T_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14457 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 14458 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 171:3a7713b1edbc 14459 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
AnnaBridge 171:3a7713b1edbc 14460 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
AnnaBridge 171:3a7713b1edbc 14461 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
AnnaBridge 171:3a7713b1edbc 14462 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
AnnaBridge 171:3a7713b1edbc 14463 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
AnnaBridge 171:3a7713b1edbc 14464 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
AnnaBridge 171:3a7713b1edbc 14465 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
AnnaBridge 171:3a7713b1edbc 14466
AnnaBridge 171:3a7713b1edbc 14467 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 14468 #define WWDG_CR_T0 WWDG_CR_T_0 /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 14469 #define WWDG_CR_T1 WWDG_CR_T_1 /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 14470 #define WWDG_CR_T2 WWDG_CR_T_2 /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 14471 #define WWDG_CR_T3 WWDG_CR_T_3 /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 14472 #define WWDG_CR_T4 WWDG_CR_T_4 /*!<Bit 4 */
AnnaBridge 171:3a7713b1edbc 14473 #define WWDG_CR_T5 WWDG_CR_T_5 /*!<Bit 5 */
AnnaBridge 171:3a7713b1edbc 14474 #define WWDG_CR_T6 WWDG_CR_T_6 /*!<Bit 6 */
AnnaBridge 171:3a7713b1edbc 14475
AnnaBridge 171:3a7713b1edbc 14476 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14477 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14478 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 171:3a7713b1edbc 14479
AnnaBridge 171:3a7713b1edbc 14480 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 171:3a7713b1edbc 14481 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14482 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 14483 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 171:3a7713b1edbc 14484 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
AnnaBridge 171:3a7713b1edbc 14485 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
AnnaBridge 171:3a7713b1edbc 14486 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
AnnaBridge 171:3a7713b1edbc 14487 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
AnnaBridge 171:3a7713b1edbc 14488 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
AnnaBridge 171:3a7713b1edbc 14489 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
AnnaBridge 171:3a7713b1edbc 14490 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
AnnaBridge 171:3a7713b1edbc 14491
AnnaBridge 171:3a7713b1edbc 14492 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 14493 #define WWDG_CFR_W0 WWDG_CFR_W_0 /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 14494 #define WWDG_CFR_W1 WWDG_CFR_W_1 /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 14495 #define WWDG_CFR_W2 WWDG_CFR_W_2 /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 14496 #define WWDG_CFR_W3 WWDG_CFR_W_3 /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 14497 #define WWDG_CFR_W4 WWDG_CFR_W_4 /*!<Bit 4 */
AnnaBridge 171:3a7713b1edbc 14498 #define WWDG_CFR_W5 WWDG_CFR_W_5 /*!<Bit 5 */
AnnaBridge 171:3a7713b1edbc 14499 #define WWDG_CFR_W6 WWDG_CFR_W_6 /*!<Bit 6 */
AnnaBridge 171:3a7713b1edbc 14500
AnnaBridge 171:3a7713b1edbc 14501 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14502 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 14503 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 171:3a7713b1edbc 14504 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
AnnaBridge 171:3a7713b1edbc 14505 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
AnnaBridge 171:3a7713b1edbc 14506
AnnaBridge 171:3a7713b1edbc 14507 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 14508 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 14509 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 14510
AnnaBridge 171:3a7713b1edbc 14511 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14512 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14513 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 14514
AnnaBridge 171:3a7713b1edbc 14515 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 14516 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14517 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14518 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 14519
AnnaBridge 171:3a7713b1edbc 14520 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14521 /* */
AnnaBridge 171:3a7713b1edbc 14522 /* DBG */
AnnaBridge 171:3a7713b1edbc 14523 /* */
AnnaBridge 171:3a7713b1edbc 14524 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14525 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 171:3a7713b1edbc 14526 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14527 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 14528 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 171:3a7713b1edbc 14529 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14530 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 14531 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 171:3a7713b1edbc 14532
AnnaBridge 171:3a7713b1edbc 14533 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 171:3a7713b1edbc 14534 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14535 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14536 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 171:3a7713b1edbc 14537 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14538 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14539 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14540 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14541 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14542 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 171:3a7713b1edbc 14543 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14544 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14545 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 171:3a7713b1edbc 14546
AnnaBridge 171:3a7713b1edbc 14547 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14548 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 14549 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 171:3a7713b1edbc 14550 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14551 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14552
AnnaBridge 171:3a7713b1edbc 14553 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 171:3a7713b1edbc 14554 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14555 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14556 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14557 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14558 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14559 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14560 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14561 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14562 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14563 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14564 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14565 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14566 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14567 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14568 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14569 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14570 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14571 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14572 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14573 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14574 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14575 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14576 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14577 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14578 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14579 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14580 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14581 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14582 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14583 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14584 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14585 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14586 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14587 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14588 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14589 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14590 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14591 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14592 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14593 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14594 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14595 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 171:3a7713b1edbc 14596 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14597 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14598 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
AnnaBridge 171:3a7713b1edbc 14599 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
AnnaBridge 171:3a7713b1edbc 14600 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14601 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
AnnaBridge 171:3a7713b1edbc 14602 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
AnnaBridge 171:3a7713b1edbc 14603 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 14604 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14605 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
AnnaBridge 171:3a7713b1edbc 14606 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 14607 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14608
AnnaBridge 171:3a7713b1edbc 14609 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 171:3a7713b1edbc 14610 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14611 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14612 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14613 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14614 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14615 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14616 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14617 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14618 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14619 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14620 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14621 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14622 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 14623 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14624 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
AnnaBridge 171:3a7713b1edbc 14625
AnnaBridge 171:3a7713b1edbc 14626 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14627 /* */
AnnaBridge 171:3a7713b1edbc 14628 /* Ethernet MAC Registers bits definitions */
AnnaBridge 171:3a7713b1edbc 14629 /* */
AnnaBridge 171:3a7713b1edbc 14630 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14631 /* Bit definition for Ethernet MAC Control Register register */
AnnaBridge 171:3a7713b1edbc 14632 #define ETH_MACCR_WD_Pos (23U)
AnnaBridge 171:3a7713b1edbc 14633 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14634 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
AnnaBridge 171:3a7713b1edbc 14635 #define ETH_MACCR_JD_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14636 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14637 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
AnnaBridge 171:3a7713b1edbc 14638 #define ETH_MACCR_IFG_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14639 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 14640 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
AnnaBridge 171:3a7713b1edbc 14641 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
AnnaBridge 171:3a7713b1edbc 14642 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
AnnaBridge 171:3a7713b1edbc 14643 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
AnnaBridge 171:3a7713b1edbc 14644 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
AnnaBridge 171:3a7713b1edbc 14645 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
AnnaBridge 171:3a7713b1edbc 14646 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
AnnaBridge 171:3a7713b1edbc 14647 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
AnnaBridge 171:3a7713b1edbc 14648 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
AnnaBridge 171:3a7713b1edbc 14649 #define ETH_MACCR_CSD_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14650 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14651 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
AnnaBridge 171:3a7713b1edbc 14652 #define ETH_MACCR_FES_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14653 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14654 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
AnnaBridge 171:3a7713b1edbc 14655 #define ETH_MACCR_ROD_Pos (13U)
AnnaBridge 171:3a7713b1edbc 14656 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14657 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
AnnaBridge 171:3a7713b1edbc 14658 #define ETH_MACCR_LM_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14659 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14660 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
AnnaBridge 171:3a7713b1edbc 14661 #define ETH_MACCR_DM_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14662 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14663 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
AnnaBridge 171:3a7713b1edbc 14664 #define ETH_MACCR_IPCO_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14665 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14666 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
AnnaBridge 171:3a7713b1edbc 14667 #define ETH_MACCR_RD_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14668 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14669 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
AnnaBridge 171:3a7713b1edbc 14670 #define ETH_MACCR_APCS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14671 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14672 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
AnnaBridge 171:3a7713b1edbc 14673 #define ETH_MACCR_BL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14674 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 14675 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
AnnaBridge 171:3a7713b1edbc 14676 a transmission attempt during retries after a collision: 0 =< r <2^k */
AnnaBridge 171:3a7713b1edbc 14677 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
AnnaBridge 171:3a7713b1edbc 14678 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
AnnaBridge 171:3a7713b1edbc 14679 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
AnnaBridge 171:3a7713b1edbc 14680 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
AnnaBridge 171:3a7713b1edbc 14681 #define ETH_MACCR_DC_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14682 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14683 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
AnnaBridge 171:3a7713b1edbc 14684 #define ETH_MACCR_TE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14685 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14686 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
AnnaBridge 171:3a7713b1edbc 14687 #define ETH_MACCR_RE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14688 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14689 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
AnnaBridge 171:3a7713b1edbc 14690
AnnaBridge 171:3a7713b1edbc 14691 /* Bit definition for Ethernet MAC Frame Filter Register */
AnnaBridge 171:3a7713b1edbc 14692 #define ETH_MACFFR_RA_Pos (31U)
AnnaBridge 171:3a7713b1edbc 14693 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 14694 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
AnnaBridge 171:3a7713b1edbc 14695 #define ETH_MACFFR_HPF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14696 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14697 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
AnnaBridge 171:3a7713b1edbc 14698 #define ETH_MACFFR_SAF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14699 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14700 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
AnnaBridge 171:3a7713b1edbc 14701 #define ETH_MACFFR_SAIF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14702 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14703 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
AnnaBridge 171:3a7713b1edbc 14704 #define ETH_MACFFR_PCF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14705 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 14706 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
AnnaBridge 171:3a7713b1edbc 14707 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14708 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14709 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
AnnaBridge 171:3a7713b1edbc 14710 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14711 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14712 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
AnnaBridge 171:3a7713b1edbc 14713 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14714 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 14715 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
AnnaBridge 171:3a7713b1edbc 14716 #define ETH_MACFFR_BFD_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14717 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14718 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
AnnaBridge 171:3a7713b1edbc 14719 #define ETH_MACFFR_PAM_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14720 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14721 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
AnnaBridge 171:3a7713b1edbc 14722 #define ETH_MACFFR_DAIF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14723 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14724 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
AnnaBridge 171:3a7713b1edbc 14725 #define ETH_MACFFR_HM_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14726 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14727 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
AnnaBridge 171:3a7713b1edbc 14728 #define ETH_MACFFR_HU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14729 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14730 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
AnnaBridge 171:3a7713b1edbc 14731 #define ETH_MACFFR_PM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14732 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14733 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
AnnaBridge 171:3a7713b1edbc 14734
AnnaBridge 171:3a7713b1edbc 14735 /* Bit definition for Ethernet MAC Hash Table High Register */
AnnaBridge 171:3a7713b1edbc 14736 #define ETH_MACHTHR_HTH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14737 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 14738 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
AnnaBridge 171:3a7713b1edbc 14739
AnnaBridge 171:3a7713b1edbc 14740 /* Bit definition for Ethernet MAC Hash Table Low Register */
AnnaBridge 171:3a7713b1edbc 14741 #define ETH_MACHTLR_HTL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14742 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 14743 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
AnnaBridge 171:3a7713b1edbc 14744
AnnaBridge 171:3a7713b1edbc 14745 /* Bit definition for Ethernet MAC MII Address Register */
AnnaBridge 171:3a7713b1edbc 14746 #define ETH_MACMIIAR_PA_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14747 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
AnnaBridge 171:3a7713b1edbc 14748 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
AnnaBridge 171:3a7713b1edbc 14749 #define ETH_MACMIIAR_MR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14750 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 14751 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
AnnaBridge 171:3a7713b1edbc 14752 #define ETH_MACMIIAR_CR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14753 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
AnnaBridge 171:3a7713b1edbc 14754 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
AnnaBridge 171:3a7713b1edbc 14755 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
AnnaBridge 171:3a7713b1edbc 14756 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14757 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14758 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
AnnaBridge 171:3a7713b1edbc 14759 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14760 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14761 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
AnnaBridge 171:3a7713b1edbc 14762 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14763 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 14764 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
AnnaBridge 171:3a7713b1edbc 14765 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14766 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14767 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
AnnaBridge 171:3a7713b1edbc 14768 #define ETH_MACMIIAR_MW_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14769 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14770 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
AnnaBridge 171:3a7713b1edbc 14771 #define ETH_MACMIIAR_MB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14772 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14773 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
AnnaBridge 171:3a7713b1edbc 14774
AnnaBridge 171:3a7713b1edbc 14775 /* Bit definition for Ethernet MAC MII Data Register */
AnnaBridge 171:3a7713b1edbc 14776 #define ETH_MACMIIDR_MD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14777 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 14778 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
AnnaBridge 171:3a7713b1edbc 14779
AnnaBridge 171:3a7713b1edbc 14780 /* Bit definition for Ethernet MAC Flow Control Register */
AnnaBridge 171:3a7713b1edbc 14781 #define ETH_MACFCR_PT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14782 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 14783 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
AnnaBridge 171:3a7713b1edbc 14784 #define ETH_MACFCR_ZQPD_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14785 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14786 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
AnnaBridge 171:3a7713b1edbc 14787 #define ETH_MACFCR_PLT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14788 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 14789 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
AnnaBridge 171:3a7713b1edbc 14790 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
AnnaBridge 171:3a7713b1edbc 14791 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14792 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14793 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
AnnaBridge 171:3a7713b1edbc 14794 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14795 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14796 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
AnnaBridge 171:3a7713b1edbc 14797 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14798 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 14799 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
AnnaBridge 171:3a7713b1edbc 14800 #define ETH_MACFCR_UPFD_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14801 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14802 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
AnnaBridge 171:3a7713b1edbc 14803 #define ETH_MACFCR_RFCE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14804 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14805 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
AnnaBridge 171:3a7713b1edbc 14806 #define ETH_MACFCR_TFCE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14807 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14808 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
AnnaBridge 171:3a7713b1edbc 14809 #define ETH_MACFCR_FCBBPA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14810 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14811 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
AnnaBridge 171:3a7713b1edbc 14812
AnnaBridge 171:3a7713b1edbc 14813 /* Bit definition for Ethernet MAC VLAN Tag Register */
AnnaBridge 171:3a7713b1edbc 14814 #define ETH_MACVLANTR_VLANTC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14815 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14816 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
AnnaBridge 171:3a7713b1edbc 14817 #define ETH_MACVLANTR_VLANTI_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14818 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 14819 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
AnnaBridge 171:3a7713b1edbc 14820
AnnaBridge 171:3a7713b1edbc 14821 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
AnnaBridge 171:3a7713b1edbc 14822 #define ETH_MACRWUFFR_D_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14823 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 14824 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
AnnaBridge 171:3a7713b1edbc 14825 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
AnnaBridge 171:3a7713b1edbc 14826 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
AnnaBridge 171:3a7713b1edbc 14827 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
AnnaBridge 171:3a7713b1edbc 14828 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
AnnaBridge 171:3a7713b1edbc 14829 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
AnnaBridge 171:3a7713b1edbc 14830 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
AnnaBridge 171:3a7713b1edbc 14831 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
AnnaBridge 171:3a7713b1edbc 14832 RSVD - Filter1 Command - RSVD - Filter0 Command
AnnaBridge 171:3a7713b1edbc 14833 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
AnnaBridge 171:3a7713b1edbc 14834 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
AnnaBridge 171:3a7713b1edbc 14835 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
AnnaBridge 171:3a7713b1edbc 14836
AnnaBridge 171:3a7713b1edbc 14837 /* Bit definition for Ethernet MAC PMT Control and Status Register */
AnnaBridge 171:3a7713b1edbc 14838 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
AnnaBridge 171:3a7713b1edbc 14839 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 14840 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
AnnaBridge 171:3a7713b1edbc 14841 #define ETH_MACPMTCSR_GU_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14842 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14843 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
AnnaBridge 171:3a7713b1edbc 14844 #define ETH_MACPMTCSR_WFR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14845 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14846 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
AnnaBridge 171:3a7713b1edbc 14847 #define ETH_MACPMTCSR_MPR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14848 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14849 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
AnnaBridge 171:3a7713b1edbc 14850 #define ETH_MACPMTCSR_WFE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14851 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14852 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
AnnaBridge 171:3a7713b1edbc 14853 #define ETH_MACPMTCSR_MPE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14854 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14855 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
AnnaBridge 171:3a7713b1edbc 14856 #define ETH_MACPMTCSR_PD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14857 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14858 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
AnnaBridge 171:3a7713b1edbc 14859
AnnaBridge 171:3a7713b1edbc 14860 /* Bit definition for Ethernet MAC debug Register */
AnnaBridge 171:3a7713b1edbc 14861 #define ETH_MACDBGR_TFF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 14862 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 14863 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
AnnaBridge 171:3a7713b1edbc 14864 #define ETH_MACDBGR_TFNE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14865 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 14866 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
AnnaBridge 171:3a7713b1edbc 14867 #define ETH_MACDBGR_TPWA_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14868 #define ETH_MACDBGR_TPWA_Msk (0x1U << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14869 #define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
AnnaBridge 171:3a7713b1edbc 14870 #define ETH_MACDBGR_TFRS_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14871 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 14872 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
AnnaBridge 171:3a7713b1edbc 14873 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14874 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 14875 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge 171:3a7713b1edbc 14876 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14877 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14878 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
AnnaBridge 171:3a7713b1edbc 14879 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14880 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14881 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
AnnaBridge 171:3a7713b1edbc 14882 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
AnnaBridge 171:3a7713b1edbc 14883 #define ETH_MACDBGR_MTP_Pos (19U)
AnnaBridge 171:3a7713b1edbc 14884 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14885 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
AnnaBridge 171:3a7713b1edbc 14886 #define ETH_MACDBGR_MTFCS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14887 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
AnnaBridge 171:3a7713b1edbc 14888 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
AnnaBridge 171:3a7713b1edbc 14889 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14890 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
AnnaBridge 171:3a7713b1edbc 14891 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
AnnaBridge 171:3a7713b1edbc 14892 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
AnnaBridge 171:3a7713b1edbc 14893 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14894 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge 171:3a7713b1edbc 14895 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14896 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14897 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge 171:3a7713b1edbc 14898 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
AnnaBridge 171:3a7713b1edbc 14899 #define ETH_MACDBGR_MMTEA_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14900 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14901 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
AnnaBridge 171:3a7713b1edbc 14902 #define ETH_MACDBGR_RFFL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14903 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 14904 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
AnnaBridge 171:3a7713b1edbc 14905 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14906 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 14907 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
AnnaBridge 171:3a7713b1edbc 14908 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14909 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14910 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
AnnaBridge 171:3a7713b1edbc 14911 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14912 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14913 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
AnnaBridge 171:3a7713b1edbc 14914 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
AnnaBridge 171:3a7713b1edbc 14915 #define ETH_MACDBGR_RFRCS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14916 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 14917 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
AnnaBridge 171:3a7713b1edbc 14918 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14919 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 14920 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
AnnaBridge 171:3a7713b1edbc 14921 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14922 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14923 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
AnnaBridge 171:3a7713b1edbc 14924 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14925 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14926 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
AnnaBridge 171:3a7713b1edbc 14927 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
AnnaBridge 171:3a7713b1edbc 14928 #define ETH_MACDBGR_RFWRA_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14929 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14930 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
AnnaBridge 171:3a7713b1edbc 14931 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14932 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 14933 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
AnnaBridge 171:3a7713b1edbc 14934 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14935 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14936 #define ETH_MACDBGR_MMRPEA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14937 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14938 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
AnnaBridge 171:3a7713b1edbc 14939
AnnaBridge 171:3a7713b1edbc 14940 /* Bit definition for Ethernet MAC Status Register */
AnnaBridge 171:3a7713b1edbc 14941 #define ETH_MACSR_TSTS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14942 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14943 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
AnnaBridge 171:3a7713b1edbc 14944 #define ETH_MACSR_MMCTS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14945 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14946 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
AnnaBridge 171:3a7713b1edbc 14947 #define ETH_MACSR_MMMCRS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14948 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14949 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
AnnaBridge 171:3a7713b1edbc 14950 #define ETH_MACSR_MMCS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14951 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14952 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
AnnaBridge 171:3a7713b1edbc 14953 #define ETH_MACSR_PMTS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14954 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14955 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
AnnaBridge 171:3a7713b1edbc 14956
AnnaBridge 171:3a7713b1edbc 14957 /* Bit definition for Ethernet MAC Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 14958 #define ETH_MACIMR_TSTIM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14959 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14960 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
AnnaBridge 171:3a7713b1edbc 14961 #define ETH_MACIMR_PMTIM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14962 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14963 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
AnnaBridge 171:3a7713b1edbc 14964
AnnaBridge 171:3a7713b1edbc 14965 /* Bit definition for Ethernet MAC Address0 High Register */
AnnaBridge 171:3a7713b1edbc 14966 #define ETH_MACA0HR_MACA0H_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14967 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 14968 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
AnnaBridge 171:3a7713b1edbc 14969
AnnaBridge 171:3a7713b1edbc 14970 /* Bit definition for Ethernet MAC Address0 Low Register */
AnnaBridge 171:3a7713b1edbc 14971 #define ETH_MACA0LR_MACA0L_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14972 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 14973 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
AnnaBridge 171:3a7713b1edbc 14974
AnnaBridge 171:3a7713b1edbc 14975 /* Bit definition for Ethernet MAC Address1 High Register */
AnnaBridge 171:3a7713b1edbc 14976 #define ETH_MACA1HR_AE_Pos (31U)
AnnaBridge 171:3a7713b1edbc 14977 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 14978 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
AnnaBridge 171:3a7713b1edbc 14979 #define ETH_MACA1HR_SA_Pos (30U)
AnnaBridge 171:3a7713b1edbc 14980 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 14981 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
AnnaBridge 171:3a7713b1edbc 14982 #define ETH_MACA1HR_MBC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14983 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 171:3a7713b1edbc 14984 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
AnnaBridge 171:3a7713b1edbc 14985 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 171:3a7713b1edbc 14986 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 171:3a7713b1edbc 14987 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 171:3a7713b1edbc 14988 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 171:3a7713b1edbc 14989 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 171:3a7713b1edbc 14990 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
AnnaBridge 171:3a7713b1edbc 14991 #define ETH_MACA1HR_MACA1H_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14992 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 14993 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
AnnaBridge 171:3a7713b1edbc 14994
AnnaBridge 171:3a7713b1edbc 14995 /* Bit definition for Ethernet MAC Address1 Low Register */
AnnaBridge 171:3a7713b1edbc 14996 #define ETH_MACA1LR_MACA1L_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14997 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 14998 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
AnnaBridge 171:3a7713b1edbc 14999
AnnaBridge 171:3a7713b1edbc 15000 /* Bit definition for Ethernet MAC Address2 High Register */
AnnaBridge 171:3a7713b1edbc 15001 #define ETH_MACA2HR_AE_Pos (31U)
AnnaBridge 171:3a7713b1edbc 15002 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 15003 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
AnnaBridge 171:3a7713b1edbc 15004 #define ETH_MACA2HR_SA_Pos (30U)
AnnaBridge 171:3a7713b1edbc 15005 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 15006 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
AnnaBridge 171:3a7713b1edbc 15007 #define ETH_MACA2HR_MBC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 15008 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 171:3a7713b1edbc 15009 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
AnnaBridge 171:3a7713b1edbc 15010 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 171:3a7713b1edbc 15011 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 171:3a7713b1edbc 15012 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 171:3a7713b1edbc 15013 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 171:3a7713b1edbc 15014 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 171:3a7713b1edbc 15015 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 171:3a7713b1edbc 15016 #define ETH_MACA2HR_MACA2H_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15017 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 15018 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
AnnaBridge 171:3a7713b1edbc 15019
AnnaBridge 171:3a7713b1edbc 15020 /* Bit definition for Ethernet MAC Address2 Low Register */
AnnaBridge 171:3a7713b1edbc 15021 #define ETH_MACA2LR_MACA2L_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15022 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15023 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
AnnaBridge 171:3a7713b1edbc 15024
AnnaBridge 171:3a7713b1edbc 15025 /* Bit definition for Ethernet MAC Address3 High Register */
AnnaBridge 171:3a7713b1edbc 15026 #define ETH_MACA3HR_AE_Pos (31U)
AnnaBridge 171:3a7713b1edbc 15027 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 15028 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
AnnaBridge 171:3a7713b1edbc 15029 #define ETH_MACA3HR_SA_Pos (30U)
AnnaBridge 171:3a7713b1edbc 15030 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 15031 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
AnnaBridge 171:3a7713b1edbc 15032 #define ETH_MACA3HR_MBC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 15033 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 171:3a7713b1edbc 15034 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
AnnaBridge 171:3a7713b1edbc 15035 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 171:3a7713b1edbc 15036 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 171:3a7713b1edbc 15037 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 171:3a7713b1edbc 15038 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 171:3a7713b1edbc 15039 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 171:3a7713b1edbc 15040 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 171:3a7713b1edbc 15041 #define ETH_MACA3HR_MACA3H_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15042 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 15043 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
AnnaBridge 171:3a7713b1edbc 15044
AnnaBridge 171:3a7713b1edbc 15045 /* Bit definition for Ethernet MAC Address3 Low Register */
AnnaBridge 171:3a7713b1edbc 15046 #define ETH_MACA3LR_MACA3L_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15047 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15048 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
AnnaBridge 171:3a7713b1edbc 15049
AnnaBridge 171:3a7713b1edbc 15050 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15051 /* Ethernet MMC Registers bits definition */
AnnaBridge 171:3a7713b1edbc 15052 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15053
AnnaBridge 171:3a7713b1edbc 15054 /* Bit definition for Ethernet MMC Contol Register */
AnnaBridge 171:3a7713b1edbc 15055 #define ETH_MMCCR_MCFHP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15056 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15057 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
AnnaBridge 171:3a7713b1edbc 15058 #define ETH_MMCCR_MCP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15059 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15060 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
AnnaBridge 171:3a7713b1edbc 15061 #define ETH_MMCCR_MCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15062 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15063 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
AnnaBridge 171:3a7713b1edbc 15064 #define ETH_MMCCR_ROR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15065 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15066 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
AnnaBridge 171:3a7713b1edbc 15067 #define ETH_MMCCR_CSR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15068 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15069 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
AnnaBridge 171:3a7713b1edbc 15070 #define ETH_MMCCR_CR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15071 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15072 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
AnnaBridge 171:3a7713b1edbc 15073
AnnaBridge 171:3a7713b1edbc 15074 /* Bit definition for Ethernet MMC Receive Interrupt Register */
AnnaBridge 171:3a7713b1edbc 15075 #define ETH_MMCRIR_RGUFS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15076 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 15077 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15078 #define ETH_MMCRIR_RFAES_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15079 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15080 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15081 #define ETH_MMCRIR_RFCES_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15082 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15083 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15084
AnnaBridge 171:3a7713b1edbc 15085 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
AnnaBridge 171:3a7713b1edbc 15086 #define ETH_MMCTIR_TGFS_Pos (21U)
AnnaBridge 171:3a7713b1edbc 15087 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 15088 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15089 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 15090 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 15091 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15092 #define ETH_MMCTIR_TGFSCS_Pos (14U)
AnnaBridge 171:3a7713b1edbc 15093 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 15094 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15095
AnnaBridge 171:3a7713b1edbc 15096 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 15097 #define ETH_MMCRIMR_RGUFM_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15098 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 15099 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15100 #define ETH_MMCRIMR_RFAEM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15101 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15102 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15103 #define ETH_MMCRIMR_RFCEM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15104 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15105 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15106
AnnaBridge 171:3a7713b1edbc 15107 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 15108 #define ETH_MMCTIMR_TGFM_Pos (21U)
AnnaBridge 171:3a7713b1edbc 15109 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 15110 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15111 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
AnnaBridge 171:3a7713b1edbc 15112 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 15113 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15114 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 15115 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 15116 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
AnnaBridge 171:3a7713b1edbc 15117
AnnaBridge 171:3a7713b1edbc 15118 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
AnnaBridge 171:3a7713b1edbc 15119 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15120 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15121 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
AnnaBridge 171:3a7713b1edbc 15122
AnnaBridge 171:3a7713b1edbc 15123 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
AnnaBridge 171:3a7713b1edbc 15124 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15125 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15126 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
AnnaBridge 171:3a7713b1edbc 15127
AnnaBridge 171:3a7713b1edbc 15128 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
AnnaBridge 171:3a7713b1edbc 15129 #define ETH_MMCTGFCR_TGFC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15130 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15131 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
AnnaBridge 171:3a7713b1edbc 15132
AnnaBridge 171:3a7713b1edbc 15133 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
AnnaBridge 171:3a7713b1edbc 15134 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15135 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15136 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
AnnaBridge 171:3a7713b1edbc 15137
AnnaBridge 171:3a7713b1edbc 15138 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
AnnaBridge 171:3a7713b1edbc 15139 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15140 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15141 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
AnnaBridge 171:3a7713b1edbc 15142
AnnaBridge 171:3a7713b1edbc 15143 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
AnnaBridge 171:3a7713b1edbc 15144 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15145 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15146 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
AnnaBridge 171:3a7713b1edbc 15147
AnnaBridge 171:3a7713b1edbc 15148 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15149 /* Ethernet PTP Registers bits definition */
AnnaBridge 171:3a7713b1edbc 15150 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15151
AnnaBridge 171:3a7713b1edbc 15152 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
AnnaBridge 171:3a7713b1edbc 15153 #define ETH_PTPTSCR_TSCNT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 15154 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 15155 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
AnnaBridge 171:3a7713b1edbc 15156 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
AnnaBridge 171:3a7713b1edbc 15157 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 15158 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
AnnaBridge 171:3a7713b1edbc 15159 #define ETH_PTPTSSR_TSSEME_Pos (14U)
AnnaBridge 171:3a7713b1edbc 15160 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 15161 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
AnnaBridge 171:3a7713b1edbc 15162 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 15163 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 15164 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
AnnaBridge 171:3a7713b1edbc 15165 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 15166 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 15167 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
AnnaBridge 171:3a7713b1edbc 15168 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 15169 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 15170 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
AnnaBridge 171:3a7713b1edbc 15171 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
AnnaBridge 171:3a7713b1edbc 15172 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 15173 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
AnnaBridge 171:3a7713b1edbc 15174 #define ETH_PTPTSSR_TSSSR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15175 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15176 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
AnnaBridge 171:3a7713b1edbc 15177 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15178 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15179 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
AnnaBridge 171:3a7713b1edbc 15180
AnnaBridge 171:3a7713b1edbc 15181 #define ETH_PTPTSCR_TSARU_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15182 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15183 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
AnnaBridge 171:3a7713b1edbc 15184 #define ETH_PTPTSCR_TSITE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15185 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15186 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
AnnaBridge 171:3a7713b1edbc 15187 #define ETH_PTPTSCR_TSSTU_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15188 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15189 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
AnnaBridge 171:3a7713b1edbc 15190 #define ETH_PTPTSCR_TSSTI_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15191 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15192 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
AnnaBridge 171:3a7713b1edbc 15193 #define ETH_PTPTSCR_TSFCU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15194 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15195 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
AnnaBridge 171:3a7713b1edbc 15196 #define ETH_PTPTSCR_TSE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15197 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15198 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
AnnaBridge 171:3a7713b1edbc 15199
AnnaBridge 171:3a7713b1edbc 15200 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
AnnaBridge 171:3a7713b1edbc 15201 #define ETH_PTPSSIR_STSSI_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15202 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 15203 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
AnnaBridge 171:3a7713b1edbc 15204
AnnaBridge 171:3a7713b1edbc 15205 /* Bit definition for Ethernet PTP Time Stamp High Register */
AnnaBridge 171:3a7713b1edbc 15206 #define ETH_PTPTSHR_STS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15207 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15208 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
AnnaBridge 171:3a7713b1edbc 15209
AnnaBridge 171:3a7713b1edbc 15210 /* Bit definition for Ethernet PTP Time Stamp Low Register */
AnnaBridge 171:3a7713b1edbc 15211 #define ETH_PTPTSLR_STPNS_Pos (31U)
AnnaBridge 171:3a7713b1edbc 15212 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 15213 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
AnnaBridge 171:3a7713b1edbc 15214 #define ETH_PTPTSLR_STSS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15215 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 171:3a7713b1edbc 15216 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
AnnaBridge 171:3a7713b1edbc 15217
AnnaBridge 171:3a7713b1edbc 15218 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
AnnaBridge 171:3a7713b1edbc 15219 #define ETH_PTPTSHUR_TSUS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15220 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15221 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
AnnaBridge 171:3a7713b1edbc 15222
AnnaBridge 171:3a7713b1edbc 15223 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
AnnaBridge 171:3a7713b1edbc 15224 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
AnnaBridge 171:3a7713b1edbc 15225 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 15226 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
AnnaBridge 171:3a7713b1edbc 15227 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15228 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 171:3a7713b1edbc 15229 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
AnnaBridge 171:3a7713b1edbc 15230
AnnaBridge 171:3a7713b1edbc 15231 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
AnnaBridge 171:3a7713b1edbc 15232 #define ETH_PTPTSAR_TSA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15233 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15234 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
AnnaBridge 171:3a7713b1edbc 15235
AnnaBridge 171:3a7713b1edbc 15236 /* Bit definition for Ethernet PTP Target Time High Register */
AnnaBridge 171:3a7713b1edbc 15237 #define ETH_PTPTTHR_TTSH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15238 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15239 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
AnnaBridge 171:3a7713b1edbc 15240
AnnaBridge 171:3a7713b1edbc 15241 /* Bit definition for Ethernet PTP Target Time Low Register */
AnnaBridge 171:3a7713b1edbc 15242 #define ETH_PTPTTLR_TTSL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15243 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15244 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
AnnaBridge 171:3a7713b1edbc 15245
AnnaBridge 171:3a7713b1edbc 15246 /* Bit definition for Ethernet PTP Time Stamp Status Register */
AnnaBridge 171:3a7713b1edbc 15247 #define ETH_PTPTSSR_TSTTR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15248 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15249 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
AnnaBridge 171:3a7713b1edbc 15250 #define ETH_PTPTSSR_TSSO_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15251 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15252 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
AnnaBridge 171:3a7713b1edbc 15253
AnnaBridge 171:3a7713b1edbc 15254 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15255 /* Ethernet DMA Registers bits definition */
AnnaBridge 171:3a7713b1edbc 15256 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15257
AnnaBridge 171:3a7713b1edbc 15258 /* Bit definition for Ethernet DMA Bus Mode Register */
AnnaBridge 171:3a7713b1edbc 15259 #define ETH_DMABMR_AAB_Pos (25U)
AnnaBridge 171:3a7713b1edbc 15260 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 15261 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
AnnaBridge 171:3a7713b1edbc 15262 #define ETH_DMABMR_FPM_Pos (24U)
AnnaBridge 171:3a7713b1edbc 15263 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 15264 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
AnnaBridge 171:3a7713b1edbc 15265 #define ETH_DMABMR_USP_Pos (23U)
AnnaBridge 171:3a7713b1edbc 15266 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 15267 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
AnnaBridge 171:3a7713b1edbc 15268 #define ETH_DMABMR_RDP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15269 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
AnnaBridge 171:3a7713b1edbc 15270 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
AnnaBridge 171:3a7713b1edbc 15271 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
AnnaBridge 171:3a7713b1edbc 15272 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
AnnaBridge 171:3a7713b1edbc 15273 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 171:3a7713b1edbc 15274 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 171:3a7713b1edbc 15275 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 171:3a7713b1edbc 15276 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 171:3a7713b1edbc 15277 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 171:3a7713b1edbc 15278 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 171:3a7713b1edbc 15279 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 171:3a7713b1edbc 15280 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 171:3a7713b1edbc 15281 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
AnnaBridge 171:3a7713b1edbc 15282 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
AnnaBridge 171:3a7713b1edbc 15283 #define ETH_DMABMR_FB_Pos (16U)
AnnaBridge 171:3a7713b1edbc 15284 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 15285 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
AnnaBridge 171:3a7713b1edbc 15286 #define ETH_DMABMR_RTPR_Pos (14U)
AnnaBridge 171:3a7713b1edbc 15287 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 15288 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
AnnaBridge 171:3a7713b1edbc 15289 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
AnnaBridge 171:3a7713b1edbc 15290 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
AnnaBridge 171:3a7713b1edbc 15291 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
AnnaBridge 171:3a7713b1edbc 15292 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
AnnaBridge 171:3a7713b1edbc 15293 #define ETH_DMABMR_PBL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15294 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
AnnaBridge 171:3a7713b1edbc 15295 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
AnnaBridge 171:3a7713b1edbc 15296 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
AnnaBridge 171:3a7713b1edbc 15297 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
AnnaBridge 171:3a7713b1edbc 15298 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 171:3a7713b1edbc 15299 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 171:3a7713b1edbc 15300 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 171:3a7713b1edbc 15301 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 171:3a7713b1edbc 15302 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 171:3a7713b1edbc 15303 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 171:3a7713b1edbc 15304 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 171:3a7713b1edbc 15305 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 171:3a7713b1edbc 15306 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
AnnaBridge 171:3a7713b1edbc 15307 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
AnnaBridge 171:3a7713b1edbc 15308 #define ETH_DMABMR_EDE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 15309 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15310 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
AnnaBridge 171:3a7713b1edbc 15311 #define ETH_DMABMR_DSL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15312 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
AnnaBridge 171:3a7713b1edbc 15313 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
AnnaBridge 171:3a7713b1edbc 15314 #define ETH_DMABMR_DA_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15315 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15316 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
AnnaBridge 171:3a7713b1edbc 15317 #define ETH_DMABMR_SR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15318 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15319 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
AnnaBridge 171:3a7713b1edbc 15320
AnnaBridge 171:3a7713b1edbc 15321 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
AnnaBridge 171:3a7713b1edbc 15322 #define ETH_DMATPDR_TPD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15323 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15324 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
AnnaBridge 171:3a7713b1edbc 15325
AnnaBridge 171:3a7713b1edbc 15326 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
AnnaBridge 171:3a7713b1edbc 15327 #define ETH_DMARPDR_RPD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15328 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15329 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
AnnaBridge 171:3a7713b1edbc 15330
AnnaBridge 171:3a7713b1edbc 15331 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
AnnaBridge 171:3a7713b1edbc 15332 #define ETH_DMARDLAR_SRL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15333 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15334 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
AnnaBridge 171:3a7713b1edbc 15335
AnnaBridge 171:3a7713b1edbc 15336 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
AnnaBridge 171:3a7713b1edbc 15337 #define ETH_DMATDLAR_STL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15338 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15339 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
AnnaBridge 171:3a7713b1edbc 15340
AnnaBridge 171:3a7713b1edbc 15341 /* Bit definition for Ethernet DMA Status Register */
AnnaBridge 171:3a7713b1edbc 15342 #define ETH_DMASR_TSTS_Pos (29U)
AnnaBridge 171:3a7713b1edbc 15343 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 15344 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
AnnaBridge 171:3a7713b1edbc 15345 #define ETH_DMASR_PMTS_Pos (28U)
AnnaBridge 171:3a7713b1edbc 15346 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 15347 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
AnnaBridge 171:3a7713b1edbc 15348 #define ETH_DMASR_MMCS_Pos (27U)
AnnaBridge 171:3a7713b1edbc 15349 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 15350 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
AnnaBridge 171:3a7713b1edbc 15351 #define ETH_DMASR_EBS_Pos (23U)
AnnaBridge 171:3a7713b1edbc 15352 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
AnnaBridge 171:3a7713b1edbc 15353 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
AnnaBridge 171:3a7713b1edbc 15354 /* combination with EBS[2:0] for GetFlagStatus function */
AnnaBridge 171:3a7713b1edbc 15355 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
AnnaBridge 171:3a7713b1edbc 15356 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 15357 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
AnnaBridge 171:3a7713b1edbc 15358 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
AnnaBridge 171:3a7713b1edbc 15359 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 15360 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
AnnaBridge 171:3a7713b1edbc 15361 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
AnnaBridge 171:3a7713b1edbc 15362 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 15363 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
AnnaBridge 171:3a7713b1edbc 15364 #define ETH_DMASR_TPS_Pos (20U)
AnnaBridge 171:3a7713b1edbc 15365 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
AnnaBridge 171:3a7713b1edbc 15366 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
AnnaBridge 171:3a7713b1edbc 15367 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
AnnaBridge 171:3a7713b1edbc 15368 #define ETH_DMASR_TPS_Fetching_Pos (20U)
AnnaBridge 171:3a7713b1edbc 15369 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 15370 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
AnnaBridge 171:3a7713b1edbc 15371 #define ETH_DMASR_TPS_Waiting_Pos (21U)
AnnaBridge 171:3a7713b1edbc 15372 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 15373 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
AnnaBridge 171:3a7713b1edbc 15374 #define ETH_DMASR_TPS_Reading_Pos (20U)
AnnaBridge 171:3a7713b1edbc 15375 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 15376 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
AnnaBridge 171:3a7713b1edbc 15377 #define ETH_DMASR_TPS_Suspended_Pos (21U)
AnnaBridge 171:3a7713b1edbc 15378 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 15379 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
AnnaBridge 171:3a7713b1edbc 15380 #define ETH_DMASR_TPS_Closing_Pos (20U)
AnnaBridge 171:3a7713b1edbc 15381 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
AnnaBridge 171:3a7713b1edbc 15382 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
AnnaBridge 171:3a7713b1edbc 15383 #define ETH_DMASR_RPS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15384 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 15385 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
AnnaBridge 171:3a7713b1edbc 15386 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
AnnaBridge 171:3a7713b1edbc 15387 #define ETH_DMASR_RPS_Fetching_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15388 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 15389 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
AnnaBridge 171:3a7713b1edbc 15390 #define ETH_DMASR_RPS_Waiting_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15391 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
AnnaBridge 171:3a7713b1edbc 15392 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
AnnaBridge 171:3a7713b1edbc 15393 #define ETH_DMASR_RPS_Suspended_Pos (19U)
AnnaBridge 171:3a7713b1edbc 15394 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 15395 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
AnnaBridge 171:3a7713b1edbc 15396 #define ETH_DMASR_RPS_Closing_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15397 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
AnnaBridge 171:3a7713b1edbc 15398 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
AnnaBridge 171:3a7713b1edbc 15399 #define ETH_DMASR_RPS_Queuing_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15400 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 15401 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
AnnaBridge 171:3a7713b1edbc 15402 #define ETH_DMASR_NIS_Pos (16U)
AnnaBridge 171:3a7713b1edbc 15403 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 15404 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
AnnaBridge 171:3a7713b1edbc 15405 #define ETH_DMASR_AIS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 15406 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 15407 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
AnnaBridge 171:3a7713b1edbc 15408 #define ETH_DMASR_ERS_Pos (14U)
AnnaBridge 171:3a7713b1edbc 15409 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 15410 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
AnnaBridge 171:3a7713b1edbc 15411 #define ETH_DMASR_FBES_Pos (13U)
AnnaBridge 171:3a7713b1edbc 15412 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 15413 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
AnnaBridge 171:3a7713b1edbc 15414 #define ETH_DMASR_ETS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 15415 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 15416 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
AnnaBridge 171:3a7713b1edbc 15417 #define ETH_DMASR_RWTS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15418 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15419 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
AnnaBridge 171:3a7713b1edbc 15420 #define ETH_DMASR_RPSS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15421 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15422 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
AnnaBridge 171:3a7713b1edbc 15423 #define ETH_DMASR_RBUS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 15424 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15425 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
AnnaBridge 171:3a7713b1edbc 15426 #define ETH_DMASR_RS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15427 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15428 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
AnnaBridge 171:3a7713b1edbc 15429 #define ETH_DMASR_TUS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15430 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15431 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
AnnaBridge 171:3a7713b1edbc 15432 #define ETH_DMASR_ROS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15433 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15434 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
AnnaBridge 171:3a7713b1edbc 15435 #define ETH_DMASR_TJTS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15436 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15437 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
AnnaBridge 171:3a7713b1edbc 15438 #define ETH_DMASR_TBUS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15439 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15440 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
AnnaBridge 171:3a7713b1edbc 15441 #define ETH_DMASR_TPSS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15442 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15443 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
AnnaBridge 171:3a7713b1edbc 15444 #define ETH_DMASR_TS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15445 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15446 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
AnnaBridge 171:3a7713b1edbc 15447
AnnaBridge 171:3a7713b1edbc 15448 /* Bit definition for Ethernet DMA Operation Mode Register */
AnnaBridge 171:3a7713b1edbc 15449 #define ETH_DMAOMR_DTCEFD_Pos (26U)
AnnaBridge 171:3a7713b1edbc 15450 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 15451 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
AnnaBridge 171:3a7713b1edbc 15452 #define ETH_DMAOMR_RSF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 15453 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 15454 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
AnnaBridge 171:3a7713b1edbc 15455 #define ETH_DMAOMR_DFRF_Pos (24U)
AnnaBridge 171:3a7713b1edbc 15456 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 15457 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
AnnaBridge 171:3a7713b1edbc 15458 #define ETH_DMAOMR_TSF_Pos (21U)
AnnaBridge 171:3a7713b1edbc 15459 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 15460 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
AnnaBridge 171:3a7713b1edbc 15461 #define ETH_DMAOMR_FTF_Pos (20U)
AnnaBridge 171:3a7713b1edbc 15462 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 15463 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
AnnaBridge 171:3a7713b1edbc 15464 #define ETH_DMAOMR_TTC_Pos (14U)
AnnaBridge 171:3a7713b1edbc 15465 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
AnnaBridge 171:3a7713b1edbc 15466 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
AnnaBridge 171:3a7713b1edbc 15467 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
AnnaBridge 171:3a7713b1edbc 15468 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
AnnaBridge 171:3a7713b1edbc 15469 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
AnnaBridge 171:3a7713b1edbc 15470 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
AnnaBridge 171:3a7713b1edbc 15471 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
AnnaBridge 171:3a7713b1edbc 15472 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
AnnaBridge 171:3a7713b1edbc 15473 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
AnnaBridge 171:3a7713b1edbc 15474 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
AnnaBridge 171:3a7713b1edbc 15475 #define ETH_DMAOMR_ST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 15476 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 15477 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
AnnaBridge 171:3a7713b1edbc 15478 #define ETH_DMAOMR_FEF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 15479 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15480 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
AnnaBridge 171:3a7713b1edbc 15481 #define ETH_DMAOMR_FUGF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15482 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15483 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
AnnaBridge 171:3a7713b1edbc 15484 #define ETH_DMAOMR_RTC_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15485 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 15486 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
AnnaBridge 171:3a7713b1edbc 15487 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
AnnaBridge 171:3a7713b1edbc 15488 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
AnnaBridge 171:3a7713b1edbc 15489 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
AnnaBridge 171:3a7713b1edbc 15490 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
AnnaBridge 171:3a7713b1edbc 15491 #define ETH_DMAOMR_OSF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15492 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15493 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
AnnaBridge 171:3a7713b1edbc 15494 #define ETH_DMAOMR_SR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15495 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15496 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
AnnaBridge 171:3a7713b1edbc 15497
AnnaBridge 171:3a7713b1edbc 15498 /* Bit definition for Ethernet DMA Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 15499 #define ETH_DMAIER_NISE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 15500 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 15501 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
AnnaBridge 171:3a7713b1edbc 15502 #define ETH_DMAIER_AISE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 15503 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 15504 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
AnnaBridge 171:3a7713b1edbc 15505 #define ETH_DMAIER_ERIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 15506 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 15507 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
AnnaBridge 171:3a7713b1edbc 15508 #define ETH_DMAIER_FBEIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 15509 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 15510 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
AnnaBridge 171:3a7713b1edbc 15511 #define ETH_DMAIER_ETIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 15512 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 15513 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
AnnaBridge 171:3a7713b1edbc 15514 #define ETH_DMAIER_RWTIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15515 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15516 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
AnnaBridge 171:3a7713b1edbc 15517 #define ETH_DMAIER_RPSIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15518 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15519 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
AnnaBridge 171:3a7713b1edbc 15520 #define ETH_DMAIER_RBUIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 15521 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15522 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
AnnaBridge 171:3a7713b1edbc 15523 #define ETH_DMAIER_RIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15524 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15525 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
AnnaBridge 171:3a7713b1edbc 15526 #define ETH_DMAIER_TUIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15527 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15528 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
AnnaBridge 171:3a7713b1edbc 15529 #define ETH_DMAIER_ROIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15530 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15531 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
AnnaBridge 171:3a7713b1edbc 15532 #define ETH_DMAIER_TJTIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15533 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15534 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
AnnaBridge 171:3a7713b1edbc 15535 #define ETH_DMAIER_TBUIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15536 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15537 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
AnnaBridge 171:3a7713b1edbc 15538 #define ETH_DMAIER_TPSIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15539 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15540 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
AnnaBridge 171:3a7713b1edbc 15541 #define ETH_DMAIER_TIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15542 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15543 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
AnnaBridge 171:3a7713b1edbc 15544
AnnaBridge 171:3a7713b1edbc 15545 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
AnnaBridge 171:3a7713b1edbc 15546 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
AnnaBridge 171:3a7713b1edbc 15547 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 15548 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
AnnaBridge 171:3a7713b1edbc 15549 #define ETH_DMAMFBOCR_MFA_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15550 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
AnnaBridge 171:3a7713b1edbc 15551 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
AnnaBridge 171:3a7713b1edbc 15552 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 15553 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 15554 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
AnnaBridge 171:3a7713b1edbc 15555 #define ETH_DMAMFBOCR_MFC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15556 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 15557 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
AnnaBridge 171:3a7713b1edbc 15558
AnnaBridge 171:3a7713b1edbc 15559 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
AnnaBridge 171:3a7713b1edbc 15560 #define ETH_DMACHTDR_HTDAP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15561 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15562 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
AnnaBridge 171:3a7713b1edbc 15563
AnnaBridge 171:3a7713b1edbc 15564 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
AnnaBridge 171:3a7713b1edbc 15565 #define ETH_DMACHRDR_HRDAP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15566 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15567 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
AnnaBridge 171:3a7713b1edbc 15568
AnnaBridge 171:3a7713b1edbc 15569 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
AnnaBridge 171:3a7713b1edbc 15570 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15571 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15572 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
AnnaBridge 171:3a7713b1edbc 15573
AnnaBridge 171:3a7713b1edbc 15574 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
AnnaBridge 171:3a7713b1edbc 15575 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15576 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 15577 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
AnnaBridge 171:3a7713b1edbc 15578
AnnaBridge 171:3a7713b1edbc 15579 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15580 /* */
AnnaBridge 171:3a7713b1edbc 15581 /* USB_OTG */
AnnaBridge 171:3a7713b1edbc 15582 /* */
AnnaBridge 171:3a7713b1edbc 15583 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15584 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
AnnaBridge 171:3a7713b1edbc 15585 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15586 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15587 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
AnnaBridge 171:3a7713b1edbc 15588 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15589 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15590 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
AnnaBridge 171:3a7713b1edbc 15591 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15592 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15593 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
AnnaBridge 171:3a7713b1edbc 15594 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15595 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15596 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
AnnaBridge 171:3a7713b1edbc 15597 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15598 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15599 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
AnnaBridge 171:3a7713b1edbc 15600 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15601 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15602 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
AnnaBridge 171:3a7713b1edbc 15603 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15604 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15605 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
AnnaBridge 171:3a7713b1edbc 15606 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
AnnaBridge 171:3a7713b1edbc 15607 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15608 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
AnnaBridge 171:3a7713b1edbc 15609 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15610 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15611 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
AnnaBridge 171:3a7713b1edbc 15612 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15613 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15614 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
AnnaBridge 171:3a7713b1edbc 15615 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 15616 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 15617 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
AnnaBridge 171:3a7713b1edbc 15618 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 15619 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 15620 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
AnnaBridge 171:3a7713b1edbc 15621 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 15622 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 15623 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
AnnaBridge 171:3a7713b1edbc 15624 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
AnnaBridge 171:3a7713b1edbc 15625 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 15626 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
AnnaBridge 171:3a7713b1edbc 15627 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15628 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 15629 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
AnnaBridge 171:3a7713b1edbc 15630 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
AnnaBridge 171:3a7713b1edbc 15631 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 15632 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
AnnaBridge 171:3a7713b1edbc 15633 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
AnnaBridge 171:3a7713b1edbc 15634 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 15635 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
AnnaBridge 171:3a7713b1edbc 15636 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
AnnaBridge 171:3a7713b1edbc 15637 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 15638 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
AnnaBridge 171:3a7713b1edbc 15639
AnnaBridge 171:3a7713b1edbc 15640 /******************** Bit definition for USB_OTG_HCFG register ********************/
AnnaBridge 171:3a7713b1edbc 15641 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15642 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 15643 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
AnnaBridge 171:3a7713b1edbc 15644 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15645 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15646 #define USB_OTG_HCFG_FSLSS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15647 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15648 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
AnnaBridge 171:3a7713b1edbc 15649
AnnaBridge 171:3a7713b1edbc 15650 /******************** Bit definition for USB_OTG_DCFG register ********************/
AnnaBridge 171:3a7713b1edbc 15651 #define USB_OTG_DCFG_DSPD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15652 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 15653 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
AnnaBridge 171:3a7713b1edbc 15654 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15655 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15656 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15657 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15658 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
AnnaBridge 171:3a7713b1edbc 15659
AnnaBridge 171:3a7713b1edbc 15660 #define USB_OTG_DCFG_DAD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15661 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
AnnaBridge 171:3a7713b1edbc 15662 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
AnnaBridge 171:3a7713b1edbc 15663 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15664 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15665 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15666 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15667 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15668 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15669 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 15670
AnnaBridge 171:3a7713b1edbc 15671 #define USB_OTG_DCFG_PFIVL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 15672 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 15673 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
AnnaBridge 171:3a7713b1edbc 15674 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 15675 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 15676
AnnaBridge 171:3a7713b1edbc 15677 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 15678 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 15679 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
AnnaBridge 171:3a7713b1edbc 15680 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 15681 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 15682
AnnaBridge 171:3a7713b1edbc 15683 /******************** Bit definition for USB_OTG_PCGCR register ********************/
AnnaBridge 171:3a7713b1edbc 15684 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15685 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15686 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
AnnaBridge 171:3a7713b1edbc 15687 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15688 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15689 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
AnnaBridge 171:3a7713b1edbc 15690 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15691 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15692 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
AnnaBridge 171:3a7713b1edbc 15693
AnnaBridge 171:3a7713b1edbc 15694 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
AnnaBridge 171:3a7713b1edbc 15695 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15696 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15697 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
AnnaBridge 171:3a7713b1edbc 15698 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15699 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15700 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
AnnaBridge 171:3a7713b1edbc 15701 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15702 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15703 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
AnnaBridge 171:3a7713b1edbc 15704 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15705 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 15706 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
AnnaBridge 171:3a7713b1edbc 15707 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
AnnaBridge 171:3a7713b1edbc 15708 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 15709 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
AnnaBridge 171:3a7713b1edbc 15710 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 15711 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 15712 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
AnnaBridge 171:3a7713b1edbc 15713 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
AnnaBridge 171:3a7713b1edbc 15714 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 15715 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
AnnaBridge 171:3a7713b1edbc 15716
AnnaBridge 171:3a7713b1edbc 15717 /******************** Bit definition for USB_OTG_DCTL register ********************/
AnnaBridge 171:3a7713b1edbc 15718 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15719 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15720 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
AnnaBridge 171:3a7713b1edbc 15721 #define USB_OTG_DCTL_SDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15722 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15723 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
AnnaBridge 171:3a7713b1edbc 15724 #define USB_OTG_DCTL_GINSTS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15725 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15726 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
AnnaBridge 171:3a7713b1edbc 15727 #define USB_OTG_DCTL_GONSTS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15728 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15729 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
AnnaBridge 171:3a7713b1edbc 15730
AnnaBridge 171:3a7713b1edbc 15731 #define USB_OTG_DCTL_TCTL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15732 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 15733 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
AnnaBridge 171:3a7713b1edbc 15734 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15735 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15736 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15737 #define USB_OTG_DCTL_SGINAK_Pos (7U)
AnnaBridge 171:3a7713b1edbc 15738 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15739 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
AnnaBridge 171:3a7713b1edbc 15740 #define USB_OTG_DCTL_CGINAK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15741 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15742 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
AnnaBridge 171:3a7713b1edbc 15743 #define USB_OTG_DCTL_SGONAK_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15744 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15745 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
AnnaBridge 171:3a7713b1edbc 15746 #define USB_OTG_DCTL_CGONAK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 15747 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 15748 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
AnnaBridge 171:3a7713b1edbc 15749 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 15750 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 15751 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
AnnaBridge 171:3a7713b1edbc 15752
AnnaBridge 171:3a7713b1edbc 15753 /******************** Bit definition for USB_OTG_HFIR register ********************/
AnnaBridge 171:3a7713b1edbc 15754 #define USB_OTG_HFIR_FRIVL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15755 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 15756 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
AnnaBridge 171:3a7713b1edbc 15757
AnnaBridge 171:3a7713b1edbc 15758 /******************** Bit definition for USB_OTG_HFNUM register ********************/
AnnaBridge 171:3a7713b1edbc 15759 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15760 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 15761 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
AnnaBridge 171:3a7713b1edbc 15762 #define USB_OTG_HFNUM_FTREM_Pos (16U)
AnnaBridge 171:3a7713b1edbc 15763 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 15764 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
AnnaBridge 171:3a7713b1edbc 15765
AnnaBridge 171:3a7713b1edbc 15766 /******************** Bit definition for USB_OTG_DSTS register ********************/
AnnaBridge 171:3a7713b1edbc 15767 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15768 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15769 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
AnnaBridge 171:3a7713b1edbc 15770
AnnaBridge 171:3a7713b1edbc 15771 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15772 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 15773 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
AnnaBridge 171:3a7713b1edbc 15774 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15775 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15776 #define USB_OTG_DSTS_EERR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15777 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15778 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
AnnaBridge 171:3a7713b1edbc 15779 #define USB_OTG_DSTS_FNSOF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15780 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
AnnaBridge 171:3a7713b1edbc 15781 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
AnnaBridge 171:3a7713b1edbc 15782
AnnaBridge 171:3a7713b1edbc 15783 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
AnnaBridge 171:3a7713b1edbc 15784 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15785 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15786 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
AnnaBridge 171:3a7713b1edbc 15787 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15788 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
AnnaBridge 171:3a7713b1edbc 15789 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
AnnaBridge 171:3a7713b1edbc 15790 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
AnnaBridge 171:3a7713b1edbc 15791 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
AnnaBridge 171:3a7713b1edbc 15792 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
AnnaBridge 171:3a7713b1edbc 15793 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
AnnaBridge 171:3a7713b1edbc 15794 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
AnnaBridge 171:3a7713b1edbc 15795 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15796 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15797 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
AnnaBridge 171:3a7713b1edbc 15798 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
AnnaBridge 171:3a7713b1edbc 15799 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15800 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
AnnaBridge 171:3a7713b1edbc 15801 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15802 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15803 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
AnnaBridge 171:3a7713b1edbc 15804
AnnaBridge 171:3a7713b1edbc 15805 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
AnnaBridge 171:3a7713b1edbc 15806 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15807 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 15808 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
AnnaBridge 171:3a7713b1edbc 15809 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15810 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15811 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15812 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15813 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15814 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 171:3a7713b1edbc 15815 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15816 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15817 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
AnnaBridge 171:3a7713b1edbc 15818 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15819 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15820 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
AnnaBridge 171:3a7713b1edbc 15821 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
AnnaBridge 171:3a7713b1edbc 15822 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
AnnaBridge 171:3a7713b1edbc 15823 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
AnnaBridge 171:3a7713b1edbc 15824 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 15825 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 15826 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 15827 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 15828 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 15829 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 15830 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
AnnaBridge 171:3a7713b1edbc 15831 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 15832 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 15833 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
AnnaBridge 171:3a7713b1edbc 15834 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
AnnaBridge 171:3a7713b1edbc 15835 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 15836 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
AnnaBridge 171:3a7713b1edbc 15837 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
AnnaBridge 171:3a7713b1edbc 15838 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 15839 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
AnnaBridge 171:3a7713b1edbc 15840 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
AnnaBridge 171:3a7713b1edbc 15841 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 15842 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
AnnaBridge 171:3a7713b1edbc 15843 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
AnnaBridge 171:3a7713b1edbc 15844 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 15845 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
AnnaBridge 171:3a7713b1edbc 15846 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
AnnaBridge 171:3a7713b1edbc 15847 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 15848 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
AnnaBridge 171:3a7713b1edbc 15849 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
AnnaBridge 171:3a7713b1edbc 15850 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 15851 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
AnnaBridge 171:3a7713b1edbc 15852 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
AnnaBridge 171:3a7713b1edbc 15853 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 15854 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
AnnaBridge 171:3a7713b1edbc 15855 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
AnnaBridge 171:3a7713b1edbc 15856 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 15857 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
AnnaBridge 171:3a7713b1edbc 15858 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
AnnaBridge 171:3a7713b1edbc 15859 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 15860 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
AnnaBridge 171:3a7713b1edbc 15861 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
AnnaBridge 171:3a7713b1edbc 15862 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 15863 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
AnnaBridge 171:3a7713b1edbc 15864 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
AnnaBridge 171:3a7713b1edbc 15865 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 15866 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
AnnaBridge 171:3a7713b1edbc 15867
AnnaBridge 171:3a7713b1edbc 15868 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
AnnaBridge 171:3a7713b1edbc 15869 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15870 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15871 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
AnnaBridge 171:3a7713b1edbc 15872 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15873 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15874 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
AnnaBridge 171:3a7713b1edbc 15875 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15876 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15877 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
AnnaBridge 171:3a7713b1edbc 15878 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15879 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15880 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
AnnaBridge 171:3a7713b1edbc 15881 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15882 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15883 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
AnnaBridge 171:3a7713b1edbc 15884 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15885 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 15886 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 171:3a7713b1edbc 15887 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15888 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 15889 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15890 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15891 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 15892 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
AnnaBridge 171:3a7713b1edbc 15893 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 15894 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
AnnaBridge 171:3a7713b1edbc 15895 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
AnnaBridge 171:3a7713b1edbc 15896 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 15897 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
AnnaBridge 171:3a7713b1edbc 15898
AnnaBridge 171:3a7713b1edbc 15899 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
AnnaBridge 171:3a7713b1edbc 15900 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15901 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15902 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 171:3a7713b1edbc 15903 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15904 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15905 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 171:3a7713b1edbc 15906 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15907 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15908 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 171:3a7713b1edbc 15909 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15910 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15911 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 171:3a7713b1edbc 15912 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15913 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15914 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 171:3a7713b1edbc 15915 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15916 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15917 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 171:3a7713b1edbc 15918 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15919 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15920 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 171:3a7713b1edbc 15921 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15922 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15923 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 171:3a7713b1edbc 15924
AnnaBridge 171:3a7713b1edbc 15925 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
AnnaBridge 171:3a7713b1edbc 15926 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15927 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 15928 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
AnnaBridge 171:3a7713b1edbc 15929 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 15930 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 15931 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
AnnaBridge 171:3a7713b1edbc 15932 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 15933 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 15934 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 15935 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 15936 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 15937 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 15938 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 15939 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 15940
AnnaBridge 171:3a7713b1edbc 15941 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
AnnaBridge 171:3a7713b1edbc 15942 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 15943 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
AnnaBridge 171:3a7713b1edbc 15944 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 15945 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 15946 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 15947 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 15948 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 15949 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 15950 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 15951 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 15952
AnnaBridge 171:3a7713b1edbc 15953 /******************** Bit definition for USB_OTG_HAINT register ********************/
AnnaBridge 171:3a7713b1edbc 15954 #define USB_OTG_HAINT_HAINT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15955 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 15956 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
AnnaBridge 171:3a7713b1edbc 15957
AnnaBridge 171:3a7713b1edbc 15958 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
AnnaBridge 171:3a7713b1edbc 15959 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15960 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15961 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 171:3a7713b1edbc 15962 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15963 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15964 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 171:3a7713b1edbc 15965 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15966 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15967 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
AnnaBridge 171:3a7713b1edbc 15968 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15969 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15970 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
AnnaBridge 171:3a7713b1edbc 15971 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 15972 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 15973 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
AnnaBridge 171:3a7713b1edbc 15974 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 15975 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 15976 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
AnnaBridge 171:3a7713b1edbc 15977 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 15978 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 15979 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
AnnaBridge 171:3a7713b1edbc 15980 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 15981 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 15982 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
AnnaBridge 171:3a7713b1edbc 15983
AnnaBridge 171:3a7713b1edbc 15984 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
AnnaBridge 171:3a7713b1edbc 15985 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 15986 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 15987 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
AnnaBridge 171:3a7713b1edbc 15988 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 15989 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 15990 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
AnnaBridge 171:3a7713b1edbc 15991 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 15992 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 15993 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
AnnaBridge 171:3a7713b1edbc 15994 #define USB_OTG_GINTSTS_SOF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 15995 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 15996 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
AnnaBridge 171:3a7713b1edbc 15997 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 15998 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 15999 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
AnnaBridge 171:3a7713b1edbc 16000 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 16001 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16002 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
AnnaBridge 171:3a7713b1edbc 16003 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16004 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16005 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
AnnaBridge 171:3a7713b1edbc 16006 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 16007 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16008 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
AnnaBridge 171:3a7713b1edbc 16009 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 16010 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 16011 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
AnnaBridge 171:3a7713b1edbc 16012 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 16013 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 16014 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
AnnaBridge 171:3a7713b1edbc 16015 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 16016 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 16017 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
AnnaBridge 171:3a7713b1edbc 16018 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 16019 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 16020 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
AnnaBridge 171:3a7713b1edbc 16021 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 16022 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 16023 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 171:3a7713b1edbc 16024 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16025 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16026 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
AnnaBridge 171:3a7713b1edbc 16027 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
AnnaBridge 171:3a7713b1edbc 16028 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16029 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
AnnaBridge 171:3a7713b1edbc 16030 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 16031 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16032 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
AnnaBridge 171:3a7713b1edbc 16033 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
AnnaBridge 171:3a7713b1edbc 16034 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 16035 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
AnnaBridge 171:3a7713b1edbc 16036 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 16037 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16038 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
AnnaBridge 171:3a7713b1edbc 16039 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
AnnaBridge 171:3a7713b1edbc 16040 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 16041 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
AnnaBridge 171:3a7713b1edbc 16042 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
AnnaBridge 171:3a7713b1edbc 16043 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16044 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
AnnaBridge 171:3a7713b1edbc 16045 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
AnnaBridge 171:3a7713b1edbc 16046 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16047 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
AnnaBridge 171:3a7713b1edbc 16048 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
AnnaBridge 171:3a7713b1edbc 16049 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 16050 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
AnnaBridge 171:3a7713b1edbc 16051 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 16052 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 16053 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
AnnaBridge 171:3a7713b1edbc 16054 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
AnnaBridge 171:3a7713b1edbc 16055 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 16056 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
AnnaBridge 171:3a7713b1edbc 16057 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
AnnaBridge 171:3a7713b1edbc 16058 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 16059 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
AnnaBridge 171:3a7713b1edbc 16060 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
AnnaBridge 171:3a7713b1edbc 16061 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 16062 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
AnnaBridge 171:3a7713b1edbc 16063 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
AnnaBridge 171:3a7713b1edbc 16064 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 16065 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
AnnaBridge 171:3a7713b1edbc 16066 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
AnnaBridge 171:3a7713b1edbc 16067 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 16068 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 171:3a7713b1edbc 16069
AnnaBridge 171:3a7713b1edbc 16070 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
AnnaBridge 171:3a7713b1edbc 16071 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16072 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16073 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
AnnaBridge 171:3a7713b1edbc 16074 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 16075 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16076 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
AnnaBridge 171:3a7713b1edbc 16077 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 16078 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16079 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
AnnaBridge 171:3a7713b1edbc 16080 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16081 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16082 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
AnnaBridge 171:3a7713b1edbc 16083 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 16084 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16085 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 171:3a7713b1edbc 16086 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16087 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16088 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 171:3a7713b1edbc 16089 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 16090 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16091 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
AnnaBridge 171:3a7713b1edbc 16092 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
AnnaBridge 171:3a7713b1edbc 16093 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 16094 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
AnnaBridge 171:3a7713b1edbc 16095 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
AnnaBridge 171:3a7713b1edbc 16096 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 16097 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
AnnaBridge 171:3a7713b1edbc 16098 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 16099 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 16100 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
AnnaBridge 171:3a7713b1edbc 16101 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
AnnaBridge 171:3a7713b1edbc 16102 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 16103 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
AnnaBridge 171:3a7713b1edbc 16104 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 16105 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 16106 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 171:3a7713b1edbc 16107 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16108 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16109 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
AnnaBridge 171:3a7713b1edbc 16110 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16111 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16112 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
AnnaBridge 171:3a7713b1edbc 16113 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
AnnaBridge 171:3a7713b1edbc 16114 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16115 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
AnnaBridge 171:3a7713b1edbc 16116 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 16117 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16118 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
AnnaBridge 171:3a7713b1edbc 16119 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
AnnaBridge 171:3a7713b1edbc 16120 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 16121 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 171:3a7713b1edbc 16122 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
AnnaBridge 171:3a7713b1edbc 16123 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16124 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
AnnaBridge 171:3a7713b1edbc 16125 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 16126 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 16127 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
AnnaBridge 171:3a7713b1edbc 16128 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
AnnaBridge 171:3a7713b1edbc 16129 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16130 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
AnnaBridge 171:3a7713b1edbc 16131 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
AnnaBridge 171:3a7713b1edbc 16132 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16133 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
AnnaBridge 171:3a7713b1edbc 16134 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
AnnaBridge 171:3a7713b1edbc 16135 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 16136 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
AnnaBridge 171:3a7713b1edbc 16137 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
AnnaBridge 171:3a7713b1edbc 16138 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 16139 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
AnnaBridge 171:3a7713b1edbc 16140 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
AnnaBridge 171:3a7713b1edbc 16141 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 16142 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
AnnaBridge 171:3a7713b1edbc 16143 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
AnnaBridge 171:3a7713b1edbc 16144 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 16145 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
AnnaBridge 171:3a7713b1edbc 16146 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
AnnaBridge 171:3a7713b1edbc 16147 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 16148 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
AnnaBridge 171:3a7713b1edbc 16149 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
AnnaBridge 171:3a7713b1edbc 16150 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 16151 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
AnnaBridge 171:3a7713b1edbc 16152 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
AnnaBridge 171:3a7713b1edbc 16153 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 16154 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 171:3a7713b1edbc 16155
AnnaBridge 171:3a7713b1edbc 16156 /******************** Bit definition for USB_OTG_DAINT register ********************/
AnnaBridge 171:3a7713b1edbc 16157 #define USB_OTG_DAINT_IEPINT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16158 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16159 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
AnnaBridge 171:3a7713b1edbc 16160 #define USB_OTG_DAINT_OEPINT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16161 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 16162 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
AnnaBridge 171:3a7713b1edbc 16163
AnnaBridge 171:3a7713b1edbc 16164 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
AnnaBridge 171:3a7713b1edbc 16165 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16166 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16167 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
AnnaBridge 171:3a7713b1edbc 16168
AnnaBridge 171:3a7713b1edbc 16169 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 171:3a7713b1edbc 16170 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16171 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 16172 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 171:3a7713b1edbc 16173 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16174 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 171:3a7713b1edbc 16175 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 171:3a7713b1edbc 16176 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16177 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 171:3a7713b1edbc 16178 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 171:3a7713b1edbc 16179 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16180 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 171:3a7713b1edbc 16181 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 171:3a7713b1edbc 16182
AnnaBridge 171:3a7713b1edbc 16183 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
AnnaBridge 171:3a7713b1edbc 16184 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16185 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16186 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 171:3a7713b1edbc 16187 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16188 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 16189 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 171:3a7713b1edbc 16190
AnnaBridge 171:3a7713b1edbc 16191 /******************** Bit definition for OTG register ********************/
AnnaBridge 171:3a7713b1edbc 16192
AnnaBridge 171:3a7713b1edbc 16193 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16194 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 16195 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 171:3a7713b1edbc 16196 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16197 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16198 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16199 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16200 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16201 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 171:3a7713b1edbc 16202 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 171:3a7713b1edbc 16203
AnnaBridge 171:3a7713b1edbc 16204 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16205 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 171:3a7713b1edbc 16206 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 171:3a7713b1edbc 16207 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16208 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16209
AnnaBridge 171:3a7713b1edbc 16210 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16211 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 171:3a7713b1edbc 16212 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 171:3a7713b1edbc 16213 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16214 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16215 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16216 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 16217
AnnaBridge 171:3a7713b1edbc 16218 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16219 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 16220 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 171:3a7713b1edbc 16221 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16222 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16223 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16224 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16225
AnnaBridge 171:3a7713b1edbc 16226 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 171:3a7713b1edbc 16227 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 171:3a7713b1edbc 16228 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 171:3a7713b1edbc 16229 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16230 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 16231 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16232 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16233
AnnaBridge 171:3a7713b1edbc 16234 /******************** Bit definition for OTG register ********************/
AnnaBridge 171:3a7713b1edbc 16235
AnnaBridge 171:3a7713b1edbc 16236 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16237 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 16238 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 171:3a7713b1edbc 16239 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16240 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16241 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16242 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16243 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16244 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 171:3a7713b1edbc 16245 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 171:3a7713b1edbc 16246
AnnaBridge 171:3a7713b1edbc 16247 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16248 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 171:3a7713b1edbc 16249 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 171:3a7713b1edbc 16250 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16251 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16252
AnnaBridge 171:3a7713b1edbc 16253 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16254 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 171:3a7713b1edbc 16255 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 171:3a7713b1edbc 16256 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16257 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16258 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16259 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 16260
AnnaBridge 171:3a7713b1edbc 16261 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16262 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 16263 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 171:3a7713b1edbc 16264 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16265 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16266 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16267 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16268
AnnaBridge 171:3a7713b1edbc 16269 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 171:3a7713b1edbc 16270 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 171:3a7713b1edbc 16271 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 171:3a7713b1edbc 16272 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16273 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 16274 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16275 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16276
AnnaBridge 171:3a7713b1edbc 16277 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
AnnaBridge 171:3a7713b1edbc 16278 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16279 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16280 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
AnnaBridge 171:3a7713b1edbc 16281
AnnaBridge 171:3a7713b1edbc 16282 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
AnnaBridge 171:3a7713b1edbc 16283 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16284 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16285 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
AnnaBridge 171:3a7713b1edbc 16286
AnnaBridge 171:3a7713b1edbc 16287 /******************** Bit definition for OTG register ********************/
AnnaBridge 171:3a7713b1edbc 16288 #define USB_OTG_NPTXFSA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16289 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16290 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
AnnaBridge 171:3a7713b1edbc 16291 #define USB_OTG_NPTXFD_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16292 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 16293 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
AnnaBridge 171:3a7713b1edbc 16294 #define USB_OTG_TX0FSA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16295 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16296 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 171:3a7713b1edbc 16297 #define USB_OTG_TX0FD_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16298 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 16299 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
AnnaBridge 171:3a7713b1edbc 16300
AnnaBridge 171:3a7713b1edbc 16301 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
AnnaBridge 171:3a7713b1edbc 16302 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16303 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 16304 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
AnnaBridge 171:3a7713b1edbc 16305
AnnaBridge 171:3a7713b1edbc 16306 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
AnnaBridge 171:3a7713b1edbc 16307 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16308 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16309 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
AnnaBridge 171:3a7713b1edbc 16310
AnnaBridge 171:3a7713b1edbc 16311 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16312 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 16313 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
AnnaBridge 171:3a7713b1edbc 16314 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16315 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16316 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16317 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16318 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 16319 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16320 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 16321 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16322
AnnaBridge 171:3a7713b1edbc 16323 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
AnnaBridge 171:3a7713b1edbc 16324 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
AnnaBridge 171:3a7713b1edbc 16325 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 171:3a7713b1edbc 16326 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16327 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 16328 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 16329 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 16330 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 16331 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 16332 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 16333
AnnaBridge 171:3a7713b1edbc 16334 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
AnnaBridge 171:3a7713b1edbc 16335 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16336 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16337 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 171:3a7713b1edbc 16338 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16339 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16340 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
AnnaBridge 171:3a7713b1edbc 16341
AnnaBridge 171:3a7713b1edbc 16342 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 16343 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
AnnaBridge 171:3a7713b1edbc 16344 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
AnnaBridge 171:3a7713b1edbc 16345 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16346 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16347 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16348 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16349 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16350 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16351 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 16352 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 16353 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 16354 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16355 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16356 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
AnnaBridge 171:3a7713b1edbc 16357
AnnaBridge 171:3a7713b1edbc 16358 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16359 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
AnnaBridge 171:3a7713b1edbc 16360 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
AnnaBridge 171:3a7713b1edbc 16361 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16362 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16363 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16364 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 16365 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16366 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 16367 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16368 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16369 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 16370 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
AnnaBridge 171:3a7713b1edbc 16371 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 16372 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
AnnaBridge 171:3a7713b1edbc 16373
AnnaBridge 171:3a7713b1edbc 16374 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 171:3a7713b1edbc 16375 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16376 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16377 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 171:3a7713b1edbc 16378
AnnaBridge 171:3a7713b1edbc 16379 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
AnnaBridge 171:3a7713b1edbc 16380 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16381 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16382 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
AnnaBridge 171:3a7713b1edbc 16383 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16384 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16385 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 171:3a7713b1edbc 16386
AnnaBridge 171:3a7713b1edbc 16387 /******************** Bit definition for USB_OTG_GCCFG register ********************/
AnnaBridge 171:3a7713b1edbc 16388 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16389 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16390 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
AnnaBridge 171:3a7713b1edbc 16391 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 16392 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16393 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
AnnaBridge 171:3a7713b1edbc 16394
AnnaBridge 171:3a7713b1edbc 16395 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
AnnaBridge 171:3a7713b1edbc 16396 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16397 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16398 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
AnnaBridge 171:3a7713b1edbc 16399 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
AnnaBridge 171:3a7713b1edbc 16400 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16401 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
AnnaBridge 171:3a7713b1edbc 16402
AnnaBridge 171:3a7713b1edbc 16403 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
AnnaBridge 171:3a7713b1edbc 16404 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16405 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16406 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 171:3a7713b1edbc 16407 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16408 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16409 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 171:3a7713b1edbc 16410
AnnaBridge 171:3a7713b1edbc 16411 /******************** Bit definition for USB_OTG_CID register ********************/
AnnaBridge 171:3a7713b1edbc 16412 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16413 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 16414 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
AnnaBridge 171:3a7713b1edbc 16415
AnnaBridge 171:3a7713b1edbc 16416 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
AnnaBridge 171:3a7713b1edbc 16417 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16418 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16419 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
AnnaBridge 171:3a7713b1edbc 16420 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16421 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16422 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
AnnaBridge 171:3a7713b1edbc 16423 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 16424 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
AnnaBridge 171:3a7713b1edbc 16425 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
AnnaBridge 171:3a7713b1edbc 16426 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16427 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16428 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
AnnaBridge 171:3a7713b1edbc 16429 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 16430 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16431 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
AnnaBridge 171:3a7713b1edbc 16432 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 16433 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 16434 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
AnnaBridge 171:3a7713b1edbc 16435 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 16436 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 16437 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
AnnaBridge 171:3a7713b1edbc 16438 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 16439 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 16440 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
AnnaBridge 171:3a7713b1edbc 16441 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16442 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16443 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
AnnaBridge 171:3a7713b1edbc 16444 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16445 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16446 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
AnnaBridge 171:3a7713b1edbc 16447 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16448 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
AnnaBridge 171:3a7713b1edbc 16449 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
AnnaBridge 171:3a7713b1edbc 16450 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 16451 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 16452 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
AnnaBridge 171:3a7713b1edbc 16453 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
AnnaBridge 171:3a7713b1edbc 16454 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16455 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
AnnaBridge 171:3a7713b1edbc 16456 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
AnnaBridge 171:3a7713b1edbc 16457 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
AnnaBridge 171:3a7713b1edbc 16458 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
AnnaBridge 171:3a7713b1edbc 16459 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
AnnaBridge 171:3a7713b1edbc 16460 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 16461 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
AnnaBridge 171:3a7713b1edbc 16462
AnnaBridge 171:3a7713b1edbc 16463 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 171:3a7713b1edbc 16464 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16465 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16466 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 171:3a7713b1edbc 16467 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16468 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16469 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 171:3a7713b1edbc 16470 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 16471 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16472 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 171:3a7713b1edbc 16473 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16474 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16475 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 171:3a7713b1edbc 16476 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 16477 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16478 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 171:3a7713b1edbc 16479 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16480 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16481 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 171:3a7713b1edbc 16482 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 16483 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 16484 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 171:3a7713b1edbc 16485 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 16486 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 16487 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 171:3a7713b1edbc 16488 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 171:3a7713b1edbc 16489 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 16490 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 171:3a7713b1edbc 16491
AnnaBridge 171:3a7713b1edbc 16492 /******************** Bit definition for USB_OTG_HPRT register ********************/
AnnaBridge 171:3a7713b1edbc 16493 #define USB_OTG_HPRT_PCSTS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16494 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16495 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
AnnaBridge 171:3a7713b1edbc 16496 #define USB_OTG_HPRT_PCDET_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16497 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16498 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
AnnaBridge 171:3a7713b1edbc 16499 #define USB_OTG_HPRT_PENA_Pos (2U)
AnnaBridge 171:3a7713b1edbc 16500 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16501 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
AnnaBridge 171:3a7713b1edbc 16502 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
AnnaBridge 171:3a7713b1edbc 16503 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16504 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
AnnaBridge 171:3a7713b1edbc 16505 #define USB_OTG_HPRT_POCA_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16506 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16507 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
AnnaBridge 171:3a7713b1edbc 16508 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
AnnaBridge 171:3a7713b1edbc 16509 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16510 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
AnnaBridge 171:3a7713b1edbc 16511 #define USB_OTG_HPRT_PRES_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16512 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16513 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
AnnaBridge 171:3a7713b1edbc 16514 #define USB_OTG_HPRT_PSUSP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 16515 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16516 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
AnnaBridge 171:3a7713b1edbc 16517 #define USB_OTG_HPRT_PRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 16518 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 16519 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
AnnaBridge 171:3a7713b1edbc 16520
AnnaBridge 171:3a7713b1edbc 16521 #define USB_OTG_HPRT_PLSTS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 16522 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 16523 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
AnnaBridge 171:3a7713b1edbc 16524 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 16525 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 16526 #define USB_OTG_HPRT_PPWR_Pos (12U)
AnnaBridge 171:3a7713b1edbc 16527 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 16528 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
AnnaBridge 171:3a7713b1edbc 16529
AnnaBridge 171:3a7713b1edbc 16530 #define USB_OTG_HPRT_PTCTL_Pos (13U)
AnnaBridge 171:3a7713b1edbc 16531 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
AnnaBridge 171:3a7713b1edbc 16532 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
AnnaBridge 171:3a7713b1edbc 16533 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 16534 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 16535 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16536 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16537
AnnaBridge 171:3a7713b1edbc 16538 #define USB_OTG_HPRT_PSPD_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16539 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
AnnaBridge 171:3a7713b1edbc 16540 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
AnnaBridge 171:3a7713b1edbc 16541 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16542 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16543
AnnaBridge 171:3a7713b1edbc 16544 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 171:3a7713b1edbc 16545 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16546 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16547 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 171:3a7713b1edbc 16548 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16549 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16550 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 171:3a7713b1edbc 16551 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 16552 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16553 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
AnnaBridge 171:3a7713b1edbc 16554 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16555 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16556 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 171:3a7713b1edbc 16557 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 16558 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16559 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 171:3a7713b1edbc 16560 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16561 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16562 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 171:3a7713b1edbc 16563 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 16564 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 16565 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
AnnaBridge 171:3a7713b1edbc 16566 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 16567 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 16568 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 171:3a7713b1edbc 16569 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
AnnaBridge 171:3a7713b1edbc 16570 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 16571 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
AnnaBridge 171:3a7713b1edbc 16572 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 171:3a7713b1edbc 16573 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 16574 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 171:3a7713b1edbc 16575 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 16576 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 16577 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
AnnaBridge 171:3a7713b1edbc 16578
AnnaBridge 171:3a7713b1edbc 16579 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
AnnaBridge 171:3a7713b1edbc 16580 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16581 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16582 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
AnnaBridge 171:3a7713b1edbc 16583 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16584 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 16585 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
AnnaBridge 171:3a7713b1edbc 16586
AnnaBridge 171:3a7713b1edbc 16587 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
AnnaBridge 171:3a7713b1edbc 16588 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16589 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 16590 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 171:3a7713b1edbc 16591 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16592 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16593 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 171:3a7713b1edbc 16594 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16595 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16596 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
AnnaBridge 171:3a7713b1edbc 16597 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16598 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16599 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 171:3a7713b1edbc 16600
AnnaBridge 171:3a7713b1edbc 16601 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 16602 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 16603 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 171:3a7713b1edbc 16604 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16605 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16606 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 16607 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16608 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 171:3a7713b1edbc 16609
AnnaBridge 171:3a7713b1edbc 16610 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 16611 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
AnnaBridge 171:3a7713b1edbc 16612 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 171:3a7713b1edbc 16613 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 16614 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16615 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16616 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 16617 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
AnnaBridge 171:3a7713b1edbc 16618 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 16619 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 171:3a7713b1edbc 16620 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
AnnaBridge 171:3a7713b1edbc 16621 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 16622 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 171:3a7713b1edbc 16623 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 171:3a7713b1edbc 16624 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 16625 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 171:3a7713b1edbc 16626 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
AnnaBridge 171:3a7713b1edbc 16627 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 16628 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 171:3a7713b1edbc 16629 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
AnnaBridge 171:3a7713b1edbc 16630 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 16631 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 171:3a7713b1edbc 16632 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
AnnaBridge 171:3a7713b1edbc 16633 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 16634 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 171:3a7713b1edbc 16635
AnnaBridge 171:3a7713b1edbc 16636 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
AnnaBridge 171:3a7713b1edbc 16637 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16638 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 16639 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 171:3a7713b1edbc 16640
AnnaBridge 171:3a7713b1edbc 16641 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
AnnaBridge 171:3a7713b1edbc 16642 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
AnnaBridge 171:3a7713b1edbc 16643 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 171:3a7713b1edbc 16644 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 16645 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 16646 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 16647 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 16648 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16649 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16650 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
AnnaBridge 171:3a7713b1edbc 16651 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16652 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16653 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
AnnaBridge 171:3a7713b1edbc 16654
AnnaBridge 171:3a7713b1edbc 16655 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 16656 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 16657 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 171:3a7713b1edbc 16658 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16659 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16660
AnnaBridge 171:3a7713b1edbc 16661 #define USB_OTG_HCCHAR_MC_Pos (20U)
AnnaBridge 171:3a7713b1edbc 16662 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 16663 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 171:3a7713b1edbc 16664 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 16665 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16666
AnnaBridge 171:3a7713b1edbc 16667 #define USB_OTG_HCCHAR_DAD_Pos (22U)
AnnaBridge 171:3a7713b1edbc 16668 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
AnnaBridge 171:3a7713b1edbc 16669 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
AnnaBridge 171:3a7713b1edbc 16670 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 16671 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 16672 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 16673 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 16674 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 16675 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 16676 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 16677 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
AnnaBridge 171:3a7713b1edbc 16678 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 16679 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
AnnaBridge 171:3a7713b1edbc 16680 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
AnnaBridge 171:3a7713b1edbc 16681 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 16682 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
AnnaBridge 171:3a7713b1edbc 16683 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
AnnaBridge 171:3a7713b1edbc 16684 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 16685 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
AnnaBridge 171:3a7713b1edbc 16686
AnnaBridge 171:3a7713b1edbc 16687 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
AnnaBridge 171:3a7713b1edbc 16688
AnnaBridge 171:3a7713b1edbc 16689 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16690 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 16691 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
AnnaBridge 171:3a7713b1edbc 16692 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16693 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16694 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16695 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16696 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16697 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16698 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16699
AnnaBridge 171:3a7713b1edbc 16700 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 16701 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
AnnaBridge 171:3a7713b1edbc 16702 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
AnnaBridge 171:3a7713b1edbc 16703 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16704 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 16705 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 16706 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 16707 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 16708 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 16709 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 16710
AnnaBridge 171:3a7713b1edbc 16711 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
AnnaBridge 171:3a7713b1edbc 16712 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 16713 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
AnnaBridge 171:3a7713b1edbc 16714 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 16715 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16716 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16717 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 16718 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
AnnaBridge 171:3a7713b1edbc 16719 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 16720 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 16721 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
AnnaBridge 171:3a7713b1edbc 16722
AnnaBridge 171:3a7713b1edbc 16723 /******************** Bit definition for USB_OTG_HCINT register ********************/
AnnaBridge 171:3a7713b1edbc 16724 #define USB_OTG_HCINT_XFRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16725 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16726 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
AnnaBridge 171:3a7713b1edbc 16727 #define USB_OTG_HCINT_CHH_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16728 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16729 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
AnnaBridge 171:3a7713b1edbc 16730 #define USB_OTG_HCINT_AHBERR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 16731 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16732 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
AnnaBridge 171:3a7713b1edbc 16733 #define USB_OTG_HCINT_STALL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 16734 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16735 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
AnnaBridge 171:3a7713b1edbc 16736 #define USB_OTG_HCINT_NAK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16737 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16738 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
AnnaBridge 171:3a7713b1edbc 16739 #define USB_OTG_HCINT_ACK_Pos (5U)
AnnaBridge 171:3a7713b1edbc 16740 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16741 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
AnnaBridge 171:3a7713b1edbc 16742 #define USB_OTG_HCINT_NYET_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16743 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16744 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
AnnaBridge 171:3a7713b1edbc 16745 #define USB_OTG_HCINT_TXERR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 16746 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16747 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
AnnaBridge 171:3a7713b1edbc 16748 #define USB_OTG_HCINT_BBERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 16749 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 16750 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
AnnaBridge 171:3a7713b1edbc 16751 #define USB_OTG_HCINT_FRMOR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 16752 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 16753 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
AnnaBridge 171:3a7713b1edbc 16754 #define USB_OTG_HCINT_DTERR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 16755 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 16756 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
AnnaBridge 171:3a7713b1edbc 16757
AnnaBridge 171:3a7713b1edbc 16758 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
AnnaBridge 171:3a7713b1edbc 16759 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16760 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16761 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 171:3a7713b1edbc 16762 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16763 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16764 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 171:3a7713b1edbc 16765 #define USB_OTG_DIEPINT_TOC_Pos (3U)
AnnaBridge 171:3a7713b1edbc 16766 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16767 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
AnnaBridge 171:3a7713b1edbc 16768 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16769 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16770 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
AnnaBridge 171:3a7713b1edbc 16771 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16772 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16773 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
AnnaBridge 171:3a7713b1edbc 16774 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 16775 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16776 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
AnnaBridge 171:3a7713b1edbc 16777 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 16778 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 16779 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
AnnaBridge 171:3a7713b1edbc 16780 #define USB_OTG_DIEPINT_BNA_Pos (9U)
AnnaBridge 171:3a7713b1edbc 16781 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 16782 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
AnnaBridge 171:3a7713b1edbc 16783 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
AnnaBridge 171:3a7713b1edbc 16784 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 16785 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
AnnaBridge 171:3a7713b1edbc 16786 #define USB_OTG_DIEPINT_BERR_Pos (12U)
AnnaBridge 171:3a7713b1edbc 16787 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 16788 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
AnnaBridge 171:3a7713b1edbc 16789 #define USB_OTG_DIEPINT_NAK_Pos (13U)
AnnaBridge 171:3a7713b1edbc 16790 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 16791 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
AnnaBridge 171:3a7713b1edbc 16792
AnnaBridge 171:3a7713b1edbc 16793 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
AnnaBridge 171:3a7713b1edbc 16794 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16795 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16796 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
AnnaBridge 171:3a7713b1edbc 16797 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16798 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16799 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
AnnaBridge 171:3a7713b1edbc 16800 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 16801 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 16802 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
AnnaBridge 171:3a7713b1edbc 16803 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 16804 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16805 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
AnnaBridge 171:3a7713b1edbc 16806 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16807 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16808 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
AnnaBridge 171:3a7713b1edbc 16809 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 16810 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16811 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 171:3a7713b1edbc 16812 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16813 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16814 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
AnnaBridge 171:3a7713b1edbc 16815 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 16816 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 16817 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
AnnaBridge 171:3a7713b1edbc 16818 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 16819 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 16820 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
AnnaBridge 171:3a7713b1edbc 16821 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 16822 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 16823 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
AnnaBridge 171:3a7713b1edbc 16824 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
AnnaBridge 171:3a7713b1edbc 16825 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 16826 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
AnnaBridge 171:3a7713b1edbc 16827
AnnaBridge 171:3a7713b1edbc 16828 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
AnnaBridge 171:3a7713b1edbc 16829
AnnaBridge 171:3a7713b1edbc 16830 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16831 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 16832 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 171:3a7713b1edbc 16833 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 16834 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 171:3a7713b1edbc 16835 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 171:3a7713b1edbc 16836 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
AnnaBridge 171:3a7713b1edbc 16837 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
AnnaBridge 171:3a7713b1edbc 16838 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
AnnaBridge 171:3a7713b1edbc 16839 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
AnnaBridge 171:3a7713b1edbc 16840 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16841 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 16842 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 171:3a7713b1edbc 16843 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 16844 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 171:3a7713b1edbc 16845 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 171:3a7713b1edbc 16846 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
AnnaBridge 171:3a7713b1edbc 16847 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 16848 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
AnnaBridge 171:3a7713b1edbc 16849 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
AnnaBridge 171:3a7713b1edbc 16850 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
AnnaBridge 171:3a7713b1edbc 16851 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
AnnaBridge 171:3a7713b1edbc 16852 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 16853 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 16854
AnnaBridge 171:3a7713b1edbc 16855 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
AnnaBridge 171:3a7713b1edbc 16856 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16857 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 16858 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 171:3a7713b1edbc 16859
AnnaBridge 171:3a7713b1edbc 16860 /******************** Bit definition for USB_OTG_HCDMA register ********************/
AnnaBridge 171:3a7713b1edbc 16861 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16862 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 16863 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 171:3a7713b1edbc 16864
AnnaBridge 171:3a7713b1edbc 16865 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
AnnaBridge 171:3a7713b1edbc 16866 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16867 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16868 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
AnnaBridge 171:3a7713b1edbc 16869
AnnaBridge 171:3a7713b1edbc 16870 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
AnnaBridge 171:3a7713b1edbc 16871 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16872 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 16873 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 171:3a7713b1edbc 16874 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
AnnaBridge 171:3a7713b1edbc 16875 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 16876 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
AnnaBridge 171:3a7713b1edbc 16877
AnnaBridge 171:3a7713b1edbc 16878 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
AnnaBridge 171:3a7713b1edbc 16879 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16880 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 16881 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 16882 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 16883 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 16884 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 171:3a7713b1edbc 16885 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
AnnaBridge 171:3a7713b1edbc 16886 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 16887 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 171:3a7713b1edbc 16888 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 171:3a7713b1edbc 16889 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 16890 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 171:3a7713b1edbc 16891 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
AnnaBridge 171:3a7713b1edbc 16892 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 16893 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 171:3a7713b1edbc 16894 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 16895 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 16896 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 171:3a7713b1edbc 16897 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 16898 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 16899 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
AnnaBridge 171:3a7713b1edbc 16900 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 16901 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
AnnaBridge 171:3a7713b1edbc 16902 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 16903 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 16904 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 171:3a7713b1edbc 16905 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
AnnaBridge 171:3a7713b1edbc 16906 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 16907 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 171:3a7713b1edbc 16908 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
AnnaBridge 171:3a7713b1edbc 16909 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 16910 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 171:3a7713b1edbc 16911 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
AnnaBridge 171:3a7713b1edbc 16912 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 16913 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 171:3a7713b1edbc 16914 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
AnnaBridge 171:3a7713b1edbc 16915 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 16916 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 171:3a7713b1edbc 16917
AnnaBridge 171:3a7713b1edbc 16918 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
AnnaBridge 171:3a7713b1edbc 16919 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16920 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16921 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 171:3a7713b1edbc 16922 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16923 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16924 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 171:3a7713b1edbc 16925 #define USB_OTG_DOEPINT_STUP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 16926 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 16927 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
AnnaBridge 171:3a7713b1edbc 16928 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16929 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16930 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
AnnaBridge 171:3a7713b1edbc 16931 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 16932 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 16933 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
AnnaBridge 171:3a7713b1edbc 16934 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 16935 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 16936 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
AnnaBridge 171:3a7713b1edbc 16937 #define USB_OTG_DOEPINT_NYET_Pos (14U)
AnnaBridge 171:3a7713b1edbc 16938 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 16939 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
AnnaBridge 171:3a7713b1edbc 16940
AnnaBridge 171:3a7713b1edbc 16941 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
AnnaBridge 171:3a7713b1edbc 16942 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16943 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 16944 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 171:3a7713b1edbc 16945 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 16946 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 171:3a7713b1edbc 16947 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 171:3a7713b1edbc 16948
AnnaBridge 171:3a7713b1edbc 16949 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
AnnaBridge 171:3a7713b1edbc 16950 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
AnnaBridge 171:3a7713b1edbc 16951 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
AnnaBridge 171:3a7713b1edbc 16952 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 16953 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 16954
AnnaBridge 171:3a7713b1edbc 16955 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 171:3a7713b1edbc 16956 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 16957 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 16958 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
AnnaBridge 171:3a7713b1edbc 16959 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 16960 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 16961 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 16962 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 16963 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 16964 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 16965
AnnaBridge 171:3a7713b1edbc 16966
AnnaBridge 171:3a7713b1edbc 16967
AnnaBridge 171:3a7713b1edbc 16968
AnnaBridge 171:3a7713b1edbc 16969 /**
AnnaBridge 171:3a7713b1edbc 16970 * @}
AnnaBridge 171:3a7713b1edbc 16971 */
AnnaBridge 171:3a7713b1edbc 16972
AnnaBridge 171:3a7713b1edbc 16973 /**
AnnaBridge 171:3a7713b1edbc 16974 * @}
AnnaBridge 171:3a7713b1edbc 16975 */
AnnaBridge 171:3a7713b1edbc 16976
AnnaBridge 171:3a7713b1edbc 16977 /** @addtogroup Exported_macros
AnnaBridge 171:3a7713b1edbc 16978 * @{
AnnaBridge 171:3a7713b1edbc 16979 */
AnnaBridge 171:3a7713b1edbc 16980
AnnaBridge 171:3a7713b1edbc 16981 /******************************* ADC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 16982 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
AnnaBridge 171:3a7713b1edbc 16983 ((__INSTANCE__) == ADC2) || \
AnnaBridge 171:3a7713b1edbc 16984 ((__INSTANCE__) == ADC3))
AnnaBridge 171:3a7713b1edbc 16985 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 171:3a7713b1edbc 16986
AnnaBridge 171:3a7713b1edbc 16987 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
AnnaBridge 171:3a7713b1edbc 16988
AnnaBridge 171:3a7713b1edbc 16989 /******************************* CAN Instances ********************************/
AnnaBridge 171:3a7713b1edbc 16990 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
AnnaBridge 171:3a7713b1edbc 16991 ((__INSTANCE__) == CAN2))
AnnaBridge 171:3a7713b1edbc 16992 /******************************* CRC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 16993 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
AnnaBridge 171:3a7713b1edbc 16994
AnnaBridge 171:3a7713b1edbc 16995 /******************************* DAC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 16996 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
AnnaBridge 171:3a7713b1edbc 16997
AnnaBridge 171:3a7713b1edbc 16998 /******************************* DCMI Instances *******************************/
AnnaBridge 171:3a7713b1edbc 16999 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
AnnaBridge 171:3a7713b1edbc 17000
AnnaBridge 171:3a7713b1edbc 17001
AnnaBridge 171:3a7713b1edbc 17002 /******************************* DMA2D Instances *******************************/
AnnaBridge 171:3a7713b1edbc 17003 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
AnnaBridge 171:3a7713b1edbc 17004
AnnaBridge 171:3a7713b1edbc 17005 /******************************** DMA Instances *******************************/
AnnaBridge 171:3a7713b1edbc 17006 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
AnnaBridge 171:3a7713b1edbc 17007 ((__INSTANCE__) == DMA1_Stream1) || \
AnnaBridge 171:3a7713b1edbc 17008 ((__INSTANCE__) == DMA1_Stream2) || \
AnnaBridge 171:3a7713b1edbc 17009 ((__INSTANCE__) == DMA1_Stream3) || \
AnnaBridge 171:3a7713b1edbc 17010 ((__INSTANCE__) == DMA1_Stream4) || \
AnnaBridge 171:3a7713b1edbc 17011 ((__INSTANCE__) == DMA1_Stream5) || \
AnnaBridge 171:3a7713b1edbc 17012 ((__INSTANCE__) == DMA1_Stream6) || \
AnnaBridge 171:3a7713b1edbc 17013 ((__INSTANCE__) == DMA1_Stream7) || \
AnnaBridge 171:3a7713b1edbc 17014 ((__INSTANCE__) == DMA2_Stream0) || \
AnnaBridge 171:3a7713b1edbc 17015 ((__INSTANCE__) == DMA2_Stream1) || \
AnnaBridge 171:3a7713b1edbc 17016 ((__INSTANCE__) == DMA2_Stream2) || \
AnnaBridge 171:3a7713b1edbc 17017 ((__INSTANCE__) == DMA2_Stream3) || \
AnnaBridge 171:3a7713b1edbc 17018 ((__INSTANCE__) == DMA2_Stream4) || \
AnnaBridge 171:3a7713b1edbc 17019 ((__INSTANCE__) == DMA2_Stream5) || \
AnnaBridge 171:3a7713b1edbc 17020 ((__INSTANCE__) == DMA2_Stream6) || \
AnnaBridge 171:3a7713b1edbc 17021 ((__INSTANCE__) == DMA2_Stream7))
AnnaBridge 171:3a7713b1edbc 17022
AnnaBridge 171:3a7713b1edbc 17023 /******************************* GPIO Instances *******************************/
AnnaBridge 171:3a7713b1edbc 17024 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 17025 ((__INSTANCE__) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 17026 ((__INSTANCE__) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 17027 ((__INSTANCE__) == GPIOD) || \
AnnaBridge 171:3a7713b1edbc 17028 ((__INSTANCE__) == GPIOE) || \
AnnaBridge 171:3a7713b1edbc 17029 ((__INSTANCE__) == GPIOF) || \
AnnaBridge 171:3a7713b1edbc 17030 ((__INSTANCE__) == GPIOG) || \
AnnaBridge 171:3a7713b1edbc 17031 ((__INSTANCE__) == GPIOH) || \
AnnaBridge 171:3a7713b1edbc 17032 ((__INSTANCE__) == GPIOI) || \
AnnaBridge 171:3a7713b1edbc 17033 ((__INSTANCE__) == GPIOJ) || \
AnnaBridge 171:3a7713b1edbc 17034 ((__INSTANCE__) == GPIOK))
AnnaBridge 171:3a7713b1edbc 17035
AnnaBridge 171:3a7713b1edbc 17036 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 17037 ((__INSTANCE__) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 17038 ((__INSTANCE__) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 17039 ((__INSTANCE__) == GPIOD) || \
AnnaBridge 171:3a7713b1edbc 17040 ((__INSTANCE__) == GPIOE) || \
AnnaBridge 171:3a7713b1edbc 17041 ((__INSTANCE__) == GPIOF) || \
AnnaBridge 171:3a7713b1edbc 17042 ((__INSTANCE__) == GPIOG) || \
AnnaBridge 171:3a7713b1edbc 17043 ((__INSTANCE__) == GPIOH) || \
AnnaBridge 171:3a7713b1edbc 17044 ((__INSTANCE__) == GPIOI) || \
AnnaBridge 171:3a7713b1edbc 17045 ((__INSTANCE__) == GPIOJ) || \
AnnaBridge 171:3a7713b1edbc 17046 ((__INSTANCE__) == GPIOK))
AnnaBridge 171:3a7713b1edbc 17047
AnnaBridge 171:3a7713b1edbc 17048 /****************************** CEC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 17049 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
AnnaBridge 171:3a7713b1edbc 17050
AnnaBridge 171:3a7713b1edbc 17051 /****************************** QSPI Instances *********************************/
AnnaBridge 171:3a7713b1edbc 17052 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
AnnaBridge 171:3a7713b1edbc 17053
AnnaBridge 171:3a7713b1edbc 17054
AnnaBridge 171:3a7713b1edbc 17055 /******************************** I2C Instances *******************************/
AnnaBridge 171:3a7713b1edbc 17056 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
AnnaBridge 171:3a7713b1edbc 17057 ((__INSTANCE__) == I2C2) || \
AnnaBridge 171:3a7713b1edbc 17058 ((__INSTANCE__) == I2C3) || \
AnnaBridge 171:3a7713b1edbc 17059 ((__INSTANCE__) == I2C4))
AnnaBridge 171:3a7713b1edbc 17060
AnnaBridge 171:3a7713b1edbc 17061 /****************************** SMBUS Instances *******************************/
AnnaBridge 171:3a7713b1edbc 17062 #define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
AnnaBridge 171:3a7713b1edbc 17063 ((__INSTANCE__) == I2C2) || \
AnnaBridge 171:3a7713b1edbc 17064 ((__INSTANCE__) == I2C3) || \
AnnaBridge 171:3a7713b1edbc 17065 ((__INSTANCE__) == I2C4))
AnnaBridge 171:3a7713b1edbc 17066
AnnaBridge 171:3a7713b1edbc 17067
AnnaBridge 171:3a7713b1edbc 17068 /******************************** I2S Instances *******************************/
AnnaBridge 171:3a7713b1edbc 17069 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
AnnaBridge 171:3a7713b1edbc 17070 ((__INSTANCE__) == SPI2) || \
AnnaBridge 171:3a7713b1edbc 17071 ((__INSTANCE__) == SPI3))
AnnaBridge 171:3a7713b1edbc 17072
AnnaBridge 171:3a7713b1edbc 17073 /******************************* LPTIM Instances ********************************/
AnnaBridge 171:3a7713b1edbc 17074 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
AnnaBridge 171:3a7713b1edbc 17075
AnnaBridge 171:3a7713b1edbc 17076 /****************************** LTDC Instances ********************************/
AnnaBridge 171:3a7713b1edbc 17077 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
AnnaBridge 171:3a7713b1edbc 17078
AnnaBridge 171:3a7713b1edbc 17079
AnnaBridge 171:3a7713b1edbc 17080
AnnaBridge 171:3a7713b1edbc 17081
AnnaBridge 171:3a7713b1edbc 17082 /******************************* RNG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 17083 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
AnnaBridge 171:3a7713b1edbc 17084
AnnaBridge 171:3a7713b1edbc 17085 /****************************** RTC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 17086 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
AnnaBridge 171:3a7713b1edbc 17087
AnnaBridge 171:3a7713b1edbc 17088 /******************************* SAI Instances ********************************/
AnnaBridge 171:3a7713b1edbc 17089 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
AnnaBridge 171:3a7713b1edbc 17090 ((__PERIPH__) == SAI1_Block_B) || \
AnnaBridge 171:3a7713b1edbc 17091 ((__PERIPH__) == SAI2_Block_A) || \
AnnaBridge 171:3a7713b1edbc 17092 ((__PERIPH__) == SAI2_Block_B))
AnnaBridge 171:3a7713b1edbc 17093 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 17094 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
AnnaBridge 171:3a7713b1edbc 17095
AnnaBridge 171:3a7713b1edbc 17096 /******************************** SDMMC Instances *******************************/
AnnaBridge 171:3a7713b1edbc 17097 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
AnnaBridge 171:3a7713b1edbc 17098
AnnaBridge 171:3a7713b1edbc 17099 /****************************** SPDIFRX Instances *********************************/
AnnaBridge 171:3a7713b1edbc 17100 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
AnnaBridge 171:3a7713b1edbc 17101
AnnaBridge 171:3a7713b1edbc 17102 /******************************** SPI Instances *******************************/
AnnaBridge 171:3a7713b1edbc 17103 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
AnnaBridge 171:3a7713b1edbc 17104 ((__INSTANCE__) == SPI2) || \
AnnaBridge 171:3a7713b1edbc 17105 ((__INSTANCE__) == SPI3) || \
AnnaBridge 171:3a7713b1edbc 17106 ((__INSTANCE__) == SPI4) || \
AnnaBridge 171:3a7713b1edbc 17107 ((__INSTANCE__) == SPI5) || \
AnnaBridge 171:3a7713b1edbc 17108 ((__INSTANCE__) == SPI6))
AnnaBridge 171:3a7713b1edbc 17109
AnnaBridge 171:3a7713b1edbc 17110 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 171:3a7713b1edbc 17111 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17112 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17113 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17114 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17115 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17116 ((__INSTANCE__) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 17117 ((__INSTANCE__) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 17118 ((__INSTANCE__) == TIM8) || \
AnnaBridge 171:3a7713b1edbc 17119 ((__INSTANCE__) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 17120 ((__INSTANCE__) == TIM10) || \
AnnaBridge 171:3a7713b1edbc 17121 ((__INSTANCE__) == TIM11) || \
AnnaBridge 171:3a7713b1edbc 17122 ((__INSTANCE__) == TIM12) || \
AnnaBridge 171:3a7713b1edbc 17123 ((__INSTANCE__) == TIM13) || \
AnnaBridge 171:3a7713b1edbc 17124 ((__INSTANCE__) == TIM14))
AnnaBridge 171:3a7713b1edbc 17125
AnnaBridge 171:3a7713b1edbc 17126 /****************** TIM Instances : supporting 32 bits counter ****************/
AnnaBridge 171:3a7713b1edbc 17127 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17128 ((__INSTANCE__) == TIM5))
AnnaBridge 171:3a7713b1edbc 17129
AnnaBridge 171:3a7713b1edbc 17130 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 171:3a7713b1edbc 17131 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17132 ((INSTANCE) == TIM8))
AnnaBridge 171:3a7713b1edbc 17133
AnnaBridge 171:3a7713b1edbc 17134 /************** TIM Instances : supporting Break source selection *************/
AnnaBridge 171:3a7713b1edbc 17135 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17136 ((INSTANCE) == TIM8))
AnnaBridge 171:3a7713b1edbc 17137
AnnaBridge 171:3a7713b1edbc 17138 /****************** TIM Instances : supporting 2 break inputs *****************/
AnnaBridge 171:3a7713b1edbc 17139 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17140 ((INSTANCE) == TIM8))
AnnaBridge 171:3a7713b1edbc 17141
AnnaBridge 171:3a7713b1edbc 17142 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 171:3a7713b1edbc 17143 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17144 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17145 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17146 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17147 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17148 ((__INSTANCE__) == TIM8) || \
AnnaBridge 171:3a7713b1edbc 17149 ((__INSTANCE__) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 17150 ((__INSTANCE__) == TIM10) || \
AnnaBridge 171:3a7713b1edbc 17151 ((__INSTANCE__) == TIM11) || \
AnnaBridge 171:3a7713b1edbc 17152 ((__INSTANCE__) == TIM12) || \
AnnaBridge 171:3a7713b1edbc 17153 ((__INSTANCE__) == TIM13) || \
AnnaBridge 171:3a7713b1edbc 17154 ((__INSTANCE__) == TIM14))
AnnaBridge 171:3a7713b1edbc 17155
AnnaBridge 171:3a7713b1edbc 17156 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 17157 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17158 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17159 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17160 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17161 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17162 ((__INSTANCE__) == TIM8) || \
AnnaBridge 171:3a7713b1edbc 17163 ((__INSTANCE__) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 17164 ((__INSTANCE__) == TIM12))
AnnaBridge 171:3a7713b1edbc 17165
AnnaBridge 171:3a7713b1edbc 17166 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 17167 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17168 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17169 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17170 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17171 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17172 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17173
AnnaBridge 171:3a7713b1edbc 17174 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 171:3a7713b1edbc 17175 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17176 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17177 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17178 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17179 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17180 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17181
AnnaBridge 171:3a7713b1edbc 17182 /****************** TIM Instances : at least 5 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 17183 #define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17184 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17185
AnnaBridge 171:3a7713b1edbc 17186 /****************** TIM Instances : at least 6 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 17187 #define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17188 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17189
AnnaBridge 171:3a7713b1edbc 17190 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
AnnaBridge 171:3a7713b1edbc 17191 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17192 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17193
AnnaBridge 171:3a7713b1edbc 17194 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
AnnaBridge 171:3a7713b1edbc 17195 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17196 ((__INSTANCE__) == TIM8) || \
AnnaBridge 171:3a7713b1edbc 17197 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17198 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17199 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17200 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17201 ((__INSTANCE__) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 17202 ((__INSTANCE__) == TIM7))
AnnaBridge 171:3a7713b1edbc 17203
AnnaBridge 171:3a7713b1edbc 17204 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 171:3a7713b1edbc 17205 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17206 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17207 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17208 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17209 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17210 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17211
AnnaBridge 171:3a7713b1edbc 17212 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 171:3a7713b1edbc 17213 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17214 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17215 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17216 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17217 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17218 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17219
AnnaBridge 171:3a7713b1edbc 17220 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
AnnaBridge 171:3a7713b1edbc 17221 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
AnnaBridge 171:3a7713b1edbc 17222 (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17223 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17224
AnnaBridge 171:3a7713b1edbc 17225 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 171:3a7713b1edbc 17226 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17227 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17228 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17229 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17230 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17231 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17232
AnnaBridge 171:3a7713b1edbc 17233 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 171:3a7713b1edbc 17234 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17235 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17236 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17237 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17238 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17239 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17240
AnnaBridge 171:3a7713b1edbc 17241 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 171:3a7713b1edbc 17242 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
AnnaBridge 171:3a7713b1edbc 17243 (((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17244 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17245 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17246 ((__INSTANCE__) == TIM5))
AnnaBridge 171:3a7713b1edbc 17247
AnnaBridge 171:3a7713b1edbc 17248 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
AnnaBridge 171:3a7713b1edbc 17249 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
AnnaBridge 171:3a7713b1edbc 17250 (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17251 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17252 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17253 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17254 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17255 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17256
AnnaBridge 171:3a7713b1edbc 17257 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
AnnaBridge 171:3a7713b1edbc 17258 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
AnnaBridge 171:3a7713b1edbc 17259 (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17260 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17261 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17262 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17263 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17264 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17265
AnnaBridge 171:3a7713b1edbc 17266 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 171:3a7713b1edbc 17267 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17268 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17269
AnnaBridge 171:3a7713b1edbc 17270 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 171:3a7713b1edbc 17271 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17272 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17273 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17274 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17275 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17276 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17277
AnnaBridge 171:3a7713b1edbc 17278 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 171:3a7713b1edbc 17279 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17280 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17281 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17282 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17283 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17284 ((__INSTANCE__) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 17285 ((__INSTANCE__) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 17286 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17287
AnnaBridge 171:3a7713b1edbc 17288 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 171:3a7713b1edbc 17289 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17290 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17291 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17292 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17293 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17294 ((__INSTANCE__) == TIM8) || \
AnnaBridge 171:3a7713b1edbc 17295 ((__INSTANCE__) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 17296 ((__INSTANCE__) == TIM12))
AnnaBridge 171:3a7713b1edbc 17297
AnnaBridge 171:3a7713b1edbc 17298 /***************** TIM Instances : external trigger input available ************/
AnnaBridge 171:3a7713b1edbc 17299 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17300 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17301 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17302 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17303 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17304 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17305
AnnaBridge 171:3a7713b1edbc 17306 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 171:3a7713b1edbc 17307 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17308 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17309 ((__INSTANCE__) == TIM11))
AnnaBridge 171:3a7713b1edbc 17310
AnnaBridge 171:3a7713b1edbc 17311 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 171:3a7713b1edbc 17312 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
AnnaBridge 171:3a7713b1edbc 17313 ((((__INSTANCE__) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 17314 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17315 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 17316 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 17317 ((__CHANNEL__) == TIM_CHANNEL_4) || \
AnnaBridge 171:3a7713b1edbc 17318 ((__CHANNEL__) == TIM_CHANNEL_5) || \
AnnaBridge 171:3a7713b1edbc 17319 ((__CHANNEL__) == TIM_CHANNEL_6))) \
AnnaBridge 171:3a7713b1edbc 17320 || \
AnnaBridge 171:3a7713b1edbc 17321 (((__INSTANCE__) == TIM2) && \
AnnaBridge 171:3a7713b1edbc 17322 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17323 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 17324 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 17325 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 17326 || \
AnnaBridge 171:3a7713b1edbc 17327 (((__INSTANCE__) == TIM3) && \
AnnaBridge 171:3a7713b1edbc 17328 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17329 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 17330 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 17331 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 17332 || \
AnnaBridge 171:3a7713b1edbc 17333 (((__INSTANCE__) == TIM4) && \
AnnaBridge 171:3a7713b1edbc 17334 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17335 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 17336 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 17337 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 17338 || \
AnnaBridge 171:3a7713b1edbc 17339 (((__INSTANCE__) == TIM5) && \
AnnaBridge 171:3a7713b1edbc 17340 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17341 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 17342 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 17343 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 17344 || \
AnnaBridge 171:3a7713b1edbc 17345 (((__INSTANCE__) == TIM8) && \
AnnaBridge 171:3a7713b1edbc 17346 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17347 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 17348 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 17349 ((__CHANNEL__) == TIM_CHANNEL_4) || \
AnnaBridge 171:3a7713b1edbc 17350 ((__CHANNEL__) == TIM_CHANNEL_5) || \
AnnaBridge 171:3a7713b1edbc 17351 ((__CHANNEL__) == TIM_CHANNEL_6))) \
AnnaBridge 171:3a7713b1edbc 17352 || \
AnnaBridge 171:3a7713b1edbc 17353 (((__INSTANCE__) == TIM9) && \
AnnaBridge 171:3a7713b1edbc 17354 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17355 ((__CHANNEL__) == TIM_CHANNEL_2))) \
AnnaBridge 171:3a7713b1edbc 17356 || \
AnnaBridge 171:3a7713b1edbc 17357 (((__INSTANCE__) == TIM10) && \
AnnaBridge 171:3a7713b1edbc 17358 (((__CHANNEL__) == TIM_CHANNEL_1))) \
AnnaBridge 171:3a7713b1edbc 17359 || \
AnnaBridge 171:3a7713b1edbc 17360 (((__INSTANCE__) == TIM11) && \
AnnaBridge 171:3a7713b1edbc 17361 (((__CHANNEL__) == TIM_CHANNEL_1))) \
AnnaBridge 171:3a7713b1edbc 17362 || \
AnnaBridge 171:3a7713b1edbc 17363 (((__INSTANCE__) == TIM12) && \
AnnaBridge 171:3a7713b1edbc 17364 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17365 ((__CHANNEL__) == TIM_CHANNEL_2))) \
AnnaBridge 171:3a7713b1edbc 17366 || \
AnnaBridge 171:3a7713b1edbc 17367 (((__INSTANCE__) == TIM13) && \
AnnaBridge 171:3a7713b1edbc 17368 (((__CHANNEL__) == TIM_CHANNEL_1))) \
AnnaBridge 171:3a7713b1edbc 17369 || \
AnnaBridge 171:3a7713b1edbc 17370 (((__INSTANCE__) == TIM14) && \
AnnaBridge 171:3a7713b1edbc 17371 (((__CHANNEL__) == TIM_CHANNEL_1))))
AnnaBridge 171:3a7713b1edbc 17372
AnnaBridge 171:3a7713b1edbc 17373 /************ TIM Instances : complementary output(s) available ***************/
AnnaBridge 171:3a7713b1edbc 17374 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
AnnaBridge 171:3a7713b1edbc 17375 ((((__INSTANCE__) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 17376 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17377 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 17378 ((__CHANNEL__) == TIM_CHANNEL_3))) \
AnnaBridge 171:3a7713b1edbc 17379 || \
AnnaBridge 171:3a7713b1edbc 17380 (((__INSTANCE__) == TIM8) && \
AnnaBridge 171:3a7713b1edbc 17381 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 17382 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 17383 ((__CHANNEL__) == TIM_CHANNEL_3))))
AnnaBridge 171:3a7713b1edbc 17384
AnnaBridge 171:3a7713b1edbc 17385 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
AnnaBridge 171:3a7713b1edbc 17386 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
AnnaBridge 171:3a7713b1edbc 17387 (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17388 ((__INSTANCE__) == TIM8) )
AnnaBridge 171:3a7713b1edbc 17389
AnnaBridge 171:3a7713b1edbc 17390 /****************** TIM Instances : supporting synchronization ****************/
AnnaBridge 171:3a7713b1edbc 17391 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
AnnaBridge 171:3a7713b1edbc 17392 (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17393 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17394 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17395 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17396 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17397 ((__INSTANCE__) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 17398 ((__INSTANCE__) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 17399 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17400
AnnaBridge 171:3a7713b1edbc 17401 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 171:3a7713b1edbc 17402 #define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17403 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17404 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17405 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17406 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17407 ((__INSTANCE__) == TIM8) || \
AnnaBridge 171:3a7713b1edbc 17408 ((__INSTANCE__) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 17409 ((__INSTANCE__) == TIM10) || \
AnnaBridge 171:3a7713b1edbc 17410 ((__INSTANCE__) == TIM11) || \
AnnaBridge 171:3a7713b1edbc 17411 ((__INSTANCE__) == TIM12) || \
AnnaBridge 171:3a7713b1edbc 17412 ((__INSTANCE__) == TIM13) || \
AnnaBridge 171:3a7713b1edbc 17413 ((__INSTANCE__) == TIM14))
AnnaBridge 171:3a7713b1edbc 17414
AnnaBridge 171:3a7713b1edbc 17415 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 171:3a7713b1edbc 17416 #define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17417 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17418
AnnaBridge 171:3a7713b1edbc 17419 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 171:3a7713b1edbc 17420 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17421 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17422 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17423 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17424 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17425 ((__INSTANCE__) == TIM8) || \
AnnaBridge 171:3a7713b1edbc 17426 ((__INSTANCE__) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 17427 ((__INSTANCE__) == TIM12))
AnnaBridge 171:3a7713b1edbc 17428
AnnaBridge 171:3a7713b1edbc 17429 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 171:3a7713b1edbc 17430 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17431 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17432 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17433 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17434 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17435 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17436
AnnaBridge 171:3a7713b1edbc 17437 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 171:3a7713b1edbc 17438 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17439 ((__INSTANCE__) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 17440 ((__INSTANCE__) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 17441 ((__INSTANCE__) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 17442 ((__INSTANCE__) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 17443 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17444
AnnaBridge 171:3a7713b1edbc 17445 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 171:3a7713b1edbc 17446 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 17447 ((__INSTANCE__) == TIM8))
AnnaBridge 171:3a7713b1edbc 17448
AnnaBridge 171:3a7713b1edbc 17449 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 17450 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17451 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17452 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17453 ((__INSTANCE__) == USART6))
AnnaBridge 171:3a7713b1edbc 17454
AnnaBridge 171:3a7713b1edbc 17455 /******************** UART Instances : Asynchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 17456 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17457 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17458 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17459 ((__INSTANCE__) == UART4) || \
AnnaBridge 171:3a7713b1edbc 17460 ((__INSTANCE__) == UART5) || \
AnnaBridge 171:3a7713b1edbc 17461 ((__INSTANCE__) == USART6) || \
AnnaBridge 171:3a7713b1edbc 17462 ((__INSTANCE__) == UART7) || \
AnnaBridge 171:3a7713b1edbc 17463 ((__INSTANCE__) == UART8))
AnnaBridge 171:3a7713b1edbc 17464
AnnaBridge 171:3a7713b1edbc 17465 /****************** UART Instances : Auto Baud Rate detection ****************/
AnnaBridge 171:3a7713b1edbc 17466 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17467 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17468 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17469 ((__INSTANCE__) == USART6))
AnnaBridge 171:3a7713b1edbc 17470
AnnaBridge 171:3a7713b1edbc 17471 /****************** UART Instances : Driver Enable *****************/
AnnaBridge 171:3a7713b1edbc 17472 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17473 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17474 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17475 ((__INSTANCE__) == UART4) || \
AnnaBridge 171:3a7713b1edbc 17476 ((__INSTANCE__) == UART5) || \
AnnaBridge 171:3a7713b1edbc 17477 ((__INSTANCE__) == USART6) || \
AnnaBridge 171:3a7713b1edbc 17478 ((__INSTANCE__) == UART7) || \
AnnaBridge 171:3a7713b1edbc 17479 ((__INSTANCE__) == UART8))
AnnaBridge 171:3a7713b1edbc 17480
AnnaBridge 171:3a7713b1edbc 17481 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 171:3a7713b1edbc 17482 #define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17483 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17484 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17485 ((__INSTANCE__) == UART4) || \
AnnaBridge 171:3a7713b1edbc 17486 ((__INSTANCE__) == UART5) || \
AnnaBridge 171:3a7713b1edbc 17487 ((__INSTANCE__) == USART6) || \
AnnaBridge 171:3a7713b1edbc 17488 ((__INSTANCE__) == UART7) || \
AnnaBridge 171:3a7713b1edbc 17489 ((__INSTANCE__) == UART8))
AnnaBridge 171:3a7713b1edbc 17490
AnnaBridge 171:3a7713b1edbc 17491 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 171:3a7713b1edbc 17492 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17493 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17494 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17495 ((__INSTANCE__) == UART4) || \
AnnaBridge 171:3a7713b1edbc 17496 ((__INSTANCE__) == UART5) || \
AnnaBridge 171:3a7713b1edbc 17497 ((__INSTANCE__) == USART6) || \
AnnaBridge 171:3a7713b1edbc 17498 ((__INSTANCE__) == UART7) || \
AnnaBridge 171:3a7713b1edbc 17499 ((__INSTANCE__) == UART8))
AnnaBridge 171:3a7713b1edbc 17500
AnnaBridge 171:3a7713b1edbc 17501 /******************** UART Instances : LIN mode **********************/
AnnaBridge 171:3a7713b1edbc 17502 #define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17503 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17504 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17505 ((__INSTANCE__) == UART4) || \
AnnaBridge 171:3a7713b1edbc 17506 ((__INSTANCE__) == UART5) || \
AnnaBridge 171:3a7713b1edbc 17507 ((__INSTANCE__) == USART6) || \
AnnaBridge 171:3a7713b1edbc 17508 ((__INSTANCE__) == UART7) || \
AnnaBridge 171:3a7713b1edbc 17509 ((__INSTANCE__) == UART8))
AnnaBridge 171:3a7713b1edbc 17510
AnnaBridge 171:3a7713b1edbc 17511 /********************* UART Instances : Smart card mode ***********************/
AnnaBridge 171:3a7713b1edbc 17512 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17513 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17514 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17515 ((__INSTANCE__) == USART6))
AnnaBridge 171:3a7713b1edbc 17516
AnnaBridge 171:3a7713b1edbc 17517 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 171:3a7713b1edbc 17518 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 171:3a7713b1edbc 17519 ((__INSTANCE__) == USART2) || \
AnnaBridge 171:3a7713b1edbc 17520 ((__INSTANCE__) == USART3) || \
AnnaBridge 171:3a7713b1edbc 17521 ((__INSTANCE__) == UART4) || \
AnnaBridge 171:3a7713b1edbc 17522 ((__INSTANCE__) == UART5) || \
AnnaBridge 171:3a7713b1edbc 17523 ((__INSTANCE__) == USART6) || \
AnnaBridge 171:3a7713b1edbc 17524 ((__INSTANCE__) == UART7) || \
AnnaBridge 171:3a7713b1edbc 17525 ((__INSTANCE__) == UART8))
AnnaBridge 171:3a7713b1edbc 17526
AnnaBridge 171:3a7713b1edbc 17527 /****************************** IWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 17528 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
AnnaBridge 171:3a7713b1edbc 17529
AnnaBridge 171:3a7713b1edbc 17530 /****************************** WWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 17531 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
AnnaBridge 171:3a7713b1edbc 17532
AnnaBridge 171:3a7713b1edbc 17533
AnnaBridge 171:3a7713b1edbc 17534 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 17535 /* For a painless codes migration between the STM32F7xx device product */
AnnaBridge 171:3a7713b1edbc 17536 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 171:3a7713b1edbc 17537 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 171:3a7713b1edbc 17538 /* No need to update developed interrupt code when moving across */
AnnaBridge 171:3a7713b1edbc 17539 /* product lines within the same STM32F7 Family */
AnnaBridge 171:3a7713b1edbc 17540 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 17541
AnnaBridge 171:3a7713b1edbc 17542 /* Aliases for __IRQn */
AnnaBridge 171:3a7713b1edbc 17543 #define HASH_RNG_IRQn RNG_IRQn
AnnaBridge 171:3a7713b1edbc 17544
AnnaBridge 171:3a7713b1edbc 17545 /* Aliases for __IRQHandler */
AnnaBridge 171:3a7713b1edbc 17546 #define HASH_RNG_IRQHandler RNG_IRQHandler
AnnaBridge 171:3a7713b1edbc 17547
AnnaBridge 171:3a7713b1edbc 17548 /**
AnnaBridge 171:3a7713b1edbc 17549 * @}
AnnaBridge 171:3a7713b1edbc 17550 */
AnnaBridge 171:3a7713b1edbc 17551
AnnaBridge 171:3a7713b1edbc 17552 /**
AnnaBridge 171:3a7713b1edbc 17553 * @}
AnnaBridge 171:3a7713b1edbc 17554 */
AnnaBridge 171:3a7713b1edbc 17555
AnnaBridge 171:3a7713b1edbc 17556 /**
AnnaBridge 171:3a7713b1edbc 17557 * @}
AnnaBridge 171:3a7713b1edbc 17558 */
AnnaBridge 171:3a7713b1edbc 17559
AnnaBridge 171:3a7713b1edbc 17560 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 17561 }
AnnaBridge 171:3a7713b1edbc 17562 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 17563
AnnaBridge 171:3a7713b1edbc 17564 #endif /* __STM32F746xx_H */
AnnaBridge 171:3a7713b1edbc 17565
AnnaBridge 171:3a7713b1edbc 17566
AnnaBridge 171:3a7713b1edbc 17567 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/