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TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f7xx_ll_system.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_ll_system.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of SYSTEM LL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | @verbatim |
| AnnaBridge | 171:3a7713b1edbc | 7 | ============================================================================== |
| AnnaBridge | 171:3a7713b1edbc | 8 | ##### How to use this driver ##### |
| AnnaBridge | 171:3a7713b1edbc | 9 | ============================================================================== |
| AnnaBridge | 171:3a7713b1edbc | 10 | [..] |
| AnnaBridge | 171:3a7713b1edbc | 11 | The LL SYSTEM driver contains a set of generic APIs that can be |
| AnnaBridge | 171:3a7713b1edbc | 12 | used by user: |
| AnnaBridge | 171:3a7713b1edbc | 13 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
| AnnaBridge | 171:3a7713b1edbc | 14 | (+) Access to DBGCMU registers |
| AnnaBridge | 171:3a7713b1edbc | 15 | (+) Access to SYSCFG registers |
| AnnaBridge | 171:3a7713b1edbc | 16 | |
| AnnaBridge | 171:3a7713b1edbc | 17 | @endverbatim |
| AnnaBridge | 171:3a7713b1edbc | 18 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 19 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 20 | * |
| AnnaBridge | 171:3a7713b1edbc | 21 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 22 | * |
| AnnaBridge | 171:3a7713b1edbc | 23 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 24 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 25 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 26 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 27 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 29 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 31 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 32 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 33 | * |
| AnnaBridge | 171:3a7713b1edbc | 34 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 35 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 36 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 37 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 38 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 39 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 40 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 41 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 42 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 43 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 44 | * |
| AnnaBridge | 171:3a7713b1edbc | 45 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 46 | */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | |
| AnnaBridge | 171:3a7713b1edbc | 48 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 49 | #ifndef __STM32F7xx_LL_SYSTEM_H |
| AnnaBridge | 171:3a7713b1edbc | 50 | #define __STM32F7xx_LL_SYSTEM_H |
| AnnaBridge | 171:3a7713b1edbc | 51 | |
| AnnaBridge | 171:3a7713b1edbc | 52 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 53 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 54 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 55 | |
| AnnaBridge | 171:3a7713b1edbc | 56 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 57 | #include "stm32f7xx.h" |
| AnnaBridge | 171:3a7713b1edbc | 58 | |
| AnnaBridge | 171:3a7713b1edbc | 59 | /** @addtogroup STM32F7xx_LL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 61 | */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | |
| AnnaBridge | 171:3a7713b1edbc | 63 | #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) |
| AnnaBridge | 171:3a7713b1edbc | 64 | |
| AnnaBridge | 171:3a7713b1edbc | 65 | /** @defgroup SYSTEM_LL SYSTEM |
| AnnaBridge | 171:3a7713b1edbc | 66 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 67 | */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | |
| AnnaBridge | 171:3a7713b1edbc | 69 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 70 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 71 | |
| AnnaBridge | 171:3a7713b1edbc | 72 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 73 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
| AnnaBridge | 171:3a7713b1edbc | 74 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 75 | */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | /** |
| AnnaBridge | 171:3a7713b1edbc | 78 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 79 | */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | |
| AnnaBridge | 171:3a7713b1edbc | 81 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 82 | |
| AnnaBridge | 171:3a7713b1edbc | 83 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 84 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 85 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 86 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 87 | */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | |
| AnnaBridge | 171:3a7713b1edbc | 89 | /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP |
| AnnaBridge | 171:3a7713b1edbc | 90 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 91 | */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define LL_SYSCFG_REMAP_BOOT0 0x00000000U /*!< Boot information after Reset */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define LL_SYSCFG_REMAP_BOOT1 SYSCFG_MEMRMP_MEM_BOOT /*!< Boot information after Reset */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | /** |
| AnnaBridge | 171:3a7713b1edbc | 95 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 96 | */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | |
| AnnaBridge | 171:3a7713b1edbc | 98 | |
| AnnaBridge | 171:3a7713b1edbc | 99 | #if defined(SYSCFG_MEMRMP_SWP_FB) |
| AnnaBridge | 171:3a7713b1edbc | 100 | /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE |
| AnnaBridge | 171:3a7713b1edbc | 101 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 102 | */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM) |
| AnnaBridge | 171:3a7713b1edbc | 104 | and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/ |
| AnnaBridge | 171:3a7713b1edbc | 105 | |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_SWP_FB /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM) |
| AnnaBridge | 171:3a7713b1edbc | 107 | and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | /** |
| AnnaBridge | 171:3a7713b1edbc | 109 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 110 | */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #endif /* SYSCFG_MEMRMP_SWP_FB */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | |
| AnnaBridge | 171:3a7713b1edbc | 113 | #if defined(SYSCFG_PMC_MII_RMII_SEL) |
| AnnaBridge | 171:3a7713b1edbc | 114 | /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC |
| AnnaBridge | 171:3a7713b1edbc | 115 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 116 | */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define LL_SYSCFG_PMC_ETHMII 0x00000000U /*!< ETH Media MII interface */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | |
| AnnaBridge | 171:3a7713b1edbc | 120 | /** |
| AnnaBridge | 171:3a7713b1edbc | 121 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 122 | */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #endif /* SYSCFG_PMC_MII_RMII_SEL */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | |
| AnnaBridge | 171:3a7713b1edbc | 125 | /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS |
| AnnaBridge | 171:3a7713b1edbc | 126 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 127 | */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #if defined(SYSCFG_PMC_I2C1_FMP) |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #endif /* SYSCFG_PMC_I2C1_FMP */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #if defined(SYSCFG_PMC_I2C4_FMP) |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #endif /* SYSCFG_PMC_I2C4_FMP */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #if defined(SYSCFG_PMC_I2C_PB6_FMP) |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #endif /* SYSCFG_PMC_I2C_PB6_FMP */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | /** |
| AnnaBridge | 171:3a7713b1edbc | 143 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 144 | */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | |
| AnnaBridge | 171:3a7713b1edbc | 146 | /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT |
| AnnaBridge | 171:3a7713b1edbc | 147 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 148 | */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #if defined(GPIOF) |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #endif /* GPIOF */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #if defined(GPIOG) |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #endif /* GPIOG */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #if defined(GPIOI) |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #endif /* GPIOI */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #if defined(GPIOJ) |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #endif /* GPIOJ */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #if defined(GPIOK) |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #endif /* GPIOK */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | /** |
| AnnaBridge | 171:3a7713b1edbc | 171 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 172 | */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | |
| AnnaBridge | 171:3a7713b1edbc | 174 | /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE |
| AnnaBridge | 171:3a7713b1edbc | 175 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 176 | */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define LL_SYSCFG_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define LL_SYSCFG_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define LL_SYSCFG_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define LL_SYSCFG_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define LL_SYSCFG_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define LL_SYSCFG_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define LL_SYSCFG_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define LL_SYSCFG_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define LL_SYSCFG_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define LL_SYSCFG_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define LL_SYSCFG_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define LL_SYSCFG_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define LL_SYSCFG_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define LL_SYSCFG_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define LL_SYSCFG_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define LL_SYSCFG_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | /** |
| AnnaBridge | 171:3a7713b1edbc | 194 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 195 | */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | |
| AnnaBridge | 171:3a7713b1edbc | 197 | /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK |
| AnnaBridge | 171:3a7713b1edbc | 198 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 199 | */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #if defined(SYSCFG_CBR_CLL) |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Lockup output (raised during core |
| AnnaBridge | 171:3a7713b1edbc | 202 | lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8 */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIMER1, TIMER8 Break input. |
| AnnaBridge | 171:3a7713b1edbc | 204 | It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits |
| AnnaBridge | 171:3a7713b1edbc | 205 | of the power controller */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #endif /* SYSCFG_CBR_CLL */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | /** |
| AnnaBridge | 171:3a7713b1edbc | 208 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 209 | */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | /** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD |
| AnnaBridge | 171:3a7713b1edbc | 211 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 212 | */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define LL_SYSCFG_DISABLE_CMP_PD 0x00000000U /*!< I/O compensation cell power-down mode */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define LL_SYSCFG_ENABLE_CMP_PD SYSCFG_CMPCR_CMP_PD /*!< I/O compensation cell enabled */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | /** |
| AnnaBridge | 171:3a7713b1edbc | 216 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 217 | */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | /** |
| AnnaBridge | 171:3a7713b1edbc | 219 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 220 | */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | |
| AnnaBridge | 171:3a7713b1edbc | 222 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
| AnnaBridge | 171:3a7713b1edbc | 223 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 224 | */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | /** |
| AnnaBridge | 171:3a7713b1edbc | 231 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 232 | */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | |
| AnnaBridge | 171:3a7713b1edbc | 234 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
| AnnaBridge | 171:3a7713b1edbc | 235 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 236 | */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIIM1 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT) |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP) |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/ |
| AnnaBridge | 171:3a7713b1edbc | 263 | /** |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 265 | */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | |
| AnnaBridge | 171:3a7713b1edbc | 267 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
| AnnaBridge | 171:3a7713b1edbc | 268 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 269 | */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | /** |
| AnnaBridge | 171:3a7713b1edbc | 276 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 277 | */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | |
| AnnaBridge | 171:3a7713b1edbc | 279 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
| AnnaBridge | 171:3a7713b1edbc | 280 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 281 | */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | /** |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 300 | */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | |
| AnnaBridge | 171:3a7713b1edbc | 302 | /** |
| AnnaBridge | 171:3a7713b1edbc | 303 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 304 | */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | |
| AnnaBridge | 171:3a7713b1edbc | 306 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 307 | |
| AnnaBridge | 171:3a7713b1edbc | 308 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 309 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 310 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 311 | */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | |
| AnnaBridge | 171:3a7713b1edbc | 313 | /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 315 | */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | |
| AnnaBridge | 171:3a7713b1edbc | 317 | /** |
| AnnaBridge | 171:3a7713b1edbc | 318 | * @brief Enables the FMC Memory Mapping Swapping |
| AnnaBridge | 171:3a7713b1edbc | 319 | * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping |
| AnnaBridge | 171:3a7713b1edbc | 320 | * @note SDRAM is accessible at 0x60000000 and NOR/RAM |
| AnnaBridge | 171:3a7713b1edbc | 321 | * is accessible at 0xC0000000 |
| AnnaBridge | 171:3a7713b1edbc | 322 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 323 | */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) |
| AnnaBridge | 171:3a7713b1edbc | 325 | { |
| AnnaBridge | 171:3a7713b1edbc | 326 | SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0); |
| AnnaBridge | 171:3a7713b1edbc | 327 | } |
| AnnaBridge | 171:3a7713b1edbc | 328 | |
| AnnaBridge | 171:3a7713b1edbc | 329 | /** |
| AnnaBridge | 171:3a7713b1edbc | 330 | * @brief Disables the FMC Memory Mapping Swapping |
| AnnaBridge | 171:3a7713b1edbc | 331 | * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping |
| AnnaBridge | 171:3a7713b1edbc | 332 | * @note SDRAM is accessible at 0xC0000000 (default mapping) |
| AnnaBridge | 171:3a7713b1edbc | 333 | * and NOR/RAM is accessible at 0x60000000 (default mapping) |
| AnnaBridge | 171:3a7713b1edbc | 334 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 335 | */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | __STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void) |
| AnnaBridge | 171:3a7713b1edbc | 337 | { |
| AnnaBridge | 171:3a7713b1edbc | 338 | CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC); |
| AnnaBridge | 171:3a7713b1edbc | 339 | } |
| AnnaBridge | 171:3a7713b1edbc | 340 | |
| AnnaBridge | 171:3a7713b1edbc | 341 | /** |
| AnnaBridge | 171:3a7713b1edbc | 342 | * @brief Enables the Compensation Cell |
| AnnaBridge | 171:3a7713b1edbc | 343 | * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell |
| AnnaBridge | 171:3a7713b1edbc | 344 | * @note The I/O compensation cell can be used only when the device supply |
| AnnaBridge | 171:3a7713b1edbc | 345 | * voltage ranges from 2.4 to 3.6 V |
| AnnaBridge | 171:3a7713b1edbc | 346 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 347 | */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) |
| AnnaBridge | 171:3a7713b1edbc | 349 | { |
| AnnaBridge | 171:3a7713b1edbc | 350 | SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); |
| AnnaBridge | 171:3a7713b1edbc | 351 | } |
| AnnaBridge | 171:3a7713b1edbc | 352 | |
| AnnaBridge | 171:3a7713b1edbc | 353 | /** |
| AnnaBridge | 171:3a7713b1edbc | 354 | * @brief Disables the Compensation Cell |
| AnnaBridge | 171:3a7713b1edbc | 355 | * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell |
| AnnaBridge | 171:3a7713b1edbc | 356 | * @note The I/O compensation cell can be used only when the device supply |
| AnnaBridge | 171:3a7713b1edbc | 357 | * voltage ranges from 2.4 to 3.6 V |
| AnnaBridge | 171:3a7713b1edbc | 358 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 359 | */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) |
| AnnaBridge | 171:3a7713b1edbc | 361 | { |
| AnnaBridge | 171:3a7713b1edbc | 362 | CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); |
| AnnaBridge | 171:3a7713b1edbc | 363 | } |
| AnnaBridge | 171:3a7713b1edbc | 364 | |
| AnnaBridge | 171:3a7713b1edbc | 365 | /** |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @brief Get Compensation Cell ready Flag |
| AnnaBridge | 171:3a7713b1edbc | 367 | * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR |
| AnnaBridge | 171:3a7713b1edbc | 368 | * @retval State of bit (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 369 | */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) |
| AnnaBridge | 171:3a7713b1edbc | 371 | { |
| AnnaBridge | 171:3a7713b1edbc | 372 | return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)); |
| AnnaBridge | 171:3a7713b1edbc | 373 | } |
| AnnaBridge | 171:3a7713b1edbc | 374 | |
| AnnaBridge | 171:3a7713b1edbc | 375 | |
| AnnaBridge | 171:3a7713b1edbc | 376 | /** |
| AnnaBridge | 171:3a7713b1edbc | 377 | * @brief Get the memory boot mapping as configured by user |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @rmtoll SYSCFG_MEMRMP MEM_BOOT LL_SYSCFG_GetRemapMemoryBoot |
| AnnaBridge | 171:3a7713b1edbc | 379 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 380 | * @arg @ref LL_SYSCFG_REMAP_BOOT0 |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @arg @ref LL_SYSCFG_REMAP_BOOT1 |
| AnnaBridge | 171:3a7713b1edbc | 382 | * |
| AnnaBridge | 171:3a7713b1edbc | 383 | * (*) value not defined in all devices |
| AnnaBridge | 171:3a7713b1edbc | 384 | */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void) |
| AnnaBridge | 171:3a7713b1edbc | 386 | { |
| AnnaBridge | 171:3a7713b1edbc | 387 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)); |
| AnnaBridge | 171:3a7713b1edbc | 388 | } |
| AnnaBridge | 171:3a7713b1edbc | 389 | |
| AnnaBridge | 171:3a7713b1edbc | 390 | #if defined(SYSCFG_PMC_MII_RMII_SEL) |
| AnnaBridge | 171:3a7713b1edbc | 391 | /** |
| AnnaBridge | 171:3a7713b1edbc | 392 | * @brief Select Ethernet PHY interface |
| AnnaBridge | 171:3a7713b1edbc | 393 | * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface |
| AnnaBridge | 171:3a7713b1edbc | 394 | * @param Interface This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 395 | * @arg @ref LL_SYSCFG_PMC_ETHMII |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @arg @ref LL_SYSCFG_PMC_ETHRMII |
| AnnaBridge | 171:3a7713b1edbc | 397 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 398 | */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) |
| AnnaBridge | 171:3a7713b1edbc | 400 | { |
| AnnaBridge | 171:3a7713b1edbc | 401 | MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface); |
| AnnaBridge | 171:3a7713b1edbc | 402 | } |
| AnnaBridge | 171:3a7713b1edbc | 403 | |
| AnnaBridge | 171:3a7713b1edbc | 404 | /** |
| AnnaBridge | 171:3a7713b1edbc | 405 | * @brief Get Ethernet PHY interface |
| AnnaBridge | 171:3a7713b1edbc | 406 | * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface |
| AnnaBridge | 171:3a7713b1edbc | 407 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 408 | * @arg @ref LL_SYSCFG_PMC_ETHMII |
| AnnaBridge | 171:3a7713b1edbc | 409 | * @arg @ref LL_SYSCFG_PMC_ETHRMII |
| AnnaBridge | 171:3a7713b1edbc | 410 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 411 | */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) |
| AnnaBridge | 171:3a7713b1edbc | 413 | { |
| AnnaBridge | 171:3a7713b1edbc | 414 | return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); |
| AnnaBridge | 171:3a7713b1edbc | 415 | } |
| AnnaBridge | 171:3a7713b1edbc | 416 | #endif /* SYSCFG_PMC_MII_RMII_SEL */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | |
| AnnaBridge | 171:3a7713b1edbc | 418 | |
| AnnaBridge | 171:3a7713b1edbc | 419 | #if defined(SYSCFG_MEMRMP_SWP_FB) |
| AnnaBridge | 171:3a7713b1edbc | 420 | /** |
| AnnaBridge | 171:3a7713b1edbc | 421 | * @brief Select Flash bank mode (Bank flashed at 0x08000000) |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode |
| AnnaBridge | 171:3a7713b1edbc | 423 | * @param Bank This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 424 | * @arg @ref LL_SYSCFG_BANKMODE_BANK1 |
| AnnaBridge | 171:3a7713b1edbc | 425 | * @arg @ref LL_SYSCFG_BANKMODE_BANK2 |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 427 | */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) |
| AnnaBridge | 171:3a7713b1edbc | 429 | { |
| AnnaBridge | 171:3a7713b1edbc | 430 | MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank); |
| AnnaBridge | 171:3a7713b1edbc | 431 | } |
| AnnaBridge | 171:3a7713b1edbc | 432 | |
| AnnaBridge | 171:3a7713b1edbc | 433 | /** |
| AnnaBridge | 171:3a7713b1edbc | 434 | * @brief Get Flash bank mode (Bank flashed at 0x08000000) |
| AnnaBridge | 171:3a7713b1edbc | 435 | * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode |
| AnnaBridge | 171:3a7713b1edbc | 436 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 437 | * @arg @ref LL_SYSCFG_BANKMODE_BANK1 |
| AnnaBridge | 171:3a7713b1edbc | 438 | * @arg @ref LL_SYSCFG_BANKMODE_BANK2 |
| AnnaBridge | 171:3a7713b1edbc | 439 | */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 441 | { |
| AnnaBridge | 171:3a7713b1edbc | 442 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB)); |
| AnnaBridge | 171:3a7713b1edbc | 443 | } |
| AnnaBridge | 171:3a7713b1edbc | 444 | |
| AnnaBridge | 171:3a7713b1edbc | 445 | #endif /* SYSCFG_MEMRMP_SWP_FB */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | |
| AnnaBridge | 171:3a7713b1edbc | 447 | #if defined(SYSCFG_PMC_I2C1_FMP) |
| AnnaBridge | 171:3a7713b1edbc | 448 | /** |
| AnnaBridge | 171:3a7713b1edbc | 449 | * @brief Enable the I2C fast mode plus driving capability. |
| AnnaBridge | 171:3a7713b1edbc | 450 | * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n |
| AnnaBridge | 171:3a7713b1edbc | 451 | * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_EnableFastModePlus |
| AnnaBridge | 171:3a7713b1edbc | 452 | * @param ConfigFastModePlus This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 453 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 |
| AnnaBridge | 171:3a7713b1edbc | 454 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 |
| AnnaBridge | 171:3a7713b1edbc | 455 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) |
| AnnaBridge | 171:3a7713b1edbc | 456 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) |
| AnnaBridge | 171:3a7713b1edbc | 457 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 458 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 459 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 460 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*) |
| AnnaBridge | 171:3a7713b1edbc | 461 | * |
| AnnaBridge | 171:3a7713b1edbc | 462 | * (*) value not defined in all devices |
| AnnaBridge | 171:3a7713b1edbc | 463 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 464 | */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) |
| AnnaBridge | 171:3a7713b1edbc | 466 | { |
| AnnaBridge | 171:3a7713b1edbc | 467 | SET_BIT(SYSCFG->PMC, ConfigFastModePlus); |
| AnnaBridge | 171:3a7713b1edbc | 468 | } |
| AnnaBridge | 171:3a7713b1edbc | 469 | |
| AnnaBridge | 171:3a7713b1edbc | 470 | /** |
| AnnaBridge | 171:3a7713b1edbc | 471 | * @brief Disable the I2C fast mode plus driving capability. |
| AnnaBridge | 171:3a7713b1edbc | 472 | * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n |
| AnnaBridge | 171:3a7713b1edbc | 473 | * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_DisableFastModePlus |
| AnnaBridge | 171:3a7713b1edbc | 474 | * @param ConfigFastModePlus This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 475 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 |
| AnnaBridge | 171:3a7713b1edbc | 476 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 |
| AnnaBridge | 171:3a7713b1edbc | 477 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) |
| AnnaBridge | 171:3a7713b1edbc | 478 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 480 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 482 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 |
| AnnaBridge | 171:3a7713b1edbc | 483 | * (*) value not defined in all devices |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 485 | */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) |
| AnnaBridge | 171:3a7713b1edbc | 487 | { |
| AnnaBridge | 171:3a7713b1edbc | 488 | CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus); |
| AnnaBridge | 171:3a7713b1edbc | 489 | } |
| AnnaBridge | 171:3a7713b1edbc | 490 | #endif /* SYSCFG_PMC_I2C1_FMP */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | |
| AnnaBridge | 171:3a7713b1edbc | 492 | |
| AnnaBridge | 171:3a7713b1edbc | 493 | /** |
| AnnaBridge | 171:3a7713b1edbc | 494 | * @brief Configure source input for the EXTI external interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 495 | * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n |
| AnnaBridge | 171:3a7713b1edbc | 496 | * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n |
| AnnaBridge | 171:3a7713b1edbc | 497 | * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n |
| AnnaBridge | 171:3a7713b1edbc | 498 | * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource |
| AnnaBridge | 171:3a7713b1edbc | 499 | * @param Port This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 500 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
| AnnaBridge | 171:3a7713b1edbc | 501 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
| AnnaBridge | 171:3a7713b1edbc | 502 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
| AnnaBridge | 171:3a7713b1edbc | 503 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
| AnnaBridge | 171:3a7713b1edbc | 504 | * @arg @ref LL_SYSCFG_EXTI_PORTE |
| AnnaBridge | 171:3a7713b1edbc | 505 | * @arg @ref LL_SYSCFG_EXTI_PORTF |
| AnnaBridge | 171:3a7713b1edbc | 506 | * @arg @ref LL_SYSCFG_EXTI_PORTG |
| AnnaBridge | 171:3a7713b1edbc | 507 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
| AnnaBridge | 171:3a7713b1edbc | 508 | * @arg @ref LL_SYSCFG_EXTI_PORTI |
| AnnaBridge | 171:3a7713b1edbc | 509 | * @arg @ref LL_SYSCFG_EXTI_PORTJ |
| AnnaBridge | 171:3a7713b1edbc | 510 | * @arg @ref LL_SYSCFG_EXTI_PORTK |
| AnnaBridge | 171:3a7713b1edbc | 511 | * |
| AnnaBridge | 171:3a7713b1edbc | 512 | * (*) value not defined in all devices |
| AnnaBridge | 171:3a7713b1edbc | 513 | * @param Line This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 514 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
| AnnaBridge | 171:3a7713b1edbc | 515 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
| AnnaBridge | 171:3a7713b1edbc | 516 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
| AnnaBridge | 171:3a7713b1edbc | 517 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
| AnnaBridge | 171:3a7713b1edbc | 518 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
| AnnaBridge | 171:3a7713b1edbc | 519 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
| AnnaBridge | 171:3a7713b1edbc | 520 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
| AnnaBridge | 171:3a7713b1edbc | 521 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
| AnnaBridge | 171:3a7713b1edbc | 522 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
| AnnaBridge | 171:3a7713b1edbc | 524 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
| AnnaBridge | 171:3a7713b1edbc | 525 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
| AnnaBridge | 171:3a7713b1edbc | 526 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
| AnnaBridge | 171:3a7713b1edbc | 527 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
| AnnaBridge | 171:3a7713b1edbc | 528 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
| AnnaBridge | 171:3a7713b1edbc | 529 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
| AnnaBridge | 171:3a7713b1edbc | 530 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 531 | */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) |
| AnnaBridge | 171:3a7713b1edbc | 533 | { |
| AnnaBridge | 171:3a7713b1edbc | 534 | MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); |
| AnnaBridge | 171:3a7713b1edbc | 535 | } |
| AnnaBridge | 171:3a7713b1edbc | 536 | |
| AnnaBridge | 171:3a7713b1edbc | 537 | /** |
| AnnaBridge | 171:3a7713b1edbc | 538 | * @brief Get the configured defined for specific EXTI Line |
| AnnaBridge | 171:3a7713b1edbc | 539 | * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n |
| AnnaBridge | 171:3a7713b1edbc | 540 | * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n |
| AnnaBridge | 171:3a7713b1edbc | 541 | * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n |
| AnnaBridge | 171:3a7713b1edbc | 542 | * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource |
| AnnaBridge | 171:3a7713b1edbc | 543 | * @param Line This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 544 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
| AnnaBridge | 171:3a7713b1edbc | 545 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
| AnnaBridge | 171:3a7713b1edbc | 546 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
| AnnaBridge | 171:3a7713b1edbc | 547 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
| AnnaBridge | 171:3a7713b1edbc | 548 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
| AnnaBridge | 171:3a7713b1edbc | 549 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
| AnnaBridge | 171:3a7713b1edbc | 550 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
| AnnaBridge | 171:3a7713b1edbc | 551 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
| AnnaBridge | 171:3a7713b1edbc | 552 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
| AnnaBridge | 171:3a7713b1edbc | 553 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
| AnnaBridge | 171:3a7713b1edbc | 554 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
| AnnaBridge | 171:3a7713b1edbc | 555 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
| AnnaBridge | 171:3a7713b1edbc | 556 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
| AnnaBridge | 171:3a7713b1edbc | 557 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
| AnnaBridge | 171:3a7713b1edbc | 558 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
| AnnaBridge | 171:3a7713b1edbc | 559 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
| AnnaBridge | 171:3a7713b1edbc | 560 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 561 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
| AnnaBridge | 171:3a7713b1edbc | 562 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
| AnnaBridge | 171:3a7713b1edbc | 563 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
| AnnaBridge | 171:3a7713b1edbc | 564 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
| AnnaBridge | 171:3a7713b1edbc | 565 | * @arg @ref LL_SYSCFG_EXTI_PORTE |
| AnnaBridge | 171:3a7713b1edbc | 566 | * @arg @ref LL_SYSCFG_EXTI_PORTF |
| AnnaBridge | 171:3a7713b1edbc | 567 | * @arg @ref LL_SYSCFG_EXTI_PORTG |
| AnnaBridge | 171:3a7713b1edbc | 568 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
| AnnaBridge | 171:3a7713b1edbc | 569 | * @arg @ref LL_SYSCFG_EXTI_PORTI |
| AnnaBridge | 171:3a7713b1edbc | 570 | * @arg @ref LL_SYSCFG_EXTI_PORTJ |
| AnnaBridge | 171:3a7713b1edbc | 571 | * @arg @ref LL_SYSCFG_EXTI_PORTK |
| AnnaBridge | 171:3a7713b1edbc | 572 | * (*) value not defined in all devices |
| AnnaBridge | 171:3a7713b1edbc | 573 | */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) |
| AnnaBridge | 171:3a7713b1edbc | 575 | { |
| AnnaBridge | 171:3a7713b1edbc | 576 | return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); |
| AnnaBridge | 171:3a7713b1edbc | 577 | } |
| AnnaBridge | 171:3a7713b1edbc | 578 | |
| AnnaBridge | 171:3a7713b1edbc | 579 | #if defined(SYSCFG_CBR_CLL) |
| AnnaBridge | 171:3a7713b1edbc | 580 | /** |
| AnnaBridge | 171:3a7713b1edbc | 581 | * @brief Set connections to TIM1/8/15/16/17 Break inputs |
| AnnaBridge | 171:3a7713b1edbc | 582 | * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs\n |
| AnnaBridge | 171:3a7713b1edbc | 583 | * SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs |
| AnnaBridge | 171:3a7713b1edbc | 584 | * @param Break This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 585 | * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP |
| AnnaBridge | 171:3a7713b1edbc | 586 | * @arg @ref LL_SYSCFG_TIMBREAK_PVD |
| AnnaBridge | 171:3a7713b1edbc | 587 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 588 | */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) |
| AnnaBridge | 171:3a7713b1edbc | 590 | { |
| AnnaBridge | 171:3a7713b1edbc | 591 | MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break); |
| AnnaBridge | 171:3a7713b1edbc | 592 | } |
| AnnaBridge | 171:3a7713b1edbc | 593 | |
| AnnaBridge | 171:3a7713b1edbc | 594 | /** |
| AnnaBridge | 171:3a7713b1edbc | 595 | * @brief Get connections to TIM1/8/15/16/17 Break inputs |
| AnnaBridge | 171:3a7713b1edbc | 596 | * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs\n |
| AnnaBridge | 171:3a7713b1edbc | 597 | * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs |
| AnnaBridge | 171:3a7713b1edbc | 598 | * @retval Returned value can be can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 599 | * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP |
| AnnaBridge | 171:3a7713b1edbc | 600 | * @arg @ref LL_SYSCFG_TIMBREAK_PVD |
| AnnaBridge | 171:3a7713b1edbc | 601 | */ |
| AnnaBridge | 171:3a7713b1edbc | 602 | __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) |
| AnnaBridge | 171:3a7713b1edbc | 603 | { |
| AnnaBridge | 171:3a7713b1edbc | 604 | return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL)); |
| AnnaBridge | 171:3a7713b1edbc | 605 | } |
| AnnaBridge | 171:3a7713b1edbc | 606 | #endif /* SYSCFG_CBR_CLL */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | |
| AnnaBridge | 171:3a7713b1edbc | 608 | /** |
| AnnaBridge | 171:3a7713b1edbc | 609 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 610 | */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | |
| AnnaBridge | 171:3a7713b1edbc | 612 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
| AnnaBridge | 171:3a7713b1edbc | 613 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 614 | */ |
| AnnaBridge | 171:3a7713b1edbc | 615 | |
| AnnaBridge | 171:3a7713b1edbc | 616 | /** |
| AnnaBridge | 171:3a7713b1edbc | 617 | * @brief Return the device identifier |
| AnnaBridge | 171:3a7713b1edbc | 618 | * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449 |
| AnnaBridge | 171:3a7713b1edbc | 619 | * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451 |
| AnnaBridge | 171:3a7713b1edbc | 620 | * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452 |
| AnnaBridge | 171:3a7713b1edbc | 621 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
| AnnaBridge | 171:3a7713b1edbc | 622 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
| AnnaBridge | 171:3a7713b1edbc | 623 | */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
| AnnaBridge | 171:3a7713b1edbc | 625 | { |
| AnnaBridge | 171:3a7713b1edbc | 626 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
| AnnaBridge | 171:3a7713b1edbc | 627 | } |
| AnnaBridge | 171:3a7713b1edbc | 628 | |
| AnnaBridge | 171:3a7713b1edbc | 629 | /** |
| AnnaBridge | 171:3a7713b1edbc | 630 | * @brief Return the device revision identifier |
| AnnaBridge | 171:3a7713b1edbc | 631 | * @note This field indicates the revision of the device. |
| AnnaBridge | 171:3a7713b1edbc | 632 | For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 |
| AnnaBridge | 171:3a7713b1edbc | 633 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
| AnnaBridge | 171:3a7713b1edbc | 634 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
| AnnaBridge | 171:3a7713b1edbc | 635 | */ |
| AnnaBridge | 171:3a7713b1edbc | 636 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
| AnnaBridge | 171:3a7713b1edbc | 637 | { |
| AnnaBridge | 171:3a7713b1edbc | 638 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
| AnnaBridge | 171:3a7713b1edbc | 639 | } |
| AnnaBridge | 171:3a7713b1edbc | 640 | |
| AnnaBridge | 171:3a7713b1edbc | 641 | /** |
| AnnaBridge | 171:3a7713b1edbc | 642 | * @brief Enable the Debug Module during SLEEP mode |
| AnnaBridge | 171:3a7713b1edbc | 643 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 645 | */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 647 | { |
| AnnaBridge | 171:3a7713b1edbc | 648 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| AnnaBridge | 171:3a7713b1edbc | 649 | } |
| AnnaBridge | 171:3a7713b1edbc | 650 | |
| AnnaBridge | 171:3a7713b1edbc | 651 | /** |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @brief Disable the Debug Module during SLEEP mode |
| AnnaBridge | 171:3a7713b1edbc | 653 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
| AnnaBridge | 171:3a7713b1edbc | 654 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 655 | */ |
| AnnaBridge | 171:3a7713b1edbc | 656 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 657 | { |
| AnnaBridge | 171:3a7713b1edbc | 658 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| AnnaBridge | 171:3a7713b1edbc | 659 | } |
| AnnaBridge | 171:3a7713b1edbc | 660 | |
| AnnaBridge | 171:3a7713b1edbc | 661 | /** |
| AnnaBridge | 171:3a7713b1edbc | 662 | * @brief Enable the Debug Module during STOP mode |
| AnnaBridge | 171:3a7713b1edbc | 663 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
| AnnaBridge | 171:3a7713b1edbc | 664 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 665 | */ |
| AnnaBridge | 171:3a7713b1edbc | 666 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 667 | { |
| AnnaBridge | 171:3a7713b1edbc | 668 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| AnnaBridge | 171:3a7713b1edbc | 669 | } |
| AnnaBridge | 171:3a7713b1edbc | 670 | |
| AnnaBridge | 171:3a7713b1edbc | 671 | /** |
| AnnaBridge | 171:3a7713b1edbc | 672 | * @brief Disable the Debug Module during STOP mode |
| AnnaBridge | 171:3a7713b1edbc | 673 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
| AnnaBridge | 171:3a7713b1edbc | 674 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 675 | */ |
| AnnaBridge | 171:3a7713b1edbc | 676 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 677 | { |
| AnnaBridge | 171:3a7713b1edbc | 678 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| AnnaBridge | 171:3a7713b1edbc | 679 | } |
| AnnaBridge | 171:3a7713b1edbc | 680 | |
| AnnaBridge | 171:3a7713b1edbc | 681 | /** |
| AnnaBridge | 171:3a7713b1edbc | 682 | * @brief Enable the Debug Module during STANDBY mode |
| AnnaBridge | 171:3a7713b1edbc | 683 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
| AnnaBridge | 171:3a7713b1edbc | 684 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 685 | */ |
| AnnaBridge | 171:3a7713b1edbc | 686 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 687 | { |
| AnnaBridge | 171:3a7713b1edbc | 688 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| AnnaBridge | 171:3a7713b1edbc | 689 | } |
| AnnaBridge | 171:3a7713b1edbc | 690 | |
| AnnaBridge | 171:3a7713b1edbc | 691 | /** |
| AnnaBridge | 171:3a7713b1edbc | 692 | * @brief Disable the Debug Module during STANDBY mode |
| AnnaBridge | 171:3a7713b1edbc | 693 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
| AnnaBridge | 171:3a7713b1edbc | 694 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 695 | */ |
| AnnaBridge | 171:3a7713b1edbc | 696 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
| AnnaBridge | 171:3a7713b1edbc | 697 | { |
| AnnaBridge | 171:3a7713b1edbc | 698 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| AnnaBridge | 171:3a7713b1edbc | 699 | } |
| AnnaBridge | 171:3a7713b1edbc | 700 | |
| AnnaBridge | 171:3a7713b1edbc | 701 | /** |
| AnnaBridge | 171:3a7713b1edbc | 702 | * @brief Set Trace pin assignment control |
| AnnaBridge | 171:3a7713b1edbc | 703 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
| AnnaBridge | 171:3a7713b1edbc | 704 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
| AnnaBridge | 171:3a7713b1edbc | 705 | * @param PinAssignment This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 706 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| AnnaBridge | 171:3a7713b1edbc | 707 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| AnnaBridge | 171:3a7713b1edbc | 708 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| AnnaBridge | 171:3a7713b1edbc | 709 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| AnnaBridge | 171:3a7713b1edbc | 710 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| AnnaBridge | 171:3a7713b1edbc | 711 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 712 | */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
| AnnaBridge | 171:3a7713b1edbc | 714 | { |
| AnnaBridge | 171:3a7713b1edbc | 715 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
| AnnaBridge | 171:3a7713b1edbc | 716 | } |
| AnnaBridge | 171:3a7713b1edbc | 717 | |
| AnnaBridge | 171:3a7713b1edbc | 718 | /** |
| AnnaBridge | 171:3a7713b1edbc | 719 | * @brief Get Trace pin assignment control |
| AnnaBridge | 171:3a7713b1edbc | 720 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
| AnnaBridge | 171:3a7713b1edbc | 721 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
| AnnaBridge | 171:3a7713b1edbc | 722 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 723 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| AnnaBridge | 171:3a7713b1edbc | 724 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| AnnaBridge | 171:3a7713b1edbc | 725 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| AnnaBridge | 171:3a7713b1edbc | 726 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| AnnaBridge | 171:3a7713b1edbc | 727 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| AnnaBridge | 171:3a7713b1edbc | 728 | */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
| AnnaBridge | 171:3a7713b1edbc | 730 | { |
| AnnaBridge | 171:3a7713b1edbc | 731 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
| AnnaBridge | 171:3a7713b1edbc | 732 | } |
| AnnaBridge | 171:3a7713b1edbc | 733 | |
| AnnaBridge | 171:3a7713b1edbc | 734 | /** |
| AnnaBridge | 171:3a7713b1edbc | 735 | * @brief Freeze APB1 peripherals (group1 peripherals) |
| AnnaBridge | 171:3a7713b1edbc | 736 | * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 737 | * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 738 | * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 739 | * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 740 | * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 741 | * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 742 | * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 743 | * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 744 | * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 745 | * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 746 | * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 747 | * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 748 | * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 749 | * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 750 | * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 751 | * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 752 | * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 753 | * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 754 | * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 755 | * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph |
| AnnaBridge | 171:3a7713b1edbc | 756 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 757 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| AnnaBridge | 171:3a7713b1edbc | 758 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| AnnaBridge | 171:3a7713b1edbc | 759 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| AnnaBridge | 171:3a7713b1edbc | 760 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
| AnnaBridge | 171:3a7713b1edbc | 761 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| AnnaBridge | 171:3a7713b1edbc | 762 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| AnnaBridge | 171:3a7713b1edbc | 763 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
| AnnaBridge | 171:3a7713b1edbc | 764 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
| AnnaBridge | 171:3a7713b1edbc | 765 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
| AnnaBridge | 171:3a7713b1edbc | 766 | * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 767 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
| AnnaBridge | 171:3a7713b1edbc | 768 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| AnnaBridge | 171:3a7713b1edbc | 769 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| AnnaBridge | 171:3a7713b1edbc | 770 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 771 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP |
| AnnaBridge | 171:3a7713b1edbc | 772 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP |
| AnnaBridge | 171:3a7713b1edbc | 773 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 774 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 775 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 776 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 777 | * |
| AnnaBridge | 171:3a7713b1edbc | 778 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 779 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 780 | */ |
| AnnaBridge | 171:3a7713b1edbc | 781 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 782 | { |
| AnnaBridge | 171:3a7713b1edbc | 783 | SET_BIT(DBGMCU->APB1FZ, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 784 | } |
| AnnaBridge | 171:3a7713b1edbc | 785 | |
| AnnaBridge | 171:3a7713b1edbc | 786 | /** |
| AnnaBridge | 171:3a7713b1edbc | 787 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
| AnnaBridge | 171:3a7713b1edbc | 788 | * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 789 | * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 790 | * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 791 | * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 792 | * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 793 | * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 794 | * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 795 | * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 796 | * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 797 | * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 798 | * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 799 | * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 800 | * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 801 | * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 802 | * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 803 | * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 804 | * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 805 | * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 806 | * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 807 | * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
| AnnaBridge | 171:3a7713b1edbc | 808 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 809 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| AnnaBridge | 171:3a7713b1edbc | 810 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| AnnaBridge | 171:3a7713b1edbc | 811 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| AnnaBridge | 171:3a7713b1edbc | 812 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
| AnnaBridge | 171:3a7713b1edbc | 813 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| AnnaBridge | 171:3a7713b1edbc | 814 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| AnnaBridge | 171:3a7713b1edbc | 815 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
| AnnaBridge | 171:3a7713b1edbc | 816 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
| AnnaBridge | 171:3a7713b1edbc | 817 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
| AnnaBridge | 171:3a7713b1edbc | 818 | * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 819 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
| AnnaBridge | 171:3a7713b1edbc | 820 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| AnnaBridge | 171:3a7713b1edbc | 821 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| AnnaBridge | 171:3a7713b1edbc | 822 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 823 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP |
| AnnaBridge | 171:3a7713b1edbc | 824 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP |
| AnnaBridge | 171:3a7713b1edbc | 825 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 826 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 827 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 828 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) |
| AnnaBridge | 171:3a7713b1edbc | 829 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 830 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 831 | */ |
| AnnaBridge | 171:3a7713b1edbc | 832 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 833 | { |
| AnnaBridge | 171:3a7713b1edbc | 834 | CLEAR_BIT(DBGMCU->APB1FZ, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 835 | } |
| AnnaBridge | 171:3a7713b1edbc | 836 | |
| AnnaBridge | 171:3a7713b1edbc | 837 | /** |
| AnnaBridge | 171:3a7713b1edbc | 838 | * @brief Freeze APB2 peripherals |
| AnnaBridge | 171:3a7713b1edbc | 839 | * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 840 | * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 841 | * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 842 | * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 843 | * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
| AnnaBridge | 171:3a7713b1edbc | 844 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 845 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 846 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP |
| AnnaBridge | 171:3a7713b1edbc | 847 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP |
| AnnaBridge | 171:3a7713b1edbc | 848 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP |
| AnnaBridge | 171:3a7713b1edbc | 849 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP |
| AnnaBridge | 171:3a7713b1edbc | 850 | * |
| AnnaBridge | 171:3a7713b1edbc | 851 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 852 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 853 | */ |
| AnnaBridge | 171:3a7713b1edbc | 854 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 855 | { |
| AnnaBridge | 171:3a7713b1edbc | 856 | SET_BIT(DBGMCU->APB2FZ, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 857 | } |
| AnnaBridge | 171:3a7713b1edbc | 858 | |
| AnnaBridge | 171:3a7713b1edbc | 859 | /** |
| AnnaBridge | 171:3a7713b1edbc | 860 | * @brief Unfreeze APB2 peripherals |
| AnnaBridge | 171:3a7713b1edbc | 861 | * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 862 | * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 863 | * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 864 | * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
| AnnaBridge | 171:3a7713b1edbc | 865 | * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph |
| AnnaBridge | 171:3a7713b1edbc | 866 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 867 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
| AnnaBridge | 171:3a7713b1edbc | 868 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP |
| AnnaBridge | 171:3a7713b1edbc | 869 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP |
| AnnaBridge | 171:3a7713b1edbc | 870 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP |
| AnnaBridge | 171:3a7713b1edbc | 871 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP |
| AnnaBridge | 171:3a7713b1edbc | 872 | * |
| AnnaBridge | 171:3a7713b1edbc | 873 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 874 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 875 | */ |
| AnnaBridge | 171:3a7713b1edbc | 876 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 877 | { |
| AnnaBridge | 171:3a7713b1edbc | 878 | CLEAR_BIT(DBGMCU->APB2FZ, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 879 | } |
| AnnaBridge | 171:3a7713b1edbc | 880 | /** |
| AnnaBridge | 171:3a7713b1edbc | 881 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 882 | */ |
| AnnaBridge | 171:3a7713b1edbc | 883 | |
| AnnaBridge | 171:3a7713b1edbc | 884 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
| AnnaBridge | 171:3a7713b1edbc | 885 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 886 | */ |
| AnnaBridge | 171:3a7713b1edbc | 887 | |
| AnnaBridge | 171:3a7713b1edbc | 888 | /** |
| AnnaBridge | 171:3a7713b1edbc | 889 | * @brief Set FLASH Latency |
| AnnaBridge | 171:3a7713b1edbc | 890 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
| AnnaBridge | 171:3a7713b1edbc | 891 | * @param Latency This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 892 | * @arg @ref LL_FLASH_LATENCY_0 |
| AnnaBridge | 171:3a7713b1edbc | 893 | * @arg @ref LL_FLASH_LATENCY_1 |
| AnnaBridge | 171:3a7713b1edbc | 894 | * @arg @ref LL_FLASH_LATENCY_2 |
| AnnaBridge | 171:3a7713b1edbc | 895 | * @arg @ref LL_FLASH_LATENCY_3 |
| AnnaBridge | 171:3a7713b1edbc | 896 | * @arg @ref LL_FLASH_LATENCY_4 |
| AnnaBridge | 171:3a7713b1edbc | 897 | * @arg @ref LL_FLASH_LATENCY_5 |
| AnnaBridge | 171:3a7713b1edbc | 898 | * @arg @ref LL_FLASH_LATENCY_6 |
| AnnaBridge | 171:3a7713b1edbc | 899 | * @arg @ref LL_FLASH_LATENCY_7 |
| AnnaBridge | 171:3a7713b1edbc | 900 | * @arg @ref LL_FLASH_LATENCY_8 |
| AnnaBridge | 171:3a7713b1edbc | 901 | * @arg @ref LL_FLASH_LATENCY_9 |
| AnnaBridge | 171:3a7713b1edbc | 902 | * @arg @ref LL_FLASH_LATENCY_10 |
| AnnaBridge | 171:3a7713b1edbc | 903 | * @arg @ref LL_FLASH_LATENCY_11 |
| AnnaBridge | 171:3a7713b1edbc | 904 | * @arg @ref LL_FLASH_LATENCY_12 |
| AnnaBridge | 171:3a7713b1edbc | 905 | * @arg @ref LL_FLASH_LATENCY_13 |
| AnnaBridge | 171:3a7713b1edbc | 906 | * @arg @ref LL_FLASH_LATENCY_14 |
| AnnaBridge | 171:3a7713b1edbc | 907 | * @arg @ref LL_FLASH_LATENCY_15 |
| AnnaBridge | 171:3a7713b1edbc | 908 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 909 | */ |
| AnnaBridge | 171:3a7713b1edbc | 910 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
| AnnaBridge | 171:3a7713b1edbc | 911 | { |
| AnnaBridge | 171:3a7713b1edbc | 912 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
| AnnaBridge | 171:3a7713b1edbc | 913 | } |
| AnnaBridge | 171:3a7713b1edbc | 914 | |
| AnnaBridge | 171:3a7713b1edbc | 915 | /** |
| AnnaBridge | 171:3a7713b1edbc | 916 | * @brief Get FLASH Latency |
| AnnaBridge | 171:3a7713b1edbc | 917 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
| AnnaBridge | 171:3a7713b1edbc | 918 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 919 | * @arg @ref LL_FLASH_LATENCY_0 |
| AnnaBridge | 171:3a7713b1edbc | 920 | * @arg @ref LL_FLASH_LATENCY_1 |
| AnnaBridge | 171:3a7713b1edbc | 921 | * @arg @ref LL_FLASH_LATENCY_2 |
| AnnaBridge | 171:3a7713b1edbc | 922 | * @arg @ref LL_FLASH_LATENCY_3 |
| AnnaBridge | 171:3a7713b1edbc | 923 | * @arg @ref LL_FLASH_LATENCY_4 |
| AnnaBridge | 171:3a7713b1edbc | 924 | * @arg @ref LL_FLASH_LATENCY_5 |
| AnnaBridge | 171:3a7713b1edbc | 925 | * @arg @ref LL_FLASH_LATENCY_6 |
| AnnaBridge | 171:3a7713b1edbc | 926 | * @arg @ref LL_FLASH_LATENCY_7 |
| AnnaBridge | 171:3a7713b1edbc | 927 | * @arg @ref LL_FLASH_LATENCY_8 |
| AnnaBridge | 171:3a7713b1edbc | 928 | * @arg @ref LL_FLASH_LATENCY_9 |
| AnnaBridge | 171:3a7713b1edbc | 929 | * @arg @ref LL_FLASH_LATENCY_10 |
| AnnaBridge | 171:3a7713b1edbc | 930 | * @arg @ref LL_FLASH_LATENCY_11 |
| AnnaBridge | 171:3a7713b1edbc | 931 | * @arg @ref LL_FLASH_LATENCY_12 |
| AnnaBridge | 171:3a7713b1edbc | 932 | * @arg @ref LL_FLASH_LATENCY_13 |
| AnnaBridge | 171:3a7713b1edbc | 933 | * @arg @ref LL_FLASH_LATENCY_14 |
| AnnaBridge | 171:3a7713b1edbc | 934 | * @arg @ref LL_FLASH_LATENCY_15 |
| AnnaBridge | 171:3a7713b1edbc | 935 | */ |
| AnnaBridge | 171:3a7713b1edbc | 936 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
| AnnaBridge | 171:3a7713b1edbc | 937 | { |
| AnnaBridge | 171:3a7713b1edbc | 938 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
| AnnaBridge | 171:3a7713b1edbc | 939 | } |
| AnnaBridge | 171:3a7713b1edbc | 940 | |
| AnnaBridge | 171:3a7713b1edbc | 941 | /** |
| AnnaBridge | 171:3a7713b1edbc | 942 | * @brief Enable Prefetch |
| AnnaBridge | 171:3a7713b1edbc | 943 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch |
| AnnaBridge | 171:3a7713b1edbc | 944 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 945 | */ |
| AnnaBridge | 171:3a7713b1edbc | 946 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
| AnnaBridge | 171:3a7713b1edbc | 947 | { |
| AnnaBridge | 171:3a7713b1edbc | 948 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
| AnnaBridge | 171:3a7713b1edbc | 949 | } |
| AnnaBridge | 171:3a7713b1edbc | 950 | |
| AnnaBridge | 171:3a7713b1edbc | 951 | /** |
| AnnaBridge | 171:3a7713b1edbc | 952 | * @brief Disable Prefetch |
| AnnaBridge | 171:3a7713b1edbc | 953 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch |
| AnnaBridge | 171:3a7713b1edbc | 954 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 955 | */ |
| AnnaBridge | 171:3a7713b1edbc | 956 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
| AnnaBridge | 171:3a7713b1edbc | 957 | { |
| AnnaBridge | 171:3a7713b1edbc | 958 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
| AnnaBridge | 171:3a7713b1edbc | 959 | } |
| AnnaBridge | 171:3a7713b1edbc | 960 | |
| AnnaBridge | 171:3a7713b1edbc | 961 | /** |
| AnnaBridge | 171:3a7713b1edbc | 962 | * @brief Check if Prefetch buffer is enabled |
| AnnaBridge | 171:3a7713b1edbc | 963 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled |
| AnnaBridge | 171:3a7713b1edbc | 964 | * @retval State of bit (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 965 | */ |
| AnnaBridge | 171:3a7713b1edbc | 966 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
| AnnaBridge | 171:3a7713b1edbc | 967 | { |
| AnnaBridge | 171:3a7713b1edbc | 968 | return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); |
| AnnaBridge | 171:3a7713b1edbc | 969 | } |
| AnnaBridge | 171:3a7713b1edbc | 970 | |
| AnnaBridge | 171:3a7713b1edbc | 971 | |
| AnnaBridge | 171:3a7713b1edbc | 972 | |
| AnnaBridge | 171:3a7713b1edbc | 973 | /** |
| AnnaBridge | 171:3a7713b1edbc | 974 | * @brief Enable ART Accelerator |
| AnnaBridge | 171:3a7713b1edbc | 975 | * @rmtoll FLASH_ACR ARTEN LL_FLASH_EnableART |
| AnnaBridge | 171:3a7713b1edbc | 976 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 977 | */ |
| AnnaBridge | 171:3a7713b1edbc | 978 | __STATIC_INLINE void LL_FLASH_EnableART(void) |
| AnnaBridge | 171:3a7713b1edbc | 979 | { |
| AnnaBridge | 171:3a7713b1edbc | 980 | SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN); |
| AnnaBridge | 171:3a7713b1edbc | 981 | } |
| AnnaBridge | 171:3a7713b1edbc | 982 | |
| AnnaBridge | 171:3a7713b1edbc | 983 | /** |
| AnnaBridge | 171:3a7713b1edbc | 984 | * @brief Disable ART Accelerator |
| AnnaBridge | 171:3a7713b1edbc | 985 | * @rmtoll FLASH_ACR ARTEN LL_FLASH_DisableART |
| AnnaBridge | 171:3a7713b1edbc | 986 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 987 | */ |
| AnnaBridge | 171:3a7713b1edbc | 988 | __STATIC_INLINE void LL_FLASH_DisableART(void) |
| AnnaBridge | 171:3a7713b1edbc | 989 | { |
| AnnaBridge | 171:3a7713b1edbc | 990 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN); |
| AnnaBridge | 171:3a7713b1edbc | 991 | } |
| AnnaBridge | 171:3a7713b1edbc | 992 | |
| AnnaBridge | 171:3a7713b1edbc | 993 | /** |
| AnnaBridge | 171:3a7713b1edbc | 994 | * @brief Enable ART Reset |
| AnnaBridge | 171:3a7713b1edbc | 995 | * @rmtoll FLASH_ACR ARTRST LL_FLASH_EnableARTReset |
| AnnaBridge | 171:3a7713b1edbc | 996 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 997 | */ |
| AnnaBridge | 171:3a7713b1edbc | 998 | __STATIC_INLINE void LL_FLASH_EnableARTReset(void) |
| AnnaBridge | 171:3a7713b1edbc | 999 | { |
| AnnaBridge | 171:3a7713b1edbc | 1000 | SET_BIT(FLASH->ACR, FLASH_ACR_ARTRST); |
| AnnaBridge | 171:3a7713b1edbc | 1001 | } |
| AnnaBridge | 171:3a7713b1edbc | 1002 | |
| AnnaBridge | 171:3a7713b1edbc | 1003 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1004 | * @brief Disable ART Reset |
| AnnaBridge | 171:3a7713b1edbc | 1005 | * @rmtoll FLASH_ACR ARTRST LL_FLASH_DisableARTReset |
| AnnaBridge | 171:3a7713b1edbc | 1006 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1007 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1008 | __STATIC_INLINE void LL_FLASH_DisableARTReset(void) |
| AnnaBridge | 171:3a7713b1edbc | 1009 | { |
| AnnaBridge | 171:3a7713b1edbc | 1010 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTRST); |
| AnnaBridge | 171:3a7713b1edbc | 1011 | } |
| AnnaBridge | 171:3a7713b1edbc | 1012 | |
| AnnaBridge | 171:3a7713b1edbc | 1013 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1014 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1015 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1016 | |
| AnnaBridge | 171:3a7713b1edbc | 1017 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1018 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1019 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1020 | |
| AnnaBridge | 171:3a7713b1edbc | 1021 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1022 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1023 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1024 | |
| AnnaBridge | 171:3a7713b1edbc | 1025 | #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ |
| AnnaBridge | 171:3a7713b1edbc | 1026 | |
| AnnaBridge | 171:3a7713b1edbc | 1027 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1028 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1029 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1030 | |
| AnnaBridge | 171:3a7713b1edbc | 1031 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 1032 | } |
| AnnaBridge | 171:3a7713b1edbc | 1033 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 1034 | |
| AnnaBridge | 171:3a7713b1edbc | 1035 | #endif /* __STM32F7xx_LL_SYSTEM_H */ |
| AnnaBridge | 171:3a7713b1edbc | 1036 | |
| AnnaBridge | 171:3a7713b1edbc | 1037 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
