mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f7xx_ll_sdmmc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f7xx_ll_sdmmc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of SDMMC HAL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F7xx_LL_SDMMC_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F7xx_LL_SDMMC_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f7xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F7xx_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/** @addtogroup SDMMC_LL
AnnaBridge	171:3a7713b1edbc	52	* @{
AnnaBridge	171:3a7713b1edbc	53	*/
AnnaBridge	171:3a7713b1edbc	54
AnnaBridge	171:3a7713b1edbc	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	56	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
AnnaBridge	171:3a7713b1edbc	57	* @{
AnnaBridge	171:3a7713b1edbc	58	*/
AnnaBridge	171:3a7713b1edbc	59
AnnaBridge	171:3a7713b1edbc	60	/**
AnnaBridge	171:3a7713b1edbc	61	* @brief SDMMC Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	62	*/
AnnaBridge	171:3a7713b1edbc	63	typedef struct
AnnaBridge	171:3a7713b1edbc	64	{
AnnaBridge	171:3a7713b1edbc	65	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge	171:3a7713b1edbc	66	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
AnnaBridge	171:3a7713b1edbc	67
AnnaBridge	171:3a7713b1edbc	68	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
AnnaBridge	171:3a7713b1edbc	69	enabled or disabled.
AnnaBridge	171:3a7713b1edbc	70	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
AnnaBridge	171:3a7713b1edbc	71
AnnaBridge	171:3a7713b1edbc	72	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
AnnaBridge	171:3a7713b1edbc	73	disabled when the bus is idle.
AnnaBridge	171:3a7713b1edbc	74	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
AnnaBridge	171:3a7713b1edbc	75
AnnaBridge	171:3a7713b1edbc	76	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
AnnaBridge	171:3a7713b1edbc	77	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
AnnaBridge	171:3a7713b1edbc	78
AnnaBridge	171:3a7713b1edbc	79	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	80	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
AnnaBridge	171:3a7713b1edbc	81
AnnaBridge	171:3a7713b1edbc	82	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
AnnaBridge	171:3a7713b1edbc	83	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	84
AnnaBridge	171:3a7713b1edbc	85	}SDMMC_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	86
AnnaBridge	171:3a7713b1edbc	87
AnnaBridge	171:3a7713b1edbc	88	/**
AnnaBridge	171:3a7713b1edbc	89	* @brief SDMMC Command Control structure
AnnaBridge	171:3a7713b1edbc	90	*/
AnnaBridge	171:3a7713b1edbc	91	typedef struct
AnnaBridge	171:3a7713b1edbc	92	{
AnnaBridge	171:3a7713b1edbc	93	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
AnnaBridge	171:3a7713b1edbc	94	to a card as part of a command message. If a command
AnnaBridge	171:3a7713b1edbc	95	contains an argument, it must be loaded into this register
AnnaBridge	171:3a7713b1edbc	96	before writing the command to the command register. */
AnnaBridge	171:3a7713b1edbc	97
AnnaBridge	171:3a7713b1edbc	98	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
AnnaBridge	171:3a7713b1edbc	99	Max_Data = 64 */
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	uint32_t Response; /*!< Specifies the SDMMC response type.
AnnaBridge	171:3a7713b1edbc	102	This parameter can be a value of @ref SDMMC_LL_Response_Type */
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
AnnaBridge	171:3a7713b1edbc	105	enabled or disabled.
AnnaBridge	171:3a7713b1edbc	106	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
AnnaBridge	171:3a7713b1edbc	107
AnnaBridge	171:3a7713b1edbc	108	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
AnnaBridge	171:3a7713b1edbc	109	is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	110	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
AnnaBridge	171:3a7713b1edbc	111	}SDMMC_CmdInitTypeDef;
AnnaBridge	171:3a7713b1edbc	112
AnnaBridge	171:3a7713b1edbc	113
AnnaBridge	171:3a7713b1edbc	114	/**
AnnaBridge	171:3a7713b1edbc	115	* @brief SDMMC Data Control structure
AnnaBridge	171:3a7713b1edbc	116	*/
AnnaBridge	171:3a7713b1edbc	117	typedef struct
AnnaBridge	171:3a7713b1edbc	118	{
AnnaBridge	171:3a7713b1edbc	119	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
AnnaBridge	171:3a7713b1edbc	120
AnnaBridge	171:3a7713b1edbc	121	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
AnnaBridge	171:3a7713b1edbc	122
AnnaBridge	171:3a7713b1edbc	123	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
AnnaBridge	171:3a7713b1edbc	124	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
AnnaBridge	171:3a7713b1edbc	125
AnnaBridge	171:3a7713b1edbc	126	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
AnnaBridge	171:3a7713b1edbc	127	is a read or write.
AnnaBridge	171:3a7713b1edbc	128	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
AnnaBridge	171:3a7713b1edbc	129
AnnaBridge	171:3a7713b1edbc	130	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
AnnaBridge	171:3a7713b1edbc	131	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
AnnaBridge	171:3a7713b1edbc	132
AnnaBridge	171:3a7713b1edbc	133	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
AnnaBridge	171:3a7713b1edbc	134	is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	135	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
AnnaBridge	171:3a7713b1edbc	136	}SDMMC_DataInitTypeDef;
AnnaBridge	171:3a7713b1edbc	137
AnnaBridge	171:3a7713b1edbc	138	/**
AnnaBridge	171:3a7713b1edbc	139	* @}
AnnaBridge	171:3a7713b1edbc	140	*/
AnnaBridge	171:3a7713b1edbc	141
AnnaBridge	171:3a7713b1edbc	142	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	143	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
AnnaBridge	171:3a7713b1edbc	144	* @{
AnnaBridge	171:3a7713b1edbc	145	*/
AnnaBridge	171:3a7713b1edbc	146	#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
AnnaBridge	171:3a7713b1edbc	147	#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /!< Command response received (but CRC check failed) /
AnnaBridge	171:3a7713b1edbc	148	#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /!< Data block sent/received (CRC check failed) /
AnnaBridge	171:3a7713b1edbc	149	#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /!< Command response timeout /
AnnaBridge	171:3a7713b1edbc	150	#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /!< Data timeout /
AnnaBridge	171:3a7713b1edbc	151	#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /!< Transmit FIFO underrun /
AnnaBridge	171:3a7713b1edbc	152	#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /!< Receive FIFO overrun /
AnnaBridge	171:3a7713b1edbc	153	#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /!< Misaligned address /
AnnaBridge	171:3a7713b1edbc	154	#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
AnnaBridge	171:3a7713b1edbc	155	number of transferred bytes does not match the block length */
AnnaBridge	171:3a7713b1edbc	156	#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /!< An error in the sequence of erase command occurs /
AnnaBridge	171:3a7713b1edbc	157	#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /!< An invalid selection for erase groups /
AnnaBridge	171:3a7713b1edbc	158	#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /!< Attempt to program a write protect block /
AnnaBridge	171:3a7713b1edbc	159	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
AnnaBridge	171:3a7713b1edbc	160	command or if there was an attempt to access a locked card */
AnnaBridge	171:3a7713b1edbc	161	#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /!< CRC check of the previous command failed /
AnnaBridge	171:3a7713b1edbc	162	#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /!< Command is not legal for the card state /
AnnaBridge	171:3a7713b1edbc	163	#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /!< Card internal ECC was applied but failed to correct the data /
AnnaBridge	171:3a7713b1edbc	164	#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /!< Internal card controller error /
AnnaBridge	171:3a7713b1edbc	165	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /!< General or unknown error /
AnnaBridge	171:3a7713b1edbc	166	#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /!< The card could not sustain data reading in stream rmode /
AnnaBridge	171:3a7713b1edbc	167	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /!< The card could not sustain data programming in stream mode /
AnnaBridge	171:3a7713b1edbc	168	#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /!< CID/CSD overwrite error /
AnnaBridge	171:3a7713b1edbc	169	#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /!< Only partial address space was erased /
AnnaBridge	171:3a7713b1edbc	170	#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /!< Command has been executed without using internal ECC /
AnnaBridge	171:3a7713b1edbc	171	#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
AnnaBridge	171:3a7713b1edbc	172	of erase sequence command was received */
AnnaBridge	171:3a7713b1edbc	173	#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /!< Error in sequence of authentication /
AnnaBridge	171:3a7713b1edbc	174	#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /!< Error in case of invalid voltage range /
AnnaBridge	171:3a7713b1edbc	175	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /!< Error when addressed block is out of range /
AnnaBridge	171:3a7713b1edbc	176	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /!< Error when command request is not applicable /
AnnaBridge	171:3a7713b1edbc	177	#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /!< the used parameter is not valid /
AnnaBridge	171:3a7713b1edbc	178	#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /!< Error when feature is not insupported /
AnnaBridge	171:3a7713b1edbc	179	#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /!< Error when transfer process is busy /
AnnaBridge	171:3a7713b1edbc	180	#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /!< Error while DMA transfer /
AnnaBridge	171:3a7713b1edbc	181	#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /!< Timeout error /
AnnaBridge	171:3a7713b1edbc	182
AnnaBridge	171:3a7713b1edbc	183	/**
AnnaBridge	171:3a7713b1edbc	184	* @brief SDMMC Commands Index
AnnaBridge	171:3a7713b1edbc	185	*/
AnnaBridge	171:3a7713b1edbc	186	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /!< Resets the SD memory card. /
AnnaBridge	171:3a7713b1edbc	187	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /!< Sends host capacity support information and activates the card's initialization process. /
AnnaBridge	171:3a7713b1edbc	188	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
AnnaBridge	171:3a7713b1edbc	189	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /!< Asks the card to publish a new relative address (RCA). /
AnnaBridge	171:3a7713b1edbc	190	#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /!< Programs the DSR of all cards. /
AnnaBridge	171:3a7713b1edbc	191	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge	171:3a7713b1edbc	192	operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	171:3a7713b1edbc	193	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
AnnaBridge	171:3a7713b1edbc	194	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /!< Selects the card by its own relative address and gets deselected by any other address /
AnnaBridge	171:3a7713b1edbc	195	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge	171:3a7713b1edbc	196	and asks the card whether card supports voltage. */
AnnaBridge	171:3a7713b1edbc	197	#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
AnnaBridge	171:3a7713b1edbc	198	#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /!< Addressed card sends its card identification (CID) on the CMD line. /
AnnaBridge	171:3a7713b1edbc	199	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /!< SD card doesn't support it. /
AnnaBridge	171:3a7713b1edbc	200	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /!< Forces the card to stop transmission. /
AnnaBridge	171:3a7713b1edbc	201	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /!< Addressed card sends its status register. /
AnnaBridge	171:3a7713b1edbc	202	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /!< Reserved /
AnnaBridge	171:3a7713b1edbc	203	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /!< Sends an addressed card into the inactive state. /
AnnaBridge	171:3a7713b1edbc	204	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge	171:3a7713b1edbc	205	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge	171:3a7713b1edbc	206	for SDHS and SDXC. */
AnnaBridge	171:3a7713b1edbc	207	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	171:3a7713b1edbc	208	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	171:3a7713b1edbc	209	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge	171:3a7713b1edbc	210	STOP_TRANSMISSION command. */
AnnaBridge	171:3a7713b1edbc	211	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
AnnaBridge	171:3a7713b1edbc	212	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /!< Speed class control command. /
AnnaBridge	171:3a7713b1edbc	213	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /!< Specify block count for CMD18 and CMD25. /
AnnaBridge	171:3a7713b1edbc	214	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	171:3a7713b1edbc	215	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	171:3a7713b1edbc	216	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
AnnaBridge	171:3a7713b1edbc	217	#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /!< Reserved for manufacturers. /
AnnaBridge	171:3a7713b1edbc	218	#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /!< Programming of the programmable bits of the CSD. /
AnnaBridge	171:3a7713b1edbc	219	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /!< Sets the write protection bit of the addressed group. /
AnnaBridge	171:3a7713b1edbc	220	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /!< Clears the write protection bit of the addressed group. /
AnnaBridge	171:3a7713b1edbc	221	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /!< Asks the card to send the status of the write protection bits. /
AnnaBridge	171:3a7713b1edbc	222	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /!< Sets the address of the first write block to be erased. (For SD card only). /
AnnaBridge	171:3a7713b1edbc	223	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /!< Sets the address of the last write block of the continuous range to be erased. /
AnnaBridge	171:3a7713b1edbc	224	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge	171:3a7713b1edbc	225	system set by switch function command (CMD6). */
AnnaBridge	171:3a7713b1edbc	226	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge	171:3a7713b1edbc	227	Reserved for each command system set by switch function command (CMD6). */
AnnaBridge	171:3a7713b1edbc	228	#define SDMMC_CMD_ERASE ((uint8_t)38U) /!< Reserved for SD security applications. /
AnnaBridge	171:3a7713b1edbc	229	#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	171:3a7713b1edbc	230	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	171:3a7713b1edbc	231	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge	171:3a7713b1edbc	232	the SET_BLOCK_LEN command. */
AnnaBridge	171:3a7713b1edbc	233	#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge	171:3a7713b1edbc	234	than a standard command. */
AnnaBridge	171:3a7713b1edbc	235	#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge	171:3a7713b1edbc	236	for general purpose/application specific commands. */
AnnaBridge	171:3a7713b1edbc	237	#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /!< No command /
AnnaBridge	171:3a7713b1edbc	238
AnnaBridge	171:3a7713b1edbc	239	/**
AnnaBridge	171:3a7713b1edbc	240	* @brief Following commands are SD Card Specific commands.
AnnaBridge	171:3a7713b1edbc	241	* SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge	171:3a7713b1edbc	242	*/
AnnaBridge	171:3a7713b1edbc	243	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge	171:3a7713b1edbc	244	widths are given in SCR register. */
AnnaBridge	171:3a7713b1edbc	245	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /!< (ACMD13) Sends the SD status. /
AnnaBridge	171:3a7713b1edbc	246	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge	171:3a7713b1edbc	247	32bit+CRC data block. */
AnnaBridge	171:3a7713b1edbc	248	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge	171:3a7713b1edbc	249	send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	171:3a7713b1edbc	250	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
AnnaBridge	171:3a7713b1edbc	251	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /!< Reads the SD Configuration Register (SCR). /
AnnaBridge	171:3a7713b1edbc	252	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	171:3a7713b1edbc	253	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	171:3a7713b1edbc	254
AnnaBridge	171:3a7713b1edbc	255	/**
AnnaBridge	171:3a7713b1edbc	256	* @brief Following commands are SD Card Specific security commands.
AnnaBridge	171:3a7713b1edbc	257	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge	171:3a7713b1edbc	258	*/
AnnaBridge	171:3a7713b1edbc	259	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
AnnaBridge	171:3a7713b1edbc	260	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
AnnaBridge	171:3a7713b1edbc	261	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
AnnaBridge	171:3a7713b1edbc	262	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
AnnaBridge	171:3a7713b1edbc	263	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
AnnaBridge	171:3a7713b1edbc	264	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
AnnaBridge	171:3a7713b1edbc	265	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
AnnaBridge	171:3a7713b1edbc	266	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
AnnaBridge	171:3a7713b1edbc	267	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
AnnaBridge	171:3a7713b1edbc	268	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
AnnaBridge	171:3a7713b1edbc	269	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
AnnaBridge	171:3a7713b1edbc	270
AnnaBridge	171:3a7713b1edbc	271	/**
AnnaBridge	171:3a7713b1edbc	272	* @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge	171:3a7713b1edbc	273	*/
AnnaBridge	171:3a7713b1edbc	274	#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
AnnaBridge	171:3a7713b1edbc	275	#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
AnnaBridge	171:3a7713b1edbc	276	#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
AnnaBridge	171:3a7713b1edbc	277	#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
AnnaBridge	171:3a7713b1edbc	278	#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
AnnaBridge	171:3a7713b1edbc	279	#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
AnnaBridge	171:3a7713b1edbc	280	#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
AnnaBridge	171:3a7713b1edbc	281	#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
AnnaBridge	171:3a7713b1edbc	282	#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
AnnaBridge	171:3a7713b1edbc	283	#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
AnnaBridge	171:3a7713b1edbc	284	#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
AnnaBridge	171:3a7713b1edbc	285	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
AnnaBridge	171:3a7713b1edbc	286	#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
AnnaBridge	171:3a7713b1edbc	287	#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
AnnaBridge	171:3a7713b1edbc	288	#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
AnnaBridge	171:3a7713b1edbc	289	#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
AnnaBridge	171:3a7713b1edbc	290	#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
AnnaBridge	171:3a7713b1edbc	291	#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
AnnaBridge	171:3a7713b1edbc	292	#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
AnnaBridge	171:3a7713b1edbc	293	#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
AnnaBridge	171:3a7713b1edbc	294
AnnaBridge	171:3a7713b1edbc	295	/**
AnnaBridge	171:3a7713b1edbc	296	* @brief Masks for R6 Response
AnnaBridge	171:3a7713b1edbc	297	*/
AnnaBridge	171:3a7713b1edbc	298	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
AnnaBridge	171:3a7713b1edbc	299	#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
AnnaBridge	171:3a7713b1edbc	300	#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
AnnaBridge	171:3a7713b1edbc	301
AnnaBridge	171:3a7713b1edbc	302	#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
AnnaBridge	171:3a7713b1edbc	303	#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
AnnaBridge	171:3a7713b1edbc	304	#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	305	#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
AnnaBridge	171:3a7713b1edbc	306
AnnaBridge	171:3a7713b1edbc	307	#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309	#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	171:3a7713b1edbc	310
AnnaBridge	171:3a7713b1edbc	311	#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	312
AnnaBridge	171:3a7713b1edbc	313	#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
AnnaBridge	171:3a7713b1edbc	314	#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
AnnaBridge	171:3a7713b1edbc	315	#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
AnnaBridge	171:3a7713b1edbc	316
AnnaBridge	171:3a7713b1edbc	317	#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
AnnaBridge	171:3a7713b1edbc	320	#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
AnnaBridge	171:3a7713b1edbc	321	#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
AnnaBridge	171:3a7713b1edbc	322	#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
AnnaBridge	171:3a7713b1edbc	323	#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
AnnaBridge	171:3a7713b1edbc	324
AnnaBridge	171:3a7713b1edbc	325	#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
AnnaBridge	171:3a7713b1edbc	326	#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	/**
AnnaBridge	171:3a7713b1edbc	329	* @brief Command Class supported
AnnaBridge	171:3a7713b1edbc	330	*/
AnnaBridge	171:3a7713b1edbc	331	#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333	#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
AnnaBridge	171:3a7713b1edbc	334	#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
AnnaBridge	171:3a7713b1edbc	335
AnnaBridge	171:3a7713b1edbc	336
AnnaBridge	171:3a7713b1edbc	337	/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
AnnaBridge	171:3a7713b1edbc	338	* @{
AnnaBridge	171:3a7713b1edbc	339	*/
AnnaBridge	171:3a7713b1edbc	340	#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	341	#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
AnnaBridge	171:3a7713b1edbc	342
AnnaBridge	171:3a7713b1edbc	343	#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) \|\| \
AnnaBridge	171:3a7713b1edbc	344	((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
AnnaBridge	171:3a7713b1edbc	345	/**
AnnaBridge	171:3a7713b1edbc	346	* @}
AnnaBridge	171:3a7713b1edbc	347	*/
AnnaBridge	171:3a7713b1edbc	348
AnnaBridge	171:3a7713b1edbc	349	/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
AnnaBridge	171:3a7713b1edbc	350	* @{
AnnaBridge	171:3a7713b1edbc	351	*/
AnnaBridge	171:3a7713b1edbc	352	#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	353	#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	356	((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
AnnaBridge	171:3a7713b1edbc	357	/**
AnnaBridge	171:3a7713b1edbc	358	* @}
AnnaBridge	171:3a7713b1edbc	359	*/
AnnaBridge	171:3a7713b1edbc	360
AnnaBridge	171:3a7713b1edbc	361	/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
AnnaBridge	171:3a7713b1edbc	362	* @{
AnnaBridge	171:3a7713b1edbc	363	*/
AnnaBridge	171:3a7713b1edbc	364	#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	365	#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
AnnaBridge	171:3a7713b1edbc	366
AnnaBridge	171:3a7713b1edbc	367	#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	368	((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
AnnaBridge	171:3a7713b1edbc	369	/**
AnnaBridge	171:3a7713b1edbc	370	* @}
AnnaBridge	171:3a7713b1edbc	371	*/
AnnaBridge	171:3a7713b1edbc	372
AnnaBridge	171:3a7713b1edbc	373	/** @defgroup SDMMC_LL_Bus_Wide Bus Width
AnnaBridge	171:3a7713b1edbc	374	* @{
AnnaBridge	171:3a7713b1edbc	375	*/
AnnaBridge	171:3a7713b1edbc	376	#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	377	#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
AnnaBridge	171:3a7713b1edbc	378	#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
AnnaBridge	171:3a7713b1edbc	379
AnnaBridge	171:3a7713b1edbc	380	#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) \|\| \
AnnaBridge	171:3a7713b1edbc	381	((WIDE) == SDMMC_BUS_WIDE_4B) \|\| \
AnnaBridge	171:3a7713b1edbc	382	((WIDE) == SDMMC_BUS_WIDE_8B))
AnnaBridge	171:3a7713b1edbc	383	/**
AnnaBridge	171:3a7713b1edbc	384	* @}
AnnaBridge	171:3a7713b1edbc	385	*/
AnnaBridge	171:3a7713b1edbc	386
AnnaBridge	171:3a7713b1edbc	387	/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
AnnaBridge	171:3a7713b1edbc	388	* @{
AnnaBridge	171:3a7713b1edbc	389	*/
AnnaBridge	171:3a7713b1edbc	390	#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	391	#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
AnnaBridge	171:3a7713b1edbc	392
AnnaBridge	171:3a7713b1edbc	393	#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	394	((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
AnnaBridge	171:3a7713b1edbc	395	/**
AnnaBridge	171:3a7713b1edbc	396	* @}
AnnaBridge	171:3a7713b1edbc	397	*/
AnnaBridge	171:3a7713b1edbc	398
AnnaBridge	171:3a7713b1edbc	399	/** @defgroup SDMMC_LL_Clock_Division Clock Division
AnnaBridge	171:3a7713b1edbc	400	* @{
AnnaBridge	171:3a7713b1edbc	401	*/
AnnaBridge	171:3a7713b1edbc	402	#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
AnnaBridge	171:3a7713b1edbc	403	/**
AnnaBridge	171:3a7713b1edbc	404	* @}
AnnaBridge	171:3a7713b1edbc	405	*/
AnnaBridge	171:3a7713b1edbc	406
AnnaBridge	171:3a7713b1edbc	407	/** @defgroup SDMMC_LL_Command_Index Command Index
AnnaBridge	171:3a7713b1edbc	408	* @{
AnnaBridge	171:3a7713b1edbc	409	*/
AnnaBridge	171:3a7713b1edbc	410	#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
AnnaBridge	171:3a7713b1edbc	411	/**
AnnaBridge	171:3a7713b1edbc	412	* @}
AnnaBridge	171:3a7713b1edbc	413	*/
AnnaBridge	171:3a7713b1edbc	414
AnnaBridge	171:3a7713b1edbc	415	/** @defgroup SDMMC_LL_Response_Type Response Type
AnnaBridge	171:3a7713b1edbc	416	* @{
AnnaBridge	171:3a7713b1edbc	417	*/
AnnaBridge	171:3a7713b1edbc	418	#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	419	#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
AnnaBridge	171:3a7713b1edbc	420	#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
AnnaBridge	171:3a7713b1edbc	421
AnnaBridge	171:3a7713b1edbc	422	#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) \|\| \
AnnaBridge	171:3a7713b1edbc	423	((RESPONSE) == SDMMC_RESPONSE_SHORT) \|\| \
AnnaBridge	171:3a7713b1edbc	424	((RESPONSE) == SDMMC_RESPONSE_LONG))
AnnaBridge	171:3a7713b1edbc	425	/**
AnnaBridge	171:3a7713b1edbc	426	* @}
AnnaBridge	171:3a7713b1edbc	427	*/
AnnaBridge	171:3a7713b1edbc	428
AnnaBridge	171:3a7713b1edbc	429	/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
AnnaBridge	171:3a7713b1edbc	430	* @{
AnnaBridge	171:3a7713b1edbc	431	*/
AnnaBridge	171:3a7713b1edbc	432	#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	433	#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
AnnaBridge	171:3a7713b1edbc	434	#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
AnnaBridge	171:3a7713b1edbc	435
AnnaBridge	171:3a7713b1edbc	436	#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) \|\| \
AnnaBridge	171:3a7713b1edbc	437	((WAIT) == SDMMC_WAIT_IT) \|\| \
AnnaBridge	171:3a7713b1edbc	438	((WAIT) == SDMMC_WAIT_PEND))
AnnaBridge	171:3a7713b1edbc	439	/**
AnnaBridge	171:3a7713b1edbc	440	* @}
AnnaBridge	171:3a7713b1edbc	441	*/
AnnaBridge	171:3a7713b1edbc	442
AnnaBridge	171:3a7713b1edbc	443	/** @defgroup SDMMC_LL_CPSM_State CPSM State
AnnaBridge	171:3a7713b1edbc	444	* @{
AnnaBridge	171:3a7713b1edbc	445	*/
AnnaBridge	171:3a7713b1edbc	446	#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	447	#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
AnnaBridge	171:3a7713b1edbc	448
AnnaBridge	171:3a7713b1edbc	449	#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	450	((CPSM) == SDMMC_CPSM_ENABLE))
AnnaBridge	171:3a7713b1edbc	451	/**
AnnaBridge	171:3a7713b1edbc	452	* @}
AnnaBridge	171:3a7713b1edbc	453	*/
AnnaBridge	171:3a7713b1edbc	454
AnnaBridge	171:3a7713b1edbc	455	/** @defgroup SDMMC_LL_Response_Registers Response Register
AnnaBridge	171:3a7713b1edbc	456	* @{
AnnaBridge	171:3a7713b1edbc	457	*/
AnnaBridge	171:3a7713b1edbc	458	#define SDMMC_RESP1 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	459	#define SDMMC_RESP2 ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	460	#define SDMMC_RESP3 ((uint32_t)0x00000008U)
AnnaBridge	171:3a7713b1edbc	461	#define SDMMC_RESP4 ((uint32_t)0x0000000C)
AnnaBridge	171:3a7713b1edbc	462
AnnaBridge	171:3a7713b1edbc	463	#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) \|\| \
AnnaBridge	171:3a7713b1edbc	464	((RESP) == SDMMC_RESP2) \|\| \
AnnaBridge	171:3a7713b1edbc	465	((RESP) == SDMMC_RESP3) \|\| \
AnnaBridge	171:3a7713b1edbc	466	((RESP) == SDMMC_RESP4))
AnnaBridge	171:3a7713b1edbc	467	/**
AnnaBridge	171:3a7713b1edbc	468	* @}
AnnaBridge	171:3a7713b1edbc	469	*/
AnnaBridge	171:3a7713b1edbc	470
AnnaBridge	171:3a7713b1edbc	471	/** @defgroup SDMMC_LL_Data_Length Data Lenght
AnnaBridge	171:3a7713b1edbc	472	* @{
AnnaBridge	171:3a7713b1edbc	473	*/
AnnaBridge	171:3a7713b1edbc	474	#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
AnnaBridge	171:3a7713b1edbc	475	/**
AnnaBridge	171:3a7713b1edbc	476	* @}
AnnaBridge	171:3a7713b1edbc	477	*/
AnnaBridge	171:3a7713b1edbc	478
AnnaBridge	171:3a7713b1edbc	479	/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
AnnaBridge	171:3a7713b1edbc	480	* @{
AnnaBridge	171:3a7713b1edbc	481	*/
AnnaBridge	171:3a7713b1edbc	482	#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	483	#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
AnnaBridge	171:3a7713b1edbc	484	#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
AnnaBridge	171:3a7713b1edbc	485	#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1)
AnnaBridge	171:3a7713b1edbc	486	#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
AnnaBridge	171:3a7713b1edbc	487	#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	171:3a7713b1edbc	488	#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	171:3a7713b1edbc	489	#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	171:3a7713b1edbc	490	#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
AnnaBridge	171:3a7713b1edbc	491	#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	492	#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	493	#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	494	#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	495	#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	496	#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	497
AnnaBridge	171:3a7713b1edbc	498	#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) \|\| \
AnnaBridge	171:3a7713b1edbc	499	((SIZE) == SDMMC_DATABLOCK_SIZE_2B) \|\| \
AnnaBridge	171:3a7713b1edbc	500	((SIZE) == SDMMC_DATABLOCK_SIZE_4B) \|\| \
AnnaBridge	171:3a7713b1edbc	501	((SIZE) == SDMMC_DATABLOCK_SIZE_8B) \|\| \
AnnaBridge	171:3a7713b1edbc	502	((SIZE) == SDMMC_DATABLOCK_SIZE_16B) \|\| \
AnnaBridge	171:3a7713b1edbc	503	((SIZE) == SDMMC_DATABLOCK_SIZE_32B) \|\| \
AnnaBridge	171:3a7713b1edbc	504	((SIZE) == SDMMC_DATABLOCK_SIZE_64B) \|\| \
AnnaBridge	171:3a7713b1edbc	505	((SIZE) == SDMMC_DATABLOCK_SIZE_128B) \|\| \
AnnaBridge	171:3a7713b1edbc	506	((SIZE) == SDMMC_DATABLOCK_SIZE_256B) \|\| \
AnnaBridge	171:3a7713b1edbc	507	((SIZE) == SDMMC_DATABLOCK_SIZE_512B) \|\| \
AnnaBridge	171:3a7713b1edbc	508	((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) \|\| \
AnnaBridge	171:3a7713b1edbc	509	((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) \|\| \
AnnaBridge	171:3a7713b1edbc	510	((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) \|\| \
AnnaBridge	171:3a7713b1edbc	511	((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) \|\| \
AnnaBridge	171:3a7713b1edbc	512	((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
AnnaBridge	171:3a7713b1edbc	513	/**
AnnaBridge	171:3a7713b1edbc	514	* @}
AnnaBridge	171:3a7713b1edbc	515	*/
AnnaBridge	171:3a7713b1edbc	516
AnnaBridge	171:3a7713b1edbc	517	/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
AnnaBridge	171:3a7713b1edbc	518	* @{
AnnaBridge	171:3a7713b1edbc	519	*/
AnnaBridge	171:3a7713b1edbc	520	#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	521	#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
AnnaBridge	171:3a7713b1edbc	522
AnnaBridge	171:3a7713b1edbc	523	#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) \|\| \
AnnaBridge	171:3a7713b1edbc	524	((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
AnnaBridge	171:3a7713b1edbc	525	/**
AnnaBridge	171:3a7713b1edbc	526	* @}
AnnaBridge	171:3a7713b1edbc	527	*/
AnnaBridge	171:3a7713b1edbc	528
AnnaBridge	171:3a7713b1edbc	529	/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
AnnaBridge	171:3a7713b1edbc	530	* @{
AnnaBridge	171:3a7713b1edbc	531	*/
AnnaBridge	171:3a7713b1edbc	532	#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	533	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
AnnaBridge	171:3a7713b1edbc	534
AnnaBridge	171:3a7713b1edbc	535	#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) \|\| \
AnnaBridge	171:3a7713b1edbc	536	((MODE) == SDMMC_TRANSFER_MODE_STREAM))
AnnaBridge	171:3a7713b1edbc	537	/**
AnnaBridge	171:3a7713b1edbc	538	* @}
AnnaBridge	171:3a7713b1edbc	539	*/
AnnaBridge	171:3a7713b1edbc	540
AnnaBridge	171:3a7713b1edbc	541	/** @defgroup SDMMC_LL_DPSM_State DPSM State
AnnaBridge	171:3a7713b1edbc	542	* @{
AnnaBridge	171:3a7713b1edbc	543	*/
AnnaBridge	171:3a7713b1edbc	544	#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	545	#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
AnnaBridge	171:3a7713b1edbc	546
AnnaBridge	171:3a7713b1edbc	547	#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) \|\|\
AnnaBridge	171:3a7713b1edbc	548	((DPSM) == SDMMC_DPSM_ENABLE))
AnnaBridge	171:3a7713b1edbc	549	/**
AnnaBridge	171:3a7713b1edbc	550	* @}
AnnaBridge	171:3a7713b1edbc	551	*/
AnnaBridge	171:3a7713b1edbc	552
AnnaBridge	171:3a7713b1edbc	553	/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
AnnaBridge	171:3a7713b1edbc	554	* @{
AnnaBridge	171:3a7713b1edbc	555	*/
AnnaBridge	171:3a7713b1edbc	556	#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	557	#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
AnnaBridge	171:3a7713b1edbc	558
AnnaBridge	171:3a7713b1edbc	559	#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) \|\| \
AnnaBridge	171:3a7713b1edbc	560	((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
AnnaBridge	171:3a7713b1edbc	561	/**
AnnaBridge	171:3a7713b1edbc	562	* @}
AnnaBridge	171:3a7713b1edbc	563	*/
AnnaBridge	171:3a7713b1edbc	564
AnnaBridge	171:3a7713b1edbc	565	/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
AnnaBridge	171:3a7713b1edbc	566	* @{
AnnaBridge	171:3a7713b1edbc	567	*/
AnnaBridge	171:3a7713b1edbc	568	#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
AnnaBridge	171:3a7713b1edbc	569	#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
AnnaBridge	171:3a7713b1edbc	570	#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
AnnaBridge	171:3a7713b1edbc	571	#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
AnnaBridge	171:3a7713b1edbc	572	#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
AnnaBridge	171:3a7713b1edbc	573	#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
AnnaBridge	171:3a7713b1edbc	574	#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
AnnaBridge	171:3a7713b1edbc	575	#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
AnnaBridge	171:3a7713b1edbc	576	#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
AnnaBridge	171:3a7713b1edbc	577	#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
AnnaBridge	171:3a7713b1edbc	578	#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
AnnaBridge	171:3a7713b1edbc	579	#define SDMMC_IT_TXACT SDMMC_STA_TXACT
AnnaBridge	171:3a7713b1edbc	580	#define SDMMC_IT_RXACT SDMMC_STA_RXACT
AnnaBridge	171:3a7713b1edbc	581	#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
AnnaBridge	171:3a7713b1edbc	582	#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
AnnaBridge	171:3a7713b1edbc	583	#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
AnnaBridge	171:3a7713b1edbc	584	#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
AnnaBridge	171:3a7713b1edbc	585	#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
AnnaBridge	171:3a7713b1edbc	586	#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
AnnaBridge	171:3a7713b1edbc	587	#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
AnnaBridge	171:3a7713b1edbc	588	#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
AnnaBridge	171:3a7713b1edbc	589	#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
AnnaBridge	171:3a7713b1edbc	590	/**
AnnaBridge	171:3a7713b1edbc	591	* @}
AnnaBridge	171:3a7713b1edbc	592	*/
AnnaBridge	171:3a7713b1edbc	593
AnnaBridge	171:3a7713b1edbc	594	/** @defgroup SDMMC_LL_Flags Flags
AnnaBridge	171:3a7713b1edbc	595	* @{
AnnaBridge	171:3a7713b1edbc	596	*/
AnnaBridge	171:3a7713b1edbc	597	#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
AnnaBridge	171:3a7713b1edbc	598	#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
AnnaBridge	171:3a7713b1edbc	599	#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
AnnaBridge	171:3a7713b1edbc	600	#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
AnnaBridge	171:3a7713b1edbc	601	#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
AnnaBridge	171:3a7713b1edbc	602	#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
AnnaBridge	171:3a7713b1edbc	603	#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
AnnaBridge	171:3a7713b1edbc	604	#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
AnnaBridge	171:3a7713b1edbc	605	#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
AnnaBridge	171:3a7713b1edbc	606	#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
AnnaBridge	171:3a7713b1edbc	607	#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
AnnaBridge	171:3a7713b1edbc	608	#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
AnnaBridge	171:3a7713b1edbc	609	#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
AnnaBridge	171:3a7713b1edbc	610	#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
AnnaBridge	171:3a7713b1edbc	611	#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
AnnaBridge	171:3a7713b1edbc	612	#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
AnnaBridge	171:3a7713b1edbc	613	#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
AnnaBridge	171:3a7713b1edbc	614	#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
AnnaBridge	171:3a7713b1edbc	615	#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
AnnaBridge	171:3a7713b1edbc	616	#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
AnnaBridge	171:3a7713b1edbc	617	#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
AnnaBridge	171:3a7713b1edbc	618	#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
AnnaBridge	171:3a7713b1edbc	619	#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_CTIMEOUT \|\
AnnaBridge	171:3a7713b1edbc	620	SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \| SDMMC_FLAG_RXOVERR \|\
AnnaBridge	171:3a7713b1edbc	621	SDMMC_FLAG_CMDREND \| SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_DATAEND \|\
AnnaBridge	171:3a7713b1edbc	622	SDMMC_FLAG_DBCKEND))
AnnaBridge	171:3a7713b1edbc	623	/**
AnnaBridge	171:3a7713b1edbc	624	* @}
AnnaBridge	171:3a7713b1edbc	625	*/
AnnaBridge	171:3a7713b1edbc	626
AnnaBridge	171:3a7713b1edbc	627	/**
AnnaBridge	171:3a7713b1edbc	628	* @}
AnnaBridge	171:3a7713b1edbc	629	*/
AnnaBridge	171:3a7713b1edbc	630
AnnaBridge	171:3a7713b1edbc	631	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	632	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
AnnaBridge	171:3a7713b1edbc	633	* @{
AnnaBridge	171:3a7713b1edbc	634	*/
AnnaBridge	171:3a7713b1edbc	635
AnnaBridge	171:3a7713b1edbc	636	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
AnnaBridge	171:3a7713b1edbc	637	* @brief SDMMC_LL registers bit address in the alias region
AnnaBridge	171:3a7713b1edbc	638	* @{
AnnaBridge	171:3a7713b1edbc	639	*/
AnnaBridge	171:3a7713b1edbc	640	/* ---------------------- SDMMC registers bit mask --------------------------- */
AnnaBridge	171:3a7713b1edbc	641	/* --- CLKCR Register ---*/
AnnaBridge	171:3a7713b1edbc	642	/* CLKCR register clear mask */
AnnaBridge	171:3a7713b1edbc	643	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
AnnaBridge	171:3a7713b1edbc	644	SDMMC_CLKCR_BYPASS \| SDMMC_CLKCR_WIDBUS \|\
AnnaBridge	171:3a7713b1edbc	645	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
AnnaBridge	171:3a7713b1edbc	646
AnnaBridge	171:3a7713b1edbc	647	/* --- DCTRL Register ---*/
AnnaBridge	171:3a7713b1edbc	648	/* SDMMC DCTRL Clear Mask */
AnnaBridge	171:3a7713b1edbc	649	#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN \| SDMMC_DCTRL_DTDIR \|\
AnnaBridge	171:3a7713b1edbc	650	SDMMC_DCTRL_DTMODE \| SDMMC_DCTRL_DBLOCKSIZE))
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/* --- CMD Register ---*/
AnnaBridge	171:3a7713b1edbc	653	/* CMD Register clear mask */
AnnaBridge	171:3a7713b1edbc	654	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
AnnaBridge	171:3a7713b1edbc	655	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
AnnaBridge	171:3a7713b1edbc	656	SDMMC_CMD_CPSMEN \| SDMMC_CMD_SDIOSUSPEND))
AnnaBridge	171:3a7713b1edbc	657
AnnaBridge	171:3a7713b1edbc	658	/* SDMMC Initialization Frequency (400KHz max) */
AnnaBridge	171:3a7713b1edbc	659	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
AnnaBridge	171:3a7713b1edbc	660
AnnaBridge	171:3a7713b1edbc	661	/* SDMMC Data Transfer Frequency (25MHz max) */
AnnaBridge	171:3a7713b1edbc	662	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
AnnaBridge	171:3a7713b1edbc	663
AnnaBridge	171:3a7713b1edbc	664	/**
AnnaBridge	171:3a7713b1edbc	665	* @}
AnnaBridge	171:3a7713b1edbc	666	*/
AnnaBridge	171:3a7713b1edbc	667
AnnaBridge	171:3a7713b1edbc	668	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge	171:3a7713b1edbc	669	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	171:3a7713b1edbc	670	* @{
AnnaBridge	171:3a7713b1edbc	671	*/
AnnaBridge	171:3a7713b1edbc	672
AnnaBridge	171:3a7713b1edbc	673	/**
AnnaBridge	171:3a7713b1edbc	674	* @brief Enable the SDMMC device.
AnnaBridge	171:3a7713b1edbc	675	* @param __INSTANCE__ SDMMC Instance
AnnaBridge	171:3a7713b1edbc	676	* @retval None
AnnaBridge	171:3a7713b1edbc	677	*/
AnnaBridge	171:3a7713b1edbc	678	#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN)
AnnaBridge	171:3a7713b1edbc	679
AnnaBridge	171:3a7713b1edbc	680	/**
AnnaBridge	171:3a7713b1edbc	681	* @brief Disable the SDMMC device.
AnnaBridge	171:3a7713b1edbc	682	* @param __INSTANCE__ SDMMC Instance
AnnaBridge	171:3a7713b1edbc	683	* @retval None
AnnaBridge	171:3a7713b1edbc	684	*/
AnnaBridge	171:3a7713b1edbc	685	#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
AnnaBridge	171:3a7713b1edbc	686
AnnaBridge	171:3a7713b1edbc	687	/**
AnnaBridge	171:3a7713b1edbc	688	* @brief Enable the SDMMC DMA transfer.
AnnaBridge	171:3a7713b1edbc	689	* @param __INSTANCE__ SDMMC Instance
AnnaBridge	171:3a7713b1edbc	690	* @retval None
AnnaBridge	171:3a7713b1edbc	691	*/
AnnaBridge	171:3a7713b1edbc	692	#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN)
AnnaBridge	171:3a7713b1edbc	693	/**
AnnaBridge	171:3a7713b1edbc	694	* @brief Disable the SDMMC DMA transfer.
AnnaBridge	171:3a7713b1edbc	695	* @param __INSTANCE__ SDMMC Instance
AnnaBridge	171:3a7713b1edbc	696	* @retval None
AnnaBridge	171:3a7713b1edbc	697	*/
AnnaBridge	171:3a7713b1edbc	698	#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
AnnaBridge	171:3a7713b1edbc	699
AnnaBridge	171:3a7713b1edbc	700	/**
AnnaBridge	171:3a7713b1edbc	701	* @brief Enable the SDMMC device interrupt.
AnnaBridge	171:3a7713b1edbc	702	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	703	* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
AnnaBridge	171:3a7713b1edbc	704	* This parameter can be one or a combination of the following values:
AnnaBridge	171:3a7713b1edbc	705	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	706	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	707	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	171:3a7713b1edbc	708	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	171:3a7713b1edbc	709	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	171:3a7713b1edbc	710	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	171:3a7713b1edbc	711	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	712	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	171:3a7713b1edbc	713	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	171:3a7713b1edbc	714	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	715	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	171:3a7713b1edbc	716	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	171:3a7713b1edbc	717	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	171:3a7713b1edbc	718	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	171:3a7713b1edbc	719	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	171:3a7713b1edbc	720	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	721	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	722	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	723	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	724	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	171:3a7713b1edbc	725	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	171:3a7713b1edbc	726	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	171:3a7713b1edbc	727	* @retval None
AnnaBridge	171:3a7713b1edbc	728	*/
AnnaBridge	171:3a7713b1edbc	729	#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	730
AnnaBridge	171:3a7713b1edbc	731	/**
AnnaBridge	171:3a7713b1edbc	732	* @brief Disable the SDMMC device interrupt.
AnnaBridge	171:3a7713b1edbc	733	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	734	* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
AnnaBridge	171:3a7713b1edbc	735	* This parameter can be one or a combination of the following values:
AnnaBridge	171:3a7713b1edbc	736	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	737	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	738	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	171:3a7713b1edbc	739	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	171:3a7713b1edbc	740	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	171:3a7713b1edbc	741	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	171:3a7713b1edbc	742	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	743	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	171:3a7713b1edbc	744	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	171:3a7713b1edbc	745	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	746	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	171:3a7713b1edbc	747	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	171:3a7713b1edbc	748	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	171:3a7713b1edbc	749	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	171:3a7713b1edbc	750	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	171:3a7713b1edbc	751	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	752	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	753	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	754	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	755	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	171:3a7713b1edbc	756	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	171:3a7713b1edbc	757	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	171:3a7713b1edbc	758	* @retval None
AnnaBridge	171:3a7713b1edbc	759	*/
AnnaBridge	171:3a7713b1edbc	760	#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	761
AnnaBridge	171:3a7713b1edbc	762	/**
AnnaBridge	171:3a7713b1edbc	763	* @brief Checks whether the specified SDMMC flag is set or not.
AnnaBridge	171:3a7713b1edbc	764	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	765	* @param __FLAG__ specifies the flag to check.
AnnaBridge	171:3a7713b1edbc	766	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	767	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	171:3a7713b1edbc	768	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	171:3a7713b1edbc	769	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	171:3a7713b1edbc	770	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge	171:3a7713b1edbc	771	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	171:3a7713b1edbc	772	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	171:3a7713b1edbc	773	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	171:3a7713b1edbc	774	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	171:3a7713b1edbc	775	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	171:3a7713b1edbc	776	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	171:3a7713b1edbc	777	* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
AnnaBridge	171:3a7713b1edbc	778	* @arg SDMMC_FLAG_TXACT: Data transmit in progress
AnnaBridge	171:3a7713b1edbc	779	* @arg SDMMC_FLAG_RXACT: Data receive in progress
AnnaBridge	171:3a7713b1edbc	780	* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
AnnaBridge	171:3a7713b1edbc	781	* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
AnnaBridge	171:3a7713b1edbc	782	* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
AnnaBridge	171:3a7713b1edbc	783	* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
AnnaBridge	171:3a7713b1edbc	784	* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
AnnaBridge	171:3a7713b1edbc	785	* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge	171:3a7713b1edbc	786	* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
AnnaBridge	171:3a7713b1edbc	787	* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
AnnaBridge	171:3a7713b1edbc	788	* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
AnnaBridge	171:3a7713b1edbc	789	* @retval The new state of SDMMC_FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	790	*/
AnnaBridge	171:3a7713b1edbc	791	#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
AnnaBridge	171:3a7713b1edbc	792
AnnaBridge	171:3a7713b1edbc	793
AnnaBridge	171:3a7713b1edbc	794	/**
AnnaBridge	171:3a7713b1edbc	795	* @brief Clears the SDMMC pending flags.
AnnaBridge	171:3a7713b1edbc	796	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	797	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	171:3a7713b1edbc	798	* This parameter can be one or a combination of the following values:
AnnaBridge	171:3a7713b1edbc	799	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	171:3a7713b1edbc	800	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	171:3a7713b1edbc	801	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	171:3a7713b1edbc	802	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge	171:3a7713b1edbc	803	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	171:3a7713b1edbc	804	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	171:3a7713b1edbc	805	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	171:3a7713b1edbc	806	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	171:3a7713b1edbc	807	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	171:3a7713b1edbc	808	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	171:3a7713b1edbc	809	* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
AnnaBridge	171:3a7713b1edbc	810	* @retval None
AnnaBridge	171:3a7713b1edbc	811	*/
AnnaBridge	171:3a7713b1edbc	812	#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
AnnaBridge	171:3a7713b1edbc	813
AnnaBridge	171:3a7713b1edbc	814	/**
AnnaBridge	171:3a7713b1edbc	815	* @brief Checks whether the specified SDMMC interrupt has occurred or not.
AnnaBridge	171:3a7713b1edbc	816	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	817	* @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
AnnaBridge	171:3a7713b1edbc	818	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	819	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	820	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	821	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	171:3a7713b1edbc	822	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	171:3a7713b1edbc	823	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	171:3a7713b1edbc	824	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	171:3a7713b1edbc	825	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	826	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	171:3a7713b1edbc	827	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	171:3a7713b1edbc	828	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	829	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	171:3a7713b1edbc	830	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	171:3a7713b1edbc	831	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	171:3a7713b1edbc	832	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	171:3a7713b1edbc	833	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	171:3a7713b1edbc	834	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	835	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	836	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	837	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	838	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	171:3a7713b1edbc	839	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	171:3a7713b1edbc	840	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	171:3a7713b1edbc	841	* @retval The new state of SDMMC_IT (SET or RESET).
AnnaBridge	171:3a7713b1edbc	842	*/
AnnaBridge	171:3a7713b1edbc	843	#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	844
AnnaBridge	171:3a7713b1edbc	845	/**
AnnaBridge	171:3a7713b1edbc	846	* @brief Clears the SDMMC's interrupt pending bits.
AnnaBridge	171:3a7713b1edbc	847	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	848	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	171:3a7713b1edbc	849	* This parameter can be one or a combination of the following values:
AnnaBridge	171:3a7713b1edbc	850	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	851	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	852	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	171:3a7713b1edbc	853	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	171:3a7713b1edbc	854	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	171:3a7713b1edbc	855	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	171:3a7713b1edbc	856	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	857	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	171:3a7713b1edbc	858	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
AnnaBridge	171:3a7713b1edbc	859	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	171:3a7713b1edbc	860	* @retval None
AnnaBridge	171:3a7713b1edbc	861	*/
AnnaBridge	171:3a7713b1edbc	862	#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	863
AnnaBridge	171:3a7713b1edbc	864	/**
AnnaBridge	171:3a7713b1edbc	865	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	171:3a7713b1edbc	866	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	867	* @retval None
AnnaBridge	171:3a7713b1edbc	868	*/
AnnaBridge	171:3a7713b1edbc	869	#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART)
AnnaBridge	171:3a7713b1edbc	870
AnnaBridge	171:3a7713b1edbc	871	/**
AnnaBridge	171:3a7713b1edbc	872	* @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge	171:3a7713b1edbc	873	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	874	* @retval None
AnnaBridge	171:3a7713b1edbc	875	*/
AnnaBridge	171:3a7713b1edbc	876	#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
AnnaBridge	171:3a7713b1edbc	877
AnnaBridge	171:3a7713b1edbc	878	/**
AnnaBridge	171:3a7713b1edbc	879	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	171:3a7713b1edbc	880	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	881	* @retval None
AnnaBridge	171:3a7713b1edbc	882	*/
AnnaBridge	171:3a7713b1edbc	883	#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP)
AnnaBridge	171:3a7713b1edbc	884
AnnaBridge	171:3a7713b1edbc	885	/**
AnnaBridge	171:3a7713b1edbc	886	* @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge	171:3a7713b1edbc	887	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	888	* @retval None
AnnaBridge	171:3a7713b1edbc	889	*/
AnnaBridge	171:3a7713b1edbc	890	#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
AnnaBridge	171:3a7713b1edbc	891
AnnaBridge	171:3a7713b1edbc	892	/**
AnnaBridge	171:3a7713b1edbc	893	* @brief Enable the SD I/O Mode Operation.
AnnaBridge	171:3a7713b1edbc	894	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	895	* @retval None
AnnaBridge	171:3a7713b1edbc	896	*/
AnnaBridge	171:3a7713b1edbc	897	#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_SDIOEN)
AnnaBridge	171:3a7713b1edbc	898
AnnaBridge	171:3a7713b1edbc	899	/**
AnnaBridge	171:3a7713b1edbc	900	* @brief Disable the SD I/O Mode Operation.
AnnaBridge	171:3a7713b1edbc	901	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	902	* @retval None
AnnaBridge	171:3a7713b1edbc	903	*/
AnnaBridge	171:3a7713b1edbc	904	#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
AnnaBridge	171:3a7713b1edbc	905
AnnaBridge	171:3a7713b1edbc	906	/**
AnnaBridge	171:3a7713b1edbc	907	* @brief Enable the SD I/O Suspend command sending.
AnnaBridge	171:3a7713b1edbc	908	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	909	* @retval None
AnnaBridge	171:3a7713b1edbc	910	*/
AnnaBridge	171:3a7713b1edbc	911	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_SDIOSUSPEND)
AnnaBridge	171:3a7713b1edbc	912
AnnaBridge	171:3a7713b1edbc	913	/**
AnnaBridge	171:3a7713b1edbc	914	* @brief Disable the SD I/O Suspend command sending.
AnnaBridge	171:3a7713b1edbc	915	* @param __INSTANCE__ Pointer to SDMMC register base
AnnaBridge	171:3a7713b1edbc	916	* @retval None
AnnaBridge	171:3a7713b1edbc	917	*/
AnnaBridge	171:3a7713b1edbc	918	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
AnnaBridge	171:3a7713b1edbc	919
AnnaBridge	171:3a7713b1edbc	920	/**
AnnaBridge	171:3a7713b1edbc	921	* @}
AnnaBridge	171:3a7713b1edbc	922	*/
AnnaBridge	171:3a7713b1edbc	923
AnnaBridge	171:3a7713b1edbc	924	/**
AnnaBridge	171:3a7713b1edbc	925	* @}
AnnaBridge	171:3a7713b1edbc	926	*/
AnnaBridge	171:3a7713b1edbc	927
AnnaBridge	171:3a7713b1edbc	928	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	929	/** @addtogroup SDMMC_LL_Exported_Functions
AnnaBridge	171:3a7713b1edbc	930	* @{
AnnaBridge	171:3a7713b1edbc	931	*/
AnnaBridge	171:3a7713b1edbc	932
AnnaBridge	171:3a7713b1edbc	933	/* Initialization/de-initialization functions **********************************/
AnnaBridge	171:3a7713b1edbc	934	/** @addtogroup HAL_SDMMC_LL_Group1
AnnaBridge	171:3a7713b1edbc	935	* @{
AnnaBridge	171:3a7713b1edbc	936	*/
AnnaBridge	171:3a7713b1edbc	937	HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	938	/**
AnnaBridge	171:3a7713b1edbc	939	* @}
AnnaBridge	171:3a7713b1edbc	940	*/
AnnaBridge	171:3a7713b1edbc	941
AnnaBridge	171:3a7713b1edbc	942	/* I/O operation functions *****************************************************/
AnnaBridge	171:3a7713b1edbc	943	/** @addtogroup HAL_SDMMC_LL_Group2
AnnaBridge	171:3a7713b1edbc	944	* @{
AnnaBridge	171:3a7713b1edbc	945	*/
AnnaBridge	171:3a7713b1edbc	946	uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	947	HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef SDMMCx, uint32_t pWriteData);
AnnaBridge	171:3a7713b1edbc	948	/**
AnnaBridge	171:3a7713b1edbc	949	* @}
AnnaBridge	171:3a7713b1edbc	950	*/
AnnaBridge	171:3a7713b1edbc	951
AnnaBridge	171:3a7713b1edbc	952	/* Peripheral Control functions ************************************************/
AnnaBridge	171:3a7713b1edbc	953	/** @addtogroup HAL_SDMMC_LL_Group3
AnnaBridge	171:3a7713b1edbc	954	* @{
AnnaBridge	171:3a7713b1edbc	955	*/
AnnaBridge	171:3a7713b1edbc	956	HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	957	HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	958	uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	959
AnnaBridge	171:3a7713b1edbc	960	/* Command path state machine (CPSM) management functions */
AnnaBridge	171:3a7713b1edbc	961	HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef SDMMCx, SDMMC_CmdInitTypeDef Command);
AnnaBridge	171:3a7713b1edbc	962	uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	963	uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
AnnaBridge	171:3a7713b1edbc	964
AnnaBridge	171:3a7713b1edbc	965	/* Data path state machine (DPSM) management functions */
AnnaBridge	171:3a7713b1edbc	966	HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef SDMMCx, SDMMC_DataInitTypeDef Data);
AnnaBridge	171:3a7713b1edbc	967	uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	968	uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	969
AnnaBridge	171:3a7713b1edbc	970	/* SDMMC Cards mode management functions */
AnnaBridge	171:3a7713b1edbc	971	HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
AnnaBridge	171:3a7713b1edbc	972
AnnaBridge	171:3a7713b1edbc	973	/* SDMMC Commands management functions */
AnnaBridge	171:3a7713b1edbc	974	uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
AnnaBridge	171:3a7713b1edbc	975	uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	171:3a7713b1edbc	976	uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	171:3a7713b1edbc	977	uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	171:3a7713b1edbc	978	uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	171:3a7713b1edbc	979	uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	171:3a7713b1edbc	980	uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	171:3a7713b1edbc	981	uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	171:3a7713b1edbc	982	uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	171:3a7713b1edbc	983	uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	984	uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	985	uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
AnnaBridge	171:3a7713b1edbc	986	uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	987	uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	988	uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	989	uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);
AnnaBridge	171:3a7713b1edbc	990	uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
AnnaBridge	171:3a7713b1edbc	991	uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	992	uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	993	uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	994	uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef SDMMCx, uint16_t pRCA);
AnnaBridge	171:3a7713b1edbc	995	uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	996	uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
AnnaBridge	171:3a7713b1edbc	997	uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	998	uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	999
AnnaBridge	171:3a7713b1edbc	1000	/**
AnnaBridge	171:3a7713b1edbc	1001	* @}
AnnaBridge	171:3a7713b1edbc	1002	*/
AnnaBridge	171:3a7713b1edbc	1003
AnnaBridge	171:3a7713b1edbc	1004	/**
AnnaBridge	171:3a7713b1edbc	1005	* @}
AnnaBridge	171:3a7713b1edbc	1006	*/
AnnaBridge	171:3a7713b1edbc	1007
AnnaBridge	171:3a7713b1edbc	1008	/**
AnnaBridge	171:3a7713b1edbc	1009	* @}
AnnaBridge	171:3a7713b1edbc	1010	*/
AnnaBridge	171:3a7713b1edbc	1011
AnnaBridge	171:3a7713b1edbc	1012	/**
AnnaBridge	171:3a7713b1edbc	1013	* @}
AnnaBridge	171:3a7713b1edbc	1014	*/
AnnaBridge	171:3a7713b1edbc	1015
AnnaBridge	171:3a7713b1edbc	1016	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1017	}
AnnaBridge	171:3a7713b1edbc	1018	#endif
AnnaBridge	171:3a7713b1edbc	1019
AnnaBridge	171:3a7713b1edbc	1020	#endif /* __STM32F7xx_LL_SDMMC_H */
AnnaBridge	171:3a7713b1edbc	1021
AnnaBridge	171:3a7713b1edbc	1022	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/