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TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f7xx_ll_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f7xx_ll_rcc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of RCC LL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F7xx_LL_RCC_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F7xx_LL_RCC_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f7xx.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F7xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	#if defined(RCC)
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @defgroup RCC_LL RCC
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	59	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
AnnaBridge	171:3a7713b1edbc	60	* @{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62
AnnaBridge	171:3a7713b1edbc	63	#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
AnnaBridge	171:3a7713b1edbc	64	static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
AnnaBridge	171:3a7713b1edbc	65	#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
AnnaBridge	171:3a7713b1edbc	66
AnnaBridge	171:3a7713b1edbc	67	/**
AnnaBridge	171:3a7713b1edbc	68	* @}
AnnaBridge	171:3a7713b1edbc	69	*/
AnnaBridge	171:3a7713b1edbc	70	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	71	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	72	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	73	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	171:3a7713b1edbc	74	* @{
AnnaBridge	171:3a7713b1edbc	75	*/
AnnaBridge	171:3a7713b1edbc	76	/**
AnnaBridge	171:3a7713b1edbc	77	* @}
AnnaBridge	171:3a7713b1edbc	78	*/
AnnaBridge	171:3a7713b1edbc	79	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	171:3a7713b1edbc	80	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	81	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	82	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	171:3a7713b1edbc	83	* @{
AnnaBridge	171:3a7713b1edbc	84	*/
AnnaBridge	171:3a7713b1edbc	85
AnnaBridge	171:3a7713b1edbc	86	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	171:3a7713b1edbc	87	* @{
AnnaBridge	171:3a7713b1edbc	88	*/
AnnaBridge	171:3a7713b1edbc	89
AnnaBridge	171:3a7713b1edbc	90	/**
AnnaBridge	171:3a7713b1edbc	91	* @brief RCC Clocks Frequency Structure
AnnaBridge	171:3a7713b1edbc	92	*/
AnnaBridge	171:3a7713b1edbc	93	typedef struct
AnnaBridge	171:3a7713b1edbc	94	{
AnnaBridge	171:3a7713b1edbc	95	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	171:3a7713b1edbc	96	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	171:3a7713b1edbc	97	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	171:3a7713b1edbc	98	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	171:3a7713b1edbc	99	} LL_RCC_ClocksTypeDef;
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	/**
AnnaBridge	171:3a7713b1edbc	102	* @}
AnnaBridge	171:3a7713b1edbc	103	*/
AnnaBridge	171:3a7713b1edbc	104
AnnaBridge	171:3a7713b1edbc	105	/**
AnnaBridge	171:3a7713b1edbc	106	* @}
AnnaBridge	171:3a7713b1edbc	107	*/
AnnaBridge	171:3a7713b1edbc	108	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	111	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	171:3a7713b1edbc	112	* @{
AnnaBridge	171:3a7713b1edbc	113	*/
AnnaBridge	171:3a7713b1edbc	114
AnnaBridge	171:3a7713b1edbc	115	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	171:3a7713b1edbc	116	* @brief Defines used to adapt values of different oscillators
AnnaBridge	171:3a7713b1edbc	117	* @note These values could be modified in the user environment according to
AnnaBridge	171:3a7713b1edbc	118	* HW set-up.
AnnaBridge	171:3a7713b1edbc	119	* @{
AnnaBridge	171:3a7713b1edbc	120	*/
AnnaBridge	171:3a7713b1edbc	121	#if !defined (HSE_VALUE)
AnnaBridge	171:3a7713b1edbc	122	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	123	#endif /* HSE_VALUE */
AnnaBridge	171:3a7713b1edbc	124
AnnaBridge	171:3a7713b1edbc	125	#if !defined (HSI_VALUE)
AnnaBridge	171:3a7713b1edbc	126	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	127	#endif /* HSI_VALUE */
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	#if !defined (LSE_VALUE)
AnnaBridge	171:3a7713b1edbc	130	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	131	#endif /* LSE_VALUE */
AnnaBridge	171:3a7713b1edbc	132
AnnaBridge	171:3a7713b1edbc	133	#if !defined (LSI_VALUE)
AnnaBridge	171:3a7713b1edbc	134	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	135	#endif /* LSI_VALUE */
AnnaBridge	171:3a7713b1edbc	136
AnnaBridge	171:3a7713b1edbc	137	#if !defined (EXTERNAL_CLOCK_VALUE)
AnnaBridge	171:3a7713b1edbc	138	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	139	#endif /* EXTERNAL_CLOCK_VALUE */
AnnaBridge	171:3a7713b1edbc	140	/**
AnnaBridge	171:3a7713b1edbc	141	* @}
AnnaBridge	171:3a7713b1edbc	142	*/
AnnaBridge	171:3a7713b1edbc	143
AnnaBridge	171:3a7713b1edbc	144	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	171:3a7713b1edbc	145	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	171:3a7713b1edbc	146	* @{
AnnaBridge	171:3a7713b1edbc	147	*/
AnnaBridge	171:3a7713b1edbc	148	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	149	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	150	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	151	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	152	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	153	#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /!< PLLI2S Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	154	#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /!< PLLSAI Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	155	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	156	/**
AnnaBridge	171:3a7713b1edbc	157	* @}
AnnaBridge	171:3a7713b1edbc	158	*/
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	171:3a7713b1edbc	161	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	171:3a7713b1edbc	162	* @{
AnnaBridge	171:3a7713b1edbc	163	*/
AnnaBridge	171:3a7713b1edbc	164	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	165	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	166	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	167	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	168	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	169	#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /!< PLLI2S Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	170	#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /!< PLLSAI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	171	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	171:3a7713b1edbc	172	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	171:3a7713b1edbc	173	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	171:3a7713b1edbc	174	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
AnnaBridge	171:3a7713b1edbc	175	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	171:3a7713b1edbc	176	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	177	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	178	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
AnnaBridge	171:3a7713b1edbc	179	/**
AnnaBridge	171:3a7713b1edbc	180	* @}
AnnaBridge	171:3a7713b1edbc	181	*/
AnnaBridge	171:3a7713b1edbc	182
AnnaBridge	171:3a7713b1edbc	183	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	171:3a7713b1edbc	184	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	171:3a7713b1edbc	185	* @{
AnnaBridge	171:3a7713b1edbc	186	*/
AnnaBridge	171:3a7713b1edbc	187	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	188	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	189	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	190	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	191	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	192	#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /!< PLLI2S Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	193	#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /!< PLLSAI Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	194	/**
AnnaBridge	171:3a7713b1edbc	195	* @}
AnnaBridge	171:3a7713b1edbc	196	*/
AnnaBridge	171:3a7713b1edbc	197
AnnaBridge	171:3a7713b1edbc	198	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
AnnaBridge	171:3a7713b1edbc	199	* @{
AnnaBridge	171:3a7713b1edbc	200	*/
AnnaBridge	171:3a7713b1edbc	201	#define LL_RCC_LSEDRIVE_LOW 0x00000000U /!< Xtal mode lower driving capability /
AnnaBridge	171:3a7713b1edbc	202	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< Xtal mode medium high driving capability /
AnnaBridge	171:3a7713b1edbc	203	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< Xtal mode medium low driving capability /
AnnaBridge	171:3a7713b1edbc	204	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
AnnaBridge	171:3a7713b1edbc	205	/**
AnnaBridge	171:3a7713b1edbc	206	* @}
AnnaBridge	171:3a7713b1edbc	207	*/
AnnaBridge	171:3a7713b1edbc	208
AnnaBridge	171:3a7713b1edbc	209	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	171:3a7713b1edbc	210	* @{
AnnaBridge	171:3a7713b1edbc	211	*/
AnnaBridge	171:3a7713b1edbc	212	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	171:3a7713b1edbc	213	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	171:3a7713b1edbc	214	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	171:3a7713b1edbc	215	/**
AnnaBridge	171:3a7713b1edbc	216	* @}
AnnaBridge	171:3a7713b1edbc	217	*/
AnnaBridge	171:3a7713b1edbc	218
AnnaBridge	171:3a7713b1edbc	219	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	171:3a7713b1edbc	220	* @{
AnnaBridge	171:3a7713b1edbc	221	*/
AnnaBridge	171:3a7713b1edbc	222	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	171:3a7713b1edbc	223	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	171:3a7713b1edbc	224	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	171:3a7713b1edbc	225	/**
AnnaBridge	171:3a7713b1edbc	226	* @}
AnnaBridge	171:3a7713b1edbc	227	*/
AnnaBridge	171:3a7713b1edbc	228
AnnaBridge	171:3a7713b1edbc	229	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	171:3a7713b1edbc	230	* @{
AnnaBridge	171:3a7713b1edbc	231	*/
AnnaBridge	171:3a7713b1edbc	232	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	171:3a7713b1edbc	233	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	234	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	235	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	236	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	237	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	171:3a7713b1edbc	238	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	171:3a7713b1edbc	239	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	171:3a7713b1edbc	240	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	171:3a7713b1edbc	241	/**
AnnaBridge	171:3a7713b1edbc	242	* @}
AnnaBridge	171:3a7713b1edbc	243	*/
AnnaBridge	171:3a7713b1edbc	244
AnnaBridge	171:3a7713b1edbc	245	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	171:3a7713b1edbc	246	* @{
AnnaBridge	171:3a7713b1edbc	247	*/
AnnaBridge	171:3a7713b1edbc	248	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	171:3a7713b1edbc	249	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	250	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	251	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	252	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	253	/**
AnnaBridge	171:3a7713b1edbc	254	* @}
AnnaBridge	171:3a7713b1edbc	255	*/
AnnaBridge	171:3a7713b1edbc	256	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	171:3a7713b1edbc	257	* @{
AnnaBridge	171:3a7713b1edbc	258	*/
AnnaBridge	171:3a7713b1edbc	259	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	171:3a7713b1edbc	260	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	261	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	262	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	263	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	264	/**
AnnaBridge	171:3a7713b1edbc	265	* @}
AnnaBridge	171:3a7713b1edbc	266	*/
AnnaBridge	171:3a7713b1edbc	267
AnnaBridge	171:3a7713b1edbc	268	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
AnnaBridge	171:3a7713b1edbc	269	* @{
AnnaBridge	171:3a7713b1edbc	270	*/
AnnaBridge	171:3a7713b1edbc	271	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1\|0x00000000U) /!< HSI selection as MCO1 source /
AnnaBridge	171:3a7713b1edbc	272	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_0 >> 16U)) /!< LSE selection as MCO1 source /
AnnaBridge	171:3a7713b1edbc	273	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_1 >> 16U)) /!< HSE selection as MCO1 source /
AnnaBridge	171:3a7713b1edbc	274	#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1\|((RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0) >> 16U)) /!< PLLCLK selection as MCO1 source /
AnnaBridge	171:3a7713b1edbc	275	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2\|0x00000000U) /!< SYSCLK selection as MCO2 source /
AnnaBridge	171:3a7713b1edbc	276	#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_0 >> 16U)) /!< PLLI2S selection as MCO2 source /
AnnaBridge	171:3a7713b1edbc	277	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_1 >> 16U)) /!< HSE selection as MCO2 source /
AnnaBridge	171:3a7713b1edbc	278	#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2\|((RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0) >> 16U)) /!< PLLCLK selection as MCO2 source /
AnnaBridge	171:3a7713b1edbc	279	/**
AnnaBridge	171:3a7713b1edbc	280	* @}
AnnaBridge	171:3a7713b1edbc	281	*/
AnnaBridge	171:3a7713b1edbc	282
AnnaBridge	171:3a7713b1edbc	283	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
AnnaBridge	171:3a7713b1edbc	284	* @{
AnnaBridge	171:3a7713b1edbc	285	*/
AnnaBridge	171:3a7713b1edbc	286	#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE\|0x00000000U) /!< MCO1 not divided /
AnnaBridge	171:3a7713b1edbc	287	#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE_2 >> 16U)) /!< MCO1 divided by 2 /
AnnaBridge	171:3a7713b1edbc	288	#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_0) >> 16U)) /!< MCO1 divided by 3 /
AnnaBridge	171:3a7713b1edbc	289	#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_1) >> 16U)) /!< MCO1 divided by 4 /
AnnaBridge	171:3a7713b1edbc	290	#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE >> 16U)) /!< MCO1 divided by 5 /
AnnaBridge	171:3a7713b1edbc	291	#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE\|0x00000000U) /!< MCO2 not divided /
AnnaBridge	171:3a7713b1edbc	292	#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE_2 >> 16U)) /!< MCO2 divided by 2 /
AnnaBridge	171:3a7713b1edbc	293	#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_0) >> 16U)) /!< MCO2 divided by 3 /
AnnaBridge	171:3a7713b1edbc	294	#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_1) >> 16U)) /!< MCO2 divided by 4 /
AnnaBridge	171:3a7713b1edbc	295	#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE >> 16U)) /!< MCO2 divided by 5 /
AnnaBridge	171:3a7713b1edbc	296	/**
AnnaBridge	171:3a7713b1edbc	297	* @}
AnnaBridge	171:3a7713b1edbc	298	*/
AnnaBridge	171:3a7713b1edbc	299
AnnaBridge	171:3a7713b1edbc	300	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
AnnaBridge	171:3a7713b1edbc	301	* @{
AnnaBridge	171:3a7713b1edbc	302	*/
AnnaBridge	171:3a7713b1edbc	303	#define LL_RCC_RTC_NOCLOCK 0x00000000U /!< HSE not divided /
AnnaBridge	171:3a7713b1edbc	304	#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /!< HSE clock divided by 2 /
AnnaBridge	171:3a7713b1edbc	305	#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 3 /
AnnaBridge	171:3a7713b1edbc	306	#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /!< HSE clock divided by 4 /
AnnaBridge	171:3a7713b1edbc	307	#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 5 /
AnnaBridge	171:3a7713b1edbc	308	#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 6 /
AnnaBridge	171:3a7713b1edbc	309	#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 7 /
AnnaBridge	171:3a7713b1edbc	310	#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /!< HSE clock divided by 8 /
AnnaBridge	171:3a7713b1edbc	311	#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 9 /
AnnaBridge	171:3a7713b1edbc	312	#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 10 /
AnnaBridge	171:3a7713b1edbc	313	#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 11 /
AnnaBridge	171:3a7713b1edbc	314	#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 12 /
AnnaBridge	171:3a7713b1edbc	315	#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 13 /
AnnaBridge	171:3a7713b1edbc	316	#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 14 /
AnnaBridge	171:3a7713b1edbc	317	#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 15 /
AnnaBridge	171:3a7713b1edbc	318	#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /!< HSE clock divided by 16 /
AnnaBridge	171:3a7713b1edbc	319	#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 17 /
AnnaBridge	171:3a7713b1edbc	320	#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 18 /
AnnaBridge	171:3a7713b1edbc	321	#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 19 /
AnnaBridge	171:3a7713b1edbc	322	#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 20 /
AnnaBridge	171:3a7713b1edbc	323	#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 21 /
AnnaBridge	171:3a7713b1edbc	324	#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 22 /
AnnaBridge	171:3a7713b1edbc	325	#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 23 /
AnnaBridge	171:3a7713b1edbc	326	#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3) /!< HSE clock divided by 24 /
AnnaBridge	171:3a7713b1edbc	327	#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 25 /
AnnaBridge	171:3a7713b1edbc	328	#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 26 /
AnnaBridge	171:3a7713b1edbc	329	#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 27 /
AnnaBridge	171:3a7713b1edbc	330	#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 28 /
AnnaBridge	171:3a7713b1edbc	331	#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 29 /
AnnaBridge	171:3a7713b1edbc	332	#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 30 /
AnnaBridge	171:3a7713b1edbc	333	#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 31 /
AnnaBridge	171:3a7713b1edbc	334	/**
AnnaBridge	171:3a7713b1edbc	335	* @}
AnnaBridge	171:3a7713b1edbc	336	*/
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	339	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	171:3a7713b1edbc	340	* @{
AnnaBridge	171:3a7713b1edbc	341	*/
AnnaBridge	171:3a7713b1edbc	342	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	171:3a7713b1edbc	343	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	171:3a7713b1edbc	344	/**
AnnaBridge	171:3a7713b1edbc	345	* @}
AnnaBridge	171:3a7713b1edbc	346	*/
AnnaBridge	171:3a7713b1edbc	347	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	348
AnnaBridge	171:3a7713b1edbc	349	/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
AnnaBridge	171:3a7713b1edbc	350	* @{
AnnaBridge	171:3a7713b1edbc	351	*/
AnnaBridge	171:3a7713b1edbc	352	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) \| 0x00000000U) /!< PCLK2 clock used as USART1 clock source /
AnnaBridge	171:3a7713b1edbc	353	#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) \| RCC_DCKCFGR2_USART1SEL_0) /!< SYSCLK clock used as USART1 clock source /
AnnaBridge	171:3a7713b1edbc	354	#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) \| RCC_DCKCFGR2_USART1SEL_1) /!< HSI clock used as USART1 clock source /
AnnaBridge	171:3a7713b1edbc	355	#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) \| RCC_DCKCFGR2_USART1SEL) /!< LSE clock used as USART1 clock source /
AnnaBridge	171:3a7713b1edbc	356	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as USART2 clock source /
AnnaBridge	171:3a7713b1edbc	357	#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) \| RCC_DCKCFGR2_USART2SEL_0) /!< SYSCLK clock used as USART2 clock source /
AnnaBridge	171:3a7713b1edbc	358	#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) \| RCC_DCKCFGR2_USART2SEL_1) /!< HSI clock used as USART2 clock source /
AnnaBridge	171:3a7713b1edbc	359	#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) \| RCC_DCKCFGR2_USART2SEL) /!< LSE clock used as USART2 clock source /
AnnaBridge	171:3a7713b1edbc	360	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as USART3 clock source /
AnnaBridge	171:3a7713b1edbc	361	#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) \| RCC_DCKCFGR2_USART3SEL_0) /!< SYSCLK clock used as USART3 clock source /
AnnaBridge	171:3a7713b1edbc	362	#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) \| RCC_DCKCFGR2_USART3SEL_1) /!< HSI clock used as USART3 clock source /
AnnaBridge	171:3a7713b1edbc	363	#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) \| RCC_DCKCFGR2_USART3SEL) /!< LSE clock used as USART3 clock source /
AnnaBridge	171:3a7713b1edbc	364	#define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) \| 0x00000000U) /!< PCLK2 clock used as USART6 clock source /
AnnaBridge	171:3a7713b1edbc	365	#define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) \| RCC_DCKCFGR2_USART6SEL_0) /!< SYSCLK clock used as USART6 clock source /
AnnaBridge	171:3a7713b1edbc	366	#define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) \| RCC_DCKCFGR2_USART6SEL_1) /!< HSI clock used as USART6 clock source /
AnnaBridge	171:3a7713b1edbc	367	#define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) \| RCC_DCKCFGR2_USART6SEL) /!< LSE clock used as USART6 clock source /
AnnaBridge	171:3a7713b1edbc	368	/**
AnnaBridge	171:3a7713b1edbc	369	* @}
AnnaBridge	171:3a7713b1edbc	370	*/
AnnaBridge	171:3a7713b1edbc	371
AnnaBridge	171:3a7713b1edbc	372	/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
AnnaBridge	171:3a7713b1edbc	373	* @{
AnnaBridge	171:3a7713b1edbc	374	*/
AnnaBridge	171:3a7713b1edbc	375	#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as UART4 clock source /
AnnaBridge	171:3a7713b1edbc	376	#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) \| RCC_DCKCFGR2_UART4SEL_0) /!< SYSCLK clock used as UART4 clock source /
AnnaBridge	171:3a7713b1edbc	377	#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) \| RCC_DCKCFGR2_UART4SEL_1) /!< HSI clock used as UART4 clock source /
AnnaBridge	171:3a7713b1edbc	378	#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) \| RCC_DCKCFGR2_UART4SEL) /!< LSE clock used as UART4 clock source /
AnnaBridge	171:3a7713b1edbc	379	#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as UART5 clock source /
AnnaBridge	171:3a7713b1edbc	380	#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) \| RCC_DCKCFGR2_UART5SEL_0) /!< SYSCLK clock used as UART5 clock source /
AnnaBridge	171:3a7713b1edbc	381	#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) \| RCC_DCKCFGR2_UART5SEL_1) /!< HSI clock used as UART5 clock source /
AnnaBridge	171:3a7713b1edbc	382	#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) \| RCC_DCKCFGR2_UART5SEL) /!< LSE clock used as UART5 clock source /
AnnaBridge	171:3a7713b1edbc	383	#define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as UART7 clock source /
AnnaBridge	171:3a7713b1edbc	384	#define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) \| RCC_DCKCFGR2_UART7SEL_0) /!< SYSCLK clock used as UART7 clock source /
AnnaBridge	171:3a7713b1edbc	385	#define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) \| RCC_DCKCFGR2_UART7SEL_1) /!< HSI clock used as UART7 clock source /
AnnaBridge	171:3a7713b1edbc	386	#define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) \| RCC_DCKCFGR2_UART7SEL) /!< LSE clock used as UART7 clock source /
AnnaBridge	171:3a7713b1edbc	387	#define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as UART8 clock source /
AnnaBridge	171:3a7713b1edbc	388	#define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) \| RCC_DCKCFGR2_UART8SEL_0) /!< SYSCLK clock used as UART8 clock source /
AnnaBridge	171:3a7713b1edbc	389	#define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) \| RCC_DCKCFGR2_UART8SEL_1) /!< HSI clock used as UART8 clock source /
AnnaBridge	171:3a7713b1edbc	390	#define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) \| RCC_DCKCFGR2_UART8SEL) /!< LSE clock used as UART8 clock source /
AnnaBridge	171:3a7713b1edbc	391	/**
AnnaBridge	171:3a7713b1edbc	392	* @}
AnnaBridge	171:3a7713b1edbc	393	*/
AnnaBridge	171:3a7713b1edbc	394
AnnaBridge	171:3a7713b1edbc	395	/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
AnnaBridge	171:3a7713b1edbc	396	* @{
AnnaBridge	171:3a7713b1edbc	397	*/
AnnaBridge	171:3a7713b1edbc	398	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL\|0x00000000U) /!< PCLK1 clock used as I2C1 clock source /
AnnaBridge	171:3a7713b1edbc	399	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL\|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /!< SYSCLK clock used as I2C1 clock source /
AnnaBridge	171:3a7713b1edbc	400	#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL\|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /!< HSI clock used as I2C1 clock source /
AnnaBridge	171:3a7713b1edbc	401	#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL\|0x00000000U) /!< PCLK1 clock used as I2C2 clock source /
AnnaBridge	171:3a7713b1edbc	402	#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL\|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /!< SYSCLK clock used as I2C2 clock source /
AnnaBridge	171:3a7713b1edbc	403	#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL\|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /!< HSI clock used as I2C2 clock source /
AnnaBridge	171:3a7713b1edbc	404	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL\|0x00000000U) /!< PCLK1 clock used as I2C3 clock source /
AnnaBridge	171:3a7713b1edbc	405	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL\|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /!< SYSCLK clock used as I2C3 clock source /
AnnaBridge	171:3a7713b1edbc	406	#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL\|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /!< HSI clock used as I2C3 clock source /
AnnaBridge	171:3a7713b1edbc	407	#if defined(I2C4)
AnnaBridge	171:3a7713b1edbc	408	#define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL\|0x00000000U) /!< PCLK1 clock used as I2C4 clock source /
AnnaBridge	171:3a7713b1edbc	409	#define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL\|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /!< SYSCLK clock used as I2C4 clock source /
AnnaBridge	171:3a7713b1edbc	410	#define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL\|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /!< HSI clock used as I2C4 clock source /
AnnaBridge	171:3a7713b1edbc	411	#endif /* I2C4 */
AnnaBridge	171:3a7713b1edbc	412	/**
AnnaBridge	171:3a7713b1edbc	413	* @}
AnnaBridge	171:3a7713b1edbc	414	*/
AnnaBridge	171:3a7713b1edbc	415
AnnaBridge	171:3a7713b1edbc	416	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
AnnaBridge	171:3a7713b1edbc	417	* @{
AnnaBridge	171:3a7713b1edbc	418	*/
AnnaBridge	171:3a7713b1edbc	419	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPTIM1 clock /
AnnaBridge	171:3a7713b1edbc	420	#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /!< LSI oscillator clock used as LPTIM1 clock /
AnnaBridge	171:3a7713b1edbc	421	#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /!< HSI oscillator clock used as LPTIM1 clock /
AnnaBridge	171:3a7713b1edbc	422	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 \| RCC_DCKCFGR2_LPTIM1SEL_0) /!< LSE oscillator clock used as LPTIM1 clock /
AnnaBridge	171:3a7713b1edbc	423	/**
AnnaBridge	171:3a7713b1edbc	424	* @}
AnnaBridge	171:3a7713b1edbc	425	*/
AnnaBridge	171:3a7713b1edbc	426
AnnaBridge	171:3a7713b1edbc	427	/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
AnnaBridge	171:3a7713b1edbc	428	* @{
AnnaBridge	171:3a7713b1edbc	429	*/
AnnaBridge	171:3a7713b1edbc	430	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL \| 0x00000000U) /!< PLLSAI clock used as SAI1 clock source /
AnnaBridge	171:3a7713b1edbc	431	#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL \| (RCC_DCKCFGR1_SAI1SEL_0 >> 16U)) /!< PLLI2S clock used as SAI1 clock source /
AnnaBridge	171:3a7713b1edbc	432	#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL \| (RCC_DCKCFGR1_SAI1SEL_1 >> 16U)) /!< External pin clock used as SAI1 clock source /
AnnaBridge	171:3a7713b1edbc	433	#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
AnnaBridge	171:3a7713b1edbc	434	#define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL \| (RCC_DCKCFGR1_SAI1SEL >> 16U)) /!< Main source clock used as SAI1 clock source /
AnnaBridge	171:3a7713b1edbc	435	#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
AnnaBridge	171:3a7713b1edbc	436	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL \| 0x00000000U) /!< PLLSAI clock used as SAI2 clock source /
AnnaBridge	171:3a7713b1edbc	437	#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL \| (RCC_DCKCFGR1_SAI2SEL_0 >> 16U)) /!< PLLI2S clock used as SAI2 clock source /
AnnaBridge	171:3a7713b1edbc	438	#define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL \| (RCC_DCKCFGR1_SAI2SEL_1 >> 16U)) /!< External pin clock used as SAI2 clock source /
AnnaBridge	171:3a7713b1edbc	439	#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
AnnaBridge	171:3a7713b1edbc	440	#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL \| (RCC_DCKCFGR1_SAI2SEL >> 16U)) /!< Main source clock used as SAI2 clock source /
AnnaBridge	171:3a7713b1edbc	441	#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
AnnaBridge	171:3a7713b1edbc	442	/**
AnnaBridge	171:3a7713b1edbc	443	* @}
AnnaBridge	171:3a7713b1edbc	444	*/
AnnaBridge	171:3a7713b1edbc	445
AnnaBridge	171:3a7713b1edbc	446	/** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection
AnnaBridge	171:3a7713b1edbc	447	* @{
AnnaBridge	171:3a7713b1edbc	448	*/
AnnaBridge	171:3a7713b1edbc	449	#define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL \| 0x00000000U) /!< PLL 48M domain clock used as SDMMC1 clock /
AnnaBridge	171:3a7713b1edbc	450	#define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL \| (RCC_DCKCFGR2_SDMMC1SEL >> 16U)) /!< System clock clock used as SDMMC1 clock /
AnnaBridge	171:3a7713b1edbc	451	#if defined(SDMMC2)
AnnaBridge	171:3a7713b1edbc	452	#define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL \| 0x00000000U) /!< PLL 48M domain clock used as SDMMC2 clock /
AnnaBridge	171:3a7713b1edbc	453	#define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL \| (RCC_DCKCFGR2_SDMMC2SEL >> 16U)) /!< System clock clock used as SDMMC2 clock /
AnnaBridge	171:3a7713b1edbc	454	#endif /* SDMMC2 */
AnnaBridge	171:3a7713b1edbc	455	/**
AnnaBridge	171:3a7713b1edbc	456	* @}
AnnaBridge	171:3a7713b1edbc	457	*/
AnnaBridge	171:3a7713b1edbc	458
AnnaBridge	171:3a7713b1edbc	459	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
AnnaBridge	171:3a7713b1edbc	460	* @{
AnnaBridge	171:3a7713b1edbc	461	*/
AnnaBridge	171:3a7713b1edbc	462	#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /!< PLL clock used as RNG clock source /
AnnaBridge	171:3a7713b1edbc	463	#define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI clock used as RNG clock source /
AnnaBridge	171:3a7713b1edbc	464	/**
AnnaBridge	171:3a7713b1edbc	465	* @}
AnnaBridge	171:3a7713b1edbc	466	*/
AnnaBridge	171:3a7713b1edbc	467
AnnaBridge	171:3a7713b1edbc	468	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
AnnaBridge	171:3a7713b1edbc	469	* @{
AnnaBridge	171:3a7713b1edbc	470	*/
AnnaBridge	171:3a7713b1edbc	471	#define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /!< PLL clock used as USB clock source /
AnnaBridge	171:3a7713b1edbc	472	#define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI1 clock used as USB clock source /
AnnaBridge	171:3a7713b1edbc	473	/**
AnnaBridge	171:3a7713b1edbc	474	* @}
AnnaBridge	171:3a7713b1edbc	475	*/
AnnaBridge	171:3a7713b1edbc	476
AnnaBridge	171:3a7713b1edbc	477	#if defined(DSI)
AnnaBridge	171:3a7713b1edbc	478	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
AnnaBridge	171:3a7713b1edbc	479	* @{
AnnaBridge	171:3a7713b1edbc	480	*/
AnnaBridge	171:3a7713b1edbc	481	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
AnnaBridge	171:3a7713b1edbc	482	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /!< PLL clock used as DSI byte lane clock source /
AnnaBridge	171:3a7713b1edbc	483	/**
AnnaBridge	171:3a7713b1edbc	484	* @}
AnnaBridge	171:3a7713b1edbc	485	*/
AnnaBridge	171:3a7713b1edbc	486	#endif /* DSI */
AnnaBridge	171:3a7713b1edbc	487
AnnaBridge	171:3a7713b1edbc	488	#if defined(CEC)
AnnaBridge	171:3a7713b1edbc	489	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
AnnaBridge	171:3a7713b1edbc	490	* @{
AnnaBridge	171:3a7713b1edbc	491	*/
AnnaBridge	171:3a7713b1edbc	492	#define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /!< LSE oscillator clock used as CEC clock /
AnnaBridge	171:3a7713b1edbc	493	#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /!< HSI oscillator clock divided by 488 used as CEC clock /
AnnaBridge	171:3a7713b1edbc	494	/**
AnnaBridge	171:3a7713b1edbc	495	* @}
AnnaBridge	171:3a7713b1edbc	496	*/
AnnaBridge	171:3a7713b1edbc	497	#endif /* CEC */
AnnaBridge	171:3a7713b1edbc	498
AnnaBridge	171:3a7713b1edbc	499	/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
AnnaBridge	171:3a7713b1edbc	500	* @{
AnnaBridge	171:3a7713b1edbc	501	*/
AnnaBridge	171:3a7713b1edbc	502	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /!< I2S oscillator clock used as I2S1 clock /
AnnaBridge	171:3a7713b1edbc	503	#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /!< External pin clock used as I2S1 clock /
AnnaBridge	171:3a7713b1edbc	504	/**
AnnaBridge	171:3a7713b1edbc	505	* @}
AnnaBridge	171:3a7713b1edbc	506	*/
AnnaBridge	171:3a7713b1edbc	507
AnnaBridge	171:3a7713b1edbc	508	/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
AnnaBridge	171:3a7713b1edbc	509	* @{
AnnaBridge	171:3a7713b1edbc	510	*/
AnnaBridge	171:3a7713b1edbc	511	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
AnnaBridge	171:3a7713b1edbc	512	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
AnnaBridge	171:3a7713b1edbc	513	/**
AnnaBridge	171:3a7713b1edbc	514	* @}
AnnaBridge	171:3a7713b1edbc	515	*/
AnnaBridge	171:3a7713b1edbc	516
AnnaBridge	171:3a7713b1edbc	517	#if defined(DFSDM1_Channel0)
AnnaBridge	171:3a7713b1edbc	518	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
AnnaBridge	171:3a7713b1edbc	519	* @{
AnnaBridge	171:3a7713b1edbc	520	*/
AnnaBridge	171:3a7713b1edbc	521	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /!< SAI1 clock used as DFSDM1 Audio clock /
AnnaBridge	171:3a7713b1edbc	522	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /!< SAI2 clock used as DFSDM1 Audio clock /
AnnaBridge	171:3a7713b1edbc	523	/**
AnnaBridge	171:3a7713b1edbc	524	* @}
AnnaBridge	171:3a7713b1edbc	525	*/
AnnaBridge	171:3a7713b1edbc	526
AnnaBridge	171:3a7713b1edbc	527	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
AnnaBridge	171:3a7713b1edbc	528	* @{
AnnaBridge	171:3a7713b1edbc	529	*/
AnnaBridge	171:3a7713b1edbc	530	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM1 clock /
AnnaBridge	171:3a7713b1edbc	531	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /!< System clock used as DFSDM1 clock /
AnnaBridge	171:3a7713b1edbc	532	/**
AnnaBridge	171:3a7713b1edbc	533	* @}
AnnaBridge	171:3a7713b1edbc	534	*/
AnnaBridge	171:3a7713b1edbc	535	#endif /* DFSDM1_Channel0 */
AnnaBridge	171:3a7713b1edbc	536
AnnaBridge	171:3a7713b1edbc	537	/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
AnnaBridge	171:3a7713b1edbc	538	* @{
AnnaBridge	171:3a7713b1edbc	539	*/
AnnaBridge	171:3a7713b1edbc	540	#define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /!< USART1 Clock source selection /
AnnaBridge	171:3a7713b1edbc	541	#define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /!< USART2 Clock source selection /
AnnaBridge	171:3a7713b1edbc	542	#define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /!< USART3 Clock source selection /
AnnaBridge	171:3a7713b1edbc	543	#define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /!< USART6 Clock source selection /
AnnaBridge	171:3a7713b1edbc	544	/**
AnnaBridge	171:3a7713b1edbc	545	* @}
AnnaBridge	171:3a7713b1edbc	546	*/
AnnaBridge	171:3a7713b1edbc	547
AnnaBridge	171:3a7713b1edbc	548	/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
AnnaBridge	171:3a7713b1edbc	549	* @{
AnnaBridge	171:3a7713b1edbc	550	*/
AnnaBridge	171:3a7713b1edbc	551	#define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /!< UART4 Clock source selection /
AnnaBridge	171:3a7713b1edbc	552	#define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /!< UART5 Clock source selection /
AnnaBridge	171:3a7713b1edbc	553	#define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /!< UART7 Clock source selection /
AnnaBridge	171:3a7713b1edbc	554	#define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /!< UART8 Clock source selection /
AnnaBridge	171:3a7713b1edbc	555	/**
AnnaBridge	171:3a7713b1edbc	556	* @}
AnnaBridge	171:3a7713b1edbc	557	*/
AnnaBridge	171:3a7713b1edbc	558
AnnaBridge	171:3a7713b1edbc	559	/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
AnnaBridge	171:3a7713b1edbc	560	* @{
AnnaBridge	171:3a7713b1edbc	561	*/
AnnaBridge	171:3a7713b1edbc	562	#define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /!< I2C1 Clock source selection /
AnnaBridge	171:3a7713b1edbc	563	#define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /!< I2C2 Clock source selection /
AnnaBridge	171:3a7713b1edbc	564	#define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /!< I2C3 Clock source selection /
AnnaBridge	171:3a7713b1edbc	565	#if defined(I2C4)
AnnaBridge	171:3a7713b1edbc	566	#define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /!< I2C4 Clock source selection /
AnnaBridge	171:3a7713b1edbc	567	#endif /* I2C4 */
AnnaBridge	171:3a7713b1edbc	568	/**
AnnaBridge	171:3a7713b1edbc	569	* @}
AnnaBridge	171:3a7713b1edbc	570	*/
AnnaBridge	171:3a7713b1edbc	571
AnnaBridge	171:3a7713b1edbc	572	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
AnnaBridge	171:3a7713b1edbc	573	* @{
AnnaBridge	171:3a7713b1edbc	574	*/
AnnaBridge	171:3a7713b1edbc	575	#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /!< LPTIM1 Clock source selection /
AnnaBridge	171:3a7713b1edbc	576	/**
AnnaBridge	171:3a7713b1edbc	577	* @}
AnnaBridge	171:3a7713b1edbc	578	*/
AnnaBridge	171:3a7713b1edbc	579
AnnaBridge	171:3a7713b1edbc	580	/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
AnnaBridge	171:3a7713b1edbc	581	* @{
AnnaBridge	171:3a7713b1edbc	582	*/
AnnaBridge	171:3a7713b1edbc	583	#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /!< SAI1 Clock source selection /
AnnaBridge	171:3a7713b1edbc	584	#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /!< SAI2 Clock source selection /
AnnaBridge	171:3a7713b1edbc	585	/**
AnnaBridge	171:3a7713b1edbc	586	* @}
AnnaBridge	171:3a7713b1edbc	587	*/
AnnaBridge	171:3a7713b1edbc	588
AnnaBridge	171:3a7713b1edbc	589	/** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source
AnnaBridge	171:3a7713b1edbc	590	* @{
AnnaBridge	171:3a7713b1edbc	591	*/
AnnaBridge	171:3a7713b1edbc	592	#define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /!< SDMMC1 Clock source selection /
AnnaBridge	171:3a7713b1edbc	593	#if defined(SDMMC2)
AnnaBridge	171:3a7713b1edbc	594	#define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /!< SDMMC2 Clock source selection /
AnnaBridge	171:3a7713b1edbc	595	#endif /* SDMMC2 */
AnnaBridge	171:3a7713b1edbc	596	/**
AnnaBridge	171:3a7713b1edbc	597	* @}
AnnaBridge	171:3a7713b1edbc	598	*/
AnnaBridge	171:3a7713b1edbc	599
AnnaBridge	171:3a7713b1edbc	600	/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
AnnaBridge	171:3a7713b1edbc	601	* @{
AnnaBridge	171:3a7713b1edbc	602	*/
AnnaBridge	171:3a7713b1edbc	603	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< CK48M Domain clock source selection /
AnnaBridge	171:3a7713b1edbc	604	/**
AnnaBridge	171:3a7713b1edbc	605	* @}
AnnaBridge	171:3a7713b1edbc	606	*/
AnnaBridge	171:3a7713b1edbc	607
AnnaBridge	171:3a7713b1edbc	608	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
AnnaBridge	171:3a7713b1edbc	609	* @{
AnnaBridge	171:3a7713b1edbc	610	*/
AnnaBridge	171:3a7713b1edbc	611	#define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< RNG Clock source selection /
AnnaBridge	171:3a7713b1edbc	612	/**
AnnaBridge	171:3a7713b1edbc	613	* @}
AnnaBridge	171:3a7713b1edbc	614	*/
AnnaBridge	171:3a7713b1edbc	615
AnnaBridge	171:3a7713b1edbc	616	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
AnnaBridge	171:3a7713b1edbc	617	* @{
AnnaBridge	171:3a7713b1edbc	618	*/
AnnaBridge	171:3a7713b1edbc	619	#define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< USB Clock source selection /
AnnaBridge	171:3a7713b1edbc	620	/**
AnnaBridge	171:3a7713b1edbc	621	* @}
AnnaBridge	171:3a7713b1edbc	622	*/
AnnaBridge	171:3a7713b1edbc	623
AnnaBridge	171:3a7713b1edbc	624	#if defined(CEC)
AnnaBridge	171:3a7713b1edbc	625	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
AnnaBridge	171:3a7713b1edbc	626	* @{
AnnaBridge	171:3a7713b1edbc	627	*/
AnnaBridge	171:3a7713b1edbc	628	#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /!< CEC Clock source selection /
AnnaBridge	171:3a7713b1edbc	629	/**
AnnaBridge	171:3a7713b1edbc	630	* @}
AnnaBridge	171:3a7713b1edbc	631	*/
AnnaBridge	171:3a7713b1edbc	632	#endif /* CEC */
AnnaBridge	171:3a7713b1edbc	633
AnnaBridge	171:3a7713b1edbc	634	/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
AnnaBridge	171:3a7713b1edbc	635	* @{
AnnaBridge	171:3a7713b1edbc	636	*/
AnnaBridge	171:3a7713b1edbc	637	#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /!< I2S Clock source selection /
AnnaBridge	171:3a7713b1edbc	638	/**
AnnaBridge	171:3a7713b1edbc	639	* @}
AnnaBridge	171:3a7713b1edbc	640	*/
AnnaBridge	171:3a7713b1edbc	641	#if defined(DFSDM1_Channel0)
AnnaBridge	171:3a7713b1edbc	642	/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
AnnaBridge	171:3a7713b1edbc	643	* @{
AnnaBridge	171:3a7713b1edbc	644	*/
AnnaBridge	171:3a7713b1edbc	645	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /!< DFSDM Audio Clock source selection /
AnnaBridge	171:3a7713b1edbc	646	/**
AnnaBridge	171:3a7713b1edbc	647	* @}
AnnaBridge	171:3a7713b1edbc	648	*/
AnnaBridge	171:3a7713b1edbc	649
AnnaBridge	171:3a7713b1edbc	650	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
AnnaBridge	171:3a7713b1edbc	651	* @{
AnnaBridge	171:3a7713b1edbc	652	*/
AnnaBridge	171:3a7713b1edbc	653	#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /!< DFSDM Clock source selection /
AnnaBridge	171:3a7713b1edbc	654	/**
AnnaBridge	171:3a7713b1edbc	655	* @}
AnnaBridge	171:3a7713b1edbc	656	*/
AnnaBridge	171:3a7713b1edbc	657	#endif /* DFSDM1_Channel0 */
AnnaBridge	171:3a7713b1edbc	658
AnnaBridge	171:3a7713b1edbc	659	#if defined(DSI)
AnnaBridge	171:3a7713b1edbc	660	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
AnnaBridge	171:3a7713b1edbc	661	* @{
AnnaBridge	171:3a7713b1edbc	662	*/
AnnaBridge	171:3a7713b1edbc	663	#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /!< DSI Clock source selection /
AnnaBridge	171:3a7713b1edbc	664	/**
AnnaBridge	171:3a7713b1edbc	665	* @}
AnnaBridge	171:3a7713b1edbc	666	*/
AnnaBridge	171:3a7713b1edbc	667	#endif /* DSI */
AnnaBridge	171:3a7713b1edbc	668
AnnaBridge	171:3a7713b1edbc	669	#if defined(LTDC)
AnnaBridge	171:3a7713b1edbc	670	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
AnnaBridge	171:3a7713b1edbc	671	* @{
AnnaBridge	171:3a7713b1edbc	672	*/
AnnaBridge	171:3a7713b1edbc	673	#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /!< LTDC Clock source selection /
AnnaBridge	171:3a7713b1edbc	674	/**
AnnaBridge	171:3a7713b1edbc	675	* @}
AnnaBridge	171:3a7713b1edbc	676	*/
AnnaBridge	171:3a7713b1edbc	677	#endif /* LTDC */
AnnaBridge	171:3a7713b1edbc	678
AnnaBridge	171:3a7713b1edbc	679	#if defined(SPDIFRX)
AnnaBridge	171:3a7713b1edbc	680	/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
AnnaBridge	171:3a7713b1edbc	681	* @{
AnnaBridge	171:3a7713b1edbc	682	*/
AnnaBridge	171:3a7713b1edbc	683	#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /!< SPDIFRX Clock source selection /
AnnaBridge	171:3a7713b1edbc	684	/**
AnnaBridge	171:3a7713b1edbc	685	* @}
AnnaBridge	171:3a7713b1edbc	686	*/
AnnaBridge	171:3a7713b1edbc	687	#endif /* SPDIFRX */
AnnaBridge	171:3a7713b1edbc	688
AnnaBridge	171:3a7713b1edbc	689	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	171:3a7713b1edbc	690	* @{
AnnaBridge	171:3a7713b1edbc	691	*/
AnnaBridge	171:3a7713b1edbc	692	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	693	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	694	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	695	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by HSE prescaler used as RTC clock /
AnnaBridge	171:3a7713b1edbc	696	/**
AnnaBridge	171:3a7713b1edbc	697	* @}
AnnaBridge	171:3a7713b1edbc	698	*/
AnnaBridge	171:3a7713b1edbc	699
AnnaBridge	171:3a7713b1edbc	700	/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
AnnaBridge	171:3a7713b1edbc	701	* @{
AnnaBridge	171:3a7713b1edbc	702	*/
AnnaBridge	171:3a7713b1edbc	703	#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /!< Timers clock to twice PCLK /
AnnaBridge	171:3a7713b1edbc	704	#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /!< Timers clock to four time PCLK /
AnnaBridge	171:3a7713b1edbc	705	/**
AnnaBridge	171:3a7713b1edbc	706	* @}
AnnaBridge	171:3a7713b1edbc	707	*/
AnnaBridge	171:3a7713b1edbc	708
AnnaBridge	171:3a7713b1edbc	709	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
AnnaBridge	171:3a7713b1edbc	710	* @{
AnnaBridge	171:3a7713b1edbc	711	*/
AnnaBridge	171:3a7713b1edbc	712	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	713	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	714	/**
AnnaBridge	171:3a7713b1edbc	715	* @}
AnnaBridge	171:3a7713b1edbc	716	*/
AnnaBridge	171:3a7713b1edbc	717
AnnaBridge	171:3a7713b1edbc	718	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
AnnaBridge	171:3a7713b1edbc	719	* @{
AnnaBridge	171:3a7713b1edbc	720	*/
AnnaBridge	171:3a7713b1edbc	721	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 2 /
AnnaBridge	171:3a7713b1edbc	722	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 3 /
AnnaBridge	171:3a7713b1edbc	723	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 4 /
AnnaBridge	171:3a7713b1edbc	724	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 5 /
AnnaBridge	171:3a7713b1edbc	725	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 6 /
AnnaBridge	171:3a7713b1edbc	726	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 7 /
AnnaBridge	171:3a7713b1edbc	727	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 8 /
AnnaBridge	171:3a7713b1edbc	728	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 9 /
AnnaBridge	171:3a7713b1edbc	729	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 10 /
AnnaBridge	171:3a7713b1edbc	730	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 11 /
AnnaBridge	171:3a7713b1edbc	731	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 12 /
AnnaBridge	171:3a7713b1edbc	732	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 13 /
AnnaBridge	171:3a7713b1edbc	733	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 14 /
AnnaBridge	171:3a7713b1edbc	734	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 15 /
AnnaBridge	171:3a7713b1edbc	735	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 16 /
AnnaBridge	171:3a7713b1edbc	736	#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 17 /
AnnaBridge	171:3a7713b1edbc	737	#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 18 /
AnnaBridge	171:3a7713b1edbc	738	#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 19 /
AnnaBridge	171:3a7713b1edbc	739	#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 20 /
AnnaBridge	171:3a7713b1edbc	740	#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 21 /
AnnaBridge	171:3a7713b1edbc	741	#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 22 /
AnnaBridge	171:3a7713b1edbc	742	#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 23 /
AnnaBridge	171:3a7713b1edbc	743	#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 24 /
AnnaBridge	171:3a7713b1edbc	744	#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 25 /
AnnaBridge	171:3a7713b1edbc	745	#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 26 /
AnnaBridge	171:3a7713b1edbc	746	#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 27 /
AnnaBridge	171:3a7713b1edbc	747	#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 28 /
AnnaBridge	171:3a7713b1edbc	748	#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 29 /
AnnaBridge	171:3a7713b1edbc	749	#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 30 /
AnnaBridge	171:3a7713b1edbc	750	#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 31 /
AnnaBridge	171:3a7713b1edbc	751	#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /!< PLL, PLLI2S and PLLSAI division factor by 32 /
AnnaBridge	171:3a7713b1edbc	752	#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 33 /
AnnaBridge	171:3a7713b1edbc	753	#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 34 /
AnnaBridge	171:3a7713b1edbc	754	#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 35 /
AnnaBridge	171:3a7713b1edbc	755	#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 36 /
AnnaBridge	171:3a7713b1edbc	756	#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 37 /
AnnaBridge	171:3a7713b1edbc	757	#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 38 /
AnnaBridge	171:3a7713b1edbc	758	#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 39 /
AnnaBridge	171:3a7713b1edbc	759	#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 40 /
AnnaBridge	171:3a7713b1edbc	760	#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 41 /
AnnaBridge	171:3a7713b1edbc	761	#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 42 /
AnnaBridge	171:3a7713b1edbc	762	#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 43 /
AnnaBridge	171:3a7713b1edbc	763	#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 44 /
AnnaBridge	171:3a7713b1edbc	764	#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 45 /
AnnaBridge	171:3a7713b1edbc	765	#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 46 /
AnnaBridge	171:3a7713b1edbc	766	#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 47 /
AnnaBridge	171:3a7713b1edbc	767	#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 48 /
AnnaBridge	171:3a7713b1edbc	768	#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 49 /
AnnaBridge	171:3a7713b1edbc	769	#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 50 /
AnnaBridge	171:3a7713b1edbc	770	#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 51 /
AnnaBridge	171:3a7713b1edbc	771	#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 52 /
AnnaBridge	171:3a7713b1edbc	772	#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 53 /
AnnaBridge	171:3a7713b1edbc	773	#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 54 /
AnnaBridge	171:3a7713b1edbc	774	#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 55 /
AnnaBridge	171:3a7713b1edbc	775	#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 56 /
AnnaBridge	171:3a7713b1edbc	776	#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 57 /
AnnaBridge	171:3a7713b1edbc	777	#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 58 /
AnnaBridge	171:3a7713b1edbc	778	#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 59 /
AnnaBridge	171:3a7713b1edbc	779	#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 60 /
AnnaBridge	171:3a7713b1edbc	780	#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 61 /
AnnaBridge	171:3a7713b1edbc	781	#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 62 /
AnnaBridge	171:3a7713b1edbc	782	#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 63 /
AnnaBridge	171:3a7713b1edbc	783	/**
AnnaBridge	171:3a7713b1edbc	784	* @}
AnnaBridge	171:3a7713b1edbc	785	*/
AnnaBridge	171:3a7713b1edbc	786
AnnaBridge	171:3a7713b1edbc	787	#if defined(RCC_PLLCFGR_PLLR)
AnnaBridge	171:3a7713b1edbc	788	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
AnnaBridge	171:3a7713b1edbc	789	* @{
AnnaBridge	171:3a7713b1edbc	790	*/
AnnaBridge	171:3a7713b1edbc	791	#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 2 /
AnnaBridge	171:3a7713b1edbc	792	#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 3 /
AnnaBridge	171:3a7713b1edbc	793	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
AnnaBridge	171:3a7713b1edbc	794	#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 5 /
AnnaBridge	171:3a7713b1edbc	795	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
AnnaBridge	171:3a7713b1edbc	796	#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 7 /
AnnaBridge	171:3a7713b1edbc	797	/**
AnnaBridge	171:3a7713b1edbc	798	* @}
AnnaBridge	171:3a7713b1edbc	799	*/
AnnaBridge	171:3a7713b1edbc	800	#endif /* RCC_PLLCFGR_PLLR */
AnnaBridge	171:3a7713b1edbc	801
AnnaBridge	171:3a7713b1edbc	802	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
AnnaBridge	171:3a7713b1edbc	803	* @{
AnnaBridge	171:3a7713b1edbc	804	*/
AnnaBridge	171:3a7713b1edbc	805	#define LL_RCC_PLLP_DIV_2 0x00000000U /!< Main PLL division factor for PLLP output by 2 /
AnnaBridge	171:3a7713b1edbc	806	#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /!< Main PLL division factor for PLLP output by 4 /
AnnaBridge	171:3a7713b1edbc	807	#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /!< Main PLL division factor for PLLP output by 6 /
AnnaBridge	171:3a7713b1edbc	808	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 \| RCC_PLLCFGR_PLLP_0) /!< Main PLL division factor for PLLP output by 8 /
AnnaBridge	171:3a7713b1edbc	809	/**
AnnaBridge	171:3a7713b1edbc	810	* @}
AnnaBridge	171:3a7713b1edbc	811	*/
AnnaBridge	171:3a7713b1edbc	812
AnnaBridge	171:3a7713b1edbc	813	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
AnnaBridge	171:3a7713b1edbc	814	* @{
AnnaBridge	171:3a7713b1edbc	815	*/
AnnaBridge	171:3a7713b1edbc	816	#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /!< Main PLL division factor for PLLQ output by 2 /
AnnaBridge	171:3a7713b1edbc	817	#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 3 /
AnnaBridge	171:3a7713b1edbc	818	#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /!< Main PLL division factor for PLLQ output by 4 /
AnnaBridge	171:3a7713b1edbc	819	#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 5 /
AnnaBridge	171:3a7713b1edbc	820	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
AnnaBridge	171:3a7713b1edbc	821	#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 7 /
AnnaBridge	171:3a7713b1edbc	822	#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /!< Main PLL division factor for PLLQ output by 8 /
AnnaBridge	171:3a7713b1edbc	823	#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 9 /
AnnaBridge	171:3a7713b1edbc	824	#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 10 /
AnnaBridge	171:3a7713b1edbc	825	#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 11 /
AnnaBridge	171:3a7713b1edbc	826	#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2) /!< Main PLL division factor for PLLQ output by 12 /
AnnaBridge	171:3a7713b1edbc	827	#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 13 /
AnnaBridge	171:3a7713b1edbc	828	#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 14 /
AnnaBridge	171:3a7713b1edbc	829	#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 15 /
AnnaBridge	171:3a7713b1edbc	830	/**
AnnaBridge	171:3a7713b1edbc	831	* @}
AnnaBridge	171:3a7713b1edbc	832	*/
AnnaBridge	171:3a7713b1edbc	833
AnnaBridge	171:3a7713b1edbc	834	/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
AnnaBridge	171:3a7713b1edbc	835	* @{
AnnaBridge	171:3a7713b1edbc	836	*/
AnnaBridge	171:3a7713b1edbc	837	#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /!< PLL center spread spectrum selection /
AnnaBridge	171:3a7713b1edbc	838	#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /!< PLL down spread spectrum selection /
AnnaBridge	171:3a7713b1edbc	839	/**
AnnaBridge	171:3a7713b1edbc	840	* @}
AnnaBridge	171:3a7713b1edbc	841	*/
AnnaBridge	171:3a7713b1edbc	842
AnnaBridge	171:3a7713b1edbc	843	/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
AnnaBridge	171:3a7713b1edbc	844	* @{
AnnaBridge	171:3a7713b1edbc	845	*/
AnnaBridge	171:3a7713b1edbc	846	#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /!< PLLI2S division factor for PLLI2SQ output by 2 /
AnnaBridge	171:3a7713b1edbc	847	#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 3 /
AnnaBridge	171:3a7713b1edbc	848	#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /!< PLLI2S division factor for PLLI2SQ output by 4 /
AnnaBridge	171:3a7713b1edbc	849	#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 5 /
AnnaBridge	171:3a7713b1edbc	850	#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 6 /
AnnaBridge	171:3a7713b1edbc	851	#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 7 /
AnnaBridge	171:3a7713b1edbc	852	#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /!< PLLI2S division factor for PLLI2SQ output by 8 /
AnnaBridge	171:3a7713b1edbc	853	#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 9 /
AnnaBridge	171:3a7713b1edbc	854	#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 10 /
AnnaBridge	171:3a7713b1edbc	855	#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 11 /
AnnaBridge	171:3a7713b1edbc	856	#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2) /!< PLLI2S division factor for PLLI2SQ output by 12 /
AnnaBridge	171:3a7713b1edbc	857	#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 13 /
AnnaBridge	171:3a7713b1edbc	858	#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 14 /
AnnaBridge	171:3a7713b1edbc	859	#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 15 /
AnnaBridge	171:3a7713b1edbc	860	/**
AnnaBridge	171:3a7713b1edbc	861	* @}
AnnaBridge	171:3a7713b1edbc	862	*/
AnnaBridge	171:3a7713b1edbc	863
AnnaBridge	171:3a7713b1edbc	864	/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
AnnaBridge	171:3a7713b1edbc	865	* @{
AnnaBridge	171:3a7713b1edbc	866	*/
AnnaBridge	171:3a7713b1edbc	867	#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /!< PLLI2S division factor for PLLI2SDIVQ output by 1 /
AnnaBridge	171:3a7713b1edbc	868	#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /!< PLLI2S division factor for PLLI2SDIVQ output by 2 /
AnnaBridge	171:3a7713b1edbc	869	#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /!< PLLI2S division factor for PLLI2SDIVQ output by 3 /
AnnaBridge	171:3a7713b1edbc	870	#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 4 /
AnnaBridge	171:3a7713b1edbc	871	#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /!< PLLI2S division factor for PLLI2SDIVQ output by 5 /
AnnaBridge	171:3a7713b1edbc	872	#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 6 /
AnnaBridge	171:3a7713b1edbc	873	#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 7 /
AnnaBridge	171:3a7713b1edbc	874	#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 8 /
AnnaBridge	171:3a7713b1edbc	875	#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /!< PLLI2S division factor for PLLI2SDIVQ output by 9 /
AnnaBridge	171:3a7713b1edbc	876	#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 10 /
AnnaBridge	171:3a7713b1edbc	877	#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 11 /
AnnaBridge	171:3a7713b1edbc	878	#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 12 /
AnnaBridge	171:3a7713b1edbc	879	#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 13 /
AnnaBridge	171:3a7713b1edbc	880	#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 14 /
AnnaBridge	171:3a7713b1edbc	881	#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 15 /
AnnaBridge	171:3a7713b1edbc	882	#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 16 /
AnnaBridge	171:3a7713b1edbc	883	#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /!< PLLI2S division factor for PLLI2SDIVQ output by 17 /
AnnaBridge	171:3a7713b1edbc	884	#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 18 /
AnnaBridge	171:3a7713b1edbc	885	#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 19 /
AnnaBridge	171:3a7713b1edbc	886	#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 20 /
AnnaBridge	171:3a7713b1edbc	887	#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 21 /
AnnaBridge	171:3a7713b1edbc	888	#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 22 /
AnnaBridge	171:3a7713b1edbc	889	#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 23 /
AnnaBridge	171:3a7713b1edbc	890	#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 24 /
AnnaBridge	171:3a7713b1edbc	891	#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3) /!< PLLI2S division factor for PLLI2SDIVQ output by 25 /
AnnaBridge	171:3a7713b1edbc	892	#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 26 /
AnnaBridge	171:3a7713b1edbc	893	#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 27 /
AnnaBridge	171:3a7713b1edbc	894	#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 28 /
AnnaBridge	171:3a7713b1edbc	895	#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 29 /
AnnaBridge	171:3a7713b1edbc	896	#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 30 /
AnnaBridge	171:3a7713b1edbc	897	#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 31 /
AnnaBridge	171:3a7713b1edbc	898	#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 32 /
AnnaBridge	171:3a7713b1edbc	899	/**
AnnaBridge	171:3a7713b1edbc	900	* @}
AnnaBridge	171:3a7713b1edbc	901	*/
AnnaBridge	171:3a7713b1edbc	902
AnnaBridge	171:3a7713b1edbc	903	/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
AnnaBridge	171:3a7713b1edbc	904	* @{
AnnaBridge	171:3a7713b1edbc	905	*/
AnnaBridge	171:3a7713b1edbc	906	#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /!< PLLI2S division factor for PLLI2SR output by 2 /
AnnaBridge	171:3a7713b1edbc	907	#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 3 /
AnnaBridge	171:3a7713b1edbc	908	#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /!< PLLI2S division factor for PLLI2SR output by 4 /
AnnaBridge	171:3a7713b1edbc	909	#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 5 /
AnnaBridge	171:3a7713b1edbc	910	#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1) /!< PLLI2S division factor for PLLI2SR output by 6 /
AnnaBridge	171:3a7713b1edbc	911	#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 7 /
AnnaBridge	171:3a7713b1edbc	912	/**
AnnaBridge	171:3a7713b1edbc	913	* @}
AnnaBridge	171:3a7713b1edbc	914	*/
AnnaBridge	171:3a7713b1edbc	915
AnnaBridge	171:3a7713b1edbc	916	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
AnnaBridge	171:3a7713b1edbc	917	/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
AnnaBridge	171:3a7713b1edbc	918	* @{
AnnaBridge	171:3a7713b1edbc	919	*/
AnnaBridge	171:3a7713b1edbc	920	#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /!< PLLI2S division factor for PLLI2SP output by 2 /
AnnaBridge	171:3a7713b1edbc	921	#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /!< PLLI2S division factor for PLLI2SP output by 4 /
AnnaBridge	171:3a7713b1edbc	922	#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /!< PLLI2S division factor for PLLI2SP output by 6 /
AnnaBridge	171:3a7713b1edbc	923	#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 \| RCC_PLLI2SCFGR_PLLI2SP_0) /!< PLLI2S division factor for PLLI2SP output by 8 /
AnnaBridge	171:3a7713b1edbc	924	/**
AnnaBridge	171:3a7713b1edbc	925	* @}
AnnaBridge	171:3a7713b1edbc	926	*/
AnnaBridge	171:3a7713b1edbc	927	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
AnnaBridge	171:3a7713b1edbc	928
AnnaBridge	171:3a7713b1edbc	929	/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
AnnaBridge	171:3a7713b1edbc	930	* @{
AnnaBridge	171:3a7713b1edbc	931	*/
AnnaBridge	171:3a7713b1edbc	932	#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /!< PLLSAI division factor for PLLSAIQ output by 2 /
AnnaBridge	171:3a7713b1edbc	933	#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 3 /
AnnaBridge	171:3a7713b1edbc	934	#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /!< PLLSAI division factor for PLLSAIQ output by 4 /
AnnaBridge	171:3a7713b1edbc	935	#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 5 /
AnnaBridge	171:3a7713b1edbc	936	#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 6 /
AnnaBridge	171:3a7713b1edbc	937	#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 7 /
AnnaBridge	171:3a7713b1edbc	938	#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /!< PLLSAI division factor for PLLSAIQ output by 8 /
AnnaBridge	171:3a7713b1edbc	939	#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 9 /
AnnaBridge	171:3a7713b1edbc	940	#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 10 /
AnnaBridge	171:3a7713b1edbc	941	#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 11 /
AnnaBridge	171:3a7713b1edbc	942	#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2) /!< PLLSAI division factor for PLLSAIQ output by 12 /
AnnaBridge	171:3a7713b1edbc	943	#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 13 /
AnnaBridge	171:3a7713b1edbc	944	#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 14 /
AnnaBridge	171:3a7713b1edbc	945	#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 15 /
AnnaBridge	171:3a7713b1edbc	946	/**
AnnaBridge	171:3a7713b1edbc	947	* @}
AnnaBridge	171:3a7713b1edbc	948	*/
AnnaBridge	171:3a7713b1edbc	949
AnnaBridge	171:3a7713b1edbc	950	/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
AnnaBridge	171:3a7713b1edbc	951	* @{
AnnaBridge	171:3a7713b1edbc	952	*/
AnnaBridge	171:3a7713b1edbc	953	#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /!< PLLSAI division factor for PLLSAIDIVQ output by 1 /
AnnaBridge	171:3a7713b1edbc	954	#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /!< PLLSAI division factor for PLLSAIDIVQ output by 2 /
AnnaBridge	171:3a7713b1edbc	955	#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /!< PLLSAI division factor for PLLSAIDIVQ output by 3 /
AnnaBridge	171:3a7713b1edbc	956	#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 4 /
AnnaBridge	171:3a7713b1edbc	957	#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /!< PLLSAI division factor for PLLSAIDIVQ output by 5 /
AnnaBridge	171:3a7713b1edbc	958	#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 6 /
AnnaBridge	171:3a7713b1edbc	959	#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 7 /
AnnaBridge	171:3a7713b1edbc	960	#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 8 /
AnnaBridge	171:3a7713b1edbc	961	#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /!< PLLSAI division factor for PLLSAIDIVQ output by 9 /
AnnaBridge	171:3a7713b1edbc	962	#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 10 /
AnnaBridge	171:3a7713b1edbc	963	#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 11 /
AnnaBridge	171:3a7713b1edbc	964	#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 12 /
AnnaBridge	171:3a7713b1edbc	965	#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 13 /
AnnaBridge	171:3a7713b1edbc	966	#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 14 /
AnnaBridge	171:3a7713b1edbc	967	#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 15 /
AnnaBridge	171:3a7713b1edbc	968	#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 16 /
AnnaBridge	171:3a7713b1edbc	969	#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /!< PLLSAI division factor for PLLSAIDIVQ output by 17 /
AnnaBridge	171:3a7713b1edbc	970	#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 18 /
AnnaBridge	171:3a7713b1edbc	971	#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 19 /
AnnaBridge	171:3a7713b1edbc	972	#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 20 /
AnnaBridge	171:3a7713b1edbc	973	#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 21 /
AnnaBridge	171:3a7713b1edbc	974	#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 22 /
AnnaBridge	171:3a7713b1edbc	975	#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 23 /
AnnaBridge	171:3a7713b1edbc	976	#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 24 /
AnnaBridge	171:3a7713b1edbc	977	#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3) /!< PLLSAI division factor for PLLSAIDIVQ output by 25 /
AnnaBridge	171:3a7713b1edbc	978	#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 26 /
AnnaBridge	171:3a7713b1edbc	979	#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 27 /
AnnaBridge	171:3a7713b1edbc	980	#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 28 /
AnnaBridge	171:3a7713b1edbc	981	#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 29 /
AnnaBridge	171:3a7713b1edbc	982	#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 30 /
AnnaBridge	171:3a7713b1edbc	983	#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 31 /
AnnaBridge	171:3a7713b1edbc	984	#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 32 /
AnnaBridge	171:3a7713b1edbc	985	/**
AnnaBridge	171:3a7713b1edbc	986	* @}
AnnaBridge	171:3a7713b1edbc	987	*/
AnnaBridge	171:3a7713b1edbc	988
AnnaBridge	171:3a7713b1edbc	989	#if defined(RCC_PLLSAICFGR_PLLSAIR)
AnnaBridge	171:3a7713b1edbc	990	/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
AnnaBridge	171:3a7713b1edbc	991	* @{
AnnaBridge	171:3a7713b1edbc	992	*/
AnnaBridge	171:3a7713b1edbc	993	#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /!< PLLSAI division factor for PLLSAIR output by 2 /
AnnaBridge	171:3a7713b1edbc	994	#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 3 /
AnnaBridge	171:3a7713b1edbc	995	#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /!< PLLSAI division factor for PLLSAIR output by 4 /
AnnaBridge	171:3a7713b1edbc	996	#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 5 /
AnnaBridge	171:3a7713b1edbc	997	#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1) /!< PLLSAI division factor for PLLSAIR output by 6 /
AnnaBridge	171:3a7713b1edbc	998	#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 7 /
AnnaBridge	171:3a7713b1edbc	999	/**
AnnaBridge	171:3a7713b1edbc	1000	* @}
AnnaBridge	171:3a7713b1edbc	1001	*/
AnnaBridge	171:3a7713b1edbc	1002	#endif /* RCC_PLLSAICFGR_PLLSAIR */
AnnaBridge	171:3a7713b1edbc	1003
AnnaBridge	171:3a7713b1edbc	1004	#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
AnnaBridge	171:3a7713b1edbc	1005	/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
AnnaBridge	171:3a7713b1edbc	1006	* @{
AnnaBridge	171:3a7713b1edbc	1007	*/
AnnaBridge	171:3a7713b1edbc	1008	#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIDIVR output by 2 /
AnnaBridge	171:3a7713b1edbc	1009	#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /!< PLLSAI division factor for PLLSAIDIVR output by 4 /
AnnaBridge	171:3a7713b1edbc	1010	#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /!< PLLSAI division factor for PLLSAIDIVR output by 8 /
AnnaBridge	171:3a7713b1edbc	1011	#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 \| RCC_DCKCFGR1_PLLSAIDIVR_0) /!< PLLSAI division factor for PLLSAIDIVR output by 16 /
AnnaBridge	171:3a7713b1edbc	1012	/**
AnnaBridge	171:3a7713b1edbc	1013	* @}
AnnaBridge	171:3a7713b1edbc	1014	*/
AnnaBridge	171:3a7713b1edbc	1015	#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
AnnaBridge	171:3a7713b1edbc	1016
AnnaBridge	171:3a7713b1edbc	1017	/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
AnnaBridge	171:3a7713b1edbc	1018	* @{
AnnaBridge	171:3a7713b1edbc	1019	*/
AnnaBridge	171:3a7713b1edbc	1020	#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIP output by 2 /
AnnaBridge	171:3a7713b1edbc	1021	#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /!< PLLSAI division factor for PLLSAIP output by 4 /
AnnaBridge	171:3a7713b1edbc	1022	#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /!< PLLSAI division factor for PLLSAIP output by 6 /
AnnaBridge	171:3a7713b1edbc	1023	#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 \| RCC_PLLSAICFGR_PLLSAIP_0) /!< PLLSAI division factor for PLLSAIP output by 8 /
AnnaBridge	171:3a7713b1edbc	1024	/**
AnnaBridge	171:3a7713b1edbc	1025	* @}
AnnaBridge	171:3a7713b1edbc	1026	*/
AnnaBridge	171:3a7713b1edbc	1027
AnnaBridge	171:3a7713b1edbc	1028	/**
AnnaBridge	171:3a7713b1edbc	1029	* @}
AnnaBridge	171:3a7713b1edbc	1030	*/
AnnaBridge	171:3a7713b1edbc	1031
AnnaBridge	171:3a7713b1edbc	1032	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1033	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	171:3a7713b1edbc	1034	* @{
AnnaBridge	171:3a7713b1edbc	1035	*/
AnnaBridge	171:3a7713b1edbc	1036
AnnaBridge	171:3a7713b1edbc	1037	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	171:3a7713b1edbc	1038	* @{
AnnaBridge	171:3a7713b1edbc	1039	*/
AnnaBridge	171:3a7713b1edbc	1040
AnnaBridge	171:3a7713b1edbc	1041	/**
AnnaBridge	171:3a7713b1edbc	1042	* @brief Write a value in RCC register
AnnaBridge	171:3a7713b1edbc	1043	* @param __REG__ Register to be written
AnnaBridge	171:3a7713b1edbc	1044	* @param __VALUE__ Value to be written in the register
AnnaBridge	171:3a7713b1edbc	1045	* @retval None
AnnaBridge	171:3a7713b1edbc	1046	*/
AnnaBridge	171:3a7713b1edbc	1047	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	171:3a7713b1edbc	1048
AnnaBridge	171:3a7713b1edbc	1049	/**
AnnaBridge	171:3a7713b1edbc	1050	* @brief Read a value in RCC register
AnnaBridge	171:3a7713b1edbc	1051	* @param __REG__ Register to be read
AnnaBridge	171:3a7713b1edbc	1052	* @retval Register value
AnnaBridge	171:3a7713b1edbc	1053	*/
AnnaBridge	171:3a7713b1edbc	1054	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	171:3a7713b1edbc	1055	/**
AnnaBridge	171:3a7713b1edbc	1056	* @}
AnnaBridge	171:3a7713b1edbc	1057	*/
AnnaBridge	171:3a7713b1edbc	1058
AnnaBridge	171:3a7713b1edbc	1059	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	171:3a7713b1edbc	1060	* @{
AnnaBridge	171:3a7713b1edbc	1061	*/
AnnaBridge	171:3a7713b1edbc	1062
AnnaBridge	171:3a7713b1edbc	1063	/**
AnnaBridge	171:3a7713b1edbc	1064	* @brief Helper macro to calculate the PLLCLK frequency on system domain
AnnaBridge	171:3a7713b1edbc	1065	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1066	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
AnnaBridge	171:3a7713b1edbc	1067	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1068	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1069	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1070	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1071	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1072	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1073	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1074	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1075	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1076	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1077	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1078	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1079	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1080	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1081	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1082	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1083	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1084	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1085	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1086	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1087	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1088	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1089	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1090	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1091	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1092	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1093	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1094	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1095	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1096	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1097	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1098	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1099	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1100	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1101	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1102	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1103	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1104	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1105	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1106	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1107	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1108	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1109	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1110	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1111	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1112	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1113	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1114	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1115	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1116	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1117	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1118	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1119	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1120	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1121	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1122	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1123	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1124	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1125	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1126	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1127	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1128	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1129	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1130	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1131	* @param __PLLN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1132	* @param __PLLP__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1133	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	171:3a7713b1edbc	1134	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	171:3a7713b1edbc	1135	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	171:3a7713b1edbc	1136	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	171:3a7713b1edbc	1137	* @retval PLL clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1138	*/
AnnaBridge	171:3a7713b1edbc	1139	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	171:3a7713b1edbc	1140	((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
AnnaBridge	171:3a7713b1edbc	1141
AnnaBridge	171:3a7713b1edbc	1142	/**
AnnaBridge	171:3a7713b1edbc	1143	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
AnnaBridge	171:3a7713b1edbc	1144	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1145	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
AnnaBridge	171:3a7713b1edbc	1146	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1147	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1148	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1149	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1150	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1151	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1152	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1153	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1154	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1155	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1156	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1157	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1158	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1159	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1160	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1161	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1162	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1163	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1164	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1165	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1166	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1167	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1168	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1169	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1170	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1171	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1172	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1173	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1174	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1175	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1176	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1177	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1178	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1179	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1180	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1181	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1182	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1183	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1184	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1185	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1186	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1187	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1188	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1189	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1190	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1191	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1192	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1193	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1194	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1195	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1196	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1197	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1198	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1199	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1200	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1201	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1202	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1203	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1204	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1205	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1206	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1207	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1208	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1209	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1210	* @param __PLLN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1211	* @param __PLLQ__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1212	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	171:3a7713b1edbc	1213	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	171:3a7713b1edbc	1214	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	171:3a7713b1edbc	1215	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	171:3a7713b1edbc	1216	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	171:3a7713b1edbc	1217	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	171:3a7713b1edbc	1218	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	171:3a7713b1edbc	1219	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	171:3a7713b1edbc	1220	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	171:3a7713b1edbc	1221	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	171:3a7713b1edbc	1222	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	171:3a7713b1edbc	1223	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	171:3a7713b1edbc	1224	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	171:3a7713b1edbc	1225	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	171:3a7713b1edbc	1226	* @retval PLL clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1227	*/
AnnaBridge	171:3a7713b1edbc	1228	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	171:3a7713b1edbc	1229	((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
AnnaBridge	171:3a7713b1edbc	1230
AnnaBridge	171:3a7713b1edbc	1231	#if defined(DSI)
AnnaBridge	171:3a7713b1edbc	1232	/**
AnnaBridge	171:3a7713b1edbc	1233	* @brief Helper macro to calculate the PLLCLK frequency used on DSI
AnnaBridge	171:3a7713b1edbc	1234	* @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1235	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
AnnaBridge	171:3a7713b1edbc	1236	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1237	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1238	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1239	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1240	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1241	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1242	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1243	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1244	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1245	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1246	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1247	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1248	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1249	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1250	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1251	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1252	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1253	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1254	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1255	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1256	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1257	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1258	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1259	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1260	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1261	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1262	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1263	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1264	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1265	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1266	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1267	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1268	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1269	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1270	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1271	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1272	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1273	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1274	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1275	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1276	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1277	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1278	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1279	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1280	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1281	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1282	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1283	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1284	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1285	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1286	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1287	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1288	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1289	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1290	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1291	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1292	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1293	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1294	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1295	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1296	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1297	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1298	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1299	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1300	* @param __PLLN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1301	* @param __PLLR__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1302	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	171:3a7713b1edbc	1303	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	171:3a7713b1edbc	1304	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	171:3a7713b1edbc	1305	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	171:3a7713b1edbc	1306	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	171:3a7713b1edbc	1307	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	171:3a7713b1edbc	1308	* @retval PLL clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1309	*/
AnnaBridge	171:3a7713b1edbc	1310	#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	171:3a7713b1edbc	1311	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
AnnaBridge	171:3a7713b1edbc	1312	#endif /* DSI */
AnnaBridge	171:3a7713b1edbc	1313
AnnaBridge	171:3a7713b1edbc	1314	/**
AnnaBridge	171:3a7713b1edbc	1315	* @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains
AnnaBridge	171:3a7713b1edbc	1316	* @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1317	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
AnnaBridge	171:3a7713b1edbc	1318	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1319	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1320	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1321	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1322	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1323	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1324	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1325	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1326	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1327	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1328	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1329	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1330	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1331	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1332	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1333	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1334	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1335	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1336	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1337	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1338	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1339	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1340	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1341	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1342	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1343	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1344	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1345	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1346	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1347	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1348	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1349	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1350	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1351	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1352	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1353	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1354	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1355	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1356	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1357	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1358	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1359	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1360	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1361	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1362	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1363	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1364	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1365	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1366	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1367	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1368	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1369	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1370	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1371	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1372	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1373	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1374	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1375	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1376	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1377	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1378	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1379	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1380	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1381	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1382	* @param __PLLSAIN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1383	* @param __PLLSAIQ__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1384	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
AnnaBridge	171:3a7713b1edbc	1385	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
AnnaBridge	171:3a7713b1edbc	1386	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
AnnaBridge	171:3a7713b1edbc	1387	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
AnnaBridge	171:3a7713b1edbc	1388	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
AnnaBridge	171:3a7713b1edbc	1389	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
AnnaBridge	171:3a7713b1edbc	1390	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
AnnaBridge	171:3a7713b1edbc	1391	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
AnnaBridge	171:3a7713b1edbc	1392	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
AnnaBridge	171:3a7713b1edbc	1393	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
AnnaBridge	171:3a7713b1edbc	1394	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
AnnaBridge	171:3a7713b1edbc	1395	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
AnnaBridge	171:3a7713b1edbc	1396	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
AnnaBridge	171:3a7713b1edbc	1397	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
AnnaBridge	171:3a7713b1edbc	1398	* @param __PLLSAIDIVQ__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1399	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
AnnaBridge	171:3a7713b1edbc	1400	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
AnnaBridge	171:3a7713b1edbc	1401	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
AnnaBridge	171:3a7713b1edbc	1402	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
AnnaBridge	171:3a7713b1edbc	1403	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
AnnaBridge	171:3a7713b1edbc	1404	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
AnnaBridge	171:3a7713b1edbc	1405	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
AnnaBridge	171:3a7713b1edbc	1406	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
AnnaBridge	171:3a7713b1edbc	1407	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
AnnaBridge	171:3a7713b1edbc	1408	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
AnnaBridge	171:3a7713b1edbc	1409	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
AnnaBridge	171:3a7713b1edbc	1410	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
AnnaBridge	171:3a7713b1edbc	1411	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
AnnaBridge	171:3a7713b1edbc	1412	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
AnnaBridge	171:3a7713b1edbc	1413	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
AnnaBridge	171:3a7713b1edbc	1414	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
AnnaBridge	171:3a7713b1edbc	1415	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
AnnaBridge	171:3a7713b1edbc	1416	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
AnnaBridge	171:3a7713b1edbc	1417	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
AnnaBridge	171:3a7713b1edbc	1418	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
AnnaBridge	171:3a7713b1edbc	1419	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
AnnaBridge	171:3a7713b1edbc	1420	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
AnnaBridge	171:3a7713b1edbc	1421	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
AnnaBridge	171:3a7713b1edbc	1422	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
AnnaBridge	171:3a7713b1edbc	1423	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
AnnaBridge	171:3a7713b1edbc	1424	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
AnnaBridge	171:3a7713b1edbc	1425	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
AnnaBridge	171:3a7713b1edbc	1426	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
AnnaBridge	171:3a7713b1edbc	1427	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
AnnaBridge	171:3a7713b1edbc	1428	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
AnnaBridge	171:3a7713b1edbc	1429	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
AnnaBridge	171:3a7713b1edbc	1430	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
AnnaBridge	171:3a7713b1edbc	1431	* @retval PLLSAI clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1432	*/
AnnaBridge	171:3a7713b1edbc	1433	#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
AnnaBridge	171:3a7713b1edbc	1434	(((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U)))
AnnaBridge	171:3a7713b1edbc	1435
AnnaBridge	171:3a7713b1edbc	1436	/**
AnnaBridge	171:3a7713b1edbc	1437	* @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
AnnaBridge	171:3a7713b1edbc	1438	* @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1439	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
AnnaBridge	171:3a7713b1edbc	1440	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1441	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1442	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1443	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1444	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1445	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1446	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1447	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1448	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1449	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1450	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1451	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1452	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1453	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1454	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1455	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1456	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1457	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1458	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1459	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1460	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1461	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1462	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1463	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1464	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1465	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1466	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1467	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1468	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1469	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1470	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1471	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1472	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1473	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1474	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1475	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1476	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1477	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1478	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1479	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1480	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1481	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1482	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1483	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1484	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1485	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1486	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1487	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1488	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1489	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1490	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1491	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1492	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1493	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1494	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1495	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1496	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1497	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1498	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1499	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1500	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1501	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1502	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1503	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1504	* @param __PLLSAIN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1505	* @param __PLLSAIP__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1506	* @arg @ref LL_RCC_PLLSAIP_DIV_2
AnnaBridge	171:3a7713b1edbc	1507	* @arg @ref LL_RCC_PLLSAIP_DIV_4
AnnaBridge	171:3a7713b1edbc	1508	* @arg @ref LL_RCC_PLLSAIP_DIV_6
AnnaBridge	171:3a7713b1edbc	1509	* @arg @ref LL_RCC_PLLSAIP_DIV_8
AnnaBridge	171:3a7713b1edbc	1510	* @retval PLLSAI clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1511	*/
AnnaBridge	171:3a7713b1edbc	1512	#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
AnnaBridge	171:3a7713b1edbc	1513	((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U))
AnnaBridge	171:3a7713b1edbc	1514
AnnaBridge	171:3a7713b1edbc	1515	#if defined(LTDC)
AnnaBridge	171:3a7713b1edbc	1516	/**
AnnaBridge	171:3a7713b1edbc	1517	* @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
AnnaBridge	171:3a7713b1edbc	1518	* @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1519	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
AnnaBridge	171:3a7713b1edbc	1520	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1521	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1522	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1523	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1524	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1525	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1526	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1527	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1528	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1529	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1530	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1531	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1532	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1533	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1534	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1535	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1536	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1537	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1538	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1539	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1540	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1541	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1542	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1543	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1544	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1545	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1546	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1547	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1548	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1549	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1550	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1551	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1552	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1553	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1554	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1555	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1556	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1557	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1558	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1559	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1560	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1561	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1562	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1563	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1564	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1565	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1566	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1567	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1568	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1569	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1570	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1571	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1572	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1573	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1574	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1575	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1576	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1577	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1578	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1579	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1580	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1581	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1582	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1583	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1584	* @param __PLLSAIN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1585	* @param __PLLSAIR__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1586	* @arg @ref LL_RCC_PLLSAIR_DIV_2
AnnaBridge	171:3a7713b1edbc	1587	* @arg @ref LL_RCC_PLLSAIR_DIV_3
AnnaBridge	171:3a7713b1edbc	1588	* @arg @ref LL_RCC_PLLSAIR_DIV_4
AnnaBridge	171:3a7713b1edbc	1589	* @arg @ref LL_RCC_PLLSAIR_DIV_5
AnnaBridge	171:3a7713b1edbc	1590	* @arg @ref LL_RCC_PLLSAIR_DIV_6
AnnaBridge	171:3a7713b1edbc	1591	* @arg @ref LL_RCC_PLLSAIR_DIV_7
AnnaBridge	171:3a7713b1edbc	1592	* @param __PLLSAIDIVR__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1593	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
AnnaBridge	171:3a7713b1edbc	1594	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
AnnaBridge	171:3a7713b1edbc	1595	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
AnnaBridge	171:3a7713b1edbc	1596	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
AnnaBridge	171:3a7713b1edbc	1597	* @retval PLLSAI clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1598	*/
AnnaBridge	171:3a7713b1edbc	1599	#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
AnnaBridge	171:3a7713b1edbc	1600	(((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos])))
AnnaBridge	171:3a7713b1edbc	1601	#endif /* LTDC */
AnnaBridge	171:3a7713b1edbc	1602
AnnaBridge	171:3a7713b1edbc	1603	/**
AnnaBridge	171:3a7713b1edbc	1604	* @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains
AnnaBridge	171:3a7713b1edbc	1605	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1606	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
AnnaBridge	171:3a7713b1edbc	1607	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1608	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1609	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1610	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1611	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1612	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1613	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1614	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1615	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1616	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1617	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1618	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1619	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1620	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1621	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1622	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1623	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1624	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1625	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1626	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1627	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1628	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1629	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1630	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1631	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1632	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1633	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1634	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1635	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1636	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1637	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1638	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1639	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1640	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1641	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1642	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1643	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1644	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1645	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1646	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1647	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1648	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1649	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1650	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1651	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1652	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1653	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1654	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1655	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1656	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1657	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1658	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1659	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1660	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1661	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1662	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1663	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1664	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1665	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1666	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1667	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1668	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1669	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1670	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1671	* @param __PLLI2SN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1672	* @param __PLLI2SQ__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1673	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
AnnaBridge	171:3a7713b1edbc	1674	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
AnnaBridge	171:3a7713b1edbc	1675	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
AnnaBridge	171:3a7713b1edbc	1676	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
AnnaBridge	171:3a7713b1edbc	1677	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
AnnaBridge	171:3a7713b1edbc	1678	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
AnnaBridge	171:3a7713b1edbc	1679	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
AnnaBridge	171:3a7713b1edbc	1680	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
AnnaBridge	171:3a7713b1edbc	1681	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
AnnaBridge	171:3a7713b1edbc	1682	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
AnnaBridge	171:3a7713b1edbc	1683	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
AnnaBridge	171:3a7713b1edbc	1684	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
AnnaBridge	171:3a7713b1edbc	1685	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
AnnaBridge	171:3a7713b1edbc	1686	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
AnnaBridge	171:3a7713b1edbc	1687	* @param __PLLI2SDIVQ__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1688	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
AnnaBridge	171:3a7713b1edbc	1689	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
AnnaBridge	171:3a7713b1edbc	1690	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
AnnaBridge	171:3a7713b1edbc	1691	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
AnnaBridge	171:3a7713b1edbc	1692	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
AnnaBridge	171:3a7713b1edbc	1693	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
AnnaBridge	171:3a7713b1edbc	1694	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
AnnaBridge	171:3a7713b1edbc	1695	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
AnnaBridge	171:3a7713b1edbc	1696	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
AnnaBridge	171:3a7713b1edbc	1697	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
AnnaBridge	171:3a7713b1edbc	1698	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
AnnaBridge	171:3a7713b1edbc	1699	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
AnnaBridge	171:3a7713b1edbc	1700	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
AnnaBridge	171:3a7713b1edbc	1701	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
AnnaBridge	171:3a7713b1edbc	1702	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
AnnaBridge	171:3a7713b1edbc	1703	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
AnnaBridge	171:3a7713b1edbc	1704	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
AnnaBridge	171:3a7713b1edbc	1705	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
AnnaBridge	171:3a7713b1edbc	1706	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
AnnaBridge	171:3a7713b1edbc	1707	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
AnnaBridge	171:3a7713b1edbc	1708	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
AnnaBridge	171:3a7713b1edbc	1709	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
AnnaBridge	171:3a7713b1edbc	1710	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
AnnaBridge	171:3a7713b1edbc	1711	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
AnnaBridge	171:3a7713b1edbc	1712	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
AnnaBridge	171:3a7713b1edbc	1713	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
AnnaBridge	171:3a7713b1edbc	1714	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
AnnaBridge	171:3a7713b1edbc	1715	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
AnnaBridge	171:3a7713b1edbc	1716	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
AnnaBridge	171:3a7713b1edbc	1717	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
AnnaBridge	171:3a7713b1edbc	1718	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
AnnaBridge	171:3a7713b1edbc	1719	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
AnnaBridge	171:3a7713b1edbc	1720	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1721	*/
AnnaBridge	171:3a7713b1edbc	1722	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	171:3a7713b1edbc	1723	(((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U)))
AnnaBridge	171:3a7713b1edbc	1724
AnnaBridge	171:3a7713b1edbc	1725	#if defined(SPDIFRX)
AnnaBridge	171:3a7713b1edbc	1726	/**
AnnaBridge	171:3a7713b1edbc	1727	* @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
AnnaBridge	171:3a7713b1edbc	1728	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1729	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
AnnaBridge	171:3a7713b1edbc	1730	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1731	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1732	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1733	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1734	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1735	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1736	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1737	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1738	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1739	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1740	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1741	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1742	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1743	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1744	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1745	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1746	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1747	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1748	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1749	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1750	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1751	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1752	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1753	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1754	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1755	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1756	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1757	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1758	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1759	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1760	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1761	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1762	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1763	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1764	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1765	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1766	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1767	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1768	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1769	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1770	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1771	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1772	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1773	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1774	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1775	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1776	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1777	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1778	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1779	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1780	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1781	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1782	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1783	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1784	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1785	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1786	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1787	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1788	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1789	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1790	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1791	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1792	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1793	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1794	* @param __PLLI2SN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1795	* @param __PLLI2SP__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1796	* @arg @ref LL_RCC_PLLI2SP_DIV_2
AnnaBridge	171:3a7713b1edbc	1797	* @arg @ref LL_RCC_PLLI2SP_DIV_4
AnnaBridge	171:3a7713b1edbc	1798	* @arg @ref LL_RCC_PLLI2SP_DIV_6
AnnaBridge	171:3a7713b1edbc	1799	* @arg @ref LL_RCC_PLLI2SP_DIV_8
AnnaBridge	171:3a7713b1edbc	1800	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1801	*/
AnnaBridge	171:3a7713b1edbc	1802	#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	171:3a7713b1edbc	1803	((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
AnnaBridge	171:3a7713b1edbc	1804	#endif /* SPDIFRX */
AnnaBridge	171:3a7713b1edbc	1805
AnnaBridge	171:3a7713b1edbc	1806	/**
AnnaBridge	171:3a7713b1edbc	1807	* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
AnnaBridge	171:3a7713b1edbc	1808	* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	171:3a7713b1edbc	1809	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
AnnaBridge	171:3a7713b1edbc	1810	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	171:3a7713b1edbc	1811	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1812	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	1813	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	1814	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	1815	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	1816	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	1817	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	1818	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	1819	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	1820	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	1821	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	1822	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	1823	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	1824	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	1825	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	1826	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	1827	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	1828	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	1829	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	1830	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	1831	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	1832	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	1833	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	1834	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	1835	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	1836	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	1837	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	1838	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	1839	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	1840	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	1841	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	1842	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	1843	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	1844	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	1845	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	1846	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	1847	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	1848	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	1849	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	1850	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	1851	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	1852	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	1853	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	1854	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	1855	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	1856	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	1857	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	1858	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	1859	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	1860	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	1861	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	1862	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	1863	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	1864	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	1865	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	1866	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	1867	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	1868	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	1869	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	1870	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	1871	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	1872	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	1873	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	1874	* @param __PLLI2SN__ Between 50 and 432
AnnaBridge	171:3a7713b1edbc	1875	* @param __PLLI2SR__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1876	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	171:3a7713b1edbc	1877	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	171:3a7713b1edbc	1878	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	171:3a7713b1edbc	1879	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	171:3a7713b1edbc	1880	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	171:3a7713b1edbc	1881	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	171:3a7713b1edbc	1882	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1883	*/
AnnaBridge	171:3a7713b1edbc	1884	#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	171:3a7713b1edbc	1885	((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
AnnaBridge	171:3a7713b1edbc	1886
AnnaBridge	171:3a7713b1edbc	1887	/**
AnnaBridge	171:3a7713b1edbc	1888	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	171:3a7713b1edbc	1889	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
AnnaBridge	171:3a7713b1edbc	1890	* @param __AHBPRESCALER__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1891	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	1892	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	1893	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	1894	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	1895	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	1896	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	1897	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	1898	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	1899	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	1900	* @retval HCLK clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1901	*/
AnnaBridge	171:3a7713b1edbc	1902	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
AnnaBridge	171:3a7713b1edbc	1903
AnnaBridge	171:3a7713b1edbc	1904	/**
AnnaBridge	171:3a7713b1edbc	1905	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	171:3a7713b1edbc	1906	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	171:3a7713b1edbc	1907	* @param __APB1PRESCALER__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1908	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	1909	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	1910	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	1911	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	1912	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	1913	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1914	*/
AnnaBridge	171:3a7713b1edbc	1915	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
AnnaBridge	171:3a7713b1edbc	1916
AnnaBridge	171:3a7713b1edbc	1917	/**
AnnaBridge	171:3a7713b1edbc	1918	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	171:3a7713b1edbc	1919	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	171:3a7713b1edbc	1920	* @param __APB2PRESCALER__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1921	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	1922	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	1923	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	1924	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	1925	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	1926	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	1927	*/
AnnaBridge	171:3a7713b1edbc	1928	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
AnnaBridge	171:3a7713b1edbc	1929
AnnaBridge	171:3a7713b1edbc	1930	/**
AnnaBridge	171:3a7713b1edbc	1931	* @}
AnnaBridge	171:3a7713b1edbc	1932	*/
AnnaBridge	171:3a7713b1edbc	1933
AnnaBridge	171:3a7713b1edbc	1934	/**
AnnaBridge	171:3a7713b1edbc	1935	* @}
AnnaBridge	171:3a7713b1edbc	1936	*/
AnnaBridge	171:3a7713b1edbc	1937
AnnaBridge	171:3a7713b1edbc	1938	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1939	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	171:3a7713b1edbc	1940	* @{
AnnaBridge	171:3a7713b1edbc	1941	*/
AnnaBridge	171:3a7713b1edbc	1942
AnnaBridge	171:3a7713b1edbc	1943	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	171:3a7713b1edbc	1944	* @{
AnnaBridge	171:3a7713b1edbc	1945	*/
AnnaBridge	171:3a7713b1edbc	1946
AnnaBridge	171:3a7713b1edbc	1947	/**
AnnaBridge	171:3a7713b1edbc	1948	* @brief Enable the Clock Security System.
AnnaBridge	171:3a7713b1edbc	1949	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
AnnaBridge	171:3a7713b1edbc	1950	* @retval None
AnnaBridge	171:3a7713b1edbc	1951	*/
AnnaBridge	171:3a7713b1edbc	1952	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	171:3a7713b1edbc	1953	{
AnnaBridge	171:3a7713b1edbc	1954	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	171:3a7713b1edbc	1955	}
AnnaBridge	171:3a7713b1edbc	1956
AnnaBridge	171:3a7713b1edbc	1957	/**
AnnaBridge	171:3a7713b1edbc	1958	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	171:3a7713b1edbc	1959	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	171:3a7713b1edbc	1960	* @retval None
AnnaBridge	171:3a7713b1edbc	1961	*/
AnnaBridge	171:3a7713b1edbc	1962	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	171:3a7713b1edbc	1963	{
AnnaBridge	171:3a7713b1edbc	1964	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	171:3a7713b1edbc	1965	}
AnnaBridge	171:3a7713b1edbc	1966
AnnaBridge	171:3a7713b1edbc	1967	/**
AnnaBridge	171:3a7713b1edbc	1968	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	171:3a7713b1edbc	1969	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	171:3a7713b1edbc	1970	* @retval None
AnnaBridge	171:3a7713b1edbc	1971	*/
AnnaBridge	171:3a7713b1edbc	1972	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	171:3a7713b1edbc	1973	{
AnnaBridge	171:3a7713b1edbc	1974	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	171:3a7713b1edbc	1975	}
AnnaBridge	171:3a7713b1edbc	1976
AnnaBridge	171:3a7713b1edbc	1977	/**
AnnaBridge	171:3a7713b1edbc	1978	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	171:3a7713b1edbc	1979	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	171:3a7713b1edbc	1980	* @retval None
AnnaBridge	171:3a7713b1edbc	1981	*/
AnnaBridge	171:3a7713b1edbc	1982	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	171:3a7713b1edbc	1983	{
AnnaBridge	171:3a7713b1edbc	1984	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	171:3a7713b1edbc	1985	}
AnnaBridge	171:3a7713b1edbc	1986
AnnaBridge	171:3a7713b1edbc	1987	/**
AnnaBridge	171:3a7713b1edbc	1988	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	171:3a7713b1edbc	1989	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	171:3a7713b1edbc	1990	* @retval None
AnnaBridge	171:3a7713b1edbc	1991	*/
AnnaBridge	171:3a7713b1edbc	1992	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	171:3a7713b1edbc	1993	{
AnnaBridge	171:3a7713b1edbc	1994	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	171:3a7713b1edbc	1995	}
AnnaBridge	171:3a7713b1edbc	1996
AnnaBridge	171:3a7713b1edbc	1997	/**
AnnaBridge	171:3a7713b1edbc	1998	* @brief Check if HSE oscillator Ready
AnnaBridge	171:3a7713b1edbc	1999	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	171:3a7713b1edbc	2000	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2001	*/
AnnaBridge	171:3a7713b1edbc	2002	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	171:3a7713b1edbc	2003	{
AnnaBridge	171:3a7713b1edbc	2004	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	171:3a7713b1edbc	2005	}
AnnaBridge	171:3a7713b1edbc	2006
AnnaBridge	171:3a7713b1edbc	2007	/**
AnnaBridge	171:3a7713b1edbc	2008	* @}
AnnaBridge	171:3a7713b1edbc	2009	*/
AnnaBridge	171:3a7713b1edbc	2010
AnnaBridge	171:3a7713b1edbc	2011	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	171:3a7713b1edbc	2012	* @{
AnnaBridge	171:3a7713b1edbc	2013	*/
AnnaBridge	171:3a7713b1edbc	2014
AnnaBridge	171:3a7713b1edbc	2015	/**
AnnaBridge	171:3a7713b1edbc	2016	* @brief Enable HSI oscillator
AnnaBridge	171:3a7713b1edbc	2017	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	171:3a7713b1edbc	2018	* @retval None
AnnaBridge	171:3a7713b1edbc	2019	*/
AnnaBridge	171:3a7713b1edbc	2020	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	171:3a7713b1edbc	2021	{
AnnaBridge	171:3a7713b1edbc	2022	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	171:3a7713b1edbc	2023	}
AnnaBridge	171:3a7713b1edbc	2024
AnnaBridge	171:3a7713b1edbc	2025	/**
AnnaBridge	171:3a7713b1edbc	2026	* @brief Disable HSI oscillator
AnnaBridge	171:3a7713b1edbc	2027	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	171:3a7713b1edbc	2028	* @retval None
AnnaBridge	171:3a7713b1edbc	2029	*/
AnnaBridge	171:3a7713b1edbc	2030	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	171:3a7713b1edbc	2031	{
AnnaBridge	171:3a7713b1edbc	2032	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	171:3a7713b1edbc	2033	}
AnnaBridge	171:3a7713b1edbc	2034
AnnaBridge	171:3a7713b1edbc	2035	/**
AnnaBridge	171:3a7713b1edbc	2036	* @brief Check if HSI clock is ready
AnnaBridge	171:3a7713b1edbc	2037	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	171:3a7713b1edbc	2038	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2039	*/
AnnaBridge	171:3a7713b1edbc	2040	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	171:3a7713b1edbc	2041	{
AnnaBridge	171:3a7713b1edbc	2042	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	171:3a7713b1edbc	2043	}
AnnaBridge	171:3a7713b1edbc	2044
AnnaBridge	171:3a7713b1edbc	2045	/**
AnnaBridge	171:3a7713b1edbc	2046	* @brief Get HSI Calibration value
AnnaBridge	171:3a7713b1edbc	2047	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	171:3a7713b1edbc	2048	* HSITRIM and the factory trim value
AnnaBridge	171:3a7713b1edbc	2049	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	171:3a7713b1edbc	2050	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	171:3a7713b1edbc	2051	*/
AnnaBridge	171:3a7713b1edbc	2052	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	171:3a7713b1edbc	2053	{
AnnaBridge	171:3a7713b1edbc	2054	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
AnnaBridge	171:3a7713b1edbc	2055	}
AnnaBridge	171:3a7713b1edbc	2056
AnnaBridge	171:3a7713b1edbc	2057	/**
AnnaBridge	171:3a7713b1edbc	2058	* @brief Set HSI Calibration trimming
AnnaBridge	171:3a7713b1edbc	2059	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	171:3a7713b1edbc	2060	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	171:3a7713b1edbc	2061	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	171:3a7713b1edbc	2062	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	171:3a7713b1edbc	2063	* @param Value Between Min_Data = 0 and Max_Data = 31
AnnaBridge	171:3a7713b1edbc	2064	* @retval None
AnnaBridge	171:3a7713b1edbc	2065	*/
AnnaBridge	171:3a7713b1edbc	2066	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	171:3a7713b1edbc	2067	{
AnnaBridge	171:3a7713b1edbc	2068	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
AnnaBridge	171:3a7713b1edbc	2069	}
AnnaBridge	171:3a7713b1edbc	2070
AnnaBridge	171:3a7713b1edbc	2071	/**
AnnaBridge	171:3a7713b1edbc	2072	* @brief Get HSI Calibration trimming
AnnaBridge	171:3a7713b1edbc	2073	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	171:3a7713b1edbc	2074	* @retval Between Min_Data = 0 and Max_Data = 31
AnnaBridge	171:3a7713b1edbc	2075	*/
AnnaBridge	171:3a7713b1edbc	2076	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	171:3a7713b1edbc	2077	{
AnnaBridge	171:3a7713b1edbc	2078	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
AnnaBridge	171:3a7713b1edbc	2079	}
AnnaBridge	171:3a7713b1edbc	2080
AnnaBridge	171:3a7713b1edbc	2081	/**
AnnaBridge	171:3a7713b1edbc	2082	* @}
AnnaBridge	171:3a7713b1edbc	2083	*/
AnnaBridge	171:3a7713b1edbc	2084
AnnaBridge	171:3a7713b1edbc	2085	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	171:3a7713b1edbc	2086	* @{
AnnaBridge	171:3a7713b1edbc	2087	*/
AnnaBridge	171:3a7713b1edbc	2088
AnnaBridge	171:3a7713b1edbc	2089	/**
AnnaBridge	171:3a7713b1edbc	2090	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	171:3a7713b1edbc	2091	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
AnnaBridge	171:3a7713b1edbc	2092	* @retval None
AnnaBridge	171:3a7713b1edbc	2093	*/
AnnaBridge	171:3a7713b1edbc	2094	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	171:3a7713b1edbc	2095	{
AnnaBridge	171:3a7713b1edbc	2096	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	171:3a7713b1edbc	2097	}
AnnaBridge	171:3a7713b1edbc	2098
AnnaBridge	171:3a7713b1edbc	2099	/**
AnnaBridge	171:3a7713b1edbc	2100	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	171:3a7713b1edbc	2101	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
AnnaBridge	171:3a7713b1edbc	2102	* @retval None
AnnaBridge	171:3a7713b1edbc	2103	*/
AnnaBridge	171:3a7713b1edbc	2104	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	171:3a7713b1edbc	2105	{
AnnaBridge	171:3a7713b1edbc	2106	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	171:3a7713b1edbc	2107	}
AnnaBridge	171:3a7713b1edbc	2108
AnnaBridge	171:3a7713b1edbc	2109	/**
AnnaBridge	171:3a7713b1edbc	2110	* @brief Enable external clock source (LSE bypass).
AnnaBridge	171:3a7713b1edbc	2111	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	171:3a7713b1edbc	2112	* @retval None
AnnaBridge	171:3a7713b1edbc	2113	*/
AnnaBridge	171:3a7713b1edbc	2114	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	171:3a7713b1edbc	2115	{
AnnaBridge	171:3a7713b1edbc	2116	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	171:3a7713b1edbc	2117	}
AnnaBridge	171:3a7713b1edbc	2118
AnnaBridge	171:3a7713b1edbc	2119	/**
AnnaBridge	171:3a7713b1edbc	2120	* @brief Disable external clock source (LSE bypass).
AnnaBridge	171:3a7713b1edbc	2121	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	171:3a7713b1edbc	2122	* @retval None
AnnaBridge	171:3a7713b1edbc	2123	*/
AnnaBridge	171:3a7713b1edbc	2124	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	171:3a7713b1edbc	2125	{
AnnaBridge	171:3a7713b1edbc	2126	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	171:3a7713b1edbc	2127	}
AnnaBridge	171:3a7713b1edbc	2128
AnnaBridge	171:3a7713b1edbc	2129	/**
AnnaBridge	171:3a7713b1edbc	2130	* @brief Set LSE oscillator drive capability
AnnaBridge	171:3a7713b1edbc	2131	* @note The oscillator is in Xtal mode when it is not in bypass mode.
AnnaBridge	171:3a7713b1edbc	2132	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
AnnaBridge	171:3a7713b1edbc	2133	* @param LSEDrive This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2134	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	171:3a7713b1edbc	2135	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	171:3a7713b1edbc	2136	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	171:3a7713b1edbc	2137	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	171:3a7713b1edbc	2138	* @retval None
AnnaBridge	171:3a7713b1edbc	2139	*/
AnnaBridge	171:3a7713b1edbc	2140	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
AnnaBridge	171:3a7713b1edbc	2141	{
AnnaBridge	171:3a7713b1edbc	2142	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
AnnaBridge	171:3a7713b1edbc	2143	}
AnnaBridge	171:3a7713b1edbc	2144
AnnaBridge	171:3a7713b1edbc	2145	/**
AnnaBridge	171:3a7713b1edbc	2146	* @brief Get LSE oscillator drive capability
AnnaBridge	171:3a7713b1edbc	2147	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
AnnaBridge	171:3a7713b1edbc	2148	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2149	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	171:3a7713b1edbc	2150	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	171:3a7713b1edbc	2151	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	171:3a7713b1edbc	2152	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	171:3a7713b1edbc	2153	*/
AnnaBridge	171:3a7713b1edbc	2154	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
AnnaBridge	171:3a7713b1edbc	2155	{
AnnaBridge	171:3a7713b1edbc	2156	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
AnnaBridge	171:3a7713b1edbc	2157	}
AnnaBridge	171:3a7713b1edbc	2158
AnnaBridge	171:3a7713b1edbc	2159	/**
AnnaBridge	171:3a7713b1edbc	2160	* @brief Check if LSE oscillator Ready
AnnaBridge	171:3a7713b1edbc	2161	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	171:3a7713b1edbc	2162	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2163	*/
AnnaBridge	171:3a7713b1edbc	2164	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	171:3a7713b1edbc	2165	{
AnnaBridge	171:3a7713b1edbc	2166	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
AnnaBridge	171:3a7713b1edbc	2167	}
AnnaBridge	171:3a7713b1edbc	2168
AnnaBridge	171:3a7713b1edbc	2169	/**
AnnaBridge	171:3a7713b1edbc	2170	* @}
AnnaBridge	171:3a7713b1edbc	2171	*/
AnnaBridge	171:3a7713b1edbc	2172
AnnaBridge	171:3a7713b1edbc	2173	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	171:3a7713b1edbc	2174	* @{
AnnaBridge	171:3a7713b1edbc	2175	*/
AnnaBridge	171:3a7713b1edbc	2176
AnnaBridge	171:3a7713b1edbc	2177	/**
AnnaBridge	171:3a7713b1edbc	2178	* @brief Enable LSI Oscillator
AnnaBridge	171:3a7713b1edbc	2179	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	171:3a7713b1edbc	2180	* @retval None
AnnaBridge	171:3a7713b1edbc	2181	*/
AnnaBridge	171:3a7713b1edbc	2182	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	171:3a7713b1edbc	2183	{
AnnaBridge	171:3a7713b1edbc	2184	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	171:3a7713b1edbc	2185	}
AnnaBridge	171:3a7713b1edbc	2186
AnnaBridge	171:3a7713b1edbc	2187	/**
AnnaBridge	171:3a7713b1edbc	2188	* @brief Disable LSI Oscillator
AnnaBridge	171:3a7713b1edbc	2189	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	171:3a7713b1edbc	2190	* @retval None
AnnaBridge	171:3a7713b1edbc	2191	*/
AnnaBridge	171:3a7713b1edbc	2192	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	171:3a7713b1edbc	2193	{
AnnaBridge	171:3a7713b1edbc	2194	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	171:3a7713b1edbc	2195	}
AnnaBridge	171:3a7713b1edbc	2196
AnnaBridge	171:3a7713b1edbc	2197	/**
AnnaBridge	171:3a7713b1edbc	2198	* @brief Check if LSI is Ready
AnnaBridge	171:3a7713b1edbc	2199	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	171:3a7713b1edbc	2200	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2201	*/
AnnaBridge	171:3a7713b1edbc	2202	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	171:3a7713b1edbc	2203	{
AnnaBridge	171:3a7713b1edbc	2204	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	171:3a7713b1edbc	2205	}
AnnaBridge	171:3a7713b1edbc	2206
AnnaBridge	171:3a7713b1edbc	2207	/**
AnnaBridge	171:3a7713b1edbc	2208	* @}
AnnaBridge	171:3a7713b1edbc	2209	*/
AnnaBridge	171:3a7713b1edbc	2210
AnnaBridge	171:3a7713b1edbc	2211	/** @defgroup RCC_LL_EF_System System
AnnaBridge	171:3a7713b1edbc	2212	* @{
AnnaBridge	171:3a7713b1edbc	2213	*/
AnnaBridge	171:3a7713b1edbc	2214
AnnaBridge	171:3a7713b1edbc	2215	/**
AnnaBridge	171:3a7713b1edbc	2216	* @brief Configure the system clock source
AnnaBridge	171:3a7713b1edbc	2217	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	171:3a7713b1edbc	2218	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2219	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2220	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	2221	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2222	* @retval None
AnnaBridge	171:3a7713b1edbc	2223	*/
AnnaBridge	171:3a7713b1edbc	2224	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	2225	{
AnnaBridge	171:3a7713b1edbc	2226	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	171:3a7713b1edbc	2227	}
AnnaBridge	171:3a7713b1edbc	2228
AnnaBridge	171:3a7713b1edbc	2229	/**
AnnaBridge	171:3a7713b1edbc	2230	* @brief Get the system clock source
AnnaBridge	171:3a7713b1edbc	2231	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	171:3a7713b1edbc	2232	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2233	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	171:3a7713b1edbc	2234	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	171:3a7713b1edbc	2235	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	171:3a7713b1edbc	2236	*/
AnnaBridge	171:3a7713b1edbc	2237	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	171:3a7713b1edbc	2238	{
AnnaBridge	171:3a7713b1edbc	2239	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	171:3a7713b1edbc	2240	}
AnnaBridge	171:3a7713b1edbc	2241
AnnaBridge	171:3a7713b1edbc	2242	/**
AnnaBridge	171:3a7713b1edbc	2243	* @brief Set AHB prescaler
AnnaBridge	171:3a7713b1edbc	2244	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	171:3a7713b1edbc	2245	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2246	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	2247	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	2248	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	2249	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	2250	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	2251	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	2252	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	2253	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	2254	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	2255	* @retval None
AnnaBridge	171:3a7713b1edbc	2256	*/
AnnaBridge	171:3a7713b1edbc	2257	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	2258	{
AnnaBridge	171:3a7713b1edbc	2259	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	171:3a7713b1edbc	2260	}
AnnaBridge	171:3a7713b1edbc	2261
AnnaBridge	171:3a7713b1edbc	2262	/**
AnnaBridge	171:3a7713b1edbc	2263	* @brief Set APB1 prescaler
AnnaBridge	171:3a7713b1edbc	2264	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	171:3a7713b1edbc	2265	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2266	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	2267	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	2268	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	2269	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	2270	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	2271	* @retval None
AnnaBridge	171:3a7713b1edbc	2272	*/
AnnaBridge	171:3a7713b1edbc	2273	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	2274	{
AnnaBridge	171:3a7713b1edbc	2275	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	171:3a7713b1edbc	2276	}
AnnaBridge	171:3a7713b1edbc	2277
AnnaBridge	171:3a7713b1edbc	2278	/**
AnnaBridge	171:3a7713b1edbc	2279	* @brief Set APB2 prescaler
AnnaBridge	171:3a7713b1edbc	2280	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	171:3a7713b1edbc	2281	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2282	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	2283	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	2284	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	2285	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	2286	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	2287	* @retval None
AnnaBridge	171:3a7713b1edbc	2288	*/
AnnaBridge	171:3a7713b1edbc	2289	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	2290	{
AnnaBridge	171:3a7713b1edbc	2291	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	171:3a7713b1edbc	2292	}
AnnaBridge	171:3a7713b1edbc	2293
AnnaBridge	171:3a7713b1edbc	2294	/**
AnnaBridge	171:3a7713b1edbc	2295	* @brief Get AHB prescaler
AnnaBridge	171:3a7713b1edbc	2296	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	171:3a7713b1edbc	2297	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2298	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	2299	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	2300	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	2301	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	2302	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	2303	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	2304	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	2305	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	2306	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	2307	*/
AnnaBridge	171:3a7713b1edbc	2308	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	171:3a7713b1edbc	2309	{
AnnaBridge	171:3a7713b1edbc	2310	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	171:3a7713b1edbc	2311	}
AnnaBridge	171:3a7713b1edbc	2312
AnnaBridge	171:3a7713b1edbc	2313	/**
AnnaBridge	171:3a7713b1edbc	2314	* @brief Get APB1 prescaler
AnnaBridge	171:3a7713b1edbc	2315	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	171:3a7713b1edbc	2316	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2317	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	2318	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	2319	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	2320	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	2321	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	2322	*/
AnnaBridge	171:3a7713b1edbc	2323	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	171:3a7713b1edbc	2324	{
AnnaBridge	171:3a7713b1edbc	2325	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	171:3a7713b1edbc	2326	}
AnnaBridge	171:3a7713b1edbc	2327
AnnaBridge	171:3a7713b1edbc	2328	/**
AnnaBridge	171:3a7713b1edbc	2329	* @brief Get APB2 prescaler
AnnaBridge	171:3a7713b1edbc	2330	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	171:3a7713b1edbc	2331	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2332	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	2333	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	2334	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	2335	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	2336	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	2337	*/
AnnaBridge	171:3a7713b1edbc	2338	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	171:3a7713b1edbc	2339	{
AnnaBridge	171:3a7713b1edbc	2340	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	171:3a7713b1edbc	2341	}
AnnaBridge	171:3a7713b1edbc	2342
AnnaBridge	171:3a7713b1edbc	2343	/**
AnnaBridge	171:3a7713b1edbc	2344	* @}
AnnaBridge	171:3a7713b1edbc	2345	*/
AnnaBridge	171:3a7713b1edbc	2346
AnnaBridge	171:3a7713b1edbc	2347	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	171:3a7713b1edbc	2348	* @{
AnnaBridge	171:3a7713b1edbc	2349	*/
AnnaBridge	171:3a7713b1edbc	2350
AnnaBridge	171:3a7713b1edbc	2351	/**
AnnaBridge	171:3a7713b1edbc	2352	* @brief Configure MCOx
AnnaBridge	171:3a7713b1edbc	2353	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
AnnaBridge	171:3a7713b1edbc	2354	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
AnnaBridge	171:3a7713b1edbc	2355	* CFGR MCO2 LL_RCC_ConfigMCO\n
AnnaBridge	171:3a7713b1edbc	2356	* CFGR MCO2PRE LL_RCC_ConfigMCO
AnnaBridge	171:3a7713b1edbc	2357	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2358	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2359	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2360	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	171:3a7713b1edbc	2361	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
AnnaBridge	171:3a7713b1edbc	2362	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2363	* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
AnnaBridge	171:3a7713b1edbc	2364	* @arg @ref LL_RCC_MCO2SOURCE_HSE
AnnaBridge	171:3a7713b1edbc	2365	* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
AnnaBridge	171:3a7713b1edbc	2366	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2367	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	171:3a7713b1edbc	2368	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	171:3a7713b1edbc	2369	* @arg @ref LL_RCC_MCO1_DIV_3
AnnaBridge	171:3a7713b1edbc	2370	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	171:3a7713b1edbc	2371	* @arg @ref LL_RCC_MCO1_DIV_5
AnnaBridge	171:3a7713b1edbc	2372	* @arg @ref LL_RCC_MCO2_DIV_1
AnnaBridge	171:3a7713b1edbc	2373	* @arg @ref LL_RCC_MCO2_DIV_2
AnnaBridge	171:3a7713b1edbc	2374	* @arg @ref LL_RCC_MCO2_DIV_3
AnnaBridge	171:3a7713b1edbc	2375	* @arg @ref LL_RCC_MCO2_DIV_4
AnnaBridge	171:3a7713b1edbc	2376	* @arg @ref LL_RCC_MCO2_DIV_5
AnnaBridge	171:3a7713b1edbc	2377	* @retval None
AnnaBridge	171:3a7713b1edbc	2378	*/
AnnaBridge	171:3a7713b1edbc	2379	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	171:3a7713b1edbc	2380	{
AnnaBridge	171:3a7713b1edbc	2381	MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) \| (MCOxPrescaler << 16U));
AnnaBridge	171:3a7713b1edbc	2382	}
AnnaBridge	171:3a7713b1edbc	2383
AnnaBridge	171:3a7713b1edbc	2384	/**
AnnaBridge	171:3a7713b1edbc	2385	* @}
AnnaBridge	171:3a7713b1edbc	2386	*/
AnnaBridge	171:3a7713b1edbc	2387
AnnaBridge	171:3a7713b1edbc	2388	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	171:3a7713b1edbc	2389	* @{
AnnaBridge	171:3a7713b1edbc	2390	*/
AnnaBridge	171:3a7713b1edbc	2391
AnnaBridge	171:3a7713b1edbc	2392	/**
AnnaBridge	171:3a7713b1edbc	2393	* @brief Configure USARTx clock source
AnnaBridge	171:3a7713b1edbc	2394	* @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2395	* DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2396	* DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2397	* DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource
AnnaBridge	171:3a7713b1edbc	2398	* @param USARTxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2399	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
AnnaBridge	171:3a7713b1edbc	2400	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2401	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2402	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2403	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2404	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2405	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2406	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2407	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2408	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2409	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2410	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2411	* @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
AnnaBridge	171:3a7713b1edbc	2412	* @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2413	* @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2414	* @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2415	* @retval None
AnnaBridge	171:3a7713b1edbc	2416	*/
AnnaBridge	171:3a7713b1edbc	2417	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
AnnaBridge	171:3a7713b1edbc	2418	{
AnnaBridge	171:3a7713b1edbc	2419	MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	2420	}
AnnaBridge	171:3a7713b1edbc	2421
AnnaBridge	171:3a7713b1edbc	2422	/**
AnnaBridge	171:3a7713b1edbc	2423	* @brief Configure UARTx clock source
AnnaBridge	171:3a7713b1edbc	2424	* @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2425	* DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2426	* DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2427	* DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource
AnnaBridge	171:3a7713b1edbc	2428	* @param UARTxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2429	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2430	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2431	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2432	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2433	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2434	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2435	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2436	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2437	* @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2438	* @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2439	* @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2440	* @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2441	* @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2442	* @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2443	* @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2444	* @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2445	* @retval None
AnnaBridge	171:3a7713b1edbc	2446	*/
AnnaBridge	171:3a7713b1edbc	2447	__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
AnnaBridge	171:3a7713b1edbc	2448	{
AnnaBridge	171:3a7713b1edbc	2449	MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	2450	}
AnnaBridge	171:3a7713b1edbc	2451
AnnaBridge	171:3a7713b1edbc	2452	/**
AnnaBridge	171:3a7713b1edbc	2453	* @brief Configure I2Cx clock source
AnnaBridge	171:3a7713b1edbc	2454	* @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n
AnnaBridge	171:3a7713b1edbc	2455	* DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n
AnnaBridge	171:3a7713b1edbc	2456	* DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n
AnnaBridge	171:3a7713b1edbc	2457	* DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource
AnnaBridge	171:3a7713b1edbc	2458	* @param I2CxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2459	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2460	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2461	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2462	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2463	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2464	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2465	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2466	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2467	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2468	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	171:3a7713b1edbc	2469	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	171:3a7713b1edbc	2470	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
AnnaBridge	171:3a7713b1edbc	2471	*
AnnaBridge	171:3a7713b1edbc	2472	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	2473	* @retval None
AnnaBridge	171:3a7713b1edbc	2474	*/
AnnaBridge	171:3a7713b1edbc	2475	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
AnnaBridge	171:3a7713b1edbc	2476	{
AnnaBridge	171:3a7713b1edbc	2477	MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U));
AnnaBridge	171:3a7713b1edbc	2478	}
AnnaBridge	171:3a7713b1edbc	2479
AnnaBridge	171:3a7713b1edbc	2480	/**
AnnaBridge	171:3a7713b1edbc	2481	* @brief Configure LPTIMx clock source
AnnaBridge	171:3a7713b1edbc	2482	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
AnnaBridge	171:3a7713b1edbc	2483	* @param LPTIMxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2484	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2485	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	171:3a7713b1edbc	2486	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2487	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2488	* @retval None
AnnaBridge	171:3a7713b1edbc	2489	*/
AnnaBridge	171:3a7713b1edbc	2490	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
AnnaBridge	171:3a7713b1edbc	2491	{
AnnaBridge	171:3a7713b1edbc	2492	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
AnnaBridge	171:3a7713b1edbc	2493	}
AnnaBridge	171:3a7713b1edbc	2494
AnnaBridge	171:3a7713b1edbc	2495	/**
AnnaBridge	171:3a7713b1edbc	2496	* @brief Configure SAIx clock source
AnnaBridge	171:3a7713b1edbc	2497	* @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n
AnnaBridge	171:3a7713b1edbc	2498	* DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource
AnnaBridge	171:3a7713b1edbc	2499	* @param SAIxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2500	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2501	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
AnnaBridge	171:3a7713b1edbc	2502	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
AnnaBridge	171:3a7713b1edbc	2503	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
AnnaBridge	171:3a7713b1edbc	2504	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2505	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
AnnaBridge	171:3a7713b1edbc	2506	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
AnnaBridge	171:3a7713b1edbc	2507	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
AnnaBridge	171:3a7713b1edbc	2508	*
AnnaBridge	171:3a7713b1edbc	2509	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	2510	* @retval None
AnnaBridge	171:3a7713b1edbc	2511	*/
AnnaBridge	171:3a7713b1edbc	2512	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
AnnaBridge	171:3a7713b1edbc	2513	{
AnnaBridge	171:3a7713b1edbc	2514	MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
AnnaBridge	171:3a7713b1edbc	2515	}
AnnaBridge	171:3a7713b1edbc	2516
AnnaBridge	171:3a7713b1edbc	2517	/**
AnnaBridge	171:3a7713b1edbc	2518	* @brief Configure SDMMC clock source
AnnaBridge	171:3a7713b1edbc	2519	* @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n
AnnaBridge	171:3a7713b1edbc	2520	* DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource
AnnaBridge	171:3a7713b1edbc	2521	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2522	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
AnnaBridge	171:3a7713b1edbc	2523	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2524	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
AnnaBridge	171:3a7713b1edbc	2525	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
AnnaBridge	171:3a7713b1edbc	2526	*
AnnaBridge	171:3a7713b1edbc	2527	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	2528	* @retval None
AnnaBridge	171:3a7713b1edbc	2529	*/
AnnaBridge	171:3a7713b1edbc	2530	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
AnnaBridge	171:3a7713b1edbc	2531	{
AnnaBridge	171:3a7713b1edbc	2532	MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U));
AnnaBridge	171:3a7713b1edbc	2533	}
AnnaBridge	171:3a7713b1edbc	2534
AnnaBridge	171:3a7713b1edbc	2535	/**
AnnaBridge	171:3a7713b1edbc	2536	* @brief Configure 48Mhz domain clock source
AnnaBridge	171:3a7713b1edbc	2537	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
AnnaBridge	171:3a7713b1edbc	2538	* @param CK48MxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2539	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2540	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2541	* @retval None
AnnaBridge	171:3a7713b1edbc	2542	*/
AnnaBridge	171:3a7713b1edbc	2543	__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
AnnaBridge	171:3a7713b1edbc	2544	{
AnnaBridge	171:3a7713b1edbc	2545	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
AnnaBridge	171:3a7713b1edbc	2546	}
AnnaBridge	171:3a7713b1edbc	2547
AnnaBridge	171:3a7713b1edbc	2548	/**
AnnaBridge	171:3a7713b1edbc	2549	* @brief Configure RNG clock source
AnnaBridge	171:3a7713b1edbc	2550	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
AnnaBridge	171:3a7713b1edbc	2551	* @param RNGxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2552	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2553	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2554	* @retval None
AnnaBridge	171:3a7713b1edbc	2555	*/
AnnaBridge	171:3a7713b1edbc	2556	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
AnnaBridge	171:3a7713b1edbc	2557	{
AnnaBridge	171:3a7713b1edbc	2558	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
AnnaBridge	171:3a7713b1edbc	2559	}
AnnaBridge	171:3a7713b1edbc	2560
AnnaBridge	171:3a7713b1edbc	2561	/**
AnnaBridge	171:3a7713b1edbc	2562	* @brief Configure USB clock source
AnnaBridge	171:3a7713b1edbc	2563	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
AnnaBridge	171:3a7713b1edbc	2564	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2565	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2566	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2567	* @retval None
AnnaBridge	171:3a7713b1edbc	2568	*/
AnnaBridge	171:3a7713b1edbc	2569	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
AnnaBridge	171:3a7713b1edbc	2570	{
AnnaBridge	171:3a7713b1edbc	2571	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
AnnaBridge	171:3a7713b1edbc	2572	}
AnnaBridge	171:3a7713b1edbc	2573
AnnaBridge	171:3a7713b1edbc	2574	#if defined(CEC)
AnnaBridge	171:3a7713b1edbc	2575	/**
AnnaBridge	171:3a7713b1edbc	2576	* @brief Configure CEC clock source
AnnaBridge	171:3a7713b1edbc	2577	* @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
AnnaBridge	171:3a7713b1edbc	2578	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2579	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2580	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
AnnaBridge	171:3a7713b1edbc	2581	* @retval None
AnnaBridge	171:3a7713b1edbc	2582	*/
AnnaBridge	171:3a7713b1edbc	2583	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	2584	{
AnnaBridge	171:3a7713b1edbc	2585	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
AnnaBridge	171:3a7713b1edbc	2586	}
AnnaBridge	171:3a7713b1edbc	2587	#endif /* CEC */
AnnaBridge	171:3a7713b1edbc	2588
AnnaBridge	171:3a7713b1edbc	2589	/**
AnnaBridge	171:3a7713b1edbc	2590	* @brief Configure I2S clock source
AnnaBridge	171:3a7713b1edbc	2591	* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
AnnaBridge	171:3a7713b1edbc	2592	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2593	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
AnnaBridge	171:3a7713b1edbc	2594	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
AnnaBridge	171:3a7713b1edbc	2595	* @retval None
AnnaBridge	171:3a7713b1edbc	2596	*/
AnnaBridge	171:3a7713b1edbc	2597	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	2598	{
AnnaBridge	171:3a7713b1edbc	2599	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
AnnaBridge	171:3a7713b1edbc	2600	}
AnnaBridge	171:3a7713b1edbc	2601
AnnaBridge	171:3a7713b1edbc	2602	#if defined(DSI)
AnnaBridge	171:3a7713b1edbc	2603	/**
AnnaBridge	171:3a7713b1edbc	2604	* @brief Configure DSI clock source
AnnaBridge	171:3a7713b1edbc	2605	* @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource
AnnaBridge	171:3a7713b1edbc	2606	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2607	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	171:3a7713b1edbc	2608	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2609	* @retval None
AnnaBridge	171:3a7713b1edbc	2610	*/
AnnaBridge	171:3a7713b1edbc	2611	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	2612	{
AnnaBridge	171:3a7713b1edbc	2613	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source);
AnnaBridge	171:3a7713b1edbc	2614	}
AnnaBridge	171:3a7713b1edbc	2615	#endif /* DSI */
AnnaBridge	171:3a7713b1edbc	2616
AnnaBridge	171:3a7713b1edbc	2617	#if defined(DFSDM1_Channel0)
AnnaBridge	171:3a7713b1edbc	2618	/**
AnnaBridge	171:3a7713b1edbc	2619	* @brief Configure DFSDM Audio clock source
AnnaBridge	171:3a7713b1edbc	2620	* @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
AnnaBridge	171:3a7713b1edbc	2621	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2622	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
AnnaBridge	171:3a7713b1edbc	2623	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
AnnaBridge	171:3a7713b1edbc	2624	* @retval None
AnnaBridge	171:3a7713b1edbc	2625	*/
AnnaBridge	171:3a7713b1edbc	2626	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	2627	{
AnnaBridge	171:3a7713b1edbc	2628	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source);
AnnaBridge	171:3a7713b1edbc	2629	}
AnnaBridge	171:3a7713b1edbc	2630
AnnaBridge	171:3a7713b1edbc	2631	/**
AnnaBridge	171:3a7713b1edbc	2632	* @brief Configure DFSDM Kernel clock source
AnnaBridge	171:3a7713b1edbc	2633	* @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	171:3a7713b1edbc	2634	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2635	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	171:3a7713b1edbc	2636	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2637	* @retval None
AnnaBridge	171:3a7713b1edbc	2638	*/
AnnaBridge	171:3a7713b1edbc	2639	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	2640	{
AnnaBridge	171:3a7713b1edbc	2641	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source);
AnnaBridge	171:3a7713b1edbc	2642	}
AnnaBridge	171:3a7713b1edbc	2643	#endif /* DFSDM1_Channel0 */
AnnaBridge	171:3a7713b1edbc	2644
AnnaBridge	171:3a7713b1edbc	2645	/**
AnnaBridge	171:3a7713b1edbc	2646	* @brief Get USARTx clock source
AnnaBridge	171:3a7713b1edbc	2647	* @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2648	* DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2649	* DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2650	* DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource
AnnaBridge	171:3a7713b1edbc	2651	* @param USARTx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2652	* @arg @ref LL_RCC_USART1_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2653	* @arg @ref LL_RCC_USART2_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2654	* @arg @ref LL_RCC_USART3_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2655	* @arg @ref LL_RCC_USART6_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2656	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2657	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
AnnaBridge	171:3a7713b1edbc	2658	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2659	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2660	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2661	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2662	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2663	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2664	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2665	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2666	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2667	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2668	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2669	* @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
AnnaBridge	171:3a7713b1edbc	2670	* @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2671	* @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2672	* @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2673	*/
AnnaBridge	171:3a7713b1edbc	2674	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
AnnaBridge	171:3a7713b1edbc	2675	{
AnnaBridge	171:3a7713b1edbc	2676	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) \| (USARTx << 16U));
AnnaBridge	171:3a7713b1edbc	2677	}
AnnaBridge	171:3a7713b1edbc	2678
AnnaBridge	171:3a7713b1edbc	2679	/**
AnnaBridge	171:3a7713b1edbc	2680	* @brief Get UARTx clock source
AnnaBridge	171:3a7713b1edbc	2681	* @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2682	* DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2683	* DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n
AnnaBridge	171:3a7713b1edbc	2684	* DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource
AnnaBridge	171:3a7713b1edbc	2685	* @param UARTx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2686	* @arg @ref LL_RCC_UART4_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2687	* @arg @ref LL_RCC_UART5_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2688	* @arg @ref LL_RCC_UART7_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2689	* @arg @ref LL_RCC_UART8_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2690	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2691	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2692	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2693	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2694	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2695	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2696	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2697	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2698	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2699	* @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2700	* @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2701	* @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2702	* @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2703	* @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2704	* @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2705	* @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2706	* @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2707	*/
AnnaBridge	171:3a7713b1edbc	2708	__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
AnnaBridge	171:3a7713b1edbc	2709	{
AnnaBridge	171:3a7713b1edbc	2710	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) \| (UARTx << 16U));
AnnaBridge	171:3a7713b1edbc	2711	}
AnnaBridge	171:3a7713b1edbc	2712
AnnaBridge	171:3a7713b1edbc	2713	/**
AnnaBridge	171:3a7713b1edbc	2714	* @brief Get I2Cx clock source
AnnaBridge	171:3a7713b1edbc	2715	* @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n
AnnaBridge	171:3a7713b1edbc	2716	* DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n
AnnaBridge	171:3a7713b1edbc	2717	* DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n
AnnaBridge	171:3a7713b1edbc	2718	* DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource
AnnaBridge	171:3a7713b1edbc	2719	* @param I2Cx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2720	* @arg @ref LL_RCC_I2C1_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2721	* @arg @ref LL_RCC_I2C2_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2722	* @arg @ref LL_RCC_I2C3_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2723	* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
AnnaBridge	171:3a7713b1edbc	2724	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2725	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2726	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2727	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2728	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2729	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2730	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2731	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2732	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2733	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2734	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	171:3a7713b1edbc	2735	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	171:3a7713b1edbc	2736	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
AnnaBridge	171:3a7713b1edbc	2737	*
AnnaBridge	171:3a7713b1edbc	2738	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	2739	*/
AnnaBridge	171:3a7713b1edbc	2740	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
AnnaBridge	171:3a7713b1edbc	2741	{
AnnaBridge	171:3a7713b1edbc	2742	return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) \| I2Cx);
AnnaBridge	171:3a7713b1edbc	2743	}
AnnaBridge	171:3a7713b1edbc	2744
AnnaBridge	171:3a7713b1edbc	2745	/**
AnnaBridge	171:3a7713b1edbc	2746	* @brief Get LPTIMx clock source
AnnaBridge	171:3a7713b1edbc	2747	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
AnnaBridge	171:3a7713b1edbc	2748	* @param LPTIMx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2749	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2750	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2751	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	171:3a7713b1edbc	2752	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	171:3a7713b1edbc	2753	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	2754	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2755	*/
AnnaBridge	171:3a7713b1edbc	2756	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
AnnaBridge	171:3a7713b1edbc	2757	{
AnnaBridge	171:3a7713b1edbc	2758	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
AnnaBridge	171:3a7713b1edbc	2759	}
AnnaBridge	171:3a7713b1edbc	2760
AnnaBridge	171:3a7713b1edbc	2761	/**
AnnaBridge	171:3a7713b1edbc	2762	* @brief Get SAIx clock source
AnnaBridge	171:3a7713b1edbc	2763	* @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n
AnnaBridge	171:3a7713b1edbc	2764	* DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource
AnnaBridge	171:3a7713b1edbc	2765	* @param SAIx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2766	* @arg @ref LL_RCC_SAI1_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2767	* @arg @ref LL_RCC_SAI2_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2768	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2769	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2770	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
AnnaBridge	171:3a7713b1edbc	2771	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
AnnaBridge	171:3a7713b1edbc	2772	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
AnnaBridge	171:3a7713b1edbc	2773	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2774	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
AnnaBridge	171:3a7713b1edbc	2775	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
AnnaBridge	171:3a7713b1edbc	2776	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
AnnaBridge	171:3a7713b1edbc	2777	*
AnnaBridge	171:3a7713b1edbc	2778	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	2779	*/
AnnaBridge	171:3a7713b1edbc	2780	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
AnnaBridge	171:3a7713b1edbc	2781	{
AnnaBridge	171:3a7713b1edbc	2782	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U \| SAIx);
AnnaBridge	171:3a7713b1edbc	2783	}
AnnaBridge	171:3a7713b1edbc	2784
AnnaBridge	171:3a7713b1edbc	2785	/**
AnnaBridge	171:3a7713b1edbc	2786	* @brief Get SDMMCx clock source
AnnaBridge	171:3a7713b1edbc	2787	* @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n
AnnaBridge	171:3a7713b1edbc	2788	* DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource
AnnaBridge	171:3a7713b1edbc	2789	* @param SDMMCx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2790	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2791	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
AnnaBridge	171:3a7713b1edbc	2792	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2793	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
AnnaBridge	171:3a7713b1edbc	2794	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2795	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
AnnaBridge	171:3a7713b1edbc	2796	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
AnnaBridge	171:3a7713b1edbc	2797	*
AnnaBridge	171:3a7713b1edbc	2798	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	2799	*/
AnnaBridge	171:3a7713b1edbc	2800	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
AnnaBridge	171:3a7713b1edbc	2801	{
AnnaBridge	171:3a7713b1edbc	2802	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U \| SDMMCx);
AnnaBridge	171:3a7713b1edbc	2803	}
AnnaBridge	171:3a7713b1edbc	2804
AnnaBridge	171:3a7713b1edbc	2805	/**
AnnaBridge	171:3a7713b1edbc	2806	* @brief Get 48Mhz domain clock source
AnnaBridge	171:3a7713b1edbc	2807	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
AnnaBridge	171:3a7713b1edbc	2808	* @param CK48Mx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2809	* @arg @ref LL_RCC_CK48M_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2810	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2811	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2812	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2813	*/
AnnaBridge	171:3a7713b1edbc	2814	__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
AnnaBridge	171:3a7713b1edbc	2815	{
AnnaBridge	171:3a7713b1edbc	2816	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
AnnaBridge	171:3a7713b1edbc	2817	}
AnnaBridge	171:3a7713b1edbc	2818
AnnaBridge	171:3a7713b1edbc	2819	/**
AnnaBridge	171:3a7713b1edbc	2820	* @brief Get RNGx clock source
AnnaBridge	171:3a7713b1edbc	2821	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
AnnaBridge	171:3a7713b1edbc	2822	* @param RNGx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2823	* @arg @ref LL_RCC_RNG_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2824	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2825	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2826	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2827	*/
AnnaBridge	171:3a7713b1edbc	2828	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
AnnaBridge	171:3a7713b1edbc	2829	{
AnnaBridge	171:3a7713b1edbc	2830	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
AnnaBridge	171:3a7713b1edbc	2831	}
AnnaBridge	171:3a7713b1edbc	2832
AnnaBridge	171:3a7713b1edbc	2833	/**
AnnaBridge	171:3a7713b1edbc	2834	* @brief Get USBx clock source
AnnaBridge	171:3a7713b1edbc	2835	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
AnnaBridge	171:3a7713b1edbc	2836	* @param USBx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2837	* @arg @ref LL_RCC_USB_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2838	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2839	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2840	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
AnnaBridge	171:3a7713b1edbc	2841	*/
AnnaBridge	171:3a7713b1edbc	2842	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
AnnaBridge	171:3a7713b1edbc	2843	{
AnnaBridge	171:3a7713b1edbc	2844	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
AnnaBridge	171:3a7713b1edbc	2845	}
AnnaBridge	171:3a7713b1edbc	2846
AnnaBridge	171:3a7713b1edbc	2847	#if defined(CEC)
AnnaBridge	171:3a7713b1edbc	2848	/**
AnnaBridge	171:3a7713b1edbc	2849	* @brief Get CEC Clock Source
AnnaBridge	171:3a7713b1edbc	2850	* @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
AnnaBridge	171:3a7713b1edbc	2851	* @param CECx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2852	* @arg @ref LL_RCC_CEC_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2853	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2854	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2855	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
AnnaBridge	171:3a7713b1edbc	2856	*/
AnnaBridge	171:3a7713b1edbc	2857	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
AnnaBridge	171:3a7713b1edbc	2858	{
AnnaBridge	171:3a7713b1edbc	2859	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
AnnaBridge	171:3a7713b1edbc	2860	}
AnnaBridge	171:3a7713b1edbc	2861	#endif /* CEC */
AnnaBridge	171:3a7713b1edbc	2862
AnnaBridge	171:3a7713b1edbc	2863	/**
AnnaBridge	171:3a7713b1edbc	2864	* @brief Get I2S Clock Source
AnnaBridge	171:3a7713b1edbc	2865	* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
AnnaBridge	171:3a7713b1edbc	2866	* @param I2Sx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2867	* @arg @ref LL_RCC_I2S1_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2868	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2869	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
AnnaBridge	171:3a7713b1edbc	2870	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
AnnaBridge	171:3a7713b1edbc	2871	*/
AnnaBridge	171:3a7713b1edbc	2872	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
AnnaBridge	171:3a7713b1edbc	2873	{
AnnaBridge	171:3a7713b1edbc	2874	return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
AnnaBridge	171:3a7713b1edbc	2875	}
AnnaBridge	171:3a7713b1edbc	2876
AnnaBridge	171:3a7713b1edbc	2877	#if defined(DFSDM1_Channel0)
AnnaBridge	171:3a7713b1edbc	2878	/**
AnnaBridge	171:3a7713b1edbc	2879	* @brief Get DFSDM Audio Clock Source
AnnaBridge	171:3a7713b1edbc	2880	* @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
AnnaBridge	171:3a7713b1edbc	2881	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2882	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2883	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2884	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
AnnaBridge	171:3a7713b1edbc	2885	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
AnnaBridge	171:3a7713b1edbc	2886	*/
AnnaBridge	171:3a7713b1edbc	2887	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
AnnaBridge	171:3a7713b1edbc	2888	{
AnnaBridge	171:3a7713b1edbc	2889	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
AnnaBridge	171:3a7713b1edbc	2890	}
AnnaBridge	171:3a7713b1edbc	2891
AnnaBridge	171:3a7713b1edbc	2892	/**
AnnaBridge	171:3a7713b1edbc	2893	* @brief Get DFSDM Audio Clock Source
AnnaBridge	171:3a7713b1edbc	2894	* @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	171:3a7713b1edbc	2895	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2896	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2897	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2898	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	171:3a7713b1edbc	2899	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	2900	*/
AnnaBridge	171:3a7713b1edbc	2901	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
AnnaBridge	171:3a7713b1edbc	2902	{
AnnaBridge	171:3a7713b1edbc	2903	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
AnnaBridge	171:3a7713b1edbc	2904	}
AnnaBridge	171:3a7713b1edbc	2905	#endif /* DFSDM1_Channel0 */
AnnaBridge	171:3a7713b1edbc	2906
AnnaBridge	171:3a7713b1edbc	2907	#if defined(DSI)
AnnaBridge	171:3a7713b1edbc	2908	/**
AnnaBridge	171:3a7713b1edbc	2909	* @brief Get DSI Clock Source
AnnaBridge	171:3a7713b1edbc	2910	* @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource
AnnaBridge	171:3a7713b1edbc	2911	* @param DSIx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2912	* @arg @ref LL_RCC_DSI_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	2913	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2914	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	171:3a7713b1edbc	2915	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	2916	*/
AnnaBridge	171:3a7713b1edbc	2917	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
AnnaBridge	171:3a7713b1edbc	2918	{
AnnaBridge	171:3a7713b1edbc	2919	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx));
AnnaBridge	171:3a7713b1edbc	2920	}
AnnaBridge	171:3a7713b1edbc	2921	#endif /* DSI */
AnnaBridge	171:3a7713b1edbc	2922
AnnaBridge	171:3a7713b1edbc	2923	/**
AnnaBridge	171:3a7713b1edbc	2924	* @}
AnnaBridge	171:3a7713b1edbc	2925	*/
AnnaBridge	171:3a7713b1edbc	2926
AnnaBridge	171:3a7713b1edbc	2927	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	171:3a7713b1edbc	2928	* @{
AnnaBridge	171:3a7713b1edbc	2929	*/
AnnaBridge	171:3a7713b1edbc	2930
AnnaBridge	171:3a7713b1edbc	2931	/**
AnnaBridge	171:3a7713b1edbc	2932	* @brief Set RTC Clock Source
AnnaBridge	171:3a7713b1edbc	2933	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
AnnaBridge	171:3a7713b1edbc	2934	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	171:3a7713b1edbc	2935	* set). The BDRST bit can be used to reset them.
AnnaBridge	171:3a7713b1edbc	2936	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	171:3a7713b1edbc	2937	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2938	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	171:3a7713b1edbc	2939	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2940	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	171:3a7713b1edbc	2941	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	2942	* @retval None
AnnaBridge	171:3a7713b1edbc	2943	*/
AnnaBridge	171:3a7713b1edbc	2944	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	2945	{
AnnaBridge	171:3a7713b1edbc	2946	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
AnnaBridge	171:3a7713b1edbc	2947	}
AnnaBridge	171:3a7713b1edbc	2948
AnnaBridge	171:3a7713b1edbc	2949	/**
AnnaBridge	171:3a7713b1edbc	2950	* @brief Get RTC Clock Source
AnnaBridge	171:3a7713b1edbc	2951	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	171:3a7713b1edbc	2952	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2953	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	171:3a7713b1edbc	2954	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	2955	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	171:3a7713b1edbc	2956	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	2957	*/
AnnaBridge	171:3a7713b1edbc	2958	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	171:3a7713b1edbc	2959	{
AnnaBridge	171:3a7713b1edbc	2960	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
AnnaBridge	171:3a7713b1edbc	2961	}
AnnaBridge	171:3a7713b1edbc	2962
AnnaBridge	171:3a7713b1edbc	2963	/**
AnnaBridge	171:3a7713b1edbc	2964	* @brief Enable RTC
AnnaBridge	171:3a7713b1edbc	2965	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
AnnaBridge	171:3a7713b1edbc	2966	* @retval None
AnnaBridge	171:3a7713b1edbc	2967	*/
AnnaBridge	171:3a7713b1edbc	2968	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	171:3a7713b1edbc	2969	{
AnnaBridge	171:3a7713b1edbc	2970	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	171:3a7713b1edbc	2971	}
AnnaBridge	171:3a7713b1edbc	2972
AnnaBridge	171:3a7713b1edbc	2973	/**
AnnaBridge	171:3a7713b1edbc	2974	* @brief Disable RTC
AnnaBridge	171:3a7713b1edbc	2975	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
AnnaBridge	171:3a7713b1edbc	2976	* @retval None
AnnaBridge	171:3a7713b1edbc	2977	*/
AnnaBridge	171:3a7713b1edbc	2978	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	171:3a7713b1edbc	2979	{
AnnaBridge	171:3a7713b1edbc	2980	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	171:3a7713b1edbc	2981	}
AnnaBridge	171:3a7713b1edbc	2982
AnnaBridge	171:3a7713b1edbc	2983	/**
AnnaBridge	171:3a7713b1edbc	2984	* @brief Check if RTC has been enabled or not
AnnaBridge	171:3a7713b1edbc	2985	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	171:3a7713b1edbc	2986	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2987	*/
AnnaBridge	171:3a7713b1edbc	2988	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	171:3a7713b1edbc	2989	{
AnnaBridge	171:3a7713b1edbc	2990	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
AnnaBridge	171:3a7713b1edbc	2991	}
AnnaBridge	171:3a7713b1edbc	2992
AnnaBridge	171:3a7713b1edbc	2993	/**
AnnaBridge	171:3a7713b1edbc	2994	* @brief Force the Backup domain reset
AnnaBridge	171:3a7713b1edbc	2995	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
AnnaBridge	171:3a7713b1edbc	2996	* @retval None
AnnaBridge	171:3a7713b1edbc	2997	*/
AnnaBridge	171:3a7713b1edbc	2998	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	171:3a7713b1edbc	2999	{
AnnaBridge	171:3a7713b1edbc	3000	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	171:3a7713b1edbc	3001	}
AnnaBridge	171:3a7713b1edbc	3002
AnnaBridge	171:3a7713b1edbc	3003	/**
AnnaBridge	171:3a7713b1edbc	3004	* @brief Release the Backup domain reset
AnnaBridge	171:3a7713b1edbc	3005	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	171:3a7713b1edbc	3006	* @retval None
AnnaBridge	171:3a7713b1edbc	3007	*/
AnnaBridge	171:3a7713b1edbc	3008	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	171:3a7713b1edbc	3009	{
AnnaBridge	171:3a7713b1edbc	3010	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	171:3a7713b1edbc	3011	}
AnnaBridge	171:3a7713b1edbc	3012
AnnaBridge	171:3a7713b1edbc	3013	/**
AnnaBridge	171:3a7713b1edbc	3014	* @brief Set HSE Prescalers for RTC Clock
AnnaBridge	171:3a7713b1edbc	3015	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
AnnaBridge	171:3a7713b1edbc	3016	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3017	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	171:3a7713b1edbc	3018	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	171:3a7713b1edbc	3019	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	171:3a7713b1edbc	3020	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	171:3a7713b1edbc	3021	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	171:3a7713b1edbc	3022	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	171:3a7713b1edbc	3023	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	171:3a7713b1edbc	3024	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	171:3a7713b1edbc	3025	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	171:3a7713b1edbc	3026	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	171:3a7713b1edbc	3027	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	171:3a7713b1edbc	3028	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	171:3a7713b1edbc	3029	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	171:3a7713b1edbc	3030	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	171:3a7713b1edbc	3031	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	171:3a7713b1edbc	3032	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	171:3a7713b1edbc	3033	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	171:3a7713b1edbc	3034	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	171:3a7713b1edbc	3035	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	171:3a7713b1edbc	3036	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	171:3a7713b1edbc	3037	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	171:3a7713b1edbc	3038	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	171:3a7713b1edbc	3039	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	171:3a7713b1edbc	3040	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	171:3a7713b1edbc	3041	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	171:3a7713b1edbc	3042	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	171:3a7713b1edbc	3043	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	171:3a7713b1edbc	3044	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	171:3a7713b1edbc	3045	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	171:3a7713b1edbc	3046	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	171:3a7713b1edbc	3047	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	171:3a7713b1edbc	3048	* @retval None
AnnaBridge	171:3a7713b1edbc	3049	*/
AnnaBridge	171:3a7713b1edbc	3050	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	3051	{
AnnaBridge	171:3a7713b1edbc	3052	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
AnnaBridge	171:3a7713b1edbc	3053	}
AnnaBridge	171:3a7713b1edbc	3054
AnnaBridge	171:3a7713b1edbc	3055	/**
AnnaBridge	171:3a7713b1edbc	3056	* @brief Get HSE Prescalers for RTC Clock
AnnaBridge	171:3a7713b1edbc	3057	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
AnnaBridge	171:3a7713b1edbc	3058	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3059	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	171:3a7713b1edbc	3060	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	171:3a7713b1edbc	3061	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	171:3a7713b1edbc	3062	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	171:3a7713b1edbc	3063	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	171:3a7713b1edbc	3064	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	171:3a7713b1edbc	3065	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	171:3a7713b1edbc	3066	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	171:3a7713b1edbc	3067	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	171:3a7713b1edbc	3068	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	171:3a7713b1edbc	3069	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	171:3a7713b1edbc	3070	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	171:3a7713b1edbc	3071	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	171:3a7713b1edbc	3072	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	171:3a7713b1edbc	3073	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	171:3a7713b1edbc	3074	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	171:3a7713b1edbc	3075	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	171:3a7713b1edbc	3076	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	171:3a7713b1edbc	3077	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	171:3a7713b1edbc	3078	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	171:3a7713b1edbc	3079	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	171:3a7713b1edbc	3080	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	171:3a7713b1edbc	3081	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	171:3a7713b1edbc	3082	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	171:3a7713b1edbc	3083	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	171:3a7713b1edbc	3084	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	171:3a7713b1edbc	3085	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	171:3a7713b1edbc	3086	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	171:3a7713b1edbc	3087	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	171:3a7713b1edbc	3088	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	171:3a7713b1edbc	3089	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	171:3a7713b1edbc	3090	*/
AnnaBridge	171:3a7713b1edbc	3091	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
AnnaBridge	171:3a7713b1edbc	3092	{
AnnaBridge	171:3a7713b1edbc	3093	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
AnnaBridge	171:3a7713b1edbc	3094	}
AnnaBridge	171:3a7713b1edbc	3095
AnnaBridge	171:3a7713b1edbc	3096	/**
AnnaBridge	171:3a7713b1edbc	3097	* @}
AnnaBridge	171:3a7713b1edbc	3098	*/
AnnaBridge	171:3a7713b1edbc	3099
AnnaBridge	171:3a7713b1edbc	3100	/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
AnnaBridge	171:3a7713b1edbc	3101	* @{
AnnaBridge	171:3a7713b1edbc	3102	*/
AnnaBridge	171:3a7713b1edbc	3103
AnnaBridge	171:3a7713b1edbc	3104	/**
AnnaBridge	171:3a7713b1edbc	3105	* @brief Set Timers Clock Prescalers
AnnaBridge	171:3a7713b1edbc	3106	* @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler
AnnaBridge	171:3a7713b1edbc	3107	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3108	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
AnnaBridge	171:3a7713b1edbc	3109	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
AnnaBridge	171:3a7713b1edbc	3110	* @retval None
AnnaBridge	171:3a7713b1edbc	3111	*/
AnnaBridge	171:3a7713b1edbc	3112	__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	3113	{
AnnaBridge	171:3a7713b1edbc	3114	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler);
AnnaBridge	171:3a7713b1edbc	3115	}
AnnaBridge	171:3a7713b1edbc	3116
AnnaBridge	171:3a7713b1edbc	3117	/**
AnnaBridge	171:3a7713b1edbc	3118	* @brief Get Timers Clock Prescalers
AnnaBridge	171:3a7713b1edbc	3119	* @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler
AnnaBridge	171:3a7713b1edbc	3120	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3121	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
AnnaBridge	171:3a7713b1edbc	3122	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
AnnaBridge	171:3a7713b1edbc	3123	*/
AnnaBridge	171:3a7713b1edbc	3124	__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
AnnaBridge	171:3a7713b1edbc	3125	{
AnnaBridge	171:3a7713b1edbc	3126	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE));
AnnaBridge	171:3a7713b1edbc	3127	}
AnnaBridge	171:3a7713b1edbc	3128
AnnaBridge	171:3a7713b1edbc	3129	/**
AnnaBridge	171:3a7713b1edbc	3130	* @}
AnnaBridge	171:3a7713b1edbc	3131	*/
AnnaBridge	171:3a7713b1edbc	3132
AnnaBridge	171:3a7713b1edbc	3133	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	171:3a7713b1edbc	3134	* @{
AnnaBridge	171:3a7713b1edbc	3135	*/
AnnaBridge	171:3a7713b1edbc	3136
AnnaBridge	171:3a7713b1edbc	3137	/**
AnnaBridge	171:3a7713b1edbc	3138	* @brief Enable PLL
AnnaBridge	171:3a7713b1edbc	3139	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	171:3a7713b1edbc	3140	* @retval None
AnnaBridge	171:3a7713b1edbc	3141	*/
AnnaBridge	171:3a7713b1edbc	3142	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	171:3a7713b1edbc	3143	{
AnnaBridge	171:3a7713b1edbc	3144	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	171:3a7713b1edbc	3145	}
AnnaBridge	171:3a7713b1edbc	3146
AnnaBridge	171:3a7713b1edbc	3147	/**
AnnaBridge	171:3a7713b1edbc	3148	* @brief Disable PLL
AnnaBridge	171:3a7713b1edbc	3149	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	171:3a7713b1edbc	3150	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	171:3a7713b1edbc	3151	* @retval None
AnnaBridge	171:3a7713b1edbc	3152	*/
AnnaBridge	171:3a7713b1edbc	3153	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	171:3a7713b1edbc	3154	{
AnnaBridge	171:3a7713b1edbc	3155	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	171:3a7713b1edbc	3156	}
AnnaBridge	171:3a7713b1edbc	3157
AnnaBridge	171:3a7713b1edbc	3158	/**
AnnaBridge	171:3a7713b1edbc	3159	* @brief Check if PLL Ready
AnnaBridge	171:3a7713b1edbc	3160	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	171:3a7713b1edbc	3161	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3162	*/
AnnaBridge	171:3a7713b1edbc	3163	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	171:3a7713b1edbc	3164	{
AnnaBridge	171:3a7713b1edbc	3165	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	171:3a7713b1edbc	3166	}
AnnaBridge	171:3a7713b1edbc	3167
AnnaBridge	171:3a7713b1edbc	3168	/**
AnnaBridge	171:3a7713b1edbc	3169	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	171:3a7713b1edbc	3170	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	3171	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	3172	* @note PLLN/PLLP can be written only when PLL is disabled
AnnaBridge	171:3a7713b1edbc	3173	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	3174	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	3175	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	3176	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	171:3a7713b1edbc	3177	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3178	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	3179	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	3180	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3181	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	3182	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	3183	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	3184	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	3185	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	3186	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	3187	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	3188	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	3189	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	3190	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	3191	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	3192	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	3193	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	3194	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	3195	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	3196	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	3197	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	3198	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	3199	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	3200	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	3201	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	3202	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	3203	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	3204	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	3205	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	3206	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	3207	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	3208	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	3209	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	3210	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	3211	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	3212	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	3213	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	3214	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	3215	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	3216	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	3217	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	3218	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	3219	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	3220	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	3221	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	3222	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	3223	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	3224	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	3225	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	3226	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	3227	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	3228	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	3229	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	3230	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	3231	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	3232	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	3233	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	3234	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	3235	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	3236	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	3237	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	3238	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	3239	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	3240	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	3241	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	3242	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	3243	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	3244	* @param PLLP This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3245	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	171:3a7713b1edbc	3246	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	171:3a7713b1edbc	3247	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	171:3a7713b1edbc	3248	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	171:3a7713b1edbc	3249	* @retval None
AnnaBridge	171:3a7713b1edbc	3250	*/
AnnaBridge	171:3a7713b1edbc	3251	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	171:3a7713b1edbc	3252	{
AnnaBridge	171:3a7713b1edbc	3253	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
AnnaBridge	171:3a7713b1edbc	3254	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
AnnaBridge	171:3a7713b1edbc	3255	}
AnnaBridge	171:3a7713b1edbc	3256
AnnaBridge	171:3a7713b1edbc	3257	/**
AnnaBridge	171:3a7713b1edbc	3258	* @brief Configure PLL used for 48Mhz domain clock
AnnaBridge	171:3a7713b1edbc	3259	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	3260	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	3261	* @note PLLN/PLLQ can be written only when PLL is disabled
AnnaBridge	171:3a7713b1edbc	3262	* @note This can be selected for USB, RNG, SDMMC1
AnnaBridge	171:3a7713b1edbc	3263	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	171:3a7713b1edbc	3264	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	171:3a7713b1edbc	3265	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	171:3a7713b1edbc	3266	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
AnnaBridge	171:3a7713b1edbc	3267	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3268	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	3269	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	3270	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3271	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	3272	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	3273	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	3274	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	3275	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	3276	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	3277	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	3278	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	3279	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	3280	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	3281	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	3282	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	3283	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	3284	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	3285	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	3286	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	3287	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	3288	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	3289	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	3290	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	3291	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	3292	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	3293	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	3294	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	3295	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	3296	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	3297	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	3298	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	3299	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	3300	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	3301	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	3302	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	3303	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	3304	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	3305	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	3306	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	3307	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	3308	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	3309	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	3310	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	3311	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	3312	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	3313	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	3314	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	3315	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	3316	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	3317	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	3318	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	3319	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	3320	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	3321	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	3322	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	3323	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	3324	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	3325	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	3326	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	3327	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	3328	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	3329	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	3330	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	3331	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	3332	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	3333	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	3334	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3335	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	171:3a7713b1edbc	3336	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	171:3a7713b1edbc	3337	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	171:3a7713b1edbc	3338	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	171:3a7713b1edbc	3339	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	171:3a7713b1edbc	3340	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	171:3a7713b1edbc	3341	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	171:3a7713b1edbc	3342	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	171:3a7713b1edbc	3343	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	171:3a7713b1edbc	3344	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	171:3a7713b1edbc	3345	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	171:3a7713b1edbc	3346	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	171:3a7713b1edbc	3347	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	171:3a7713b1edbc	3348	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	171:3a7713b1edbc	3349	* @retval None
AnnaBridge	171:3a7713b1edbc	3350	*/
AnnaBridge	171:3a7713b1edbc	3351	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	171:3a7713b1edbc	3352	{
AnnaBridge	171:3a7713b1edbc	3353	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
AnnaBridge	171:3a7713b1edbc	3354	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
AnnaBridge	171:3a7713b1edbc	3355	}
AnnaBridge	171:3a7713b1edbc	3356
AnnaBridge	171:3a7713b1edbc	3357	#if defined(DSI)
AnnaBridge	171:3a7713b1edbc	3358	/**
AnnaBridge	171:3a7713b1edbc	3359	* @brief Configure PLL used for DSI clock
AnnaBridge	171:3a7713b1edbc	3360	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	3361	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	3362	* @note PLLN/PLLR can be written only when PLL is disabled
AnnaBridge	171:3a7713b1edbc	3363	* @note This can be selected for DSI
AnnaBridge	171:3a7713b1edbc	3364	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
AnnaBridge	171:3a7713b1edbc	3365	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
AnnaBridge	171:3a7713b1edbc	3366	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
AnnaBridge	171:3a7713b1edbc	3367	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
AnnaBridge	171:3a7713b1edbc	3368	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3369	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	3370	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	3371	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3372	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	3373	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	3374	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	3375	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	3376	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	3377	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	3378	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	3379	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	3380	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	3381	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	3382	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	3383	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	3384	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	3385	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	3386	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	3387	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	3388	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	3389	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	3390	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	3391	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	3392	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	3393	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	3394	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	3395	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	3396	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	3397	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	3398	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	3399	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	3400	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	3401	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	3402	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	3403	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	3404	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	3405	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	3406	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	3407	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	3408	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	3409	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	3410	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	3411	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	3412	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	3413	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	3414	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	3415	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	3416	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	3417	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	3418	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	3419	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	3420	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	3421	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	3422	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	3423	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	3424	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	3425	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	3426	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	3427	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	3428	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	3429	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	3430	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	3431	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	3432	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	3433	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	3434	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	3435	* @param PLLR This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3436	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	171:3a7713b1edbc	3437	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	171:3a7713b1edbc	3438	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	171:3a7713b1edbc	3439	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	171:3a7713b1edbc	3440	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	171:3a7713b1edbc	3441	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	171:3a7713b1edbc	3442	* @retval None
AnnaBridge	171:3a7713b1edbc	3443	*/
AnnaBridge	171:3a7713b1edbc	3444	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	171:3a7713b1edbc	3445	{
AnnaBridge	171:3a7713b1edbc	3446	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	171:3a7713b1edbc	3447	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
AnnaBridge	171:3a7713b1edbc	3448	}
AnnaBridge	171:3a7713b1edbc	3449	#endif /* DSI */
AnnaBridge	171:3a7713b1edbc	3450
AnnaBridge	171:3a7713b1edbc	3451	/**
AnnaBridge	171:3a7713b1edbc	3452	* @brief Configure PLL clock source
AnnaBridge	171:3a7713b1edbc	3453	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
AnnaBridge	171:3a7713b1edbc	3454	* @param PLLSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3455	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	3456	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	3457	* @retval None
AnnaBridge	171:3a7713b1edbc	3458	*/
AnnaBridge	171:3a7713b1edbc	3459	__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
AnnaBridge	171:3a7713b1edbc	3460	{
AnnaBridge	171:3a7713b1edbc	3461	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
AnnaBridge	171:3a7713b1edbc	3462	}
AnnaBridge	171:3a7713b1edbc	3463
AnnaBridge	171:3a7713b1edbc	3464	/**
AnnaBridge	171:3a7713b1edbc	3465	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	171:3a7713b1edbc	3466	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	171:3a7713b1edbc	3467	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3468	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	3469	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	3470	*/
AnnaBridge	171:3a7713b1edbc	3471	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	171:3a7713b1edbc	3472	{
AnnaBridge	171:3a7713b1edbc	3473	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
AnnaBridge	171:3a7713b1edbc	3474	}
AnnaBridge	171:3a7713b1edbc	3475
AnnaBridge	171:3a7713b1edbc	3476	/**
AnnaBridge	171:3a7713b1edbc	3477	* @brief Get Main PLL multiplication factor for VCO
AnnaBridge	171:3a7713b1edbc	3478	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
AnnaBridge	171:3a7713b1edbc	3479	* @retval Between 50 and 432
AnnaBridge	171:3a7713b1edbc	3480	*/
AnnaBridge	171:3a7713b1edbc	3481	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
AnnaBridge	171:3a7713b1edbc	3482	{
AnnaBridge	171:3a7713b1edbc	3483	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
AnnaBridge	171:3a7713b1edbc	3484	}
AnnaBridge	171:3a7713b1edbc	3485
AnnaBridge	171:3a7713b1edbc	3486	/**
AnnaBridge	171:3a7713b1edbc	3487	* @brief Get Main PLL division factor for PLLP
AnnaBridge	171:3a7713b1edbc	3488	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
AnnaBridge	171:3a7713b1edbc	3489	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3490	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	171:3a7713b1edbc	3491	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	171:3a7713b1edbc	3492	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	171:3a7713b1edbc	3493	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	171:3a7713b1edbc	3494	*/
AnnaBridge	171:3a7713b1edbc	3495	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
AnnaBridge	171:3a7713b1edbc	3496	{
AnnaBridge	171:3a7713b1edbc	3497	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
AnnaBridge	171:3a7713b1edbc	3498	}
AnnaBridge	171:3a7713b1edbc	3499
AnnaBridge	171:3a7713b1edbc	3500	/**
AnnaBridge	171:3a7713b1edbc	3501	* @brief Get Main PLL division factor for PLLQ
AnnaBridge	171:3a7713b1edbc	3502	* @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock)
AnnaBridge	171:3a7713b1edbc	3503	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
AnnaBridge	171:3a7713b1edbc	3504	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3505	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	171:3a7713b1edbc	3506	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	171:3a7713b1edbc	3507	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	171:3a7713b1edbc	3508	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	171:3a7713b1edbc	3509	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	171:3a7713b1edbc	3510	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	171:3a7713b1edbc	3511	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	171:3a7713b1edbc	3512	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	171:3a7713b1edbc	3513	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	171:3a7713b1edbc	3514	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	171:3a7713b1edbc	3515	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	171:3a7713b1edbc	3516	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	171:3a7713b1edbc	3517	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	171:3a7713b1edbc	3518	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	171:3a7713b1edbc	3519	*/
AnnaBridge	171:3a7713b1edbc	3520	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
AnnaBridge	171:3a7713b1edbc	3521	{
AnnaBridge	171:3a7713b1edbc	3522	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
AnnaBridge	171:3a7713b1edbc	3523	}
AnnaBridge	171:3a7713b1edbc	3524
AnnaBridge	171:3a7713b1edbc	3525	#if defined(RCC_PLLCFGR_PLLR)
AnnaBridge	171:3a7713b1edbc	3526	/**
AnnaBridge	171:3a7713b1edbc	3527	* @brief Get Main PLL division factor for PLLR
AnnaBridge	171:3a7713b1edbc	3528	* @note used for PLLCLK (system clock)
AnnaBridge	171:3a7713b1edbc	3529	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
AnnaBridge	171:3a7713b1edbc	3530	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3531	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	171:3a7713b1edbc	3532	* @arg @ref LL_RCC_PLLR_DIV_3
AnnaBridge	171:3a7713b1edbc	3533	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	171:3a7713b1edbc	3534	* @arg @ref LL_RCC_PLLR_DIV_5
AnnaBridge	171:3a7713b1edbc	3535	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	171:3a7713b1edbc	3536	* @arg @ref LL_RCC_PLLR_DIV_7
AnnaBridge	171:3a7713b1edbc	3537	*/
AnnaBridge	171:3a7713b1edbc	3538	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
AnnaBridge	171:3a7713b1edbc	3539	{
AnnaBridge	171:3a7713b1edbc	3540	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
AnnaBridge	171:3a7713b1edbc	3541	}
AnnaBridge	171:3a7713b1edbc	3542	#endif /* RCC_PLLCFGR_PLLR */
AnnaBridge	171:3a7713b1edbc	3543
AnnaBridge	171:3a7713b1edbc	3544	/**
AnnaBridge	171:3a7713b1edbc	3545	* @brief Get Division factor for the main PLL and other PLL
AnnaBridge	171:3a7713b1edbc	3546	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
AnnaBridge	171:3a7713b1edbc	3547	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3548	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	3549	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	3550	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	3551	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	3552	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	3553	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	3554	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	3555	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	3556	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	3557	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	3558	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	3559	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	3560	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	3561	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	3562	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	3563	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	3564	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	3565	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	3566	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	3567	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	3568	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	3569	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	3570	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	3571	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	3572	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	3573	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	3574	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	3575	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	3576	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	3577	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	3578	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	3579	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	3580	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	3581	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	3582	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	3583	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	3584	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	3585	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	3586	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	3587	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	3588	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	3589	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	3590	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	3591	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	3592	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	3593	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	3594	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	3595	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	3596	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	3597	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	3598	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	3599	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	3600	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	3601	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	3602	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	3603	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	3604	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	3605	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	3606	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	3607	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	3608	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	3609	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	3610	*/
AnnaBridge	171:3a7713b1edbc	3611	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
AnnaBridge	171:3a7713b1edbc	3612	{
AnnaBridge	171:3a7713b1edbc	3613	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
AnnaBridge	171:3a7713b1edbc	3614	}
AnnaBridge	171:3a7713b1edbc	3615
AnnaBridge	171:3a7713b1edbc	3616	/**
AnnaBridge	171:3a7713b1edbc	3617	* @brief Configure Spread Spectrum used for PLL
AnnaBridge	171:3a7713b1edbc	3618	* @note These bits must be written before enabling PLL
AnnaBridge	171:3a7713b1edbc	3619	* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
AnnaBridge	171:3a7713b1edbc	3620	* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
AnnaBridge	171:3a7713b1edbc	3621	* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
AnnaBridge	171:3a7713b1edbc	3622	* @param Mod Between Min_Data=0 and Max_Data=8191
AnnaBridge	171:3a7713b1edbc	3623	* @param Inc Between Min_Data=0 and Max_Data=32767
AnnaBridge	171:3a7713b1edbc	3624	* @param Sel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3625	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
AnnaBridge	171:3a7713b1edbc	3626	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
AnnaBridge	171:3a7713b1edbc	3627	* @retval None
AnnaBridge	171:3a7713b1edbc	3628	*/
AnnaBridge	171:3a7713b1edbc	3629	__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
AnnaBridge	171:3a7713b1edbc	3630	{
AnnaBridge	171:3a7713b1edbc	3631	MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER \| RCC_SSCGR_INCSTEP \| RCC_SSCGR_SPREADSEL, Mod \| (Inc << RCC_SSCGR_INCSTEP_Pos) \| Sel);
AnnaBridge	171:3a7713b1edbc	3632	}
AnnaBridge	171:3a7713b1edbc	3633
AnnaBridge	171:3a7713b1edbc	3634	/**
AnnaBridge	171:3a7713b1edbc	3635	* @brief Get Spread Spectrum Modulation Period for PLL
AnnaBridge	171:3a7713b1edbc	3636	* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
AnnaBridge	171:3a7713b1edbc	3637	* @retval Between Min_Data=0 and Max_Data=8191
AnnaBridge	171:3a7713b1edbc	3638	*/
AnnaBridge	171:3a7713b1edbc	3639	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
AnnaBridge	171:3a7713b1edbc	3640	{
AnnaBridge	171:3a7713b1edbc	3641	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
AnnaBridge	171:3a7713b1edbc	3642	}
AnnaBridge	171:3a7713b1edbc	3643
AnnaBridge	171:3a7713b1edbc	3644	/**
AnnaBridge	171:3a7713b1edbc	3645	* @brief Get Spread Spectrum Incrementation Step for PLL
AnnaBridge	171:3a7713b1edbc	3646	* @note Must be written before enabling PLL
AnnaBridge	171:3a7713b1edbc	3647	* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
AnnaBridge	171:3a7713b1edbc	3648	* @retval Between Min_Data=0 and Max_Data=32767
AnnaBridge	171:3a7713b1edbc	3649	*/
AnnaBridge	171:3a7713b1edbc	3650	__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
AnnaBridge	171:3a7713b1edbc	3651	{
AnnaBridge	171:3a7713b1edbc	3652	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
AnnaBridge	171:3a7713b1edbc	3653	}
AnnaBridge	171:3a7713b1edbc	3654
AnnaBridge	171:3a7713b1edbc	3655	/**
AnnaBridge	171:3a7713b1edbc	3656	* @brief Get Spread Spectrum Selection for PLL
AnnaBridge	171:3a7713b1edbc	3657	* @note Must be written before enabling PLL
AnnaBridge	171:3a7713b1edbc	3658	* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
AnnaBridge	171:3a7713b1edbc	3659	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3660	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
AnnaBridge	171:3a7713b1edbc	3661	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
AnnaBridge	171:3a7713b1edbc	3662	*/
AnnaBridge	171:3a7713b1edbc	3663	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
AnnaBridge	171:3a7713b1edbc	3664	{
AnnaBridge	171:3a7713b1edbc	3665	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
AnnaBridge	171:3a7713b1edbc	3666	}
AnnaBridge	171:3a7713b1edbc	3667
AnnaBridge	171:3a7713b1edbc	3668	/**
AnnaBridge	171:3a7713b1edbc	3669	* @brief Enable Spread Spectrum for PLL.
AnnaBridge	171:3a7713b1edbc	3670	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
AnnaBridge	171:3a7713b1edbc	3671	* @retval None
AnnaBridge	171:3a7713b1edbc	3672	*/
AnnaBridge	171:3a7713b1edbc	3673	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
AnnaBridge	171:3a7713b1edbc	3674	{
AnnaBridge	171:3a7713b1edbc	3675	SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
AnnaBridge	171:3a7713b1edbc	3676	}
AnnaBridge	171:3a7713b1edbc	3677
AnnaBridge	171:3a7713b1edbc	3678	/**
AnnaBridge	171:3a7713b1edbc	3679	* @brief Disable Spread Spectrum for PLL.
AnnaBridge	171:3a7713b1edbc	3680	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
AnnaBridge	171:3a7713b1edbc	3681	* @retval None
AnnaBridge	171:3a7713b1edbc	3682	*/
AnnaBridge	171:3a7713b1edbc	3683	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
AnnaBridge	171:3a7713b1edbc	3684	{
AnnaBridge	171:3a7713b1edbc	3685	CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
AnnaBridge	171:3a7713b1edbc	3686	}
AnnaBridge	171:3a7713b1edbc	3687
AnnaBridge	171:3a7713b1edbc	3688	/**
AnnaBridge	171:3a7713b1edbc	3689	* @}
AnnaBridge	171:3a7713b1edbc	3690	*/
AnnaBridge	171:3a7713b1edbc	3691
AnnaBridge	171:3a7713b1edbc	3692	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
AnnaBridge	171:3a7713b1edbc	3693	* @{
AnnaBridge	171:3a7713b1edbc	3694	*/
AnnaBridge	171:3a7713b1edbc	3695
AnnaBridge	171:3a7713b1edbc	3696	/**
AnnaBridge	171:3a7713b1edbc	3697	* @brief Enable PLLI2S
AnnaBridge	171:3a7713b1edbc	3698	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
AnnaBridge	171:3a7713b1edbc	3699	* @retval None
AnnaBridge	171:3a7713b1edbc	3700	*/
AnnaBridge	171:3a7713b1edbc	3701	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
AnnaBridge	171:3a7713b1edbc	3702	{
AnnaBridge	171:3a7713b1edbc	3703	SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
AnnaBridge	171:3a7713b1edbc	3704	}
AnnaBridge	171:3a7713b1edbc	3705
AnnaBridge	171:3a7713b1edbc	3706	/**
AnnaBridge	171:3a7713b1edbc	3707	* @brief Disable PLLI2S
AnnaBridge	171:3a7713b1edbc	3708	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
AnnaBridge	171:3a7713b1edbc	3709	* @retval None
AnnaBridge	171:3a7713b1edbc	3710	*/
AnnaBridge	171:3a7713b1edbc	3711	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
AnnaBridge	171:3a7713b1edbc	3712	{
AnnaBridge	171:3a7713b1edbc	3713	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
AnnaBridge	171:3a7713b1edbc	3714	}
AnnaBridge	171:3a7713b1edbc	3715
AnnaBridge	171:3a7713b1edbc	3716	/**
AnnaBridge	171:3a7713b1edbc	3717	* @brief Check if PLLI2S Ready
AnnaBridge	171:3a7713b1edbc	3718	* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
AnnaBridge	171:3a7713b1edbc	3719	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3720	*/
AnnaBridge	171:3a7713b1edbc	3721	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
AnnaBridge	171:3a7713b1edbc	3722	{
AnnaBridge	171:3a7713b1edbc	3723	return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
AnnaBridge	171:3a7713b1edbc	3724	}
AnnaBridge	171:3a7713b1edbc	3725
AnnaBridge	171:3a7713b1edbc	3726	/**
AnnaBridge	171:3a7713b1edbc	3727	* @brief Configure PLLI2S used for SAI1 and SAI2 domain clock
AnnaBridge	171:3a7713b1edbc	3728	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	3729	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	3730	* @note PLLN/PLLQ can be written only when PLLI2S is disabled
AnnaBridge	171:3a7713b1edbc	3731	* @note This can be selected for SAI1 and SAI2
AnnaBridge	171:3a7713b1edbc	3732	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	171:3a7713b1edbc	3733	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	171:3a7713b1edbc	3734	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	171:3a7713b1edbc	3735	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
AnnaBridge	171:3a7713b1edbc	3736	* DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI
AnnaBridge	171:3a7713b1edbc	3737	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3738	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	3739	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	3740	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3741	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	3742	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	3743	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	3744	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	3745	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	3746	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	3747	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	3748	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	3749	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	3750	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	3751	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	3752	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	3753	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	3754	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	3755	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	3756	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	3757	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	3758	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	3759	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	3760	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	3761	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	3762	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	3763	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	3764	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	3765	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	3766	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	3767	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	3768	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	3769	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	3770	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	3771	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	3772	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	3773	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	3774	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	3775	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	3776	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	3777	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	3778	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	3779	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	3780	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	3781	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	3782	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	3783	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	3784	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	3785	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	3786	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	3787	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	3788	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	3789	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	3790	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	3791	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	3792	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	3793	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	3794	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	3795	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	3796	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	3797	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	3798	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	3799	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	3800	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	3801	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	3802	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	3803	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	3804	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3805	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
AnnaBridge	171:3a7713b1edbc	3806	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
AnnaBridge	171:3a7713b1edbc	3807	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
AnnaBridge	171:3a7713b1edbc	3808	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
AnnaBridge	171:3a7713b1edbc	3809	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
AnnaBridge	171:3a7713b1edbc	3810	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
AnnaBridge	171:3a7713b1edbc	3811	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
AnnaBridge	171:3a7713b1edbc	3812	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
AnnaBridge	171:3a7713b1edbc	3813	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
AnnaBridge	171:3a7713b1edbc	3814	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
AnnaBridge	171:3a7713b1edbc	3815	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
AnnaBridge	171:3a7713b1edbc	3816	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
AnnaBridge	171:3a7713b1edbc	3817	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
AnnaBridge	171:3a7713b1edbc	3818	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
AnnaBridge	171:3a7713b1edbc	3819	* @param PLLDIVQ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3820	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
AnnaBridge	171:3a7713b1edbc	3821	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
AnnaBridge	171:3a7713b1edbc	3822	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
AnnaBridge	171:3a7713b1edbc	3823	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
AnnaBridge	171:3a7713b1edbc	3824	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
AnnaBridge	171:3a7713b1edbc	3825	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
AnnaBridge	171:3a7713b1edbc	3826	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
AnnaBridge	171:3a7713b1edbc	3827	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
AnnaBridge	171:3a7713b1edbc	3828	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
AnnaBridge	171:3a7713b1edbc	3829	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
AnnaBridge	171:3a7713b1edbc	3830	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
AnnaBridge	171:3a7713b1edbc	3831	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
AnnaBridge	171:3a7713b1edbc	3832	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
AnnaBridge	171:3a7713b1edbc	3833	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
AnnaBridge	171:3a7713b1edbc	3834	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
AnnaBridge	171:3a7713b1edbc	3835	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
AnnaBridge	171:3a7713b1edbc	3836	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
AnnaBridge	171:3a7713b1edbc	3837	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
AnnaBridge	171:3a7713b1edbc	3838	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
AnnaBridge	171:3a7713b1edbc	3839	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
AnnaBridge	171:3a7713b1edbc	3840	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
AnnaBridge	171:3a7713b1edbc	3841	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
AnnaBridge	171:3a7713b1edbc	3842	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
AnnaBridge	171:3a7713b1edbc	3843	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
AnnaBridge	171:3a7713b1edbc	3844	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
AnnaBridge	171:3a7713b1edbc	3845	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
AnnaBridge	171:3a7713b1edbc	3846	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
AnnaBridge	171:3a7713b1edbc	3847	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
AnnaBridge	171:3a7713b1edbc	3848	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
AnnaBridge	171:3a7713b1edbc	3849	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
AnnaBridge	171:3a7713b1edbc	3850	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
AnnaBridge	171:3a7713b1edbc	3851	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
AnnaBridge	171:3a7713b1edbc	3852	* @retval None
AnnaBridge	171:3a7713b1edbc	3853	*/
AnnaBridge	171:3a7713b1edbc	3854	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
AnnaBridge	171:3a7713b1edbc	3855	{
AnnaBridge	171:3a7713b1edbc	3856	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	171:3a7713b1edbc	3857	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLQ);
AnnaBridge	171:3a7713b1edbc	3858	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ);
AnnaBridge	171:3a7713b1edbc	3859	}
AnnaBridge	171:3a7713b1edbc	3860
AnnaBridge	171:3a7713b1edbc	3861	#if defined(SPDIFRX)
AnnaBridge	171:3a7713b1edbc	3862	/**
AnnaBridge	171:3a7713b1edbc	3863	* @brief Configure PLLI2S used for SPDIFRX domain clock
AnnaBridge	171:3a7713b1edbc	3864	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	3865	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	3866	* @note PLLN/PLLP can be written only when PLLI2S is disabled
AnnaBridge	171:3a7713b1edbc	3867	* @note This can be selected for SPDIFRX
AnnaBridge	171:3a7713b1edbc	3868	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
AnnaBridge	171:3a7713b1edbc	3869	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
AnnaBridge	171:3a7713b1edbc	3870	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
AnnaBridge	171:3a7713b1edbc	3871	* PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
AnnaBridge	171:3a7713b1edbc	3872	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3873	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	3874	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	3875	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3876	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	3877	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	3878	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	3879	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	3880	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	3881	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	3882	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	3883	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	3884	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	3885	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	3886	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	3887	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	3888	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	3889	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	3890	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	3891	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	3892	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	3893	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	3894	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	3895	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	3896	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	3897	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	3898	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	3899	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	3900	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	3901	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	3902	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	3903	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	3904	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	3905	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	3906	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	3907	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	3908	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	3909	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	3910	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	3911	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	3912	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	3913	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	3914	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	3915	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	3916	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	3917	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	3918	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	3919	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	3920	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	3921	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	3922	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	3923	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	3924	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	3925	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	3926	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	3927	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	3928	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	3929	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	3930	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	3931	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	3932	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	3933	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	3934	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	3935	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	3936	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	3937	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	3938	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	3939	* @param PLLP This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3940	* @arg @ref LL_RCC_PLLI2SP_DIV_2
AnnaBridge	171:3a7713b1edbc	3941	* @arg @ref LL_RCC_PLLI2SP_DIV_4
AnnaBridge	171:3a7713b1edbc	3942	* @arg @ref LL_RCC_PLLI2SP_DIV_6
AnnaBridge	171:3a7713b1edbc	3943	* @arg @ref LL_RCC_PLLI2SP_DIV_8
AnnaBridge	171:3a7713b1edbc	3944	* @retval None
AnnaBridge	171:3a7713b1edbc	3945	*/
AnnaBridge	171:3a7713b1edbc	3946	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	171:3a7713b1edbc	3947	{
AnnaBridge	171:3a7713b1edbc	3948	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	171:3a7713b1edbc	3949	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLP);
AnnaBridge	171:3a7713b1edbc	3950	}
AnnaBridge	171:3a7713b1edbc	3951	#endif /* SPDIFRX */
AnnaBridge	171:3a7713b1edbc	3952
AnnaBridge	171:3a7713b1edbc	3953	/**
AnnaBridge	171:3a7713b1edbc	3954	* @brief Configure PLLI2S used for I2S1 domain clock
AnnaBridge	171:3a7713b1edbc	3955	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	3956	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	3957	* @note PLLN/PLLR can be written only when PLLI2S is disabled
AnnaBridge	171:3a7713b1edbc	3958	* @note This can be selected for I2S
AnnaBridge	171:3a7713b1edbc	3959	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	171:3a7713b1edbc	3960	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	171:3a7713b1edbc	3961	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	171:3a7713b1edbc	3962	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
AnnaBridge	171:3a7713b1edbc	3963	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3964	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	3965	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	3966	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3967	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	3968	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	3969	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	3970	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	3971	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	3972	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	3973	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	3974	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	3975	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	3976	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	3977	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	3978	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	3979	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	3980	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	3981	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	3982	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	3983	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	3984	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	3985	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	3986	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	3987	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	3988	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	3989	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	3990	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	3991	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	3992	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	3993	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	3994	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	3995	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	3996	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	3997	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	3998	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	3999	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	4000	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	4001	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	4002	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	4003	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	4004	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	4005	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	4006	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	4007	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	4008	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	4009	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	4010	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	4011	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	4012	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	4013	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	4014	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	4015	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	4016	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	4017	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	4018	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	4019	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	4020	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	4021	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	4022	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	4023	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	4024	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	4025	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	4026	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	4027	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	4028	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	4029	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	4030	* @param PLLR This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4031	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	171:3a7713b1edbc	4032	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	171:3a7713b1edbc	4033	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	171:3a7713b1edbc	4034	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	171:3a7713b1edbc	4035	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	171:3a7713b1edbc	4036	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	171:3a7713b1edbc	4037	* @retval None
AnnaBridge	171:3a7713b1edbc	4038	*/
AnnaBridge	171:3a7713b1edbc	4039	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	171:3a7713b1edbc	4040	{
AnnaBridge	171:3a7713b1edbc	4041	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	171:3a7713b1edbc	4042	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLR);
AnnaBridge	171:3a7713b1edbc	4043	}
AnnaBridge	171:3a7713b1edbc	4044
AnnaBridge	171:3a7713b1edbc	4045	/**
AnnaBridge	171:3a7713b1edbc	4046	* @brief Get I2SPLL multiplication factor for VCO
AnnaBridge	171:3a7713b1edbc	4047	* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
AnnaBridge	171:3a7713b1edbc	4048	* @retval Between 50 and 432
AnnaBridge	171:3a7713b1edbc	4049	*/
AnnaBridge	171:3a7713b1edbc	4050	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
AnnaBridge	171:3a7713b1edbc	4051	{
AnnaBridge	171:3a7713b1edbc	4052	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
AnnaBridge	171:3a7713b1edbc	4053	}
AnnaBridge	171:3a7713b1edbc	4054
AnnaBridge	171:3a7713b1edbc	4055	/**
AnnaBridge	171:3a7713b1edbc	4056	* @brief Get I2SPLL division factor for PLLI2SQ
AnnaBridge	171:3a7713b1edbc	4057	* @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
AnnaBridge	171:3a7713b1edbc	4058	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4059	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
AnnaBridge	171:3a7713b1edbc	4060	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
AnnaBridge	171:3a7713b1edbc	4061	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
AnnaBridge	171:3a7713b1edbc	4062	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
AnnaBridge	171:3a7713b1edbc	4063	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
AnnaBridge	171:3a7713b1edbc	4064	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
AnnaBridge	171:3a7713b1edbc	4065	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
AnnaBridge	171:3a7713b1edbc	4066	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
AnnaBridge	171:3a7713b1edbc	4067	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
AnnaBridge	171:3a7713b1edbc	4068	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
AnnaBridge	171:3a7713b1edbc	4069	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
AnnaBridge	171:3a7713b1edbc	4070	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
AnnaBridge	171:3a7713b1edbc	4071	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
AnnaBridge	171:3a7713b1edbc	4072	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
AnnaBridge	171:3a7713b1edbc	4073	*/
AnnaBridge	171:3a7713b1edbc	4074	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
AnnaBridge	171:3a7713b1edbc	4075	{
AnnaBridge	171:3a7713b1edbc	4076	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
AnnaBridge	171:3a7713b1edbc	4077	}
AnnaBridge	171:3a7713b1edbc	4078
AnnaBridge	171:3a7713b1edbc	4079	/**
AnnaBridge	171:3a7713b1edbc	4080	* @brief Get I2SPLL division factor for PLLI2SR
AnnaBridge	171:3a7713b1edbc	4081	* @note used for PLLI2SCLK (I2S clock)
AnnaBridge	171:3a7713b1edbc	4082	* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
AnnaBridge	171:3a7713b1edbc	4083	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4084	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	171:3a7713b1edbc	4085	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	171:3a7713b1edbc	4086	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	171:3a7713b1edbc	4087	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	171:3a7713b1edbc	4088	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	171:3a7713b1edbc	4089	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	171:3a7713b1edbc	4090	*/
AnnaBridge	171:3a7713b1edbc	4091	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
AnnaBridge	171:3a7713b1edbc	4092	{
AnnaBridge	171:3a7713b1edbc	4093	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
AnnaBridge	171:3a7713b1edbc	4094	}
AnnaBridge	171:3a7713b1edbc	4095
AnnaBridge	171:3a7713b1edbc	4096	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
AnnaBridge	171:3a7713b1edbc	4097	/**
AnnaBridge	171:3a7713b1edbc	4098	* @brief Get I2SPLL division factor for PLLI2SP
AnnaBridge	171:3a7713b1edbc	4099	* @note used for PLLSPDIFRXCLK (SPDIFRX clock)
AnnaBridge	171:3a7713b1edbc	4100	* @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
AnnaBridge	171:3a7713b1edbc	4101	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4102	* @arg @ref LL_RCC_PLLI2SP_DIV_2
AnnaBridge	171:3a7713b1edbc	4103	* @arg @ref LL_RCC_PLLI2SP_DIV_4
AnnaBridge	171:3a7713b1edbc	4104	* @arg @ref LL_RCC_PLLI2SP_DIV_6
AnnaBridge	171:3a7713b1edbc	4105	* @arg @ref LL_RCC_PLLI2SP_DIV_8
AnnaBridge	171:3a7713b1edbc	4106	*/
AnnaBridge	171:3a7713b1edbc	4107	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
AnnaBridge	171:3a7713b1edbc	4108	{
AnnaBridge	171:3a7713b1edbc	4109	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
AnnaBridge	171:3a7713b1edbc	4110	}
AnnaBridge	171:3a7713b1edbc	4111	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
AnnaBridge	171:3a7713b1edbc	4112
AnnaBridge	171:3a7713b1edbc	4113	/**
AnnaBridge	171:3a7713b1edbc	4114	* @brief Get I2SPLL division factor for PLLI2SDIVQ
AnnaBridge	171:3a7713b1edbc	4115	* @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
AnnaBridge	171:3a7713b1edbc	4116	* @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
AnnaBridge	171:3a7713b1edbc	4117	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4118	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
AnnaBridge	171:3a7713b1edbc	4119	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
AnnaBridge	171:3a7713b1edbc	4120	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
AnnaBridge	171:3a7713b1edbc	4121	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
AnnaBridge	171:3a7713b1edbc	4122	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
AnnaBridge	171:3a7713b1edbc	4123	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
AnnaBridge	171:3a7713b1edbc	4124	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
AnnaBridge	171:3a7713b1edbc	4125	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
AnnaBridge	171:3a7713b1edbc	4126	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
AnnaBridge	171:3a7713b1edbc	4127	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
AnnaBridge	171:3a7713b1edbc	4128	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
AnnaBridge	171:3a7713b1edbc	4129	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
AnnaBridge	171:3a7713b1edbc	4130	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
AnnaBridge	171:3a7713b1edbc	4131	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
AnnaBridge	171:3a7713b1edbc	4132	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
AnnaBridge	171:3a7713b1edbc	4133	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
AnnaBridge	171:3a7713b1edbc	4134	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
AnnaBridge	171:3a7713b1edbc	4135	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
AnnaBridge	171:3a7713b1edbc	4136	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
AnnaBridge	171:3a7713b1edbc	4137	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
AnnaBridge	171:3a7713b1edbc	4138	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
AnnaBridge	171:3a7713b1edbc	4139	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
AnnaBridge	171:3a7713b1edbc	4140	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
AnnaBridge	171:3a7713b1edbc	4141	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
AnnaBridge	171:3a7713b1edbc	4142	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
AnnaBridge	171:3a7713b1edbc	4143	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
AnnaBridge	171:3a7713b1edbc	4144	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
AnnaBridge	171:3a7713b1edbc	4145	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
AnnaBridge	171:3a7713b1edbc	4146	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
AnnaBridge	171:3a7713b1edbc	4147	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
AnnaBridge	171:3a7713b1edbc	4148	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
AnnaBridge	171:3a7713b1edbc	4149	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
AnnaBridge	171:3a7713b1edbc	4150	*/
AnnaBridge	171:3a7713b1edbc	4151	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
AnnaBridge	171:3a7713b1edbc	4152	{
AnnaBridge	171:3a7713b1edbc	4153	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ));
AnnaBridge	171:3a7713b1edbc	4154	}
AnnaBridge	171:3a7713b1edbc	4155
AnnaBridge	171:3a7713b1edbc	4156	/**
AnnaBridge	171:3a7713b1edbc	4157	* @}
AnnaBridge	171:3a7713b1edbc	4158	*/
AnnaBridge	171:3a7713b1edbc	4159
AnnaBridge	171:3a7713b1edbc	4160	/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
AnnaBridge	171:3a7713b1edbc	4161	* @{
AnnaBridge	171:3a7713b1edbc	4162	*/
AnnaBridge	171:3a7713b1edbc	4163
AnnaBridge	171:3a7713b1edbc	4164	/**
AnnaBridge	171:3a7713b1edbc	4165	* @brief Enable PLLSAI
AnnaBridge	171:3a7713b1edbc	4166	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
AnnaBridge	171:3a7713b1edbc	4167	* @retval None
AnnaBridge	171:3a7713b1edbc	4168	*/
AnnaBridge	171:3a7713b1edbc	4169	__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
AnnaBridge	171:3a7713b1edbc	4170	{
AnnaBridge	171:3a7713b1edbc	4171	SET_BIT(RCC->CR, RCC_CR_PLLSAION);
AnnaBridge	171:3a7713b1edbc	4172	}
AnnaBridge	171:3a7713b1edbc	4173
AnnaBridge	171:3a7713b1edbc	4174	/**
AnnaBridge	171:3a7713b1edbc	4175	* @brief Disable PLLSAI
AnnaBridge	171:3a7713b1edbc	4176	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
AnnaBridge	171:3a7713b1edbc	4177	* @retval None
AnnaBridge	171:3a7713b1edbc	4178	*/
AnnaBridge	171:3a7713b1edbc	4179	__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
AnnaBridge	171:3a7713b1edbc	4180	{
AnnaBridge	171:3a7713b1edbc	4181	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
AnnaBridge	171:3a7713b1edbc	4182	}
AnnaBridge	171:3a7713b1edbc	4183
AnnaBridge	171:3a7713b1edbc	4184	/**
AnnaBridge	171:3a7713b1edbc	4185	* @brief Check if PLLSAI Ready
AnnaBridge	171:3a7713b1edbc	4186	* @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
AnnaBridge	171:3a7713b1edbc	4187	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4188	*/
AnnaBridge	171:3a7713b1edbc	4189	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
AnnaBridge	171:3a7713b1edbc	4190	{
AnnaBridge	171:3a7713b1edbc	4191	return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
AnnaBridge	171:3a7713b1edbc	4192	}
AnnaBridge	171:3a7713b1edbc	4193
AnnaBridge	171:3a7713b1edbc	4194	/**
AnnaBridge	171:3a7713b1edbc	4195	* @brief Configure PLLSAI used for SAI1 and SAI2 domain clock
AnnaBridge	171:3a7713b1edbc	4196	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	4197	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	4198	* @note PLLN/PLLQ can be written only when PLLSAI is disabled
AnnaBridge	171:3a7713b1edbc	4199	* @note This can be selected for SAI1 and SAI2
AnnaBridge	171:3a7713b1edbc	4200	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	171:3a7713b1edbc	4201	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	171:3a7713b1edbc	4202	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	171:3a7713b1edbc	4203	* PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
AnnaBridge	171:3a7713b1edbc	4204	* DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
AnnaBridge	171:3a7713b1edbc	4205	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4206	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	4207	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	4208	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4209	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	4210	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	4211	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	4212	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	4213	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	4214	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	4215	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	4216	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	4217	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	4218	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	4219	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	4220	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	4221	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	4222	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	4223	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	4224	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	4225	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	4226	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	4227	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	4228	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	4229	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	4230	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	4231	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	4232	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	4233	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	4234	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	4235	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	4236	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	4237	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	4238	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	4239	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	4240	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	4241	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	4242	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	4243	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	4244	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	4245	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	4246	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	4247	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	4248	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	4249	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	4250	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	4251	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	4252	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	4253	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	4254	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	4255	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	4256	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	4257	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	4258	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	4259	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	4260	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	4261	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	4262	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	4263	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	4264	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	4265	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	4266	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	4267	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	4268	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	4269	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	4270	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	4271	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	4272	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4273	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
AnnaBridge	171:3a7713b1edbc	4274	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
AnnaBridge	171:3a7713b1edbc	4275	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
AnnaBridge	171:3a7713b1edbc	4276	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
AnnaBridge	171:3a7713b1edbc	4277	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
AnnaBridge	171:3a7713b1edbc	4278	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
AnnaBridge	171:3a7713b1edbc	4279	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
AnnaBridge	171:3a7713b1edbc	4280	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
AnnaBridge	171:3a7713b1edbc	4281	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
AnnaBridge	171:3a7713b1edbc	4282	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
AnnaBridge	171:3a7713b1edbc	4283	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
AnnaBridge	171:3a7713b1edbc	4284	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
AnnaBridge	171:3a7713b1edbc	4285	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
AnnaBridge	171:3a7713b1edbc	4286	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
AnnaBridge	171:3a7713b1edbc	4287	* @param PLLDIVQ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4288	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
AnnaBridge	171:3a7713b1edbc	4289	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
AnnaBridge	171:3a7713b1edbc	4290	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
AnnaBridge	171:3a7713b1edbc	4291	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
AnnaBridge	171:3a7713b1edbc	4292	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
AnnaBridge	171:3a7713b1edbc	4293	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
AnnaBridge	171:3a7713b1edbc	4294	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
AnnaBridge	171:3a7713b1edbc	4295	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
AnnaBridge	171:3a7713b1edbc	4296	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
AnnaBridge	171:3a7713b1edbc	4297	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
AnnaBridge	171:3a7713b1edbc	4298	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
AnnaBridge	171:3a7713b1edbc	4299	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
AnnaBridge	171:3a7713b1edbc	4300	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
AnnaBridge	171:3a7713b1edbc	4301	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
AnnaBridge	171:3a7713b1edbc	4302	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
AnnaBridge	171:3a7713b1edbc	4303	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
AnnaBridge	171:3a7713b1edbc	4304	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
AnnaBridge	171:3a7713b1edbc	4305	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
AnnaBridge	171:3a7713b1edbc	4306	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
AnnaBridge	171:3a7713b1edbc	4307	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
AnnaBridge	171:3a7713b1edbc	4308	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
AnnaBridge	171:3a7713b1edbc	4309	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
AnnaBridge	171:3a7713b1edbc	4310	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
AnnaBridge	171:3a7713b1edbc	4311	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
AnnaBridge	171:3a7713b1edbc	4312	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
AnnaBridge	171:3a7713b1edbc	4313	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
AnnaBridge	171:3a7713b1edbc	4314	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
AnnaBridge	171:3a7713b1edbc	4315	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
AnnaBridge	171:3a7713b1edbc	4316	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
AnnaBridge	171:3a7713b1edbc	4317	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
AnnaBridge	171:3a7713b1edbc	4318	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
AnnaBridge	171:3a7713b1edbc	4319	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
AnnaBridge	171:3a7713b1edbc	4320	* @retval None
AnnaBridge	171:3a7713b1edbc	4321	*/
AnnaBridge	171:3a7713b1edbc	4322	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
AnnaBridge	171:3a7713b1edbc	4323	{
AnnaBridge	171:3a7713b1edbc	4324	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	171:3a7713b1edbc	4325	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLQ);
AnnaBridge	171:3a7713b1edbc	4326	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ);
AnnaBridge	171:3a7713b1edbc	4327	}
AnnaBridge	171:3a7713b1edbc	4328
AnnaBridge	171:3a7713b1edbc	4329	/**
AnnaBridge	171:3a7713b1edbc	4330	* @brief Configure PLLSAI used for 48Mhz domain clock
AnnaBridge	171:3a7713b1edbc	4331	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	4332	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	4333	* @note PLLN/PLLP can be written only when PLLSAI is disabled
AnnaBridge	171:3a7713b1edbc	4334	* @note This can be selected for USB, RNG, SDMMC1
AnnaBridge	171:3a7713b1edbc	4335	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
AnnaBridge	171:3a7713b1edbc	4336	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
AnnaBridge	171:3a7713b1edbc	4337	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
AnnaBridge	171:3a7713b1edbc	4338	* PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
AnnaBridge	171:3a7713b1edbc	4339	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4340	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	4341	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	4342	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4343	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	4344	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	4345	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	4346	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	4347	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	4348	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	4349	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	4350	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	4351	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	4352	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	4353	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	4354	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	4355	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	4356	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	4357	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	4358	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	4359	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	4360	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	4361	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	4362	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	4363	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	4364	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	4365	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	4366	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	4367	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	4368	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	4369	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	4370	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	4371	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	4372	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	4373	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	4374	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	4375	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	4376	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	4377	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	4378	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	4379	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	4380	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	4381	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	4382	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	4383	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	4384	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	4385	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	4386	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	4387	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	4388	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	4389	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	4390	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	4391	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	4392	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	4393	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	4394	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	4395	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	4396	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	4397	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	4398	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	4399	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	4400	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	4401	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	4402	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	4403	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	4404	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	4405	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	4406	* @param PLLP This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4407	* @arg @ref LL_RCC_PLLSAIP_DIV_2
AnnaBridge	171:3a7713b1edbc	4408	* @arg @ref LL_RCC_PLLSAIP_DIV_4
AnnaBridge	171:3a7713b1edbc	4409	* @arg @ref LL_RCC_PLLSAIP_DIV_6
AnnaBridge	171:3a7713b1edbc	4410	* @arg @ref LL_RCC_PLLSAIP_DIV_8
AnnaBridge	171:3a7713b1edbc	4411	* @retval None
AnnaBridge	171:3a7713b1edbc	4412	*/
AnnaBridge	171:3a7713b1edbc	4413	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	171:3a7713b1edbc	4414	{
AnnaBridge	171:3a7713b1edbc	4415	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	171:3a7713b1edbc	4416	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLP);
AnnaBridge	171:3a7713b1edbc	4417	}
AnnaBridge	171:3a7713b1edbc	4418
AnnaBridge	171:3a7713b1edbc	4419	#if defined(LTDC)
AnnaBridge	171:3a7713b1edbc	4420	/**
AnnaBridge	171:3a7713b1edbc	4421	* @brief Configure PLLSAI used for LTDC domain clock
AnnaBridge	171:3a7713b1edbc	4422	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	171:3a7713b1edbc	4423	* PLLI2S and PLLSAI are disabled
AnnaBridge	171:3a7713b1edbc	4424	* @note PLLN/PLLR can be written only when PLLSAI is disabled
AnnaBridge	171:3a7713b1edbc	4425	* @note This can be selected for LTDC
AnnaBridge	171:3a7713b1edbc	4426	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
AnnaBridge	171:3a7713b1edbc	4427	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
AnnaBridge	171:3a7713b1edbc	4428	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
AnnaBridge	171:3a7713b1edbc	4429	* PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
AnnaBridge	171:3a7713b1edbc	4430	* DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
AnnaBridge	171:3a7713b1edbc	4431	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4432	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	4433	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	4434	* @param PLLM This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4435	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	171:3a7713b1edbc	4436	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	171:3a7713b1edbc	4437	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	171:3a7713b1edbc	4438	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	171:3a7713b1edbc	4439	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	171:3a7713b1edbc	4440	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	171:3a7713b1edbc	4441	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	171:3a7713b1edbc	4442	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	171:3a7713b1edbc	4443	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	171:3a7713b1edbc	4444	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	171:3a7713b1edbc	4445	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	171:3a7713b1edbc	4446	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	171:3a7713b1edbc	4447	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	171:3a7713b1edbc	4448	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	171:3a7713b1edbc	4449	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	171:3a7713b1edbc	4450	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	171:3a7713b1edbc	4451	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	171:3a7713b1edbc	4452	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	171:3a7713b1edbc	4453	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	171:3a7713b1edbc	4454	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	171:3a7713b1edbc	4455	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	171:3a7713b1edbc	4456	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	171:3a7713b1edbc	4457	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	171:3a7713b1edbc	4458	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	171:3a7713b1edbc	4459	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	171:3a7713b1edbc	4460	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	171:3a7713b1edbc	4461	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	171:3a7713b1edbc	4462	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	171:3a7713b1edbc	4463	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	171:3a7713b1edbc	4464	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	171:3a7713b1edbc	4465	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	171:3a7713b1edbc	4466	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	171:3a7713b1edbc	4467	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	171:3a7713b1edbc	4468	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	171:3a7713b1edbc	4469	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	171:3a7713b1edbc	4470	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	171:3a7713b1edbc	4471	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	171:3a7713b1edbc	4472	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	171:3a7713b1edbc	4473	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	171:3a7713b1edbc	4474	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	171:3a7713b1edbc	4475	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	171:3a7713b1edbc	4476	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	171:3a7713b1edbc	4477	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	171:3a7713b1edbc	4478	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	171:3a7713b1edbc	4479	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	171:3a7713b1edbc	4480	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	171:3a7713b1edbc	4481	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	171:3a7713b1edbc	4482	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	171:3a7713b1edbc	4483	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	171:3a7713b1edbc	4484	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	171:3a7713b1edbc	4485	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	171:3a7713b1edbc	4486	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	171:3a7713b1edbc	4487	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	171:3a7713b1edbc	4488	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	171:3a7713b1edbc	4489	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	171:3a7713b1edbc	4490	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	171:3a7713b1edbc	4491	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	171:3a7713b1edbc	4492	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	171:3a7713b1edbc	4493	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	171:3a7713b1edbc	4494	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	171:3a7713b1edbc	4495	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	171:3a7713b1edbc	4496	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	171:3a7713b1edbc	4497	* @param PLLN Between 50 and 432
AnnaBridge	171:3a7713b1edbc	4498	* @param PLLR This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4499	* @arg @ref LL_RCC_PLLSAIR_DIV_2
AnnaBridge	171:3a7713b1edbc	4500	* @arg @ref LL_RCC_PLLSAIR_DIV_3
AnnaBridge	171:3a7713b1edbc	4501	* @arg @ref LL_RCC_PLLSAIR_DIV_4
AnnaBridge	171:3a7713b1edbc	4502	* @arg @ref LL_RCC_PLLSAIR_DIV_5
AnnaBridge	171:3a7713b1edbc	4503	* @arg @ref LL_RCC_PLLSAIR_DIV_6
AnnaBridge	171:3a7713b1edbc	4504	* @arg @ref LL_RCC_PLLSAIR_DIV_7
AnnaBridge	171:3a7713b1edbc	4505	* @param PLLDIVR This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4506	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
AnnaBridge	171:3a7713b1edbc	4507	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
AnnaBridge	171:3a7713b1edbc	4508	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
AnnaBridge	171:3a7713b1edbc	4509	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
AnnaBridge	171:3a7713b1edbc	4510	* @retval None
AnnaBridge	171:3a7713b1edbc	4511	*/
AnnaBridge	171:3a7713b1edbc	4512	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
AnnaBridge	171:3a7713b1edbc	4513	{
AnnaBridge	171:3a7713b1edbc	4514	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	171:3a7713b1edbc	4515	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLR);
AnnaBridge	171:3a7713b1edbc	4516	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR);
AnnaBridge	171:3a7713b1edbc	4517	}
AnnaBridge	171:3a7713b1edbc	4518	#endif /* LTDC */
AnnaBridge	171:3a7713b1edbc	4519
AnnaBridge	171:3a7713b1edbc	4520	/**
AnnaBridge	171:3a7713b1edbc	4521	* @brief Get SAIPLL multiplication factor for VCO
AnnaBridge	171:3a7713b1edbc	4522	* @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
AnnaBridge	171:3a7713b1edbc	4523	* @retval Between 50 and 432
AnnaBridge	171:3a7713b1edbc	4524	*/
AnnaBridge	171:3a7713b1edbc	4525	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
AnnaBridge	171:3a7713b1edbc	4526	{
AnnaBridge	171:3a7713b1edbc	4527	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
AnnaBridge	171:3a7713b1edbc	4528	}
AnnaBridge	171:3a7713b1edbc	4529
AnnaBridge	171:3a7713b1edbc	4530	/**
AnnaBridge	171:3a7713b1edbc	4531	* @brief Get SAIPLL division factor for PLLSAIQ
AnnaBridge	171:3a7713b1edbc	4532	* @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
AnnaBridge	171:3a7713b1edbc	4533	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4534	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
AnnaBridge	171:3a7713b1edbc	4535	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
AnnaBridge	171:3a7713b1edbc	4536	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
AnnaBridge	171:3a7713b1edbc	4537	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
AnnaBridge	171:3a7713b1edbc	4538	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
AnnaBridge	171:3a7713b1edbc	4539	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
AnnaBridge	171:3a7713b1edbc	4540	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
AnnaBridge	171:3a7713b1edbc	4541	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
AnnaBridge	171:3a7713b1edbc	4542	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
AnnaBridge	171:3a7713b1edbc	4543	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
AnnaBridge	171:3a7713b1edbc	4544	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
AnnaBridge	171:3a7713b1edbc	4545	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
AnnaBridge	171:3a7713b1edbc	4546	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
AnnaBridge	171:3a7713b1edbc	4547	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
AnnaBridge	171:3a7713b1edbc	4548	*/
AnnaBridge	171:3a7713b1edbc	4549	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
AnnaBridge	171:3a7713b1edbc	4550	{
AnnaBridge	171:3a7713b1edbc	4551	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
AnnaBridge	171:3a7713b1edbc	4552	}
AnnaBridge	171:3a7713b1edbc	4553
AnnaBridge	171:3a7713b1edbc	4554	#if defined(RCC_PLLSAICFGR_PLLSAIR)
AnnaBridge	171:3a7713b1edbc	4555	/**
AnnaBridge	171:3a7713b1edbc	4556	* @brief Get SAIPLL division factor for PLLSAIR
AnnaBridge	171:3a7713b1edbc	4557	* @note used for PLLSAICLK (SAI clock)
AnnaBridge	171:3a7713b1edbc	4558	* @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
AnnaBridge	171:3a7713b1edbc	4559	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4560	* @arg @ref LL_RCC_PLLSAIR_DIV_2
AnnaBridge	171:3a7713b1edbc	4561	* @arg @ref LL_RCC_PLLSAIR_DIV_3
AnnaBridge	171:3a7713b1edbc	4562	* @arg @ref LL_RCC_PLLSAIR_DIV_4
AnnaBridge	171:3a7713b1edbc	4563	* @arg @ref LL_RCC_PLLSAIR_DIV_5
AnnaBridge	171:3a7713b1edbc	4564	* @arg @ref LL_RCC_PLLSAIR_DIV_6
AnnaBridge	171:3a7713b1edbc	4565	* @arg @ref LL_RCC_PLLSAIR_DIV_7
AnnaBridge	171:3a7713b1edbc	4566	*/
AnnaBridge	171:3a7713b1edbc	4567	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
AnnaBridge	171:3a7713b1edbc	4568	{
AnnaBridge	171:3a7713b1edbc	4569	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
AnnaBridge	171:3a7713b1edbc	4570	}
AnnaBridge	171:3a7713b1edbc	4571	#endif /* RCC_PLLSAICFGR_PLLSAIR */
AnnaBridge	171:3a7713b1edbc	4572
AnnaBridge	171:3a7713b1edbc	4573	/**
AnnaBridge	171:3a7713b1edbc	4574	* @brief Get SAIPLL division factor for PLLSAIP
AnnaBridge	171:3a7713b1edbc	4575	* @note used for PLL48MCLK (48M domain clock)
AnnaBridge	171:3a7713b1edbc	4576	* @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
AnnaBridge	171:3a7713b1edbc	4577	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4578	* @arg @ref LL_RCC_PLLSAIP_DIV_2
AnnaBridge	171:3a7713b1edbc	4579	* @arg @ref LL_RCC_PLLSAIP_DIV_4
AnnaBridge	171:3a7713b1edbc	4580	* @arg @ref LL_RCC_PLLSAIP_DIV_6
AnnaBridge	171:3a7713b1edbc	4581	* @arg @ref LL_RCC_PLLSAIP_DIV_8
AnnaBridge	171:3a7713b1edbc	4582	*/
AnnaBridge	171:3a7713b1edbc	4583	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
AnnaBridge	171:3a7713b1edbc	4584	{
AnnaBridge	171:3a7713b1edbc	4585	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
AnnaBridge	171:3a7713b1edbc	4586	}
AnnaBridge	171:3a7713b1edbc	4587
AnnaBridge	171:3a7713b1edbc	4588	/**
AnnaBridge	171:3a7713b1edbc	4589	* @brief Get SAIPLL division factor for PLLSAIDIVQ
AnnaBridge	171:3a7713b1edbc	4590	* @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
AnnaBridge	171:3a7713b1edbc	4591	* @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
AnnaBridge	171:3a7713b1edbc	4592	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4593	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
AnnaBridge	171:3a7713b1edbc	4594	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
AnnaBridge	171:3a7713b1edbc	4595	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
AnnaBridge	171:3a7713b1edbc	4596	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
AnnaBridge	171:3a7713b1edbc	4597	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
AnnaBridge	171:3a7713b1edbc	4598	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
AnnaBridge	171:3a7713b1edbc	4599	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
AnnaBridge	171:3a7713b1edbc	4600	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
AnnaBridge	171:3a7713b1edbc	4601	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
AnnaBridge	171:3a7713b1edbc	4602	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
AnnaBridge	171:3a7713b1edbc	4603	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
AnnaBridge	171:3a7713b1edbc	4604	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
AnnaBridge	171:3a7713b1edbc	4605	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
AnnaBridge	171:3a7713b1edbc	4606	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
AnnaBridge	171:3a7713b1edbc	4607	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
AnnaBridge	171:3a7713b1edbc	4608	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
AnnaBridge	171:3a7713b1edbc	4609	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
AnnaBridge	171:3a7713b1edbc	4610	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
AnnaBridge	171:3a7713b1edbc	4611	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
AnnaBridge	171:3a7713b1edbc	4612	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
AnnaBridge	171:3a7713b1edbc	4613	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
AnnaBridge	171:3a7713b1edbc	4614	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
AnnaBridge	171:3a7713b1edbc	4615	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
AnnaBridge	171:3a7713b1edbc	4616	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
AnnaBridge	171:3a7713b1edbc	4617	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
AnnaBridge	171:3a7713b1edbc	4618	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
AnnaBridge	171:3a7713b1edbc	4619	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
AnnaBridge	171:3a7713b1edbc	4620	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
AnnaBridge	171:3a7713b1edbc	4621	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
AnnaBridge	171:3a7713b1edbc	4622	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
AnnaBridge	171:3a7713b1edbc	4623	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
AnnaBridge	171:3a7713b1edbc	4624	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
AnnaBridge	171:3a7713b1edbc	4625	*/
AnnaBridge	171:3a7713b1edbc	4626	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
AnnaBridge	171:3a7713b1edbc	4627	{
AnnaBridge	171:3a7713b1edbc	4628	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ));
AnnaBridge	171:3a7713b1edbc	4629	}
AnnaBridge	171:3a7713b1edbc	4630
AnnaBridge	171:3a7713b1edbc	4631	#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
AnnaBridge	171:3a7713b1edbc	4632	/**
AnnaBridge	171:3a7713b1edbc	4633	* @brief Get SAIPLL division factor for PLLSAIDIVR
AnnaBridge	171:3a7713b1edbc	4634	* @note used for LTDC domain clock
AnnaBridge	171:3a7713b1edbc	4635	* @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
AnnaBridge	171:3a7713b1edbc	4636	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	4637	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
AnnaBridge	171:3a7713b1edbc	4638	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
AnnaBridge	171:3a7713b1edbc	4639	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
AnnaBridge	171:3a7713b1edbc	4640	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
AnnaBridge	171:3a7713b1edbc	4641	*/
AnnaBridge	171:3a7713b1edbc	4642	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
AnnaBridge	171:3a7713b1edbc	4643	{
AnnaBridge	171:3a7713b1edbc	4644	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR));
AnnaBridge	171:3a7713b1edbc	4645	}
AnnaBridge	171:3a7713b1edbc	4646	#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
AnnaBridge	171:3a7713b1edbc	4647
AnnaBridge	171:3a7713b1edbc	4648	/**
AnnaBridge	171:3a7713b1edbc	4649	* @}
AnnaBridge	171:3a7713b1edbc	4650	*/
AnnaBridge	171:3a7713b1edbc	4651
AnnaBridge	171:3a7713b1edbc	4652	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	171:3a7713b1edbc	4653	* @{
AnnaBridge	171:3a7713b1edbc	4654	*/
AnnaBridge	171:3a7713b1edbc	4655
AnnaBridge	171:3a7713b1edbc	4656	/**
AnnaBridge	171:3a7713b1edbc	4657	* @brief Clear LSI ready interrupt flag
AnnaBridge	171:3a7713b1edbc	4658	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	171:3a7713b1edbc	4659	* @retval None
AnnaBridge	171:3a7713b1edbc	4660	*/
AnnaBridge	171:3a7713b1edbc	4661	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	4662	{
AnnaBridge	171:3a7713b1edbc	4663	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
AnnaBridge	171:3a7713b1edbc	4664	}
AnnaBridge	171:3a7713b1edbc	4665
AnnaBridge	171:3a7713b1edbc	4666	/**
AnnaBridge	171:3a7713b1edbc	4667	* @brief Clear LSE ready interrupt flag
AnnaBridge	171:3a7713b1edbc	4668	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	171:3a7713b1edbc	4669	* @retval None
AnnaBridge	171:3a7713b1edbc	4670	*/
AnnaBridge	171:3a7713b1edbc	4671	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	4672	{
AnnaBridge	171:3a7713b1edbc	4673	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
AnnaBridge	171:3a7713b1edbc	4674	}
AnnaBridge	171:3a7713b1edbc	4675
AnnaBridge	171:3a7713b1edbc	4676	/**
AnnaBridge	171:3a7713b1edbc	4677	* @brief Clear HSI ready interrupt flag
AnnaBridge	171:3a7713b1edbc	4678	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	171:3a7713b1edbc	4679	* @retval None
AnnaBridge	171:3a7713b1edbc	4680	*/
AnnaBridge	171:3a7713b1edbc	4681	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	4682	{
AnnaBridge	171:3a7713b1edbc	4683	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
AnnaBridge	171:3a7713b1edbc	4684	}
AnnaBridge	171:3a7713b1edbc	4685
AnnaBridge	171:3a7713b1edbc	4686	/**
AnnaBridge	171:3a7713b1edbc	4687	* @brief Clear HSE ready interrupt flag
AnnaBridge	171:3a7713b1edbc	4688	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	171:3a7713b1edbc	4689	* @retval None
AnnaBridge	171:3a7713b1edbc	4690	*/
AnnaBridge	171:3a7713b1edbc	4691	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	4692	{
AnnaBridge	171:3a7713b1edbc	4693	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
AnnaBridge	171:3a7713b1edbc	4694	}
AnnaBridge	171:3a7713b1edbc	4695
AnnaBridge	171:3a7713b1edbc	4696	/**
AnnaBridge	171:3a7713b1edbc	4697	* @brief Clear PLL ready interrupt flag
AnnaBridge	171:3a7713b1edbc	4698	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	171:3a7713b1edbc	4699	* @retval None
AnnaBridge	171:3a7713b1edbc	4700	*/
AnnaBridge	171:3a7713b1edbc	4701	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	4702	{
AnnaBridge	171:3a7713b1edbc	4703	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
AnnaBridge	171:3a7713b1edbc	4704	}
AnnaBridge	171:3a7713b1edbc	4705
AnnaBridge	171:3a7713b1edbc	4706	/**
AnnaBridge	171:3a7713b1edbc	4707	* @brief Clear PLLI2S ready interrupt flag
AnnaBridge	171:3a7713b1edbc	4708	* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	4709	* @retval None
AnnaBridge	171:3a7713b1edbc	4710	*/
AnnaBridge	171:3a7713b1edbc	4711	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	4712	{
AnnaBridge	171:3a7713b1edbc	4713	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
AnnaBridge	171:3a7713b1edbc	4714	}
AnnaBridge	171:3a7713b1edbc	4715
AnnaBridge	171:3a7713b1edbc	4716	/**
AnnaBridge	171:3a7713b1edbc	4717	* @brief Clear PLLSAI ready interrupt flag
AnnaBridge	171:3a7713b1edbc	4718	* @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
AnnaBridge	171:3a7713b1edbc	4719	* @retval None
AnnaBridge	171:3a7713b1edbc	4720	*/
AnnaBridge	171:3a7713b1edbc	4721	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
AnnaBridge	171:3a7713b1edbc	4722	{
AnnaBridge	171:3a7713b1edbc	4723	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
AnnaBridge	171:3a7713b1edbc	4724	}
AnnaBridge	171:3a7713b1edbc	4725
AnnaBridge	171:3a7713b1edbc	4726	/**
AnnaBridge	171:3a7713b1edbc	4727	* @brief Clear Clock security system interrupt flag
AnnaBridge	171:3a7713b1edbc	4728	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	171:3a7713b1edbc	4729	* @retval None
AnnaBridge	171:3a7713b1edbc	4730	*/
AnnaBridge	171:3a7713b1edbc	4731	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	171:3a7713b1edbc	4732	{
AnnaBridge	171:3a7713b1edbc	4733	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
AnnaBridge	171:3a7713b1edbc	4734	}
AnnaBridge	171:3a7713b1edbc	4735
AnnaBridge	171:3a7713b1edbc	4736	/**
AnnaBridge	171:3a7713b1edbc	4737	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	4738	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	171:3a7713b1edbc	4739	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4740	*/
AnnaBridge	171:3a7713b1edbc	4741	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	4742	{
AnnaBridge	171:3a7713b1edbc	4743	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
AnnaBridge	171:3a7713b1edbc	4744	}
AnnaBridge	171:3a7713b1edbc	4745
AnnaBridge	171:3a7713b1edbc	4746	/**
AnnaBridge	171:3a7713b1edbc	4747	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	4748	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	171:3a7713b1edbc	4749	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4750	*/
AnnaBridge	171:3a7713b1edbc	4751	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	4752	{
AnnaBridge	171:3a7713b1edbc	4753	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
AnnaBridge	171:3a7713b1edbc	4754	}
AnnaBridge	171:3a7713b1edbc	4755
AnnaBridge	171:3a7713b1edbc	4756	/**
AnnaBridge	171:3a7713b1edbc	4757	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	4758	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	171:3a7713b1edbc	4759	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4760	*/
AnnaBridge	171:3a7713b1edbc	4761	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	4762	{
AnnaBridge	171:3a7713b1edbc	4763	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
AnnaBridge	171:3a7713b1edbc	4764	}
AnnaBridge	171:3a7713b1edbc	4765
AnnaBridge	171:3a7713b1edbc	4766	/**
AnnaBridge	171:3a7713b1edbc	4767	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	4768	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	171:3a7713b1edbc	4769	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4770	*/
AnnaBridge	171:3a7713b1edbc	4771	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	4772	{
AnnaBridge	171:3a7713b1edbc	4773	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
AnnaBridge	171:3a7713b1edbc	4774	}
AnnaBridge	171:3a7713b1edbc	4775
AnnaBridge	171:3a7713b1edbc	4776	/**
AnnaBridge	171:3a7713b1edbc	4777	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	4778	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	171:3a7713b1edbc	4779	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4780	*/
AnnaBridge	171:3a7713b1edbc	4781	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	4782	{
AnnaBridge	171:3a7713b1edbc	4783	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
AnnaBridge	171:3a7713b1edbc	4784	}
AnnaBridge	171:3a7713b1edbc	4785
AnnaBridge	171:3a7713b1edbc	4786	/**
AnnaBridge	171:3a7713b1edbc	4787	* @brief Check if PLLI2S ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	4788	* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	4789	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4790	*/
AnnaBridge	171:3a7713b1edbc	4791	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	4792	{
AnnaBridge	171:3a7713b1edbc	4793	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
AnnaBridge	171:3a7713b1edbc	4794	}
AnnaBridge	171:3a7713b1edbc	4795
AnnaBridge	171:3a7713b1edbc	4796	/**
AnnaBridge	171:3a7713b1edbc	4797	* @brief Check if PLLSAI ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	4798	* @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
AnnaBridge	171:3a7713b1edbc	4799	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4800	*/
AnnaBridge	171:3a7713b1edbc	4801	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
AnnaBridge	171:3a7713b1edbc	4802	{
AnnaBridge	171:3a7713b1edbc	4803	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
AnnaBridge	171:3a7713b1edbc	4804	}
AnnaBridge	171:3a7713b1edbc	4805
AnnaBridge	171:3a7713b1edbc	4806	/**
AnnaBridge	171:3a7713b1edbc	4807	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	4808	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	171:3a7713b1edbc	4809	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4810	*/
AnnaBridge	171:3a7713b1edbc	4811	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	171:3a7713b1edbc	4812	{
AnnaBridge	171:3a7713b1edbc	4813	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
AnnaBridge	171:3a7713b1edbc	4814	}
AnnaBridge	171:3a7713b1edbc	4815
AnnaBridge	171:3a7713b1edbc	4816	/**
AnnaBridge	171:3a7713b1edbc	4817	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	171:3a7713b1edbc	4818	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	171:3a7713b1edbc	4819	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4820	*/
AnnaBridge	171:3a7713b1edbc	4821	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	171:3a7713b1edbc	4822	{
AnnaBridge	171:3a7713b1edbc	4823	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	171:3a7713b1edbc	4824	}
AnnaBridge	171:3a7713b1edbc	4825
AnnaBridge	171:3a7713b1edbc	4826	/**
AnnaBridge	171:3a7713b1edbc	4827	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	171:3a7713b1edbc	4828	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	171:3a7713b1edbc	4829	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4830	*/
AnnaBridge	171:3a7713b1edbc	4831	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	171:3a7713b1edbc	4832	{
AnnaBridge	171:3a7713b1edbc	4833	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	171:3a7713b1edbc	4834	}
AnnaBridge	171:3a7713b1edbc	4835
AnnaBridge	171:3a7713b1edbc	4836	/**
AnnaBridge	171:3a7713b1edbc	4837	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	171:3a7713b1edbc	4838	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	171:3a7713b1edbc	4839	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4840	*/
AnnaBridge	171:3a7713b1edbc	4841	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	171:3a7713b1edbc	4842	{
AnnaBridge	171:3a7713b1edbc	4843	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	171:3a7713b1edbc	4844	}
AnnaBridge	171:3a7713b1edbc	4845
AnnaBridge	171:3a7713b1edbc	4846	/**
AnnaBridge	171:3a7713b1edbc	4847	* @brief Check if RCC flag POR/PDR reset is set or not.
AnnaBridge	171:3a7713b1edbc	4848	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
AnnaBridge	171:3a7713b1edbc	4849	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4850	*/
AnnaBridge	171:3a7713b1edbc	4851	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
AnnaBridge	171:3a7713b1edbc	4852	{
AnnaBridge	171:3a7713b1edbc	4853	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
AnnaBridge	171:3a7713b1edbc	4854	}
AnnaBridge	171:3a7713b1edbc	4855
AnnaBridge	171:3a7713b1edbc	4856	/**
AnnaBridge	171:3a7713b1edbc	4857	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	171:3a7713b1edbc	4858	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	171:3a7713b1edbc	4859	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4860	*/
AnnaBridge	171:3a7713b1edbc	4861	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	171:3a7713b1edbc	4862	{
AnnaBridge	171:3a7713b1edbc	4863	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	171:3a7713b1edbc	4864	}
AnnaBridge	171:3a7713b1edbc	4865
AnnaBridge	171:3a7713b1edbc	4866	/**
AnnaBridge	171:3a7713b1edbc	4867	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	171:3a7713b1edbc	4868	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	171:3a7713b1edbc	4869	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4870	*/
AnnaBridge	171:3a7713b1edbc	4871	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	171:3a7713b1edbc	4872	{
AnnaBridge	171:3a7713b1edbc	4873	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	171:3a7713b1edbc	4874	}
AnnaBridge	171:3a7713b1edbc	4875
AnnaBridge	171:3a7713b1edbc	4876	/**
AnnaBridge	171:3a7713b1edbc	4877	* @brief Check if RCC flag BOR reset is set or not.
AnnaBridge	171:3a7713b1edbc	4878	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
AnnaBridge	171:3a7713b1edbc	4879	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	4880	*/
AnnaBridge	171:3a7713b1edbc	4881	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
AnnaBridge	171:3a7713b1edbc	4882	{
AnnaBridge	171:3a7713b1edbc	4883	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
AnnaBridge	171:3a7713b1edbc	4884	}
AnnaBridge	171:3a7713b1edbc	4885
AnnaBridge	171:3a7713b1edbc	4886	/**
AnnaBridge	171:3a7713b1edbc	4887	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	171:3a7713b1edbc	4888	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	171:3a7713b1edbc	4889	* @retval None
AnnaBridge	171:3a7713b1edbc	4890	*/
AnnaBridge	171:3a7713b1edbc	4891	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	171:3a7713b1edbc	4892	{
AnnaBridge	171:3a7713b1edbc	4893	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	171:3a7713b1edbc	4894	}
AnnaBridge	171:3a7713b1edbc	4895
AnnaBridge	171:3a7713b1edbc	4896	/**
AnnaBridge	171:3a7713b1edbc	4897	* @}
AnnaBridge	171:3a7713b1edbc	4898	*/
AnnaBridge	171:3a7713b1edbc	4899
AnnaBridge	171:3a7713b1edbc	4900	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	171:3a7713b1edbc	4901	* @{
AnnaBridge	171:3a7713b1edbc	4902	*/
AnnaBridge	171:3a7713b1edbc	4903
AnnaBridge	171:3a7713b1edbc	4904	/**
AnnaBridge	171:3a7713b1edbc	4905	* @brief Enable LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	4906	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	4907	* @retval None
AnnaBridge	171:3a7713b1edbc	4908	*/
AnnaBridge	171:3a7713b1edbc	4909	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	4910	{
AnnaBridge	171:3a7713b1edbc	4911	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	171:3a7713b1edbc	4912	}
AnnaBridge	171:3a7713b1edbc	4913
AnnaBridge	171:3a7713b1edbc	4914	/**
AnnaBridge	171:3a7713b1edbc	4915	* @brief Enable LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	4916	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	171:3a7713b1edbc	4917	* @retval None
AnnaBridge	171:3a7713b1edbc	4918	*/
AnnaBridge	171:3a7713b1edbc	4919	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	4920	{
AnnaBridge	171:3a7713b1edbc	4921	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	171:3a7713b1edbc	4922	}
AnnaBridge	171:3a7713b1edbc	4923
AnnaBridge	171:3a7713b1edbc	4924	/**
AnnaBridge	171:3a7713b1edbc	4925	* @brief Enable HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	4926	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	4927	* @retval None
AnnaBridge	171:3a7713b1edbc	4928	*/
AnnaBridge	171:3a7713b1edbc	4929	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	4930	{
AnnaBridge	171:3a7713b1edbc	4931	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	171:3a7713b1edbc	4932	}
AnnaBridge	171:3a7713b1edbc	4933
AnnaBridge	171:3a7713b1edbc	4934	/**
AnnaBridge	171:3a7713b1edbc	4935	* @brief Enable HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	4936	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	171:3a7713b1edbc	4937	* @retval None
AnnaBridge	171:3a7713b1edbc	4938	*/
AnnaBridge	171:3a7713b1edbc	4939	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	4940	{
AnnaBridge	171:3a7713b1edbc	4941	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	171:3a7713b1edbc	4942	}
AnnaBridge	171:3a7713b1edbc	4943
AnnaBridge	171:3a7713b1edbc	4944	/**
AnnaBridge	171:3a7713b1edbc	4945	* @brief Enable PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	4946	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	4947	* @retval None
AnnaBridge	171:3a7713b1edbc	4948	*/
AnnaBridge	171:3a7713b1edbc	4949	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	4950	{
AnnaBridge	171:3a7713b1edbc	4951	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	171:3a7713b1edbc	4952	}
AnnaBridge	171:3a7713b1edbc	4953
AnnaBridge	171:3a7713b1edbc	4954	/**
AnnaBridge	171:3a7713b1edbc	4955	* @brief Enable PLLI2S ready interrupt
AnnaBridge	171:3a7713b1edbc	4956	* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	4957	* @retval None
AnnaBridge	171:3a7713b1edbc	4958	*/
AnnaBridge	171:3a7713b1edbc	4959	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	4960	{
AnnaBridge	171:3a7713b1edbc	4961	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
AnnaBridge	171:3a7713b1edbc	4962	}
AnnaBridge	171:3a7713b1edbc	4963
AnnaBridge	171:3a7713b1edbc	4964	/**
AnnaBridge	171:3a7713b1edbc	4965	* @brief Enable PLLSAI ready interrupt
AnnaBridge	171:3a7713b1edbc	4966	* @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
AnnaBridge	171:3a7713b1edbc	4967	* @retval None
AnnaBridge	171:3a7713b1edbc	4968	*/
AnnaBridge	171:3a7713b1edbc	4969	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
AnnaBridge	171:3a7713b1edbc	4970	{
AnnaBridge	171:3a7713b1edbc	4971	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
AnnaBridge	171:3a7713b1edbc	4972	}
AnnaBridge	171:3a7713b1edbc	4973
AnnaBridge	171:3a7713b1edbc	4974	/**
AnnaBridge	171:3a7713b1edbc	4975	* @brief Disable LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	4976	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	4977	* @retval None
AnnaBridge	171:3a7713b1edbc	4978	*/
AnnaBridge	171:3a7713b1edbc	4979	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	4980	{
AnnaBridge	171:3a7713b1edbc	4981	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	171:3a7713b1edbc	4982	}
AnnaBridge	171:3a7713b1edbc	4983
AnnaBridge	171:3a7713b1edbc	4984	/**
AnnaBridge	171:3a7713b1edbc	4985	* @brief Disable LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	4986	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	171:3a7713b1edbc	4987	* @retval None
AnnaBridge	171:3a7713b1edbc	4988	*/
AnnaBridge	171:3a7713b1edbc	4989	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	4990	{
AnnaBridge	171:3a7713b1edbc	4991	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	171:3a7713b1edbc	4992	}
AnnaBridge	171:3a7713b1edbc	4993
AnnaBridge	171:3a7713b1edbc	4994	/**
AnnaBridge	171:3a7713b1edbc	4995	* @brief Disable HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	4996	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	4997	* @retval None
AnnaBridge	171:3a7713b1edbc	4998	*/
AnnaBridge	171:3a7713b1edbc	4999	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	5000	{
AnnaBridge	171:3a7713b1edbc	5001	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	171:3a7713b1edbc	5002	}
AnnaBridge	171:3a7713b1edbc	5003
AnnaBridge	171:3a7713b1edbc	5004	/**
AnnaBridge	171:3a7713b1edbc	5005	* @brief Disable HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	5006	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	171:3a7713b1edbc	5007	* @retval None
AnnaBridge	171:3a7713b1edbc	5008	*/
AnnaBridge	171:3a7713b1edbc	5009	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	5010	{
AnnaBridge	171:3a7713b1edbc	5011	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	171:3a7713b1edbc	5012	}
AnnaBridge	171:3a7713b1edbc	5013
AnnaBridge	171:3a7713b1edbc	5014	/**
AnnaBridge	171:3a7713b1edbc	5015	* @brief Disable PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	5016	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	5017	* @retval None
AnnaBridge	171:3a7713b1edbc	5018	*/
AnnaBridge	171:3a7713b1edbc	5019	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	5020	{
AnnaBridge	171:3a7713b1edbc	5021	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	171:3a7713b1edbc	5022	}
AnnaBridge	171:3a7713b1edbc	5023
AnnaBridge	171:3a7713b1edbc	5024	/**
AnnaBridge	171:3a7713b1edbc	5025	* @brief Disable PLLI2S ready interrupt
AnnaBridge	171:3a7713b1edbc	5026	* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	5027	* @retval None
AnnaBridge	171:3a7713b1edbc	5028	*/
AnnaBridge	171:3a7713b1edbc	5029	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	5030	{
AnnaBridge	171:3a7713b1edbc	5031	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
AnnaBridge	171:3a7713b1edbc	5032	}
AnnaBridge	171:3a7713b1edbc	5033
AnnaBridge	171:3a7713b1edbc	5034	/**
AnnaBridge	171:3a7713b1edbc	5035	* @brief Disable PLLSAI ready interrupt
AnnaBridge	171:3a7713b1edbc	5036	* @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
AnnaBridge	171:3a7713b1edbc	5037	* @retval None
AnnaBridge	171:3a7713b1edbc	5038	*/
AnnaBridge	171:3a7713b1edbc	5039	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
AnnaBridge	171:3a7713b1edbc	5040	{
AnnaBridge	171:3a7713b1edbc	5041	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
AnnaBridge	171:3a7713b1edbc	5042	}
AnnaBridge	171:3a7713b1edbc	5043
AnnaBridge	171:3a7713b1edbc	5044	/**
AnnaBridge	171:3a7713b1edbc	5045	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	5046	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	5047	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	5048	*/
AnnaBridge	171:3a7713b1edbc	5049	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	5050	{
AnnaBridge	171:3a7713b1edbc	5051	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
AnnaBridge	171:3a7713b1edbc	5052	}
AnnaBridge	171:3a7713b1edbc	5053
AnnaBridge	171:3a7713b1edbc	5054	/**
AnnaBridge	171:3a7713b1edbc	5055	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	5056	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	171:3a7713b1edbc	5057	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	5058	*/
AnnaBridge	171:3a7713b1edbc	5059	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	5060	{
AnnaBridge	171:3a7713b1edbc	5061	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
AnnaBridge	171:3a7713b1edbc	5062	}
AnnaBridge	171:3a7713b1edbc	5063
AnnaBridge	171:3a7713b1edbc	5064	/**
AnnaBridge	171:3a7713b1edbc	5065	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	5066	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	5067	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	5068	*/
AnnaBridge	171:3a7713b1edbc	5069	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	5070	{
AnnaBridge	171:3a7713b1edbc	5071	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
AnnaBridge	171:3a7713b1edbc	5072	}
AnnaBridge	171:3a7713b1edbc	5073
AnnaBridge	171:3a7713b1edbc	5074	/**
AnnaBridge	171:3a7713b1edbc	5075	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	5076	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	171:3a7713b1edbc	5077	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	5078	*/
AnnaBridge	171:3a7713b1edbc	5079	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	5080	{
AnnaBridge	171:3a7713b1edbc	5081	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
AnnaBridge	171:3a7713b1edbc	5082	}
AnnaBridge	171:3a7713b1edbc	5083
AnnaBridge	171:3a7713b1edbc	5084	/**
AnnaBridge	171:3a7713b1edbc	5085	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	5086	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	5087	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	5088	*/
AnnaBridge	171:3a7713b1edbc	5089	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	5090	{
AnnaBridge	171:3a7713b1edbc	5091	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
AnnaBridge	171:3a7713b1edbc	5092	}
AnnaBridge	171:3a7713b1edbc	5093
AnnaBridge	171:3a7713b1edbc	5094	/**
AnnaBridge	171:3a7713b1edbc	5095	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	5096	* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	5097	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	5098	*/
AnnaBridge	171:3a7713b1edbc	5099	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	5100	{
AnnaBridge	171:3a7713b1edbc	5101	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
AnnaBridge	171:3a7713b1edbc	5102	}
AnnaBridge	171:3a7713b1edbc	5103
AnnaBridge	171:3a7713b1edbc	5104	/**
AnnaBridge	171:3a7713b1edbc	5105	* @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	5106	* @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
AnnaBridge	171:3a7713b1edbc	5107	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	5108	*/
AnnaBridge	171:3a7713b1edbc	5109	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
AnnaBridge	171:3a7713b1edbc	5110	{
AnnaBridge	171:3a7713b1edbc	5111	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
AnnaBridge	171:3a7713b1edbc	5112	}
AnnaBridge	171:3a7713b1edbc	5113
AnnaBridge	171:3a7713b1edbc	5114	/**
AnnaBridge	171:3a7713b1edbc	5115	* @}
AnnaBridge	171:3a7713b1edbc	5116	*/
AnnaBridge	171:3a7713b1edbc	5117
AnnaBridge	171:3a7713b1edbc	5118	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	5119	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	171:3a7713b1edbc	5120	* @{
AnnaBridge	171:3a7713b1edbc	5121	*/
AnnaBridge	171:3a7713b1edbc	5122	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	171:3a7713b1edbc	5123	/**
AnnaBridge	171:3a7713b1edbc	5124	* @}
AnnaBridge	171:3a7713b1edbc	5125	*/
AnnaBridge	171:3a7713b1edbc	5126
AnnaBridge	171:3a7713b1edbc	5127	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	171:3a7713b1edbc	5128	* @{
AnnaBridge	171:3a7713b1edbc	5129	*/
AnnaBridge	171:3a7713b1edbc	5130	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	171:3a7713b1edbc	5131	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
AnnaBridge	171:3a7713b1edbc	5132	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
AnnaBridge	171:3a7713b1edbc	5133	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
AnnaBridge	171:3a7713b1edbc	5134	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
AnnaBridge	171:3a7713b1edbc	5135	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
AnnaBridge	171:3a7713b1edbc	5136	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
AnnaBridge	171:3a7713b1edbc	5137	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
AnnaBridge	171:3a7713b1edbc	5138	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
AnnaBridge	171:3a7713b1edbc	5139	#if defined(DFSDM1_Channel0)
AnnaBridge	171:3a7713b1edbc	5140	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
AnnaBridge	171:3a7713b1edbc	5141	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
AnnaBridge	171:3a7713b1edbc	5142	#endif /* DFSDM1_Channel0 */
AnnaBridge	171:3a7713b1edbc	5143	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
AnnaBridge	171:3a7713b1edbc	5144	#if defined(CEC)
AnnaBridge	171:3a7713b1edbc	5145	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
AnnaBridge	171:3a7713b1edbc	5146	#endif /* CEC */
AnnaBridge	171:3a7713b1edbc	5147	#if defined(LTDC)
AnnaBridge	171:3a7713b1edbc	5148	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
AnnaBridge	171:3a7713b1edbc	5149	#endif /* LTDC */
AnnaBridge	171:3a7713b1edbc	5150	#if defined(SPDIFRX)
AnnaBridge	171:3a7713b1edbc	5151	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
AnnaBridge	171:3a7713b1edbc	5152	#endif /* SPDIFRX */
AnnaBridge	171:3a7713b1edbc	5153	#if defined(DSI)
AnnaBridge	171:3a7713b1edbc	5154	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
AnnaBridge	171:3a7713b1edbc	5155	#endif /* DSI */
AnnaBridge	171:3a7713b1edbc	5156	/**
AnnaBridge	171:3a7713b1edbc	5157	* @}
AnnaBridge	171:3a7713b1edbc	5158	*/
AnnaBridge	171:3a7713b1edbc	5159	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	5160
AnnaBridge	171:3a7713b1edbc	5161	/**
AnnaBridge	171:3a7713b1edbc	5162	* @}
AnnaBridge	171:3a7713b1edbc	5163	*/
AnnaBridge	171:3a7713b1edbc	5164
AnnaBridge	171:3a7713b1edbc	5165	/**
AnnaBridge	171:3a7713b1edbc	5166	* @}
AnnaBridge	171:3a7713b1edbc	5167	*/
AnnaBridge	171:3a7713b1edbc	5168
AnnaBridge	171:3a7713b1edbc	5169	#endif /* defined(RCC) */
AnnaBridge	171:3a7713b1edbc	5170
AnnaBridge	171:3a7713b1edbc	5171	/**
AnnaBridge	171:3a7713b1edbc	5172	* @}
AnnaBridge	171:3a7713b1edbc	5173	*/
AnnaBridge	171:3a7713b1edbc	5174
AnnaBridge	171:3a7713b1edbc	5175	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	5176	}
AnnaBridge	171:3a7713b1edbc	5177	#endif
AnnaBridge	171:3a7713b1edbc	5178
AnnaBridge	171:3a7713b1edbc	5179	#endif /* __STM32F7xx_LL_RCC_H */
AnnaBridge	171:3a7713b1edbc	5180
AnnaBridge	171:3a7713b1edbc	5181	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/