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TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f7xx_ll_pwr.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f7xx_ll_pwr.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of PWR LL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F7xx_LL_PWR_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F7xx_LL_PWR_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f7xx.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F7xx_LL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 #if defined(PWR)
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @defgroup PWR_LL PWR
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 59 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 61 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 62 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 63 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
AnnaBridge 171:3a7713b1edbc 64 * @{
AnnaBridge 171:3a7713b1edbc 65 */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge 171:3a7713b1edbc 68 * @brief Flags defines which can be used with LL_PWR_WriteReg function
AnnaBridge 171:3a7713b1edbc 69 * @{
AnnaBridge 171:3a7713b1edbc 70 */
AnnaBridge 171:3a7713b1edbc 71 #define LL_PWR_CR1_CSBF PWR_CR1_CSBF /*!< Clear standby flag */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 #define LL_PWR_CR2_CWUF6 PWR_CR2_CWUF6 /*!< Clear WKUP pin 6 */
AnnaBridge 171:3a7713b1edbc 74 #define LL_PWR_CR2_CWUF5 PWR_CR2_CWUF5 /*!< Clear WKUP pin 5 */
AnnaBridge 171:3a7713b1edbc 75 #define LL_PWR_CR2_CWUF4 PWR_CR2_CWUF4 /*!< Clear WKUP pin 4 */
AnnaBridge 171:3a7713b1edbc 76 #define LL_PWR_CR2_CWUF3 PWR_CR2_CWUF3 /*!< Clear WKUP pin 3 */
AnnaBridge 171:3a7713b1edbc 77 #define LL_PWR_CR2_CWUF2 PWR_CR2_CWUF2 /*!< Clear WKUP pin 2 */
AnnaBridge 171:3a7713b1edbc 78 #define LL_PWR_CR2_CWUF1 PWR_CR2_CWUF1 /*!< Clear WKUP pin 1 */
AnnaBridge 171:3a7713b1edbc 79 /**
AnnaBridge 171:3a7713b1edbc 80 * @}
AnnaBridge 171:3a7713b1edbc 81 */
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 171:3a7713b1edbc 84 * @brief Flags defines which can be used with LL_PWR_ReadReg function
AnnaBridge 171:3a7713b1edbc 85 * @{
AnnaBridge 171:3a7713b1edbc 86 */
AnnaBridge 171:3a7713b1edbc 87 #define LL_PWR_CSR1_WUIF PWR_CSR1_WUIF /*!< Wakeup flag */
AnnaBridge 171:3a7713b1edbc 88 #define LL_PWR_CSR1_SBF PWR_CSR1_SBF /*!< Standby flag */
AnnaBridge 171:3a7713b1edbc 89 #define LL_PWR_CSR1_PVDO PWR_CSR1_PVDO /*!< Power voltage detector output flag */
AnnaBridge 171:3a7713b1edbc 90 #define LL_PWR_CSR1_BRR PWR_CSR1_BRR /*!< Backup Regulator ready flag */
AnnaBridge 171:3a7713b1edbc 91 #define LL_PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY /*!< Voltage scaling select flag */
AnnaBridge 171:3a7713b1edbc 92 #define LL_PWR_CSR1_ODRDY PWR_CSR1_ODRDY /*!< Over-drive mode ready */
AnnaBridge 171:3a7713b1edbc 93 #define LL_PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY /*!< Over-drive mode switching ready */
AnnaBridge 171:3a7713b1edbc 94 #define LL_PWR_CSR1_UDRDY PWR_CSR1_UDRDY /*!< Under-drive ready flag */
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 #define LL_PWR_CSR2_EWUP1 PWR_CSR2_EWUP1 /*!< Enable WKUP pin 1 */
AnnaBridge 171:3a7713b1edbc 97 #define LL_PWR_CSR2_EWUP2 PWR_CSR2_EWUP2 /*!< Enable WKUP pin 2 */
AnnaBridge 171:3a7713b1edbc 98 #define LL_PWR_CSR2_EWUP3 PWR_CSR2_EWUP3 /*!< Enable WKUP pin 3 */
AnnaBridge 171:3a7713b1edbc 99 #define LL_PWR_CSR2_EWUP4 PWR_CSR2_EWUP4 /*!< Enable WKUP pin 4 */
AnnaBridge 171:3a7713b1edbc 100 #define LL_PWR_CSR2_EWUP5 PWR_CSR2_EWUP5 /*!< Enable WKUP pin 5 */
AnnaBridge 171:3a7713b1edbc 101 #define LL_PWR_CSR2_EWUP6 PWR_CSR2_EWUP6 /*!< Enable WKUP pin 6 */
AnnaBridge 171:3a7713b1edbc 102 /**
AnnaBridge 171:3a7713b1edbc 103 * @}
AnnaBridge 171:3a7713b1edbc 104 */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
AnnaBridge 171:3a7713b1edbc 107 * @{
AnnaBridge 171:3a7713b1edbc 108 */
AnnaBridge 171:3a7713b1edbc 109 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode (with main Regulator ON) when the CPU enters deepsleep */
AnnaBridge 171:3a7713b1edbc 110 #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR1_MRUDS | PWR_CR1_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
AnnaBridge 171:3a7713b1edbc 111 #define LL_PWR_MODE_STOP_LPREGU PWR_CR1_LPDS /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
AnnaBridge 171:3a7713b1edbc 112 #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
AnnaBridge 171:3a7713b1edbc 113 #define LL_PWR_MODE_STANDBY PWR_CR1_PDDS /*!< Enter Standby mode when the CPU enters deepsleep */
AnnaBridge 171:3a7713b1edbc 114 /**
AnnaBridge 171:3a7713b1edbc 115 * @}
AnnaBridge 171:3a7713b1edbc 116 */
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
AnnaBridge 171:3a7713b1edbc 119 * @{
AnnaBridge 171:3a7713b1edbc 120 */
AnnaBridge 171:3a7713b1edbc 121 #define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_CR1_VOS_0
AnnaBridge 171:3a7713b1edbc 122 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1
AnnaBridge 171:3a7713b1edbc 123 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0 | PWR_CR1_VOS_1)
AnnaBridge 171:3a7713b1edbc 124 /**
AnnaBridge 171:3a7713b1edbc 125 * @}
AnnaBridge 171:3a7713b1edbc 126 */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
AnnaBridge 171:3a7713b1edbc 129 * @{
AnnaBridge 171:3a7713b1edbc 130 */
AnnaBridge 171:3a7713b1edbc 131 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
AnnaBridge 171:3a7713b1edbc 132 #define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */
AnnaBridge 171:3a7713b1edbc 133 /**
AnnaBridge 171:3a7713b1edbc 134 * @}
AnnaBridge 171:3a7713b1edbc 135 */
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
AnnaBridge 171:3a7713b1edbc 138 * @{
AnnaBridge 171:3a7713b1edbc 139 */
AnnaBridge 171:3a7713b1edbc 140 #define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 2.0 V */
AnnaBridge 171:3a7713b1edbc 141 #define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */
AnnaBridge 171:3a7713b1edbc 142 #define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.3 V */
AnnaBridge 171:3a7713b1edbc 143 #define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.5 V */
AnnaBridge 171:3a7713b1edbc 144 #define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.6 V */
AnnaBridge 171:3a7713b1edbc 145 #define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */
AnnaBridge 171:3a7713b1edbc 146 #define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.8 V */
AnnaBridge 171:3a7713b1edbc 147 #define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< Voltage threshold detected by PVD 2.9 V */
AnnaBridge 171:3a7713b1edbc 148 /**
AnnaBridge 171:3a7713b1edbc 149 * @}
AnnaBridge 171:3a7713b1edbc 150 */
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
AnnaBridge 171:3a7713b1edbc 153 * @{
AnnaBridge 171:3a7713b1edbc 154 */
AnnaBridge 171:3a7713b1edbc 155 #define LL_PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 /*!< WKUP pin 1 : PA0 */
AnnaBridge 171:3a7713b1edbc 156 #define LL_PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 /*!< WKUP pin 2 : PA2 */
AnnaBridge 171:3a7713b1edbc 157 #define LL_PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 /*!< WKUP pin 3 : PC1 */
AnnaBridge 171:3a7713b1edbc 158 #define LL_PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 /*!< WKUP pin 4 : PC13 */
AnnaBridge 171:3a7713b1edbc 159 #define LL_PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 /*!< WKUP pin 5 : PI8 */
AnnaBridge 171:3a7713b1edbc 160 #define LL_PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 /*!< WKUP pin 6 : PI11 */
AnnaBridge 171:3a7713b1edbc 161 /**
AnnaBridge 171:3a7713b1edbc 162 * @}
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 /**
AnnaBridge 171:3a7713b1edbc 166 * @}
AnnaBridge 171:3a7713b1edbc 167 */
AnnaBridge 171:3a7713b1edbc 168 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 169 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
AnnaBridge 171:3a7713b1edbc 170 * @{
AnnaBridge 171:3a7713b1edbc 171 */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
AnnaBridge 171:3a7713b1edbc 174 * @{
AnnaBridge 171:3a7713b1edbc 175 */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /**
AnnaBridge 171:3a7713b1edbc 178 * @brief Write a value in PWR register
AnnaBridge 171:3a7713b1edbc 179 * @param __REG__ Register to be written
AnnaBridge 171:3a7713b1edbc 180 * @param __VALUE__ Value to be written in the register
AnnaBridge 171:3a7713b1edbc 181 * @retval None
AnnaBridge 171:3a7713b1edbc 182 */
AnnaBridge 171:3a7713b1edbc 183 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 /**
AnnaBridge 171:3a7713b1edbc 186 * @brief Read a value in PWR register
AnnaBridge 171:3a7713b1edbc 187 * @param __REG__ Register to be read
AnnaBridge 171:3a7713b1edbc 188 * @retval Register value
AnnaBridge 171:3a7713b1edbc 189 */
AnnaBridge 171:3a7713b1edbc 190 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
AnnaBridge 171:3a7713b1edbc 191 /**
AnnaBridge 171:3a7713b1edbc 192 * @}
AnnaBridge 171:3a7713b1edbc 193 */
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 /**
AnnaBridge 171:3a7713b1edbc 196 * @}
AnnaBridge 171:3a7713b1edbc 197 */
AnnaBridge 171:3a7713b1edbc 198 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 199 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
AnnaBridge 171:3a7713b1edbc 200 * @{
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 /** @defgroup PWR_LL_EF_Configuration Configuration
AnnaBridge 171:3a7713b1edbc 204 * @{
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 /**
AnnaBridge 171:3a7713b1edbc 208 * @brief Enable Under Drive Mode
AnnaBridge 171:3a7713b1edbc 209 * @rmtoll CR1 UDEN LL_PWR_EnableUnderDriveMode
AnnaBridge 171:3a7713b1edbc 210 * @note This mode is enabled only with STOP low power mode.
AnnaBridge 171:3a7713b1edbc 211 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
AnnaBridge 171:3a7713b1edbc 212 * mode is only available when the main Regulator or the low power Regulator
AnnaBridge 171:3a7713b1edbc 213 * is in low voltage mode.
AnnaBridge 171:3a7713b1edbc 214 * @note If the Under-drive mode was enabled, it is automatically disabled after
AnnaBridge 171:3a7713b1edbc 215 * exiting Stop mode.
AnnaBridge 171:3a7713b1edbc 216 * When the voltage Regulator operates in Under-drive mode, an additional
AnnaBridge 171:3a7713b1edbc 217 * startup delay is induced when waking up from Stop mode.
AnnaBridge 171:3a7713b1edbc 218 * @retval None
AnnaBridge 171:3a7713b1edbc 219 */
AnnaBridge 171:3a7713b1edbc 220 __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
AnnaBridge 171:3a7713b1edbc 221 {
AnnaBridge 171:3a7713b1edbc 222 SET_BIT(PWR->CR1, PWR_CR1_UDEN);
AnnaBridge 171:3a7713b1edbc 223 }
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 /**
AnnaBridge 171:3a7713b1edbc 226 * @brief Disable Under Drive Mode
AnnaBridge 171:3a7713b1edbc 227 * @rmtoll CR1 UDEN LL_PWR_DisableUnderDriveMode
AnnaBridge 171:3a7713b1edbc 228 * @retval None
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230 __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
AnnaBridge 171:3a7713b1edbc 231 {
AnnaBridge 171:3a7713b1edbc 232 CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN);
AnnaBridge 171:3a7713b1edbc 233 }
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235 /**
AnnaBridge 171:3a7713b1edbc 236 * @brief Check if Under Drive Mode is enabled
AnnaBridge 171:3a7713b1edbc 237 * @rmtoll CR1 UDEN LL_PWR_IsEnabledUnderDriveMode
AnnaBridge 171:3a7713b1edbc 238 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 239 */
AnnaBridge 171:3a7713b1edbc 240 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
AnnaBridge 171:3a7713b1edbc 241 {
AnnaBridge 171:3a7713b1edbc 242 return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN));
AnnaBridge 171:3a7713b1edbc 243 }
AnnaBridge 171:3a7713b1edbc 244
AnnaBridge 171:3a7713b1edbc 245 /**
AnnaBridge 171:3a7713b1edbc 246 * @brief Enable Over drive switching
AnnaBridge 171:3a7713b1edbc 247 * @rmtoll CR1 ODSWEN LL_PWR_EnableOverDriveSwitching
AnnaBridge 171:3a7713b1edbc 248 * @retval None
AnnaBridge 171:3a7713b1edbc 249 */
AnnaBridge 171:3a7713b1edbc 250 __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
AnnaBridge 171:3a7713b1edbc 251 {
AnnaBridge 171:3a7713b1edbc 252 SET_BIT(PWR->CR1, PWR_CR1_ODSWEN);
AnnaBridge 171:3a7713b1edbc 253 }
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 /**
AnnaBridge 171:3a7713b1edbc 256 * @brief Disable Over drive switching
AnnaBridge 171:3a7713b1edbc 257 * @rmtoll CR1 ODSWEN LL_PWR_DisableOverDriveSwitching
AnnaBridge 171:3a7713b1edbc 258 * @retval None
AnnaBridge 171:3a7713b1edbc 259 */
AnnaBridge 171:3a7713b1edbc 260 __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
AnnaBridge 171:3a7713b1edbc 261 {
AnnaBridge 171:3a7713b1edbc 262 CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN);
AnnaBridge 171:3a7713b1edbc 263 }
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /**
AnnaBridge 171:3a7713b1edbc 266 * @brief Check if Over drive switching is enabled
AnnaBridge 171:3a7713b1edbc 267 * @rmtoll CR1 ODSWEN LL_PWR_IsEnabledOverDriveSwitching
AnnaBridge 171:3a7713b1edbc 268 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 269 */
AnnaBridge 171:3a7713b1edbc 270 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
AnnaBridge 171:3a7713b1edbc 271 {
AnnaBridge 171:3a7713b1edbc 272 return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN));
AnnaBridge 171:3a7713b1edbc 273 }
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 /**
AnnaBridge 171:3a7713b1edbc 276 * @brief Enable Over drive Mode
AnnaBridge 171:3a7713b1edbc 277 * @rmtoll CR1 ODEN LL_PWR_EnableOverDriveMode
AnnaBridge 171:3a7713b1edbc 278 * @retval None
AnnaBridge 171:3a7713b1edbc 279 */
AnnaBridge 171:3a7713b1edbc 280 __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
AnnaBridge 171:3a7713b1edbc 281 {
AnnaBridge 171:3a7713b1edbc 282 SET_BIT(PWR->CR1, PWR_CR1_ODEN);
AnnaBridge 171:3a7713b1edbc 283 }
AnnaBridge 171:3a7713b1edbc 284
AnnaBridge 171:3a7713b1edbc 285 /**
AnnaBridge 171:3a7713b1edbc 286 * @brief Disable Over drive Mode
AnnaBridge 171:3a7713b1edbc 287 * @rmtoll CR1 ODEN LL_PWR_DisableOverDriveMode
AnnaBridge 171:3a7713b1edbc 288 * @retval None
AnnaBridge 171:3a7713b1edbc 289 */
AnnaBridge 171:3a7713b1edbc 290 __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
AnnaBridge 171:3a7713b1edbc 291 {
AnnaBridge 171:3a7713b1edbc 292 CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN);
AnnaBridge 171:3a7713b1edbc 293 }
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /**
AnnaBridge 171:3a7713b1edbc 296 * @brief Check if Over drive switching is enabled
AnnaBridge 171:3a7713b1edbc 297 * @rmtoll CR1 ODEN LL_PWR_IsEnabledOverDriveMode
AnnaBridge 171:3a7713b1edbc 298 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
AnnaBridge 171:3a7713b1edbc 301 {
AnnaBridge 171:3a7713b1edbc 302 return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN));
AnnaBridge 171:3a7713b1edbc 303 }
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 /**
AnnaBridge 171:3a7713b1edbc 306 * @brief Set the main internal Regulator output voltage
AnnaBridge 171:3a7713b1edbc 307 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
AnnaBridge 171:3a7713b1edbc 308 * @param VoltageScaling This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 309 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
AnnaBridge 171:3a7713b1edbc 310 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
AnnaBridge 171:3a7713b1edbc 311 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
AnnaBridge 171:3a7713b1edbc 312 * @retval None
AnnaBridge 171:3a7713b1edbc 313 */
AnnaBridge 171:3a7713b1edbc 314 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
AnnaBridge 171:3a7713b1edbc 315 {
AnnaBridge 171:3a7713b1edbc 316 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
AnnaBridge 171:3a7713b1edbc 317 }
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 /**
AnnaBridge 171:3a7713b1edbc 320 * @brief Get the main internal Regulator output voltage
AnnaBridge 171:3a7713b1edbc 321 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
AnnaBridge 171:3a7713b1edbc 322 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 323 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
AnnaBridge 171:3a7713b1edbc 324 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
AnnaBridge 171:3a7713b1edbc 325 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
AnnaBridge 171:3a7713b1edbc 326 */
AnnaBridge 171:3a7713b1edbc 327 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
AnnaBridge 171:3a7713b1edbc 328 {
AnnaBridge 171:3a7713b1edbc 329 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
AnnaBridge 171:3a7713b1edbc 330 }
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 /**
AnnaBridge 171:3a7713b1edbc 333 * @brief Enable Main Regulator in deepsleep under-drive Mode
AnnaBridge 171:3a7713b1edbc 334 * @rmtoll CR1 MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
AnnaBridge 171:3a7713b1edbc 335 * @retval None
AnnaBridge 171:3a7713b1edbc 336 */
AnnaBridge 171:3a7713b1edbc 337 __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
AnnaBridge 171:3a7713b1edbc 338 {
AnnaBridge 171:3a7713b1edbc 339 SET_BIT(PWR->CR1, PWR_CR1_MRUDS);
AnnaBridge 171:3a7713b1edbc 340 }
AnnaBridge 171:3a7713b1edbc 341
AnnaBridge 171:3a7713b1edbc 342 /**
AnnaBridge 171:3a7713b1edbc 343 * @brief Disable Main Regulator in deepsleep under-drive Mode
AnnaBridge 171:3a7713b1edbc 344 * @rmtoll CR1 MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
AnnaBridge 171:3a7713b1edbc 345 * @retval None
AnnaBridge 171:3a7713b1edbc 346 */
AnnaBridge 171:3a7713b1edbc 347 __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
AnnaBridge 171:3a7713b1edbc 348 {
AnnaBridge 171:3a7713b1edbc 349 CLEAR_BIT(PWR->CR1, PWR_CR1_MRUDS);
AnnaBridge 171:3a7713b1edbc 350 }
AnnaBridge 171:3a7713b1edbc 351
AnnaBridge 171:3a7713b1edbc 352 /**
AnnaBridge 171:3a7713b1edbc 353 * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
AnnaBridge 171:3a7713b1edbc 354 * @rmtoll CR1 MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
AnnaBridge 171:3a7713b1edbc 355 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 356 */
AnnaBridge 171:3a7713b1edbc 357 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
AnnaBridge 171:3a7713b1edbc 358 {
AnnaBridge 171:3a7713b1edbc 359 return (READ_BIT(PWR->CR1, PWR_CR1_MRUDS) == (PWR_CR1_MRUDS));
AnnaBridge 171:3a7713b1edbc 360 }
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 /**
AnnaBridge 171:3a7713b1edbc 363 * @brief Enable Low Power Regulator in deepsleep under-drive Mode
AnnaBridge 171:3a7713b1edbc 364 * @rmtoll CR1 LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
AnnaBridge 171:3a7713b1edbc 365 * @retval None
AnnaBridge 171:3a7713b1edbc 366 */
AnnaBridge 171:3a7713b1edbc 367 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
AnnaBridge 171:3a7713b1edbc 368 {
AnnaBridge 171:3a7713b1edbc 369 SET_BIT(PWR->CR1, PWR_CR1_LPUDS);
AnnaBridge 171:3a7713b1edbc 370 }
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372 /**
AnnaBridge 171:3a7713b1edbc 373 * @brief Disable Low Power Regulator in deepsleep under-drive Mode
AnnaBridge 171:3a7713b1edbc 374 * @rmtoll CR1 LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
AnnaBridge 171:3a7713b1edbc 375 * @retval None
AnnaBridge 171:3a7713b1edbc 376 */
AnnaBridge 171:3a7713b1edbc 377 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
AnnaBridge 171:3a7713b1edbc 378 {
AnnaBridge 171:3a7713b1edbc 379 CLEAR_BIT(PWR->CR1, PWR_CR1_LPUDS);
AnnaBridge 171:3a7713b1edbc 380 }
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 /**
AnnaBridge 171:3a7713b1edbc 383 * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
AnnaBridge 171:3a7713b1edbc 384 * @rmtoll CR1 LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
AnnaBridge 171:3a7713b1edbc 385 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 386 */
AnnaBridge 171:3a7713b1edbc 387 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
AnnaBridge 171:3a7713b1edbc 388 {
AnnaBridge 171:3a7713b1edbc 389 return (READ_BIT(PWR->CR1, PWR_CR1_LPUDS) == (PWR_CR1_LPUDS));
AnnaBridge 171:3a7713b1edbc 390 }
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 /**
AnnaBridge 171:3a7713b1edbc 393 * @brief Enable the Flash Power Down in Stop Mode
AnnaBridge 171:3a7713b1edbc 394 * @rmtoll CR1 FPDS LL_PWR_EnableFlashPowerDown
AnnaBridge 171:3a7713b1edbc 395 * @retval None
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
AnnaBridge 171:3a7713b1edbc 398 {
AnnaBridge 171:3a7713b1edbc 399 SET_BIT(PWR->CR1, PWR_CR1_FPDS);
AnnaBridge 171:3a7713b1edbc 400 }
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 /**
AnnaBridge 171:3a7713b1edbc 403 * @brief Disable the Flash Power Down in Stop Mode
AnnaBridge 171:3a7713b1edbc 404 * @rmtoll CR1 FPDS LL_PWR_DisableFlashPowerDown
AnnaBridge 171:3a7713b1edbc 405 * @retval None
AnnaBridge 171:3a7713b1edbc 406 */
AnnaBridge 171:3a7713b1edbc 407 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
AnnaBridge 171:3a7713b1edbc 408 {
AnnaBridge 171:3a7713b1edbc 409 CLEAR_BIT(PWR->CR1, PWR_CR1_FPDS);
AnnaBridge 171:3a7713b1edbc 410 }
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 /**
AnnaBridge 171:3a7713b1edbc 413 * @brief Check if the Flash Power Down in Stop Mode is enabled
AnnaBridge 171:3a7713b1edbc 414 * @rmtoll CR1 FPDS LL_PWR_IsEnabledFlashPowerDown
AnnaBridge 171:3a7713b1edbc 415 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 416 */
AnnaBridge 171:3a7713b1edbc 417 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
AnnaBridge 171:3a7713b1edbc 418 {
AnnaBridge 171:3a7713b1edbc 419 return (READ_BIT(PWR->CR1, PWR_CR1_FPDS) == (PWR_CR1_FPDS));
AnnaBridge 171:3a7713b1edbc 420 }
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 /**
AnnaBridge 171:3a7713b1edbc 423 * @brief Enable access to the backup domain
AnnaBridge 171:3a7713b1edbc 424 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
AnnaBridge 171:3a7713b1edbc 425 * @retval None
AnnaBridge 171:3a7713b1edbc 426 */
AnnaBridge 171:3a7713b1edbc 427 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
AnnaBridge 171:3a7713b1edbc 428 {
AnnaBridge 171:3a7713b1edbc 429 SET_BIT(PWR->CR1, PWR_CR1_DBP);
AnnaBridge 171:3a7713b1edbc 430 }
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 /**
AnnaBridge 171:3a7713b1edbc 433 * @brief Disable access to the backup domain
AnnaBridge 171:3a7713b1edbc 434 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
AnnaBridge 171:3a7713b1edbc 435 * @retval None
AnnaBridge 171:3a7713b1edbc 436 */
AnnaBridge 171:3a7713b1edbc 437 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
AnnaBridge 171:3a7713b1edbc 438 {
AnnaBridge 171:3a7713b1edbc 439 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
AnnaBridge 171:3a7713b1edbc 440 }
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 /**
AnnaBridge 171:3a7713b1edbc 443 * @brief Check if the backup domain is enabled
AnnaBridge 171:3a7713b1edbc 444 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
AnnaBridge 171:3a7713b1edbc 445 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 446 */
AnnaBridge 171:3a7713b1edbc 447 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
AnnaBridge 171:3a7713b1edbc 448 {
AnnaBridge 171:3a7713b1edbc 449 return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));
AnnaBridge 171:3a7713b1edbc 450 }
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 /**
AnnaBridge 171:3a7713b1edbc 453 * @brief Enable Backup Regulator
AnnaBridge 171:3a7713b1edbc 454 * @rmtoll CSR1 BRE LL_PWR_EnableBkUpRegulator
AnnaBridge 171:3a7713b1edbc 455 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
AnnaBridge 171:3a7713b1edbc 456 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
AnnaBridge 171:3a7713b1edbc 457 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
AnnaBridge 171:3a7713b1edbc 458 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
AnnaBridge 171:3a7713b1edbc 459 * the data written into the RAM will be maintained in the Standby and VBAT modes.
AnnaBridge 171:3a7713b1edbc 460 * @retval None
AnnaBridge 171:3a7713b1edbc 461 */
AnnaBridge 171:3a7713b1edbc 462 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
AnnaBridge 171:3a7713b1edbc 463 {
AnnaBridge 171:3a7713b1edbc 464 SET_BIT(PWR->CSR1, PWR_CSR1_BRE);
AnnaBridge 171:3a7713b1edbc 465 }
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 /**
AnnaBridge 171:3a7713b1edbc 468 * @brief Disable Backup Regulator
AnnaBridge 171:3a7713b1edbc 469 * @rmtoll CSR1 BRE LL_PWR_DisableBkUpRegulator
AnnaBridge 171:3a7713b1edbc 470 * @retval None
AnnaBridge 171:3a7713b1edbc 471 */
AnnaBridge 171:3a7713b1edbc 472 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
AnnaBridge 171:3a7713b1edbc 473 {
AnnaBridge 171:3a7713b1edbc 474 CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE);
AnnaBridge 171:3a7713b1edbc 475 }
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /**
AnnaBridge 171:3a7713b1edbc 478 * @brief Check if the backup Regulator is enabled
AnnaBridge 171:3a7713b1edbc 479 * @rmtoll CSR1 BRE LL_PWR_IsEnabledBkUpRegulator
AnnaBridge 171:3a7713b1edbc 480 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 481 */
AnnaBridge 171:3a7713b1edbc 482 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
AnnaBridge 171:3a7713b1edbc 483 {
AnnaBridge 171:3a7713b1edbc 484 return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE));
AnnaBridge 171:3a7713b1edbc 485 }
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /**
AnnaBridge 171:3a7713b1edbc 488 * @brief Set voltage Regulator mode during deep sleep mode
AnnaBridge 171:3a7713b1edbc 489 * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS
AnnaBridge 171:3a7713b1edbc 490 * @param RegulMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 491 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
AnnaBridge 171:3a7713b1edbc 492 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
AnnaBridge 171:3a7713b1edbc 493 * @retval None
AnnaBridge 171:3a7713b1edbc 494 */
AnnaBridge 171:3a7713b1edbc 495 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
AnnaBridge 171:3a7713b1edbc 496 {
AnnaBridge 171:3a7713b1edbc 497 MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
AnnaBridge 171:3a7713b1edbc 498 }
AnnaBridge 171:3a7713b1edbc 499
AnnaBridge 171:3a7713b1edbc 500 /**
AnnaBridge 171:3a7713b1edbc 501 * @brief Get voltage Regulator mode during deep sleep mode
AnnaBridge 171:3a7713b1edbc 502 * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS
AnnaBridge 171:3a7713b1edbc 503 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 504 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
AnnaBridge 171:3a7713b1edbc 505 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
AnnaBridge 171:3a7713b1edbc 506 */
AnnaBridge 171:3a7713b1edbc 507 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
AnnaBridge 171:3a7713b1edbc 508 {
AnnaBridge 171:3a7713b1edbc 509 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
AnnaBridge 171:3a7713b1edbc 510 }
AnnaBridge 171:3a7713b1edbc 511
AnnaBridge 171:3a7713b1edbc 512 /**
AnnaBridge 171:3a7713b1edbc 513 * @brief Set Power Down mode when CPU enters deepsleep
AnnaBridge 171:3a7713b1edbc 514 * @rmtoll CR1 PDDS LL_PWR_SetPowerMode\n
AnnaBridge 171:3a7713b1edbc 515 * CR1 LPDS LL_PWR_SetPowerMode\n
AnnaBridge 171:3a7713b1edbc 516 * CR1 FPDS LL_PWR_SetPowerMode\n
AnnaBridge 171:3a7713b1edbc 517 * CR1 LPUDS LL_PWR_SetPowerMode\n
AnnaBridge 171:3a7713b1edbc 518 * CR1 MRUDS LL_PWR_SetPowerMode
AnnaBridge 171:3a7713b1edbc 519 * @param PDMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 520 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
AnnaBridge 171:3a7713b1edbc 521 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE
AnnaBridge 171:3a7713b1edbc 522 * @arg @ref LL_PWR_MODE_STOP_LPREGU
AnnaBridge 171:3a7713b1edbc 523 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE
AnnaBridge 171:3a7713b1edbc 524 * @arg @ref LL_PWR_MODE_STANDBY
AnnaBridge 171:3a7713b1edbc 525 * @retval None
AnnaBridge 171:3a7713b1edbc 526 */
AnnaBridge 171:3a7713b1edbc 527 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
AnnaBridge 171:3a7713b1edbc 528 {
AnnaBridge 171:3a7713b1edbc 529 MODIFY_REG(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS), PDMode);
AnnaBridge 171:3a7713b1edbc 530 }
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /**
AnnaBridge 171:3a7713b1edbc 533 * @brief Get Power Down mode when CPU enters deepsleep
AnnaBridge 171:3a7713b1edbc 534 * @rmtoll CR1 PDDS LL_PWR_GetPowerMode\n
AnnaBridge 171:3a7713b1edbc 535 * CR1 LPDS LL_PWR_GetPowerMode\n
AnnaBridge 171:3a7713b1edbc 536 * CR1 FPDS LL_PWR_GetPowerMode\n
AnnaBridge 171:3a7713b1edbc 537 * CR1 LPUDS LL_PWR_GetPowerMode\n
AnnaBridge 171:3a7713b1edbc 538 * CR1 MRUDS LL_PWR_GetPowerMode
AnnaBridge 171:3a7713b1edbc 539 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 540 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
AnnaBridge 171:3a7713b1edbc 541 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE
AnnaBridge 171:3a7713b1edbc 542 * @arg @ref LL_PWR_MODE_STOP_LPREGU
AnnaBridge 171:3a7713b1edbc 543 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE
AnnaBridge 171:3a7713b1edbc 544 * @arg @ref LL_PWR_MODE_STANDBY
AnnaBridge 171:3a7713b1edbc 545 */
AnnaBridge 171:3a7713b1edbc 546 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
AnnaBridge 171:3a7713b1edbc 547 {
AnnaBridge 171:3a7713b1edbc 548 return (uint32_t)(READ_BIT(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS)));
AnnaBridge 171:3a7713b1edbc 549 }
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 /**
AnnaBridge 171:3a7713b1edbc 552 * @brief Configure the voltage threshold detected by the Power Voltage Detector
AnnaBridge 171:3a7713b1edbc 553 * @rmtoll CR1 PLS LL_PWR_SetPVDLevel
AnnaBridge 171:3a7713b1edbc 554 * @param PVDLevel This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 555 * @arg @ref LL_PWR_PVDLEVEL_0
AnnaBridge 171:3a7713b1edbc 556 * @arg @ref LL_PWR_PVDLEVEL_1
AnnaBridge 171:3a7713b1edbc 557 * @arg @ref LL_PWR_PVDLEVEL_2
AnnaBridge 171:3a7713b1edbc 558 * @arg @ref LL_PWR_PVDLEVEL_3
AnnaBridge 171:3a7713b1edbc 559 * @arg @ref LL_PWR_PVDLEVEL_4
AnnaBridge 171:3a7713b1edbc 560 * @arg @ref LL_PWR_PVDLEVEL_5
AnnaBridge 171:3a7713b1edbc 561 * @arg @ref LL_PWR_PVDLEVEL_6
AnnaBridge 171:3a7713b1edbc 562 * @arg @ref LL_PWR_PVDLEVEL_7
AnnaBridge 171:3a7713b1edbc 563 * @retval None
AnnaBridge 171:3a7713b1edbc 564 */
AnnaBridge 171:3a7713b1edbc 565 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
AnnaBridge 171:3a7713b1edbc 566 {
AnnaBridge 171:3a7713b1edbc 567 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
AnnaBridge 171:3a7713b1edbc 568 }
AnnaBridge 171:3a7713b1edbc 569
AnnaBridge 171:3a7713b1edbc 570 /**
AnnaBridge 171:3a7713b1edbc 571 * @brief Get the voltage threshold detection
AnnaBridge 171:3a7713b1edbc 572 * @rmtoll CR1 PLS LL_PWR_GetPVDLevel
AnnaBridge 171:3a7713b1edbc 573 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 574 * @arg @ref LL_PWR_PVDLEVEL_0
AnnaBridge 171:3a7713b1edbc 575 * @arg @ref LL_PWR_PVDLEVEL_1
AnnaBridge 171:3a7713b1edbc 576 * @arg @ref LL_PWR_PVDLEVEL_2
AnnaBridge 171:3a7713b1edbc 577 * @arg @ref LL_PWR_PVDLEVEL_3
AnnaBridge 171:3a7713b1edbc 578 * @arg @ref LL_PWR_PVDLEVEL_4
AnnaBridge 171:3a7713b1edbc 579 * @arg @ref LL_PWR_PVDLEVEL_5
AnnaBridge 171:3a7713b1edbc 580 * @arg @ref LL_PWR_PVDLEVEL_6
AnnaBridge 171:3a7713b1edbc 581 * @arg @ref LL_PWR_PVDLEVEL_7
AnnaBridge 171:3a7713b1edbc 582 */
AnnaBridge 171:3a7713b1edbc 583 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
AnnaBridge 171:3a7713b1edbc 584 {
AnnaBridge 171:3a7713b1edbc 585 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
AnnaBridge 171:3a7713b1edbc 586 }
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 /**
AnnaBridge 171:3a7713b1edbc 589 * @brief Enable Power Voltage Detector
AnnaBridge 171:3a7713b1edbc 590 * @rmtoll CR1 PVDE LL_PWR_EnablePVD
AnnaBridge 171:3a7713b1edbc 591 * @retval None
AnnaBridge 171:3a7713b1edbc 592 */
AnnaBridge 171:3a7713b1edbc 593 __STATIC_INLINE void LL_PWR_EnablePVD(void)
AnnaBridge 171:3a7713b1edbc 594 {
AnnaBridge 171:3a7713b1edbc 595 SET_BIT(PWR->CR1, PWR_CR1_PVDE);
AnnaBridge 171:3a7713b1edbc 596 }
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 /**
AnnaBridge 171:3a7713b1edbc 599 * @brief Disable Power Voltage Detector
AnnaBridge 171:3a7713b1edbc 600 * @rmtoll CR1 PVDE LL_PWR_DisablePVD
AnnaBridge 171:3a7713b1edbc 601 * @retval None
AnnaBridge 171:3a7713b1edbc 602 */
AnnaBridge 171:3a7713b1edbc 603 __STATIC_INLINE void LL_PWR_DisablePVD(void)
AnnaBridge 171:3a7713b1edbc 604 {
AnnaBridge 171:3a7713b1edbc 605 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
AnnaBridge 171:3a7713b1edbc 606 }
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 /**
AnnaBridge 171:3a7713b1edbc 609 * @brief Check if Power Voltage Detector is enabled
AnnaBridge 171:3a7713b1edbc 610 * @rmtoll CR1 PVDE LL_PWR_IsEnabledPVD
AnnaBridge 171:3a7713b1edbc 611 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 612 */
AnnaBridge 171:3a7713b1edbc 613 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
AnnaBridge 171:3a7713b1edbc 614 {
AnnaBridge 171:3a7713b1edbc 615 return (READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE));
AnnaBridge 171:3a7713b1edbc 616 }
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 /**
AnnaBridge 171:3a7713b1edbc 619 * @brief Enable the WakeUp PINx functionality
AnnaBridge 171:3a7713b1edbc 620 * @rmtoll CSR2 EWUP1 LL_PWR_EnableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 621 * CSR2 EWUP2 LL_PWR_EnableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 622 * CSR2 EWUP3 LL_PWR_EnableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 623 * CSR2 EWUP4 LL_PWR_EnableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 624 * CSR2 EWUP5 LL_PWR_EnableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 625 * CSR2 EWUP6 LL_PWR_EnableWakeUpPin
AnnaBridge 171:3a7713b1edbc 626 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 627 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 628 * @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge 171:3a7713b1edbc 629 * @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge 171:3a7713b1edbc 630 * @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge 171:3a7713b1edbc 631 * @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge 171:3a7713b1edbc 632 * @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge 171:3a7713b1edbc 633 * @retval None
AnnaBridge 171:3a7713b1edbc 634 */
AnnaBridge 171:3a7713b1edbc 635 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 636 {
AnnaBridge 171:3a7713b1edbc 637 SET_BIT(PWR->CSR2, WakeUpPin);
AnnaBridge 171:3a7713b1edbc 638 }
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 /**
AnnaBridge 171:3a7713b1edbc 641 * @brief Disable the WakeUp PINx functionality
AnnaBridge 171:3a7713b1edbc 642 * @rmtoll CSR2 EWUP1 LL_PWR_DisableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 643 * CSR2 EWUP2 LL_PWR_DisableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 644 * CSR2 EWUP3 LL_PWR_DisableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 645 * CSR2 EWUP4 LL_PWR_DisableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 646 * CSR2 EWUP5 LL_PWR_DisableWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 647 * CSR2 EWUP6 LL_PWR_DisableWakeUpPin
AnnaBridge 171:3a7713b1edbc 648 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 649 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 650 * @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge 171:3a7713b1edbc 651 * @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge 171:3a7713b1edbc 652 * @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge 171:3a7713b1edbc 653 * @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge 171:3a7713b1edbc 654 * @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge 171:3a7713b1edbc 655 * @retval None
AnnaBridge 171:3a7713b1edbc 656 */
AnnaBridge 171:3a7713b1edbc 657 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 658 {
AnnaBridge 171:3a7713b1edbc 659 CLEAR_BIT(PWR->CSR2, WakeUpPin);
AnnaBridge 171:3a7713b1edbc 660 }
AnnaBridge 171:3a7713b1edbc 661
AnnaBridge 171:3a7713b1edbc 662 /**
AnnaBridge 171:3a7713b1edbc 663 * @brief Check if the WakeUp PINx functionality is enabled
AnnaBridge 171:3a7713b1edbc 664 * @rmtoll CSR2 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 665 * CSR2 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 666 * CSR2 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 667 * CSR2 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 668 * CSR2 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge 171:3a7713b1edbc 669 * CSR2 EWUP6 LL_PWR_IsEnabledWakeUpPin
AnnaBridge 171:3a7713b1edbc 670 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 671 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 672 * @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge 171:3a7713b1edbc 673 * @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge 171:3a7713b1edbc 674 * @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge 171:3a7713b1edbc 675 * @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge 171:3a7713b1edbc 676 * @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge 171:3a7713b1edbc 677 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 678 */
AnnaBridge 171:3a7713b1edbc 679 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 680 {
AnnaBridge 171:3a7713b1edbc 681 return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin));
AnnaBridge 171:3a7713b1edbc 682 }
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 /**
AnnaBridge 171:3a7713b1edbc 685 * @brief Set the Wake-Up pin polarity low for the event detection
AnnaBridge 171:3a7713b1edbc 686 * @rmtoll CR2 WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 687 * CR2 WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 688 * CR2 WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 689 * CR2 WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 690 * CR2 WUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 691 * CR2 WUPP6 LL_PWR_SetWakeUpPinPolarityLow
AnnaBridge 171:3a7713b1edbc 692 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 693 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 694 * @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge 171:3a7713b1edbc 695 * @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge 171:3a7713b1edbc 696 * @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge 171:3a7713b1edbc 697 * @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge 171:3a7713b1edbc 698 * @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge 171:3a7713b1edbc 699 * @retval None
AnnaBridge 171:3a7713b1edbc 700 */
AnnaBridge 171:3a7713b1edbc 701 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 702 {
AnnaBridge 171:3a7713b1edbc 703 SET_BIT(PWR->CR2, WakeUpPin);
AnnaBridge 171:3a7713b1edbc 704 }
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 /**
AnnaBridge 171:3a7713b1edbc 707 * @brief Set the Wake-Up pin polarity high for the event detection
AnnaBridge 171:3a7713b1edbc 708 * @rmtoll CR2 WUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge 171:3a7713b1edbc 709 * CR2 WUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge 171:3a7713b1edbc 710 * CR2 WUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge 171:3a7713b1edbc 711 * CR2 WUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge 171:3a7713b1edbc 712 * CR2 WUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge 171:3a7713b1edbc 713 * CR2 WUPP6 LL_PWR_SetWakeUpPinPolarityHigh
AnnaBridge 171:3a7713b1edbc 714 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 715 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 716 * @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge 171:3a7713b1edbc 717 * @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge 171:3a7713b1edbc 718 * @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge 171:3a7713b1edbc 719 * @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge 171:3a7713b1edbc 720 * @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge 171:3a7713b1edbc 721 * @retval None
AnnaBridge 171:3a7713b1edbc 722 */
AnnaBridge 171:3a7713b1edbc 723 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 724 {
AnnaBridge 171:3a7713b1edbc 725 CLEAR_BIT(PWR->CR2, WakeUpPin);
AnnaBridge 171:3a7713b1edbc 726 }
AnnaBridge 171:3a7713b1edbc 727
AnnaBridge 171:3a7713b1edbc 728 /**
AnnaBridge 171:3a7713b1edbc 729 * @brief Get the Wake-Up pin polarity for the event detection
AnnaBridge 171:3a7713b1edbc 730 * @rmtoll CR2 WUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 731 * CR2 WUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 732 * CR2 WUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 733 * CR2 WUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 734 * CR2 WUPP5 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge 171:3a7713b1edbc 735 * CR2 WUPP6 LL_PWR_IsWakeUpPinPolarityLow
AnnaBridge 171:3a7713b1edbc 736 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 737 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 738 * @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge 171:3a7713b1edbc 739 * @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge 171:3a7713b1edbc 740 * @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge 171:3a7713b1edbc 741 * @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge 171:3a7713b1edbc 742 * @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge 171:3a7713b1edbc 743 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 744 */
AnnaBridge 171:3a7713b1edbc 745 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 746 {
AnnaBridge 171:3a7713b1edbc 747 return (READ_BIT(PWR->CR2, WakeUpPin) == (WakeUpPin));
AnnaBridge 171:3a7713b1edbc 748 }
AnnaBridge 171:3a7713b1edbc 749
AnnaBridge 171:3a7713b1edbc 750 /**
AnnaBridge 171:3a7713b1edbc 751 * @brief Enable Internal WakeUp
AnnaBridge 171:3a7713b1edbc 752 * @rmtoll CSR1 EIWUP LL_PWR_EnableInternalWakeUp
AnnaBridge 171:3a7713b1edbc 753 * @note This API must be used when RTC events (Alarm A or Alarm B, RTC Tamper, RTC TimeStamp
AnnaBridge 171:3a7713b1edbc 754 * or RTC Wakeup time) are used to wake up the system from Standby mode.
AnnaBridge 171:3a7713b1edbc 755 * @retval None
AnnaBridge 171:3a7713b1edbc 756 */
AnnaBridge 171:3a7713b1edbc 757 __STATIC_INLINE void LL_PWR_EnableInternalWakeUp(void)
AnnaBridge 171:3a7713b1edbc 758 {
AnnaBridge 171:3a7713b1edbc 759 SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP);
AnnaBridge 171:3a7713b1edbc 760 }
AnnaBridge 171:3a7713b1edbc 761
AnnaBridge 171:3a7713b1edbc 762 /**
AnnaBridge 171:3a7713b1edbc 763 * @brief Disable Internal WakeUp
AnnaBridge 171:3a7713b1edbc 764 * @rmtoll CSR1 EIWUP LL_PWR_DisableInternalWakeUp
AnnaBridge 171:3a7713b1edbc 765 * @retval None
AnnaBridge 171:3a7713b1edbc 766 */
AnnaBridge 171:3a7713b1edbc 767 __STATIC_INLINE void LL_PWR_DisableInternalWakeUp(void)
AnnaBridge 171:3a7713b1edbc 768 {
AnnaBridge 171:3a7713b1edbc 769 CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP);
AnnaBridge 171:3a7713b1edbc 770 }
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772 /**
AnnaBridge 171:3a7713b1edbc 773 * @brief Check if the Internal WakeUp functionality is enabled
AnnaBridge 171:3a7713b1edbc 774 * @rmtoll CSR1 EIWUP LL_PWR_IsEnabledInternalWakeUp
AnnaBridge 171:3a7713b1edbc 775 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 776 */
AnnaBridge 171:3a7713b1edbc 777 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternalWakeUp(void)
AnnaBridge 171:3a7713b1edbc 778 {
AnnaBridge 171:3a7713b1edbc 779 return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP));
AnnaBridge 171:3a7713b1edbc 780 }
AnnaBridge 171:3a7713b1edbc 781
AnnaBridge 171:3a7713b1edbc 782 /**
AnnaBridge 171:3a7713b1edbc 783 * @}
AnnaBridge 171:3a7713b1edbc 784 */
AnnaBridge 171:3a7713b1edbc 785
AnnaBridge 171:3a7713b1edbc 786 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 171:3a7713b1edbc 787 * @{
AnnaBridge 171:3a7713b1edbc 788 */
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 /**
AnnaBridge 171:3a7713b1edbc 791 * @brief Get Wake-up Flag 6
AnnaBridge 171:3a7713b1edbc 792 * @rmtoll CSR2 WUPF6 LL_PWR_IsActiveFlag_WU6
AnnaBridge 171:3a7713b1edbc 793 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 794 */
AnnaBridge 171:3a7713b1edbc 795 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
AnnaBridge 171:3a7713b1edbc 796 {
AnnaBridge 171:3a7713b1edbc 797 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6));
AnnaBridge 171:3a7713b1edbc 798 }
AnnaBridge 171:3a7713b1edbc 799
AnnaBridge 171:3a7713b1edbc 800 /**
AnnaBridge 171:3a7713b1edbc 801 * @brief Get Wake-up Flag 5
AnnaBridge 171:3a7713b1edbc 802 * @rmtoll CSR2 WUPF5 LL_PWR_IsActiveFlag_WU5
AnnaBridge 171:3a7713b1edbc 803 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 804 */
AnnaBridge 171:3a7713b1edbc 805 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
AnnaBridge 171:3a7713b1edbc 806 {
AnnaBridge 171:3a7713b1edbc 807 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5));
AnnaBridge 171:3a7713b1edbc 808 }
AnnaBridge 171:3a7713b1edbc 809
AnnaBridge 171:3a7713b1edbc 810 /**
AnnaBridge 171:3a7713b1edbc 811 * @brief Get Wake-up Flag 4
AnnaBridge 171:3a7713b1edbc 812 * @rmtoll CSR2 WUPF4 LL_PWR_IsActiveFlag_WU4
AnnaBridge 171:3a7713b1edbc 813 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 814 */
AnnaBridge 171:3a7713b1edbc 815 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
AnnaBridge 171:3a7713b1edbc 816 {
AnnaBridge 171:3a7713b1edbc 817 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4));
AnnaBridge 171:3a7713b1edbc 818 }
AnnaBridge 171:3a7713b1edbc 819
AnnaBridge 171:3a7713b1edbc 820 /**
AnnaBridge 171:3a7713b1edbc 821 * @brief Get Wake-up Flag 3
AnnaBridge 171:3a7713b1edbc 822 * @rmtoll CSR2 WUPF3 LL_PWR_IsActiveFlag_WU3
AnnaBridge 171:3a7713b1edbc 823 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 824 */
AnnaBridge 171:3a7713b1edbc 825 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
AnnaBridge 171:3a7713b1edbc 826 {
AnnaBridge 171:3a7713b1edbc 827 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3));
AnnaBridge 171:3a7713b1edbc 828 }
AnnaBridge 171:3a7713b1edbc 829
AnnaBridge 171:3a7713b1edbc 830 /**
AnnaBridge 171:3a7713b1edbc 831 * @brief Get Wake-up Flag 2
AnnaBridge 171:3a7713b1edbc 832 * @rmtoll CSR2 WUPF2 LL_PWR_IsActiveFlag_WU2
AnnaBridge 171:3a7713b1edbc 833 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 834 */
AnnaBridge 171:3a7713b1edbc 835 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
AnnaBridge 171:3a7713b1edbc 836 {
AnnaBridge 171:3a7713b1edbc 837 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2));
AnnaBridge 171:3a7713b1edbc 838 }
AnnaBridge 171:3a7713b1edbc 839
AnnaBridge 171:3a7713b1edbc 840 /**
AnnaBridge 171:3a7713b1edbc 841 * @brief Get Wake-up Flag 1
AnnaBridge 171:3a7713b1edbc 842 * @rmtoll CSR2 WUPF1 LL_PWR_IsActiveFlag_WU1
AnnaBridge 171:3a7713b1edbc 843 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 844 */
AnnaBridge 171:3a7713b1edbc 845 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
AnnaBridge 171:3a7713b1edbc 846 {
AnnaBridge 171:3a7713b1edbc 847 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1));
AnnaBridge 171:3a7713b1edbc 848 }
AnnaBridge 171:3a7713b1edbc 849
AnnaBridge 171:3a7713b1edbc 850 /**
AnnaBridge 171:3a7713b1edbc 851 * @brief Get Standby Flag
AnnaBridge 171:3a7713b1edbc 852 * @rmtoll CSR1 SBF LL_PWR_IsActiveFlag_SB
AnnaBridge 171:3a7713b1edbc 853 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 854 */
AnnaBridge 171:3a7713b1edbc 855 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
AnnaBridge 171:3a7713b1edbc 856 {
AnnaBridge 171:3a7713b1edbc 857 return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF));
AnnaBridge 171:3a7713b1edbc 858 }
AnnaBridge 171:3a7713b1edbc 859
AnnaBridge 171:3a7713b1edbc 860 /**
AnnaBridge 171:3a7713b1edbc 861 * @brief Indicate whether VDD voltage is below the selected PVD threshold
AnnaBridge 171:3a7713b1edbc 862 * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO
AnnaBridge 171:3a7713b1edbc 863 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 864 */
AnnaBridge 171:3a7713b1edbc 865 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
AnnaBridge 171:3a7713b1edbc 866 {
AnnaBridge 171:3a7713b1edbc 867 return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO));
AnnaBridge 171:3a7713b1edbc 868 }
AnnaBridge 171:3a7713b1edbc 869
AnnaBridge 171:3a7713b1edbc 870 /**
AnnaBridge 171:3a7713b1edbc 871 * @brief Get Backup Regulator ready Flag
AnnaBridge 171:3a7713b1edbc 872 * @rmtoll CSR1 BRR LL_PWR_IsActiveFlag_BRR
AnnaBridge 171:3a7713b1edbc 873 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 874 */
AnnaBridge 171:3a7713b1edbc 875 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
AnnaBridge 171:3a7713b1edbc 876 {
AnnaBridge 171:3a7713b1edbc 877 return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR));
AnnaBridge 171:3a7713b1edbc 878 }
AnnaBridge 171:3a7713b1edbc 879
AnnaBridge 171:3a7713b1edbc 880 /**
AnnaBridge 171:3a7713b1edbc 881 * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
AnnaBridge 171:3a7713b1edbc 882 * @rmtoll CSR1 VOSRDY LL_PWR_IsActiveFlag_VOS
AnnaBridge 171:3a7713b1edbc 883 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 884 */
AnnaBridge 171:3a7713b1edbc 885 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
AnnaBridge 171:3a7713b1edbc 886 {
AnnaBridge 171:3a7713b1edbc 887 return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY));
AnnaBridge 171:3a7713b1edbc 888 }
AnnaBridge 171:3a7713b1edbc 889
AnnaBridge 171:3a7713b1edbc 890 /**
AnnaBridge 171:3a7713b1edbc 891 * @brief Indicate whether the Over-Drive mode is ready or not
AnnaBridge 171:3a7713b1edbc 892 * @rmtoll CSR1 ODRDY LL_PWR_IsActiveFlag_OD
AnnaBridge 171:3a7713b1edbc 893 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 894 */
AnnaBridge 171:3a7713b1edbc 895 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
AnnaBridge 171:3a7713b1edbc 896 {
AnnaBridge 171:3a7713b1edbc 897 return (READ_BIT(PWR->CSR1, PWR_CSR1_ODRDY) == (PWR_CSR1_ODRDY));
AnnaBridge 171:3a7713b1edbc 898 }
AnnaBridge 171:3a7713b1edbc 899
AnnaBridge 171:3a7713b1edbc 900 /**
AnnaBridge 171:3a7713b1edbc 901 * @brief Indicate whether the Over-Drive mode switching is ready or not
AnnaBridge 171:3a7713b1edbc 902 * @rmtoll CSR1 ODSWRDY LL_PWR_IsActiveFlag_ODSW
AnnaBridge 171:3a7713b1edbc 903 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 904 */
AnnaBridge 171:3a7713b1edbc 905 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
AnnaBridge 171:3a7713b1edbc 906 {
AnnaBridge 171:3a7713b1edbc 907 return (READ_BIT(PWR->CSR1, PWR_CSR1_ODSWRDY) == (PWR_CSR1_ODSWRDY));
AnnaBridge 171:3a7713b1edbc 908 }
AnnaBridge 171:3a7713b1edbc 909
AnnaBridge 171:3a7713b1edbc 910 /**
AnnaBridge 171:3a7713b1edbc 911 * @brief Indicate whether the Under-Drive mode is ready or not
AnnaBridge 171:3a7713b1edbc 912 * @rmtoll CSR1 UDRDY LL_PWR_IsActiveFlag_UD
AnnaBridge 171:3a7713b1edbc 913 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 914 */
AnnaBridge 171:3a7713b1edbc 915 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
AnnaBridge 171:3a7713b1edbc 916 {
AnnaBridge 171:3a7713b1edbc 917 return (READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY) == (PWR_CSR1_UDRDY));
AnnaBridge 171:3a7713b1edbc 918 }
AnnaBridge 171:3a7713b1edbc 919
AnnaBridge 171:3a7713b1edbc 920 /**
AnnaBridge 171:3a7713b1edbc 921 * @brief Clear Standby Flag
AnnaBridge 171:3a7713b1edbc 922 * @rmtoll CR1 CSBF LL_PWR_ClearFlag_SB
AnnaBridge 171:3a7713b1edbc 923 * @retval None
AnnaBridge 171:3a7713b1edbc 924 */
AnnaBridge 171:3a7713b1edbc 925 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
AnnaBridge 171:3a7713b1edbc 926 {
AnnaBridge 171:3a7713b1edbc 927 SET_BIT(PWR->CR1, PWR_CR1_CSBF);
AnnaBridge 171:3a7713b1edbc 928 }
AnnaBridge 171:3a7713b1edbc 929
AnnaBridge 171:3a7713b1edbc 930 /**
AnnaBridge 171:3a7713b1edbc 931 * @brief Clear Wake-up Flag 6
AnnaBridge 171:3a7713b1edbc 932 * @rmtoll CR2 CWUF6 LL_PWR_ClearFlag_WU6
AnnaBridge 171:3a7713b1edbc 933 * @retval None
AnnaBridge 171:3a7713b1edbc 934 */
AnnaBridge 171:3a7713b1edbc 935 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
AnnaBridge 171:3a7713b1edbc 936 {
AnnaBridge 171:3a7713b1edbc 937 WRITE_REG(PWR->CR2, PWR_CR2_CWUPF6);
AnnaBridge 171:3a7713b1edbc 938 }
AnnaBridge 171:3a7713b1edbc 939
AnnaBridge 171:3a7713b1edbc 940 /**
AnnaBridge 171:3a7713b1edbc 941 * @brief Clear Wake-up Flag 5
AnnaBridge 171:3a7713b1edbc 942 * @rmtoll CR2 CWUF5 LL_PWR_ClearFlag_WU5
AnnaBridge 171:3a7713b1edbc 943 * @retval None
AnnaBridge 171:3a7713b1edbc 944 */
AnnaBridge 171:3a7713b1edbc 945 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
AnnaBridge 171:3a7713b1edbc 946 {
AnnaBridge 171:3a7713b1edbc 947 WRITE_REG(PWR->CR2, PWR_CR2_CWUPF5);
AnnaBridge 171:3a7713b1edbc 948 }
AnnaBridge 171:3a7713b1edbc 949
AnnaBridge 171:3a7713b1edbc 950 /**
AnnaBridge 171:3a7713b1edbc 951 * @brief Clear Wake-up Flag 4
AnnaBridge 171:3a7713b1edbc 952 * @rmtoll CR2 CWUF4 LL_PWR_ClearFlag_WU4
AnnaBridge 171:3a7713b1edbc 953 * @retval None
AnnaBridge 171:3a7713b1edbc 954 */
AnnaBridge 171:3a7713b1edbc 955 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
AnnaBridge 171:3a7713b1edbc 956 {
AnnaBridge 171:3a7713b1edbc 957 WRITE_REG(PWR->CR2, PWR_CR2_CWUPF4);
AnnaBridge 171:3a7713b1edbc 958 }
AnnaBridge 171:3a7713b1edbc 959
AnnaBridge 171:3a7713b1edbc 960 /**
AnnaBridge 171:3a7713b1edbc 961 * @brief Clear Wake-up Flag 3
AnnaBridge 171:3a7713b1edbc 962 * @rmtoll CR2 CWUF3 LL_PWR_ClearFlag_WU3
AnnaBridge 171:3a7713b1edbc 963 * @retval None
AnnaBridge 171:3a7713b1edbc 964 */
AnnaBridge 171:3a7713b1edbc 965 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
AnnaBridge 171:3a7713b1edbc 966 {
AnnaBridge 171:3a7713b1edbc 967 WRITE_REG(PWR->CR2, PWR_CR2_CWUPF3);
AnnaBridge 171:3a7713b1edbc 968 }
AnnaBridge 171:3a7713b1edbc 969
AnnaBridge 171:3a7713b1edbc 970 /**
AnnaBridge 171:3a7713b1edbc 971 * @brief Clear Wake-up Flag 2
AnnaBridge 171:3a7713b1edbc 972 * @rmtoll CR2 CWUF2 LL_PWR_ClearFlag_WU2
AnnaBridge 171:3a7713b1edbc 973 * @retval None
AnnaBridge 171:3a7713b1edbc 974 */
AnnaBridge 171:3a7713b1edbc 975 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
AnnaBridge 171:3a7713b1edbc 976 {
AnnaBridge 171:3a7713b1edbc 977 WRITE_REG(PWR->CR2, PWR_CR2_CWUPF2);
AnnaBridge 171:3a7713b1edbc 978 }
AnnaBridge 171:3a7713b1edbc 979
AnnaBridge 171:3a7713b1edbc 980 /**
AnnaBridge 171:3a7713b1edbc 981 * @brief Clear Wake-up Flag 1
AnnaBridge 171:3a7713b1edbc 982 * @rmtoll CR2 CWUF1 LL_PWR_ClearFlag_WU1
AnnaBridge 171:3a7713b1edbc 983 * @retval None
AnnaBridge 171:3a7713b1edbc 984 */
AnnaBridge 171:3a7713b1edbc 985 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
AnnaBridge 171:3a7713b1edbc 986 {
AnnaBridge 171:3a7713b1edbc 987 WRITE_REG(PWR->CR2, PWR_CR2_CWUPF1);
AnnaBridge 171:3a7713b1edbc 988 }
AnnaBridge 171:3a7713b1edbc 989
AnnaBridge 171:3a7713b1edbc 990 /**
AnnaBridge 171:3a7713b1edbc 991 * @brief Clear Under-Drive ready Flag
AnnaBridge 171:3a7713b1edbc 992 * @rmtoll CSR1 UDRDY LL_PWR_ClearFlag_UD
AnnaBridge 171:3a7713b1edbc 993 * @retval None
AnnaBridge 171:3a7713b1edbc 994 */
AnnaBridge 171:3a7713b1edbc 995 __STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
AnnaBridge 171:3a7713b1edbc 996 {
AnnaBridge 171:3a7713b1edbc 997 WRITE_REG(PWR->CSR1, PWR_CSR1_UDRDY);
AnnaBridge 171:3a7713b1edbc 998 }
AnnaBridge 171:3a7713b1edbc 999
AnnaBridge 171:3a7713b1edbc 1000 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 1001 /** @defgroup PWR_LL_EF_Init De-initialization function
AnnaBridge 171:3a7713b1edbc 1002 * @{
AnnaBridge 171:3a7713b1edbc 1003 */
AnnaBridge 171:3a7713b1edbc 1004 ErrorStatus LL_PWR_DeInit(void);
AnnaBridge 171:3a7713b1edbc 1005 /**
AnnaBridge 171:3a7713b1edbc 1006 * @}
AnnaBridge 171:3a7713b1edbc 1007 */
AnnaBridge 171:3a7713b1edbc 1008 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 1009
AnnaBridge 171:3a7713b1edbc 1010 /**
AnnaBridge 171:3a7713b1edbc 1011 * @}
AnnaBridge 171:3a7713b1edbc 1012 */
AnnaBridge 171:3a7713b1edbc 1013
AnnaBridge 171:3a7713b1edbc 1014 /**
AnnaBridge 171:3a7713b1edbc 1015 * @}
AnnaBridge 171:3a7713b1edbc 1016 */
AnnaBridge 171:3a7713b1edbc 1017
AnnaBridge 171:3a7713b1edbc 1018 /**
AnnaBridge 171:3a7713b1edbc 1019 * @}
AnnaBridge 171:3a7713b1edbc 1020 */
AnnaBridge 171:3a7713b1edbc 1021
AnnaBridge 171:3a7713b1edbc 1022 #endif /* defined(PWR) */
AnnaBridge 171:3a7713b1edbc 1023
AnnaBridge 171:3a7713b1edbc 1024 /**
AnnaBridge 171:3a7713b1edbc 1025 * @}
AnnaBridge 171:3a7713b1edbc 1026 */
AnnaBridge 171:3a7713b1edbc 1027
AnnaBridge 171:3a7713b1edbc 1028 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1029 }
AnnaBridge 171:3a7713b1edbc 1030 #endif
AnnaBridge 171:3a7713b1edbc 1031
AnnaBridge 171:3a7713b1edbc 1032 #endif /* __STM32F7xx_LL_PWR_H */
AnnaBridge 171:3a7713b1edbc 1033
AnnaBridge 171:3a7713b1edbc 1034 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/