mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f7xx_ll_cortex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f7xx_ll_cortex.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of CORTEX LL module.
AnnaBridge 171:3a7713b1edbc 6 @verbatim
AnnaBridge 171:3a7713b1edbc 7 ==============================================================================
AnnaBridge 171:3a7713b1edbc 8 ##### How to use this driver #####
AnnaBridge 171:3a7713b1edbc 9 ==============================================================================
AnnaBridge 171:3a7713b1edbc 10 [..]
AnnaBridge 171:3a7713b1edbc 11 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 171:3a7713b1edbc 12 used by user:
AnnaBridge 171:3a7713b1edbc 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 171:3a7713b1edbc 14 functions
AnnaBridge 171:3a7713b1edbc 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 171:3a7713b1edbc 16 (+) MPU API to configure and enable regions
AnnaBridge 171:3a7713b1edbc 17 (+) API to access to MCU info (CPUID register)
AnnaBridge 171:3a7713b1edbc 18 (+) API to enable fault handler (SHCSR accesses)
AnnaBridge 171:3a7713b1edbc 19
AnnaBridge 171:3a7713b1edbc 20 @endverbatim
AnnaBridge 171:3a7713b1edbc 21 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 22 * @attention
AnnaBridge 171:3a7713b1edbc 23 *
AnnaBridge 171:3a7713b1edbc 24 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 27 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 28 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 29 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 30 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 31 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 32 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 33 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 34 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 35 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 40 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 41 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 42 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 43 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 44 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 47 *
AnnaBridge 171:3a7713b1edbc 48 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 52 #ifndef __STM32F7xx_LL_CORTEX_H
AnnaBridge 171:3a7713b1edbc 53 #define __STM32F7xx_LL_CORTEX_H
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 56 extern "C" {
AnnaBridge 171:3a7713b1edbc 57 #endif
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60 #include "stm32f7xx.h"
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /** @addtogroup STM32F7xx_LL_Driver
AnnaBridge 171:3a7713b1edbc 63 * @{
AnnaBridge 171:3a7713b1edbc 64 */
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 171:3a7713b1edbc 67 * @{
AnnaBridge 171:3a7713b1edbc 68 */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 71 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 78 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 79 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 171:3a7713b1edbc 80 * @{
AnnaBridge 171:3a7713b1edbc 81 */
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 171:3a7713b1edbc 84 * @{
AnnaBridge 171:3a7713b1edbc 85 */
AnnaBridge 171:3a7713b1edbc 86 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 171:3a7713b1edbc 87 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 171:3a7713b1edbc 88 /**
AnnaBridge 171:3a7713b1edbc 89 * @}
AnnaBridge 171:3a7713b1edbc 90 */
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
AnnaBridge 171:3a7713b1edbc 93 * @{
AnnaBridge 171:3a7713b1edbc 94 */
AnnaBridge 171:3a7713b1edbc 95 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
AnnaBridge 171:3a7713b1edbc 96 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
AnnaBridge 171:3a7713b1edbc 97 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
AnnaBridge 171:3a7713b1edbc 98 /**
AnnaBridge 171:3a7713b1edbc 99 * @}
AnnaBridge 171:3a7713b1edbc 100 */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 #if __MPU_PRESENT
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
AnnaBridge 171:3a7713b1edbc 105 * @{
AnnaBridge 171:3a7713b1edbc 106 */
AnnaBridge 171:3a7713b1edbc 107 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
AnnaBridge 171:3a7713b1edbc 108 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
AnnaBridge 171:3a7713b1edbc 109 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
AnnaBridge 171:3a7713b1edbc 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
AnnaBridge 171:3a7713b1edbc 111 /**
AnnaBridge 171:3a7713b1edbc 112 * @}
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
AnnaBridge 171:3a7713b1edbc 116 * @{
AnnaBridge 171:3a7713b1edbc 117 */
AnnaBridge 171:3a7713b1edbc 118 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 171:3a7713b1edbc 119 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 171:3a7713b1edbc 120 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 171:3a7713b1edbc 121 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 171:3a7713b1edbc 122 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 171:3a7713b1edbc 123 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 171:3a7713b1edbc 124 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 171:3a7713b1edbc 125 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
AnnaBridge 171:3a7713b1edbc 126 /**
AnnaBridge 171:3a7713b1edbc 127 * @}
AnnaBridge 171:3a7713b1edbc 128 */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
AnnaBridge 171:3a7713b1edbc 131 * @{
AnnaBridge 171:3a7713b1edbc 132 */
AnnaBridge 171:3a7713b1edbc 133 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 134 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 135 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 136 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 137 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 138 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 139 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 140 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 141 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 142 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 143 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 144 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 145 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 146 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 147 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 148 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 149 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 150 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 151 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 152 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 153 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 154 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 155 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 156 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 157 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 158 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 159 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 160 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
AnnaBridge 171:3a7713b1edbc 161 /**
AnnaBridge 171:3a7713b1edbc 162 * @}
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
AnnaBridge 171:3a7713b1edbc 166 * @{
AnnaBridge 171:3a7713b1edbc 167 */
AnnaBridge 171:3a7713b1edbc 168 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 171:3a7713b1edbc 169 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 171:3a7713b1edbc 170 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 171:3a7713b1edbc 171 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 171:3a7713b1edbc 172 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 171:3a7713b1edbc 173 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
AnnaBridge 171:3a7713b1edbc 174 /**
AnnaBridge 171:3a7713b1edbc 175 * @}
AnnaBridge 171:3a7713b1edbc 176 */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
AnnaBridge 171:3a7713b1edbc 179 * @{
AnnaBridge 171:3a7713b1edbc 180 */
AnnaBridge 171:3a7713b1edbc 181 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 171:3a7713b1edbc 182 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 171:3a7713b1edbc 183 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 171:3a7713b1edbc 184 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
AnnaBridge 171:3a7713b1edbc 185 /**
AnnaBridge 171:3a7713b1edbc 186 * @}
AnnaBridge 171:3a7713b1edbc 187 */
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
AnnaBridge 171:3a7713b1edbc 190 * @{
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
AnnaBridge 171:3a7713b1edbc 193 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
AnnaBridge 171:3a7713b1edbc 194 /**
AnnaBridge 171:3a7713b1edbc 195 * @}
AnnaBridge 171:3a7713b1edbc 196 */
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
AnnaBridge 171:3a7713b1edbc 199 * @{
AnnaBridge 171:3a7713b1edbc 200 */
AnnaBridge 171:3a7713b1edbc 201 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 171:3a7713b1edbc 202 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
AnnaBridge 171:3a7713b1edbc 203 /**
AnnaBridge 171:3a7713b1edbc 204 * @}
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
AnnaBridge 171:3a7713b1edbc 208 * @{
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 171:3a7713b1edbc 211 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
AnnaBridge 171:3a7713b1edbc 212 /**
AnnaBridge 171:3a7713b1edbc 213 * @}
AnnaBridge 171:3a7713b1edbc 214 */
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
AnnaBridge 171:3a7713b1edbc 217 * @{
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 171:3a7713b1edbc 220 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
AnnaBridge 171:3a7713b1edbc 221 /**
AnnaBridge 171:3a7713b1edbc 222 * @}
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224 #endif /* __MPU_PRESENT */
AnnaBridge 171:3a7713b1edbc 225 /**
AnnaBridge 171:3a7713b1edbc 226 * @}
AnnaBridge 171:3a7713b1edbc 227 */
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 232 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 171:3a7713b1edbc 233 * @{
AnnaBridge 171:3a7713b1edbc 234 */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 171:3a7713b1edbc 237 * @{
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239
AnnaBridge 171:3a7713b1edbc 240 /**
AnnaBridge 171:3a7713b1edbc 241 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 171:3a7713b1edbc 242 * @note It can be used in timeout function on application side.
AnnaBridge 171:3a7713b1edbc 243 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 171:3a7713b1edbc 244 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 245 */
AnnaBridge 171:3a7713b1edbc 246 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 171:3a7713b1edbc 247 {
AnnaBridge 171:3a7713b1edbc 248 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
AnnaBridge 171:3a7713b1edbc 249 }
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 /**
AnnaBridge 171:3a7713b1edbc 252 * @brief Configures the SysTick clock source
AnnaBridge 171:3a7713b1edbc 253 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 171:3a7713b1edbc 254 * @param Source This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 255 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 171:3a7713b1edbc 256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 171:3a7713b1edbc 257 * @retval None
AnnaBridge 171:3a7713b1edbc 258 */
AnnaBridge 171:3a7713b1edbc 259 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 171:3a7713b1edbc 260 {
AnnaBridge 171:3a7713b1edbc 261 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
AnnaBridge 171:3a7713b1edbc 262 {
AnnaBridge 171:3a7713b1edbc 263 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 171:3a7713b1edbc 264 }
AnnaBridge 171:3a7713b1edbc 265 else
AnnaBridge 171:3a7713b1edbc 266 {
AnnaBridge 171:3a7713b1edbc 267 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 171:3a7713b1edbc 268 }
AnnaBridge 171:3a7713b1edbc 269 }
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271 /**
AnnaBridge 171:3a7713b1edbc 272 * @brief Get the SysTick clock source
AnnaBridge 171:3a7713b1edbc 273 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 171:3a7713b1edbc 274 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 275 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 171:3a7713b1edbc 276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 171:3a7713b1edbc 277 */
AnnaBridge 171:3a7713b1edbc 278 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 171:3a7713b1edbc 279 {
AnnaBridge 171:3a7713b1edbc 280 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 171:3a7713b1edbc 281 }
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 /**
AnnaBridge 171:3a7713b1edbc 284 * @brief Enable SysTick exception request
AnnaBridge 171:3a7713b1edbc 285 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 171:3a7713b1edbc 286 * @retval None
AnnaBridge 171:3a7713b1edbc 287 */
AnnaBridge 171:3a7713b1edbc 288 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 171:3a7713b1edbc 289 {
AnnaBridge 171:3a7713b1edbc 290 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 171:3a7713b1edbc 291 }
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 /**
AnnaBridge 171:3a7713b1edbc 294 * @brief Disable SysTick exception request
AnnaBridge 171:3a7713b1edbc 295 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 171:3a7713b1edbc 296 * @retval None
AnnaBridge 171:3a7713b1edbc 297 */
AnnaBridge 171:3a7713b1edbc 298 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 171:3a7713b1edbc 299 {
AnnaBridge 171:3a7713b1edbc 300 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 171:3a7713b1edbc 301 }
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /**
AnnaBridge 171:3a7713b1edbc 304 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 305 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 171:3a7713b1edbc 306 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 307 */
AnnaBridge 171:3a7713b1edbc 308 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 171:3a7713b1edbc 309 {
AnnaBridge 171:3a7713b1edbc 310 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
AnnaBridge 171:3a7713b1edbc 311 }
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 /**
AnnaBridge 171:3a7713b1edbc 314 * @}
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 171:3a7713b1edbc 318 * @{
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 /**
AnnaBridge 171:3a7713b1edbc 322 * @brief Processor uses sleep as its low power mode
AnnaBridge 171:3a7713b1edbc 323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 171:3a7713b1edbc 324 * @retval None
AnnaBridge 171:3a7713b1edbc 325 */
AnnaBridge 171:3a7713b1edbc 326 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 171:3a7713b1edbc 327 {
AnnaBridge 171:3a7713b1edbc 328 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 171:3a7713b1edbc 330 }
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 /**
AnnaBridge 171:3a7713b1edbc 333 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 171:3a7713b1edbc 334 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 171:3a7713b1edbc 335 * @retval None
AnnaBridge 171:3a7713b1edbc 336 */
AnnaBridge 171:3a7713b1edbc 337 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 171:3a7713b1edbc 338 {
AnnaBridge 171:3a7713b1edbc 339 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 171:3a7713b1edbc 341 }
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /**
AnnaBridge 171:3a7713b1edbc 344 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 171:3a7713b1edbc 345 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 171:3a7713b1edbc 346 * empty main application.
AnnaBridge 171:3a7713b1edbc 347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 171:3a7713b1edbc 348 * @retval None
AnnaBridge 171:3a7713b1edbc 349 */
AnnaBridge 171:3a7713b1edbc 350 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 171:3a7713b1edbc 351 {
AnnaBridge 171:3a7713b1edbc 352 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 171:3a7713b1edbc 354 }
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 /**
AnnaBridge 171:3a7713b1edbc 357 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 171:3a7713b1edbc 358 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 171:3a7713b1edbc 359 * @retval None
AnnaBridge 171:3a7713b1edbc 360 */
AnnaBridge 171:3a7713b1edbc 361 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 171:3a7713b1edbc 362 {
AnnaBridge 171:3a7713b1edbc 363 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 171:3a7713b1edbc 365 }
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367 /**
AnnaBridge 171:3a7713b1edbc 368 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 171:3a7713b1edbc 369 * processor.
AnnaBridge 171:3a7713b1edbc 370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 171:3a7713b1edbc 371 * @retval None
AnnaBridge 171:3a7713b1edbc 372 */
AnnaBridge 171:3a7713b1edbc 373 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 171:3a7713b1edbc 374 {
AnnaBridge 171:3a7713b1edbc 375 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 171:3a7713b1edbc 377 }
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 /**
AnnaBridge 171:3a7713b1edbc 380 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 171:3a7713b1edbc 381 * excluded
AnnaBridge 171:3a7713b1edbc 382 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 171:3a7713b1edbc 383 * @retval None
AnnaBridge 171:3a7713b1edbc 384 */
AnnaBridge 171:3a7713b1edbc 385 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 171:3a7713b1edbc 386 {
AnnaBridge 171:3a7713b1edbc 387 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 171:3a7713b1edbc 389 }
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 /**
AnnaBridge 171:3a7713b1edbc 392 * @}
AnnaBridge 171:3a7713b1edbc 393 */
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
AnnaBridge 171:3a7713b1edbc 396 * @{
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399 /**
AnnaBridge 171:3a7713b1edbc 400 * @brief Enable a fault in System handler control register (SHCSR)
AnnaBridge 171:3a7713b1edbc 401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
AnnaBridge 171:3a7713b1edbc 402 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 171:3a7713b1edbc 403 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 171:3a7713b1edbc 404 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 171:3a7713b1edbc 405 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 171:3a7713b1edbc 406 * @retval None
AnnaBridge 171:3a7713b1edbc 407 */
AnnaBridge 171:3a7713b1edbc 408 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
AnnaBridge 171:3a7713b1edbc 409 {
AnnaBridge 171:3a7713b1edbc 410 /* Enable the system handler fault */
AnnaBridge 171:3a7713b1edbc 411 SET_BIT(SCB->SHCSR, Fault);
AnnaBridge 171:3a7713b1edbc 412 }
AnnaBridge 171:3a7713b1edbc 413
AnnaBridge 171:3a7713b1edbc 414 /**
AnnaBridge 171:3a7713b1edbc 415 * @brief Disable a fault in System handler control register (SHCSR)
AnnaBridge 171:3a7713b1edbc 416 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
AnnaBridge 171:3a7713b1edbc 417 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 171:3a7713b1edbc 418 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 171:3a7713b1edbc 419 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 171:3a7713b1edbc 420 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 171:3a7713b1edbc 421 * @retval None
AnnaBridge 171:3a7713b1edbc 422 */
AnnaBridge 171:3a7713b1edbc 423 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
AnnaBridge 171:3a7713b1edbc 424 {
AnnaBridge 171:3a7713b1edbc 425 /* Disable the system handler fault */
AnnaBridge 171:3a7713b1edbc 426 CLEAR_BIT(SCB->SHCSR, Fault);
AnnaBridge 171:3a7713b1edbc 427 }
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 /**
AnnaBridge 171:3a7713b1edbc 430 * @}
AnnaBridge 171:3a7713b1edbc 431 */
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 171:3a7713b1edbc 434 * @{
AnnaBridge 171:3a7713b1edbc 435 */
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 /**
AnnaBridge 171:3a7713b1edbc 438 * @brief Get Implementer code
AnnaBridge 171:3a7713b1edbc 439 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 171:3a7713b1edbc 440 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 171:3a7713b1edbc 441 */
AnnaBridge 171:3a7713b1edbc 442 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 171:3a7713b1edbc 443 {
AnnaBridge 171:3a7713b1edbc 444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 171:3a7713b1edbc 445 }
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 /**
AnnaBridge 171:3a7713b1edbc 448 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 171:3a7713b1edbc 449 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 171:3a7713b1edbc 450 * @retval Value between 0 and 255 (0x0: revision 0)
AnnaBridge 171:3a7713b1edbc 451 */
AnnaBridge 171:3a7713b1edbc 452 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 171:3a7713b1edbc 453 {
AnnaBridge 171:3a7713b1edbc 454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 171:3a7713b1edbc 455 }
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 /**
AnnaBridge 171:3a7713b1edbc 458 * @brief Get Constant number
AnnaBridge 171:3a7713b1edbc 459 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
AnnaBridge 171:3a7713b1edbc 460 * @retval Value should be equal to 0xF for Cortex-M7 devices
AnnaBridge 171:3a7713b1edbc 461 */
AnnaBridge 171:3a7713b1edbc 462 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
AnnaBridge 171:3a7713b1edbc 463 {
AnnaBridge 171:3a7713b1edbc 464 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 171:3a7713b1edbc 465 }
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 /**
AnnaBridge 171:3a7713b1edbc 468 * @brief Get Part number
AnnaBridge 171:3a7713b1edbc 469 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 171:3a7713b1edbc 470 * @retval Value should be equal to 0xC27 for Cortex-M7
AnnaBridge 171:3a7713b1edbc 471 */
AnnaBridge 171:3a7713b1edbc 472 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 171:3a7713b1edbc 473 {
AnnaBridge 171:3a7713b1edbc 474 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 171:3a7713b1edbc 475 }
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /**
AnnaBridge 171:3a7713b1edbc 478 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 171:3a7713b1edbc 479 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 171:3a7713b1edbc 480 * @retval Value between 0 and 255 (0x1: patch 1)
AnnaBridge 171:3a7713b1edbc 481 */
AnnaBridge 171:3a7713b1edbc 482 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 171:3a7713b1edbc 483 {
AnnaBridge 171:3a7713b1edbc 484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 171:3a7713b1edbc 485 }
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /**
AnnaBridge 171:3a7713b1edbc 488 * @}
AnnaBridge 171:3a7713b1edbc 489 */
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 #if __MPU_PRESENT
AnnaBridge 171:3a7713b1edbc 492 /** @defgroup CORTEX_LL_EF_MPU MPU
AnnaBridge 171:3a7713b1edbc 493 * @{
AnnaBridge 171:3a7713b1edbc 494 */
AnnaBridge 171:3a7713b1edbc 495
AnnaBridge 171:3a7713b1edbc 496 /**
AnnaBridge 171:3a7713b1edbc 497 * @brief Enable MPU with input options
AnnaBridge 171:3a7713b1edbc 498 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
AnnaBridge 171:3a7713b1edbc 499 * @param Options This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 500 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
AnnaBridge 171:3a7713b1edbc 501 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
AnnaBridge 171:3a7713b1edbc 502 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
AnnaBridge 171:3a7713b1edbc 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
AnnaBridge 171:3a7713b1edbc 504 * @retval None
AnnaBridge 171:3a7713b1edbc 505 */
AnnaBridge 171:3a7713b1edbc 506 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
AnnaBridge 171:3a7713b1edbc 507 {
AnnaBridge 171:3a7713b1edbc 508 /* Enable the MPU*/
AnnaBridge 171:3a7713b1edbc 509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
AnnaBridge 171:3a7713b1edbc 510 /* Ensure MPU settings take effects */
AnnaBridge 171:3a7713b1edbc 511 __DSB();
AnnaBridge 171:3a7713b1edbc 512 /* Sequence instruction fetches using update settings */
AnnaBridge 171:3a7713b1edbc 513 __ISB();
AnnaBridge 171:3a7713b1edbc 514 }
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /**
AnnaBridge 171:3a7713b1edbc 517 * @brief Disable MPU
AnnaBridge 171:3a7713b1edbc 518 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
AnnaBridge 171:3a7713b1edbc 519 * @retval None
AnnaBridge 171:3a7713b1edbc 520 */
AnnaBridge 171:3a7713b1edbc 521 __STATIC_INLINE void LL_MPU_Disable(void)
AnnaBridge 171:3a7713b1edbc 522 {
AnnaBridge 171:3a7713b1edbc 523 /* Make sure outstanding transfers are done */
AnnaBridge 171:3a7713b1edbc 524 __DMB();
AnnaBridge 171:3a7713b1edbc 525 /* Disable MPU*/
AnnaBridge 171:3a7713b1edbc 526 WRITE_REG(MPU->CTRL, 0U);
AnnaBridge 171:3a7713b1edbc 527 }
AnnaBridge 171:3a7713b1edbc 528
AnnaBridge 171:3a7713b1edbc 529 /**
AnnaBridge 171:3a7713b1edbc 530 * @brief Check if MPU is enabled or not
AnnaBridge 171:3a7713b1edbc 531 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
AnnaBridge 171:3a7713b1edbc 532 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 533 */
AnnaBridge 171:3a7713b1edbc 534 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
AnnaBridge 171:3a7713b1edbc 535 {
AnnaBridge 171:3a7713b1edbc 536 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
AnnaBridge 171:3a7713b1edbc 537 }
AnnaBridge 171:3a7713b1edbc 538
AnnaBridge 171:3a7713b1edbc 539 /**
AnnaBridge 171:3a7713b1edbc 540 * @brief Enable a MPU region
AnnaBridge 171:3a7713b1edbc 541 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
AnnaBridge 171:3a7713b1edbc 542 * @param Region This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 543 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 171:3a7713b1edbc 544 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 171:3a7713b1edbc 545 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 171:3a7713b1edbc 546 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 171:3a7713b1edbc 547 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 171:3a7713b1edbc 548 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 171:3a7713b1edbc 549 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 171:3a7713b1edbc 550 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 171:3a7713b1edbc 551 * @retval None
AnnaBridge 171:3a7713b1edbc 552 */
AnnaBridge 171:3a7713b1edbc 553 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
AnnaBridge 171:3a7713b1edbc 554 {
AnnaBridge 171:3a7713b1edbc 555 /* Set Region number */
AnnaBridge 171:3a7713b1edbc 556 WRITE_REG(MPU->RNR, Region);
AnnaBridge 171:3a7713b1edbc 557 /* Enable the MPU region */
AnnaBridge 171:3a7713b1edbc 558 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 171:3a7713b1edbc 559 }
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561 /**
AnnaBridge 171:3a7713b1edbc 562 * @brief Configure and enable a region
AnnaBridge 171:3a7713b1edbc 563 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
AnnaBridge 171:3a7713b1edbc 564 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
AnnaBridge 171:3a7713b1edbc 565 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
AnnaBridge 171:3a7713b1edbc 566 * MPU_RASR XN LL_MPU_ConfigRegion\n
AnnaBridge 171:3a7713b1edbc 567 * MPU_RASR AP LL_MPU_ConfigRegion\n
AnnaBridge 171:3a7713b1edbc 568 * MPU_RASR S LL_MPU_ConfigRegion\n
AnnaBridge 171:3a7713b1edbc 569 * MPU_RASR C LL_MPU_ConfigRegion\n
AnnaBridge 171:3a7713b1edbc 570 * MPU_RASR B LL_MPU_ConfigRegion\n
AnnaBridge 171:3a7713b1edbc 571 * MPU_RASR SIZE LL_MPU_ConfigRegion
AnnaBridge 171:3a7713b1edbc 572 * @param Region This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 573 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 171:3a7713b1edbc 574 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 171:3a7713b1edbc 575 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 171:3a7713b1edbc 576 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 171:3a7713b1edbc 577 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 171:3a7713b1edbc 578 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 171:3a7713b1edbc 579 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 171:3a7713b1edbc 580 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 171:3a7713b1edbc 581 * @param Address Value of region base address
AnnaBridge 171:3a7713b1edbc 582 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge 171:3a7713b1edbc 583 * @param Attributes This parameter can be a combination of the following values:
AnnaBridge 171:3a7713b1edbc 584 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
AnnaBridge 171:3a7713b1edbc 585 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
AnnaBridge 171:3a7713b1edbc 586 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
AnnaBridge 171:3a7713b1edbc 587 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
AnnaBridge 171:3a7713b1edbc 588 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
AnnaBridge 171:3a7713b1edbc 589 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
AnnaBridge 171:3a7713b1edbc 590 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
AnnaBridge 171:3a7713b1edbc 591 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
AnnaBridge 171:3a7713b1edbc 592 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
AnnaBridge 171:3a7713b1edbc 593 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
AnnaBridge 171:3a7713b1edbc 594 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
AnnaBridge 171:3a7713b1edbc 595 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
AnnaBridge 171:3a7713b1edbc 596 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
AnnaBridge 171:3a7713b1edbc 597 * @retval None
AnnaBridge 171:3a7713b1edbc 598 */
AnnaBridge 171:3a7713b1edbc 599 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
AnnaBridge 171:3a7713b1edbc 600 {
AnnaBridge 171:3a7713b1edbc 601 /* Set Region number */
AnnaBridge 171:3a7713b1edbc 602 WRITE_REG(MPU->RNR, Region);
AnnaBridge 171:3a7713b1edbc 603 /* Set base address */
AnnaBridge 171:3a7713b1edbc 604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
AnnaBridge 171:3a7713b1edbc 605 /* Configure MPU */
AnnaBridge 171:3a7713b1edbc 606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
AnnaBridge 171:3a7713b1edbc 607 }
AnnaBridge 171:3a7713b1edbc 608
AnnaBridge 171:3a7713b1edbc 609 /**
AnnaBridge 171:3a7713b1edbc 610 * @brief Disable a region
AnnaBridge 171:3a7713b1edbc 611 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
AnnaBridge 171:3a7713b1edbc 612 * MPU_RASR ENABLE LL_MPU_DisableRegion
AnnaBridge 171:3a7713b1edbc 613 * @param Region This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 614 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 171:3a7713b1edbc 615 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 171:3a7713b1edbc 616 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 171:3a7713b1edbc 617 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 171:3a7713b1edbc 618 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 171:3a7713b1edbc 619 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 171:3a7713b1edbc 620 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 171:3a7713b1edbc 621 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 171:3a7713b1edbc 622 * @retval None
AnnaBridge 171:3a7713b1edbc 623 */
AnnaBridge 171:3a7713b1edbc 624 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
AnnaBridge 171:3a7713b1edbc 625 {
AnnaBridge 171:3a7713b1edbc 626 /* Set Region number */
AnnaBridge 171:3a7713b1edbc 627 WRITE_REG(MPU->RNR, Region);
AnnaBridge 171:3a7713b1edbc 628 /* Disable the MPU region */
AnnaBridge 171:3a7713b1edbc 629 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 171:3a7713b1edbc 630 }
AnnaBridge 171:3a7713b1edbc 631
AnnaBridge 171:3a7713b1edbc 632 /**
AnnaBridge 171:3a7713b1edbc 633 * @}
AnnaBridge 171:3a7713b1edbc 634 */
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 #endif /* __MPU_PRESENT */
AnnaBridge 171:3a7713b1edbc 637 /**
AnnaBridge 171:3a7713b1edbc 638 * @}
AnnaBridge 171:3a7713b1edbc 639 */
AnnaBridge 171:3a7713b1edbc 640
AnnaBridge 171:3a7713b1edbc 641 /**
AnnaBridge 171:3a7713b1edbc 642 * @}
AnnaBridge 171:3a7713b1edbc 643 */
AnnaBridge 171:3a7713b1edbc 644
AnnaBridge 171:3a7713b1edbc 645 /**
AnnaBridge 171:3a7713b1edbc 646 * @}
AnnaBridge 171:3a7713b1edbc 647 */
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 650 }
AnnaBridge 171:3a7713b1edbc 651 #endif
AnnaBridge 171:3a7713b1edbc 652
AnnaBridge 171:3a7713b1edbc 653 #endif /* __STM32F7xx_LL_CORTEX_H */
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/