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TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f7xx_hal_spi.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_spi.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of SPI HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_SPI_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_SPI_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup SPI |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup SPI_Exported_Types SPI Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 58 | */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | |
| AnnaBridge | 171:3a7713b1edbc | 60 | /** |
| AnnaBridge | 171:3a7713b1edbc | 61 | * @brief SPI Configuration Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 62 | */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 64 | { |
| AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| AnnaBridge | 171:3a7713b1edbc | 66 | This parameter can be a value of @ref SPI_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | |
| AnnaBridge | 171:3a7713b1edbc | 68 | uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. |
| AnnaBridge | 171:3a7713b1edbc | 69 | This parameter can be a value of @ref SPI_Direction */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | |
| AnnaBridge | 171:3a7713b1edbc | 71 | uint32_t DataSize; /*!< Specifies the SPI data size. |
| AnnaBridge | 171:3a7713b1edbc | 72 | This parameter can be a value of @ref SPI_Data_Size */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | |
| AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
| AnnaBridge | 171:3a7713b1edbc | 75 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
| AnnaBridge | 171:3a7713b1edbc | 78 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | |
| AnnaBridge | 171:3a7713b1edbc | 80 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
| AnnaBridge | 171:3a7713b1edbc | 81 | hardware (NSS pin) or by software using the SSI bit. |
| AnnaBridge | 171:3a7713b1edbc | 82 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | |
| AnnaBridge | 171:3a7713b1edbc | 84 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| AnnaBridge | 171:3a7713b1edbc | 85 | used to configure the transmit and receive SCK clock. |
| AnnaBridge | 171:3a7713b1edbc | 86 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 171:3a7713b1edbc | 87 | @note The communication clock is derived from the master |
| AnnaBridge | 171:3a7713b1edbc | 88 | clock. The slave clock does not need to be set. */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| AnnaBridge | 171:3a7713b1edbc | 91 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | |
| AnnaBridge | 171:3a7713b1edbc | 93 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
| AnnaBridge | 171:3a7713b1edbc | 94 | This parameter can be a value of @ref SPI_TI_mode */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | |
| AnnaBridge | 171:3a7713b1edbc | 96 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
| AnnaBridge | 171:3a7713b1edbc | 97 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | |
| AnnaBridge | 171:3a7713b1edbc | 99 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
| AnnaBridge | 171:3a7713b1edbc | 100 | This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | |
| AnnaBridge | 171:3a7713b1edbc | 102 | uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. |
| AnnaBridge | 171:3a7713b1edbc | 103 | CRC Length is only used with Data8 and Data16, not other data size |
| AnnaBridge | 171:3a7713b1edbc | 104 | This parameter can be a value of @ref SPI_CRC_length */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | |
| AnnaBridge | 171:3a7713b1edbc | 106 | uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . |
| AnnaBridge | 171:3a7713b1edbc | 107 | This parameter can be a value of @ref SPI_NSSP_Mode |
| AnnaBridge | 171:3a7713b1edbc | 108 | This mode is activated by the NSSP bit in the SPIx_CR2 register and |
| AnnaBridge | 171:3a7713b1edbc | 109 | it takes effect only if the SPI interface is configured as Motorola SPI |
| AnnaBridge | 171:3a7713b1edbc | 110 | master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, |
| AnnaBridge | 171:3a7713b1edbc | 111 | CPOL setting is ignored).. */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | } SPI_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 113 | |
| AnnaBridge | 171:3a7713b1edbc | 114 | /** |
| AnnaBridge | 171:3a7713b1edbc | 115 | * @brief HAL SPI State structure definition |
| AnnaBridge | 171:3a7713b1edbc | 116 | */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | typedef enum |
| AnnaBridge | 171:3a7713b1edbc | 118 | { |
| AnnaBridge | 171:3a7713b1edbc | 119 | HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | } HAL_SPI_StateTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 128 | |
| AnnaBridge | 171:3a7713b1edbc | 129 | /** |
| AnnaBridge | 171:3a7713b1edbc | 130 | * @brief SPI handle Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 131 | */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | typedef struct __SPI_HandleTypeDef |
| AnnaBridge | 171:3a7713b1edbc | 133 | { |
| AnnaBridge | 171:3a7713b1edbc | 134 | SPI_TypeDef *Instance; /*!< SPI registers base address */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | |
| AnnaBridge | 171:3a7713b1edbc | 136 | SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | |
| AnnaBridge | 171:3a7713b1edbc | 138 | uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | uint16_t TxXferSize; /*!< SPI Tx Transfer size */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | |
| AnnaBridge | 171:3a7713b1edbc | 142 | __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | |
| AnnaBridge | 171:3a7713b1edbc | 144 | uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | |
| AnnaBridge | 171:3a7713b1edbc | 146 | uint16_t RxXferSize; /*!< SPI Rx Transfer size */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | |
| AnnaBridge | 171:3a7713b1edbc | 148 | __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | |
| AnnaBridge | 171:3a7713b1edbc | 150 | uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | |
| AnnaBridge | 171:3a7713b1edbc | 152 | void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | |
| AnnaBridge | 171:3a7713b1edbc | 154 | void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | |
| AnnaBridge | 171:3a7713b1edbc | 156 | DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | |
| AnnaBridge | 171:3a7713b1edbc | 158 | DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | |
| AnnaBridge | 171:3a7713b1edbc | 160 | HAL_LockTypeDef Lock; /*!< Locking object */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | |
| AnnaBridge | 171:3a7713b1edbc | 162 | __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | |
| AnnaBridge | 171:3a7713b1edbc | 164 | __IO uint32_t ErrorCode; /*!< SPI Error code */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | |
| AnnaBridge | 171:3a7713b1edbc | 166 | } SPI_HandleTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 167 | |
| AnnaBridge | 171:3a7713b1edbc | 168 | /** |
| AnnaBridge | 171:3a7713b1edbc | 169 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 170 | */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 173 | |
| AnnaBridge | 171:3a7713b1edbc | 174 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 175 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 176 | */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | |
| AnnaBridge | 171:3a7713b1edbc | 178 | /** @defgroup SPI_Error_Code SPI Error Code |
| AnnaBridge | 171:3a7713b1edbc | 179 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 180 | */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define HAL_SPI_ERROR_ABORT ((uint32_t)0x00000040U) /*!< Error during SPI Abort procedure */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | /** |
| AnnaBridge | 171:3a7713b1edbc | 190 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 191 | */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | |
| AnnaBridge | 171:3a7713b1edbc | 193 | /** @defgroup SPI_Mode SPI Mode |
| AnnaBridge | 171:3a7713b1edbc | 194 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 195 | */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define SPI_MODE_SLAVE ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| AnnaBridge | 171:3a7713b1edbc | 198 | /** |
| AnnaBridge | 171:3a7713b1edbc | 199 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 200 | */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | |
| AnnaBridge | 171:3a7713b1edbc | 202 | /** @defgroup SPI_Direction SPI Direction Mode |
| AnnaBridge | 171:3a7713b1edbc | 203 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 204 | */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| AnnaBridge | 171:3a7713b1edbc | 208 | /** |
| AnnaBridge | 171:3a7713b1edbc | 209 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 210 | */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | |
| AnnaBridge | 171:3a7713b1edbc | 212 | /** @defgroup SPI_Data_Size SPI Data Size |
| AnnaBridge | 171:3a7713b1edbc | 213 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 214 | */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define SPI_DATASIZE_4BIT ((uint32_t)0x00000300U) |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define SPI_DATASIZE_5BIT ((uint32_t)0x00000400U) |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define SPI_DATASIZE_6BIT ((uint32_t)0x00000500U) |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define SPI_DATASIZE_7BIT ((uint32_t)0x00000600U) |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define SPI_DATASIZE_8BIT ((uint32_t)0x00000700U) |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define SPI_DATASIZE_9BIT ((uint32_t)0x00000800U) |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define SPI_DATASIZE_10BIT ((uint32_t)0x00000900U) |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define SPI_DATASIZE_11BIT ((uint32_t)0x00000A00U) |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define SPI_DATASIZE_12BIT ((uint32_t)0x00000B00U) |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define SPI_DATASIZE_13BIT ((uint32_t)0x00000C00U) |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define SPI_DATASIZE_14BIT ((uint32_t)0x00000D00U) |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define SPI_DATASIZE_15BIT ((uint32_t)0x00000E00U) |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define SPI_DATASIZE_16BIT ((uint32_t)0x00000F00U) |
| AnnaBridge | 171:3a7713b1edbc | 228 | /** |
| AnnaBridge | 171:3a7713b1edbc | 229 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 230 | */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | |
| AnnaBridge | 171:3a7713b1edbc | 232 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
| AnnaBridge | 171:3a7713b1edbc | 233 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 234 | */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define SPI_POLARITY_LOW ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| AnnaBridge | 171:3a7713b1edbc | 237 | /** |
| AnnaBridge | 171:3a7713b1edbc | 238 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 239 | */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | |
| AnnaBridge | 171:3a7713b1edbc | 241 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
| AnnaBridge | 171:3a7713b1edbc | 242 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 243 | */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define SPI_PHASE_1EDGE ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| AnnaBridge | 171:3a7713b1edbc | 246 | /** |
| AnnaBridge | 171:3a7713b1edbc | 247 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 248 | */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | |
| AnnaBridge | 171:3a7713b1edbc | 250 | /** @defgroup SPI_Slave_Select_management SPI Slave Select Management |
| AnnaBridge | 171:3a7713b1edbc | 251 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 252 | */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U) |
| AnnaBridge | 171:3a7713b1edbc | 256 | /** |
| AnnaBridge | 171:3a7713b1edbc | 257 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 258 | */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | |
| AnnaBridge | 171:3a7713b1edbc | 260 | /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode |
| AnnaBridge | 171:3a7713b1edbc | 261 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 262 | */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 265 | /** |
| AnnaBridge | 171:3a7713b1edbc | 266 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 267 | */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | |
| AnnaBridge | 171:3a7713b1edbc | 269 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 271 | */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U) |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U) |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U) |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U) |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U) |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U) |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U) |
| AnnaBridge | 171:3a7713b1edbc | 280 | /** |
| AnnaBridge | 171:3a7713b1edbc | 281 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 282 | */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | |
| AnnaBridge | 171:3a7713b1edbc | 284 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission |
| AnnaBridge | 171:3a7713b1edbc | 285 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 286 | */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| AnnaBridge | 171:3a7713b1edbc | 289 | /** |
| AnnaBridge | 171:3a7713b1edbc | 290 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 291 | */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | |
| AnnaBridge | 171:3a7713b1edbc | 293 | /** @defgroup SPI_TI_mode SPI TI Mode |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 295 | */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define SPI_TIMODE_ENABLE SPI_CR2_FRF |
| AnnaBridge | 171:3a7713b1edbc | 298 | /** |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 300 | */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | |
| AnnaBridge | 171:3a7713b1edbc | 302 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
| AnnaBridge | 171:3a7713b1edbc | 303 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 304 | */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
| AnnaBridge | 171:3a7713b1edbc | 307 | /** |
| AnnaBridge | 171:3a7713b1edbc | 308 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 309 | */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | |
| AnnaBridge | 171:3a7713b1edbc | 311 | /** @defgroup SPI_CRC_length SPI CRC Length |
| AnnaBridge | 171:3a7713b1edbc | 312 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 313 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 314 | * SPI_CRC_LENGTH_DATASIZE: aligned with the data size |
| AnnaBridge | 171:3a7713b1edbc | 315 | * SPI_CRC_LENGTH_8BIT : CRC 8bit |
| AnnaBridge | 171:3a7713b1edbc | 316 | * SPI_CRC_LENGTH_16BIT : CRC 16bit |
| AnnaBridge | 171:3a7713b1edbc | 317 | */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001U) |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002U) |
| AnnaBridge | 171:3a7713b1edbc | 321 | /** |
| AnnaBridge | 171:3a7713b1edbc | 322 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 323 | */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | |
| AnnaBridge | 171:3a7713b1edbc | 325 | /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold |
| AnnaBridge | 171:3a7713b1edbc | 326 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 327 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 328 | * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : |
| AnnaBridge | 171:3a7713b1edbc | 329 | * RXNE event is generated if the FIFO |
| AnnaBridge | 171:3a7713b1edbc | 330 | * level is greater or equal to 1/2(16-bits). |
| AnnaBridge | 171:3a7713b1edbc | 331 | * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO |
| AnnaBridge | 171:3a7713b1edbc | 332 | * level is greater or equal to 1/4(8 bits). */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 336 | |
| AnnaBridge | 171:3a7713b1edbc | 337 | /** |
| AnnaBridge | 171:3a7713b1edbc | 338 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 339 | */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | |
| AnnaBridge | 171:3a7713b1edbc | 341 | /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition |
| AnnaBridge | 171:3a7713b1edbc | 342 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 343 | */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| AnnaBridge | 171:3a7713b1edbc | 347 | /** |
| AnnaBridge | 171:3a7713b1edbc | 348 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 349 | */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | |
| AnnaBridge | 171:3a7713b1edbc | 351 | /** @defgroup SPI_Flags_definition SPI Flags Definition |
| AnnaBridge | 171:3a7713b1edbc | 352 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 353 | */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | /** |
| AnnaBridge | 171:3a7713b1edbc | 364 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 365 | */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | |
| AnnaBridge | 171:3a7713b1edbc | 367 | /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level |
| AnnaBridge | 171:3a7713b1edbc | 368 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 369 | */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define SPI_FTLVL_EMPTY ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x00000800U) |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define SPI_FTLVL_HALF_FULL ((uint32_t)0x00001000U) |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define SPI_FTLVL_FULL ((uint32_t)0x00001800U) |
| AnnaBridge | 171:3a7713b1edbc | 374 | |
| AnnaBridge | 171:3a7713b1edbc | 375 | /** |
| AnnaBridge | 171:3a7713b1edbc | 376 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 377 | */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | |
| AnnaBridge | 171:3a7713b1edbc | 379 | /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level |
| AnnaBridge | 171:3a7713b1edbc | 380 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 381 | */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define SPI_FRLVL_EMPTY ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x00000200U) |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define SPI_FRLVL_HALF_FULL ((uint32_t)0x00000400U) |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define SPI_FRLVL_FULL ((uint32_t)0x00000600U) |
| AnnaBridge | 171:3a7713b1edbc | 386 | /** |
| AnnaBridge | 171:3a7713b1edbc | 387 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 388 | */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | |
| AnnaBridge | 171:3a7713b1edbc | 390 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 391 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 392 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 393 | */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | |
| AnnaBridge | 171:3a7713b1edbc | 395 | /** @brief Reset SPI handle state. |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 397 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 398 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 399 | */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| AnnaBridge | 171:3a7713b1edbc | 401 | |
| AnnaBridge | 171:3a7713b1edbc | 402 | /** @brief Enable or disable the specified SPI interrupts. |
| AnnaBridge | 171:3a7713b1edbc | 403 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 404 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 405 | * @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
| AnnaBridge | 171:3a7713b1edbc | 406 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 407 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 408 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 409 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 410 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 411 | */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) |
| AnnaBridge | 171:3a7713b1edbc | 414 | |
| AnnaBridge | 171:3a7713b1edbc | 415 | /** @brief Check whether the specified SPI interrupt source is enabled or not. |
| AnnaBridge | 171:3a7713b1edbc | 416 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 417 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 418 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
| AnnaBridge | 171:3a7713b1edbc | 419 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 420 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 421 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 423 | * @retval The new state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 171:3a7713b1edbc | 424 | */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 171:3a7713b1edbc | 426 | |
| AnnaBridge | 171:3a7713b1edbc | 427 | /** @brief Check whether the specified SPI flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 428 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 429 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 430 | * @param __FLAG__ specifies the flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 431 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 432 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| AnnaBridge | 171:3a7713b1edbc | 433 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| AnnaBridge | 171:3a7713b1edbc | 434 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| AnnaBridge | 171:3a7713b1edbc | 435 | * @arg SPI_FLAG_MODF: Mode fault flag |
| AnnaBridge | 171:3a7713b1edbc | 436 | * @arg SPI_FLAG_OVR: Overrun flag |
| AnnaBridge | 171:3a7713b1edbc | 437 | * @arg SPI_FLAG_BSY: Busy flag |
| AnnaBridge | 171:3a7713b1edbc | 438 | * @arg SPI_FLAG_FRE: Frame format error flag |
| AnnaBridge | 171:3a7713b1edbc | 439 | * @arg SPI_FLAG_FTLVL: SPI fifo transmission level |
| AnnaBridge | 171:3a7713b1edbc | 440 | * @arg SPI_FLAG_FRLVL: SPI fifo reception level |
| AnnaBridge | 171:3a7713b1edbc | 441 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 171:3a7713b1edbc | 442 | */ |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 444 | |
| AnnaBridge | 171:3a7713b1edbc | 445 | /** @brief Clear the SPI CRCERR pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 446 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 447 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 448 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 449 | */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
| AnnaBridge | 171:3a7713b1edbc | 451 | |
| AnnaBridge | 171:3a7713b1edbc | 452 | /** @brief Clear the SPI MODF pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 453 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 454 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 455 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 456 | */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 458 | do{ \ |
| AnnaBridge | 171:3a7713b1edbc | 459 | __IO uint32_t tmpreg_modf = 0x00U; \ |
| AnnaBridge | 171:3a7713b1edbc | 460 | tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 171:3a7713b1edbc | 461 | (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ |
| AnnaBridge | 171:3a7713b1edbc | 462 | UNUSED(tmpreg_modf); \ |
| AnnaBridge | 171:3a7713b1edbc | 463 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 464 | |
| AnnaBridge | 171:3a7713b1edbc | 465 | /** @brief Clear the SPI OVR pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 466 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 467 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 468 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 469 | */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 471 | do{ \ |
| AnnaBridge | 171:3a7713b1edbc | 472 | __IO uint32_t tmpreg_ovr = 0x00U; \ |
| AnnaBridge | 171:3a7713b1edbc | 473 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
| AnnaBridge | 171:3a7713b1edbc | 474 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 171:3a7713b1edbc | 475 | UNUSED(tmpreg_ovr); \ |
| AnnaBridge | 171:3a7713b1edbc | 476 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 477 | |
| AnnaBridge | 171:3a7713b1edbc | 478 | /** @brief Clear the SPI FRE pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 480 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 482 | */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 484 | do{ \ |
| AnnaBridge | 171:3a7713b1edbc | 485 | __IO uint32_t tmpreg_fre = 0x00U; \ |
| AnnaBridge | 171:3a7713b1edbc | 486 | tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 171:3a7713b1edbc | 487 | UNUSED(tmpreg_fre); \ |
| AnnaBridge | 171:3a7713b1edbc | 488 | }while(0) |
| AnnaBridge | 171:3a7713b1edbc | 489 | |
| AnnaBridge | 171:3a7713b1edbc | 490 | /** @brief Enable the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 491 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 492 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 493 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 494 | */ |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) |
| AnnaBridge | 171:3a7713b1edbc | 496 | |
| AnnaBridge | 171:3a7713b1edbc | 497 | /** @brief Disable the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 498 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 499 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 500 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 501 | */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) |
| AnnaBridge | 171:3a7713b1edbc | 503 | |
| AnnaBridge | 171:3a7713b1edbc | 504 | /** |
| AnnaBridge | 171:3a7713b1edbc | 505 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 506 | */ |
| AnnaBridge | 171:3a7713b1edbc | 507 | |
| AnnaBridge | 171:3a7713b1edbc | 508 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 509 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 510 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 511 | */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | |
| AnnaBridge | 171:3a7713b1edbc | 513 | /** @brief Set the SPI transmit-only mode. |
| AnnaBridge | 171:3a7713b1edbc | 514 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 515 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 516 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 517 | */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) |
| AnnaBridge | 171:3a7713b1edbc | 519 | |
| AnnaBridge | 171:3a7713b1edbc | 520 | /** @brief Set the SPI receive-only mode. |
| AnnaBridge | 171:3a7713b1edbc | 521 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 522 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 524 | */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) |
| AnnaBridge | 171:3a7713b1edbc | 526 | |
| AnnaBridge | 171:3a7713b1edbc | 527 | /** @brief Reset the CRC calculation of the SPI. |
| AnnaBridge | 171:3a7713b1edbc | 528 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 529 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 530 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 531 | */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 533 | (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) |
| AnnaBridge | 171:3a7713b1edbc | 534 | |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 536 | ((MODE) == SPI_MODE_MASTER)) |
| AnnaBridge | 171:3a7713b1edbc | 537 | |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 171:3a7713b1edbc | 539 | ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ |
| AnnaBridge | 171:3a7713b1edbc | 540 | ((MODE) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 171:3a7713b1edbc | 541 | |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) |
| AnnaBridge | 171:3a7713b1edbc | 543 | |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 171:3a7713b1edbc | 545 | ((MODE) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 171:3a7713b1edbc | 546 | |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 548 | ((DATASIZE) == SPI_DATASIZE_15BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 549 | ((DATASIZE) == SPI_DATASIZE_14BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 550 | ((DATASIZE) == SPI_DATASIZE_13BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 551 | ((DATASIZE) == SPI_DATASIZE_12BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 552 | ((DATASIZE) == SPI_DATASIZE_11BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 553 | ((DATASIZE) == SPI_DATASIZE_10BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 554 | ((DATASIZE) == SPI_DATASIZE_9BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 555 | ((DATASIZE) == SPI_DATASIZE_8BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 556 | ((DATASIZE) == SPI_DATASIZE_7BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 557 | ((DATASIZE) == SPI_DATASIZE_6BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 558 | ((DATASIZE) == SPI_DATASIZE_5BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 559 | ((DATASIZE) == SPI_DATASIZE_4BIT)) |
| AnnaBridge | 171:3a7713b1edbc | 560 | |
| AnnaBridge | 171:3a7713b1edbc | 561 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ |
| AnnaBridge | 171:3a7713b1edbc | 562 | ((CPOL) == SPI_POLARITY_HIGH)) |
| AnnaBridge | 171:3a7713b1edbc | 563 | |
| AnnaBridge | 171:3a7713b1edbc | 564 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 565 | ((CPHA) == SPI_PHASE_2EDGE)) |
| AnnaBridge | 171:3a7713b1edbc | 566 | |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 568 | ((NSS) == SPI_NSS_HARD_INPUT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 569 | ((NSS) == SPI_NSS_HARD_OUTPUT)) |
| AnnaBridge | 171:3a7713b1edbc | 570 | |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 572 | ((NSSP) == SPI_NSS_PULSE_DISABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 573 | |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 575 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 576 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 577 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ |
| AnnaBridge | 171:3a7713b1edbc | 578 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ |
| AnnaBridge | 171:3a7713b1edbc | 579 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ |
| AnnaBridge | 171:3a7713b1edbc | 580 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ |
| AnnaBridge | 171:3a7713b1edbc | 581 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) |
| AnnaBridge | 171:3a7713b1edbc | 582 | |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 584 | ((BIT) == SPI_FIRSTBIT_LSB)) |
| AnnaBridge | 171:3a7713b1edbc | 585 | |
| AnnaBridge | 171:3a7713b1edbc | 586 | #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 587 | ((MODE) == SPI_TIMODE_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 588 | |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 590 | ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 591 | |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 593 | ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 594 | ((LENGTH) == SPI_CRC_LENGTH_16BIT)) |
| AnnaBridge | 171:3a7713b1edbc | 595 | |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0)) |
| AnnaBridge | 171:3a7713b1edbc | 597 | |
| AnnaBridge | 171:3a7713b1edbc | 598 | /** |
| AnnaBridge | 171:3a7713b1edbc | 599 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 600 | */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | |
| AnnaBridge | 171:3a7713b1edbc | 602 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 603 | /** @addtogroup SPI_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 604 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 605 | */ |
| AnnaBridge | 171:3a7713b1edbc | 606 | |
| AnnaBridge | 171:3a7713b1edbc | 607 | /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 171:3a7713b1edbc | 608 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 609 | */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | /* Initialization/de-initialization functions ********************************/ |
| AnnaBridge | 171:3a7713b1edbc | 611 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 612 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 613 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 614 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 615 | /** |
| AnnaBridge | 171:3a7713b1edbc | 616 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 617 | */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | |
| AnnaBridge | 171:3a7713b1edbc | 619 | /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions |
| AnnaBridge | 171:3a7713b1edbc | 620 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 621 | */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | /* I/O operation functions ***************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 623 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 624 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 625 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, |
| AnnaBridge | 171:3a7713b1edbc | 626 | uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 627 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 628 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 629 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
| AnnaBridge | 171:3a7713b1edbc | 630 | uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 631 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 632 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 633 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
| AnnaBridge | 171:3a7713b1edbc | 634 | uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 635 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 636 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 637 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 638 | /* Transfer Abort functions */ |
| AnnaBridge | 171:3a7713b1edbc | 639 | HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 640 | HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 641 | |
| AnnaBridge | 171:3a7713b1edbc | 642 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 643 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 644 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 645 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 646 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 647 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 648 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 649 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 650 | void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 651 | /** |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 653 | */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | |
| AnnaBridge | 171:3a7713b1edbc | 655 | /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions |
| AnnaBridge | 171:3a7713b1edbc | 656 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 657 | */ |
| AnnaBridge | 171:3a7713b1edbc | 658 | |
| AnnaBridge | 171:3a7713b1edbc | 659 | /* Peripheral State and Error functions ***************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 660 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 661 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 662 | /** |
| AnnaBridge | 171:3a7713b1edbc | 663 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 664 | */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | |
| AnnaBridge | 171:3a7713b1edbc | 666 | /** |
| AnnaBridge | 171:3a7713b1edbc | 667 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 668 | */ |
| AnnaBridge | 171:3a7713b1edbc | 669 | |
| AnnaBridge | 171:3a7713b1edbc | 670 | /** |
| AnnaBridge | 171:3a7713b1edbc | 671 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 672 | */ |
| AnnaBridge | 171:3a7713b1edbc | 673 | |
| AnnaBridge | 171:3a7713b1edbc | 674 | /** |
| AnnaBridge | 171:3a7713b1edbc | 675 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 676 | */ |
| AnnaBridge | 171:3a7713b1edbc | 677 | |
| AnnaBridge | 171:3a7713b1edbc | 678 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 679 | } |
| AnnaBridge | 171:3a7713b1edbc | 680 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 681 | |
| AnnaBridge | 171:3a7713b1edbc | 682 | #endif /* __STM32F7xx_HAL_SPI_H */ |
| AnnaBridge | 171:3a7713b1edbc | 683 | |
| AnnaBridge | 171:3a7713b1edbc | 684 | /** |
| AnnaBridge | 171:3a7713b1edbc | 685 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 686 | */ |
| AnnaBridge | 171:3a7713b1edbc | 687 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
