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TARGET_DISCO_F407VG/TOOLCHAIN_IAR/stm32f407xx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /**
AnnaBridge 161:aa5281ff4a02 2 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 3 * @file stm32f407xx.h
AnnaBridge 161:aa5281ff4a02 4 * @author MCD Application Team
AnnaBridge 161:aa5281ff4a02 5 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
AnnaBridge 161:aa5281ff4a02 6 *
AnnaBridge 161:aa5281ff4a02 7 * This file contains:
AnnaBridge 161:aa5281ff4a02 8 * - Data structures and the address mapping for all peripherals
AnnaBridge 161:aa5281ff4a02 9 * - peripherals registers declarations and bits definition
AnnaBridge 161:aa5281ff4a02 10 * - Macros to access peripheral's registers hardware
AnnaBridge 161:aa5281ff4a02 11 *
AnnaBridge 161:aa5281ff4a02 12 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 13 * @attention
AnnaBridge 161:aa5281ff4a02 14 *
AnnaBridge 161:aa5281ff4a02 15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 161:aa5281ff4a02 16 *
AnnaBridge 161:aa5281ff4a02 17 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 161:aa5281ff4a02 18 * are permitted provided that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 19 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 161:aa5281ff4a02 20 * this list of conditions and the following disclaimer.
AnnaBridge 161:aa5281ff4a02 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 161:aa5281ff4a02 22 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 161:aa5281ff4a02 23 * and/or other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 161:aa5281ff4a02 25 * may be used to endorse or promote products derived from this software
AnnaBridge 161:aa5281ff4a02 26 * without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 27 *
AnnaBridge 161:aa5281ff4a02 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 161:aa5281ff4a02 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 161:aa5281ff4a02 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 161:aa5281ff4a02 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 161:aa5281ff4a02 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 161:aa5281ff4a02 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 161:aa5281ff4a02 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 161:aa5281ff4a02 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 161:aa5281ff4a02 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 161:aa5281ff4a02 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 38 *
AnnaBridge 161:aa5281ff4a02 39 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 40 */
AnnaBridge 161:aa5281ff4a02 41
AnnaBridge 161:aa5281ff4a02 42 /** @addtogroup CMSIS_Device
AnnaBridge 161:aa5281ff4a02 43 * @{
AnnaBridge 161:aa5281ff4a02 44 */
AnnaBridge 161:aa5281ff4a02 45
AnnaBridge 161:aa5281ff4a02 46 /** @addtogroup stm32f407xx
AnnaBridge 161:aa5281ff4a02 47 * @{
AnnaBridge 161:aa5281ff4a02 48 */
AnnaBridge 161:aa5281ff4a02 49
AnnaBridge 161:aa5281ff4a02 50 #ifndef __STM32F407xx_H
AnnaBridge 161:aa5281ff4a02 51 #define __STM32F407xx_H
AnnaBridge 161:aa5281ff4a02 52
AnnaBridge 161:aa5281ff4a02 53 #ifdef __cplusplus
AnnaBridge 161:aa5281ff4a02 54 extern "C" {
AnnaBridge 161:aa5281ff4a02 55 #endif /* __cplusplus */
AnnaBridge 161:aa5281ff4a02 56
AnnaBridge 161:aa5281ff4a02 57 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 161:aa5281ff4a02 58 * @{
AnnaBridge 161:aa5281ff4a02 59 */
AnnaBridge 161:aa5281ff4a02 60
AnnaBridge 161:aa5281ff4a02 61 /**
AnnaBridge 161:aa5281ff4a02 62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
AnnaBridge 161:aa5281ff4a02 63 */
AnnaBridge 161:aa5281ff4a02 64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
AnnaBridge 161:aa5281ff4a02 65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
AnnaBridge 161:aa5281ff4a02 66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
AnnaBridge 161:aa5281ff4a02 67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 163:e59c8e839560 68 /* MBED */
AnnaBridge 161:aa5281ff4a02 69 #ifndef __FPU_PRESENT
AnnaBridge 161:aa5281ff4a02 70 #define __FPU_PRESENT 1U /*!< FPU present */
AnnaBridge 161:aa5281ff4a02 71 #endif /* __FPU_PRESENT */
AnnaBridge 163:e59c8e839560 72 /* MBED */
AnnaBridge 161:aa5281ff4a02 73
AnnaBridge 161:aa5281ff4a02 74 /**
AnnaBridge 161:aa5281ff4a02 75 * @}
AnnaBridge 161:aa5281ff4a02 76 */
AnnaBridge 161:aa5281ff4a02 77
AnnaBridge 161:aa5281ff4a02 78 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 161:aa5281ff4a02 79 * @{
AnnaBridge 161:aa5281ff4a02 80 */
AnnaBridge 161:aa5281ff4a02 81
AnnaBridge 161:aa5281ff4a02 82 /**
AnnaBridge 161:aa5281ff4a02 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
AnnaBridge 161:aa5281ff4a02 84 * in @ref Library_configuration_section
AnnaBridge 161:aa5281ff4a02 85 */
AnnaBridge 161:aa5281ff4a02 86 typedef enum
AnnaBridge 161:aa5281ff4a02 87 {
AnnaBridge 161:aa5281ff4a02 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 161:aa5281ff4a02 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 161:aa5281ff4a02 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 161:aa5281ff4a02 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 161:aa5281ff4a02 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 161:aa5281ff4a02 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 161:aa5281ff4a02 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 161:aa5281ff4a02 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 161:aa5281ff4a02 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 161:aa5281ff4a02 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 161:aa5281ff4a02 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 161:aa5281ff4a02 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 161:aa5281ff4a02 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 161:aa5281ff4a02 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 161:aa5281ff4a02 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 161:aa5281ff4a02 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 161:aa5281ff4a02 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 161:aa5281ff4a02 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 161:aa5281ff4a02 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 161:aa5281ff4a02 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 161:aa5281ff4a02 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 161:aa5281ff4a02 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
AnnaBridge 161:aa5281ff4a02 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
AnnaBridge 161:aa5281ff4a02 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
AnnaBridge 161:aa5281ff4a02 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
AnnaBridge 161:aa5281ff4a02 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
AnnaBridge 161:aa5281ff4a02 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
AnnaBridge 161:aa5281ff4a02 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
AnnaBridge 161:aa5281ff4a02 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
AnnaBridge 161:aa5281ff4a02 117 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
AnnaBridge 161:aa5281ff4a02 118 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
AnnaBridge 161:aa5281ff4a02 119 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
AnnaBridge 161:aa5281ff4a02 120 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
AnnaBridge 161:aa5281ff4a02 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 161:aa5281ff4a02 122 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
AnnaBridge 161:aa5281ff4a02 123 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
AnnaBridge 161:aa5281ff4a02 124 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
AnnaBridge 161:aa5281ff4a02 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 161:aa5281ff4a02 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 161:aa5281ff4a02 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 161:aa5281ff4a02 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
AnnaBridge 161:aa5281ff4a02 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 161:aa5281ff4a02 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 161:aa5281ff4a02 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 161:aa5281ff4a02 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 161:aa5281ff4a02 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 161:aa5281ff4a02 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 161:aa5281ff4a02 135 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 161:aa5281ff4a02 136 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 161:aa5281ff4a02 137 USART3_IRQn = 39, /*!< USART3 global Interrupt */
AnnaBridge 161:aa5281ff4a02 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 161:aa5281ff4a02 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 161:aa5281ff4a02 140 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
AnnaBridge 161:aa5281ff4a02 141 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
AnnaBridge 161:aa5281ff4a02 142 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
AnnaBridge 161:aa5281ff4a02 143 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
AnnaBridge 161:aa5281ff4a02 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
AnnaBridge 161:aa5281ff4a02 145 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
AnnaBridge 161:aa5281ff4a02 146 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
AnnaBridge 161:aa5281ff4a02 147 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
AnnaBridge 161:aa5281ff4a02 148 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
AnnaBridge 161:aa5281ff4a02 149 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
AnnaBridge 161:aa5281ff4a02 150 UART4_IRQn = 52, /*!< UART4 global Interrupt */
AnnaBridge 161:aa5281ff4a02 151 UART5_IRQn = 53, /*!< UART5 global Interrupt */
AnnaBridge 161:aa5281ff4a02 152 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
AnnaBridge 161:aa5281ff4a02 153 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
AnnaBridge 161:aa5281ff4a02 154 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
AnnaBridge 161:aa5281ff4a02 155 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
AnnaBridge 161:aa5281ff4a02 156 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
AnnaBridge 161:aa5281ff4a02 157 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
AnnaBridge 161:aa5281ff4a02 158 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
AnnaBridge 161:aa5281ff4a02 159 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
AnnaBridge 161:aa5281ff4a02 160 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
AnnaBridge 161:aa5281ff4a02 161 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
AnnaBridge 161:aa5281ff4a02 162 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
AnnaBridge 161:aa5281ff4a02 163 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
AnnaBridge 161:aa5281ff4a02 164 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
AnnaBridge 161:aa5281ff4a02 165 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
AnnaBridge 161:aa5281ff4a02 166 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
AnnaBridge 161:aa5281ff4a02 167 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
AnnaBridge 161:aa5281ff4a02 168 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
AnnaBridge 161:aa5281ff4a02 169 USART6_IRQn = 71, /*!< USART6 global interrupt */
AnnaBridge 161:aa5281ff4a02 170 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
AnnaBridge 161:aa5281ff4a02 171 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 161:aa5281ff4a02 172 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
AnnaBridge 161:aa5281ff4a02 173 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
AnnaBridge 161:aa5281ff4a02 174 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
AnnaBridge 161:aa5281ff4a02 175 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
AnnaBridge 161:aa5281ff4a02 176 DCMI_IRQn = 78, /*!< DCMI global interrupt */
AnnaBridge 163:e59c8e839560 177 RNG_IRQn = 80, /*!< RNG global Interrupt */
AnnaBridge 161:aa5281ff4a02 178 FPU_IRQn = 81 /*!< FPU global interrupt */
AnnaBridge 161:aa5281ff4a02 179 } IRQn_Type;
AnnaBridge 163:e59c8e839560 180 /* Legacy define */
AnnaBridge 163:e59c8e839560 181 #define HASH_RNG_IRQn RNG_IRQn
AnnaBridge 161:aa5281ff4a02 182
AnnaBridge 161:aa5281ff4a02 183 /**
AnnaBridge 161:aa5281ff4a02 184 * @}
AnnaBridge 161:aa5281ff4a02 185 */
AnnaBridge 161:aa5281ff4a02 186
AnnaBridge 161:aa5281ff4a02 187 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 161:aa5281ff4a02 188 #include "system_stm32f4xx.h"
AnnaBridge 161:aa5281ff4a02 189 #include <stdint.h>
AnnaBridge 161:aa5281ff4a02 190
AnnaBridge 161:aa5281ff4a02 191 /** @addtogroup Peripheral_registers_structures
AnnaBridge 161:aa5281ff4a02 192 * @{
AnnaBridge 161:aa5281ff4a02 193 */
AnnaBridge 161:aa5281ff4a02 194
AnnaBridge 161:aa5281ff4a02 195 /**
AnnaBridge 161:aa5281ff4a02 196 * @brief Analog to Digital Converter
AnnaBridge 161:aa5281ff4a02 197 */
AnnaBridge 161:aa5281ff4a02 198
AnnaBridge 161:aa5281ff4a02 199 typedef struct
AnnaBridge 161:aa5281ff4a02 200 {
AnnaBridge 161:aa5281ff4a02 201 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 202 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 203 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 204 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 205 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 206 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 207 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 208 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 209 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 210 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
AnnaBridge 161:aa5281ff4a02 211 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
AnnaBridge 161:aa5281ff4a02 212 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
AnnaBridge 161:aa5281ff4a02 213 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
AnnaBridge 161:aa5281ff4a02 214 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
AnnaBridge 161:aa5281ff4a02 215 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
AnnaBridge 161:aa5281ff4a02 216 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
AnnaBridge 161:aa5281ff4a02 217 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
AnnaBridge 161:aa5281ff4a02 218 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
AnnaBridge 161:aa5281ff4a02 219 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
AnnaBridge 161:aa5281ff4a02 220 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
AnnaBridge 161:aa5281ff4a02 221 } ADC_TypeDef;
AnnaBridge 161:aa5281ff4a02 222
AnnaBridge 161:aa5281ff4a02 223 typedef struct
AnnaBridge 161:aa5281ff4a02 224 {
AnnaBridge 161:aa5281ff4a02 225 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
AnnaBridge 161:aa5281ff4a02 226 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
AnnaBridge 161:aa5281ff4a02 227 __IO uint32_t CDR; /*!< ADC common regular data register for dual
AnnaBridge 161:aa5281ff4a02 228 AND triple modes, Address offset: ADC1 base address + 0x308 */
AnnaBridge 161:aa5281ff4a02 229 } ADC_Common_TypeDef;
AnnaBridge 161:aa5281ff4a02 230
AnnaBridge 161:aa5281ff4a02 231
AnnaBridge 161:aa5281ff4a02 232 /**
AnnaBridge 161:aa5281ff4a02 233 * @brief Controller Area Network TxMailBox
AnnaBridge 161:aa5281ff4a02 234 */
AnnaBridge 161:aa5281ff4a02 235
AnnaBridge 161:aa5281ff4a02 236 typedef struct
AnnaBridge 161:aa5281ff4a02 237 {
AnnaBridge 161:aa5281ff4a02 238 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
AnnaBridge 161:aa5281ff4a02 239 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
AnnaBridge 161:aa5281ff4a02 240 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
AnnaBridge 161:aa5281ff4a02 241 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
AnnaBridge 161:aa5281ff4a02 242 } CAN_TxMailBox_TypeDef;
AnnaBridge 161:aa5281ff4a02 243
AnnaBridge 161:aa5281ff4a02 244 /**
AnnaBridge 161:aa5281ff4a02 245 * @brief Controller Area Network FIFOMailBox
AnnaBridge 161:aa5281ff4a02 246 */
AnnaBridge 161:aa5281ff4a02 247
AnnaBridge 161:aa5281ff4a02 248 typedef struct
AnnaBridge 161:aa5281ff4a02 249 {
AnnaBridge 161:aa5281ff4a02 250 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
AnnaBridge 161:aa5281ff4a02 251 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
AnnaBridge 161:aa5281ff4a02 252 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
AnnaBridge 161:aa5281ff4a02 253 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
AnnaBridge 161:aa5281ff4a02 254 } CAN_FIFOMailBox_TypeDef;
AnnaBridge 161:aa5281ff4a02 255
AnnaBridge 161:aa5281ff4a02 256 /**
AnnaBridge 161:aa5281ff4a02 257 * @brief Controller Area Network FilterRegister
AnnaBridge 161:aa5281ff4a02 258 */
AnnaBridge 161:aa5281ff4a02 259
AnnaBridge 161:aa5281ff4a02 260 typedef struct
AnnaBridge 161:aa5281ff4a02 261 {
AnnaBridge 161:aa5281ff4a02 262 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
AnnaBridge 161:aa5281ff4a02 263 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
AnnaBridge 161:aa5281ff4a02 264 } CAN_FilterRegister_TypeDef;
AnnaBridge 161:aa5281ff4a02 265
AnnaBridge 161:aa5281ff4a02 266 /**
AnnaBridge 161:aa5281ff4a02 267 * @brief Controller Area Network
AnnaBridge 161:aa5281ff4a02 268 */
AnnaBridge 161:aa5281ff4a02 269
AnnaBridge 161:aa5281ff4a02 270 typedef struct
AnnaBridge 161:aa5281ff4a02 271 {
AnnaBridge 161:aa5281ff4a02 272 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 273 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 274 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 275 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 276 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 277 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 278 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 279 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 280 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
AnnaBridge 161:aa5281ff4a02 281 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
AnnaBridge 161:aa5281ff4a02 282 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
AnnaBridge 161:aa5281ff4a02 283 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
AnnaBridge 161:aa5281ff4a02 284 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
AnnaBridge 161:aa5281ff4a02 285 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
AnnaBridge 161:aa5281ff4a02 286 uint32_t RESERVED2; /*!< Reserved, 0x208 */
AnnaBridge 161:aa5281ff4a02 287 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
AnnaBridge 161:aa5281ff4a02 288 uint32_t RESERVED3; /*!< Reserved, 0x210 */
AnnaBridge 161:aa5281ff4a02 289 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
AnnaBridge 161:aa5281ff4a02 290 uint32_t RESERVED4; /*!< Reserved, 0x218 */
AnnaBridge 161:aa5281ff4a02 291 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
AnnaBridge 161:aa5281ff4a02 292 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
AnnaBridge 161:aa5281ff4a02 293 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
AnnaBridge 161:aa5281ff4a02 294 } CAN_TypeDef;
AnnaBridge 161:aa5281ff4a02 295
AnnaBridge 161:aa5281ff4a02 296 /**
AnnaBridge 161:aa5281ff4a02 297 * @brief CRC calculation unit
AnnaBridge 161:aa5281ff4a02 298 */
AnnaBridge 161:aa5281ff4a02 299
AnnaBridge 161:aa5281ff4a02 300 typedef struct
AnnaBridge 161:aa5281ff4a02 301 {
AnnaBridge 161:aa5281ff4a02 302 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 303 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 304 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 161:aa5281ff4a02 305 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 161:aa5281ff4a02 306 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 307 } CRC_TypeDef;
AnnaBridge 161:aa5281ff4a02 308
AnnaBridge 161:aa5281ff4a02 309 /**
AnnaBridge 161:aa5281ff4a02 310 * @brief Digital to Analog Converter
AnnaBridge 161:aa5281ff4a02 311 */
AnnaBridge 161:aa5281ff4a02 312
AnnaBridge 161:aa5281ff4a02 313 typedef struct
AnnaBridge 161:aa5281ff4a02 314 {
AnnaBridge 161:aa5281ff4a02 315 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 316 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 317 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 318 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 319 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 320 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 321 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 322 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 323 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 324 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 161:aa5281ff4a02 325 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 161:aa5281ff4a02 326 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 161:aa5281ff4a02 327 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 161:aa5281ff4a02 328 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 161:aa5281ff4a02 329 } DAC_TypeDef;
AnnaBridge 161:aa5281ff4a02 330
AnnaBridge 161:aa5281ff4a02 331 /**
AnnaBridge 161:aa5281ff4a02 332 * @brief Debug MCU
AnnaBridge 161:aa5281ff4a02 333 */
AnnaBridge 161:aa5281ff4a02 334
AnnaBridge 161:aa5281ff4a02 335 typedef struct
AnnaBridge 161:aa5281ff4a02 336 {
AnnaBridge 161:aa5281ff4a02 337 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 338 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 339 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 340 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 341 }DBGMCU_TypeDef;
AnnaBridge 161:aa5281ff4a02 342
AnnaBridge 161:aa5281ff4a02 343 /**
AnnaBridge 161:aa5281ff4a02 344 * @brief DCMI
AnnaBridge 161:aa5281ff4a02 345 */
AnnaBridge 161:aa5281ff4a02 346
AnnaBridge 161:aa5281ff4a02 347 typedef struct
AnnaBridge 161:aa5281ff4a02 348 {
AnnaBridge 161:aa5281ff4a02 349 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 350 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 351 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 352 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 353 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 354 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 355 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 356 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 357 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 358 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
AnnaBridge 161:aa5281ff4a02 359 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
AnnaBridge 161:aa5281ff4a02 360 } DCMI_TypeDef;
AnnaBridge 161:aa5281ff4a02 361
AnnaBridge 161:aa5281ff4a02 362 /**
AnnaBridge 161:aa5281ff4a02 363 * @brief DMA Controller
AnnaBridge 161:aa5281ff4a02 364 */
AnnaBridge 161:aa5281ff4a02 365
AnnaBridge 161:aa5281ff4a02 366 typedef struct
AnnaBridge 161:aa5281ff4a02 367 {
AnnaBridge 161:aa5281ff4a02 368 __IO uint32_t CR; /*!< DMA stream x configuration register */
AnnaBridge 161:aa5281ff4a02 369 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
AnnaBridge 161:aa5281ff4a02 370 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
AnnaBridge 161:aa5281ff4a02 371 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
AnnaBridge 161:aa5281ff4a02 372 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
AnnaBridge 161:aa5281ff4a02 373 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
AnnaBridge 161:aa5281ff4a02 374 } DMA_Stream_TypeDef;
AnnaBridge 161:aa5281ff4a02 375
AnnaBridge 161:aa5281ff4a02 376 typedef struct
AnnaBridge 161:aa5281ff4a02 377 {
AnnaBridge 161:aa5281ff4a02 378 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 379 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 380 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 381 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 382 } DMA_TypeDef;
AnnaBridge 161:aa5281ff4a02 383
AnnaBridge 161:aa5281ff4a02 384 /**
AnnaBridge 161:aa5281ff4a02 385 * @brief Ethernet MAC
AnnaBridge 161:aa5281ff4a02 386 */
AnnaBridge 161:aa5281ff4a02 387
AnnaBridge 161:aa5281ff4a02 388 typedef struct
AnnaBridge 161:aa5281ff4a02 389 {
AnnaBridge 161:aa5281ff4a02 390 __IO uint32_t MACCR;
AnnaBridge 161:aa5281ff4a02 391 __IO uint32_t MACFFR;
AnnaBridge 161:aa5281ff4a02 392 __IO uint32_t MACHTHR;
AnnaBridge 161:aa5281ff4a02 393 __IO uint32_t MACHTLR;
AnnaBridge 161:aa5281ff4a02 394 __IO uint32_t MACMIIAR;
AnnaBridge 161:aa5281ff4a02 395 __IO uint32_t MACMIIDR;
AnnaBridge 161:aa5281ff4a02 396 __IO uint32_t MACFCR;
AnnaBridge 161:aa5281ff4a02 397 __IO uint32_t MACVLANTR; /* 8 */
AnnaBridge 161:aa5281ff4a02 398 uint32_t RESERVED0[2];
AnnaBridge 161:aa5281ff4a02 399 __IO uint32_t MACRWUFFR; /* 11 */
AnnaBridge 161:aa5281ff4a02 400 __IO uint32_t MACPMTCSR;
AnnaBridge 161:aa5281ff4a02 401 uint32_t RESERVED1;
AnnaBridge 161:aa5281ff4a02 402 __IO uint32_t MACDBGR;
AnnaBridge 161:aa5281ff4a02 403 __IO uint32_t MACSR; /* 15 */
AnnaBridge 161:aa5281ff4a02 404 __IO uint32_t MACIMR;
AnnaBridge 161:aa5281ff4a02 405 __IO uint32_t MACA0HR;
AnnaBridge 161:aa5281ff4a02 406 __IO uint32_t MACA0LR;
AnnaBridge 161:aa5281ff4a02 407 __IO uint32_t MACA1HR;
AnnaBridge 161:aa5281ff4a02 408 __IO uint32_t MACA1LR;
AnnaBridge 161:aa5281ff4a02 409 __IO uint32_t MACA2HR;
AnnaBridge 161:aa5281ff4a02 410 __IO uint32_t MACA2LR;
AnnaBridge 161:aa5281ff4a02 411 __IO uint32_t MACA3HR;
AnnaBridge 161:aa5281ff4a02 412 __IO uint32_t MACA3LR; /* 24 */
AnnaBridge 161:aa5281ff4a02 413 uint32_t RESERVED2[40];
AnnaBridge 161:aa5281ff4a02 414 __IO uint32_t MMCCR; /* 65 */
AnnaBridge 161:aa5281ff4a02 415 __IO uint32_t MMCRIR;
AnnaBridge 161:aa5281ff4a02 416 __IO uint32_t MMCTIR;
AnnaBridge 161:aa5281ff4a02 417 __IO uint32_t MMCRIMR;
AnnaBridge 161:aa5281ff4a02 418 __IO uint32_t MMCTIMR; /* 69 */
AnnaBridge 161:aa5281ff4a02 419 uint32_t RESERVED3[14];
AnnaBridge 161:aa5281ff4a02 420 __IO uint32_t MMCTGFSCCR; /* 84 */
AnnaBridge 161:aa5281ff4a02 421 __IO uint32_t MMCTGFMSCCR;
AnnaBridge 161:aa5281ff4a02 422 uint32_t RESERVED4[5];
AnnaBridge 161:aa5281ff4a02 423 __IO uint32_t MMCTGFCR;
AnnaBridge 161:aa5281ff4a02 424 uint32_t RESERVED5[10];
AnnaBridge 161:aa5281ff4a02 425 __IO uint32_t MMCRFCECR;
AnnaBridge 161:aa5281ff4a02 426 __IO uint32_t MMCRFAECR;
AnnaBridge 161:aa5281ff4a02 427 uint32_t RESERVED6[10];
AnnaBridge 161:aa5281ff4a02 428 __IO uint32_t MMCRGUFCR;
AnnaBridge 161:aa5281ff4a02 429 uint32_t RESERVED7[334];
AnnaBridge 161:aa5281ff4a02 430 __IO uint32_t PTPTSCR;
AnnaBridge 161:aa5281ff4a02 431 __IO uint32_t PTPSSIR;
AnnaBridge 161:aa5281ff4a02 432 __IO uint32_t PTPTSHR;
AnnaBridge 161:aa5281ff4a02 433 __IO uint32_t PTPTSLR;
AnnaBridge 161:aa5281ff4a02 434 __IO uint32_t PTPTSHUR;
AnnaBridge 161:aa5281ff4a02 435 __IO uint32_t PTPTSLUR;
AnnaBridge 161:aa5281ff4a02 436 __IO uint32_t PTPTSAR;
AnnaBridge 161:aa5281ff4a02 437 __IO uint32_t PTPTTHR;
AnnaBridge 161:aa5281ff4a02 438 __IO uint32_t PTPTTLR;
AnnaBridge 161:aa5281ff4a02 439 __IO uint32_t RESERVED8;
AnnaBridge 161:aa5281ff4a02 440 __IO uint32_t PTPTSSR;
AnnaBridge 161:aa5281ff4a02 441 uint32_t RESERVED9[565];
AnnaBridge 161:aa5281ff4a02 442 __IO uint32_t DMABMR;
AnnaBridge 161:aa5281ff4a02 443 __IO uint32_t DMATPDR;
AnnaBridge 161:aa5281ff4a02 444 __IO uint32_t DMARPDR;
AnnaBridge 161:aa5281ff4a02 445 __IO uint32_t DMARDLAR;
AnnaBridge 161:aa5281ff4a02 446 __IO uint32_t DMATDLAR;
AnnaBridge 161:aa5281ff4a02 447 __IO uint32_t DMASR;
AnnaBridge 161:aa5281ff4a02 448 __IO uint32_t DMAOMR;
AnnaBridge 161:aa5281ff4a02 449 __IO uint32_t DMAIER;
AnnaBridge 161:aa5281ff4a02 450 __IO uint32_t DMAMFBOCR;
AnnaBridge 161:aa5281ff4a02 451 __IO uint32_t DMARSWTR;
AnnaBridge 161:aa5281ff4a02 452 uint32_t RESERVED10[8];
AnnaBridge 161:aa5281ff4a02 453 __IO uint32_t DMACHTDR;
AnnaBridge 161:aa5281ff4a02 454 __IO uint32_t DMACHRDR;
AnnaBridge 161:aa5281ff4a02 455 __IO uint32_t DMACHTBAR;
AnnaBridge 161:aa5281ff4a02 456 __IO uint32_t DMACHRBAR;
AnnaBridge 161:aa5281ff4a02 457 } ETH_TypeDef;
AnnaBridge 161:aa5281ff4a02 458
AnnaBridge 161:aa5281ff4a02 459 /**
AnnaBridge 161:aa5281ff4a02 460 * @brief External Interrupt/Event Controller
AnnaBridge 161:aa5281ff4a02 461 */
AnnaBridge 161:aa5281ff4a02 462
AnnaBridge 161:aa5281ff4a02 463 typedef struct
AnnaBridge 161:aa5281ff4a02 464 {
AnnaBridge 161:aa5281ff4a02 465 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 466 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 467 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 468 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 469 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 470 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 471 } EXTI_TypeDef;
AnnaBridge 161:aa5281ff4a02 472
AnnaBridge 161:aa5281ff4a02 473 /**
AnnaBridge 161:aa5281ff4a02 474 * @brief FLASH Registers
AnnaBridge 161:aa5281ff4a02 475 */
AnnaBridge 161:aa5281ff4a02 476
AnnaBridge 161:aa5281ff4a02 477 typedef struct
AnnaBridge 161:aa5281ff4a02 478 {
AnnaBridge 161:aa5281ff4a02 479 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 480 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 481 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 482 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 483 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 484 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 485 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 486 } FLASH_TypeDef;
AnnaBridge 161:aa5281ff4a02 487
AnnaBridge 161:aa5281ff4a02 488
AnnaBridge 161:aa5281ff4a02 489
AnnaBridge 161:aa5281ff4a02 490 /**
AnnaBridge 161:aa5281ff4a02 491 * @brief Flexible Static Memory Controller
AnnaBridge 161:aa5281ff4a02 492 */
AnnaBridge 161:aa5281ff4a02 493
AnnaBridge 161:aa5281ff4a02 494 typedef struct
AnnaBridge 161:aa5281ff4a02 495 {
AnnaBridge 161:aa5281ff4a02 496 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
AnnaBridge 161:aa5281ff4a02 497 } FSMC_Bank1_TypeDef;
AnnaBridge 161:aa5281ff4a02 498
AnnaBridge 161:aa5281ff4a02 499 /**
AnnaBridge 161:aa5281ff4a02 500 * @brief Flexible Static Memory Controller Bank1E
AnnaBridge 161:aa5281ff4a02 501 */
AnnaBridge 161:aa5281ff4a02 502
AnnaBridge 161:aa5281ff4a02 503 typedef struct
AnnaBridge 161:aa5281ff4a02 504 {
AnnaBridge 161:aa5281ff4a02 505 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
AnnaBridge 161:aa5281ff4a02 506 } FSMC_Bank1E_TypeDef;
AnnaBridge 161:aa5281ff4a02 507
AnnaBridge 161:aa5281ff4a02 508 /**
AnnaBridge 161:aa5281ff4a02 509 * @brief Flexible Static Memory Controller Bank2
AnnaBridge 161:aa5281ff4a02 510 */
AnnaBridge 161:aa5281ff4a02 511
AnnaBridge 161:aa5281ff4a02 512 typedef struct
AnnaBridge 161:aa5281ff4a02 513 {
AnnaBridge 161:aa5281ff4a02 514 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
AnnaBridge 161:aa5281ff4a02 515 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
AnnaBridge 161:aa5281ff4a02 516 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
AnnaBridge 161:aa5281ff4a02 517 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
AnnaBridge 161:aa5281ff4a02 518 uint32_t RESERVED0; /*!< Reserved, 0x70 */
AnnaBridge 161:aa5281ff4a02 519 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
AnnaBridge 161:aa5281ff4a02 520 uint32_t RESERVED1; /*!< Reserved, 0x78 */
AnnaBridge 161:aa5281ff4a02 521 uint32_t RESERVED2; /*!< Reserved, 0x7C */
AnnaBridge 161:aa5281ff4a02 522 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
AnnaBridge 161:aa5281ff4a02 523 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
AnnaBridge 161:aa5281ff4a02 524 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
AnnaBridge 161:aa5281ff4a02 525 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
AnnaBridge 161:aa5281ff4a02 526 uint32_t RESERVED3; /*!< Reserved, 0x90 */
AnnaBridge 161:aa5281ff4a02 527 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
AnnaBridge 161:aa5281ff4a02 528 } FSMC_Bank2_3_TypeDef;
AnnaBridge 161:aa5281ff4a02 529
AnnaBridge 161:aa5281ff4a02 530 /**
AnnaBridge 161:aa5281ff4a02 531 * @brief Flexible Static Memory Controller Bank4
AnnaBridge 161:aa5281ff4a02 532 */
AnnaBridge 161:aa5281ff4a02 533
AnnaBridge 161:aa5281ff4a02 534 typedef struct
AnnaBridge 161:aa5281ff4a02 535 {
AnnaBridge 161:aa5281ff4a02 536 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
AnnaBridge 161:aa5281ff4a02 537 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
AnnaBridge 161:aa5281ff4a02 538 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
AnnaBridge 161:aa5281ff4a02 539 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
AnnaBridge 161:aa5281ff4a02 540 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
AnnaBridge 161:aa5281ff4a02 541 } FSMC_Bank4_TypeDef;
AnnaBridge 161:aa5281ff4a02 542
AnnaBridge 161:aa5281ff4a02 543 /**
AnnaBridge 161:aa5281ff4a02 544 * @brief General Purpose I/O
AnnaBridge 161:aa5281ff4a02 545 */
AnnaBridge 161:aa5281ff4a02 546
AnnaBridge 161:aa5281ff4a02 547 typedef struct
AnnaBridge 161:aa5281ff4a02 548 {
AnnaBridge 161:aa5281ff4a02 549 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 550 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 551 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 552 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 553 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 554 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 555 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 556 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 557 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 161:aa5281ff4a02 558 } GPIO_TypeDef;
AnnaBridge 161:aa5281ff4a02 559
AnnaBridge 161:aa5281ff4a02 560 /**
AnnaBridge 161:aa5281ff4a02 561 * @brief System configuration controller
AnnaBridge 161:aa5281ff4a02 562 */
AnnaBridge 161:aa5281ff4a02 563
AnnaBridge 161:aa5281ff4a02 564 typedef struct
AnnaBridge 161:aa5281ff4a02 565 {
AnnaBridge 161:aa5281ff4a02 566 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 567 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 568 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 161:aa5281ff4a02 569 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
AnnaBridge 161:aa5281ff4a02 570 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 571 } SYSCFG_TypeDef;
AnnaBridge 161:aa5281ff4a02 572
AnnaBridge 161:aa5281ff4a02 573 /**
AnnaBridge 161:aa5281ff4a02 574 * @brief Inter-integrated Circuit Interface
AnnaBridge 161:aa5281ff4a02 575 */
AnnaBridge 161:aa5281ff4a02 576
AnnaBridge 161:aa5281ff4a02 577 typedef struct
AnnaBridge 161:aa5281ff4a02 578 {
AnnaBridge 161:aa5281ff4a02 579 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 580 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 581 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 582 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 583 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 584 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 585 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 586 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 587 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 588 } I2C_TypeDef;
AnnaBridge 161:aa5281ff4a02 589
AnnaBridge 161:aa5281ff4a02 590 /**
AnnaBridge 161:aa5281ff4a02 591 * @brief Independent WATCHDOG
AnnaBridge 161:aa5281ff4a02 592 */
AnnaBridge 161:aa5281ff4a02 593
AnnaBridge 161:aa5281ff4a02 594 typedef struct
AnnaBridge 161:aa5281ff4a02 595 {
AnnaBridge 161:aa5281ff4a02 596 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 597 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 598 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 599 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 600 } IWDG_TypeDef;
AnnaBridge 161:aa5281ff4a02 601
AnnaBridge 161:aa5281ff4a02 602
AnnaBridge 161:aa5281ff4a02 603 /**
AnnaBridge 161:aa5281ff4a02 604 * @brief Power Control
AnnaBridge 161:aa5281ff4a02 605 */
AnnaBridge 161:aa5281ff4a02 606
AnnaBridge 161:aa5281ff4a02 607 typedef struct
AnnaBridge 161:aa5281ff4a02 608 {
AnnaBridge 161:aa5281ff4a02 609 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 610 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 611 } PWR_TypeDef;
AnnaBridge 161:aa5281ff4a02 612
AnnaBridge 161:aa5281ff4a02 613 /**
AnnaBridge 161:aa5281ff4a02 614 * @brief Reset and Clock Control
AnnaBridge 161:aa5281ff4a02 615 */
AnnaBridge 161:aa5281ff4a02 616
AnnaBridge 161:aa5281ff4a02 617 typedef struct
AnnaBridge 161:aa5281ff4a02 618 {
AnnaBridge 161:aa5281ff4a02 619 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 620 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 621 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 622 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 623 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 624 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 625 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 626 uint32_t RESERVED0; /*!< Reserved, 0x1C */
AnnaBridge 161:aa5281ff4a02 627 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 628 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
AnnaBridge 161:aa5281ff4a02 629 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
AnnaBridge 161:aa5281ff4a02 630 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
AnnaBridge 161:aa5281ff4a02 631 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
AnnaBridge 161:aa5281ff4a02 632 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
AnnaBridge 161:aa5281ff4a02 633 uint32_t RESERVED2; /*!< Reserved, 0x3C */
AnnaBridge 161:aa5281ff4a02 634 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
AnnaBridge 161:aa5281ff4a02 635 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
AnnaBridge 161:aa5281ff4a02 636 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
AnnaBridge 161:aa5281ff4a02 637 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
AnnaBridge 161:aa5281ff4a02 638 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
AnnaBridge 161:aa5281ff4a02 639 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
AnnaBridge 161:aa5281ff4a02 640 uint32_t RESERVED4; /*!< Reserved, 0x5C */
AnnaBridge 161:aa5281ff4a02 641 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
AnnaBridge 161:aa5281ff4a02 642 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
AnnaBridge 161:aa5281ff4a02 643 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
AnnaBridge 161:aa5281ff4a02 644 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
AnnaBridge 161:aa5281ff4a02 645 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
AnnaBridge 161:aa5281ff4a02 646 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
AnnaBridge 161:aa5281ff4a02 647 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
AnnaBridge 161:aa5281ff4a02 648 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
AnnaBridge 161:aa5281ff4a02 649 } RCC_TypeDef;
AnnaBridge 161:aa5281ff4a02 650
AnnaBridge 161:aa5281ff4a02 651 /**
AnnaBridge 161:aa5281ff4a02 652 * @brief Real-Time Clock
AnnaBridge 161:aa5281ff4a02 653 */
AnnaBridge 161:aa5281ff4a02 654
AnnaBridge 161:aa5281ff4a02 655 typedef struct
AnnaBridge 161:aa5281ff4a02 656 {
AnnaBridge 161:aa5281ff4a02 657 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 658 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 659 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 660 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 661 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 662 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 663 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 664 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 665 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 666 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 161:aa5281ff4a02 667 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 161:aa5281ff4a02 668 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 161:aa5281ff4a02 669 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 161:aa5281ff4a02 670 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 161:aa5281ff4a02 671 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 161:aa5281ff4a02 672 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 161:aa5281ff4a02 673 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
AnnaBridge 161:aa5281ff4a02 674 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 161:aa5281ff4a02 675 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 161:aa5281ff4a02 676 uint32_t RESERVED7; /*!< Reserved, 0x4C */
AnnaBridge 161:aa5281ff4a02 677 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
AnnaBridge 161:aa5281ff4a02 678 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 161:aa5281ff4a02 679 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 161:aa5281ff4a02 680 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 161:aa5281ff4a02 681 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 161:aa5281ff4a02 682 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 161:aa5281ff4a02 683 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 161:aa5281ff4a02 684 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 161:aa5281ff4a02 685 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 161:aa5281ff4a02 686 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 161:aa5281ff4a02 687 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 161:aa5281ff4a02 688 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 161:aa5281ff4a02 689 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 161:aa5281ff4a02 690 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 161:aa5281ff4a02 691 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 161:aa5281ff4a02 692 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 161:aa5281ff4a02 693 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 161:aa5281ff4a02 694 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 161:aa5281ff4a02 695 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 161:aa5281ff4a02 696 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 161:aa5281ff4a02 697 } RTC_TypeDef;
AnnaBridge 161:aa5281ff4a02 698
AnnaBridge 161:aa5281ff4a02 699 /**
AnnaBridge 161:aa5281ff4a02 700 * @brief SD host Interface
AnnaBridge 161:aa5281ff4a02 701 */
AnnaBridge 161:aa5281ff4a02 702
AnnaBridge 161:aa5281ff4a02 703 typedef struct
AnnaBridge 161:aa5281ff4a02 704 {
AnnaBridge 161:aa5281ff4a02 705 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 706 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 707 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 708 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 709 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 710 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 711 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 712 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 713 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 714 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
AnnaBridge 161:aa5281ff4a02 715 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
AnnaBridge 161:aa5281ff4a02 716 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
AnnaBridge 161:aa5281ff4a02 717 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
AnnaBridge 161:aa5281ff4a02 718 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
AnnaBridge 161:aa5281ff4a02 719 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
AnnaBridge 161:aa5281ff4a02 720 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
AnnaBridge 161:aa5281ff4a02 721 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
AnnaBridge 161:aa5281ff4a02 722 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
AnnaBridge 161:aa5281ff4a02 723 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
AnnaBridge 161:aa5281ff4a02 724 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
AnnaBridge 161:aa5281ff4a02 725 } SDIO_TypeDef;
AnnaBridge 161:aa5281ff4a02 726
AnnaBridge 161:aa5281ff4a02 727 /**
AnnaBridge 161:aa5281ff4a02 728 * @brief Serial Peripheral Interface
AnnaBridge 161:aa5281ff4a02 729 */
AnnaBridge 161:aa5281ff4a02 730
AnnaBridge 161:aa5281ff4a02 731 typedef struct
AnnaBridge 161:aa5281ff4a02 732 {
AnnaBridge 161:aa5281ff4a02 733 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 734 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 735 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 736 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 737 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 738 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 739 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 740 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 741 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 742 } SPI_TypeDef;
AnnaBridge 161:aa5281ff4a02 743
AnnaBridge 161:aa5281ff4a02 744
AnnaBridge 161:aa5281ff4a02 745 /**
AnnaBridge 161:aa5281ff4a02 746 * @brief TIM
AnnaBridge 161:aa5281ff4a02 747 */
AnnaBridge 161:aa5281ff4a02 748
AnnaBridge 161:aa5281ff4a02 749 typedef struct
AnnaBridge 161:aa5281ff4a02 750 {
AnnaBridge 161:aa5281ff4a02 751 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 752 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 753 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 754 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 755 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 756 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 757 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 758 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 161:aa5281ff4a02 759 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 161:aa5281ff4a02 760 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 161:aa5281ff4a02 761 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 161:aa5281ff4a02 762 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 161:aa5281ff4a02 763 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 161:aa5281ff4a02 764 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 161:aa5281ff4a02 765 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 161:aa5281ff4a02 766 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 161:aa5281ff4a02 767 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 161:aa5281ff4a02 768 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 161:aa5281ff4a02 769 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 161:aa5281ff4a02 770 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 161:aa5281ff4a02 771 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 161:aa5281ff4a02 772 } TIM_TypeDef;
AnnaBridge 161:aa5281ff4a02 773
AnnaBridge 161:aa5281ff4a02 774 /**
AnnaBridge 161:aa5281ff4a02 775 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 161:aa5281ff4a02 776 */
AnnaBridge 161:aa5281ff4a02 777
AnnaBridge 161:aa5281ff4a02 778 typedef struct
AnnaBridge 161:aa5281ff4a02 779 {
AnnaBridge 161:aa5281ff4a02 780 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 781 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 782 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 783 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
AnnaBridge 161:aa5281ff4a02 784 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
AnnaBridge 161:aa5281ff4a02 785 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
AnnaBridge 161:aa5281ff4a02 786 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
AnnaBridge 161:aa5281ff4a02 787 } USART_TypeDef;
AnnaBridge 161:aa5281ff4a02 788
AnnaBridge 161:aa5281ff4a02 789 /**
AnnaBridge 161:aa5281ff4a02 790 * @brief Window WATCHDOG
AnnaBridge 161:aa5281ff4a02 791 */
AnnaBridge 161:aa5281ff4a02 792
AnnaBridge 161:aa5281ff4a02 793 typedef struct
AnnaBridge 161:aa5281ff4a02 794 {
AnnaBridge 161:aa5281ff4a02 795 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 796 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 797 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 798 } WWDG_TypeDef;
AnnaBridge 161:aa5281ff4a02 799
AnnaBridge 161:aa5281ff4a02 800 /**
AnnaBridge 161:aa5281ff4a02 801 * @brief RNG
AnnaBridge 161:aa5281ff4a02 802 */
AnnaBridge 161:aa5281ff4a02 803
AnnaBridge 161:aa5281ff4a02 804 typedef struct
AnnaBridge 161:aa5281ff4a02 805 {
AnnaBridge 161:aa5281ff4a02 806 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 161:aa5281ff4a02 807 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 161:aa5281ff4a02 808 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 161:aa5281ff4a02 809 } RNG_TypeDef;
AnnaBridge 161:aa5281ff4a02 810
AnnaBridge 161:aa5281ff4a02 811 /**
AnnaBridge 161:aa5281ff4a02 812 * @brief USB_OTG_Core_Registers
AnnaBridge 161:aa5281ff4a02 813 */
AnnaBridge 161:aa5281ff4a02 814 typedef struct
AnnaBridge 161:aa5281ff4a02 815 {
AnnaBridge 161:aa5281ff4a02 816 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 161:aa5281ff4a02 817 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 161:aa5281ff4a02 818 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 161:aa5281ff4a02 819 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 161:aa5281ff4a02 820 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 161:aa5281ff4a02 821 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 161:aa5281ff4a02 822 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 161:aa5281ff4a02 823 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 161:aa5281ff4a02 824 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 161:aa5281ff4a02 825 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 161:aa5281ff4a02 826 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 161:aa5281ff4a02 827 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 161:aa5281ff4a02 828 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 161:aa5281ff4a02 829 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 161:aa5281ff4a02 830 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 161:aa5281ff4a02 831 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
AnnaBridge 161:aa5281ff4a02 832 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 161:aa5281ff4a02 833 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 161:aa5281ff4a02 834 } USB_OTG_GlobalTypeDef;
AnnaBridge 161:aa5281ff4a02 835
AnnaBridge 161:aa5281ff4a02 836 /**
AnnaBridge 161:aa5281ff4a02 837 * @brief USB_OTG_device_Registers
AnnaBridge 161:aa5281ff4a02 838 */
AnnaBridge 161:aa5281ff4a02 839 typedef struct
AnnaBridge 161:aa5281ff4a02 840 {
AnnaBridge 161:aa5281ff4a02 841 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 161:aa5281ff4a02 842 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 161:aa5281ff4a02 843 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 161:aa5281ff4a02 844 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 161:aa5281ff4a02 845 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 161:aa5281ff4a02 846 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 161:aa5281ff4a02 847 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 161:aa5281ff4a02 848 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 161:aa5281ff4a02 849 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 161:aa5281ff4a02 850 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 161:aa5281ff4a02 851 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 161:aa5281ff4a02 852 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 161:aa5281ff4a02 853 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 161:aa5281ff4a02 854 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 161:aa5281ff4a02 855 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 161:aa5281ff4a02 856 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 161:aa5281ff4a02 857 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 161:aa5281ff4a02 858 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 161:aa5281ff4a02 859 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 161:aa5281ff4a02 860 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 161:aa5281ff4a02 861 } USB_OTG_DeviceTypeDef;
AnnaBridge 161:aa5281ff4a02 862
AnnaBridge 161:aa5281ff4a02 863 /**
AnnaBridge 161:aa5281ff4a02 864 * @brief USB_OTG_IN_Endpoint-Specific_Register
AnnaBridge 161:aa5281ff4a02 865 */
AnnaBridge 161:aa5281ff4a02 866 typedef struct
AnnaBridge 161:aa5281ff4a02 867 {
AnnaBridge 161:aa5281ff4a02 868 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 161:aa5281ff4a02 869 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 161:aa5281ff4a02 870 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 161:aa5281ff4a02 871 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 161:aa5281ff4a02 872 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 161:aa5281ff4a02 873 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 161:aa5281ff4a02 874 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 161:aa5281ff4a02 875 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 161:aa5281ff4a02 876 } USB_OTG_INEndpointTypeDef;
AnnaBridge 161:aa5281ff4a02 877
AnnaBridge 161:aa5281ff4a02 878 /**
AnnaBridge 161:aa5281ff4a02 879 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
AnnaBridge 161:aa5281ff4a02 880 */
AnnaBridge 161:aa5281ff4a02 881 typedef struct
AnnaBridge 161:aa5281ff4a02 882 {
AnnaBridge 161:aa5281ff4a02 883 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 161:aa5281ff4a02 884 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 161:aa5281ff4a02 885 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 161:aa5281ff4a02 886 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 161:aa5281ff4a02 887 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 161:aa5281ff4a02 888 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 161:aa5281ff4a02 889 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 161:aa5281ff4a02 890 } USB_OTG_OUTEndpointTypeDef;
AnnaBridge 161:aa5281ff4a02 891
AnnaBridge 161:aa5281ff4a02 892 /**
AnnaBridge 161:aa5281ff4a02 893 * @brief USB_OTG_Host_Mode_Register_Structures
AnnaBridge 161:aa5281ff4a02 894 */
AnnaBridge 161:aa5281ff4a02 895 typedef struct
AnnaBridge 161:aa5281ff4a02 896 {
AnnaBridge 161:aa5281ff4a02 897 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 161:aa5281ff4a02 898 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 161:aa5281ff4a02 899 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 161:aa5281ff4a02 900 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 161:aa5281ff4a02 901 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 161:aa5281ff4a02 902 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 161:aa5281ff4a02 903 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 161:aa5281ff4a02 904 } USB_OTG_HostTypeDef;
AnnaBridge 161:aa5281ff4a02 905
AnnaBridge 161:aa5281ff4a02 906 /**
AnnaBridge 161:aa5281ff4a02 907 * @brief USB_OTG_Host_Channel_Specific_Registers
AnnaBridge 161:aa5281ff4a02 908 */
AnnaBridge 161:aa5281ff4a02 909 typedef struct
AnnaBridge 161:aa5281ff4a02 910 {
AnnaBridge 161:aa5281ff4a02 911 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 161:aa5281ff4a02 912 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 161:aa5281ff4a02 913 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 161:aa5281ff4a02 914 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 161:aa5281ff4a02 915 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 161:aa5281ff4a02 916 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 161:aa5281ff4a02 917 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 161:aa5281ff4a02 918 } USB_OTG_HostChannelTypeDef;
AnnaBridge 161:aa5281ff4a02 919
AnnaBridge 161:aa5281ff4a02 920 /**
AnnaBridge 161:aa5281ff4a02 921 * @}
AnnaBridge 161:aa5281ff4a02 922 */
AnnaBridge 161:aa5281ff4a02 923
AnnaBridge 161:aa5281ff4a02 924 /** @addtogroup Peripheral_memory_map
AnnaBridge 161:aa5281ff4a02 925 * @{
AnnaBridge 161:aa5281ff4a02 926 */
AnnaBridge 161:aa5281ff4a02 927 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
AnnaBridge 161:aa5281ff4a02 928 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
AnnaBridge 161:aa5281ff4a02 929 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
AnnaBridge 161:aa5281ff4a02 930 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
AnnaBridge 161:aa5281ff4a02 931 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
AnnaBridge 161:aa5281ff4a02 932 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
AnnaBridge 161:aa5281ff4a02 933 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
AnnaBridge 161:aa5281ff4a02 934 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
AnnaBridge 161:aa5281ff4a02 935 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
AnnaBridge 161:aa5281ff4a02 936 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
AnnaBridge 161:aa5281ff4a02 937 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
AnnaBridge 161:aa5281ff4a02 938 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
AnnaBridge 161:aa5281ff4a02 939 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 161:aa5281ff4a02 940 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 161:aa5281ff4a02 941 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
AnnaBridge 161:aa5281ff4a02 942
AnnaBridge 161:aa5281ff4a02 943 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 944 #define SRAM_BASE SRAM1_BASE
AnnaBridge 161:aa5281ff4a02 945 #define SRAM_BB_BASE SRAM1_BB_BASE
AnnaBridge 161:aa5281ff4a02 946
AnnaBridge 161:aa5281ff4a02 947 /*!< Peripheral memory map */
AnnaBridge 161:aa5281ff4a02 948 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 161:aa5281ff4a02 949 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 161:aa5281ff4a02 950 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 161:aa5281ff4a02 951 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
AnnaBridge 161:aa5281ff4a02 952
AnnaBridge 161:aa5281ff4a02 953 /*!< APB1 peripherals */
AnnaBridge 161:aa5281ff4a02 954 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
AnnaBridge 161:aa5281ff4a02 955 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
AnnaBridge 161:aa5281ff4a02 956 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
AnnaBridge 161:aa5281ff4a02 957 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
AnnaBridge 161:aa5281ff4a02 958 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
AnnaBridge 161:aa5281ff4a02 959 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
AnnaBridge 161:aa5281ff4a02 960 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
AnnaBridge 161:aa5281ff4a02 961 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
AnnaBridge 161:aa5281ff4a02 962 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
AnnaBridge 161:aa5281ff4a02 963 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
AnnaBridge 161:aa5281ff4a02 964 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
AnnaBridge 161:aa5281ff4a02 965 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
AnnaBridge 161:aa5281ff4a02 966 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
AnnaBridge 161:aa5281ff4a02 967 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
AnnaBridge 161:aa5281ff4a02 968 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
AnnaBridge 161:aa5281ff4a02 969 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
AnnaBridge 161:aa5281ff4a02 970 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
AnnaBridge 161:aa5281ff4a02 971 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
AnnaBridge 161:aa5281ff4a02 972 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
AnnaBridge 161:aa5281ff4a02 973 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
AnnaBridge 161:aa5281ff4a02 974 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
AnnaBridge 161:aa5281ff4a02 975 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
AnnaBridge 161:aa5281ff4a02 976 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
AnnaBridge 161:aa5281ff4a02 977 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
AnnaBridge 161:aa5281ff4a02 978 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
AnnaBridge 161:aa5281ff4a02 979 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
AnnaBridge 161:aa5281ff4a02 980 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
AnnaBridge 161:aa5281ff4a02 981
AnnaBridge 161:aa5281ff4a02 982 /*!< APB2 peripherals */
AnnaBridge 161:aa5281ff4a02 983 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
AnnaBridge 161:aa5281ff4a02 984 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
AnnaBridge 161:aa5281ff4a02 985 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
AnnaBridge 161:aa5281ff4a02 986 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
AnnaBridge 161:aa5281ff4a02 987 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
AnnaBridge 161:aa5281ff4a02 988 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
AnnaBridge 161:aa5281ff4a02 989 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
AnnaBridge 161:aa5281ff4a02 990 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 161:aa5281ff4a02 991 /* Legacy define */
AnnaBridge 161:aa5281ff4a02 992 #define ADC_BASE ADC123_COMMON_BASE
AnnaBridge 161:aa5281ff4a02 993 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
AnnaBridge 161:aa5281ff4a02 994 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
AnnaBridge 161:aa5281ff4a02 995 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
AnnaBridge 161:aa5281ff4a02 996 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
AnnaBridge 161:aa5281ff4a02 997 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
AnnaBridge 161:aa5281ff4a02 998 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
AnnaBridge 161:aa5281ff4a02 999 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
AnnaBridge 161:aa5281ff4a02 1000
AnnaBridge 161:aa5281ff4a02 1001 /*!< AHB1 peripherals */
AnnaBridge 161:aa5281ff4a02 1002 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
AnnaBridge 161:aa5281ff4a02 1003 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
AnnaBridge 161:aa5281ff4a02 1004 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
AnnaBridge 161:aa5281ff4a02 1005 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
AnnaBridge 161:aa5281ff4a02 1006 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
AnnaBridge 161:aa5281ff4a02 1007 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
AnnaBridge 161:aa5281ff4a02 1008 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
AnnaBridge 161:aa5281ff4a02 1009 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
AnnaBridge 161:aa5281ff4a02 1010 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
AnnaBridge 161:aa5281ff4a02 1011 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
AnnaBridge 161:aa5281ff4a02 1012 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
AnnaBridge 161:aa5281ff4a02 1013 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
AnnaBridge 161:aa5281ff4a02 1014 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
AnnaBridge 161:aa5281ff4a02 1015 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
AnnaBridge 161:aa5281ff4a02 1016 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
AnnaBridge 161:aa5281ff4a02 1017 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
AnnaBridge 161:aa5281ff4a02 1018 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
AnnaBridge 161:aa5281ff4a02 1019 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
AnnaBridge 161:aa5281ff4a02 1020 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
AnnaBridge 161:aa5281ff4a02 1021 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
AnnaBridge 161:aa5281ff4a02 1022 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
AnnaBridge 161:aa5281ff4a02 1023 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
AnnaBridge 161:aa5281ff4a02 1024 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
AnnaBridge 161:aa5281ff4a02 1025 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
AnnaBridge 161:aa5281ff4a02 1026 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
AnnaBridge 161:aa5281ff4a02 1027 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
AnnaBridge 161:aa5281ff4a02 1028 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
AnnaBridge 161:aa5281ff4a02 1029 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
AnnaBridge 161:aa5281ff4a02 1030 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
AnnaBridge 161:aa5281ff4a02 1031 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
AnnaBridge 161:aa5281ff4a02 1032 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
AnnaBridge 161:aa5281ff4a02 1033 #define ETH_MAC_BASE (ETH_BASE)
AnnaBridge 161:aa5281ff4a02 1034 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
AnnaBridge 161:aa5281ff4a02 1035 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
AnnaBridge 161:aa5281ff4a02 1036 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
AnnaBridge 161:aa5281ff4a02 1037
AnnaBridge 161:aa5281ff4a02 1038 /*!< AHB2 peripherals */
AnnaBridge 161:aa5281ff4a02 1039 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
AnnaBridge 161:aa5281ff4a02 1040 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
AnnaBridge 161:aa5281ff4a02 1041
AnnaBridge 161:aa5281ff4a02 1042 /*!< FSMC Bankx registers base address */
AnnaBridge 161:aa5281ff4a02 1043 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
AnnaBridge 161:aa5281ff4a02 1044 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
AnnaBridge 161:aa5281ff4a02 1045 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
AnnaBridge 161:aa5281ff4a02 1046 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
AnnaBridge 161:aa5281ff4a02 1047
AnnaBridge 161:aa5281ff4a02 1048
AnnaBridge 161:aa5281ff4a02 1049 /*!< Debug MCU registers base address */
AnnaBridge 161:aa5281ff4a02 1050 #define DBGMCU_BASE 0xE0042000U
AnnaBridge 161:aa5281ff4a02 1051 /*!< USB registers base address */
AnnaBridge 161:aa5281ff4a02 1052 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
AnnaBridge 161:aa5281ff4a02 1053 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
AnnaBridge 161:aa5281ff4a02 1054
AnnaBridge 161:aa5281ff4a02 1055 #define USB_OTG_GLOBAL_BASE 0x000U
AnnaBridge 161:aa5281ff4a02 1056 #define USB_OTG_DEVICE_BASE 0x800U
AnnaBridge 161:aa5281ff4a02 1057 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
AnnaBridge 161:aa5281ff4a02 1058 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
AnnaBridge 161:aa5281ff4a02 1059 #define USB_OTG_EP_REG_SIZE 0x20U
AnnaBridge 161:aa5281ff4a02 1060 #define USB_OTG_HOST_BASE 0x400U
AnnaBridge 161:aa5281ff4a02 1061 #define USB_OTG_HOST_PORT_BASE 0x440U
AnnaBridge 161:aa5281ff4a02 1062 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
AnnaBridge 161:aa5281ff4a02 1063 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
AnnaBridge 161:aa5281ff4a02 1064 #define USB_OTG_PCGCCTL_BASE 0xE00U
AnnaBridge 161:aa5281ff4a02 1065 #define USB_OTG_FIFO_BASE 0x1000U
AnnaBridge 161:aa5281ff4a02 1066 #define USB_OTG_FIFO_SIZE 0x1000U
AnnaBridge 161:aa5281ff4a02 1067
AnnaBridge 161:aa5281ff4a02 1068 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
AnnaBridge 161:aa5281ff4a02 1069 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
AnnaBridge 161:aa5281ff4a02 1070 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
AnnaBridge 161:aa5281ff4a02 1071 /**
AnnaBridge 161:aa5281ff4a02 1072 * @}
AnnaBridge 161:aa5281ff4a02 1073 */
AnnaBridge 161:aa5281ff4a02 1074
AnnaBridge 161:aa5281ff4a02 1075 /** @addtogroup Peripheral_declaration
AnnaBridge 161:aa5281ff4a02 1076 * @{
AnnaBridge 161:aa5281ff4a02 1077 */
AnnaBridge 161:aa5281ff4a02 1078 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 161:aa5281ff4a02 1079 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 161:aa5281ff4a02 1080 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
AnnaBridge 161:aa5281ff4a02 1081 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 161:aa5281ff4a02 1082 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 161:aa5281ff4a02 1083 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 161:aa5281ff4a02 1084 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
AnnaBridge 161:aa5281ff4a02 1085 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
AnnaBridge 161:aa5281ff4a02 1086 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
AnnaBridge 161:aa5281ff4a02 1087 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 161:aa5281ff4a02 1088 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 161:aa5281ff4a02 1089 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 161:aa5281ff4a02 1090 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
AnnaBridge 161:aa5281ff4a02 1091 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 161:aa5281ff4a02 1092 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 161:aa5281ff4a02 1093 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
AnnaBridge 161:aa5281ff4a02 1094 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 161:aa5281ff4a02 1095 #define USART3 ((USART_TypeDef *) USART3_BASE)
AnnaBridge 161:aa5281ff4a02 1096 #define UART4 ((USART_TypeDef *) UART4_BASE)
AnnaBridge 161:aa5281ff4a02 1097 #define UART5 ((USART_TypeDef *) UART5_BASE)
AnnaBridge 161:aa5281ff4a02 1098 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 161:aa5281ff4a02 1099 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 161:aa5281ff4a02 1100 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 161:aa5281ff4a02 1101 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
AnnaBridge 161:aa5281ff4a02 1102 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
AnnaBridge 161:aa5281ff4a02 1103 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 161:aa5281ff4a02 1104 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 161:aa5281ff4a02 1105 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
AnnaBridge 161:aa5281ff4a02 1106 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 161:aa5281ff4a02 1107 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
AnnaBridge 161:aa5281ff4a02 1108 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 161:aa5281ff4a02 1109 #define USART6 ((USART_TypeDef *) USART6_BASE)
AnnaBridge 161:aa5281ff4a02 1110 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 161:aa5281ff4a02 1111 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
AnnaBridge 161:aa5281ff4a02 1112 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
AnnaBridge 161:aa5281ff4a02 1113 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
AnnaBridge 161:aa5281ff4a02 1114 /* Legacy define */
AnnaBridge 161:aa5281ff4a02 1115 #define ADC ADC123_COMMON
AnnaBridge 161:aa5281ff4a02 1116 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
AnnaBridge 161:aa5281ff4a02 1117 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 161:aa5281ff4a02 1118 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 161:aa5281ff4a02 1119 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 161:aa5281ff4a02 1120 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
AnnaBridge 161:aa5281ff4a02 1121 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
AnnaBridge 161:aa5281ff4a02 1122 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
AnnaBridge 161:aa5281ff4a02 1123 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 161:aa5281ff4a02 1124 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 161:aa5281ff4a02 1125 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 161:aa5281ff4a02 1126 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 161:aa5281ff4a02 1127 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 161:aa5281ff4a02 1128 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
AnnaBridge 161:aa5281ff4a02 1129 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
AnnaBridge 161:aa5281ff4a02 1130 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 161:aa5281ff4a02 1131 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
AnnaBridge 161:aa5281ff4a02 1132 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 161:aa5281ff4a02 1133 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 161:aa5281ff4a02 1134 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 161:aa5281ff4a02 1135 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 161:aa5281ff4a02 1136 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
AnnaBridge 161:aa5281ff4a02 1137 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
AnnaBridge 161:aa5281ff4a02 1138 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
AnnaBridge 161:aa5281ff4a02 1139 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
AnnaBridge 161:aa5281ff4a02 1140 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
AnnaBridge 161:aa5281ff4a02 1141 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
AnnaBridge 161:aa5281ff4a02 1142 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
AnnaBridge 161:aa5281ff4a02 1143 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
AnnaBridge 161:aa5281ff4a02 1144 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 161:aa5281ff4a02 1145 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
AnnaBridge 161:aa5281ff4a02 1146 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
AnnaBridge 161:aa5281ff4a02 1147 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
AnnaBridge 161:aa5281ff4a02 1148 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
AnnaBridge 161:aa5281ff4a02 1149 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
AnnaBridge 161:aa5281ff4a02 1150 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
AnnaBridge 161:aa5281ff4a02 1151 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
AnnaBridge 161:aa5281ff4a02 1152 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
AnnaBridge 161:aa5281ff4a02 1153 #define ETH ((ETH_TypeDef *) ETH_BASE)
AnnaBridge 161:aa5281ff4a02 1154 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
AnnaBridge 161:aa5281ff4a02 1155 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 161:aa5281ff4a02 1156 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
AnnaBridge 161:aa5281ff4a02 1157 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
AnnaBridge 161:aa5281ff4a02 1158 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
AnnaBridge 161:aa5281ff4a02 1159 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
AnnaBridge 161:aa5281ff4a02 1160 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 161:aa5281ff4a02 1161 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
AnnaBridge 161:aa5281ff4a02 1162 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
AnnaBridge 161:aa5281ff4a02 1163
AnnaBridge 161:aa5281ff4a02 1164 /**
AnnaBridge 161:aa5281ff4a02 1165 * @}
AnnaBridge 161:aa5281ff4a02 1166 */
AnnaBridge 161:aa5281ff4a02 1167
AnnaBridge 161:aa5281ff4a02 1168 /** @addtogroup Exported_constants
AnnaBridge 161:aa5281ff4a02 1169 * @{
AnnaBridge 161:aa5281ff4a02 1170 */
AnnaBridge 161:aa5281ff4a02 1171
AnnaBridge 161:aa5281ff4a02 1172 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 161:aa5281ff4a02 1173 * @{
AnnaBridge 161:aa5281ff4a02 1174 */
AnnaBridge 161:aa5281ff4a02 1175
AnnaBridge 161:aa5281ff4a02 1176 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 1177 /* Peripheral Registers_Bits_Definition */
AnnaBridge 161:aa5281ff4a02 1178 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 1179
AnnaBridge 161:aa5281ff4a02 1180 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 1181 /* */
AnnaBridge 161:aa5281ff4a02 1182 /* Analog to Digital Converter */
AnnaBridge 161:aa5281ff4a02 1183 /* */
AnnaBridge 161:aa5281ff4a02 1184 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 1185 /*
AnnaBridge 161:aa5281ff4a02 1186 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 161:aa5281ff4a02 1187 */
AnnaBridge 161:aa5281ff4a02 1188 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
AnnaBridge 161:aa5281ff4a02 1189
AnnaBridge 161:aa5281ff4a02 1190 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 161:aa5281ff4a02 1191 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1192 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1193 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
AnnaBridge 161:aa5281ff4a02 1194 #define ADC_SR_EOC_Pos (1U)
AnnaBridge 161:aa5281ff4a02 1195 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1196 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
AnnaBridge 161:aa5281ff4a02 1197 #define ADC_SR_JEOC_Pos (2U)
AnnaBridge 161:aa5281ff4a02 1198 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1199 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
AnnaBridge 161:aa5281ff4a02 1200 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1201 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1202 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
AnnaBridge 161:aa5281ff4a02 1203 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 161:aa5281ff4a02 1204 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1205 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
AnnaBridge 161:aa5281ff4a02 1206 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1207 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1208 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 161:aa5281ff4a02 1209
AnnaBridge 161:aa5281ff4a02 1210 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 161:aa5281ff4a02 1211 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1212 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 161:aa5281ff4a02 1213 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 161:aa5281ff4a02 1214 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1215 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1216 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1217 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1218 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1219 #define ADC_CR1_EOCIE_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1220 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1221 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
AnnaBridge 161:aa5281ff4a02 1222 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 1223 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1224 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 161:aa5281ff4a02 1225 #define ADC_CR1_JEOCIE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 1226 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1227 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
AnnaBridge 161:aa5281ff4a02 1228 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 1229 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1230 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
AnnaBridge 161:aa5281ff4a02 1231 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 161:aa5281ff4a02 1232 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1233 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 161:aa5281ff4a02 1234 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1235 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1236 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
AnnaBridge 161:aa5281ff4a02 1237 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 1238 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1239 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
AnnaBridge 161:aa5281ff4a02 1240 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 1241 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 1242 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
AnnaBridge 161:aa5281ff4a02 1243 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 161:aa5281ff4a02 1244 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 161:aa5281ff4a02 1245 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 161:aa5281ff4a02 1246 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1247 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 1248 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1249 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 161:aa5281ff4a02 1250 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 1251 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
AnnaBridge 161:aa5281ff4a02 1252 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 161:aa5281ff4a02 1253 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 1254 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
AnnaBridge 161:aa5281ff4a02 1255 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 161:aa5281ff4a02 1256 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 161:aa5281ff4a02 1257 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
AnnaBridge 161:aa5281ff4a02 1258 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 1259 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 1260 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 161:aa5281ff4a02 1261 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 1262 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
AnnaBridge 161:aa5281ff4a02 1263
AnnaBridge 161:aa5281ff4a02 1264 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 161:aa5281ff4a02 1265 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1266 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1267 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
AnnaBridge 161:aa5281ff4a02 1268 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 161:aa5281ff4a02 1269 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1270 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
AnnaBridge 161:aa5281ff4a02 1271 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 161:aa5281ff4a02 1272 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1273 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
AnnaBridge 161:aa5281ff4a02 1274 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 161:aa5281ff4a02 1275 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1276 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
AnnaBridge 161:aa5281ff4a02 1277 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1278 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1279 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
AnnaBridge 161:aa5281ff4a02 1280 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 1281 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1282 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
AnnaBridge 161:aa5281ff4a02 1283 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 161:aa5281ff4a02 1284 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 1285 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 161:aa5281ff4a02 1286 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1287 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1288 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1289 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1290 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 161:aa5281ff4a02 1291 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 1292 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 161:aa5281ff4a02 1293 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 1294 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 1295 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 161:aa5281ff4a02 1296 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 1297 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
AnnaBridge 161:aa5281ff4a02 1298 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 161:aa5281ff4a02 1299 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 1300 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 161:aa5281ff4a02 1301 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 1302 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 1303 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 1304 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 1305 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 161:aa5281ff4a02 1306 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 1307 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 161:aa5281ff4a02 1308 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 1309 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 1310 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 161:aa5281ff4a02 1311 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 1312 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
AnnaBridge 161:aa5281ff4a02 1313
AnnaBridge 161:aa5281ff4a02 1314 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 161:aa5281ff4a02 1315 #define ADC_SMPR1_SMP10_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1316 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 161:aa5281ff4a02 1317 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1318 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1319 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1320 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1321 #define ADC_SMPR1_SMP11_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1322 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 161:aa5281ff4a02 1323 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1324 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1325 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1326 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1327 #define ADC_SMPR1_SMP12_Pos (6U)
AnnaBridge 161:aa5281ff4a02 1328 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 161:aa5281ff4a02 1329 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1330 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1331 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1332 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1333 #define ADC_SMPR1_SMP13_Pos (9U)
AnnaBridge 161:aa5281ff4a02 1334 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 161:aa5281ff4a02 1335 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1336 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1337 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1338 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1339 #define ADC_SMPR1_SMP14_Pos (12U)
AnnaBridge 161:aa5281ff4a02 1340 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 161:aa5281ff4a02 1341 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1342 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 1343 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1344 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 1345 #define ADC_SMPR1_SMP15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1346 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 161:aa5281ff4a02 1347 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1348 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1349 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1350 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1351 #define ADC_SMPR1_SMP16_Pos (18U)
AnnaBridge 161:aa5281ff4a02 1352 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 161:aa5281ff4a02 1353 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1354 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1355 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1356 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 1357 #define ADC_SMPR1_SMP17_Pos (21U)
AnnaBridge 161:aa5281ff4a02 1358 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 161:aa5281ff4a02 1359 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1360 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 1361 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 1362 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 1363 #define ADC_SMPR1_SMP18_Pos (24U)
AnnaBridge 161:aa5281ff4a02 1364 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 161:aa5281ff4a02 1365 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1366 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 1367 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 1368 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 1369
AnnaBridge 161:aa5281ff4a02 1370 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 161:aa5281ff4a02 1371 #define ADC_SMPR2_SMP0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1372 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 161:aa5281ff4a02 1373 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1374 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1375 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1376 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1377 #define ADC_SMPR2_SMP1_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1378 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 161:aa5281ff4a02 1379 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1380 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1381 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1382 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1383 #define ADC_SMPR2_SMP2_Pos (6U)
AnnaBridge 161:aa5281ff4a02 1384 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 161:aa5281ff4a02 1385 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1386 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1387 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1388 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1389 #define ADC_SMPR2_SMP3_Pos (9U)
AnnaBridge 161:aa5281ff4a02 1390 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 161:aa5281ff4a02 1391 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1392 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1393 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1394 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1395 #define ADC_SMPR2_SMP4_Pos (12U)
AnnaBridge 161:aa5281ff4a02 1396 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 161:aa5281ff4a02 1397 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1398 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 1399 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1400 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 1401 #define ADC_SMPR2_SMP5_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1402 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 161:aa5281ff4a02 1403 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1404 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1405 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1406 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1407 #define ADC_SMPR2_SMP6_Pos (18U)
AnnaBridge 161:aa5281ff4a02 1408 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 161:aa5281ff4a02 1409 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1410 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1411 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1412 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 1413 #define ADC_SMPR2_SMP7_Pos (21U)
AnnaBridge 161:aa5281ff4a02 1414 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 161:aa5281ff4a02 1415 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1416 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 1417 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 1418 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 1419 #define ADC_SMPR2_SMP8_Pos (24U)
AnnaBridge 161:aa5281ff4a02 1420 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 161:aa5281ff4a02 1421 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1422 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 1423 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 1424 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 1425 #define ADC_SMPR2_SMP9_Pos (27U)
AnnaBridge 161:aa5281ff4a02 1426 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 161:aa5281ff4a02 1427 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 161:aa5281ff4a02 1428 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 1429 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 1430 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 1431
AnnaBridge 161:aa5281ff4a02 1432 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 161:aa5281ff4a02 1433 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1434 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 1435 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
AnnaBridge 161:aa5281ff4a02 1436
AnnaBridge 161:aa5281ff4a02 1437 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 161:aa5281ff4a02 1438 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1439 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 1440 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
AnnaBridge 161:aa5281ff4a02 1441
AnnaBridge 161:aa5281ff4a02 1442 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 161:aa5281ff4a02 1443 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1444 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 1445 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
AnnaBridge 161:aa5281ff4a02 1446
AnnaBridge 161:aa5281ff4a02 1447 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 161:aa5281ff4a02 1448 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1449 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 1450 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
AnnaBridge 161:aa5281ff4a02 1451
AnnaBridge 161:aa5281ff4a02 1452 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 161:aa5281ff4a02 1453 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1454 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 1455 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
AnnaBridge 161:aa5281ff4a02 1456
AnnaBridge 161:aa5281ff4a02 1457 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 161:aa5281ff4a02 1458 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1459 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 1460 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
AnnaBridge 161:aa5281ff4a02 1461
AnnaBridge 161:aa5281ff4a02 1462 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 161:aa5281ff4a02 1463 #define ADC_SQR1_SQ13_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1464 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 161:aa5281ff4a02 1465 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1466 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1467 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1468 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1469 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1470 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1471 #define ADC_SQR1_SQ14_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1472 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 161:aa5281ff4a02 1473 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1474 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1475 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1476 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1477 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1478 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1479 #define ADC_SQR1_SQ15_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1480 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 161:aa5281ff4a02 1481 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1482 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1483 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1484 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 1485 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1486 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 1487 #define ADC_SQR1_SQ16_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1488 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 161:aa5281ff4a02 1489 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1490 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1491 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1492 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1493 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1494 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1495 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 161:aa5281ff4a02 1496 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
AnnaBridge 161:aa5281ff4a02 1497 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 161:aa5281ff4a02 1498 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 1499 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 1500 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 1501 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 1502
AnnaBridge 161:aa5281ff4a02 1503 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 161:aa5281ff4a02 1504 #define ADC_SQR2_SQ7_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1505 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 161:aa5281ff4a02 1506 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1507 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1508 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1509 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1510 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1511 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1512 #define ADC_SQR2_SQ8_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1513 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 161:aa5281ff4a02 1514 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1515 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1516 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1517 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1518 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1519 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1520 #define ADC_SQR2_SQ9_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1521 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 161:aa5281ff4a02 1522 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1523 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1524 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1525 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 1526 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1527 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 1528 #define ADC_SQR2_SQ10_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1529 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 161:aa5281ff4a02 1530 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1531 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1532 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1533 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1534 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1535 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1536 #define ADC_SQR2_SQ11_Pos (20U)
AnnaBridge 161:aa5281ff4a02 1537 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 161:aa5281ff4a02 1538 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1539 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 1540 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 1541 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 1542 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 1543 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 1544 #define ADC_SQR2_SQ12_Pos (25U)
AnnaBridge 161:aa5281ff4a02 1545 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 161:aa5281ff4a02 1546 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1547 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 1548 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 1549 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 1550 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 1551 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 1552
AnnaBridge 161:aa5281ff4a02 1553 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 161:aa5281ff4a02 1554 #define ADC_SQR3_SQ1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1555 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 161:aa5281ff4a02 1556 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1557 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1558 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1559 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1560 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1561 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1562 #define ADC_SQR3_SQ2_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1563 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 161:aa5281ff4a02 1564 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1565 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1566 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1567 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1568 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1569 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1570 #define ADC_SQR3_SQ3_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1571 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 161:aa5281ff4a02 1572 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1573 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1574 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1575 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 1576 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1577 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 1578 #define ADC_SQR3_SQ4_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1579 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 161:aa5281ff4a02 1580 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1581 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1582 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1583 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1584 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1585 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1586 #define ADC_SQR3_SQ5_Pos (20U)
AnnaBridge 161:aa5281ff4a02 1587 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 161:aa5281ff4a02 1588 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1589 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 1590 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 1591 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 1592 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 1593 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 1594 #define ADC_SQR3_SQ6_Pos (25U)
AnnaBridge 161:aa5281ff4a02 1595 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 161:aa5281ff4a02 1596 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 161:aa5281ff4a02 1597 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 1598 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 1599 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 1600 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 1601 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 1602
AnnaBridge 161:aa5281ff4a02 1603 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 161:aa5281ff4a02 1604 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1605 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 161:aa5281ff4a02 1606 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 161:aa5281ff4a02 1607 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1608 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1609 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1610 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1611 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1612 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1613 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 161:aa5281ff4a02 1614 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 161:aa5281ff4a02 1615 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1616 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1617 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1618 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1619 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1620 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1621 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 161:aa5281ff4a02 1622 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 161:aa5281ff4a02 1623 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1624 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1625 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 1626 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1627 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 1628 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1629 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 161:aa5281ff4a02 1630 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 161:aa5281ff4a02 1631 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1632 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1633 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1634 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1635 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1636 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 161:aa5281ff4a02 1637 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 1638 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 161:aa5281ff4a02 1639 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 1640 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 1641
AnnaBridge 161:aa5281ff4a02 1642 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 161:aa5281ff4a02 1643 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1644 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 1645 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
AnnaBridge 161:aa5281ff4a02 1646
AnnaBridge 161:aa5281ff4a02 1647 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 161:aa5281ff4a02 1648 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1649 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 1650 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
AnnaBridge 161:aa5281ff4a02 1651
AnnaBridge 161:aa5281ff4a02 1652 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 161:aa5281ff4a02 1653 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1654 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 1655 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
AnnaBridge 161:aa5281ff4a02 1656
AnnaBridge 161:aa5281ff4a02 1657 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 161:aa5281ff4a02 1658 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1659 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 1660 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
AnnaBridge 161:aa5281ff4a02 1661
AnnaBridge 161:aa5281ff4a02 1662 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 161:aa5281ff4a02 1663 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1664 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 1665 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
AnnaBridge 161:aa5281ff4a02 1666 #define ADC_DR_ADC2DATA_Pos (16U)
AnnaBridge 161:aa5281ff4a02 1667 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 1668 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
AnnaBridge 161:aa5281ff4a02 1669
AnnaBridge 161:aa5281ff4a02 1670 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 161:aa5281ff4a02 1671 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1672 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1673 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
AnnaBridge 161:aa5281ff4a02 1674 #define ADC_CSR_EOC1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 1675 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1676 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
AnnaBridge 161:aa5281ff4a02 1677 #define ADC_CSR_JEOC1_Pos (2U)
AnnaBridge 161:aa5281ff4a02 1678 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1679 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
AnnaBridge 161:aa5281ff4a02 1680 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1681 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1682 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
AnnaBridge 161:aa5281ff4a02 1683 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 161:aa5281ff4a02 1684 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1685 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
AnnaBridge 161:aa5281ff4a02 1686 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1687 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1688 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
AnnaBridge 161:aa5281ff4a02 1689 #define ADC_CSR_AWD2_Pos (8U)
AnnaBridge 161:aa5281ff4a02 1690 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1691 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
AnnaBridge 161:aa5281ff4a02 1692 #define ADC_CSR_EOC2_Pos (9U)
AnnaBridge 161:aa5281ff4a02 1693 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1694 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
AnnaBridge 161:aa5281ff4a02 1695 #define ADC_CSR_JEOC2_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1696 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1697 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
AnnaBridge 161:aa5281ff4a02 1698 #define ADC_CSR_JSTRT2_Pos (11U)
AnnaBridge 161:aa5281ff4a02 1699 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1700 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
AnnaBridge 161:aa5281ff4a02 1701 #define ADC_CSR_STRT2_Pos (12U)
AnnaBridge 161:aa5281ff4a02 1702 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 1703 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
AnnaBridge 161:aa5281ff4a02 1704 #define ADC_CSR_OVR2_Pos (13U)
AnnaBridge 161:aa5281ff4a02 1705 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1706 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
AnnaBridge 161:aa5281ff4a02 1707 #define ADC_CSR_AWD3_Pos (16U)
AnnaBridge 161:aa5281ff4a02 1708 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1709 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
AnnaBridge 161:aa5281ff4a02 1710 #define ADC_CSR_EOC3_Pos (17U)
AnnaBridge 161:aa5281ff4a02 1711 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1712 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
AnnaBridge 161:aa5281ff4a02 1713 #define ADC_CSR_JEOC3_Pos (18U)
AnnaBridge 161:aa5281ff4a02 1714 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1715 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
AnnaBridge 161:aa5281ff4a02 1716 #define ADC_CSR_JSTRT3_Pos (19U)
AnnaBridge 161:aa5281ff4a02 1717 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1718 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
AnnaBridge 161:aa5281ff4a02 1719 #define ADC_CSR_STRT3_Pos (20U)
AnnaBridge 161:aa5281ff4a02 1720 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 1721 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
AnnaBridge 161:aa5281ff4a02 1722 #define ADC_CSR_OVR3_Pos (21U)
AnnaBridge 161:aa5281ff4a02 1723 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 1724 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
AnnaBridge 161:aa5281ff4a02 1725
AnnaBridge 161:aa5281ff4a02 1726 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 1727 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
AnnaBridge 161:aa5281ff4a02 1728 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
AnnaBridge 161:aa5281ff4a02 1729 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
AnnaBridge 161:aa5281ff4a02 1730
AnnaBridge 161:aa5281ff4a02 1731 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 161:aa5281ff4a02 1732 #define ADC_CCR_MULTI_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1733 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 161:aa5281ff4a02 1734 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 161:aa5281ff4a02 1735 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1736 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1737 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1738 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1739 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1740 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 161:aa5281ff4a02 1741 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 1742 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 161:aa5281ff4a02 1743 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1744 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1745 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1746 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1747 #define ADC_CCR_DDS_Pos (13U)
AnnaBridge 161:aa5281ff4a02 1748 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 1749 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 161:aa5281ff4a02 1750 #define ADC_CCR_DMA_Pos (14U)
AnnaBridge 161:aa5281ff4a02 1751 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
AnnaBridge 161:aa5281ff4a02 1752 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 161:aa5281ff4a02 1753 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 1754 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1755 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 1756 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 161:aa5281ff4a02 1757 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 161:aa5281ff4a02 1758 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1759 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1760 #define ADC_CCR_VBATE_Pos (22U)
AnnaBridge 161:aa5281ff4a02 1761 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 1762 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
AnnaBridge 161:aa5281ff4a02 1763 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 161:aa5281ff4a02 1764 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 1765 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
AnnaBridge 161:aa5281ff4a02 1766
AnnaBridge 161:aa5281ff4a02 1767 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 161:aa5281ff4a02 1768 #define ADC_CDR_DATA1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1769 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 1770 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
AnnaBridge 161:aa5281ff4a02 1771 #define ADC_CDR_DATA2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 1772 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 1773 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
AnnaBridge 161:aa5281ff4a02 1774
AnnaBridge 161:aa5281ff4a02 1775 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 1776 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
AnnaBridge 161:aa5281ff4a02 1777 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
AnnaBridge 161:aa5281ff4a02 1778
AnnaBridge 161:aa5281ff4a02 1779 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 1780 /* */
AnnaBridge 161:aa5281ff4a02 1781 /* Controller Area Network */
AnnaBridge 161:aa5281ff4a02 1782 /* */
AnnaBridge 161:aa5281ff4a02 1783 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 1784 /*!<CAN control and status registers */
AnnaBridge 161:aa5281ff4a02 1785 /******************* Bit definition for CAN_MCR register ********************/
AnnaBridge 161:aa5281ff4a02 1786 #define CAN_MCR_INRQ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1787 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1788 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
AnnaBridge 161:aa5281ff4a02 1789 #define CAN_MCR_SLEEP_Pos (1U)
AnnaBridge 161:aa5281ff4a02 1790 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1791 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
AnnaBridge 161:aa5281ff4a02 1792 #define CAN_MCR_TXFP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 1793 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1794 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
AnnaBridge 161:aa5281ff4a02 1795 #define CAN_MCR_RFLM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1796 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1797 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
AnnaBridge 161:aa5281ff4a02 1798 #define CAN_MCR_NART_Pos (4U)
AnnaBridge 161:aa5281ff4a02 1799 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1800 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
AnnaBridge 161:aa5281ff4a02 1801 #define CAN_MCR_AWUM_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1802 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1803 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
AnnaBridge 161:aa5281ff4a02 1804 #define CAN_MCR_ABOM_Pos (6U)
AnnaBridge 161:aa5281ff4a02 1805 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1806 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
AnnaBridge 161:aa5281ff4a02 1807 #define CAN_MCR_TTCM_Pos (7U)
AnnaBridge 161:aa5281ff4a02 1808 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1809 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
AnnaBridge 161:aa5281ff4a02 1810 #define CAN_MCR_RESET_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1811 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1812 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
AnnaBridge 161:aa5281ff4a02 1813 #define CAN_MCR_DBF_Pos (16U)
AnnaBridge 161:aa5281ff4a02 1814 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1815 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
AnnaBridge 161:aa5281ff4a02 1816 /******************* Bit definition for CAN_MSR register ********************/
AnnaBridge 161:aa5281ff4a02 1817 #define CAN_MSR_INAK_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1818 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1819 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
AnnaBridge 161:aa5281ff4a02 1820 #define CAN_MSR_SLAK_Pos (1U)
AnnaBridge 161:aa5281ff4a02 1821 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1822 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
AnnaBridge 161:aa5281ff4a02 1823 #define CAN_MSR_ERRI_Pos (2U)
AnnaBridge 161:aa5281ff4a02 1824 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1825 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
AnnaBridge 161:aa5281ff4a02 1826 #define CAN_MSR_WKUI_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1827 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1828 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
AnnaBridge 161:aa5281ff4a02 1829 #define CAN_MSR_SLAKI_Pos (4U)
AnnaBridge 161:aa5281ff4a02 1830 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1831 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
AnnaBridge 161:aa5281ff4a02 1832 #define CAN_MSR_TXM_Pos (8U)
AnnaBridge 161:aa5281ff4a02 1833 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1834 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
AnnaBridge 161:aa5281ff4a02 1835 #define CAN_MSR_RXM_Pos (9U)
AnnaBridge 161:aa5281ff4a02 1836 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1837 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
AnnaBridge 161:aa5281ff4a02 1838 #define CAN_MSR_SAMP_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1839 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1840 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
AnnaBridge 161:aa5281ff4a02 1841 #define CAN_MSR_RX_Pos (11U)
AnnaBridge 161:aa5281ff4a02 1842 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1843 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
AnnaBridge 161:aa5281ff4a02 1844
AnnaBridge 161:aa5281ff4a02 1845 /******************* Bit definition for CAN_TSR register ********************/
AnnaBridge 161:aa5281ff4a02 1846 #define CAN_TSR_RQCP0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1847 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1848 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
AnnaBridge 161:aa5281ff4a02 1849 #define CAN_TSR_TXOK0_Pos (1U)
AnnaBridge 161:aa5281ff4a02 1850 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1851 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
AnnaBridge 161:aa5281ff4a02 1852 #define CAN_TSR_ALST0_Pos (2U)
AnnaBridge 161:aa5281ff4a02 1853 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1854 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
AnnaBridge 161:aa5281ff4a02 1855 #define CAN_TSR_TERR0_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1856 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1857 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
AnnaBridge 161:aa5281ff4a02 1858 #define CAN_TSR_ABRQ0_Pos (7U)
AnnaBridge 161:aa5281ff4a02 1859 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 1860 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
AnnaBridge 161:aa5281ff4a02 1861 #define CAN_TSR_RQCP1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 1862 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1863 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
AnnaBridge 161:aa5281ff4a02 1864 #define CAN_TSR_TXOK1_Pos (9U)
AnnaBridge 161:aa5281ff4a02 1865 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1866 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
AnnaBridge 161:aa5281ff4a02 1867 #define CAN_TSR_ALST1_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1868 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1869 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
AnnaBridge 161:aa5281ff4a02 1870 #define CAN_TSR_TERR1_Pos (11U)
AnnaBridge 161:aa5281ff4a02 1871 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1872 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
AnnaBridge 161:aa5281ff4a02 1873 #define CAN_TSR_ABRQ1_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1874 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1875 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
AnnaBridge 161:aa5281ff4a02 1876 #define CAN_TSR_RQCP2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 1877 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1878 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
AnnaBridge 161:aa5281ff4a02 1879 #define CAN_TSR_TXOK2_Pos (17U)
AnnaBridge 161:aa5281ff4a02 1880 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1881 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
AnnaBridge 161:aa5281ff4a02 1882 #define CAN_TSR_ALST2_Pos (18U)
AnnaBridge 161:aa5281ff4a02 1883 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 1884 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
AnnaBridge 161:aa5281ff4a02 1885 #define CAN_TSR_TERR2_Pos (19U)
AnnaBridge 161:aa5281ff4a02 1886 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 1887 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
AnnaBridge 161:aa5281ff4a02 1888 #define CAN_TSR_ABRQ2_Pos (23U)
AnnaBridge 161:aa5281ff4a02 1889 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 1890 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
AnnaBridge 161:aa5281ff4a02 1891 #define CAN_TSR_CODE_Pos (24U)
AnnaBridge 161:aa5281ff4a02 1892 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
AnnaBridge 161:aa5281ff4a02 1893 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
AnnaBridge 161:aa5281ff4a02 1894
AnnaBridge 161:aa5281ff4a02 1895 #define CAN_TSR_TME_Pos (26U)
AnnaBridge 161:aa5281ff4a02 1896 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
AnnaBridge 161:aa5281ff4a02 1897 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
AnnaBridge 161:aa5281ff4a02 1898 #define CAN_TSR_TME0_Pos (26U)
AnnaBridge 161:aa5281ff4a02 1899 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 1900 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
AnnaBridge 161:aa5281ff4a02 1901 #define CAN_TSR_TME1_Pos (27U)
AnnaBridge 161:aa5281ff4a02 1902 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 1903 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
AnnaBridge 161:aa5281ff4a02 1904 #define CAN_TSR_TME2_Pos (28U)
AnnaBridge 161:aa5281ff4a02 1905 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 1906 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
AnnaBridge 161:aa5281ff4a02 1907
AnnaBridge 161:aa5281ff4a02 1908 #define CAN_TSR_LOW_Pos (29U)
AnnaBridge 161:aa5281ff4a02 1909 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
AnnaBridge 161:aa5281ff4a02 1910 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
AnnaBridge 161:aa5281ff4a02 1911 #define CAN_TSR_LOW0_Pos (29U)
AnnaBridge 161:aa5281ff4a02 1912 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 1913 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
AnnaBridge 161:aa5281ff4a02 1914 #define CAN_TSR_LOW1_Pos (30U)
AnnaBridge 161:aa5281ff4a02 1915 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 1916 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
AnnaBridge 161:aa5281ff4a02 1917 #define CAN_TSR_LOW2_Pos (31U)
AnnaBridge 161:aa5281ff4a02 1918 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 1919 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
AnnaBridge 161:aa5281ff4a02 1920
AnnaBridge 161:aa5281ff4a02 1921 /******************* Bit definition for CAN_RF0R register *******************/
AnnaBridge 161:aa5281ff4a02 1922 #define CAN_RF0R_FMP0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1923 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 1924 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
AnnaBridge 161:aa5281ff4a02 1925 #define CAN_RF0R_FULL0_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1926 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1927 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
AnnaBridge 161:aa5281ff4a02 1928 #define CAN_RF0R_FOVR0_Pos (4U)
AnnaBridge 161:aa5281ff4a02 1929 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1930 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
AnnaBridge 161:aa5281ff4a02 1931 #define CAN_RF0R_RFOM0_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1932 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1933 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
AnnaBridge 161:aa5281ff4a02 1934
AnnaBridge 161:aa5281ff4a02 1935 /******************* Bit definition for CAN_RF1R register *******************/
AnnaBridge 161:aa5281ff4a02 1936 #define CAN_RF1R_FMP1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1937 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 1938 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
AnnaBridge 161:aa5281ff4a02 1939 #define CAN_RF1R_FULL1_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1940 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1941 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
AnnaBridge 161:aa5281ff4a02 1942 #define CAN_RF1R_FOVR1_Pos (4U)
AnnaBridge 161:aa5281ff4a02 1943 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1944 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
AnnaBridge 161:aa5281ff4a02 1945 #define CAN_RF1R_RFOM1_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1946 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1947 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
AnnaBridge 161:aa5281ff4a02 1948
AnnaBridge 161:aa5281ff4a02 1949 /******************** Bit definition for CAN_IER register *******************/
AnnaBridge 161:aa5281ff4a02 1950 #define CAN_IER_TMEIE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1951 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1952 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1953 #define CAN_IER_FMPIE0_Pos (1U)
AnnaBridge 161:aa5281ff4a02 1954 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 1955 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1956 #define CAN_IER_FFIE0_Pos (2U)
AnnaBridge 161:aa5281ff4a02 1957 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 1958 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1959 #define CAN_IER_FOVIE0_Pos (3U)
AnnaBridge 161:aa5281ff4a02 1960 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 1961 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1962 #define CAN_IER_FMPIE1_Pos (4U)
AnnaBridge 161:aa5281ff4a02 1963 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 1964 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1965 #define CAN_IER_FFIE1_Pos (5U)
AnnaBridge 161:aa5281ff4a02 1966 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 1967 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1968 #define CAN_IER_FOVIE1_Pos (6U)
AnnaBridge 161:aa5281ff4a02 1969 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 1970 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1971 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 1972 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 1973 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1974 #define CAN_IER_EPVIE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 1975 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 1976 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1977 #define CAN_IER_BOFIE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 1978 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 1979 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1980 #define CAN_IER_LECIE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 1981 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 1982 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1983 #define CAN_IER_ERRIE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 1984 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 1985 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1986 #define CAN_IER_WKUIE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 1987 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 1988 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1989 #define CAN_IER_SLKIE_Pos (17U)
AnnaBridge 161:aa5281ff4a02 1990 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 1991 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 1992 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 1993
AnnaBridge 161:aa5281ff4a02 1994 /******************** Bit definition for CAN_ESR register *******************/
AnnaBridge 161:aa5281ff4a02 1995 #define CAN_ESR_EWGF_Pos (0U)
AnnaBridge 161:aa5281ff4a02 1996 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 1997 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
AnnaBridge 161:aa5281ff4a02 1998 #define CAN_ESR_EPVF_Pos (1U)
AnnaBridge 161:aa5281ff4a02 1999 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2000 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
AnnaBridge 161:aa5281ff4a02 2001 #define CAN_ESR_BOFF_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2002 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2003 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
AnnaBridge 161:aa5281ff4a02 2004
AnnaBridge 161:aa5281ff4a02 2005 #define CAN_ESR_LEC_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2006 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 2007 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
AnnaBridge 161:aa5281ff4a02 2008 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2009 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 2010 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 2011
AnnaBridge 161:aa5281ff4a02 2012 #define CAN_ESR_TEC_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2013 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2014 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
AnnaBridge 161:aa5281ff4a02 2015 #define CAN_ESR_REC_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2016 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2017 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
AnnaBridge 161:aa5281ff4a02 2018
AnnaBridge 161:aa5281ff4a02 2019 /******************* Bit definition for CAN_BTR register ********************/
AnnaBridge 161:aa5281ff4a02 2020 #define CAN_BTR_BRP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2021 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
AnnaBridge 161:aa5281ff4a02 2022 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
AnnaBridge 161:aa5281ff4a02 2023 #define CAN_BTR_TS1_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2024 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 2025 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
AnnaBridge 161:aa5281ff4a02 2026 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 2027 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 2028 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 2029 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 2030 #define CAN_BTR_TS2_Pos (20U)
AnnaBridge 161:aa5281ff4a02 2031 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
AnnaBridge 161:aa5281ff4a02 2032 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
AnnaBridge 161:aa5281ff4a02 2033 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 2034 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 2035 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 2036 #define CAN_BTR_SJW_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2037 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
AnnaBridge 161:aa5281ff4a02 2038 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
AnnaBridge 161:aa5281ff4a02 2039 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 2040 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 2041 #define CAN_BTR_LBKM_Pos (30U)
AnnaBridge 161:aa5281ff4a02 2042 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 2043 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
AnnaBridge 161:aa5281ff4a02 2044 #define CAN_BTR_SILM_Pos (31U)
AnnaBridge 161:aa5281ff4a02 2045 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 2046 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
AnnaBridge 161:aa5281ff4a02 2047
AnnaBridge 161:aa5281ff4a02 2048
AnnaBridge 161:aa5281ff4a02 2049 /*!<Mailbox registers */
AnnaBridge 161:aa5281ff4a02 2050 /****************** Bit definition for CAN_TI0R register ********************/
AnnaBridge 161:aa5281ff4a02 2051 #define CAN_TI0R_TXRQ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2052 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2053 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 161:aa5281ff4a02 2054 #define CAN_TI0R_RTR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2055 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2056 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 161:aa5281ff4a02 2057 #define CAN_TI0R_IDE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2058 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2059 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 161:aa5281ff4a02 2060 #define CAN_TI0R_EXID_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2061 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 161:aa5281ff4a02 2062 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 161:aa5281ff4a02 2063 #define CAN_TI0R_STID_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2064 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 161:aa5281ff4a02 2065 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 161:aa5281ff4a02 2066
AnnaBridge 161:aa5281ff4a02 2067 /****************** Bit definition for CAN_TDT0R register *******************/
AnnaBridge 161:aa5281ff4a02 2068 #define CAN_TDT0R_DLC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2069 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 2070 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 161:aa5281ff4a02 2071 #define CAN_TDT0R_TGT_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2072 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2073 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 161:aa5281ff4a02 2074 #define CAN_TDT0R_TIME_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2075 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 2076 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 161:aa5281ff4a02 2077
AnnaBridge 161:aa5281ff4a02 2078 /****************** Bit definition for CAN_TDL0R register *******************/
AnnaBridge 161:aa5281ff4a02 2079 #define CAN_TDL0R_DATA0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2080 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2081 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 161:aa5281ff4a02 2082 #define CAN_TDL0R_DATA1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2083 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2084 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 161:aa5281ff4a02 2085 #define CAN_TDL0R_DATA2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2086 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2087 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 161:aa5281ff4a02 2088 #define CAN_TDL0R_DATA3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2089 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2090 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 161:aa5281ff4a02 2091
AnnaBridge 161:aa5281ff4a02 2092 /****************** Bit definition for CAN_TDH0R register *******************/
AnnaBridge 161:aa5281ff4a02 2093 #define CAN_TDH0R_DATA4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2094 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2095 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 161:aa5281ff4a02 2096 #define CAN_TDH0R_DATA5_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2097 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2098 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 161:aa5281ff4a02 2099 #define CAN_TDH0R_DATA6_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2100 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2101 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 161:aa5281ff4a02 2102 #define CAN_TDH0R_DATA7_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2103 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2104 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 161:aa5281ff4a02 2105
AnnaBridge 161:aa5281ff4a02 2106 /******************* Bit definition for CAN_TI1R register *******************/
AnnaBridge 161:aa5281ff4a02 2107 #define CAN_TI1R_TXRQ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2108 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2109 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 161:aa5281ff4a02 2110 #define CAN_TI1R_RTR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2111 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2112 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 161:aa5281ff4a02 2113 #define CAN_TI1R_IDE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2114 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2115 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 161:aa5281ff4a02 2116 #define CAN_TI1R_EXID_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2117 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 161:aa5281ff4a02 2118 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 161:aa5281ff4a02 2119 #define CAN_TI1R_STID_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2120 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 161:aa5281ff4a02 2121 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 161:aa5281ff4a02 2122
AnnaBridge 161:aa5281ff4a02 2123 /******************* Bit definition for CAN_TDT1R register ******************/
AnnaBridge 161:aa5281ff4a02 2124 #define CAN_TDT1R_DLC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2125 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 2126 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 161:aa5281ff4a02 2127 #define CAN_TDT1R_TGT_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2128 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2129 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 161:aa5281ff4a02 2130 #define CAN_TDT1R_TIME_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2131 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 2132 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 161:aa5281ff4a02 2133
AnnaBridge 161:aa5281ff4a02 2134 /******************* Bit definition for CAN_TDL1R register ******************/
AnnaBridge 161:aa5281ff4a02 2135 #define CAN_TDL1R_DATA0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2136 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2137 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 161:aa5281ff4a02 2138 #define CAN_TDL1R_DATA1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2139 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2140 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 161:aa5281ff4a02 2141 #define CAN_TDL1R_DATA2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2142 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2143 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 161:aa5281ff4a02 2144 #define CAN_TDL1R_DATA3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2145 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2146 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 161:aa5281ff4a02 2147
AnnaBridge 161:aa5281ff4a02 2148 /******************* Bit definition for CAN_TDH1R register ******************/
AnnaBridge 161:aa5281ff4a02 2149 #define CAN_TDH1R_DATA4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2150 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2151 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 161:aa5281ff4a02 2152 #define CAN_TDH1R_DATA5_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2153 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2154 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 161:aa5281ff4a02 2155 #define CAN_TDH1R_DATA6_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2156 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2157 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 161:aa5281ff4a02 2158 #define CAN_TDH1R_DATA7_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2159 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2160 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 161:aa5281ff4a02 2161
AnnaBridge 161:aa5281ff4a02 2162 /******************* Bit definition for CAN_TI2R register *******************/
AnnaBridge 161:aa5281ff4a02 2163 #define CAN_TI2R_TXRQ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2164 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2165 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 161:aa5281ff4a02 2166 #define CAN_TI2R_RTR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2167 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2168 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 161:aa5281ff4a02 2169 #define CAN_TI2R_IDE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2170 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2171 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 161:aa5281ff4a02 2172 #define CAN_TI2R_EXID_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2173 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 161:aa5281ff4a02 2174 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
AnnaBridge 161:aa5281ff4a02 2175 #define CAN_TI2R_STID_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2176 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 161:aa5281ff4a02 2177 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 161:aa5281ff4a02 2178
AnnaBridge 161:aa5281ff4a02 2179 /******************* Bit definition for CAN_TDT2R register ******************/
AnnaBridge 161:aa5281ff4a02 2180 #define CAN_TDT2R_DLC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2181 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 2182 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
AnnaBridge 161:aa5281ff4a02 2183 #define CAN_TDT2R_TGT_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2184 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2185 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 161:aa5281ff4a02 2186 #define CAN_TDT2R_TIME_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2187 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 2188 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 161:aa5281ff4a02 2189
AnnaBridge 161:aa5281ff4a02 2190 /******************* Bit definition for CAN_TDL2R register ******************/
AnnaBridge 161:aa5281ff4a02 2191 #define CAN_TDL2R_DATA0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2192 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2193 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 161:aa5281ff4a02 2194 #define CAN_TDL2R_DATA1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2195 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2196 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 161:aa5281ff4a02 2197 #define CAN_TDL2R_DATA2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2198 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2199 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 161:aa5281ff4a02 2200 #define CAN_TDL2R_DATA3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2201 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2202 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 161:aa5281ff4a02 2203
AnnaBridge 161:aa5281ff4a02 2204 /******************* Bit definition for CAN_TDH2R register ******************/
AnnaBridge 161:aa5281ff4a02 2205 #define CAN_TDH2R_DATA4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2206 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2207 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 161:aa5281ff4a02 2208 #define CAN_TDH2R_DATA5_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2209 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2210 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 161:aa5281ff4a02 2211 #define CAN_TDH2R_DATA6_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2212 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2213 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 161:aa5281ff4a02 2214 #define CAN_TDH2R_DATA7_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2215 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2216 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 161:aa5281ff4a02 2217
AnnaBridge 161:aa5281ff4a02 2218 /******************* Bit definition for CAN_RI0R register *******************/
AnnaBridge 161:aa5281ff4a02 2219 #define CAN_RI0R_RTR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2220 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2221 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 161:aa5281ff4a02 2222 #define CAN_RI0R_IDE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2223 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2224 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 161:aa5281ff4a02 2225 #define CAN_RI0R_EXID_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2226 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 161:aa5281ff4a02 2227 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 161:aa5281ff4a02 2228 #define CAN_RI0R_STID_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2229 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 161:aa5281ff4a02 2230 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 161:aa5281ff4a02 2231
AnnaBridge 161:aa5281ff4a02 2232 /******************* Bit definition for CAN_RDT0R register ******************/
AnnaBridge 161:aa5281ff4a02 2233 #define CAN_RDT0R_DLC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2234 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 2235 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 161:aa5281ff4a02 2236 #define CAN_RDT0R_FMI_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2237 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2238 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 161:aa5281ff4a02 2239 #define CAN_RDT0R_TIME_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2240 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 2241 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 161:aa5281ff4a02 2242
AnnaBridge 161:aa5281ff4a02 2243 /******************* Bit definition for CAN_RDL0R register ******************/
AnnaBridge 161:aa5281ff4a02 2244 #define CAN_RDL0R_DATA0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2245 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2246 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 161:aa5281ff4a02 2247 #define CAN_RDL0R_DATA1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2248 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2249 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 161:aa5281ff4a02 2250 #define CAN_RDL0R_DATA2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2251 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2252 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 161:aa5281ff4a02 2253 #define CAN_RDL0R_DATA3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2254 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2255 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 161:aa5281ff4a02 2256
AnnaBridge 161:aa5281ff4a02 2257 /******************* Bit definition for CAN_RDH0R register ******************/
AnnaBridge 161:aa5281ff4a02 2258 #define CAN_RDH0R_DATA4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2259 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2260 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 161:aa5281ff4a02 2261 #define CAN_RDH0R_DATA5_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2262 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2263 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 161:aa5281ff4a02 2264 #define CAN_RDH0R_DATA6_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2265 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2266 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 161:aa5281ff4a02 2267 #define CAN_RDH0R_DATA7_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2268 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2269 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 161:aa5281ff4a02 2270
AnnaBridge 161:aa5281ff4a02 2271 /******************* Bit definition for CAN_RI1R register *******************/
AnnaBridge 161:aa5281ff4a02 2272 #define CAN_RI1R_RTR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2273 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2274 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 161:aa5281ff4a02 2275 #define CAN_RI1R_IDE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2276 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2277 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 161:aa5281ff4a02 2278 #define CAN_RI1R_EXID_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2279 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 161:aa5281ff4a02 2280 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
AnnaBridge 161:aa5281ff4a02 2281 #define CAN_RI1R_STID_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2282 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 161:aa5281ff4a02 2283 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 161:aa5281ff4a02 2284
AnnaBridge 161:aa5281ff4a02 2285 /******************* Bit definition for CAN_RDT1R register ******************/
AnnaBridge 161:aa5281ff4a02 2286 #define CAN_RDT1R_DLC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2287 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 2288 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 161:aa5281ff4a02 2289 #define CAN_RDT1R_FMI_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2290 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2291 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 161:aa5281ff4a02 2292 #define CAN_RDT1R_TIME_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2293 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 2294 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 161:aa5281ff4a02 2295
AnnaBridge 161:aa5281ff4a02 2296 /******************* Bit definition for CAN_RDL1R register ******************/
AnnaBridge 161:aa5281ff4a02 2297 #define CAN_RDL1R_DATA0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2298 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2299 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 161:aa5281ff4a02 2300 #define CAN_RDL1R_DATA1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2301 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2302 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 161:aa5281ff4a02 2303 #define CAN_RDL1R_DATA2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2304 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2305 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 161:aa5281ff4a02 2306 #define CAN_RDL1R_DATA3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2307 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2308 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 161:aa5281ff4a02 2309
AnnaBridge 161:aa5281ff4a02 2310 /******************* Bit definition for CAN_RDH1R register ******************/
AnnaBridge 161:aa5281ff4a02 2311 #define CAN_RDH1R_DATA4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2312 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 2313 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 161:aa5281ff4a02 2314 #define CAN_RDH1R_DATA5_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2315 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 2316 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 161:aa5281ff4a02 2317 #define CAN_RDH1R_DATA6_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2318 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 2319 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 161:aa5281ff4a02 2320 #define CAN_RDH1R_DATA7_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2321 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 2322 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 161:aa5281ff4a02 2323
AnnaBridge 161:aa5281ff4a02 2324 /*!<CAN filter registers */
AnnaBridge 161:aa5281ff4a02 2325 /******************* Bit definition for CAN_FMR register ********************/
AnnaBridge 161:aa5281ff4a02 2326 #define CAN_FMR_FINIT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2327 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2328 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
AnnaBridge 161:aa5281ff4a02 2329 #define CAN_FMR_CAN2SB_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2330 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
AnnaBridge 161:aa5281ff4a02 2331 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
AnnaBridge 161:aa5281ff4a02 2332
AnnaBridge 161:aa5281ff4a02 2333 /******************* Bit definition for CAN_FM1R register *******************/
AnnaBridge 161:aa5281ff4a02 2334 #define CAN_FM1R_FBM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2335 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 161:aa5281ff4a02 2336 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
AnnaBridge 161:aa5281ff4a02 2337 #define CAN_FM1R_FBM0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2338 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2339 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
AnnaBridge 161:aa5281ff4a02 2340 #define CAN_FM1R_FBM1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2341 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2342 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
AnnaBridge 161:aa5281ff4a02 2343 #define CAN_FM1R_FBM2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2344 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2345 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
AnnaBridge 161:aa5281ff4a02 2346 #define CAN_FM1R_FBM3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2347 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 2348 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
AnnaBridge 161:aa5281ff4a02 2349 #define CAN_FM1R_FBM4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2350 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2351 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
AnnaBridge 161:aa5281ff4a02 2352 #define CAN_FM1R_FBM5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 2353 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 2354 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
AnnaBridge 161:aa5281ff4a02 2355 #define CAN_FM1R_FBM6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 2356 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 2357 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
AnnaBridge 161:aa5281ff4a02 2358 #define CAN_FM1R_FBM7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 2359 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 2360 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
AnnaBridge 161:aa5281ff4a02 2361 #define CAN_FM1R_FBM8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2362 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2363 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
AnnaBridge 161:aa5281ff4a02 2364 #define CAN_FM1R_FBM9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 2365 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 2366 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
AnnaBridge 161:aa5281ff4a02 2367 #define CAN_FM1R_FBM10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 2368 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 2369 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
AnnaBridge 161:aa5281ff4a02 2370 #define CAN_FM1R_FBM11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 2371 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 2372 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
AnnaBridge 161:aa5281ff4a02 2373 #define CAN_FM1R_FBM12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 2374 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 2375 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
AnnaBridge 161:aa5281ff4a02 2376 #define CAN_FM1R_FBM13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 2377 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 2378 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
AnnaBridge 161:aa5281ff4a02 2379 #define CAN_FM1R_FBM14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 2380 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 2381 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
AnnaBridge 161:aa5281ff4a02 2382 #define CAN_FM1R_FBM15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 2383 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 2384 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
AnnaBridge 161:aa5281ff4a02 2385 #define CAN_FM1R_FBM16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2386 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 2387 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
AnnaBridge 161:aa5281ff4a02 2388 #define CAN_FM1R_FBM17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 2389 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 2390 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
AnnaBridge 161:aa5281ff4a02 2391 #define CAN_FM1R_FBM18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 2392 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 2393 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
AnnaBridge 161:aa5281ff4a02 2394 #define CAN_FM1R_FBM19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 2395 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 2396 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
AnnaBridge 161:aa5281ff4a02 2397 #define CAN_FM1R_FBM20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 2398 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 2399 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
AnnaBridge 161:aa5281ff4a02 2400 #define CAN_FM1R_FBM21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2401 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 2402 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
AnnaBridge 161:aa5281ff4a02 2403 #define CAN_FM1R_FBM22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 2404 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 2405 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
AnnaBridge 161:aa5281ff4a02 2406 #define CAN_FM1R_FBM23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 2407 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 2408 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
AnnaBridge 161:aa5281ff4a02 2409 #define CAN_FM1R_FBM24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2410 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 2411 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
AnnaBridge 161:aa5281ff4a02 2412 #define CAN_FM1R_FBM25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 2413 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 2414 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
AnnaBridge 161:aa5281ff4a02 2415 #define CAN_FM1R_FBM26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 2416 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 2417 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
AnnaBridge 161:aa5281ff4a02 2418 #define CAN_FM1R_FBM27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 2419 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 2420 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
AnnaBridge 161:aa5281ff4a02 2421
AnnaBridge 161:aa5281ff4a02 2422 /******************* Bit definition for CAN_FS1R register *******************/
AnnaBridge 161:aa5281ff4a02 2423 #define CAN_FS1R_FSC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2424 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 161:aa5281ff4a02 2425 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
AnnaBridge 161:aa5281ff4a02 2426 #define CAN_FS1R_FSC0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2427 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2428 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
AnnaBridge 161:aa5281ff4a02 2429 #define CAN_FS1R_FSC1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2430 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2431 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
AnnaBridge 161:aa5281ff4a02 2432 #define CAN_FS1R_FSC2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2433 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2434 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
AnnaBridge 161:aa5281ff4a02 2435 #define CAN_FS1R_FSC3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2436 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 2437 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
AnnaBridge 161:aa5281ff4a02 2438 #define CAN_FS1R_FSC4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2439 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2440 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
AnnaBridge 161:aa5281ff4a02 2441 #define CAN_FS1R_FSC5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 2442 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 2443 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
AnnaBridge 161:aa5281ff4a02 2444 #define CAN_FS1R_FSC6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 2445 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 2446 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
AnnaBridge 161:aa5281ff4a02 2447 #define CAN_FS1R_FSC7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 2448 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 2449 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
AnnaBridge 161:aa5281ff4a02 2450 #define CAN_FS1R_FSC8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2451 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2452 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
AnnaBridge 161:aa5281ff4a02 2453 #define CAN_FS1R_FSC9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 2454 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 2455 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
AnnaBridge 161:aa5281ff4a02 2456 #define CAN_FS1R_FSC10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 2457 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 2458 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
AnnaBridge 161:aa5281ff4a02 2459 #define CAN_FS1R_FSC11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 2460 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 2461 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
AnnaBridge 161:aa5281ff4a02 2462 #define CAN_FS1R_FSC12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 2463 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 2464 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
AnnaBridge 161:aa5281ff4a02 2465 #define CAN_FS1R_FSC13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 2466 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 2467 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
AnnaBridge 161:aa5281ff4a02 2468 #define CAN_FS1R_FSC14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 2469 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 2470 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
AnnaBridge 161:aa5281ff4a02 2471 #define CAN_FS1R_FSC15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 2472 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 2473 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
AnnaBridge 161:aa5281ff4a02 2474 #define CAN_FS1R_FSC16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2475 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 2476 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
AnnaBridge 161:aa5281ff4a02 2477 #define CAN_FS1R_FSC17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 2478 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 2479 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
AnnaBridge 161:aa5281ff4a02 2480 #define CAN_FS1R_FSC18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 2481 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 2482 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
AnnaBridge 161:aa5281ff4a02 2483 #define CAN_FS1R_FSC19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 2484 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 2485 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
AnnaBridge 161:aa5281ff4a02 2486 #define CAN_FS1R_FSC20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 2487 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 2488 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
AnnaBridge 161:aa5281ff4a02 2489 #define CAN_FS1R_FSC21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2490 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 2491 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
AnnaBridge 161:aa5281ff4a02 2492 #define CAN_FS1R_FSC22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 2493 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 2494 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
AnnaBridge 161:aa5281ff4a02 2495 #define CAN_FS1R_FSC23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 2496 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 2497 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
AnnaBridge 161:aa5281ff4a02 2498 #define CAN_FS1R_FSC24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2499 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 2500 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
AnnaBridge 161:aa5281ff4a02 2501 #define CAN_FS1R_FSC25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 2502 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 2503 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
AnnaBridge 161:aa5281ff4a02 2504 #define CAN_FS1R_FSC26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 2505 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 2506 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
AnnaBridge 161:aa5281ff4a02 2507 #define CAN_FS1R_FSC27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 2508 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 2509 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
AnnaBridge 161:aa5281ff4a02 2510
AnnaBridge 161:aa5281ff4a02 2511 /****************** Bit definition for CAN_FFA1R register *******************/
AnnaBridge 161:aa5281ff4a02 2512 #define CAN_FFA1R_FFA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2513 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 161:aa5281ff4a02 2514 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
AnnaBridge 161:aa5281ff4a02 2515 #define CAN_FFA1R_FFA0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2516 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2517 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
AnnaBridge 161:aa5281ff4a02 2518 #define CAN_FFA1R_FFA1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2519 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2520 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
AnnaBridge 161:aa5281ff4a02 2521 #define CAN_FFA1R_FFA2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2522 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2523 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
AnnaBridge 161:aa5281ff4a02 2524 #define CAN_FFA1R_FFA3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2525 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 2526 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
AnnaBridge 161:aa5281ff4a02 2527 #define CAN_FFA1R_FFA4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2528 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2529 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
AnnaBridge 161:aa5281ff4a02 2530 #define CAN_FFA1R_FFA5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 2531 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 2532 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
AnnaBridge 161:aa5281ff4a02 2533 #define CAN_FFA1R_FFA6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 2534 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 2535 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
AnnaBridge 161:aa5281ff4a02 2536 #define CAN_FFA1R_FFA7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 2537 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 2538 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
AnnaBridge 161:aa5281ff4a02 2539 #define CAN_FFA1R_FFA8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2540 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2541 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
AnnaBridge 161:aa5281ff4a02 2542 #define CAN_FFA1R_FFA9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 2543 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 2544 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
AnnaBridge 161:aa5281ff4a02 2545 #define CAN_FFA1R_FFA10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 2546 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 2547 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
AnnaBridge 161:aa5281ff4a02 2548 #define CAN_FFA1R_FFA11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 2549 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 2550 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
AnnaBridge 161:aa5281ff4a02 2551 #define CAN_FFA1R_FFA12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 2552 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 2553 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
AnnaBridge 161:aa5281ff4a02 2554 #define CAN_FFA1R_FFA13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 2555 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 2556 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
AnnaBridge 161:aa5281ff4a02 2557 #define CAN_FFA1R_FFA14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 2558 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 2559 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
AnnaBridge 161:aa5281ff4a02 2560 #define CAN_FFA1R_FFA15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 2561 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 2562 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
AnnaBridge 161:aa5281ff4a02 2563 #define CAN_FFA1R_FFA16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2564 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 2565 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
AnnaBridge 161:aa5281ff4a02 2566 #define CAN_FFA1R_FFA17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 2567 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 2568 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
AnnaBridge 161:aa5281ff4a02 2569 #define CAN_FFA1R_FFA18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 2570 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 2571 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
AnnaBridge 161:aa5281ff4a02 2572 #define CAN_FFA1R_FFA19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 2573 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 2574 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
AnnaBridge 161:aa5281ff4a02 2575 #define CAN_FFA1R_FFA20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 2576 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 2577 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
AnnaBridge 161:aa5281ff4a02 2578 #define CAN_FFA1R_FFA21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2579 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 2580 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
AnnaBridge 161:aa5281ff4a02 2581 #define CAN_FFA1R_FFA22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 2582 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 2583 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
AnnaBridge 161:aa5281ff4a02 2584 #define CAN_FFA1R_FFA23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 2585 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 2586 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
AnnaBridge 161:aa5281ff4a02 2587 #define CAN_FFA1R_FFA24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2588 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 2589 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
AnnaBridge 161:aa5281ff4a02 2590 #define CAN_FFA1R_FFA25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 2591 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 2592 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
AnnaBridge 161:aa5281ff4a02 2593 #define CAN_FFA1R_FFA26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 2594 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 2595 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
AnnaBridge 161:aa5281ff4a02 2596 #define CAN_FFA1R_FFA27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 2597 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 2598 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
AnnaBridge 161:aa5281ff4a02 2599
AnnaBridge 161:aa5281ff4a02 2600 /******************* Bit definition for CAN_FA1R register *******************/
AnnaBridge 161:aa5281ff4a02 2601 #define CAN_FA1R_FACT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2602 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 161:aa5281ff4a02 2603 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
AnnaBridge 161:aa5281ff4a02 2604 #define CAN_FA1R_FACT0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2605 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2606 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
AnnaBridge 161:aa5281ff4a02 2607 #define CAN_FA1R_FACT1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2608 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2609 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
AnnaBridge 161:aa5281ff4a02 2610 #define CAN_FA1R_FACT2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2611 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2612 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
AnnaBridge 161:aa5281ff4a02 2613 #define CAN_FA1R_FACT3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2614 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 2615 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
AnnaBridge 161:aa5281ff4a02 2616 #define CAN_FA1R_FACT4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2617 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2618 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
AnnaBridge 161:aa5281ff4a02 2619 #define CAN_FA1R_FACT5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 2620 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 2621 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
AnnaBridge 161:aa5281ff4a02 2622 #define CAN_FA1R_FACT6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 2623 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 2624 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
AnnaBridge 161:aa5281ff4a02 2625 #define CAN_FA1R_FACT7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 2626 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 2627 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
AnnaBridge 161:aa5281ff4a02 2628 #define CAN_FA1R_FACT8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2629 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2630 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
AnnaBridge 161:aa5281ff4a02 2631 #define CAN_FA1R_FACT9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 2632 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 2633 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
AnnaBridge 161:aa5281ff4a02 2634 #define CAN_FA1R_FACT10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 2635 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 2636 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
AnnaBridge 161:aa5281ff4a02 2637 #define CAN_FA1R_FACT11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 2638 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 2639 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
AnnaBridge 161:aa5281ff4a02 2640 #define CAN_FA1R_FACT12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 2641 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 2642 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
AnnaBridge 161:aa5281ff4a02 2643 #define CAN_FA1R_FACT13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 2644 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 2645 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
AnnaBridge 161:aa5281ff4a02 2646 #define CAN_FA1R_FACT14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 2647 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 2648 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
AnnaBridge 161:aa5281ff4a02 2649 #define CAN_FA1R_FACT15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 2650 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 2651 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
AnnaBridge 161:aa5281ff4a02 2652 #define CAN_FA1R_FACT16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2653 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 2654 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
AnnaBridge 161:aa5281ff4a02 2655 #define CAN_FA1R_FACT17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 2656 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 2657 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
AnnaBridge 161:aa5281ff4a02 2658 #define CAN_FA1R_FACT18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 2659 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 2660 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
AnnaBridge 161:aa5281ff4a02 2661 #define CAN_FA1R_FACT19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 2662 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 2663 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
AnnaBridge 161:aa5281ff4a02 2664 #define CAN_FA1R_FACT20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 2665 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 2666 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
AnnaBridge 161:aa5281ff4a02 2667 #define CAN_FA1R_FACT21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2668 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 2669 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
AnnaBridge 161:aa5281ff4a02 2670 #define CAN_FA1R_FACT22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 2671 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 2672 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
AnnaBridge 161:aa5281ff4a02 2673 #define CAN_FA1R_FACT23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 2674 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 2675 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
AnnaBridge 161:aa5281ff4a02 2676 #define CAN_FA1R_FACT24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2677 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 2678 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
AnnaBridge 161:aa5281ff4a02 2679 #define CAN_FA1R_FACT25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 2680 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 2681 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
AnnaBridge 161:aa5281ff4a02 2682 #define CAN_FA1R_FACT26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 2683 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 2684 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
AnnaBridge 161:aa5281ff4a02 2685 #define CAN_FA1R_FACT27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 2686 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 2687 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
AnnaBridge 161:aa5281ff4a02 2688
AnnaBridge 161:aa5281ff4a02 2689
AnnaBridge 161:aa5281ff4a02 2690 /******************* Bit definition for CAN_F0R1 register *******************/
AnnaBridge 161:aa5281ff4a02 2691 #define CAN_F0R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2692 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2693 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 2694 #define CAN_F0R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2695 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2696 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 2697 #define CAN_F0R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2698 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2699 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 2700 #define CAN_F0R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2701 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 2702 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 2703 #define CAN_F0R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2704 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2705 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 2706 #define CAN_F0R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 2707 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 2708 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 2709 #define CAN_F0R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 2710 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 2711 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 2712 #define CAN_F0R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 2713 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 2714 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 2715 #define CAN_F0R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2716 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2717 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 2718 #define CAN_F0R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 2719 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 2720 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 2721 #define CAN_F0R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 2722 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 2723 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 2724 #define CAN_F0R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 2725 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 2726 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 2727 #define CAN_F0R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 2728 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 2729 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 2730 #define CAN_F0R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 2731 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 2732 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 2733 #define CAN_F0R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 2734 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 2735 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 2736 #define CAN_F0R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 2737 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 2738 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 2739 #define CAN_F0R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2740 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 2741 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 2742 #define CAN_F0R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 2743 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 2744 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 2745 #define CAN_F0R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 2746 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 2747 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 2748 #define CAN_F0R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 2749 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 2750 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 2751 #define CAN_F0R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 2752 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 2753 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 2754 #define CAN_F0R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2755 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 2756 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 2757 #define CAN_F0R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 2758 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 2759 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 2760 #define CAN_F0R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 2761 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 2762 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 2763 #define CAN_F0R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2764 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 2765 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 2766 #define CAN_F0R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 2767 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 2768 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 2769 #define CAN_F0R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 2770 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 2771 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 2772 #define CAN_F0R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 2773 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 2774 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 2775 #define CAN_F0R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 2776 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 2777 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 2778 #define CAN_F0R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 2779 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 2780 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 2781 #define CAN_F0R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 2782 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 2783 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 2784 #define CAN_F0R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 2785 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 2786 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 2787
AnnaBridge 161:aa5281ff4a02 2788 /******************* Bit definition for CAN_F1R1 register *******************/
AnnaBridge 161:aa5281ff4a02 2789 #define CAN_F1R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2790 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2791 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 2792 #define CAN_F1R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2793 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2794 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 2795 #define CAN_F1R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2796 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2797 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 2798 #define CAN_F1R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2799 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 2800 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 2801 #define CAN_F1R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2802 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2803 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 2804 #define CAN_F1R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 2805 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 2806 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 2807 #define CAN_F1R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 2808 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 2809 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 2810 #define CAN_F1R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 2811 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 2812 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 2813 #define CAN_F1R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2814 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2815 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 2816 #define CAN_F1R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 2817 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 2818 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 2819 #define CAN_F1R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 2820 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 2821 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 2822 #define CAN_F1R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 2823 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 2824 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 2825 #define CAN_F1R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 2826 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 2827 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 2828 #define CAN_F1R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 2829 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 2830 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 2831 #define CAN_F1R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 2832 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 2833 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 2834 #define CAN_F1R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 2835 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 2836 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 2837 #define CAN_F1R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2838 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 2839 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 2840 #define CAN_F1R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 2841 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 2842 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 2843 #define CAN_F1R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 2844 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 2845 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 2846 #define CAN_F1R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 2847 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 2848 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 2849 #define CAN_F1R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 2850 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 2851 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 2852 #define CAN_F1R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2853 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 2854 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 2855 #define CAN_F1R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 2856 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 2857 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 2858 #define CAN_F1R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 2859 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 2860 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 2861 #define CAN_F1R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2862 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 2863 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 2864 #define CAN_F1R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 2865 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 2866 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 2867 #define CAN_F1R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 2868 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 2869 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 2870 #define CAN_F1R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 2871 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 2872 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 2873 #define CAN_F1R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 2874 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 2875 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 2876 #define CAN_F1R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 2877 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 2878 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 2879 #define CAN_F1R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 2880 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 2881 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 2882 #define CAN_F1R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 2883 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 2884 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 2885
AnnaBridge 161:aa5281ff4a02 2886 /******************* Bit definition for CAN_F2R1 register *******************/
AnnaBridge 161:aa5281ff4a02 2887 #define CAN_F2R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2888 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2889 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 2890 #define CAN_F2R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2891 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2892 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 2893 #define CAN_F2R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2894 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2895 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 2896 #define CAN_F2R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2897 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 2898 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 2899 #define CAN_F2R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2900 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2901 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 2902 #define CAN_F2R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 2903 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 2904 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 2905 #define CAN_F2R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 2906 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 2907 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 2908 #define CAN_F2R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 2909 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 2910 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 2911 #define CAN_F2R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 2912 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 2913 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 2914 #define CAN_F2R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 2915 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 2916 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 2917 #define CAN_F2R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 2918 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 2919 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 2920 #define CAN_F2R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 2921 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 2922 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 2923 #define CAN_F2R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 2924 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 2925 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 2926 #define CAN_F2R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 2927 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 2928 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 2929 #define CAN_F2R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 2930 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 2931 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 2932 #define CAN_F2R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 2933 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 2934 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 2935 #define CAN_F2R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 2936 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 2937 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 2938 #define CAN_F2R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 2939 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 2940 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 2941 #define CAN_F2R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 2942 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 2943 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 2944 #define CAN_F2R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 2945 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 2946 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 2947 #define CAN_F2R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 2948 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 2949 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 2950 #define CAN_F2R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 2951 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 2952 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 2953 #define CAN_F2R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 2954 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 2955 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 2956 #define CAN_F2R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 2957 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 2958 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 2959 #define CAN_F2R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 2960 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 2961 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 2962 #define CAN_F2R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 2963 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 2964 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 2965 #define CAN_F2R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 2966 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 2967 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 2968 #define CAN_F2R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 2969 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 2970 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 2971 #define CAN_F2R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 2972 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 2973 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 2974 #define CAN_F2R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 2975 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 2976 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 2977 #define CAN_F2R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 2978 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 2979 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 2980 #define CAN_F2R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 2981 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 2982 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 2983
AnnaBridge 161:aa5281ff4a02 2984 /******************* Bit definition for CAN_F3R1 register *******************/
AnnaBridge 161:aa5281ff4a02 2985 #define CAN_F3R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 2986 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 2987 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 2988 #define CAN_F3R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 2989 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 2990 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 2991 #define CAN_F3R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 2992 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 2993 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 2994 #define CAN_F3R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 2995 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 2996 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 2997 #define CAN_F3R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 2998 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 2999 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3000 #define CAN_F3R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3001 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3002 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3003 #define CAN_F3R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3004 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3005 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3006 #define CAN_F3R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3007 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3008 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3009 #define CAN_F3R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3010 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3011 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3012 #define CAN_F3R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3013 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3014 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3015 #define CAN_F3R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3016 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3017 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3018 #define CAN_F3R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3019 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3020 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3021 #define CAN_F3R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3022 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3023 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3024 #define CAN_F3R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3025 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3026 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3027 #define CAN_F3R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3028 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3029 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3030 #define CAN_F3R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3031 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3032 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3033 #define CAN_F3R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3034 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3035 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3036 #define CAN_F3R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3037 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3038 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3039 #define CAN_F3R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3040 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3041 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3042 #define CAN_F3R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3043 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3044 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3045 #define CAN_F3R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3046 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3047 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3048 #define CAN_F3R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3049 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3050 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3051 #define CAN_F3R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3052 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3053 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3054 #define CAN_F3R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3055 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3056 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3057 #define CAN_F3R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3058 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3059 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3060 #define CAN_F3R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3061 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3062 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3063 #define CAN_F3R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3064 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3065 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3066 #define CAN_F3R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3067 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3068 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3069 #define CAN_F3R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3070 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3071 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3072 #define CAN_F3R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3073 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3074 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3075 #define CAN_F3R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3076 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3077 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3078 #define CAN_F3R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3079 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3080 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3081
AnnaBridge 161:aa5281ff4a02 3082 /******************* Bit definition for CAN_F4R1 register *******************/
AnnaBridge 161:aa5281ff4a02 3083 #define CAN_F4R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3084 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3085 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3086 #define CAN_F4R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3087 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3088 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3089 #define CAN_F4R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3090 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3091 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3092 #define CAN_F4R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3093 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3094 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3095 #define CAN_F4R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3096 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3097 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3098 #define CAN_F4R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3099 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3100 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3101 #define CAN_F4R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3102 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3103 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3104 #define CAN_F4R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3105 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3106 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3107 #define CAN_F4R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3108 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3109 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3110 #define CAN_F4R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3111 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3112 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3113 #define CAN_F4R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3114 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3115 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3116 #define CAN_F4R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3117 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3118 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3119 #define CAN_F4R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3120 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3121 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3122 #define CAN_F4R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3123 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3124 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3125 #define CAN_F4R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3126 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3127 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3128 #define CAN_F4R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3129 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3130 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3131 #define CAN_F4R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3132 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3133 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3134 #define CAN_F4R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3135 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3136 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3137 #define CAN_F4R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3138 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3139 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3140 #define CAN_F4R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3141 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3142 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3143 #define CAN_F4R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3144 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3145 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3146 #define CAN_F4R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3147 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3148 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3149 #define CAN_F4R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3150 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3151 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3152 #define CAN_F4R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3153 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3154 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3155 #define CAN_F4R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3156 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3157 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3158 #define CAN_F4R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3159 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3160 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3161 #define CAN_F4R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3162 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3163 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3164 #define CAN_F4R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3165 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3166 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3167 #define CAN_F4R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3168 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3169 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3170 #define CAN_F4R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3171 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3172 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3173 #define CAN_F4R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3174 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3175 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3176 #define CAN_F4R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3177 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3178 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3179
AnnaBridge 161:aa5281ff4a02 3180 /******************* Bit definition for CAN_F5R1 register *******************/
AnnaBridge 161:aa5281ff4a02 3181 #define CAN_F5R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3182 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3183 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3184 #define CAN_F5R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3185 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3186 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3187 #define CAN_F5R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3188 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3189 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3190 #define CAN_F5R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3191 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3192 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3193 #define CAN_F5R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3194 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3195 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3196 #define CAN_F5R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3197 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3198 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3199 #define CAN_F5R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3200 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3201 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3202 #define CAN_F5R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3203 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3204 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3205 #define CAN_F5R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3206 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3207 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3208 #define CAN_F5R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3209 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3210 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3211 #define CAN_F5R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3212 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3213 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3214 #define CAN_F5R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3215 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3216 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3217 #define CAN_F5R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3218 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3219 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3220 #define CAN_F5R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3221 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3222 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3223 #define CAN_F5R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3224 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3225 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3226 #define CAN_F5R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3227 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3228 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3229 #define CAN_F5R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3230 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3231 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3232 #define CAN_F5R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3233 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3234 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3235 #define CAN_F5R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3236 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3237 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3238 #define CAN_F5R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3239 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3240 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3241 #define CAN_F5R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3242 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3243 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3244 #define CAN_F5R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3245 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3246 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3247 #define CAN_F5R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3248 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3249 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3250 #define CAN_F5R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3251 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3252 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3253 #define CAN_F5R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3254 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3255 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3256 #define CAN_F5R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3257 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3258 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3259 #define CAN_F5R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3260 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3261 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3262 #define CAN_F5R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3263 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3264 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3265 #define CAN_F5R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3266 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3267 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3268 #define CAN_F5R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3269 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3270 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3271 #define CAN_F5R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3272 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3273 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3274 #define CAN_F5R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3275 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3276 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3277
AnnaBridge 161:aa5281ff4a02 3278 /******************* Bit definition for CAN_F6R1 register *******************/
AnnaBridge 161:aa5281ff4a02 3279 #define CAN_F6R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3280 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3281 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3282 #define CAN_F6R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3283 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3284 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3285 #define CAN_F6R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3286 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3287 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3288 #define CAN_F6R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3289 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3290 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3291 #define CAN_F6R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3292 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3293 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3294 #define CAN_F6R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3295 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3296 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3297 #define CAN_F6R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3298 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3299 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3300 #define CAN_F6R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3301 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3302 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3303 #define CAN_F6R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3304 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3305 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3306 #define CAN_F6R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3307 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3308 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3309 #define CAN_F6R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3310 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3311 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3312 #define CAN_F6R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3313 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3314 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3315 #define CAN_F6R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3316 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3317 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3318 #define CAN_F6R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3319 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3320 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3321 #define CAN_F6R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3322 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3323 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3324 #define CAN_F6R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3325 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3326 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3327 #define CAN_F6R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3328 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3329 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3330 #define CAN_F6R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3331 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3332 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3333 #define CAN_F6R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3334 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3335 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3336 #define CAN_F6R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3337 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3338 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3339 #define CAN_F6R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3340 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3341 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3342 #define CAN_F6R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3343 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3344 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3345 #define CAN_F6R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3346 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3347 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3348 #define CAN_F6R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3349 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3350 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3351 #define CAN_F6R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3352 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3353 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3354 #define CAN_F6R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3355 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3356 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3357 #define CAN_F6R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3358 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3359 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3360 #define CAN_F6R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3361 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3362 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3363 #define CAN_F6R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3364 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3365 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3366 #define CAN_F6R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3367 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3368 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3369 #define CAN_F6R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3370 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3371 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3372 #define CAN_F6R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3373 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3374 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3375
AnnaBridge 161:aa5281ff4a02 3376 /******************* Bit definition for CAN_F7R1 register *******************/
AnnaBridge 161:aa5281ff4a02 3377 #define CAN_F7R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3378 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3379 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3380 #define CAN_F7R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3381 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3382 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3383 #define CAN_F7R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3384 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3385 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3386 #define CAN_F7R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3387 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3388 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3389 #define CAN_F7R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3390 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3391 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3392 #define CAN_F7R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3393 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3394 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3395 #define CAN_F7R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3396 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3397 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3398 #define CAN_F7R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3399 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3400 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3401 #define CAN_F7R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3402 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3403 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3404 #define CAN_F7R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3405 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3406 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3407 #define CAN_F7R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3408 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3409 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3410 #define CAN_F7R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3411 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3412 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3413 #define CAN_F7R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3414 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3415 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3416 #define CAN_F7R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3417 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3418 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3419 #define CAN_F7R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3420 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3421 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3422 #define CAN_F7R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3423 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3424 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3425 #define CAN_F7R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3426 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3427 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3428 #define CAN_F7R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3429 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3430 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3431 #define CAN_F7R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3432 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3433 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3434 #define CAN_F7R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3435 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3436 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3437 #define CAN_F7R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3438 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3439 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3440 #define CAN_F7R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3441 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3442 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3443 #define CAN_F7R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3444 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3445 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3446 #define CAN_F7R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3447 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3448 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3449 #define CAN_F7R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3450 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3451 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3452 #define CAN_F7R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3453 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3454 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3455 #define CAN_F7R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3456 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3457 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3458 #define CAN_F7R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3459 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3460 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3461 #define CAN_F7R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3462 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3463 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3464 #define CAN_F7R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3465 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3466 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3467 #define CAN_F7R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3468 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3469 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3470 #define CAN_F7R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3471 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3472 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3473
AnnaBridge 161:aa5281ff4a02 3474 /******************* Bit definition for CAN_F8R1 register *******************/
AnnaBridge 161:aa5281ff4a02 3475 #define CAN_F8R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3476 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3477 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3478 #define CAN_F8R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3479 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3480 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3481 #define CAN_F8R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3482 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3483 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3484 #define CAN_F8R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3485 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3486 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3487 #define CAN_F8R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3488 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3489 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3490 #define CAN_F8R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3491 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3492 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3493 #define CAN_F8R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3494 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3495 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3496 #define CAN_F8R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3497 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3498 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3499 #define CAN_F8R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3500 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3501 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3502 #define CAN_F8R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3503 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3504 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3505 #define CAN_F8R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3506 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3507 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3508 #define CAN_F8R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3509 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3510 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3511 #define CAN_F8R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3512 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3513 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3514 #define CAN_F8R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3515 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3516 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3517 #define CAN_F8R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3518 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3519 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3520 #define CAN_F8R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3521 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3522 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3523 #define CAN_F8R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3524 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3525 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3526 #define CAN_F8R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3527 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3528 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3529 #define CAN_F8R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3530 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3531 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3532 #define CAN_F8R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3533 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3534 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3535 #define CAN_F8R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3536 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3537 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3538 #define CAN_F8R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3539 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3540 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3541 #define CAN_F8R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3542 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3543 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3544 #define CAN_F8R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3545 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3546 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3547 #define CAN_F8R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3548 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3549 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3550 #define CAN_F8R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3551 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3552 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3553 #define CAN_F8R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3554 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3555 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3556 #define CAN_F8R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3557 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3558 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3559 #define CAN_F8R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3560 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3561 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3562 #define CAN_F8R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3563 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3564 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3565 #define CAN_F8R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3566 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3567 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3568 #define CAN_F8R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3569 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3570 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3571
AnnaBridge 161:aa5281ff4a02 3572 /******************* Bit definition for CAN_F9R1 register *******************/
AnnaBridge 161:aa5281ff4a02 3573 #define CAN_F9R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3574 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3575 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3576 #define CAN_F9R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3577 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3578 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3579 #define CAN_F9R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3580 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3581 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3582 #define CAN_F9R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3583 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3584 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3585 #define CAN_F9R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3586 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3587 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3588 #define CAN_F9R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3589 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3590 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3591 #define CAN_F9R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3592 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3593 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3594 #define CAN_F9R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3595 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3596 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3597 #define CAN_F9R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3598 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3599 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3600 #define CAN_F9R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3601 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3602 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3603 #define CAN_F9R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3604 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3605 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3606 #define CAN_F9R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3607 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3608 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3609 #define CAN_F9R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3610 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3611 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3612 #define CAN_F9R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3613 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3614 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3615 #define CAN_F9R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3616 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3617 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3618 #define CAN_F9R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3619 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3620 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3621 #define CAN_F9R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3622 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3623 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3624 #define CAN_F9R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3625 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3626 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3627 #define CAN_F9R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3628 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3629 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3630 #define CAN_F9R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3631 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3632 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3633 #define CAN_F9R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3634 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3635 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3636 #define CAN_F9R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3637 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3638 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3639 #define CAN_F9R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3640 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3641 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3642 #define CAN_F9R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3643 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3644 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3645 #define CAN_F9R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3646 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3647 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3648 #define CAN_F9R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3649 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3650 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3651 #define CAN_F9R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3652 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3653 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3654 #define CAN_F9R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3655 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3656 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3657 #define CAN_F9R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3658 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3659 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3660 #define CAN_F9R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3661 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3662 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3663 #define CAN_F9R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3664 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3665 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3666 #define CAN_F9R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3667 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3668 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3669
AnnaBridge 161:aa5281ff4a02 3670 /******************* Bit definition for CAN_F10R1 register ******************/
AnnaBridge 161:aa5281ff4a02 3671 #define CAN_F10R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3672 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3673 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3674 #define CAN_F10R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3675 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3676 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3677 #define CAN_F10R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3678 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3679 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3680 #define CAN_F10R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3681 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3682 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3683 #define CAN_F10R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3684 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3685 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3686 #define CAN_F10R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3687 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3688 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3689 #define CAN_F10R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3690 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3691 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3692 #define CAN_F10R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3693 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3694 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3695 #define CAN_F10R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3696 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3697 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3698 #define CAN_F10R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3699 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3700 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3701 #define CAN_F10R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3702 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3703 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3704 #define CAN_F10R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3705 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3706 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3707 #define CAN_F10R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3708 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3709 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3710 #define CAN_F10R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3711 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3712 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3713 #define CAN_F10R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3714 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3715 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3716 #define CAN_F10R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3717 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3718 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3719 #define CAN_F10R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3720 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3721 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3722 #define CAN_F10R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3723 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3724 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3725 #define CAN_F10R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3726 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3727 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3728 #define CAN_F10R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3729 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3730 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3731 #define CAN_F10R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3732 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3733 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3734 #define CAN_F10R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3735 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3736 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3737 #define CAN_F10R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3738 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3739 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3740 #define CAN_F10R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3741 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3742 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3743 #define CAN_F10R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3744 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3745 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3746 #define CAN_F10R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3747 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3748 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3749 #define CAN_F10R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3750 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3751 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3752 #define CAN_F10R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3753 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3754 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3755 #define CAN_F10R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3756 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3757 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3758 #define CAN_F10R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3759 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3760 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3761 #define CAN_F10R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3762 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3763 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3764 #define CAN_F10R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3765 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3766 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3767
AnnaBridge 161:aa5281ff4a02 3768 /******************* Bit definition for CAN_F11R1 register ******************/
AnnaBridge 161:aa5281ff4a02 3769 #define CAN_F11R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3770 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3771 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3772 #define CAN_F11R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3773 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3774 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3775 #define CAN_F11R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3776 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3777 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3778 #define CAN_F11R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3779 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3780 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3781 #define CAN_F11R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3782 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3783 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3784 #define CAN_F11R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3785 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3786 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3787 #define CAN_F11R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3788 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3789 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3790 #define CAN_F11R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3791 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3792 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3793 #define CAN_F11R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3794 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3795 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3796 #define CAN_F11R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3797 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3798 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3799 #define CAN_F11R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3800 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3801 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3802 #define CAN_F11R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3803 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3804 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3805 #define CAN_F11R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3806 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3807 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3808 #define CAN_F11R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3809 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3810 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3811 #define CAN_F11R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3812 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3813 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3814 #define CAN_F11R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3815 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3816 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3817 #define CAN_F11R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3818 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3819 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3820 #define CAN_F11R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3821 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3822 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3823 #define CAN_F11R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3824 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3825 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3826 #define CAN_F11R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3827 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3828 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3829 #define CAN_F11R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3830 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3831 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3832 #define CAN_F11R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3833 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3834 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3835 #define CAN_F11R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3836 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3837 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3838 #define CAN_F11R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3839 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3840 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3841 #define CAN_F11R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3842 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3843 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3844 #define CAN_F11R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3845 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3846 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3847 #define CAN_F11R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3848 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3849 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3850 #define CAN_F11R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3851 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3852 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3853 #define CAN_F11R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3854 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3855 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3856 #define CAN_F11R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3857 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3858 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3859 #define CAN_F11R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3860 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3861 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3862 #define CAN_F11R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3863 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3864 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3865
AnnaBridge 161:aa5281ff4a02 3866 /******************* Bit definition for CAN_F12R1 register ******************/
AnnaBridge 161:aa5281ff4a02 3867 #define CAN_F12R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3868 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3869 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3870 #define CAN_F12R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3871 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3872 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3873 #define CAN_F12R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3874 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3875 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3876 #define CAN_F12R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3877 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3878 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3879 #define CAN_F12R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3880 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3881 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3882 #define CAN_F12R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3883 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3884 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3885 #define CAN_F12R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3886 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3887 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3888 #define CAN_F12R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3889 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3890 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3891 #define CAN_F12R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3892 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3893 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3894 #define CAN_F12R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3895 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3896 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3897 #define CAN_F12R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3898 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3899 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3900 #define CAN_F12R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3901 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 3902 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 3903 #define CAN_F12R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 3904 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 3905 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 3906 #define CAN_F12R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 3907 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 3908 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 3909 #define CAN_F12R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 3910 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 3911 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 3912 #define CAN_F12R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 3913 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 3914 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 3915 #define CAN_F12R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 3916 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 3917 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 3918 #define CAN_F12R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 3919 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 3920 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 3921 #define CAN_F12R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 3922 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 3923 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 3924 #define CAN_F12R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 3925 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 3926 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 3927 #define CAN_F12R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 3928 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 3929 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 3930 #define CAN_F12R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 3931 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 3932 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 3933 #define CAN_F12R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 3934 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 3935 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 3936 #define CAN_F12R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 3937 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 3938 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 3939 #define CAN_F12R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 3940 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 3941 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 3942 #define CAN_F12R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 3943 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 3944 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 3945 #define CAN_F12R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 3946 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 3947 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 3948 #define CAN_F12R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 3949 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 3950 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 3951 #define CAN_F12R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 3952 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 3953 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 3954 #define CAN_F12R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 3955 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 3956 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 3957 #define CAN_F12R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 3958 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 3959 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 3960 #define CAN_F12R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 3961 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 3962 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 3963
AnnaBridge 161:aa5281ff4a02 3964 /******************* Bit definition for CAN_F13R1 register ******************/
AnnaBridge 161:aa5281ff4a02 3965 #define CAN_F13R1_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 3966 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 3967 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 3968 #define CAN_F13R1_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 3969 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 3970 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 3971 #define CAN_F13R1_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 3972 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 3973 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 3974 #define CAN_F13R1_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 3975 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 3976 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 3977 #define CAN_F13R1_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 3978 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 3979 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 3980 #define CAN_F13R1_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 3981 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 3982 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 3983 #define CAN_F13R1_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 3984 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 3985 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 3986 #define CAN_F13R1_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 3987 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 3988 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 3989 #define CAN_F13R1_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 3990 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 3991 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 3992 #define CAN_F13R1_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 3993 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 3994 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 3995 #define CAN_F13R1_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 3996 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 3997 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 3998 #define CAN_F13R1_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 3999 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4000 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4001 #define CAN_F13R1_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4002 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4003 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4004 #define CAN_F13R1_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4005 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4006 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4007 #define CAN_F13R1_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4008 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4009 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4010 #define CAN_F13R1_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4011 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4012 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4013 #define CAN_F13R1_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4014 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4015 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4016 #define CAN_F13R1_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4017 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4018 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4019 #define CAN_F13R1_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4020 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4021 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4022 #define CAN_F13R1_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4023 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4024 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4025 #define CAN_F13R1_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4026 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4027 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4028 #define CAN_F13R1_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4029 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4030 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4031 #define CAN_F13R1_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4032 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4033 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4034 #define CAN_F13R1_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4035 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4036 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4037 #define CAN_F13R1_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4038 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4039 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4040 #define CAN_F13R1_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4041 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4042 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4043 #define CAN_F13R1_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4044 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4045 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4046 #define CAN_F13R1_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4047 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4048 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4049 #define CAN_F13R1_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4050 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4051 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4052 #define CAN_F13R1_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4053 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4054 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4055 #define CAN_F13R1_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4056 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4057 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4058 #define CAN_F13R1_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4059 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4060 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4061
AnnaBridge 161:aa5281ff4a02 4062 /******************* Bit definition for CAN_F0R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4063 #define CAN_F0R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4064 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4065 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4066 #define CAN_F0R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4067 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4068 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4069 #define CAN_F0R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4070 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4071 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4072 #define CAN_F0R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4073 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4074 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4075 #define CAN_F0R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4076 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4077 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4078 #define CAN_F0R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4079 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4080 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4081 #define CAN_F0R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4082 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4083 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4084 #define CAN_F0R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4085 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4086 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4087 #define CAN_F0R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4088 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4089 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4090 #define CAN_F0R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4091 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4092 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4093 #define CAN_F0R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4094 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4095 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4096 #define CAN_F0R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4097 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4098 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4099 #define CAN_F0R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4100 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4101 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4102 #define CAN_F0R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4103 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4104 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4105 #define CAN_F0R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4106 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4107 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4108 #define CAN_F0R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4109 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4110 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4111 #define CAN_F0R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4112 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4113 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4114 #define CAN_F0R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4115 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4116 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4117 #define CAN_F0R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4118 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4119 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4120 #define CAN_F0R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4121 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4122 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4123 #define CAN_F0R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4124 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4125 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4126 #define CAN_F0R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4127 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4128 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4129 #define CAN_F0R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4130 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4131 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4132 #define CAN_F0R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4133 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4134 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4135 #define CAN_F0R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4136 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4137 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4138 #define CAN_F0R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4139 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4140 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4141 #define CAN_F0R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4142 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4143 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4144 #define CAN_F0R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4145 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4146 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4147 #define CAN_F0R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4148 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4149 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4150 #define CAN_F0R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4151 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4152 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4153 #define CAN_F0R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4154 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4155 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4156 #define CAN_F0R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4157 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4158 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4159
AnnaBridge 161:aa5281ff4a02 4160 /******************* Bit definition for CAN_F1R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4161 #define CAN_F1R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4162 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4163 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4164 #define CAN_F1R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4165 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4166 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4167 #define CAN_F1R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4168 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4169 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4170 #define CAN_F1R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4171 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4172 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4173 #define CAN_F1R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4174 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4175 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4176 #define CAN_F1R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4177 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4178 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4179 #define CAN_F1R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4180 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4181 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4182 #define CAN_F1R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4183 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4184 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4185 #define CAN_F1R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4186 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4187 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4188 #define CAN_F1R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4189 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4190 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4191 #define CAN_F1R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4192 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4193 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4194 #define CAN_F1R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4195 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4196 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4197 #define CAN_F1R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4198 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4199 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4200 #define CAN_F1R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4201 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4202 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4203 #define CAN_F1R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4204 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4205 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4206 #define CAN_F1R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4207 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4208 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4209 #define CAN_F1R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4210 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4211 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4212 #define CAN_F1R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4213 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4214 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4215 #define CAN_F1R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4216 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4217 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4218 #define CAN_F1R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4219 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4220 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4221 #define CAN_F1R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4222 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4223 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4224 #define CAN_F1R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4225 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4226 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4227 #define CAN_F1R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4228 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4229 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4230 #define CAN_F1R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4231 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4232 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4233 #define CAN_F1R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4234 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4235 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4236 #define CAN_F1R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4237 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4238 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4239 #define CAN_F1R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4240 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4241 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4242 #define CAN_F1R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4243 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4244 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4245 #define CAN_F1R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4246 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4247 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4248 #define CAN_F1R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4249 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4250 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4251 #define CAN_F1R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4252 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4253 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4254 #define CAN_F1R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4255 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4256 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4257
AnnaBridge 161:aa5281ff4a02 4258 /******************* Bit definition for CAN_F2R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4259 #define CAN_F2R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4260 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4261 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4262 #define CAN_F2R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4263 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4264 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4265 #define CAN_F2R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4266 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4267 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4268 #define CAN_F2R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4269 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4270 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4271 #define CAN_F2R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4272 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4273 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4274 #define CAN_F2R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4275 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4276 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4277 #define CAN_F2R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4278 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4279 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4280 #define CAN_F2R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4281 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4282 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4283 #define CAN_F2R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4284 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4285 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4286 #define CAN_F2R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4287 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4288 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4289 #define CAN_F2R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4290 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4291 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4292 #define CAN_F2R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4293 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4294 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4295 #define CAN_F2R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4296 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4297 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4298 #define CAN_F2R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4299 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4300 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4301 #define CAN_F2R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4302 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4303 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4304 #define CAN_F2R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4305 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4306 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4307 #define CAN_F2R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4308 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4309 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4310 #define CAN_F2R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4311 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4312 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4313 #define CAN_F2R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4314 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4315 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4316 #define CAN_F2R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4317 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4318 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4319 #define CAN_F2R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4320 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4321 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4322 #define CAN_F2R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4323 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4324 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4325 #define CAN_F2R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4326 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4327 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4328 #define CAN_F2R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4329 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4330 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4331 #define CAN_F2R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4332 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4333 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4334 #define CAN_F2R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4335 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4336 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4337 #define CAN_F2R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4338 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4339 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4340 #define CAN_F2R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4341 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4342 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4343 #define CAN_F2R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4344 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4345 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4346 #define CAN_F2R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4347 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4348 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4349 #define CAN_F2R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4350 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4351 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4352 #define CAN_F2R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4353 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4354 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4355
AnnaBridge 161:aa5281ff4a02 4356 /******************* Bit definition for CAN_F3R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4357 #define CAN_F3R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4358 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4359 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4360 #define CAN_F3R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4361 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4362 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4363 #define CAN_F3R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4364 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4365 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4366 #define CAN_F3R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4367 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4368 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4369 #define CAN_F3R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4370 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4371 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4372 #define CAN_F3R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4373 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4374 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4375 #define CAN_F3R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4376 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4377 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4378 #define CAN_F3R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4379 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4380 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4381 #define CAN_F3R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4382 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4383 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4384 #define CAN_F3R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4385 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4386 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4387 #define CAN_F3R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4388 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4389 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4390 #define CAN_F3R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4391 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4392 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4393 #define CAN_F3R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4394 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4395 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4396 #define CAN_F3R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4397 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4398 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4399 #define CAN_F3R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4400 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4401 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4402 #define CAN_F3R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4403 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4404 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4405 #define CAN_F3R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4406 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4407 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4408 #define CAN_F3R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4409 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4410 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4411 #define CAN_F3R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4412 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4413 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4414 #define CAN_F3R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4415 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4416 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4417 #define CAN_F3R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4418 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4419 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4420 #define CAN_F3R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4421 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4422 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4423 #define CAN_F3R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4424 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4425 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4426 #define CAN_F3R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4427 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4428 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4429 #define CAN_F3R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4430 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4431 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4432 #define CAN_F3R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4433 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4434 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4435 #define CAN_F3R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4436 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4437 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4438 #define CAN_F3R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4439 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4440 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4441 #define CAN_F3R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4442 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4443 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4444 #define CAN_F3R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4445 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4446 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4447 #define CAN_F3R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4448 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4449 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4450 #define CAN_F3R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4451 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4452 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4453
AnnaBridge 161:aa5281ff4a02 4454 /******************* Bit definition for CAN_F4R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4455 #define CAN_F4R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4456 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4457 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4458 #define CAN_F4R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4459 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4460 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4461 #define CAN_F4R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4462 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4463 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4464 #define CAN_F4R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4465 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4466 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4467 #define CAN_F4R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4468 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4469 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4470 #define CAN_F4R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4471 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4472 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4473 #define CAN_F4R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4474 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4475 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4476 #define CAN_F4R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4477 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4478 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4479 #define CAN_F4R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4480 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4481 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4482 #define CAN_F4R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4483 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4484 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4485 #define CAN_F4R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4486 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4487 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4488 #define CAN_F4R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4489 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4490 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4491 #define CAN_F4R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4492 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4493 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4494 #define CAN_F4R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4495 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4496 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4497 #define CAN_F4R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4498 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4499 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4500 #define CAN_F4R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4501 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4502 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4503 #define CAN_F4R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4504 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4505 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4506 #define CAN_F4R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4507 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4508 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4509 #define CAN_F4R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4510 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4511 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4512 #define CAN_F4R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4513 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4514 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4515 #define CAN_F4R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4516 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4517 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4518 #define CAN_F4R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4519 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4520 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4521 #define CAN_F4R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4522 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4523 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4524 #define CAN_F4R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4525 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4526 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4527 #define CAN_F4R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4528 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4529 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4530 #define CAN_F4R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4531 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4532 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4533 #define CAN_F4R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4534 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4535 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4536 #define CAN_F4R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4537 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4538 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4539 #define CAN_F4R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4540 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4541 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4542 #define CAN_F4R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4543 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4544 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4545 #define CAN_F4R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4546 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4547 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4548 #define CAN_F4R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4549 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4550 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4551
AnnaBridge 161:aa5281ff4a02 4552 /******************* Bit definition for CAN_F5R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4553 #define CAN_F5R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4554 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4555 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4556 #define CAN_F5R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4557 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4558 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4559 #define CAN_F5R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4560 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4561 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4562 #define CAN_F5R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4563 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4564 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4565 #define CAN_F5R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4566 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4567 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4568 #define CAN_F5R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4569 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4570 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4571 #define CAN_F5R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4572 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4573 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4574 #define CAN_F5R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4575 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4576 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4577 #define CAN_F5R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4578 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4579 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4580 #define CAN_F5R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4581 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4582 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4583 #define CAN_F5R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4584 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4585 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4586 #define CAN_F5R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4587 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4588 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4589 #define CAN_F5R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4590 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4591 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4592 #define CAN_F5R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4593 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4594 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4595 #define CAN_F5R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4596 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4597 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4598 #define CAN_F5R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4599 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4600 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4601 #define CAN_F5R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4602 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4603 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4604 #define CAN_F5R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4605 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4606 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4607 #define CAN_F5R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4608 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4609 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4610 #define CAN_F5R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4611 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4612 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4613 #define CAN_F5R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4614 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4615 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4616 #define CAN_F5R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4617 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4618 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4619 #define CAN_F5R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4620 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4621 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4622 #define CAN_F5R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4623 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4624 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4625 #define CAN_F5R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4626 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4627 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4628 #define CAN_F5R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4629 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4630 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4631 #define CAN_F5R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4632 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4633 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4634 #define CAN_F5R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4635 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4636 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4637 #define CAN_F5R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4638 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4639 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4640 #define CAN_F5R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4641 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4642 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4643 #define CAN_F5R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4644 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4645 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4646 #define CAN_F5R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4647 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4648 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4649
AnnaBridge 161:aa5281ff4a02 4650 /******************* Bit definition for CAN_F6R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4651 #define CAN_F6R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4652 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4653 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4654 #define CAN_F6R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4655 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4656 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4657 #define CAN_F6R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4658 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4659 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4660 #define CAN_F6R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4661 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4662 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4663 #define CAN_F6R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4664 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4665 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4666 #define CAN_F6R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4667 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4668 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4669 #define CAN_F6R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4670 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4671 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4672 #define CAN_F6R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4673 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4674 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4675 #define CAN_F6R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4676 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4677 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4678 #define CAN_F6R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4679 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4680 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4681 #define CAN_F6R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4682 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4683 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4684 #define CAN_F6R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4685 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4686 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4687 #define CAN_F6R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4688 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4689 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4690 #define CAN_F6R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4691 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4692 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4693 #define CAN_F6R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4694 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4695 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4696 #define CAN_F6R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4697 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4698 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4699 #define CAN_F6R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4700 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4701 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4702 #define CAN_F6R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4703 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4704 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4705 #define CAN_F6R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4706 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4707 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4708 #define CAN_F6R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4709 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4710 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4711 #define CAN_F6R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4712 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4713 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4714 #define CAN_F6R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4715 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4716 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4717 #define CAN_F6R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4718 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4719 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4720 #define CAN_F6R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4721 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4722 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4723 #define CAN_F6R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4724 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4725 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4726 #define CAN_F6R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4727 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4728 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4729 #define CAN_F6R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4730 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4731 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4732 #define CAN_F6R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4733 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4734 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4735 #define CAN_F6R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4736 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4737 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4738 #define CAN_F6R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4739 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4740 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4741 #define CAN_F6R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4742 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4743 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4744 #define CAN_F6R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4745 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4746 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4747
AnnaBridge 161:aa5281ff4a02 4748 /******************* Bit definition for CAN_F7R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4749 #define CAN_F7R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4750 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4751 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4752 #define CAN_F7R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4753 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4754 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4755 #define CAN_F7R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4756 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4757 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4758 #define CAN_F7R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4759 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4760 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4761 #define CAN_F7R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4762 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4763 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4764 #define CAN_F7R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4765 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4766 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4767 #define CAN_F7R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4768 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4769 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4770 #define CAN_F7R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4771 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4772 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4773 #define CAN_F7R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4774 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4775 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4776 #define CAN_F7R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4777 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4778 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4779 #define CAN_F7R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4780 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4781 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4782 #define CAN_F7R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4783 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4784 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4785 #define CAN_F7R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4786 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4787 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4788 #define CAN_F7R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4789 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4790 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4791 #define CAN_F7R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4792 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4793 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4794 #define CAN_F7R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4795 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4796 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4797 #define CAN_F7R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4798 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4799 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4800 #define CAN_F7R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4801 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4802 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4803 #define CAN_F7R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4804 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4805 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4806 #define CAN_F7R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4807 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4808 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4809 #define CAN_F7R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4810 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4811 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4812 #define CAN_F7R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4813 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4814 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4815 #define CAN_F7R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4816 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4817 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4818 #define CAN_F7R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4819 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4820 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4821 #define CAN_F7R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4822 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4823 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4824 #define CAN_F7R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4825 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4826 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4827 #define CAN_F7R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4828 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4829 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4830 #define CAN_F7R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4831 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4832 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4833 #define CAN_F7R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4834 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4835 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4836 #define CAN_F7R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4837 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4838 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4839 #define CAN_F7R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4840 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4841 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4842 #define CAN_F7R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4843 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4844 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4845
AnnaBridge 161:aa5281ff4a02 4846 /******************* Bit definition for CAN_F8R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4847 #define CAN_F8R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4848 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4849 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4850 #define CAN_F8R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4851 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4852 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4853 #define CAN_F8R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4854 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4855 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4856 #define CAN_F8R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4857 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4858 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4859 #define CAN_F8R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4860 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4861 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4862 #define CAN_F8R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4863 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4864 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4865 #define CAN_F8R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4866 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4867 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4868 #define CAN_F8R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4869 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4870 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4871 #define CAN_F8R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4872 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4873 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4874 #define CAN_F8R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4875 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4876 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4877 #define CAN_F8R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4878 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4879 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4880 #define CAN_F8R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4881 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4882 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4883 #define CAN_F8R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4884 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4885 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4886 #define CAN_F8R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4887 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4888 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4889 #define CAN_F8R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4890 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4891 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4892 #define CAN_F8R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4893 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4894 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4895 #define CAN_F8R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4896 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4897 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4898 #define CAN_F8R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4899 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4900 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4901 #define CAN_F8R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 4902 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 4903 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 4904 #define CAN_F8R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 4905 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 4906 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 4907 #define CAN_F8R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 4908 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 4909 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 4910 #define CAN_F8R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 4911 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 4912 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 4913 #define CAN_F8R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 4914 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 4915 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 4916 #define CAN_F8R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 4917 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 4918 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 4919 #define CAN_F8R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 4920 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 4921 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 4922 #define CAN_F8R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 4923 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 4924 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 4925 #define CAN_F8R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 4926 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 4927 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 4928 #define CAN_F8R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 4929 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 4930 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 4931 #define CAN_F8R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 4932 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 4933 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 4934 #define CAN_F8R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 4935 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 4936 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 4937 #define CAN_F8R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 4938 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 4939 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 4940 #define CAN_F8R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 4941 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 4942 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 4943
AnnaBridge 161:aa5281ff4a02 4944 /******************* Bit definition for CAN_F9R2 register *******************/
AnnaBridge 161:aa5281ff4a02 4945 #define CAN_F9R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 4946 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 4947 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 4948 #define CAN_F9R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 4949 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 4950 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 4951 #define CAN_F9R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 4952 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 4953 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 4954 #define CAN_F9R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 4955 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 4956 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 4957 #define CAN_F9R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 4958 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 4959 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 4960 #define CAN_F9R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 4961 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 4962 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 4963 #define CAN_F9R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 4964 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 4965 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 4966 #define CAN_F9R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 4967 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 4968 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 4969 #define CAN_F9R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 4970 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 4971 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 4972 #define CAN_F9R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 4973 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 4974 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 4975 #define CAN_F9R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 4976 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 4977 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 4978 #define CAN_F9R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 4979 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 4980 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 4981 #define CAN_F9R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 4982 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 4983 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 4984 #define CAN_F9R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 4985 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 4986 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 4987 #define CAN_F9R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 4988 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 4989 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 4990 #define CAN_F9R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 4991 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 4992 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 4993 #define CAN_F9R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 4994 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 4995 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 4996 #define CAN_F9R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 4997 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 4998 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 4999 #define CAN_F9R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 5000 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 5001 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 5002 #define CAN_F9R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 5003 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 5004 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 5005 #define CAN_F9R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 5006 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 5007 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 5008 #define CAN_F9R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 5009 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 5010 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 5011 #define CAN_F9R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 5012 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 5013 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 5014 #define CAN_F9R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 5015 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 5016 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 5017 #define CAN_F9R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5018 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 5019 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 5020 #define CAN_F9R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 5021 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 5022 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 5023 #define CAN_F9R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 5024 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 5025 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 5026 #define CAN_F9R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 5027 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 5028 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 5029 #define CAN_F9R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 5030 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 5031 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 5032 #define CAN_F9R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 5033 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 5034 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 5035 #define CAN_F9R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 5036 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 5037 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 5038 #define CAN_F9R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 5039 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 5040 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 5041
AnnaBridge 161:aa5281ff4a02 5042 /******************* Bit definition for CAN_F10R2 register ******************/
AnnaBridge 161:aa5281ff4a02 5043 #define CAN_F10R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5044 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5045 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 5046 #define CAN_F10R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5047 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5048 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 5049 #define CAN_F10R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5050 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5051 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 5052 #define CAN_F10R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5053 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5054 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 5055 #define CAN_F10R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5056 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5057 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 5058 #define CAN_F10R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 5059 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5060 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 5061 #define CAN_F10R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 5062 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5063 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 5064 #define CAN_F10R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 5065 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5066 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 5067 #define CAN_F10R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5068 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 5069 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 5070 #define CAN_F10R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 5071 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 5072 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 5073 #define CAN_F10R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 5074 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 5075 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 5076 #define CAN_F10R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 5077 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 5078 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 5079 #define CAN_F10R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 5080 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 5081 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 5082 #define CAN_F10R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 5083 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 5084 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 5085 #define CAN_F10R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 5086 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 5087 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 5088 #define CAN_F10R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 5089 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 5090 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 5091 #define CAN_F10R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5092 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 5093 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 5094 #define CAN_F10R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 5095 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 5096 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 5097 #define CAN_F10R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 5098 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 5099 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 5100 #define CAN_F10R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 5101 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 5102 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 5103 #define CAN_F10R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 5104 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 5105 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 5106 #define CAN_F10R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 5107 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 5108 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 5109 #define CAN_F10R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 5110 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 5111 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 5112 #define CAN_F10R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 5113 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 5114 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 5115 #define CAN_F10R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5116 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 5117 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 5118 #define CAN_F10R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 5119 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 5120 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 5121 #define CAN_F10R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 5122 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 5123 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 5124 #define CAN_F10R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 5125 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 5126 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 5127 #define CAN_F10R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 5128 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 5129 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 5130 #define CAN_F10R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 5131 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 5132 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 5133 #define CAN_F10R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 5134 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 5135 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 5136 #define CAN_F10R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 5137 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 5138 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 5139
AnnaBridge 161:aa5281ff4a02 5140 /******************* Bit definition for CAN_F11R2 register ******************/
AnnaBridge 161:aa5281ff4a02 5141 #define CAN_F11R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5142 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5143 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 5144 #define CAN_F11R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5145 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5146 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 5147 #define CAN_F11R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5148 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5149 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 5150 #define CAN_F11R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5151 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5152 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 5153 #define CAN_F11R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5154 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5155 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 5156 #define CAN_F11R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 5157 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5158 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 5159 #define CAN_F11R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 5160 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5161 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 5162 #define CAN_F11R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 5163 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5164 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 5165 #define CAN_F11R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5166 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 5167 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 5168 #define CAN_F11R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 5169 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 5170 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 5171 #define CAN_F11R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 5172 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 5173 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 5174 #define CAN_F11R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 5175 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 5176 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 5177 #define CAN_F11R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 5178 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 5179 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 5180 #define CAN_F11R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 5181 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 5182 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 5183 #define CAN_F11R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 5184 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 5185 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 5186 #define CAN_F11R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 5187 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 5188 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 5189 #define CAN_F11R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5190 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 5191 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 5192 #define CAN_F11R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 5193 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 5194 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 5195 #define CAN_F11R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 5196 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 5197 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 5198 #define CAN_F11R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 5199 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 5200 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 5201 #define CAN_F11R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 5202 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 5203 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 5204 #define CAN_F11R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 5205 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 5206 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 5207 #define CAN_F11R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 5208 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 5209 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 5210 #define CAN_F11R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 5211 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 5212 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 5213 #define CAN_F11R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5214 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 5215 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 5216 #define CAN_F11R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 5217 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 5218 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 5219 #define CAN_F11R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 5220 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 5221 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 5222 #define CAN_F11R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 5223 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 5224 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 5225 #define CAN_F11R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 5226 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 5227 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 5228 #define CAN_F11R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 5229 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 5230 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 5231 #define CAN_F11R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 5232 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 5233 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 5234 #define CAN_F11R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 5235 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 5236 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 5237
AnnaBridge 161:aa5281ff4a02 5238 /******************* Bit definition for CAN_F12R2 register ******************/
AnnaBridge 161:aa5281ff4a02 5239 #define CAN_F12R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5240 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5241 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 5242 #define CAN_F12R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5243 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5244 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 5245 #define CAN_F12R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5246 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5247 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 5248 #define CAN_F12R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5249 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5250 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 5251 #define CAN_F12R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5252 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5253 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 5254 #define CAN_F12R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 5255 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5256 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 5257 #define CAN_F12R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 5258 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5259 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 5260 #define CAN_F12R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 5261 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5262 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 5263 #define CAN_F12R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5264 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 5265 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 5266 #define CAN_F12R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 5267 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 5268 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 5269 #define CAN_F12R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 5270 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 5271 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 5272 #define CAN_F12R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 5273 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 5274 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 5275 #define CAN_F12R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 5276 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 5277 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 5278 #define CAN_F12R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 5279 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 5280 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 5281 #define CAN_F12R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 5282 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 5283 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 5284 #define CAN_F12R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 5285 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 5286 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 5287 #define CAN_F12R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5288 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 5289 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 5290 #define CAN_F12R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 5291 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 5292 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 5293 #define CAN_F12R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 5294 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 5295 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 5296 #define CAN_F12R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 5297 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 5298 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 5299 #define CAN_F12R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 5300 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 5301 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 5302 #define CAN_F12R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 5303 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 5304 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 5305 #define CAN_F12R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 5306 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 5307 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 5308 #define CAN_F12R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 5309 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 5310 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 5311 #define CAN_F12R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5312 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 5313 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 5314 #define CAN_F12R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 5315 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 5316 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 5317 #define CAN_F12R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 5318 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 5319 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 5320 #define CAN_F12R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 5321 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 5322 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 5323 #define CAN_F12R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 5324 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 5325 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 5326 #define CAN_F12R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 5327 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 5328 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 5329 #define CAN_F12R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 5330 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 5331 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 5332 #define CAN_F12R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 5333 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 5334 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 5335
AnnaBridge 161:aa5281ff4a02 5336 /******************* Bit definition for CAN_F13R2 register ******************/
AnnaBridge 161:aa5281ff4a02 5337 #define CAN_F13R2_FB0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5338 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5339 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 161:aa5281ff4a02 5340 #define CAN_F13R2_FB1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5341 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5342 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 161:aa5281ff4a02 5343 #define CAN_F13R2_FB2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5344 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5345 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 161:aa5281ff4a02 5346 #define CAN_F13R2_FB3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5347 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5348 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 161:aa5281ff4a02 5349 #define CAN_F13R2_FB4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5350 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5351 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 161:aa5281ff4a02 5352 #define CAN_F13R2_FB5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 5353 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5354 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 161:aa5281ff4a02 5355 #define CAN_F13R2_FB6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 5356 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5357 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 161:aa5281ff4a02 5358 #define CAN_F13R2_FB7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 5359 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5360 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 161:aa5281ff4a02 5361 #define CAN_F13R2_FB8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5362 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 5363 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 161:aa5281ff4a02 5364 #define CAN_F13R2_FB9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 5365 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 5366 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 161:aa5281ff4a02 5367 #define CAN_F13R2_FB10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 5368 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 5369 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 161:aa5281ff4a02 5370 #define CAN_F13R2_FB11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 5371 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 5372 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 161:aa5281ff4a02 5373 #define CAN_F13R2_FB12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 5374 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 5375 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 161:aa5281ff4a02 5376 #define CAN_F13R2_FB13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 5377 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 5378 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 161:aa5281ff4a02 5379 #define CAN_F13R2_FB14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 5380 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 5381 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 161:aa5281ff4a02 5382 #define CAN_F13R2_FB15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 5383 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 5384 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 161:aa5281ff4a02 5385 #define CAN_F13R2_FB16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5386 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 5387 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 161:aa5281ff4a02 5388 #define CAN_F13R2_FB17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 5389 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 5390 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 161:aa5281ff4a02 5391 #define CAN_F13R2_FB18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 5392 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 5393 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 161:aa5281ff4a02 5394 #define CAN_F13R2_FB19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 5395 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 5396 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 161:aa5281ff4a02 5397 #define CAN_F13R2_FB20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 5398 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 5399 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 161:aa5281ff4a02 5400 #define CAN_F13R2_FB21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 5401 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 5402 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 161:aa5281ff4a02 5403 #define CAN_F13R2_FB22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 5404 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 5405 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 161:aa5281ff4a02 5406 #define CAN_F13R2_FB23_Pos (23U)
AnnaBridge 161:aa5281ff4a02 5407 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 5408 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 161:aa5281ff4a02 5409 #define CAN_F13R2_FB24_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5410 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 5411 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 161:aa5281ff4a02 5412 #define CAN_F13R2_FB25_Pos (25U)
AnnaBridge 161:aa5281ff4a02 5413 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 5414 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 161:aa5281ff4a02 5415 #define CAN_F13R2_FB26_Pos (26U)
AnnaBridge 161:aa5281ff4a02 5416 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 5417 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 161:aa5281ff4a02 5418 #define CAN_F13R2_FB27_Pos (27U)
AnnaBridge 161:aa5281ff4a02 5419 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 5420 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 161:aa5281ff4a02 5421 #define CAN_F13R2_FB28_Pos (28U)
AnnaBridge 161:aa5281ff4a02 5422 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 5423 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 161:aa5281ff4a02 5424 #define CAN_F13R2_FB29_Pos (29U)
AnnaBridge 161:aa5281ff4a02 5425 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 5426 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 161:aa5281ff4a02 5427 #define CAN_F13R2_FB30_Pos (30U)
AnnaBridge 161:aa5281ff4a02 5428 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 5429 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 161:aa5281ff4a02 5430 #define CAN_F13R2_FB31_Pos (31U)
AnnaBridge 161:aa5281ff4a02 5431 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 5432 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 161:aa5281ff4a02 5433
AnnaBridge 161:aa5281ff4a02 5434 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 5435 /* */
AnnaBridge 161:aa5281ff4a02 5436 /* CRC calculation unit */
AnnaBridge 161:aa5281ff4a02 5437 /* */
AnnaBridge 161:aa5281ff4a02 5438 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 5439 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 161:aa5281ff4a02 5440 #define CRC_DR_DR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5441 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 5442 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 161:aa5281ff4a02 5443
AnnaBridge 161:aa5281ff4a02 5444
AnnaBridge 161:aa5281ff4a02 5445 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 161:aa5281ff4a02 5446 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5447 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 5448 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
AnnaBridge 161:aa5281ff4a02 5449
AnnaBridge 161:aa5281ff4a02 5450
AnnaBridge 161:aa5281ff4a02 5451 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 161:aa5281ff4a02 5452 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5453 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5454 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
AnnaBridge 161:aa5281ff4a02 5455
AnnaBridge 161:aa5281ff4a02 5456 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 5457 /* */
AnnaBridge 161:aa5281ff4a02 5458 /* Digital to Analog Converter */
AnnaBridge 161:aa5281ff4a02 5459 /* */
AnnaBridge 161:aa5281ff4a02 5460 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 5461 /*
AnnaBridge 161:aa5281ff4a02 5462 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 161:aa5281ff4a02 5463 */
AnnaBridge 161:aa5281ff4a02 5464 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
AnnaBridge 161:aa5281ff4a02 5465 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 161:aa5281ff4a02 5466 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5467 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5468 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 161:aa5281ff4a02 5469 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5470 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5471 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
AnnaBridge 161:aa5281ff4a02 5472 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5473 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5474 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 161:aa5281ff4a02 5475
AnnaBridge 161:aa5281ff4a02 5476 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5477 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 161:aa5281ff4a02 5478 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 161:aa5281ff4a02 5479 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5480 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5481 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5482
AnnaBridge 161:aa5281ff4a02 5483 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 161:aa5281ff4a02 5484 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 5485 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 161:aa5281ff4a02 5486 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5487 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5488
AnnaBridge 161:aa5281ff4a02 5489 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5490 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 5491 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 161:aa5281ff4a02 5492 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 5493 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 5494 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 5495 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 5496
AnnaBridge 161:aa5281ff4a02 5497 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 161:aa5281ff4a02 5498 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 5499 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 161:aa5281ff4a02 5500 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 161:aa5281ff4a02 5501 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 5502 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
AnnaBridge 161:aa5281ff4a02 5503 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5504 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 5505 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 161:aa5281ff4a02 5506 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 161:aa5281ff4a02 5507 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 5508 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
AnnaBridge 161:aa5281ff4a02 5509 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 161:aa5281ff4a02 5510 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 5511 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 161:aa5281ff4a02 5512
AnnaBridge 161:aa5281ff4a02 5513 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 161:aa5281ff4a02 5514 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 161:aa5281ff4a02 5515 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 161:aa5281ff4a02 5516 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 5517 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 5518 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 5519
AnnaBridge 161:aa5281ff4a02 5520 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 161:aa5281ff4a02 5521 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 161:aa5281ff4a02 5522 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 161:aa5281ff4a02 5523 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 5524 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 5525
AnnaBridge 161:aa5281ff4a02 5526 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5527 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 5528 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 161:aa5281ff4a02 5529 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 5530 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 5531 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 5532 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 5533
AnnaBridge 161:aa5281ff4a02 5534 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 161:aa5281ff4a02 5535 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 5536 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
AnnaBridge 161:aa5281ff4a02 5537 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 161:aa5281ff4a02 5538 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 5539 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
AnnaBridge 161:aa5281ff4a02 5540
AnnaBridge 161:aa5281ff4a02 5541 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 161:aa5281ff4a02 5542 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5543 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5544 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 161:aa5281ff4a02 5545 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5546 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5547 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
AnnaBridge 161:aa5281ff4a02 5548
AnnaBridge 161:aa5281ff4a02 5549 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 161:aa5281ff4a02 5550 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5551 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 5552 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 161:aa5281ff4a02 5553
AnnaBridge 161:aa5281ff4a02 5554 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 161:aa5281ff4a02 5555 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5556 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 161:aa5281ff4a02 5557 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 161:aa5281ff4a02 5558
AnnaBridge 161:aa5281ff4a02 5559 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 161:aa5281ff4a02 5560 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5561 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 5562 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 161:aa5281ff4a02 5563
AnnaBridge 161:aa5281ff4a02 5564 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 161:aa5281ff4a02 5565 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5566 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 5567 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 161:aa5281ff4a02 5568
AnnaBridge 161:aa5281ff4a02 5569 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 161:aa5281ff4a02 5570 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5571 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 161:aa5281ff4a02 5572 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 161:aa5281ff4a02 5573
AnnaBridge 161:aa5281ff4a02 5574 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 161:aa5281ff4a02 5575 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5576 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 5577 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 161:aa5281ff4a02 5578
AnnaBridge 161:aa5281ff4a02 5579 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 161:aa5281ff4a02 5580 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5581 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 5582 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 161:aa5281ff4a02 5583 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5584 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 161:aa5281ff4a02 5585 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 161:aa5281ff4a02 5586
AnnaBridge 161:aa5281ff4a02 5587 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 161:aa5281ff4a02 5588 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5589 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 161:aa5281ff4a02 5590 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 161:aa5281ff4a02 5591 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 161:aa5281ff4a02 5592 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 161:aa5281ff4a02 5593 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 161:aa5281ff4a02 5594
AnnaBridge 161:aa5281ff4a02 5595 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 161:aa5281ff4a02 5596 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5597 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 5598 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 161:aa5281ff4a02 5599 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5600 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 5601 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 161:aa5281ff4a02 5602
AnnaBridge 161:aa5281ff4a02 5603 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 161:aa5281ff4a02 5604 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5605 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 5606 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
AnnaBridge 161:aa5281ff4a02 5607
AnnaBridge 161:aa5281ff4a02 5608 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 161:aa5281ff4a02 5609 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5610 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 5611 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
AnnaBridge 161:aa5281ff4a02 5612
AnnaBridge 161:aa5281ff4a02 5613 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 161:aa5281ff4a02 5614 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 161:aa5281ff4a02 5615 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 5616 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 161:aa5281ff4a02 5617 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 161:aa5281ff4a02 5618 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 5619 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
AnnaBridge 161:aa5281ff4a02 5620
AnnaBridge 161:aa5281ff4a02 5621 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 5622 /* */
AnnaBridge 161:aa5281ff4a02 5623 /* DCMI */
AnnaBridge 161:aa5281ff4a02 5624 /* */
AnnaBridge 161:aa5281ff4a02 5625 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 5626 /******************** Bits definition for DCMI_CR register ******************/
AnnaBridge 161:aa5281ff4a02 5627 #define DCMI_CR_CAPTURE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5628 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5629 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
AnnaBridge 161:aa5281ff4a02 5630 #define DCMI_CR_CM_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5631 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5632 #define DCMI_CR_CM DCMI_CR_CM_Msk
AnnaBridge 161:aa5281ff4a02 5633 #define DCMI_CR_CROP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5634 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5635 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
AnnaBridge 161:aa5281ff4a02 5636 #define DCMI_CR_JPEG_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5637 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5638 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
AnnaBridge 161:aa5281ff4a02 5639 #define DCMI_CR_ESS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5640 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5641 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
AnnaBridge 161:aa5281ff4a02 5642 #define DCMI_CR_PCKPOL_Pos (5U)
AnnaBridge 161:aa5281ff4a02 5643 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5644 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
AnnaBridge 161:aa5281ff4a02 5645 #define DCMI_CR_HSPOL_Pos (6U)
AnnaBridge 161:aa5281ff4a02 5646 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5647 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
AnnaBridge 161:aa5281ff4a02 5648 #define DCMI_CR_VSPOL_Pos (7U)
AnnaBridge 161:aa5281ff4a02 5649 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5650 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
AnnaBridge 161:aa5281ff4a02 5651 #define DCMI_CR_FCRC_0 0x00000100U
AnnaBridge 161:aa5281ff4a02 5652 #define DCMI_CR_FCRC_1 0x00000200U
AnnaBridge 161:aa5281ff4a02 5653 #define DCMI_CR_EDM_0 0x00000400U
AnnaBridge 161:aa5281ff4a02 5654 #define DCMI_CR_EDM_1 0x00000800U
AnnaBridge 161:aa5281ff4a02 5655 #define DCMI_CR_CRE_Pos (12U)
AnnaBridge 161:aa5281ff4a02 5656 #define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 5657 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
AnnaBridge 161:aa5281ff4a02 5658 #define DCMI_CR_ENABLE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 5659 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 5660 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
AnnaBridge 161:aa5281ff4a02 5661
AnnaBridge 161:aa5281ff4a02 5662 /******************** Bits definition for DCMI_SR register ******************/
AnnaBridge 161:aa5281ff4a02 5663 #define DCMI_SR_HSYNC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5664 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5665 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
AnnaBridge 161:aa5281ff4a02 5666 #define DCMI_SR_VSYNC_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5667 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5668 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
AnnaBridge 161:aa5281ff4a02 5669 #define DCMI_SR_FNE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5670 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5671 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
AnnaBridge 161:aa5281ff4a02 5672
AnnaBridge 161:aa5281ff4a02 5673 /******************** Bits definition for DCMI_RIS register *****************/
AnnaBridge 161:aa5281ff4a02 5674 #define DCMI_RIS_FRAME_RIS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5675 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5676 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
AnnaBridge 161:aa5281ff4a02 5677 #define DCMI_RIS_OVR_RIS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5678 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5679 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
AnnaBridge 161:aa5281ff4a02 5680 #define DCMI_RIS_ERR_RIS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5681 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5682 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
AnnaBridge 161:aa5281ff4a02 5683 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5684 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5685 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
AnnaBridge 161:aa5281ff4a02 5686 #define DCMI_RIS_LINE_RIS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5687 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5688 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
AnnaBridge 161:aa5281ff4a02 5689 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 5690 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
AnnaBridge 161:aa5281ff4a02 5691 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
AnnaBridge 161:aa5281ff4a02 5692 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
AnnaBridge 161:aa5281ff4a02 5693 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
AnnaBridge 161:aa5281ff4a02 5694 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
AnnaBridge 161:aa5281ff4a02 5695 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
AnnaBridge 161:aa5281ff4a02 5696
AnnaBridge 161:aa5281ff4a02 5697 /******************** Bits definition for DCMI_IER register *****************/
AnnaBridge 161:aa5281ff4a02 5698 #define DCMI_IER_FRAME_IE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5699 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5700 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
AnnaBridge 161:aa5281ff4a02 5701 #define DCMI_IER_OVR_IE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5702 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5703 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
AnnaBridge 161:aa5281ff4a02 5704 #define DCMI_IER_ERR_IE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5705 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5706 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
AnnaBridge 161:aa5281ff4a02 5707 #define DCMI_IER_VSYNC_IE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5708 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5709 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
AnnaBridge 161:aa5281ff4a02 5710 #define DCMI_IER_LINE_IE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5711 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5712 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
AnnaBridge 161:aa5281ff4a02 5713 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 5714 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
AnnaBridge 161:aa5281ff4a02 5715
AnnaBridge 161:aa5281ff4a02 5716 /******************** Bits definition for DCMI_MIS register *****************/
AnnaBridge 161:aa5281ff4a02 5717 #define DCMI_MIS_FRAME_MIS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5718 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5719 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
AnnaBridge 161:aa5281ff4a02 5720 #define DCMI_MIS_OVR_MIS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5721 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5722 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
AnnaBridge 161:aa5281ff4a02 5723 #define DCMI_MIS_ERR_MIS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5724 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5725 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
AnnaBridge 161:aa5281ff4a02 5726 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5727 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5728 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
AnnaBridge 161:aa5281ff4a02 5729 #define DCMI_MIS_LINE_MIS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5730 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5731 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
AnnaBridge 161:aa5281ff4a02 5732
AnnaBridge 161:aa5281ff4a02 5733 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 5734 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
AnnaBridge 161:aa5281ff4a02 5735 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
AnnaBridge 161:aa5281ff4a02 5736 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
AnnaBridge 161:aa5281ff4a02 5737 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
AnnaBridge 161:aa5281ff4a02 5738 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
AnnaBridge 161:aa5281ff4a02 5739
AnnaBridge 161:aa5281ff4a02 5740 /******************** Bits definition for DCMI_ICR register *****************/
AnnaBridge 161:aa5281ff4a02 5741 #define DCMI_ICR_FRAME_ISC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5742 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5743 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
AnnaBridge 161:aa5281ff4a02 5744 #define DCMI_ICR_OVR_ISC_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5745 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5746 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
AnnaBridge 161:aa5281ff4a02 5747 #define DCMI_ICR_ERR_ISC_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5748 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5749 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
AnnaBridge 161:aa5281ff4a02 5750 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5751 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5752 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
AnnaBridge 161:aa5281ff4a02 5753 #define DCMI_ICR_LINE_ISC_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5754 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5755 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
AnnaBridge 161:aa5281ff4a02 5756
AnnaBridge 161:aa5281ff4a02 5757 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 5758 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
AnnaBridge 161:aa5281ff4a02 5759
AnnaBridge 161:aa5281ff4a02 5760 /******************** Bits definition for DCMI_ESCR register ******************/
AnnaBridge 161:aa5281ff4a02 5761 #define DCMI_ESCR_FSC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5762 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 5763 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
AnnaBridge 161:aa5281ff4a02 5764 #define DCMI_ESCR_LSC_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5765 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 5766 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
AnnaBridge 161:aa5281ff4a02 5767 #define DCMI_ESCR_LEC_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5768 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 5769 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
AnnaBridge 161:aa5281ff4a02 5770 #define DCMI_ESCR_FEC_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5771 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 5772 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
AnnaBridge 161:aa5281ff4a02 5773
AnnaBridge 161:aa5281ff4a02 5774 /******************** Bits definition for DCMI_ESUR register ******************/
AnnaBridge 161:aa5281ff4a02 5775 #define DCMI_ESUR_FSU_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5776 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 5777 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
AnnaBridge 161:aa5281ff4a02 5778 #define DCMI_ESUR_LSU_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5779 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 5780 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
AnnaBridge 161:aa5281ff4a02 5781 #define DCMI_ESUR_LEU_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5782 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 5783 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
AnnaBridge 161:aa5281ff4a02 5784 #define DCMI_ESUR_FEU_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5785 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 5786 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
AnnaBridge 161:aa5281ff4a02 5787
AnnaBridge 161:aa5281ff4a02 5788 /******************** Bits definition for DCMI_CWSTRT register ******************/
AnnaBridge 161:aa5281ff4a02 5789 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5790 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 161:aa5281ff4a02 5791 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
AnnaBridge 161:aa5281ff4a02 5792 #define DCMI_CWSTRT_VST_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5793 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
AnnaBridge 161:aa5281ff4a02 5794 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
AnnaBridge 161:aa5281ff4a02 5795
AnnaBridge 161:aa5281ff4a02 5796 /******************** Bits definition for DCMI_CWSIZE register ******************/
AnnaBridge 161:aa5281ff4a02 5797 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5798 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 161:aa5281ff4a02 5799 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
AnnaBridge 161:aa5281ff4a02 5800 #define DCMI_CWSIZE_VLINE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5801 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
AnnaBridge 161:aa5281ff4a02 5802 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
AnnaBridge 161:aa5281ff4a02 5803
AnnaBridge 161:aa5281ff4a02 5804 /******************** Bits definition for DCMI_DR register *********************/
AnnaBridge 161:aa5281ff4a02 5805 #define DCMI_DR_BYTE0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5806 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 5807 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
AnnaBridge 161:aa5281ff4a02 5808 #define DCMI_DR_BYTE1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5809 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 5810 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
AnnaBridge 161:aa5281ff4a02 5811 #define DCMI_DR_BYTE2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5812 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 5813 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
AnnaBridge 161:aa5281ff4a02 5814 #define DCMI_DR_BYTE3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5815 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 5816 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
AnnaBridge 161:aa5281ff4a02 5817
AnnaBridge 161:aa5281ff4a02 5818 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 5819 /* */
AnnaBridge 161:aa5281ff4a02 5820 /* DMA Controller */
AnnaBridge 161:aa5281ff4a02 5821 /* */
AnnaBridge 161:aa5281ff4a02 5822 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 5823 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 161:aa5281ff4a02 5824 #define DMA_SxCR_CHSEL_Pos (25U)
AnnaBridge 161:aa5281ff4a02 5825 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
AnnaBridge 161:aa5281ff4a02 5826 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
AnnaBridge 161:aa5281ff4a02 5827 #define DMA_SxCR_CHSEL_0 0x02000000U
AnnaBridge 161:aa5281ff4a02 5828 #define DMA_SxCR_CHSEL_1 0x04000000U
AnnaBridge 161:aa5281ff4a02 5829 #define DMA_SxCR_CHSEL_2 0x08000000U
AnnaBridge 161:aa5281ff4a02 5830 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 161:aa5281ff4a02 5831 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 161:aa5281ff4a02 5832 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
AnnaBridge 161:aa5281ff4a02 5833 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 5834 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 5835 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 161:aa5281ff4a02 5836 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 161:aa5281ff4a02 5837 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
AnnaBridge 161:aa5281ff4a02 5838 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 5839 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 5840 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 161:aa5281ff4a02 5841 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 5842 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
AnnaBridge 161:aa5281ff4a02 5843 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 161:aa5281ff4a02 5844 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 5845 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
AnnaBridge 161:aa5281ff4a02 5846 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5847 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 161:aa5281ff4a02 5848 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
AnnaBridge 161:aa5281ff4a02 5849 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 5850 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 5851 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 161:aa5281ff4a02 5852 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 5853 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
AnnaBridge 161:aa5281ff4a02 5854 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 5855 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 161:aa5281ff4a02 5856 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
AnnaBridge 161:aa5281ff4a02 5857 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 5858 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 5859 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 5860 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 161:aa5281ff4a02 5861 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
AnnaBridge 161:aa5281ff4a02 5862 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 5863 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 5864 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 161:aa5281ff4a02 5865 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 5866 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
AnnaBridge 161:aa5281ff4a02 5867 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 161:aa5281ff4a02 5868 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 5869 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
AnnaBridge 161:aa5281ff4a02 5870 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5871 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 5872 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
AnnaBridge 161:aa5281ff4a02 5873 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 161:aa5281ff4a02 5874 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 5875 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
AnnaBridge 161:aa5281ff4a02 5876 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5877 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5878 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 161:aa5281ff4a02 5879 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5880 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
AnnaBridge 161:aa5281ff4a02 5881 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5882 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5883 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
AnnaBridge 161:aa5281ff4a02 5884 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5885 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5886 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
AnnaBridge 161:aa5281ff4a02 5887 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5888 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5889 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
AnnaBridge 161:aa5281ff4a02 5890 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 5891 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5892 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
AnnaBridge 161:aa5281ff4a02 5893 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5894 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5895 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
AnnaBridge 161:aa5281ff4a02 5896
AnnaBridge 161:aa5281ff4a02 5897 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 5898 #define DMA_SxCR_ACK_Pos (20U)
AnnaBridge 161:aa5281ff4a02 5899 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 5900 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
AnnaBridge 161:aa5281ff4a02 5901
AnnaBridge 161:aa5281ff4a02 5902 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 161:aa5281ff4a02 5903 #define DMA_SxNDT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5904 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 5905 #define DMA_SxNDT DMA_SxNDT_Msk
AnnaBridge 161:aa5281ff4a02 5906 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5907 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5908 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5909 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5910 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5911 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5912 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5913 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5914 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 5915 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 5916 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 5917 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 5918 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 5919 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 5920 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 5921 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 5922
AnnaBridge 161:aa5281ff4a02 5923 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 161:aa5281ff4a02 5924 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 5925 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 5926 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
AnnaBridge 161:aa5281ff4a02 5927 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5928 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 161:aa5281ff4a02 5929 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
AnnaBridge 161:aa5281ff4a02 5930 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5931 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5932 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5933 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5934 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5935 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
AnnaBridge 161:aa5281ff4a02 5936 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 161:aa5281ff4a02 5937 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 5938 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
AnnaBridge 161:aa5281ff4a02 5939 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 5940 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 5941
AnnaBridge 161:aa5281ff4a02 5942 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 161:aa5281ff4a02 5943 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 161:aa5281ff4a02 5944 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 5945 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
AnnaBridge 161:aa5281ff4a02 5946 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 161:aa5281ff4a02 5947 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 5948 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
AnnaBridge 161:aa5281ff4a02 5949 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 161:aa5281ff4a02 5950 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 5951 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
AnnaBridge 161:aa5281ff4a02 5952 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 5953 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 5954 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
AnnaBridge 161:aa5281ff4a02 5955 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 161:aa5281ff4a02 5956 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 5957 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
AnnaBridge 161:aa5281ff4a02 5958 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 161:aa5281ff4a02 5959 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 5960 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
AnnaBridge 161:aa5281ff4a02 5961 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 161:aa5281ff4a02 5962 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 5963 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
AnnaBridge 161:aa5281ff4a02 5964 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 161:aa5281ff4a02 5965 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 5966 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
AnnaBridge 161:aa5281ff4a02 5967 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 161:aa5281ff4a02 5968 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 5969 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
AnnaBridge 161:aa5281ff4a02 5970 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 5971 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 5972 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
AnnaBridge 161:aa5281ff4a02 5973 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 161:aa5281ff4a02 5974 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 5975 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
AnnaBridge 161:aa5281ff4a02 5976 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 161:aa5281ff4a02 5977 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 5978 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
AnnaBridge 161:aa5281ff4a02 5979 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 161:aa5281ff4a02 5980 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 5981 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
AnnaBridge 161:aa5281ff4a02 5982 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 5983 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 5984 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
AnnaBridge 161:aa5281ff4a02 5985 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 161:aa5281ff4a02 5986 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 5987 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
AnnaBridge 161:aa5281ff4a02 5988 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 161:aa5281ff4a02 5989 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 5990 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
AnnaBridge 161:aa5281ff4a02 5991 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 161:aa5281ff4a02 5992 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 5993 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
AnnaBridge 161:aa5281ff4a02 5994 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 161:aa5281ff4a02 5995 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 5996 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
AnnaBridge 161:aa5281ff4a02 5997 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 161:aa5281ff4a02 5998 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 5999 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
AnnaBridge 161:aa5281ff4a02 6000 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6001 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6002 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
AnnaBridge 161:aa5281ff4a02 6003
AnnaBridge 161:aa5281ff4a02 6004 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 161:aa5281ff4a02 6005 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 161:aa5281ff4a02 6006 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 6007 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
AnnaBridge 161:aa5281ff4a02 6008 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 161:aa5281ff4a02 6009 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 6010 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
AnnaBridge 161:aa5281ff4a02 6011 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 161:aa5281ff4a02 6012 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 6013 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
AnnaBridge 161:aa5281ff4a02 6014 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 161:aa5281ff4a02 6015 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 6016 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
AnnaBridge 161:aa5281ff4a02 6017 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6018 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6019 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
AnnaBridge 161:aa5281ff4a02 6020 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6021 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6022 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
AnnaBridge 161:aa5281ff4a02 6023 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6024 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6025 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
AnnaBridge 161:aa5281ff4a02 6026 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6027 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6028 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
AnnaBridge 161:aa5281ff4a02 6029 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6030 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6031 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
AnnaBridge 161:aa5281ff4a02 6032 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6033 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6034 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
AnnaBridge 161:aa5281ff4a02 6035 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6036 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6037 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
AnnaBridge 161:aa5281ff4a02 6038 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6039 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6040 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
AnnaBridge 161:aa5281ff4a02 6041 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6042 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6043 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
AnnaBridge 161:aa5281ff4a02 6044 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6045 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6046 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
AnnaBridge 161:aa5281ff4a02 6047 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6048 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6049 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
AnnaBridge 161:aa5281ff4a02 6050 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6051 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6052 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
AnnaBridge 161:aa5281ff4a02 6053 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6054 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6055 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
AnnaBridge 161:aa5281ff4a02 6056 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6057 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6058 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
AnnaBridge 161:aa5281ff4a02 6059 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6060 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6061 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
AnnaBridge 161:aa5281ff4a02 6062 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6063 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6064 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
AnnaBridge 161:aa5281ff4a02 6065
AnnaBridge 161:aa5281ff4a02 6066 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 161:aa5281ff4a02 6067 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 161:aa5281ff4a02 6068 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 6069 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
AnnaBridge 161:aa5281ff4a02 6070 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 161:aa5281ff4a02 6071 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 6072 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
AnnaBridge 161:aa5281ff4a02 6073 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 161:aa5281ff4a02 6074 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 6075 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
AnnaBridge 161:aa5281ff4a02 6076 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 6077 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 6078 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
AnnaBridge 161:aa5281ff4a02 6079 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6080 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6081 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
AnnaBridge 161:aa5281ff4a02 6082 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6083 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6084 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
AnnaBridge 161:aa5281ff4a02 6085 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6086 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6087 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
AnnaBridge 161:aa5281ff4a02 6088 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6089 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6090 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
AnnaBridge 161:aa5281ff4a02 6091 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6092 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6093 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
AnnaBridge 161:aa5281ff4a02 6094 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6095 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6096 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
AnnaBridge 161:aa5281ff4a02 6097 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6098 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6099 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
AnnaBridge 161:aa5281ff4a02 6100 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6101 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6102 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
AnnaBridge 161:aa5281ff4a02 6103 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6104 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6105 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
AnnaBridge 161:aa5281ff4a02 6106 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6107 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6108 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
AnnaBridge 161:aa5281ff4a02 6109 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6110 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6111 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
AnnaBridge 161:aa5281ff4a02 6112 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6113 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6114 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
AnnaBridge 161:aa5281ff4a02 6115 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6116 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6117 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
AnnaBridge 161:aa5281ff4a02 6118 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6119 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6120 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
AnnaBridge 161:aa5281ff4a02 6121 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6122 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6123 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
AnnaBridge 161:aa5281ff4a02 6124 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6125 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6126 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
AnnaBridge 161:aa5281ff4a02 6127
AnnaBridge 161:aa5281ff4a02 6128 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 161:aa5281ff4a02 6129 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 161:aa5281ff4a02 6130 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 6131 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
AnnaBridge 161:aa5281ff4a02 6132 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 161:aa5281ff4a02 6133 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 6134 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
AnnaBridge 161:aa5281ff4a02 6135 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 161:aa5281ff4a02 6136 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 6137 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
AnnaBridge 161:aa5281ff4a02 6138 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 161:aa5281ff4a02 6139 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 6140 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
AnnaBridge 161:aa5281ff4a02 6141 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6142 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6143 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
AnnaBridge 161:aa5281ff4a02 6144 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6145 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6146 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
AnnaBridge 161:aa5281ff4a02 6147 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6148 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6149 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
AnnaBridge 161:aa5281ff4a02 6150 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6151 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6152 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
AnnaBridge 161:aa5281ff4a02 6153 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6154 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6155 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
AnnaBridge 161:aa5281ff4a02 6156 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6157 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6158 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
AnnaBridge 161:aa5281ff4a02 6159 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6160 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6161 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
AnnaBridge 161:aa5281ff4a02 6162 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6163 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6164 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
AnnaBridge 161:aa5281ff4a02 6165 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6166 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6167 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
AnnaBridge 161:aa5281ff4a02 6168 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6169 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6170 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
AnnaBridge 161:aa5281ff4a02 6171 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6172 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6173 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
AnnaBridge 161:aa5281ff4a02 6174 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6175 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6176 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
AnnaBridge 161:aa5281ff4a02 6177 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6178 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6179 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
AnnaBridge 161:aa5281ff4a02 6180 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6181 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6182 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
AnnaBridge 161:aa5281ff4a02 6183 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6184 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6185 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
AnnaBridge 161:aa5281ff4a02 6186 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6187 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6188 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
AnnaBridge 161:aa5281ff4a02 6189
AnnaBridge 161:aa5281ff4a02 6190 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 161:aa5281ff4a02 6191 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6192 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 6193 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 161:aa5281ff4a02 6194
AnnaBridge 161:aa5281ff4a02 6195 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 161:aa5281ff4a02 6196 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6197 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 6198 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
AnnaBridge 161:aa5281ff4a02 6199
AnnaBridge 161:aa5281ff4a02 6200 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 161:aa5281ff4a02 6201 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6202 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 6203 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
AnnaBridge 161:aa5281ff4a02 6204
AnnaBridge 161:aa5281ff4a02 6205
AnnaBridge 161:aa5281ff4a02 6206 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 6207 /* */
AnnaBridge 161:aa5281ff4a02 6208 /* External Interrupt/Event Controller */
AnnaBridge 161:aa5281ff4a02 6209 /* */
AnnaBridge 161:aa5281ff4a02 6210 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 6211 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 161:aa5281ff4a02 6212 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6213 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6214 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 161:aa5281ff4a02 6215 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6216 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6217 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 161:aa5281ff4a02 6218 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6219 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6220 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 161:aa5281ff4a02 6221 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6222 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6223 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 161:aa5281ff4a02 6224 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6225 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6226 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 161:aa5281ff4a02 6227 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6228 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6229 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 161:aa5281ff4a02 6230 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6231 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6232 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 161:aa5281ff4a02 6233 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 6234 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6235 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 161:aa5281ff4a02 6236 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6237 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6238 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 161:aa5281ff4a02 6239 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6240 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6241 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 161:aa5281ff4a02 6242 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6243 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6244 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 161:aa5281ff4a02 6245 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6246 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6247 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 161:aa5281ff4a02 6248 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6249 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6250 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 161:aa5281ff4a02 6251 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 6252 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6253 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 161:aa5281ff4a02 6254 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 6255 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6256 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 161:aa5281ff4a02 6257 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 6258 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6259 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 161:aa5281ff4a02 6260 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6261 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6262 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 161:aa5281ff4a02 6263 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 6264 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6265 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 161:aa5281ff4a02 6266 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6267 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6268 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 161:aa5281ff4a02 6269 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6270 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6271 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 161:aa5281ff4a02 6272 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6273 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6274 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 161:aa5281ff4a02 6275 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6276 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6277 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 161:aa5281ff4a02 6278 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6279 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6280 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 161:aa5281ff4a02 6281
AnnaBridge 161:aa5281ff4a02 6282 /* Reference Defines */
AnnaBridge 161:aa5281ff4a02 6283 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 161:aa5281ff4a02 6284 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 161:aa5281ff4a02 6285 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 161:aa5281ff4a02 6286 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 161:aa5281ff4a02 6287 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 161:aa5281ff4a02 6288 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 161:aa5281ff4a02 6289 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 161:aa5281ff4a02 6290 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 161:aa5281ff4a02 6291 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 161:aa5281ff4a02 6292 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 161:aa5281ff4a02 6293 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 161:aa5281ff4a02 6294 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 161:aa5281ff4a02 6295 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 161:aa5281ff4a02 6296 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 161:aa5281ff4a02 6297 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 161:aa5281ff4a02 6298 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 161:aa5281ff4a02 6299 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 161:aa5281ff4a02 6300 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 161:aa5281ff4a02 6301 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 161:aa5281ff4a02 6302 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 161:aa5281ff4a02 6303 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 161:aa5281ff4a02 6304 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 161:aa5281ff4a02 6305 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 161:aa5281ff4a02 6306 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6307 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
AnnaBridge 161:aa5281ff4a02 6308 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 161:aa5281ff4a02 6309
AnnaBridge 161:aa5281ff4a02 6310 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 161:aa5281ff4a02 6311 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6312 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6313 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 161:aa5281ff4a02 6314 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6315 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6316 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 161:aa5281ff4a02 6317 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6318 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6319 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 161:aa5281ff4a02 6320 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6321 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6322 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 161:aa5281ff4a02 6323 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6324 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6325 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 161:aa5281ff4a02 6326 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6327 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6328 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 161:aa5281ff4a02 6329 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6330 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6331 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 161:aa5281ff4a02 6332 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 6333 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6334 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 161:aa5281ff4a02 6335 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6336 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6337 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 161:aa5281ff4a02 6338 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6339 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6340 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 161:aa5281ff4a02 6341 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6342 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6343 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 161:aa5281ff4a02 6344 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6345 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6346 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 161:aa5281ff4a02 6347 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6348 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6349 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 161:aa5281ff4a02 6350 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 6351 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6352 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 161:aa5281ff4a02 6353 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 6354 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6355 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 161:aa5281ff4a02 6356 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 6357 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6358 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 161:aa5281ff4a02 6359 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6360 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6361 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 161:aa5281ff4a02 6362 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 6363 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6364 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 161:aa5281ff4a02 6365 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6366 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6367 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 161:aa5281ff4a02 6368 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6369 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6370 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 161:aa5281ff4a02 6371 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6372 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6373 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 161:aa5281ff4a02 6374 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6375 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6376 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 161:aa5281ff4a02 6377 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6378 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6379 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 161:aa5281ff4a02 6380
AnnaBridge 161:aa5281ff4a02 6381 /* Reference Defines */
AnnaBridge 161:aa5281ff4a02 6382 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 161:aa5281ff4a02 6383 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 161:aa5281ff4a02 6384 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 161:aa5281ff4a02 6385 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 161:aa5281ff4a02 6386 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 161:aa5281ff4a02 6387 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 161:aa5281ff4a02 6388 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 161:aa5281ff4a02 6389 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 161:aa5281ff4a02 6390 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 161:aa5281ff4a02 6391 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 161:aa5281ff4a02 6392 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 161:aa5281ff4a02 6393 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 161:aa5281ff4a02 6394 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 161:aa5281ff4a02 6395 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 161:aa5281ff4a02 6396 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 161:aa5281ff4a02 6397 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 161:aa5281ff4a02 6398 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 161:aa5281ff4a02 6399 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 161:aa5281ff4a02 6400 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 161:aa5281ff4a02 6401 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 161:aa5281ff4a02 6402 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 161:aa5281ff4a02 6403 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 161:aa5281ff4a02 6404 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 161:aa5281ff4a02 6405
AnnaBridge 161:aa5281ff4a02 6406 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 161:aa5281ff4a02 6407 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6408 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6409 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 161:aa5281ff4a02 6410 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6411 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6412 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 161:aa5281ff4a02 6413 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6414 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6415 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 161:aa5281ff4a02 6416 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6417 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6418 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 161:aa5281ff4a02 6419 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6420 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6421 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 161:aa5281ff4a02 6422 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6423 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6424 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 161:aa5281ff4a02 6425 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6426 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6427 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 161:aa5281ff4a02 6428 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 6429 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6430 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 161:aa5281ff4a02 6431 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6432 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6433 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 161:aa5281ff4a02 6434 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6435 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6436 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 161:aa5281ff4a02 6437 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6438 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6439 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 161:aa5281ff4a02 6440 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6441 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6442 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 161:aa5281ff4a02 6443 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6444 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6445 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 161:aa5281ff4a02 6446 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 6447 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6448 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 161:aa5281ff4a02 6449 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 6450 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6451 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 161:aa5281ff4a02 6452 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 6453 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6454 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 161:aa5281ff4a02 6455 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6456 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6457 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 161:aa5281ff4a02 6458 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 6459 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6460 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 161:aa5281ff4a02 6461 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6462 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6463 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 161:aa5281ff4a02 6464 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6465 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6466 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 161:aa5281ff4a02 6467 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6468 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6469 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 161:aa5281ff4a02 6470 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6471 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6472 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 161:aa5281ff4a02 6473 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6474 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6475 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 161:aa5281ff4a02 6476
AnnaBridge 161:aa5281ff4a02 6477 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 161:aa5281ff4a02 6478 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6479 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6480 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 161:aa5281ff4a02 6481 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6482 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6483 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 161:aa5281ff4a02 6484 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6485 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6486 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 161:aa5281ff4a02 6487 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6488 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6489 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 161:aa5281ff4a02 6490 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6491 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6492 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 161:aa5281ff4a02 6493 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6494 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6495 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 161:aa5281ff4a02 6496 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6497 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6498 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 161:aa5281ff4a02 6499 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 6500 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6501 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 161:aa5281ff4a02 6502 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6503 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6504 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 161:aa5281ff4a02 6505 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6506 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6507 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 161:aa5281ff4a02 6508 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6509 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6510 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 161:aa5281ff4a02 6511 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6512 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6513 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 161:aa5281ff4a02 6514 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6515 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6516 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 161:aa5281ff4a02 6517 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 6518 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6519 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 161:aa5281ff4a02 6520 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 6521 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6522 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 161:aa5281ff4a02 6523 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 6524 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6525 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 161:aa5281ff4a02 6526 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6527 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6528 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 161:aa5281ff4a02 6529 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 6530 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6531 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 161:aa5281ff4a02 6532 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6533 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6534 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 161:aa5281ff4a02 6535 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6536 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6537 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 161:aa5281ff4a02 6538 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6539 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6540 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 161:aa5281ff4a02 6541 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6542 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6543 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 161:aa5281ff4a02 6544 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6545 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6546 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 161:aa5281ff4a02 6547
AnnaBridge 161:aa5281ff4a02 6548 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 161:aa5281ff4a02 6549 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6550 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6551 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 161:aa5281ff4a02 6552 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6553 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6554 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 161:aa5281ff4a02 6555 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6556 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6557 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 161:aa5281ff4a02 6558 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6559 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6560 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 161:aa5281ff4a02 6561 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6562 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6563 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 161:aa5281ff4a02 6564 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6565 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6566 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 161:aa5281ff4a02 6567 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6568 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6569 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 161:aa5281ff4a02 6570 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 6571 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6572 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 161:aa5281ff4a02 6573 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6574 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6575 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 161:aa5281ff4a02 6576 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6577 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6578 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 161:aa5281ff4a02 6579 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6580 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6581 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 161:aa5281ff4a02 6582 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6583 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6584 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 161:aa5281ff4a02 6585 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6586 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6587 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 161:aa5281ff4a02 6588 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 6589 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6590 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 161:aa5281ff4a02 6591 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 6592 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6593 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 161:aa5281ff4a02 6594 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 6595 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6596 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 161:aa5281ff4a02 6597 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6598 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6599 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 161:aa5281ff4a02 6600 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 6601 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6602 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 161:aa5281ff4a02 6603 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6604 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6605 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 161:aa5281ff4a02 6606 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6607 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6608 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 161:aa5281ff4a02 6609 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6610 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6611 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 161:aa5281ff4a02 6612 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6613 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6614 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 161:aa5281ff4a02 6615 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6616 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6617 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 161:aa5281ff4a02 6618
AnnaBridge 161:aa5281ff4a02 6619 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 161:aa5281ff4a02 6620 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6621 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6622 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 161:aa5281ff4a02 6623 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6624 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6625 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 161:aa5281ff4a02 6626 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6627 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6628 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 161:aa5281ff4a02 6629 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6630 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6631 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 161:aa5281ff4a02 6632 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6633 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6634 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 161:aa5281ff4a02 6635 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6636 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6637 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 161:aa5281ff4a02 6638 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6639 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6640 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 161:aa5281ff4a02 6641 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 6642 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6643 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 161:aa5281ff4a02 6644 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6645 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6646 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 161:aa5281ff4a02 6647 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6648 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6649 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 161:aa5281ff4a02 6650 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6651 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6652 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 161:aa5281ff4a02 6653 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6654 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6655 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 161:aa5281ff4a02 6656 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6657 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6658 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 161:aa5281ff4a02 6659 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 6660 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6661 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 161:aa5281ff4a02 6662 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 6663 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6664 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 161:aa5281ff4a02 6665 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 6666 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6667 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 161:aa5281ff4a02 6668 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6669 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6670 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 161:aa5281ff4a02 6671 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 161:aa5281ff4a02 6672 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6673 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 161:aa5281ff4a02 6674 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 161:aa5281ff4a02 6675 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6676 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 161:aa5281ff4a02 6677 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6678 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6679 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 161:aa5281ff4a02 6680 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 161:aa5281ff4a02 6681 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6682 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 161:aa5281ff4a02 6683 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 161:aa5281ff4a02 6684 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6685 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 161:aa5281ff4a02 6686 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 161:aa5281ff4a02 6687 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6688 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
AnnaBridge 161:aa5281ff4a02 6689
AnnaBridge 161:aa5281ff4a02 6690 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 6691 /* */
AnnaBridge 161:aa5281ff4a02 6692 /* FLASH */
AnnaBridge 161:aa5281ff4a02 6693 /* */
AnnaBridge 161:aa5281ff4a02 6694 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 6695 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 161:aa5281ff4a02 6696 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6697 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 6698 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 161:aa5281ff4a02 6699 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 161:aa5281ff4a02 6700 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 161:aa5281ff4a02 6701 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 161:aa5281ff4a02 6702 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 161:aa5281ff4a02 6703 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 161:aa5281ff4a02 6704 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 161:aa5281ff4a02 6705 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 161:aa5281ff4a02 6706 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 161:aa5281ff4a02 6707
AnnaBridge 161:aa5281ff4a02 6708 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6709 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6710 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 161:aa5281ff4a02 6711 #define FLASH_ACR_ICEN_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6712 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6713 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
AnnaBridge 161:aa5281ff4a02 6714 #define FLASH_ACR_DCEN_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6715 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6716 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
AnnaBridge 161:aa5281ff4a02 6717 #define FLASH_ACR_ICRST_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6718 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6719 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
AnnaBridge 161:aa5281ff4a02 6720 #define FLASH_ACR_DCRST_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6721 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6722 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
AnnaBridge 161:aa5281ff4a02 6723 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6724 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
AnnaBridge 161:aa5281ff4a02 6725 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
AnnaBridge 161:aa5281ff4a02 6726 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6727 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
AnnaBridge 161:aa5281ff4a02 6728 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
AnnaBridge 161:aa5281ff4a02 6729
AnnaBridge 161:aa5281ff4a02 6730 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 161:aa5281ff4a02 6731 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6732 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6733 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 161:aa5281ff4a02 6734 #define FLASH_SR_SOP_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6735 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6736 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
AnnaBridge 161:aa5281ff4a02 6737 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6738 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6739 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 161:aa5281ff4a02 6740 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6741 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6742 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 161:aa5281ff4a02 6743 #define FLASH_SR_PGPERR_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6744 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6745 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
AnnaBridge 161:aa5281ff4a02 6746 #define FLASH_SR_PGSERR_Pos (7U)
AnnaBridge 161:aa5281ff4a02 6747 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6748 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 161:aa5281ff4a02 6749 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6750 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6751 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
AnnaBridge 161:aa5281ff4a02 6752
AnnaBridge 161:aa5281ff4a02 6753 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 161:aa5281ff4a02 6754 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6755 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6756 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 161:aa5281ff4a02 6757 #define FLASH_CR_SER_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6758 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6759 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 161:aa5281ff4a02 6760 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6761 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6762 #define FLASH_CR_MER FLASH_CR_MER_Msk
AnnaBridge 161:aa5281ff4a02 6763 #define FLASH_CR_SNB_Pos (3U)
AnnaBridge 161:aa5281ff4a02 6764 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
AnnaBridge 161:aa5281ff4a02 6765 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 161:aa5281ff4a02 6766 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6767 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6768 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6769 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6770 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6771 #define FLASH_CR_PSIZE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6772 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 6773 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 161:aa5281ff4a02 6774 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6775 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6776 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6777 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6778 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 161:aa5281ff4a02 6779 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 161:aa5281ff4a02 6780 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 6781 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 161:aa5281ff4a02 6782 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 161:aa5281ff4a02 6783 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 6784 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
AnnaBridge 161:aa5281ff4a02 6785
AnnaBridge 161:aa5281ff4a02 6786 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 161:aa5281ff4a02 6787 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6788 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6789 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 161:aa5281ff4a02 6790 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6791 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6792 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
AnnaBridge 161:aa5281ff4a02 6793
AnnaBridge 161:aa5281ff4a02 6794 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
AnnaBridge 161:aa5281ff4a02 6795 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
AnnaBridge 161:aa5281ff4a02 6796 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6797 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 6798 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
AnnaBridge 161:aa5281ff4a02 6799 #define FLASH_OPTCR_WDG_SW_Pos (5U)
AnnaBridge 161:aa5281ff4a02 6800 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6801 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
AnnaBridge 161:aa5281ff4a02 6802 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6803 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6804 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
AnnaBridge 161:aa5281ff4a02 6805 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
AnnaBridge 161:aa5281ff4a02 6806 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 6807 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
AnnaBridge 161:aa5281ff4a02 6808 #define FLASH_OPTCR_RDP_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6809 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 6810 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
AnnaBridge 161:aa5281ff4a02 6811 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6812 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6813 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6814 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6815 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6816 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6817 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6818 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6819 #define FLASH_OPTCR_nWRP_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6820 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 161:aa5281ff4a02 6821 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
AnnaBridge 161:aa5281ff4a02 6822 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 161:aa5281ff4a02 6823 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 161:aa5281ff4a02 6824 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 161:aa5281ff4a02 6825 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 161:aa5281ff4a02 6826 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 161:aa5281ff4a02 6827 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 161:aa5281ff4a02 6828 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 161:aa5281ff4a02 6829 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 161:aa5281ff4a02 6830 #define FLASH_OPTCR_nWRP_8 0x01000000U
AnnaBridge 161:aa5281ff4a02 6831 #define FLASH_OPTCR_nWRP_9 0x02000000U
AnnaBridge 161:aa5281ff4a02 6832 #define FLASH_OPTCR_nWRP_10 0x04000000U
AnnaBridge 161:aa5281ff4a02 6833 #define FLASH_OPTCR_nWRP_11 0x08000000U
AnnaBridge 161:aa5281ff4a02 6834
AnnaBridge 161:aa5281ff4a02 6835 /****************** Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 161:aa5281ff4a02 6836 #define FLASH_OPTCR1_nWRP_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6837 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 161:aa5281ff4a02 6838 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
AnnaBridge 161:aa5281ff4a02 6839 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6840 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6841 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6842 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6843 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 6844 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 6845 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 6846 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 6847 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 6848 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 6849 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 6850 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 6851
AnnaBridge 161:aa5281ff4a02 6852 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 6853 /* */
AnnaBridge 161:aa5281ff4a02 6854 /* Flexible Static Memory Controller */
AnnaBridge 161:aa5281ff4a02 6855 /* */
AnnaBridge 161:aa5281ff4a02 6856 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 6857 /****************** Bit definition for FSMC_BCR1 register *******************/
AnnaBridge 161:aa5281ff4a02 6858 #define FSMC_BCR1_MBKEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6859 #define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6860 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 161:aa5281ff4a02 6861 #define FSMC_BCR1_MUXEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6862 #define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6863 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 161:aa5281ff4a02 6864
AnnaBridge 161:aa5281ff4a02 6865 #define FSMC_BCR1_MTYP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6866 #define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 6867 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 161:aa5281ff4a02 6868 #define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6869 #define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6870
AnnaBridge 161:aa5281ff4a02 6871 #define FSMC_BCR1_MWID_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6872 #define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 6873 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 161:aa5281ff4a02 6874 #define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6875 #define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6876
AnnaBridge 161:aa5281ff4a02 6877 #define FSMC_BCR1_FACCEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6878 #define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6879 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 161:aa5281ff4a02 6880 #define FSMC_BCR1_BURSTEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6881 #define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6882 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 161:aa5281ff4a02 6883 #define FSMC_BCR1_WAITPOL_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6884 #define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6885 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 161:aa5281ff4a02 6886 #define FSMC_BCR1_WRAPMOD_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6887 #define FSMC_BCR1_WRAPMOD_Msk (0x1U << FSMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6888 #define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 161:aa5281ff4a02 6889 #define FSMC_BCR1_WAITCFG_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6890 #define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6891 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 161:aa5281ff4a02 6892 #define FSMC_BCR1_WREN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6893 #define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6894 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
AnnaBridge 161:aa5281ff4a02 6895 #define FSMC_BCR1_WAITEN_Pos (13U)
AnnaBridge 161:aa5281ff4a02 6896 #define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6897 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 161:aa5281ff4a02 6898 #define FSMC_BCR1_EXTMOD_Pos (14U)
AnnaBridge 161:aa5281ff4a02 6899 #define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6900 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 161:aa5281ff4a02 6901 #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
AnnaBridge 161:aa5281ff4a02 6902 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6903 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 161:aa5281ff4a02 6904 #define FSMC_BCR1_CPSIZE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6905 #define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 161:aa5281ff4a02 6906 #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 161:aa5281ff4a02 6907 #define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6908 #define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6909 #define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6910 #define FSMC_BCR1_CBURSTRW_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6911 #define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6912 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 161:aa5281ff4a02 6913
AnnaBridge 161:aa5281ff4a02 6914 /****************** Bit definition for FSMC_BCR2 register *******************/
AnnaBridge 161:aa5281ff4a02 6915 #define FSMC_BCR2_MBKEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6916 #define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6917 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 161:aa5281ff4a02 6918 #define FSMC_BCR2_MUXEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6919 #define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6920 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 161:aa5281ff4a02 6921
AnnaBridge 161:aa5281ff4a02 6922 #define FSMC_BCR2_MTYP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6923 #define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 6924 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 161:aa5281ff4a02 6925 #define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6926 #define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6927
AnnaBridge 161:aa5281ff4a02 6928 #define FSMC_BCR2_MWID_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6929 #define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 6930 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 161:aa5281ff4a02 6931 #define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6932 #define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6933
AnnaBridge 161:aa5281ff4a02 6934 #define FSMC_BCR2_FACCEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6935 #define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6936 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 161:aa5281ff4a02 6937 #define FSMC_BCR2_BURSTEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6938 #define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6939 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 161:aa5281ff4a02 6940 #define FSMC_BCR2_WAITPOL_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6941 #define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6942 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 161:aa5281ff4a02 6943 #define FSMC_BCR2_WRAPMOD_Pos (10U)
AnnaBridge 161:aa5281ff4a02 6944 #define FSMC_BCR2_WRAPMOD_Msk (0x1U << FSMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 6945 #define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 161:aa5281ff4a02 6946 #define FSMC_BCR2_WAITCFG_Pos (11U)
AnnaBridge 161:aa5281ff4a02 6947 #define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 6948 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 161:aa5281ff4a02 6949 #define FSMC_BCR2_WREN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 6950 #define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 6951 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
AnnaBridge 161:aa5281ff4a02 6952 #define FSMC_BCR2_WAITEN_Pos (13U)
AnnaBridge 161:aa5281ff4a02 6953 #define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 6954 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 161:aa5281ff4a02 6955 #define FSMC_BCR2_EXTMOD_Pos (14U)
AnnaBridge 161:aa5281ff4a02 6956 #define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 6957 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 161:aa5281ff4a02 6958 #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
AnnaBridge 161:aa5281ff4a02 6959 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 6960 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 161:aa5281ff4a02 6961 #define FSMC_BCR2_CPSIZE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 6962 #define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 161:aa5281ff4a02 6963 #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 161:aa5281ff4a02 6964 #define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 6965 #define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 6966 #define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 6967 #define FSMC_BCR2_CBURSTRW_Pos (19U)
AnnaBridge 161:aa5281ff4a02 6968 #define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 6969 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 161:aa5281ff4a02 6970
AnnaBridge 161:aa5281ff4a02 6971 /****************** Bit definition for FSMC_BCR3 register *******************/
AnnaBridge 161:aa5281ff4a02 6972 #define FSMC_BCR3_MBKEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 6973 #define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 6974 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 161:aa5281ff4a02 6975 #define FSMC_BCR3_MUXEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 6976 #define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 6977 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 161:aa5281ff4a02 6978
AnnaBridge 161:aa5281ff4a02 6979 #define FSMC_BCR3_MTYP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 6980 #define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 6981 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 161:aa5281ff4a02 6982 #define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 6983 #define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 6984
AnnaBridge 161:aa5281ff4a02 6985 #define FSMC_BCR3_MWID_Pos (4U)
AnnaBridge 161:aa5281ff4a02 6986 #define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 6987 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 161:aa5281ff4a02 6988 #define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 6989 #define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 6990
AnnaBridge 161:aa5281ff4a02 6991 #define FSMC_BCR3_FACCEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 6992 #define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 6993 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 161:aa5281ff4a02 6994 #define FSMC_BCR3_BURSTEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 6995 #define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 6996 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 161:aa5281ff4a02 6997 #define FSMC_BCR3_WAITPOL_Pos (9U)
AnnaBridge 161:aa5281ff4a02 6998 #define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 6999 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 161:aa5281ff4a02 7000 #define FSMC_BCR3_WRAPMOD_Pos (10U)
AnnaBridge 161:aa5281ff4a02 7001 #define FSMC_BCR3_WRAPMOD_Msk (0x1U << FSMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7002 #define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 161:aa5281ff4a02 7003 #define FSMC_BCR3_WAITCFG_Pos (11U)
AnnaBridge 161:aa5281ff4a02 7004 #define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7005 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 161:aa5281ff4a02 7006 #define FSMC_BCR3_WREN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 7007 #define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7008 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
AnnaBridge 161:aa5281ff4a02 7009 #define FSMC_BCR3_WAITEN_Pos (13U)
AnnaBridge 161:aa5281ff4a02 7010 #define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7011 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 161:aa5281ff4a02 7012 #define FSMC_BCR3_EXTMOD_Pos (14U)
AnnaBridge 161:aa5281ff4a02 7013 #define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7014 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 161:aa5281ff4a02 7015 #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
AnnaBridge 161:aa5281ff4a02 7016 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7017 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 161:aa5281ff4a02 7018 #define FSMC_BCR3_CPSIZE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7019 #define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 161:aa5281ff4a02 7020 #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 161:aa5281ff4a02 7021 #define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7022 #define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7023 #define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7024 #define FSMC_BCR3_CBURSTRW_Pos (19U)
AnnaBridge 161:aa5281ff4a02 7025 #define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7026 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 161:aa5281ff4a02 7027
AnnaBridge 161:aa5281ff4a02 7028 /****************** Bit definition for FSMC_BCR4 register *******************/
AnnaBridge 161:aa5281ff4a02 7029 #define FSMC_BCR4_MBKEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7030 #define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7031 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 161:aa5281ff4a02 7032 #define FSMC_BCR4_MUXEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 7033 #define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7034 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 161:aa5281ff4a02 7035
AnnaBridge 161:aa5281ff4a02 7036 #define FSMC_BCR4_MTYP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 7037 #define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 7038 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 161:aa5281ff4a02 7039 #define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7040 #define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7041
AnnaBridge 161:aa5281ff4a02 7042 #define FSMC_BCR4_MWID_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7043 #define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 7044 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 161:aa5281ff4a02 7045 #define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7046 #define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7047
AnnaBridge 161:aa5281ff4a02 7048 #define FSMC_BCR4_FACCEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 7049 #define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7050 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 161:aa5281ff4a02 7051 #define FSMC_BCR4_BURSTEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7052 #define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7053 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 161:aa5281ff4a02 7054 #define FSMC_BCR4_WAITPOL_Pos (9U)
AnnaBridge 161:aa5281ff4a02 7055 #define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7056 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 161:aa5281ff4a02 7057 #define FSMC_BCR4_WRAPMOD_Pos (10U)
AnnaBridge 161:aa5281ff4a02 7058 #define FSMC_BCR4_WRAPMOD_Msk (0x1U << FSMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7059 #define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 161:aa5281ff4a02 7060 #define FSMC_BCR4_WAITCFG_Pos (11U)
AnnaBridge 161:aa5281ff4a02 7061 #define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7062 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 161:aa5281ff4a02 7063 #define FSMC_BCR4_WREN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 7064 #define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7065 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
AnnaBridge 161:aa5281ff4a02 7066 #define FSMC_BCR4_WAITEN_Pos (13U)
AnnaBridge 161:aa5281ff4a02 7067 #define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7068 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 161:aa5281ff4a02 7069 #define FSMC_BCR4_EXTMOD_Pos (14U)
AnnaBridge 161:aa5281ff4a02 7070 #define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7071 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 161:aa5281ff4a02 7072 #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
AnnaBridge 161:aa5281ff4a02 7073 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7074 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 161:aa5281ff4a02 7075 #define FSMC_BCR4_CPSIZE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7076 #define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 161:aa5281ff4a02 7077 #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 161:aa5281ff4a02 7078 #define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7079 #define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7080 #define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7081 #define FSMC_BCR4_CBURSTRW_Pos (19U)
AnnaBridge 161:aa5281ff4a02 7082 #define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7083 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 161:aa5281ff4a02 7084
AnnaBridge 161:aa5281ff4a02 7085 /****************** Bit definition for FSMC_BTR1 register ******************/
AnnaBridge 161:aa5281ff4a02 7086 #define FSMC_BTR1_ADDSET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7087 #define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 7088 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 161:aa5281ff4a02 7089 #define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7090 #define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7091 #define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7092 #define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7093
AnnaBridge 161:aa5281ff4a02 7094 #define FSMC_BTR1_ADDHLD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7095 #define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 7096 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 161:aa5281ff4a02 7097 #define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7098 #define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7099 #define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7100 #define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7101
AnnaBridge 161:aa5281ff4a02 7102 #define FSMC_BTR1_DATAST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7103 #define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7104 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 161:aa5281ff4a02 7105 #define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7106 #define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7107 #define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7108 #define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7109 #define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7110 #define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7111 #define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7112 #define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7113
AnnaBridge 161:aa5281ff4a02 7114 #define FSMC_BTR1_BUSTURN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7115 #define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 7116 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 161:aa5281ff4a02 7117 #define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7118 #define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7119 #define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7120 #define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7121
AnnaBridge 161:aa5281ff4a02 7122 #define FSMC_BTR1_CLKDIV_Pos (20U)
AnnaBridge 161:aa5281ff4a02 7123 #define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 161:aa5281ff4a02 7124 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 161:aa5281ff4a02 7125 #define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7126 #define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7127 #define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7128 #define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7129
AnnaBridge 161:aa5281ff4a02 7130 #define FSMC_BTR1_DATLAT_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7131 #define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 7132 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 161:aa5281ff4a02 7133 #define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7134 #define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7135 #define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7136 #define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7137
AnnaBridge 161:aa5281ff4a02 7138 #define FSMC_BTR1_ACCMOD_Pos (28U)
AnnaBridge 161:aa5281ff4a02 7139 #define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 7140 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 161:aa5281ff4a02 7141 #define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7142 #define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7143
AnnaBridge 161:aa5281ff4a02 7144 /****************** Bit definition for FSMC_BTR2 register *******************/
AnnaBridge 161:aa5281ff4a02 7145 #define FSMC_BTR2_ADDSET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7146 #define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 7147 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 161:aa5281ff4a02 7148 #define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7149 #define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7150 #define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7151 #define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7152
AnnaBridge 161:aa5281ff4a02 7153 #define FSMC_BTR2_ADDHLD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7154 #define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 7155 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 161:aa5281ff4a02 7156 #define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7157 #define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7158 #define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7159 #define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7160
AnnaBridge 161:aa5281ff4a02 7161 #define FSMC_BTR2_DATAST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7162 #define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7163 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 161:aa5281ff4a02 7164 #define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7165 #define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7166 #define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7167 #define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7168 #define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7169 #define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7170 #define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7171 #define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7172
AnnaBridge 161:aa5281ff4a02 7173 #define FSMC_BTR2_BUSTURN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7174 #define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 7175 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 161:aa5281ff4a02 7176 #define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7177 #define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7178 #define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7179 #define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7180
AnnaBridge 161:aa5281ff4a02 7181 #define FSMC_BTR2_CLKDIV_Pos (20U)
AnnaBridge 161:aa5281ff4a02 7182 #define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 161:aa5281ff4a02 7183 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 161:aa5281ff4a02 7184 #define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7185 #define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7186 #define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7187 #define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7188
AnnaBridge 161:aa5281ff4a02 7189 #define FSMC_BTR2_DATLAT_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7190 #define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 7191 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 161:aa5281ff4a02 7192 #define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7193 #define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7194 #define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7195 #define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7196
AnnaBridge 161:aa5281ff4a02 7197 #define FSMC_BTR2_ACCMOD_Pos (28U)
AnnaBridge 161:aa5281ff4a02 7198 #define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 7199 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 161:aa5281ff4a02 7200 #define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7201 #define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7202
AnnaBridge 161:aa5281ff4a02 7203 /******************* Bit definition for FSMC_BTR3 register *******************/
AnnaBridge 161:aa5281ff4a02 7204 #define FSMC_BTR3_ADDSET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7205 #define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 7206 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 161:aa5281ff4a02 7207 #define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7208 #define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7209 #define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7210 #define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7211
AnnaBridge 161:aa5281ff4a02 7212 #define FSMC_BTR3_ADDHLD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7213 #define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 7214 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 161:aa5281ff4a02 7215 #define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7216 #define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7217 #define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7218 #define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7219
AnnaBridge 161:aa5281ff4a02 7220 #define FSMC_BTR3_DATAST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7221 #define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7222 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 161:aa5281ff4a02 7223 #define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7224 #define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7225 #define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7226 #define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7227 #define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7228 #define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7229 #define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7230 #define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7231
AnnaBridge 161:aa5281ff4a02 7232 #define FSMC_BTR3_BUSTURN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7233 #define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 7234 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 161:aa5281ff4a02 7235 #define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7236 #define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7237 #define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7238 #define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7239
AnnaBridge 161:aa5281ff4a02 7240 #define FSMC_BTR3_CLKDIV_Pos (20U)
AnnaBridge 161:aa5281ff4a02 7241 #define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 161:aa5281ff4a02 7242 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 161:aa5281ff4a02 7243 #define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7244 #define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7245 #define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7246 #define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7247
AnnaBridge 161:aa5281ff4a02 7248 #define FSMC_BTR3_DATLAT_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7249 #define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 7250 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 161:aa5281ff4a02 7251 #define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7252 #define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7253 #define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7254 #define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7255
AnnaBridge 161:aa5281ff4a02 7256 #define FSMC_BTR3_ACCMOD_Pos (28U)
AnnaBridge 161:aa5281ff4a02 7257 #define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 7258 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 161:aa5281ff4a02 7259 #define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7260 #define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7261
AnnaBridge 161:aa5281ff4a02 7262 /****************** Bit definition for FSMC_BTR4 register *******************/
AnnaBridge 161:aa5281ff4a02 7263 #define FSMC_BTR4_ADDSET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7264 #define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 7265 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 161:aa5281ff4a02 7266 #define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7267 #define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7268 #define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7269 #define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7270
AnnaBridge 161:aa5281ff4a02 7271 #define FSMC_BTR4_ADDHLD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7272 #define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 7273 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 161:aa5281ff4a02 7274 #define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7275 #define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7276 #define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7277 #define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7278
AnnaBridge 161:aa5281ff4a02 7279 #define FSMC_BTR4_DATAST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7280 #define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7281 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 161:aa5281ff4a02 7282 #define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7283 #define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7284 #define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7285 #define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7286 #define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7287 #define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7288 #define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7289 #define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7290
AnnaBridge 161:aa5281ff4a02 7291 #define FSMC_BTR4_BUSTURN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7292 #define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 7293 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 161:aa5281ff4a02 7294 #define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7295 #define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7296 #define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7297 #define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7298
AnnaBridge 161:aa5281ff4a02 7299 #define FSMC_BTR4_CLKDIV_Pos (20U)
AnnaBridge 161:aa5281ff4a02 7300 #define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 161:aa5281ff4a02 7301 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 161:aa5281ff4a02 7302 #define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7303 #define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7304 #define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7305 #define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7306
AnnaBridge 161:aa5281ff4a02 7307 #define FSMC_BTR4_DATLAT_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7308 #define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 7309 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 161:aa5281ff4a02 7310 #define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7311 #define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7312 #define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7313 #define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7314
AnnaBridge 161:aa5281ff4a02 7315 #define FSMC_BTR4_ACCMOD_Pos (28U)
AnnaBridge 161:aa5281ff4a02 7316 #define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 7317 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 161:aa5281ff4a02 7318 #define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7319 #define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7320
AnnaBridge 161:aa5281ff4a02 7321 /****************** Bit definition for FSMC_BWTR1 register ******************/
AnnaBridge 161:aa5281ff4a02 7322 #define FSMC_BWTR1_ADDSET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7323 #define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 7324 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 161:aa5281ff4a02 7325 #define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7326 #define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7327 #define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7328 #define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7329
AnnaBridge 161:aa5281ff4a02 7330 #define FSMC_BWTR1_ADDHLD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7331 #define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 7332 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 161:aa5281ff4a02 7333 #define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7334 #define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7335 #define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7336 #define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7337
AnnaBridge 161:aa5281ff4a02 7338 #define FSMC_BWTR1_DATAST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7339 #define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7340 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 161:aa5281ff4a02 7341 #define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7342 #define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7343 #define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7344 #define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7345 #define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7346 #define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7347 #define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7348 #define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7349
AnnaBridge 161:aa5281ff4a02 7350 #define FSMC_BWTR1_BUSTURN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7351 #define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 7352 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 161:aa5281ff4a02 7353 #define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7354 #define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7355 #define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7356 #define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7357
AnnaBridge 161:aa5281ff4a02 7358 #define FSMC_BWTR1_ACCMOD_Pos (28U)
AnnaBridge 161:aa5281ff4a02 7359 #define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 7360 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 161:aa5281ff4a02 7361 #define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7362 #define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7363
AnnaBridge 161:aa5281ff4a02 7364 /****************** Bit definition for FSMC_BWTR2 register ******************/
AnnaBridge 161:aa5281ff4a02 7365 #define FSMC_BWTR2_ADDSET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7366 #define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 7367 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 161:aa5281ff4a02 7368 #define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7369 #define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7370 #define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7371 #define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7372
AnnaBridge 161:aa5281ff4a02 7373 #define FSMC_BWTR2_ADDHLD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7374 #define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 7375 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 161:aa5281ff4a02 7376 #define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7377 #define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7378 #define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7379 #define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7380
AnnaBridge 161:aa5281ff4a02 7381 #define FSMC_BWTR2_DATAST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7382 #define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7383 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 161:aa5281ff4a02 7384 #define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7385 #define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7386 #define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7387 #define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7388 #define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7389 #define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7390 #define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7391 #define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7392
AnnaBridge 161:aa5281ff4a02 7393 #define FSMC_BWTR2_BUSTURN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7394 #define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 7395 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 161:aa5281ff4a02 7396 #define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7397 #define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7398 #define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7399 #define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7400
AnnaBridge 161:aa5281ff4a02 7401 #define FSMC_BWTR2_ACCMOD_Pos (28U)
AnnaBridge 161:aa5281ff4a02 7402 #define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 7403 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 161:aa5281ff4a02 7404 #define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7405 #define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7406
AnnaBridge 161:aa5281ff4a02 7407 /****************** Bit definition for FSMC_BWTR3 register ******************/
AnnaBridge 161:aa5281ff4a02 7408 #define FSMC_BWTR3_ADDSET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7409 #define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 7410 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 161:aa5281ff4a02 7411 #define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7412 #define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7413 #define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7414 #define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7415
AnnaBridge 161:aa5281ff4a02 7416 #define FSMC_BWTR3_ADDHLD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7417 #define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 7418 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 161:aa5281ff4a02 7419 #define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7420 #define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7421 #define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7422 #define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7423
AnnaBridge 161:aa5281ff4a02 7424 #define FSMC_BWTR3_DATAST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7425 #define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7426 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
AnnaBridge 161:aa5281ff4a02 7427 #define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7428 #define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7429 #define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7430 #define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7431 #define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7432 #define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7433 #define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7434 #define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7435
AnnaBridge 161:aa5281ff4a02 7436 #define FSMC_BWTR3_BUSTURN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7437 #define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 7438 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 161:aa5281ff4a02 7439 #define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7440 #define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7441 #define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7442 #define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7443
AnnaBridge 161:aa5281ff4a02 7444 #define FSMC_BWTR3_ACCMOD_Pos (28U)
AnnaBridge 161:aa5281ff4a02 7445 #define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 7446 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 161:aa5281ff4a02 7447 #define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7448 #define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7449
AnnaBridge 161:aa5281ff4a02 7450 /****************** Bit definition for FSMC_BWTR4 register ******************/
AnnaBridge 161:aa5281ff4a02 7451 #define FSMC_BWTR4_ADDSET_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7452 #define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 7453 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 161:aa5281ff4a02 7454 #define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7455 #define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7456 #define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7457 #define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7458
AnnaBridge 161:aa5281ff4a02 7459 #define FSMC_BWTR4_ADDHLD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7460 #define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 7461 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 161:aa5281ff4a02 7462 #define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7463 #define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7464 #define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7465 #define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7466
AnnaBridge 161:aa5281ff4a02 7467 #define FSMC_BWTR4_DATAST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7468 #define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7469 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 161:aa5281ff4a02 7470 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 161:aa5281ff4a02 7471 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 161:aa5281ff4a02 7472 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 161:aa5281ff4a02 7473 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 161:aa5281ff4a02 7474 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 161:aa5281ff4a02 7475 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 161:aa5281ff4a02 7476 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 161:aa5281ff4a02 7477 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 161:aa5281ff4a02 7478
AnnaBridge 161:aa5281ff4a02 7479 #define FSMC_BWTR4_BUSTURN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7480 #define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 7481 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 161:aa5281ff4a02 7482 #define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7483 #define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7484 #define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7485 #define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7486
AnnaBridge 161:aa5281ff4a02 7487 #define FSMC_BWTR4_ACCMOD_Pos (28U)
AnnaBridge 161:aa5281ff4a02 7488 #define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 7489 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 161:aa5281ff4a02 7490 #define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7491 #define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7492
AnnaBridge 161:aa5281ff4a02 7493 /****************** Bit definition for FSMC_PCR2 register *******************/
AnnaBridge 161:aa5281ff4a02 7494 #define FSMC_PCR2_PWAITEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 7495 #define FSMC_PCR2_PWAITEN_Msk (0x1U << FSMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7496 #define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 161:aa5281ff4a02 7497 #define FSMC_PCR2_PBKEN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 7498 #define FSMC_PCR2_PBKEN_Msk (0x1U << FSMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7499 #define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 161:aa5281ff4a02 7500 #define FSMC_PCR2_PTYP_Pos (3U)
AnnaBridge 161:aa5281ff4a02 7501 #define FSMC_PCR2_PTYP_Msk (0x1U << FSMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7502 #define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk /*!<Memory type */
AnnaBridge 161:aa5281ff4a02 7503
AnnaBridge 161:aa5281ff4a02 7504 #define FSMC_PCR2_PWID_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7505 #define FSMC_PCR2_PWID_Msk (0x3U << FSMC_PCR2_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 7506 #define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 161:aa5281ff4a02 7507 #define FSMC_PCR2_PWID_0 (0x1U << FSMC_PCR2_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7508 #define FSMC_PCR2_PWID_1 (0x2U << FSMC_PCR2_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7509
AnnaBridge 161:aa5281ff4a02 7510 #define FSMC_PCR2_ECCEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 7511 #define FSMC_PCR2_ECCEN_Msk (0x1U << FSMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7512 #define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 161:aa5281ff4a02 7513
AnnaBridge 161:aa5281ff4a02 7514 #define FSMC_PCR2_TCLR_Pos (9U)
AnnaBridge 161:aa5281ff4a02 7515 #define FSMC_PCR2_TCLR_Msk (0xFU << FSMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 161:aa5281ff4a02 7516 #define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 161:aa5281ff4a02 7517 #define FSMC_PCR2_TCLR_0 (0x1U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7518 #define FSMC_PCR2_TCLR_1 (0x2U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7519 #define FSMC_PCR2_TCLR_2 (0x4U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7520 #define FSMC_PCR2_TCLR_3 (0x8U << FSMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7521
AnnaBridge 161:aa5281ff4a02 7522 #define FSMC_PCR2_TAR_Pos (13U)
AnnaBridge 161:aa5281ff4a02 7523 #define FSMC_PCR2_TAR_Msk (0xFU << FSMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 161:aa5281ff4a02 7524 #define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 161:aa5281ff4a02 7525 #define FSMC_PCR2_TAR_0 (0x1U << FSMC_PCR2_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7526 #define FSMC_PCR2_TAR_1 (0x2U << FSMC_PCR2_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7527 #define FSMC_PCR2_TAR_2 (0x4U << FSMC_PCR2_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7528 #define FSMC_PCR2_TAR_3 (0x8U << FSMC_PCR2_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7529
AnnaBridge 161:aa5281ff4a02 7530 #define FSMC_PCR2_ECCPS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 7531 #define FSMC_PCR2_ECCPS_Msk (0x7U << FSMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 161:aa5281ff4a02 7532 #define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
AnnaBridge 161:aa5281ff4a02 7533 #define FSMC_PCR2_ECCPS_0 (0x1U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7534 #define FSMC_PCR2_ECCPS_1 (0x2U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7535 #define FSMC_PCR2_ECCPS_2 (0x4U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7536
AnnaBridge 161:aa5281ff4a02 7537 /****************** Bit definition for FSMC_PCR3 register *******************/
AnnaBridge 161:aa5281ff4a02 7538 #define FSMC_PCR3_PWAITEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 7539 #define FSMC_PCR3_PWAITEN_Msk (0x1U << FSMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7540 #define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 161:aa5281ff4a02 7541 #define FSMC_PCR3_PBKEN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 7542 #define FSMC_PCR3_PBKEN_Msk (0x1U << FSMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7543 #define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 161:aa5281ff4a02 7544 #define FSMC_PCR3_PTYP_Pos (3U)
AnnaBridge 161:aa5281ff4a02 7545 #define FSMC_PCR3_PTYP_Msk (0x1U << FSMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7546 #define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk /*!<Memory type */
AnnaBridge 161:aa5281ff4a02 7547
AnnaBridge 161:aa5281ff4a02 7548 #define FSMC_PCR3_PWID_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7549 #define FSMC_PCR3_PWID_Msk (0x3U << FSMC_PCR3_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 7550 #define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 161:aa5281ff4a02 7551 #define FSMC_PCR3_PWID_0 (0x1U << FSMC_PCR3_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7552 #define FSMC_PCR3_PWID_1 (0x2U << FSMC_PCR3_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7553
AnnaBridge 161:aa5281ff4a02 7554 #define FSMC_PCR3_ECCEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 7555 #define FSMC_PCR3_ECCEN_Msk (0x1U << FSMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7556 #define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 161:aa5281ff4a02 7557
AnnaBridge 161:aa5281ff4a02 7558 #define FSMC_PCR3_TCLR_Pos (9U)
AnnaBridge 161:aa5281ff4a02 7559 #define FSMC_PCR3_TCLR_Msk (0xFU << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 161:aa5281ff4a02 7560 #define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 161:aa5281ff4a02 7561 #define FSMC_PCR3_TCLR_0 (0x1U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7562 #define FSMC_PCR3_TCLR_1 (0x2U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7563 #define FSMC_PCR3_TCLR_2 (0x4U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7564 #define FSMC_PCR3_TCLR_3 (0x8U << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7565
AnnaBridge 161:aa5281ff4a02 7566 #define FSMC_PCR3_TAR_Pos (13U)
AnnaBridge 161:aa5281ff4a02 7567 #define FSMC_PCR3_TAR_Msk (0xFU << FSMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 161:aa5281ff4a02 7568 #define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 161:aa5281ff4a02 7569 #define FSMC_PCR3_TAR_0 (0x1U << FSMC_PCR3_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7570 #define FSMC_PCR3_TAR_1 (0x2U << FSMC_PCR3_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7571 #define FSMC_PCR3_TAR_2 (0x4U << FSMC_PCR3_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7572 #define FSMC_PCR3_TAR_3 (0x8U << FSMC_PCR3_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7573
AnnaBridge 161:aa5281ff4a02 7574 #define FSMC_PCR3_ECCPS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 7575 #define FSMC_PCR3_ECCPS_Msk (0x7U << FSMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 161:aa5281ff4a02 7576 #define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
AnnaBridge 161:aa5281ff4a02 7577 #define FSMC_PCR3_ECCPS_0 (0x1U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7578 #define FSMC_PCR3_ECCPS_1 (0x2U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7579 #define FSMC_PCR3_ECCPS_2 (0x4U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7580
AnnaBridge 161:aa5281ff4a02 7581 /****************** Bit definition for FSMC_PCR4 register *******************/
AnnaBridge 161:aa5281ff4a02 7582 #define FSMC_PCR4_PWAITEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 7583 #define FSMC_PCR4_PWAITEN_Msk (0x1U << FSMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7584 #define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 161:aa5281ff4a02 7585 #define FSMC_PCR4_PBKEN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 7586 #define FSMC_PCR4_PBKEN_Msk (0x1U << FSMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7587 #define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 161:aa5281ff4a02 7588 #define FSMC_PCR4_PTYP_Pos (3U)
AnnaBridge 161:aa5281ff4a02 7589 #define FSMC_PCR4_PTYP_Msk (0x1U << FSMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7590 #define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk /*!<Memory type */
AnnaBridge 161:aa5281ff4a02 7591
AnnaBridge 161:aa5281ff4a02 7592 #define FSMC_PCR4_PWID_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7593 #define FSMC_PCR4_PWID_Msk (0x3U << FSMC_PCR4_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 7594 #define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 161:aa5281ff4a02 7595 #define FSMC_PCR4_PWID_0 (0x1U << FSMC_PCR4_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7596 #define FSMC_PCR4_PWID_1 (0x2U << FSMC_PCR4_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7597
AnnaBridge 161:aa5281ff4a02 7598 #define FSMC_PCR4_ECCEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 7599 #define FSMC_PCR4_ECCEN_Msk (0x1U << FSMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7600 #define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 161:aa5281ff4a02 7601
AnnaBridge 161:aa5281ff4a02 7602 #define FSMC_PCR4_TCLR_Pos (9U)
AnnaBridge 161:aa5281ff4a02 7603 #define FSMC_PCR4_TCLR_Msk (0xFU << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 161:aa5281ff4a02 7604 #define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 161:aa5281ff4a02 7605 #define FSMC_PCR4_TCLR_0 (0x1U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7606 #define FSMC_PCR4_TCLR_1 (0x2U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7607 #define FSMC_PCR4_TCLR_2 (0x4U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7608 #define FSMC_PCR4_TCLR_3 (0x8U << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7609
AnnaBridge 161:aa5281ff4a02 7610 #define FSMC_PCR4_TAR_Pos (13U)
AnnaBridge 161:aa5281ff4a02 7611 #define FSMC_PCR4_TAR_Msk (0xFU << FSMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 161:aa5281ff4a02 7612 #define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 161:aa5281ff4a02 7613 #define FSMC_PCR4_TAR_0 (0x1U << FSMC_PCR4_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7614 #define FSMC_PCR4_TAR_1 (0x2U << FSMC_PCR4_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7615 #define FSMC_PCR4_TAR_2 (0x4U << FSMC_PCR4_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7616 #define FSMC_PCR4_TAR_3 (0x8U << FSMC_PCR4_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7617
AnnaBridge 161:aa5281ff4a02 7618 #define FSMC_PCR4_ECCPS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 7619 #define FSMC_PCR4_ECCPS_Msk (0x7U << FSMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 161:aa5281ff4a02 7620 #define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
AnnaBridge 161:aa5281ff4a02 7621 #define FSMC_PCR4_ECCPS_0 (0x1U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7622 #define FSMC_PCR4_ECCPS_1 (0x2U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7623 #define FSMC_PCR4_ECCPS_2 (0x4U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7624
AnnaBridge 161:aa5281ff4a02 7625 /******************* Bit definition for FSMC_SR2 register *******************/
AnnaBridge 161:aa5281ff4a02 7626 #define FSMC_SR2_IRS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7627 #define FSMC_SR2_IRS_Msk (0x1U << FSMC_SR2_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7628 #define FSMC_SR2_IRS FSMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 161:aa5281ff4a02 7629 #define FSMC_SR2_ILS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 7630 #define FSMC_SR2_ILS_Msk (0x1U << FSMC_SR2_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7631 #define FSMC_SR2_ILS FSMC_SR2_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 161:aa5281ff4a02 7632 #define FSMC_SR2_IFS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 7633 #define FSMC_SR2_IFS_Msk (0x1U << FSMC_SR2_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7634 #define FSMC_SR2_IFS FSMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 161:aa5281ff4a02 7635 #define FSMC_SR2_IREN_Pos (3U)
AnnaBridge 161:aa5281ff4a02 7636 #define FSMC_SR2_IREN_Msk (0x1U << FSMC_SR2_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7637 #define FSMC_SR2_IREN FSMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7638 #define FSMC_SR2_ILEN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7639 #define FSMC_SR2_ILEN_Msk (0x1U << FSMC_SR2_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7640 #define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7641 #define FSMC_SR2_IFEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 7642 #define FSMC_SR2_IFEN_Msk (0x1U << FSMC_SR2_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7643 #define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7644 #define FSMC_SR2_FEMPT_Pos (6U)
AnnaBridge 161:aa5281ff4a02 7645 #define FSMC_SR2_FEMPT_Msk (0x1U << FSMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7646 #define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk /*!<FIFO empty */
AnnaBridge 161:aa5281ff4a02 7647
AnnaBridge 161:aa5281ff4a02 7648 /******************* Bit definition for FSMC_SR3 register *******************/
AnnaBridge 161:aa5281ff4a02 7649 #define FSMC_SR3_IRS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7650 #define FSMC_SR3_IRS_Msk (0x1U << FSMC_SR3_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7651 #define FSMC_SR3_IRS FSMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 161:aa5281ff4a02 7652 #define FSMC_SR3_ILS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 7653 #define FSMC_SR3_ILS_Msk (0x1U << FSMC_SR3_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7654 #define FSMC_SR3_ILS FSMC_SR3_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 161:aa5281ff4a02 7655 #define FSMC_SR3_IFS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 7656 #define FSMC_SR3_IFS_Msk (0x1U << FSMC_SR3_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7657 #define FSMC_SR3_IFS FSMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 161:aa5281ff4a02 7658 #define FSMC_SR3_IREN_Pos (3U)
AnnaBridge 161:aa5281ff4a02 7659 #define FSMC_SR3_IREN_Msk (0x1U << FSMC_SR3_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7660 #define FSMC_SR3_IREN FSMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7661 #define FSMC_SR3_ILEN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7662 #define FSMC_SR3_ILEN_Msk (0x1U << FSMC_SR3_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7663 #define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7664 #define FSMC_SR3_IFEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 7665 #define FSMC_SR3_IFEN_Msk (0x1U << FSMC_SR3_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7666 #define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7667 #define FSMC_SR3_FEMPT_Pos (6U)
AnnaBridge 161:aa5281ff4a02 7668 #define FSMC_SR3_FEMPT_Msk (0x1U << FSMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7669 #define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk /*!<FIFO empty */
AnnaBridge 161:aa5281ff4a02 7670
AnnaBridge 161:aa5281ff4a02 7671 /******************* Bit definition for FSMC_SR4 register *******************/
AnnaBridge 161:aa5281ff4a02 7672 #define FSMC_SR4_IRS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7673 #define FSMC_SR4_IRS_Msk (0x1U << FSMC_SR4_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7674 #define FSMC_SR4_IRS FSMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 161:aa5281ff4a02 7675 #define FSMC_SR4_ILS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 7676 #define FSMC_SR4_ILS_Msk (0x1U << FSMC_SR4_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7677 #define FSMC_SR4_ILS FSMC_SR4_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 161:aa5281ff4a02 7678 #define FSMC_SR4_IFS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 7679 #define FSMC_SR4_IFS_Msk (0x1U << FSMC_SR4_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7680 #define FSMC_SR4_IFS FSMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 161:aa5281ff4a02 7681 #define FSMC_SR4_IREN_Pos (3U)
AnnaBridge 161:aa5281ff4a02 7682 #define FSMC_SR4_IREN_Msk (0x1U << FSMC_SR4_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7683 #define FSMC_SR4_IREN FSMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7684 #define FSMC_SR4_ILEN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 7685 #define FSMC_SR4_ILEN_Msk (0x1U << FSMC_SR4_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7686 #define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7687 #define FSMC_SR4_IFEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 7688 #define FSMC_SR4_IFEN_Msk (0x1U << FSMC_SR4_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7689 #define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 161:aa5281ff4a02 7690 #define FSMC_SR4_FEMPT_Pos (6U)
AnnaBridge 161:aa5281ff4a02 7691 #define FSMC_SR4_FEMPT_Msk (0x1U << FSMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7692 #define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk /*!<FIFO empty */
AnnaBridge 161:aa5281ff4a02 7693
AnnaBridge 161:aa5281ff4a02 7694 /****************** Bit definition for FSMC_PMEM2 register ******************/
AnnaBridge 161:aa5281ff4a02 7695 #define FSMC_PMEM2_MEMSET2_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7696 #define FSMC_PMEM2_MEMSET2_Msk (0xFFU << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 7697 #define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
AnnaBridge 161:aa5281ff4a02 7698 #define FSMC_PMEM2_MEMSET2_0 (0x01U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7699 #define FSMC_PMEM2_MEMSET2_1 (0x02U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7700 #define FSMC_PMEM2_MEMSET2_2 (0x04U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7701 #define FSMC_PMEM2_MEMSET2_3 (0x08U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7702 #define FSMC_PMEM2_MEMSET2_4 (0x10U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7703 #define FSMC_PMEM2_MEMSET2_5 (0x20U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7704 #define FSMC_PMEM2_MEMSET2_6 (0x40U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7705 #define FSMC_PMEM2_MEMSET2_7 (0x80U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7706
AnnaBridge 161:aa5281ff4a02 7707 #define FSMC_PMEM2_MEMWAIT2_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7708 #define FSMC_PMEM2_MEMWAIT2_Msk (0xFFU << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7709 #define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
AnnaBridge 161:aa5281ff4a02 7710 #define FSMC_PMEM2_MEMWAIT2_0 (0x01U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7711 #define FSMC_PMEM2_MEMWAIT2_1 (0x02U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7712 #define FSMC_PMEM2_MEMWAIT2_2 (0x04U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7713 #define FSMC_PMEM2_MEMWAIT2_3 (0x08U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7714 #define FSMC_PMEM2_MEMWAIT2_4 (0x10U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7715 #define FSMC_PMEM2_MEMWAIT2_5 (0x20U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7716 #define FSMC_PMEM2_MEMWAIT2_6 (0x40U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7717 #define FSMC_PMEM2_MEMWAIT2_7 (0x80U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7718
AnnaBridge 161:aa5281ff4a02 7719 #define FSMC_PMEM2_MEMHOLD2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7720 #define FSMC_PMEM2_MEMHOLD2_Msk (0xFFU << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 7721 #define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
AnnaBridge 161:aa5281ff4a02 7722 #define FSMC_PMEM2_MEMHOLD2_0 (0x01U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7723 #define FSMC_PMEM2_MEMHOLD2_1 (0x02U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7724 #define FSMC_PMEM2_MEMHOLD2_2 (0x04U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7725 #define FSMC_PMEM2_MEMHOLD2_3 (0x08U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7726 #define FSMC_PMEM2_MEMHOLD2_4 (0x10U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7727 #define FSMC_PMEM2_MEMHOLD2_5 (0x20U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7728 #define FSMC_PMEM2_MEMHOLD2_6 (0x40U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7729 #define FSMC_PMEM2_MEMHOLD2_7 (0x80U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7730
AnnaBridge 161:aa5281ff4a02 7731 #define FSMC_PMEM2_MEMHIZ2_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7732 #define FSMC_PMEM2_MEMHIZ2_Msk (0xFFU << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 7733 #define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
AnnaBridge 161:aa5281ff4a02 7734 #define FSMC_PMEM2_MEMHIZ2_0 (0x01U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7735 #define FSMC_PMEM2_MEMHIZ2_1 (0x02U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7736 #define FSMC_PMEM2_MEMHIZ2_2 (0x04U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7737 #define FSMC_PMEM2_MEMHIZ2_3 (0x08U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7738 #define FSMC_PMEM2_MEMHIZ2_4 (0x10U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7739 #define FSMC_PMEM2_MEMHIZ2_5 (0x20U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7740 #define FSMC_PMEM2_MEMHIZ2_6 (0x40U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 7741 #define FSMC_PMEM2_MEMHIZ2_7 (0x80U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 7742
AnnaBridge 161:aa5281ff4a02 7743 /****************** Bit definition for FSMC_PMEM3 register ******************/
AnnaBridge 161:aa5281ff4a02 7744 #define FSMC_PMEM3_MEMSET3_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7745 #define FSMC_PMEM3_MEMSET3_Msk (0xFFU << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 7746 #define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
AnnaBridge 161:aa5281ff4a02 7747 #define FSMC_PMEM3_MEMSET3_0 (0x01U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7748 #define FSMC_PMEM3_MEMSET3_1 (0x02U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7749 #define FSMC_PMEM3_MEMSET3_2 (0x04U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7750 #define FSMC_PMEM3_MEMSET3_3 (0x08U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7751 #define FSMC_PMEM3_MEMSET3_4 (0x10U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7752 #define FSMC_PMEM3_MEMSET3_5 (0x20U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7753 #define FSMC_PMEM3_MEMSET3_6 (0x40U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7754 #define FSMC_PMEM3_MEMSET3_7 (0x80U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7755
AnnaBridge 161:aa5281ff4a02 7756 #define FSMC_PMEM3_MEMWAIT3_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7757 #define FSMC_PMEM3_MEMWAIT3_Msk (0xFFU << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7758 #define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
AnnaBridge 161:aa5281ff4a02 7759 #define FSMC_PMEM3_MEMWAIT3_0 (0x01U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7760 #define FSMC_PMEM3_MEMWAIT3_1 (0x02U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7761 #define FSMC_PMEM3_MEMWAIT3_2 (0x04U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7762 #define FSMC_PMEM3_MEMWAIT3_3 (0x08U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7763 #define FSMC_PMEM3_MEMWAIT3_4 (0x10U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7764 #define FSMC_PMEM3_MEMWAIT3_5 (0x20U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7765 #define FSMC_PMEM3_MEMWAIT3_6 (0x40U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7766 #define FSMC_PMEM3_MEMWAIT3_7 (0x80U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7767
AnnaBridge 161:aa5281ff4a02 7768 #define FSMC_PMEM3_MEMHOLD3_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7769 #define FSMC_PMEM3_MEMHOLD3_Msk (0xFFU << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 7770 #define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
AnnaBridge 161:aa5281ff4a02 7771 #define FSMC_PMEM3_MEMHOLD3_0 (0x01U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7772 #define FSMC_PMEM3_MEMHOLD3_1 (0x02U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7773 #define FSMC_PMEM3_MEMHOLD3_2 (0x04U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7774 #define FSMC_PMEM3_MEMHOLD3_3 (0x08U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7775 #define FSMC_PMEM3_MEMHOLD3_4 (0x10U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7776 #define FSMC_PMEM3_MEMHOLD3_5 (0x20U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7777 #define FSMC_PMEM3_MEMHOLD3_6 (0x40U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7778 #define FSMC_PMEM3_MEMHOLD3_7 (0x80U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7779
AnnaBridge 161:aa5281ff4a02 7780 #define FSMC_PMEM3_MEMHIZ3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7781 #define FSMC_PMEM3_MEMHIZ3_Msk (0xFFU << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 7782 #define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
AnnaBridge 161:aa5281ff4a02 7783 #define FSMC_PMEM3_MEMHIZ3_0 (0x01U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7784 #define FSMC_PMEM3_MEMHIZ3_1 (0x02U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7785 #define FSMC_PMEM3_MEMHIZ3_2 (0x04U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7786 #define FSMC_PMEM3_MEMHIZ3_3 (0x08U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7787 #define FSMC_PMEM3_MEMHIZ3_4 (0x10U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7788 #define FSMC_PMEM3_MEMHIZ3_5 (0x20U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7789 #define FSMC_PMEM3_MEMHIZ3_6 (0x40U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 7790 #define FSMC_PMEM3_MEMHIZ3_7 (0x80U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 7791
AnnaBridge 161:aa5281ff4a02 7792 /****************** Bit definition for FSMC_PMEM4 register ******************/
AnnaBridge 161:aa5281ff4a02 7793 #define FSMC_PMEM4_MEMSET4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7794 #define FSMC_PMEM4_MEMSET4_Msk (0xFFU << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 7795 #define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
AnnaBridge 161:aa5281ff4a02 7796 #define FSMC_PMEM4_MEMSET4_0 (0x01U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7797 #define FSMC_PMEM4_MEMSET4_1 (0x02U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7798 #define FSMC_PMEM4_MEMSET4_2 (0x04U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7799 #define FSMC_PMEM4_MEMSET4_3 (0x08U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7800 #define FSMC_PMEM4_MEMSET4_4 (0x10U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7801 #define FSMC_PMEM4_MEMSET4_5 (0x20U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7802 #define FSMC_PMEM4_MEMSET4_6 (0x40U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7803 #define FSMC_PMEM4_MEMSET4_7 (0x80U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7804
AnnaBridge 161:aa5281ff4a02 7805 #define FSMC_PMEM4_MEMWAIT4_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7806 #define FSMC_PMEM4_MEMWAIT4_Msk (0xFFU << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7807 #define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
AnnaBridge 161:aa5281ff4a02 7808 #define FSMC_PMEM4_MEMWAIT4_0 (0x01U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7809 #define FSMC_PMEM4_MEMWAIT4_1 (0x02U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7810 #define FSMC_PMEM4_MEMWAIT4_2 (0x04U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7811 #define FSMC_PMEM4_MEMWAIT4_3 (0x08U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7812 #define FSMC_PMEM4_MEMWAIT4_4 (0x10U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7813 #define FSMC_PMEM4_MEMWAIT4_5 (0x20U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7814 #define FSMC_PMEM4_MEMWAIT4_6 (0x40U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7815 #define FSMC_PMEM4_MEMWAIT4_7 (0x80U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7816
AnnaBridge 161:aa5281ff4a02 7817 #define FSMC_PMEM4_MEMHOLD4_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7818 #define FSMC_PMEM4_MEMHOLD4_Msk (0xFFU << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 7819 #define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
AnnaBridge 161:aa5281ff4a02 7820 #define FSMC_PMEM4_MEMHOLD4_0 (0x01U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7821 #define FSMC_PMEM4_MEMHOLD4_1 (0x02U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7822 #define FSMC_PMEM4_MEMHOLD4_2 (0x04U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7823 #define FSMC_PMEM4_MEMHOLD4_3 (0x08U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7824 #define FSMC_PMEM4_MEMHOLD4_4 (0x10U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7825 #define FSMC_PMEM4_MEMHOLD4_5 (0x20U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7826 #define FSMC_PMEM4_MEMHOLD4_6 (0x40U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7827 #define FSMC_PMEM4_MEMHOLD4_7 (0x80U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7828
AnnaBridge 161:aa5281ff4a02 7829 #define FSMC_PMEM4_MEMHIZ4_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7830 #define FSMC_PMEM4_MEMHIZ4_Msk (0xFFU << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 7831 #define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
AnnaBridge 161:aa5281ff4a02 7832 #define FSMC_PMEM4_MEMHIZ4_0 (0x01U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7833 #define FSMC_PMEM4_MEMHIZ4_1 (0x02U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7834 #define FSMC_PMEM4_MEMHIZ4_2 (0x04U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7835 #define FSMC_PMEM4_MEMHIZ4_3 (0x08U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7836 #define FSMC_PMEM4_MEMHIZ4_4 (0x10U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7837 #define FSMC_PMEM4_MEMHIZ4_5 (0x20U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7838 #define FSMC_PMEM4_MEMHIZ4_6 (0x40U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 7839 #define FSMC_PMEM4_MEMHIZ4_7 (0x80U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 7840
AnnaBridge 161:aa5281ff4a02 7841 /****************** Bit definition for FSMC_PATT2 register ******************/
AnnaBridge 161:aa5281ff4a02 7842 #define FSMC_PATT2_ATTSET2_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7843 #define FSMC_PATT2_ATTSET2_Msk (0xFFU << FSMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 7844 #define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
AnnaBridge 161:aa5281ff4a02 7845 #define FSMC_PATT2_ATTSET2_0 (0x01U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7846 #define FSMC_PATT2_ATTSET2_1 (0x02U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7847 #define FSMC_PATT2_ATTSET2_2 (0x04U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7848 #define FSMC_PATT2_ATTSET2_3 (0x08U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7849 #define FSMC_PATT2_ATTSET2_4 (0x10U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7850 #define FSMC_PATT2_ATTSET2_5 (0x20U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7851 #define FSMC_PATT2_ATTSET2_6 (0x40U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7852 #define FSMC_PATT2_ATTSET2_7 (0x80U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7853
AnnaBridge 161:aa5281ff4a02 7854 #define FSMC_PATT2_ATTWAIT2_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7855 #define FSMC_PATT2_ATTWAIT2_Msk (0xFFU << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7856 #define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
AnnaBridge 161:aa5281ff4a02 7857 #define FSMC_PATT2_ATTWAIT2_0 (0x01U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7858 #define FSMC_PATT2_ATTWAIT2_1 (0x02U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7859 #define FSMC_PATT2_ATTWAIT2_2 (0x04U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7860 #define FSMC_PATT2_ATTWAIT2_3 (0x08U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7861 #define FSMC_PATT2_ATTWAIT2_4 (0x10U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7862 #define FSMC_PATT2_ATTWAIT2_5 (0x20U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7863 #define FSMC_PATT2_ATTWAIT2_6 (0x40U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7864 #define FSMC_PATT2_ATTWAIT2_7 (0x80U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7865
AnnaBridge 161:aa5281ff4a02 7866 #define FSMC_PATT2_ATTHOLD2_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7867 #define FSMC_PATT2_ATTHOLD2_Msk (0xFFU << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 7868 #define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
AnnaBridge 161:aa5281ff4a02 7869 #define FSMC_PATT2_ATTHOLD2_0 (0x01U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7870 #define FSMC_PATT2_ATTHOLD2_1 (0x02U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7871 #define FSMC_PATT2_ATTHOLD2_2 (0x04U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7872 #define FSMC_PATT2_ATTHOLD2_3 (0x08U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7873 #define FSMC_PATT2_ATTHOLD2_4 (0x10U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7874 #define FSMC_PATT2_ATTHOLD2_5 (0x20U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7875 #define FSMC_PATT2_ATTHOLD2_6 (0x40U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7876 #define FSMC_PATT2_ATTHOLD2_7 (0x80U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7877
AnnaBridge 161:aa5281ff4a02 7878 #define FSMC_PATT2_ATTHIZ2_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7879 #define FSMC_PATT2_ATTHIZ2_Msk (0xFFU << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 7880 #define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
AnnaBridge 161:aa5281ff4a02 7881 #define FSMC_PATT2_ATTHIZ2_0 (0x01U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7882 #define FSMC_PATT2_ATTHIZ2_1 (0x02U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7883 #define FSMC_PATT2_ATTHIZ2_2 (0x04U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7884 #define FSMC_PATT2_ATTHIZ2_3 (0x08U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7885 #define FSMC_PATT2_ATTHIZ2_4 (0x10U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7886 #define FSMC_PATT2_ATTHIZ2_5 (0x20U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7887 #define FSMC_PATT2_ATTHIZ2_6 (0x40U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 7888 #define FSMC_PATT2_ATTHIZ2_7 (0x80U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 7889
AnnaBridge 161:aa5281ff4a02 7890 /****************** Bit definition for FSMC_PATT3 register ******************/
AnnaBridge 161:aa5281ff4a02 7891 #define FSMC_PATT3_ATTSET3_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7892 #define FSMC_PATT3_ATTSET3_Msk (0xFFU << FSMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 7893 #define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
AnnaBridge 161:aa5281ff4a02 7894 #define FSMC_PATT3_ATTSET3_0 (0x01U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7895 #define FSMC_PATT3_ATTSET3_1 (0x02U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7896 #define FSMC_PATT3_ATTSET3_2 (0x04U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7897 #define FSMC_PATT3_ATTSET3_3 (0x08U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7898 #define FSMC_PATT3_ATTSET3_4 (0x10U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7899 #define FSMC_PATT3_ATTSET3_5 (0x20U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7900 #define FSMC_PATT3_ATTSET3_6 (0x40U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7901 #define FSMC_PATT3_ATTSET3_7 (0x80U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7902
AnnaBridge 161:aa5281ff4a02 7903 #define FSMC_PATT3_ATTWAIT3_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7904 #define FSMC_PATT3_ATTWAIT3_Msk (0xFFU << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7905 #define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
AnnaBridge 161:aa5281ff4a02 7906 #define FSMC_PATT3_ATTWAIT3_0 (0x01U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7907 #define FSMC_PATT3_ATTWAIT3_1 (0x02U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7908 #define FSMC_PATT3_ATTWAIT3_2 (0x04U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7909 #define FSMC_PATT3_ATTWAIT3_3 (0x08U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7910 #define FSMC_PATT3_ATTWAIT3_4 (0x10U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7911 #define FSMC_PATT3_ATTWAIT3_5 (0x20U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7912 #define FSMC_PATT3_ATTWAIT3_6 (0x40U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7913 #define FSMC_PATT3_ATTWAIT3_7 (0x80U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7914
AnnaBridge 161:aa5281ff4a02 7915 #define FSMC_PATT3_ATTHOLD3_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7916 #define FSMC_PATT3_ATTHOLD3_Msk (0xFFU << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 7917 #define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
AnnaBridge 161:aa5281ff4a02 7918 #define FSMC_PATT3_ATTHOLD3_0 (0x01U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7919 #define FSMC_PATT3_ATTHOLD3_1 (0x02U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7920 #define FSMC_PATT3_ATTHOLD3_2 (0x04U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7921 #define FSMC_PATT3_ATTHOLD3_3 (0x08U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7922 #define FSMC_PATT3_ATTHOLD3_4 (0x10U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7923 #define FSMC_PATT3_ATTHOLD3_5 (0x20U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7924 #define FSMC_PATT3_ATTHOLD3_6 (0x40U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7925 #define FSMC_PATT3_ATTHOLD3_7 (0x80U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7926
AnnaBridge 161:aa5281ff4a02 7927 #define FSMC_PATT3_ATTHIZ3_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7928 #define FSMC_PATT3_ATTHIZ3_Msk (0xFFU << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 7929 #define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
AnnaBridge 161:aa5281ff4a02 7930 #define FSMC_PATT3_ATTHIZ3_0 (0x01U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7931 #define FSMC_PATT3_ATTHIZ3_1 (0x02U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7932 #define FSMC_PATT3_ATTHIZ3_2 (0x04U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7933 #define FSMC_PATT3_ATTHIZ3_3 (0x08U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7934 #define FSMC_PATT3_ATTHIZ3_4 (0x10U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7935 #define FSMC_PATT3_ATTHIZ3_5 (0x20U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7936 #define FSMC_PATT3_ATTHIZ3_6 (0x40U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 7937 #define FSMC_PATT3_ATTHIZ3_7 (0x80U << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 7938
AnnaBridge 161:aa5281ff4a02 7939 /****************** Bit definition for FSMC_PATT4 register ******************/
AnnaBridge 161:aa5281ff4a02 7940 #define FSMC_PATT4_ATTSET4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7941 #define FSMC_PATT4_ATTSET4_Msk (0xFFU << FSMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 7942 #define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
AnnaBridge 161:aa5281ff4a02 7943 #define FSMC_PATT4_ATTSET4_0 (0x01U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7944 #define FSMC_PATT4_ATTSET4_1 (0x02U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7945 #define FSMC_PATT4_ATTSET4_2 (0x04U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7946 #define FSMC_PATT4_ATTSET4_3 (0x08U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7947 #define FSMC_PATT4_ATTSET4_4 (0x10U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7948 #define FSMC_PATT4_ATTSET4_5 (0x20U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7949 #define FSMC_PATT4_ATTSET4_6 (0x40U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7950 #define FSMC_PATT4_ATTSET4_7 (0x80U << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 7951
AnnaBridge 161:aa5281ff4a02 7952 #define FSMC_PATT4_ATTWAIT4_Pos (8U)
AnnaBridge 161:aa5281ff4a02 7953 #define FSMC_PATT4_ATTWAIT4_Msk (0xFFU << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 7954 #define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
AnnaBridge 161:aa5281ff4a02 7955 #define FSMC_PATT4_ATTWAIT4_0 (0x01U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 7956 #define FSMC_PATT4_ATTWAIT4_1 (0x02U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 7957 #define FSMC_PATT4_ATTWAIT4_2 (0x04U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 7958 #define FSMC_PATT4_ATTWAIT4_3 (0x08U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 7959 #define FSMC_PATT4_ATTWAIT4_4 (0x10U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 7960 #define FSMC_PATT4_ATTWAIT4_5 (0x20U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 7961 #define FSMC_PATT4_ATTWAIT4_6 (0x40U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 7962 #define FSMC_PATT4_ATTWAIT4_7 (0x80U << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 7963
AnnaBridge 161:aa5281ff4a02 7964 #define FSMC_PATT4_ATTHOLD4_Pos (16U)
AnnaBridge 161:aa5281ff4a02 7965 #define FSMC_PATT4_ATTHOLD4_Msk (0xFFU << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 7966 #define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
AnnaBridge 161:aa5281ff4a02 7967 #define FSMC_PATT4_ATTHOLD4_0 (0x01U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 7968 #define FSMC_PATT4_ATTHOLD4_1 (0x02U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 7969 #define FSMC_PATT4_ATTHOLD4_2 (0x04U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 7970 #define FSMC_PATT4_ATTHOLD4_3 (0x08U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 7971 #define FSMC_PATT4_ATTHOLD4_4 (0x10U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 7972 #define FSMC_PATT4_ATTHOLD4_5 (0x20U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 7973 #define FSMC_PATT4_ATTHOLD4_6 (0x40U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 7974 #define FSMC_PATT4_ATTHOLD4_7 (0x80U << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 7975
AnnaBridge 161:aa5281ff4a02 7976 #define FSMC_PATT4_ATTHIZ4_Pos (24U)
AnnaBridge 161:aa5281ff4a02 7977 #define FSMC_PATT4_ATTHIZ4_Msk (0xFFU << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 7978 #define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
AnnaBridge 161:aa5281ff4a02 7979 #define FSMC_PATT4_ATTHIZ4_0 (0x01U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 7980 #define FSMC_PATT4_ATTHIZ4_1 (0x02U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 7981 #define FSMC_PATT4_ATTHIZ4_2 (0x04U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 7982 #define FSMC_PATT4_ATTHIZ4_3 (0x08U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 7983 #define FSMC_PATT4_ATTHIZ4_4 (0x10U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 7984 #define FSMC_PATT4_ATTHIZ4_5 (0x20U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 7985 #define FSMC_PATT4_ATTHIZ4_6 (0x40U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 7986 #define FSMC_PATT4_ATTHIZ4_7 (0x80U << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 7987
AnnaBridge 161:aa5281ff4a02 7988 /****************** Bit definition for FSMC_PIO4 register *******************/
AnnaBridge 161:aa5281ff4a02 7989 #define FSMC_PIO4_IOSET4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 7990 #define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 7991 #define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
AnnaBridge 161:aa5281ff4a02 7992 #define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 7993 #define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 7994 #define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 7995 #define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 7996 #define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 7997 #define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 7998 #define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 7999 #define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8000
AnnaBridge 161:aa5281ff4a02 8001 #define FSMC_PIO4_IOWAIT4_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8002 #define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 8003 #define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
AnnaBridge 161:aa5281ff4a02 8004 #define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8005 #define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8006 #define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8007 #define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8008 #define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8009 #define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8010 #define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8011 #define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8012
AnnaBridge 161:aa5281ff4a02 8013 #define FSMC_PIO4_IOHOLD4_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8014 #define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 8015 #define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
AnnaBridge 161:aa5281ff4a02 8016 #define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8017 #define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 8018 #define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 8019 #define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 8020 #define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 8021 #define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 8022 #define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 8023 #define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 8024
AnnaBridge 161:aa5281ff4a02 8025 #define FSMC_PIO4_IOHIZ4_Pos (24U)
AnnaBridge 161:aa5281ff4a02 8026 #define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 8027 #define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
AnnaBridge 161:aa5281ff4a02 8028 #define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 8029 #define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 8030 #define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 8031 #define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 8032 #define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 8033 #define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 8034 #define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 8035 #define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 8036
AnnaBridge 161:aa5281ff4a02 8037 /****************** Bit definition for FSMC_ECCR2 register ******************/
AnnaBridge 161:aa5281ff4a02 8038 #define FSMC_ECCR2_ECC2_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8039 #define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 8040 #define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!<ECC result */
AnnaBridge 161:aa5281ff4a02 8041
AnnaBridge 161:aa5281ff4a02 8042 /****************** Bit definition for FSMC_ECCR3 register ******************/
AnnaBridge 161:aa5281ff4a02 8043 #define FSMC_ECCR3_ECC3_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8044 #define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 8045 #define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!<ECC result */
AnnaBridge 161:aa5281ff4a02 8046
AnnaBridge 161:aa5281ff4a02 8047 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 8048 /* */
AnnaBridge 161:aa5281ff4a02 8049 /* General Purpose I/O */
AnnaBridge 161:aa5281ff4a02 8050 /* */
AnnaBridge 161:aa5281ff4a02 8051 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 8052 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 161:aa5281ff4a02 8053 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8054 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 8055 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 161:aa5281ff4a02 8056 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8057 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8058 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8059 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 8060 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 161:aa5281ff4a02 8061 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8062 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8063 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8064 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 8065 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 161:aa5281ff4a02 8066 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8067 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8068 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8069 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 8070 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 161:aa5281ff4a02 8071 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8072 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8073 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8074 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 8075 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 161:aa5281ff4a02 8076 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8077 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8078 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8079 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 161:aa5281ff4a02 8080 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 161:aa5281ff4a02 8081 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8082 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8083 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8084 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 161:aa5281ff4a02 8085 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 161:aa5281ff4a02 8086 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8087 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8088 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8089 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 161:aa5281ff4a02 8090 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 161:aa5281ff4a02 8091 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8092 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8093 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8094 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 161:aa5281ff4a02 8095 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 161:aa5281ff4a02 8096 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8097 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 8098 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 161:aa5281ff4a02 8099 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 161:aa5281ff4a02 8100 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 161:aa5281ff4a02 8101 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 8102 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 8103 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 161:aa5281ff4a02 8104 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 8105 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 161:aa5281ff4a02 8106 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 8107 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 8108 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 161:aa5281ff4a02 8109 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 161:aa5281ff4a02 8110 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 161:aa5281ff4a02 8111 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 8112 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 8113 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 161:aa5281ff4a02 8114 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 161:aa5281ff4a02 8115 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 161:aa5281ff4a02 8116 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 8117 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 8118 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 161:aa5281ff4a02 8119 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 161:aa5281ff4a02 8120 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 161:aa5281ff4a02 8121 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 8122 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 8123 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 161:aa5281ff4a02 8124 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 8125 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 161:aa5281ff4a02 8126 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 8127 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 8128 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 161:aa5281ff4a02 8129 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 161:aa5281ff4a02 8130 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 161:aa5281ff4a02 8131 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 8132 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 8133
AnnaBridge 161:aa5281ff4a02 8134 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 8135 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8136 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 8137 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 161:aa5281ff4a02 8138 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8139 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8140 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8141 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 8142 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 161:aa5281ff4a02 8143 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8144 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8145 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8146 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 8147 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 161:aa5281ff4a02 8148 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8149 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8150 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8151 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 8152 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 161:aa5281ff4a02 8153 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8154 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8155 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8156 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 8157 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 161:aa5281ff4a02 8158 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8159 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8160 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8161 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 161:aa5281ff4a02 8162 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 161:aa5281ff4a02 8163 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8164 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8165 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8166 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 161:aa5281ff4a02 8167 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 161:aa5281ff4a02 8168 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8169 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8170 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8171 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 161:aa5281ff4a02 8172 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 161:aa5281ff4a02 8173 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8174 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8175 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8176 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 161:aa5281ff4a02 8177 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 161:aa5281ff4a02 8178 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8179 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 8180 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 161:aa5281ff4a02 8181 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 161:aa5281ff4a02 8182 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 161:aa5281ff4a02 8183 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 8184 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 8185 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 161:aa5281ff4a02 8186 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 8187 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 161:aa5281ff4a02 8188 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 8189 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 8190 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 161:aa5281ff4a02 8191 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 161:aa5281ff4a02 8192 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 161:aa5281ff4a02 8193 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 8194 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 8195 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 161:aa5281ff4a02 8196 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 161:aa5281ff4a02 8197 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 161:aa5281ff4a02 8198 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 8199 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 8200 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 161:aa5281ff4a02 8201 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 161:aa5281ff4a02 8202 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 161:aa5281ff4a02 8203 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 8204 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 8205 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 161:aa5281ff4a02 8206 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 8207 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 161:aa5281ff4a02 8208 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 8209 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 8210 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 161:aa5281ff4a02 8211 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 161:aa5281ff4a02 8212 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 161:aa5281ff4a02 8213 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 8214 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 8215
AnnaBridge 161:aa5281ff4a02 8216 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 161:aa5281ff4a02 8217 #define GPIO_OTYPER_OT0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8218 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8219 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
AnnaBridge 161:aa5281ff4a02 8220 #define GPIO_OTYPER_OT1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 8221 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8222 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
AnnaBridge 161:aa5281ff4a02 8223 #define GPIO_OTYPER_OT2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8224 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8225 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
AnnaBridge 161:aa5281ff4a02 8226 #define GPIO_OTYPER_OT3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 8227 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8228 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
AnnaBridge 161:aa5281ff4a02 8229 #define GPIO_OTYPER_OT4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8230 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8231 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
AnnaBridge 161:aa5281ff4a02 8232 #define GPIO_OTYPER_OT5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 8233 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8234 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
AnnaBridge 161:aa5281ff4a02 8235 #define GPIO_OTYPER_OT6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8236 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8237 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
AnnaBridge 161:aa5281ff4a02 8238 #define GPIO_OTYPER_OT7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 8239 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8240 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
AnnaBridge 161:aa5281ff4a02 8241 #define GPIO_OTYPER_OT8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8242 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8243 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
AnnaBridge 161:aa5281ff4a02 8244 #define GPIO_OTYPER_OT9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 8245 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8246 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
AnnaBridge 161:aa5281ff4a02 8247 #define GPIO_OTYPER_OT10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8248 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8249 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
AnnaBridge 161:aa5281ff4a02 8250 #define GPIO_OTYPER_OT11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 8251 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8252 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
AnnaBridge 161:aa5281ff4a02 8253 #define GPIO_OTYPER_OT12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8254 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8255 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
AnnaBridge 161:aa5281ff4a02 8256 #define GPIO_OTYPER_OT13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 8257 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8258 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
AnnaBridge 161:aa5281ff4a02 8259 #define GPIO_OTYPER_OT14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8260 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8261 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
AnnaBridge 161:aa5281ff4a02 8262 #define GPIO_OTYPER_OT15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 8263 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8264 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
AnnaBridge 161:aa5281ff4a02 8265
AnnaBridge 161:aa5281ff4a02 8266 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 8267 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
AnnaBridge 161:aa5281ff4a02 8268 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
AnnaBridge 161:aa5281ff4a02 8269 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
AnnaBridge 161:aa5281ff4a02 8270 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
AnnaBridge 161:aa5281ff4a02 8271 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
AnnaBridge 161:aa5281ff4a02 8272 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
AnnaBridge 161:aa5281ff4a02 8273 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
AnnaBridge 161:aa5281ff4a02 8274 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
AnnaBridge 161:aa5281ff4a02 8275 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
AnnaBridge 161:aa5281ff4a02 8276 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
AnnaBridge 161:aa5281ff4a02 8277 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
AnnaBridge 161:aa5281ff4a02 8278 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
AnnaBridge 161:aa5281ff4a02 8279 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
AnnaBridge 161:aa5281ff4a02 8280 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
AnnaBridge 161:aa5281ff4a02 8281 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
AnnaBridge 161:aa5281ff4a02 8282 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
AnnaBridge 161:aa5281ff4a02 8283
AnnaBridge 161:aa5281ff4a02 8284 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 161:aa5281ff4a02 8285 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8286 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 8287 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
AnnaBridge 161:aa5281ff4a02 8288 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8289 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8290 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8291 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 8292 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
AnnaBridge 161:aa5281ff4a02 8293 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8294 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8295 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8296 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 8297 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
AnnaBridge 161:aa5281ff4a02 8298 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8299 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8300 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8301 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 8302 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
AnnaBridge 161:aa5281ff4a02 8303 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8304 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8305 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8306 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 8307 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
AnnaBridge 161:aa5281ff4a02 8308 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8309 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8310 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8311 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 161:aa5281ff4a02 8312 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
AnnaBridge 161:aa5281ff4a02 8313 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8314 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8315 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8316 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 161:aa5281ff4a02 8317 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
AnnaBridge 161:aa5281ff4a02 8318 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8319 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8320 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8321 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 161:aa5281ff4a02 8322 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
AnnaBridge 161:aa5281ff4a02 8323 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8324 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8325 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8326 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 161:aa5281ff4a02 8327 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
AnnaBridge 161:aa5281ff4a02 8328 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8329 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 8330 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
AnnaBridge 161:aa5281ff4a02 8331 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 161:aa5281ff4a02 8332 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
AnnaBridge 161:aa5281ff4a02 8333 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 8334 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 8335 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
AnnaBridge 161:aa5281ff4a02 8336 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 8337 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
AnnaBridge 161:aa5281ff4a02 8338 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 8339 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 8340 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
AnnaBridge 161:aa5281ff4a02 8341 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 161:aa5281ff4a02 8342 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
AnnaBridge 161:aa5281ff4a02 8343 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 8344 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 8345 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
AnnaBridge 161:aa5281ff4a02 8346 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 161:aa5281ff4a02 8347 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
AnnaBridge 161:aa5281ff4a02 8348 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 8349 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 8350 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
AnnaBridge 161:aa5281ff4a02 8351 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 161:aa5281ff4a02 8352 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
AnnaBridge 161:aa5281ff4a02 8353 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 8354 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 8355 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
AnnaBridge 161:aa5281ff4a02 8356 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 8357 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
AnnaBridge 161:aa5281ff4a02 8358 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 8359 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 8360 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
AnnaBridge 161:aa5281ff4a02 8361 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 161:aa5281ff4a02 8362 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
AnnaBridge 161:aa5281ff4a02 8363 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 8364 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 8365
AnnaBridge 161:aa5281ff4a02 8366 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 8367 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
AnnaBridge 161:aa5281ff4a02 8368 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
AnnaBridge 161:aa5281ff4a02 8369 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
AnnaBridge 161:aa5281ff4a02 8370 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
AnnaBridge 161:aa5281ff4a02 8371 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
AnnaBridge 161:aa5281ff4a02 8372 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
AnnaBridge 161:aa5281ff4a02 8373 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
AnnaBridge 161:aa5281ff4a02 8374 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
AnnaBridge 161:aa5281ff4a02 8375 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
AnnaBridge 161:aa5281ff4a02 8376 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
AnnaBridge 161:aa5281ff4a02 8377 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
AnnaBridge 161:aa5281ff4a02 8378 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
AnnaBridge 161:aa5281ff4a02 8379 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
AnnaBridge 161:aa5281ff4a02 8380 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
AnnaBridge 161:aa5281ff4a02 8381 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
AnnaBridge 161:aa5281ff4a02 8382 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
AnnaBridge 161:aa5281ff4a02 8383 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
AnnaBridge 161:aa5281ff4a02 8384 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
AnnaBridge 161:aa5281ff4a02 8385 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
AnnaBridge 161:aa5281ff4a02 8386 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
AnnaBridge 161:aa5281ff4a02 8387 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
AnnaBridge 161:aa5281ff4a02 8388 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
AnnaBridge 161:aa5281ff4a02 8389 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
AnnaBridge 161:aa5281ff4a02 8390 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
AnnaBridge 161:aa5281ff4a02 8391 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
AnnaBridge 161:aa5281ff4a02 8392 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
AnnaBridge 161:aa5281ff4a02 8393 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
AnnaBridge 161:aa5281ff4a02 8394 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
AnnaBridge 161:aa5281ff4a02 8395 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
AnnaBridge 161:aa5281ff4a02 8396 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
AnnaBridge 161:aa5281ff4a02 8397 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
AnnaBridge 161:aa5281ff4a02 8398 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
AnnaBridge 161:aa5281ff4a02 8399 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
AnnaBridge 161:aa5281ff4a02 8400 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
AnnaBridge 161:aa5281ff4a02 8401 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
AnnaBridge 161:aa5281ff4a02 8402 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
AnnaBridge 161:aa5281ff4a02 8403 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
AnnaBridge 161:aa5281ff4a02 8404 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
AnnaBridge 161:aa5281ff4a02 8405 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
AnnaBridge 161:aa5281ff4a02 8406 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
AnnaBridge 161:aa5281ff4a02 8407 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
AnnaBridge 161:aa5281ff4a02 8408 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
AnnaBridge 161:aa5281ff4a02 8409 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
AnnaBridge 161:aa5281ff4a02 8410 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
AnnaBridge 161:aa5281ff4a02 8411 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
AnnaBridge 161:aa5281ff4a02 8412 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
AnnaBridge 161:aa5281ff4a02 8413 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
AnnaBridge 161:aa5281ff4a02 8414 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
AnnaBridge 161:aa5281ff4a02 8415
AnnaBridge 161:aa5281ff4a02 8416 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 161:aa5281ff4a02 8417 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8418 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 8419 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 161:aa5281ff4a02 8420 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8421 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8422 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8423 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 8424 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 161:aa5281ff4a02 8425 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8426 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8427 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8428 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 8429 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 161:aa5281ff4a02 8430 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8431 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8432 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8433 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 8434 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 161:aa5281ff4a02 8435 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8436 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8437 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8438 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 8439 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 161:aa5281ff4a02 8440 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8441 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8442 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8443 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 161:aa5281ff4a02 8444 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 161:aa5281ff4a02 8445 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8446 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8447 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8448 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 161:aa5281ff4a02 8449 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 161:aa5281ff4a02 8450 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8451 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8452 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8453 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 161:aa5281ff4a02 8454 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 161:aa5281ff4a02 8455 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8456 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8457 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8458 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 161:aa5281ff4a02 8459 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 161:aa5281ff4a02 8460 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8461 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 8462 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 161:aa5281ff4a02 8463 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 161:aa5281ff4a02 8464 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 161:aa5281ff4a02 8465 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 8466 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 8467 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 161:aa5281ff4a02 8468 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 8469 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 161:aa5281ff4a02 8470 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 8471 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 8472 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 161:aa5281ff4a02 8473 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 161:aa5281ff4a02 8474 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 161:aa5281ff4a02 8475 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 8476 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 8477 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 161:aa5281ff4a02 8478 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 161:aa5281ff4a02 8479 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 161:aa5281ff4a02 8480 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 8481 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 8482 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 161:aa5281ff4a02 8483 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 161:aa5281ff4a02 8484 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 161:aa5281ff4a02 8485 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 8486 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 8487 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 161:aa5281ff4a02 8488 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 8489 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 161:aa5281ff4a02 8490 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 8491 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 8492 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 161:aa5281ff4a02 8493 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 161:aa5281ff4a02 8494 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 161:aa5281ff4a02 8495 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 8496 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 8497
AnnaBridge 161:aa5281ff4a02 8498 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 8499 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
AnnaBridge 161:aa5281ff4a02 8500 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
AnnaBridge 161:aa5281ff4a02 8501 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
AnnaBridge 161:aa5281ff4a02 8502 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
AnnaBridge 161:aa5281ff4a02 8503 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
AnnaBridge 161:aa5281ff4a02 8504 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
AnnaBridge 161:aa5281ff4a02 8505 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
AnnaBridge 161:aa5281ff4a02 8506 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
AnnaBridge 161:aa5281ff4a02 8507 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
AnnaBridge 161:aa5281ff4a02 8508 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
AnnaBridge 161:aa5281ff4a02 8509 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
AnnaBridge 161:aa5281ff4a02 8510 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
AnnaBridge 161:aa5281ff4a02 8511 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
AnnaBridge 161:aa5281ff4a02 8512 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
AnnaBridge 161:aa5281ff4a02 8513 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
AnnaBridge 161:aa5281ff4a02 8514 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
AnnaBridge 161:aa5281ff4a02 8515 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
AnnaBridge 161:aa5281ff4a02 8516 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
AnnaBridge 161:aa5281ff4a02 8517 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
AnnaBridge 161:aa5281ff4a02 8518 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
AnnaBridge 161:aa5281ff4a02 8519 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
AnnaBridge 161:aa5281ff4a02 8520 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
AnnaBridge 161:aa5281ff4a02 8521 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
AnnaBridge 161:aa5281ff4a02 8522 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
AnnaBridge 161:aa5281ff4a02 8523 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
AnnaBridge 161:aa5281ff4a02 8524 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
AnnaBridge 161:aa5281ff4a02 8525 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
AnnaBridge 161:aa5281ff4a02 8526 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
AnnaBridge 161:aa5281ff4a02 8527 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
AnnaBridge 161:aa5281ff4a02 8528 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
AnnaBridge 161:aa5281ff4a02 8529 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
AnnaBridge 161:aa5281ff4a02 8530 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
AnnaBridge 161:aa5281ff4a02 8531 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
AnnaBridge 161:aa5281ff4a02 8532 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
AnnaBridge 161:aa5281ff4a02 8533 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
AnnaBridge 161:aa5281ff4a02 8534 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
AnnaBridge 161:aa5281ff4a02 8535 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
AnnaBridge 161:aa5281ff4a02 8536 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
AnnaBridge 161:aa5281ff4a02 8537 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
AnnaBridge 161:aa5281ff4a02 8538 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
AnnaBridge 161:aa5281ff4a02 8539 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
AnnaBridge 161:aa5281ff4a02 8540 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
AnnaBridge 161:aa5281ff4a02 8541 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
AnnaBridge 161:aa5281ff4a02 8542 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
AnnaBridge 161:aa5281ff4a02 8543 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
AnnaBridge 161:aa5281ff4a02 8544 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
AnnaBridge 161:aa5281ff4a02 8545 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
AnnaBridge 161:aa5281ff4a02 8546 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
AnnaBridge 161:aa5281ff4a02 8547
AnnaBridge 161:aa5281ff4a02 8548 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 161:aa5281ff4a02 8549 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8550 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8551 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 161:aa5281ff4a02 8552 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 8553 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8554 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 161:aa5281ff4a02 8555 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8556 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8557 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 161:aa5281ff4a02 8558 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 8559 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8560 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 161:aa5281ff4a02 8561 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8562 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8563 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 161:aa5281ff4a02 8564 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 8565 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8566 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 161:aa5281ff4a02 8567 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8568 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8569 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 161:aa5281ff4a02 8570 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 8571 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8572 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 161:aa5281ff4a02 8573 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8574 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8575 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 161:aa5281ff4a02 8576 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 8577 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8578 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 161:aa5281ff4a02 8579 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8580 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8581 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 161:aa5281ff4a02 8582 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 8583 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8584 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 161:aa5281ff4a02 8585 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8586 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8587 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 161:aa5281ff4a02 8588 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 8589 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8590 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 161:aa5281ff4a02 8591 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8592 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8593 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 161:aa5281ff4a02 8594 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 8595 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8596 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 161:aa5281ff4a02 8597
AnnaBridge 161:aa5281ff4a02 8598 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 8599 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
AnnaBridge 161:aa5281ff4a02 8600 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
AnnaBridge 161:aa5281ff4a02 8601 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
AnnaBridge 161:aa5281ff4a02 8602 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
AnnaBridge 161:aa5281ff4a02 8603 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
AnnaBridge 161:aa5281ff4a02 8604 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
AnnaBridge 161:aa5281ff4a02 8605 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
AnnaBridge 161:aa5281ff4a02 8606 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
AnnaBridge 161:aa5281ff4a02 8607 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
AnnaBridge 161:aa5281ff4a02 8608 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
AnnaBridge 161:aa5281ff4a02 8609 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
AnnaBridge 161:aa5281ff4a02 8610 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
AnnaBridge 161:aa5281ff4a02 8611 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
AnnaBridge 161:aa5281ff4a02 8612 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
AnnaBridge 161:aa5281ff4a02 8613 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
AnnaBridge 161:aa5281ff4a02 8614 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
AnnaBridge 161:aa5281ff4a02 8615
AnnaBridge 161:aa5281ff4a02 8616 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 161:aa5281ff4a02 8617 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8618 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8619 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 161:aa5281ff4a02 8620 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 8621 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8622 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 161:aa5281ff4a02 8623 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8624 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8625 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 161:aa5281ff4a02 8626 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 8627 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8628 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 161:aa5281ff4a02 8629 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8630 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8631 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 161:aa5281ff4a02 8632 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 8633 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8634 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 161:aa5281ff4a02 8635 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8636 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8637 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 161:aa5281ff4a02 8638 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 8639 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8640 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 161:aa5281ff4a02 8641 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8642 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8643 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 161:aa5281ff4a02 8644 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 8645 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8646 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 161:aa5281ff4a02 8647 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8648 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8649 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 161:aa5281ff4a02 8650 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 8651 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8652 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 161:aa5281ff4a02 8653 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8654 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8655 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 161:aa5281ff4a02 8656 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 8657 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8658 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 161:aa5281ff4a02 8659 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8660 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8661 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 161:aa5281ff4a02 8662 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 8663 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8664 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 161:aa5281ff4a02 8665 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 8666 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
AnnaBridge 161:aa5281ff4a02 8667 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
AnnaBridge 161:aa5281ff4a02 8668 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
AnnaBridge 161:aa5281ff4a02 8669 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
AnnaBridge 161:aa5281ff4a02 8670 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
AnnaBridge 161:aa5281ff4a02 8671 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
AnnaBridge 161:aa5281ff4a02 8672 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
AnnaBridge 161:aa5281ff4a02 8673 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
AnnaBridge 161:aa5281ff4a02 8674 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
AnnaBridge 161:aa5281ff4a02 8675 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
AnnaBridge 161:aa5281ff4a02 8676 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
AnnaBridge 161:aa5281ff4a02 8677 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
AnnaBridge 161:aa5281ff4a02 8678 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
AnnaBridge 161:aa5281ff4a02 8679 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
AnnaBridge 161:aa5281ff4a02 8680 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
AnnaBridge 161:aa5281ff4a02 8681 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
AnnaBridge 161:aa5281ff4a02 8682
AnnaBridge 161:aa5281ff4a02 8683 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 161:aa5281ff4a02 8684 #define GPIO_BSRR_BS0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8685 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8686 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
AnnaBridge 161:aa5281ff4a02 8687 #define GPIO_BSRR_BS1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 8688 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8689 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
AnnaBridge 161:aa5281ff4a02 8690 #define GPIO_BSRR_BS2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8691 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8692 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
AnnaBridge 161:aa5281ff4a02 8693 #define GPIO_BSRR_BS3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 8694 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8695 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
AnnaBridge 161:aa5281ff4a02 8696 #define GPIO_BSRR_BS4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8697 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8698 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
AnnaBridge 161:aa5281ff4a02 8699 #define GPIO_BSRR_BS5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 8700 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8701 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
AnnaBridge 161:aa5281ff4a02 8702 #define GPIO_BSRR_BS6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8703 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8704 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
AnnaBridge 161:aa5281ff4a02 8705 #define GPIO_BSRR_BS7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 8706 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8707 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
AnnaBridge 161:aa5281ff4a02 8708 #define GPIO_BSRR_BS8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8709 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8710 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
AnnaBridge 161:aa5281ff4a02 8711 #define GPIO_BSRR_BS9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 8712 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8713 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
AnnaBridge 161:aa5281ff4a02 8714 #define GPIO_BSRR_BS10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8715 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8716 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
AnnaBridge 161:aa5281ff4a02 8717 #define GPIO_BSRR_BS11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 8718 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8719 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
AnnaBridge 161:aa5281ff4a02 8720 #define GPIO_BSRR_BS12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8721 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8722 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
AnnaBridge 161:aa5281ff4a02 8723 #define GPIO_BSRR_BS13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 8724 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8725 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
AnnaBridge 161:aa5281ff4a02 8726 #define GPIO_BSRR_BS14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8727 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8728 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
AnnaBridge 161:aa5281ff4a02 8729 #define GPIO_BSRR_BS15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 8730 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8731 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
AnnaBridge 161:aa5281ff4a02 8732 #define GPIO_BSRR_BR0_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8733 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8734 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
AnnaBridge 161:aa5281ff4a02 8735 #define GPIO_BSRR_BR1_Pos (17U)
AnnaBridge 161:aa5281ff4a02 8736 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 8737 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
AnnaBridge 161:aa5281ff4a02 8738 #define GPIO_BSRR_BR2_Pos (18U)
AnnaBridge 161:aa5281ff4a02 8739 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 8740 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
AnnaBridge 161:aa5281ff4a02 8741 #define GPIO_BSRR_BR3_Pos (19U)
AnnaBridge 161:aa5281ff4a02 8742 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 8743 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
AnnaBridge 161:aa5281ff4a02 8744 #define GPIO_BSRR_BR4_Pos (20U)
AnnaBridge 161:aa5281ff4a02 8745 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 8746 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
AnnaBridge 161:aa5281ff4a02 8747 #define GPIO_BSRR_BR5_Pos (21U)
AnnaBridge 161:aa5281ff4a02 8748 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 8749 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
AnnaBridge 161:aa5281ff4a02 8750 #define GPIO_BSRR_BR6_Pos (22U)
AnnaBridge 161:aa5281ff4a02 8751 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 8752 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
AnnaBridge 161:aa5281ff4a02 8753 #define GPIO_BSRR_BR7_Pos (23U)
AnnaBridge 161:aa5281ff4a02 8754 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 8755 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
AnnaBridge 161:aa5281ff4a02 8756 #define GPIO_BSRR_BR8_Pos (24U)
AnnaBridge 161:aa5281ff4a02 8757 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 8758 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
AnnaBridge 161:aa5281ff4a02 8759 #define GPIO_BSRR_BR9_Pos (25U)
AnnaBridge 161:aa5281ff4a02 8760 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 8761 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
AnnaBridge 161:aa5281ff4a02 8762 #define GPIO_BSRR_BR10_Pos (26U)
AnnaBridge 161:aa5281ff4a02 8763 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 8764 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
AnnaBridge 161:aa5281ff4a02 8765 #define GPIO_BSRR_BR11_Pos (27U)
AnnaBridge 161:aa5281ff4a02 8766 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 8767 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
AnnaBridge 161:aa5281ff4a02 8768 #define GPIO_BSRR_BR12_Pos (28U)
AnnaBridge 161:aa5281ff4a02 8769 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 8770 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
AnnaBridge 161:aa5281ff4a02 8771 #define GPIO_BSRR_BR13_Pos (29U)
AnnaBridge 161:aa5281ff4a02 8772 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 8773 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
AnnaBridge 161:aa5281ff4a02 8774 #define GPIO_BSRR_BR14_Pos (30U)
AnnaBridge 161:aa5281ff4a02 8775 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 8776 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
AnnaBridge 161:aa5281ff4a02 8777 #define GPIO_BSRR_BR15_Pos (31U)
AnnaBridge 161:aa5281ff4a02 8778 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 8779 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
AnnaBridge 161:aa5281ff4a02 8780
AnnaBridge 161:aa5281ff4a02 8781 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 8782 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
AnnaBridge 161:aa5281ff4a02 8783 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
AnnaBridge 161:aa5281ff4a02 8784 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
AnnaBridge 161:aa5281ff4a02 8785 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
AnnaBridge 161:aa5281ff4a02 8786 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
AnnaBridge 161:aa5281ff4a02 8787 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
AnnaBridge 161:aa5281ff4a02 8788 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
AnnaBridge 161:aa5281ff4a02 8789 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
AnnaBridge 161:aa5281ff4a02 8790 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
AnnaBridge 161:aa5281ff4a02 8791 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
AnnaBridge 161:aa5281ff4a02 8792 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
AnnaBridge 161:aa5281ff4a02 8793 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
AnnaBridge 161:aa5281ff4a02 8794 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
AnnaBridge 161:aa5281ff4a02 8795 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
AnnaBridge 161:aa5281ff4a02 8796 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
AnnaBridge 161:aa5281ff4a02 8797 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
AnnaBridge 161:aa5281ff4a02 8798 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
AnnaBridge 161:aa5281ff4a02 8799 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
AnnaBridge 161:aa5281ff4a02 8800 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
AnnaBridge 161:aa5281ff4a02 8801 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
AnnaBridge 161:aa5281ff4a02 8802 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
AnnaBridge 161:aa5281ff4a02 8803 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
AnnaBridge 161:aa5281ff4a02 8804 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
AnnaBridge 161:aa5281ff4a02 8805 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
AnnaBridge 161:aa5281ff4a02 8806 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
AnnaBridge 161:aa5281ff4a02 8807 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
AnnaBridge 161:aa5281ff4a02 8808 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
AnnaBridge 161:aa5281ff4a02 8809 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
AnnaBridge 161:aa5281ff4a02 8810 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
AnnaBridge 161:aa5281ff4a02 8811 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
AnnaBridge 161:aa5281ff4a02 8812 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
AnnaBridge 161:aa5281ff4a02 8813 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
AnnaBridge 161:aa5281ff4a02 8814 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 161:aa5281ff4a02 8815 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8816 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8817 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 161:aa5281ff4a02 8818 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 8819 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8820 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 161:aa5281ff4a02 8821 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 8822 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8823 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 161:aa5281ff4a02 8824 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 8825 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8826 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 161:aa5281ff4a02 8827 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8828 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8829 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 161:aa5281ff4a02 8830 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 8831 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8832 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 161:aa5281ff4a02 8833 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 8834 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8835 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 161:aa5281ff4a02 8836 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 8837 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8838 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 161:aa5281ff4a02 8839 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8840 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8841 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 161:aa5281ff4a02 8842 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 8843 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8844 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 161:aa5281ff4a02 8845 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 8846 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8847 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 161:aa5281ff4a02 8848 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 8849 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8850 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 161:aa5281ff4a02 8851 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8852 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8853 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 161:aa5281ff4a02 8854 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 8855 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8856 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 161:aa5281ff4a02 8857 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 8858 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8859 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 161:aa5281ff4a02 8860 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 8861 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8862 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 161:aa5281ff4a02 8863 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8864 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8865 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 161:aa5281ff4a02 8866 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 161:aa5281ff4a02 8867 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8868 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 8869 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 161:aa5281ff4a02 8870 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8871 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8872 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8873 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8874 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8875 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 8876 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 161:aa5281ff4a02 8877 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8878 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8879 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8880 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8881 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8882 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 8883 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 161:aa5281ff4a02 8884 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8885 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8886 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8887 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8888 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8889 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 161:aa5281ff4a02 8890 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 161:aa5281ff4a02 8891 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8892 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8893 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8894 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8895 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8896 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 8897 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 161:aa5281ff4a02 8898 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8899 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 8900 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 8901 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 8902 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 161:aa5281ff4a02 8903 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 161:aa5281ff4a02 8904 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 161:aa5281ff4a02 8905 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 8906 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 8907 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 8908 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 8909 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 161:aa5281ff4a02 8910 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 8911 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 161:aa5281ff4a02 8912 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 8913 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 8914 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 8915 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 8916 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 161:aa5281ff4a02 8917 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 161:aa5281ff4a02 8918 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 161:aa5281ff4a02 8919 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 8920 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 8921 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 8922 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 8923
AnnaBridge 161:aa5281ff4a02 8924 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 8925 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 161:aa5281ff4a02 8926 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
AnnaBridge 161:aa5281ff4a02 8927 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
AnnaBridge 161:aa5281ff4a02 8928 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
AnnaBridge 161:aa5281ff4a02 8929 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
AnnaBridge 161:aa5281ff4a02 8930 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 161:aa5281ff4a02 8931 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
AnnaBridge 161:aa5281ff4a02 8932 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
AnnaBridge 161:aa5281ff4a02 8933 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
AnnaBridge 161:aa5281ff4a02 8934 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
AnnaBridge 161:aa5281ff4a02 8935 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 161:aa5281ff4a02 8936 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
AnnaBridge 161:aa5281ff4a02 8937 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
AnnaBridge 161:aa5281ff4a02 8938 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
AnnaBridge 161:aa5281ff4a02 8939 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
AnnaBridge 161:aa5281ff4a02 8940 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 161:aa5281ff4a02 8941 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
AnnaBridge 161:aa5281ff4a02 8942 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
AnnaBridge 161:aa5281ff4a02 8943 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
AnnaBridge 161:aa5281ff4a02 8944 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
AnnaBridge 161:aa5281ff4a02 8945 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 161:aa5281ff4a02 8946 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
AnnaBridge 161:aa5281ff4a02 8947 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
AnnaBridge 161:aa5281ff4a02 8948 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
AnnaBridge 161:aa5281ff4a02 8949 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
AnnaBridge 161:aa5281ff4a02 8950 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 161:aa5281ff4a02 8951 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
AnnaBridge 161:aa5281ff4a02 8952 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
AnnaBridge 161:aa5281ff4a02 8953 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
AnnaBridge 161:aa5281ff4a02 8954 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
AnnaBridge 161:aa5281ff4a02 8955 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 161:aa5281ff4a02 8956 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
AnnaBridge 161:aa5281ff4a02 8957 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
AnnaBridge 161:aa5281ff4a02 8958 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
AnnaBridge 161:aa5281ff4a02 8959 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
AnnaBridge 161:aa5281ff4a02 8960 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 161:aa5281ff4a02 8961 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
AnnaBridge 161:aa5281ff4a02 8962 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
AnnaBridge 161:aa5281ff4a02 8963 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
AnnaBridge 161:aa5281ff4a02 8964 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
AnnaBridge 161:aa5281ff4a02 8965
AnnaBridge 161:aa5281ff4a02 8966 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 161:aa5281ff4a02 8967 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 161:aa5281ff4a02 8968 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 8969 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 161:aa5281ff4a02 8970 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 8971 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 8972 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 8973 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 8974 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 161:aa5281ff4a02 8975 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 8976 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 161:aa5281ff4a02 8977 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 8978 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 8979 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 8980 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 8981 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 161:aa5281ff4a02 8982 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 8983 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 161:aa5281ff4a02 8984 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 8985 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 8986 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 8987 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 8988 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 161:aa5281ff4a02 8989 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 161:aa5281ff4a02 8990 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 161:aa5281ff4a02 8991 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 8992 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 8993 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 8994 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 8995 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 161:aa5281ff4a02 8996 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 8997 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 161:aa5281ff4a02 8998 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 8999 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 9000 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 9001 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 9002 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 161:aa5281ff4a02 9003 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 161:aa5281ff4a02 9004 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 161:aa5281ff4a02 9005 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 9006 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 9007 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 9008 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 9009 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 161:aa5281ff4a02 9010 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 9011 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 161:aa5281ff4a02 9012 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 9013 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 9014 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 9015 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 9016 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 161:aa5281ff4a02 9017 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 161:aa5281ff4a02 9018 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 161:aa5281ff4a02 9019 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 9020 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 9021 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 9022 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 9023
AnnaBridge 161:aa5281ff4a02 9024 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 9025 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 161:aa5281ff4a02 9026 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
AnnaBridge 161:aa5281ff4a02 9027 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
AnnaBridge 161:aa5281ff4a02 9028 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
AnnaBridge 161:aa5281ff4a02 9029 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
AnnaBridge 161:aa5281ff4a02 9030 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 161:aa5281ff4a02 9031 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
AnnaBridge 161:aa5281ff4a02 9032 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
AnnaBridge 161:aa5281ff4a02 9033 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
AnnaBridge 161:aa5281ff4a02 9034 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
AnnaBridge 161:aa5281ff4a02 9035 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 161:aa5281ff4a02 9036 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
AnnaBridge 161:aa5281ff4a02 9037 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
AnnaBridge 161:aa5281ff4a02 9038 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
AnnaBridge 161:aa5281ff4a02 9039 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
AnnaBridge 161:aa5281ff4a02 9040 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 161:aa5281ff4a02 9041 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
AnnaBridge 161:aa5281ff4a02 9042 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
AnnaBridge 161:aa5281ff4a02 9043 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
AnnaBridge 161:aa5281ff4a02 9044 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
AnnaBridge 161:aa5281ff4a02 9045 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 161:aa5281ff4a02 9046 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
AnnaBridge 161:aa5281ff4a02 9047 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
AnnaBridge 161:aa5281ff4a02 9048 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
AnnaBridge 161:aa5281ff4a02 9049 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
AnnaBridge 161:aa5281ff4a02 9050 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 161:aa5281ff4a02 9051 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
AnnaBridge 161:aa5281ff4a02 9052 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
AnnaBridge 161:aa5281ff4a02 9053 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
AnnaBridge 161:aa5281ff4a02 9054 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
AnnaBridge 161:aa5281ff4a02 9055 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 161:aa5281ff4a02 9056 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
AnnaBridge 161:aa5281ff4a02 9057 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
AnnaBridge 161:aa5281ff4a02 9058 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
AnnaBridge 161:aa5281ff4a02 9059 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
AnnaBridge 161:aa5281ff4a02 9060 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 161:aa5281ff4a02 9061 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
AnnaBridge 161:aa5281ff4a02 9062 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
AnnaBridge 161:aa5281ff4a02 9063 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
AnnaBridge 161:aa5281ff4a02 9064 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
AnnaBridge 161:aa5281ff4a02 9065
AnnaBridge 161:aa5281ff4a02 9066 /****************** Bits definition for GPIO_BRR register ******************/
AnnaBridge 161:aa5281ff4a02 9067 #define GPIO_BRR_BR0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9068 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9069 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
AnnaBridge 161:aa5281ff4a02 9070 #define GPIO_BRR_BR1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9071 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9072 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
AnnaBridge 161:aa5281ff4a02 9073 #define GPIO_BRR_BR2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9074 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9075 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
AnnaBridge 161:aa5281ff4a02 9076 #define GPIO_BRR_BR3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9077 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9078 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
AnnaBridge 161:aa5281ff4a02 9079 #define GPIO_BRR_BR4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9080 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9081 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
AnnaBridge 161:aa5281ff4a02 9082 #define GPIO_BRR_BR5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9083 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9084 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
AnnaBridge 161:aa5281ff4a02 9085 #define GPIO_BRR_BR6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9086 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9087 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
AnnaBridge 161:aa5281ff4a02 9088 #define GPIO_BRR_BR7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9089 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9090 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
AnnaBridge 161:aa5281ff4a02 9091 #define GPIO_BRR_BR8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9092 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9093 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
AnnaBridge 161:aa5281ff4a02 9094 #define GPIO_BRR_BR9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 9095 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9096 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
AnnaBridge 161:aa5281ff4a02 9097 #define GPIO_BRR_BR10_Pos (10U)
AnnaBridge 161:aa5281ff4a02 9098 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 9099 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
AnnaBridge 161:aa5281ff4a02 9100 #define GPIO_BRR_BR11_Pos (11U)
AnnaBridge 161:aa5281ff4a02 9101 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9102 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
AnnaBridge 161:aa5281ff4a02 9103 #define GPIO_BRR_BR12_Pos (12U)
AnnaBridge 161:aa5281ff4a02 9104 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9105 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
AnnaBridge 161:aa5281ff4a02 9106 #define GPIO_BRR_BR13_Pos (13U)
AnnaBridge 161:aa5281ff4a02 9107 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 9108 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
AnnaBridge 161:aa5281ff4a02 9109 #define GPIO_BRR_BR14_Pos (14U)
AnnaBridge 161:aa5281ff4a02 9110 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9111 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
AnnaBridge 161:aa5281ff4a02 9112 #define GPIO_BRR_BR15_Pos (15U)
AnnaBridge 161:aa5281ff4a02 9113 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 9114 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
AnnaBridge 161:aa5281ff4a02 9115
AnnaBridge 161:aa5281ff4a02 9116
AnnaBridge 161:aa5281ff4a02 9117 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 9118 /* */
AnnaBridge 161:aa5281ff4a02 9119 /* Inter-integrated Circuit Interface */
AnnaBridge 161:aa5281ff4a02 9120 /* */
AnnaBridge 161:aa5281ff4a02 9121 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 9122 /******************* Bit definition for I2C_CR1 register ********************/
AnnaBridge 161:aa5281ff4a02 9123 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9124 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9125 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
AnnaBridge 161:aa5281ff4a02 9126 #define I2C_CR1_SMBUS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9127 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9128 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
AnnaBridge 161:aa5281ff4a02 9129 #define I2C_CR1_SMBTYPE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9130 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9131 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
AnnaBridge 161:aa5281ff4a02 9132 #define I2C_CR1_ENARP_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9133 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9134 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
AnnaBridge 161:aa5281ff4a02 9135 #define I2C_CR1_ENPEC_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9136 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9137 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
AnnaBridge 161:aa5281ff4a02 9138 #define I2C_CR1_ENGC_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9139 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9140 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
AnnaBridge 161:aa5281ff4a02 9141 #define I2C_CR1_NOSTRETCH_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9142 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9143 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
AnnaBridge 161:aa5281ff4a02 9144 #define I2C_CR1_START_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9145 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9146 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
AnnaBridge 161:aa5281ff4a02 9147 #define I2C_CR1_STOP_Pos (9U)
AnnaBridge 161:aa5281ff4a02 9148 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9149 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
AnnaBridge 161:aa5281ff4a02 9150 #define I2C_CR1_ACK_Pos (10U)
AnnaBridge 161:aa5281ff4a02 9151 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 9152 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
AnnaBridge 161:aa5281ff4a02 9153 #define I2C_CR1_POS_Pos (11U)
AnnaBridge 161:aa5281ff4a02 9154 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9155 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
AnnaBridge 161:aa5281ff4a02 9156 #define I2C_CR1_PEC_Pos (12U)
AnnaBridge 161:aa5281ff4a02 9157 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9158 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
AnnaBridge 161:aa5281ff4a02 9159 #define I2C_CR1_ALERT_Pos (13U)
AnnaBridge 161:aa5281ff4a02 9160 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 9161 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
AnnaBridge 161:aa5281ff4a02 9162 #define I2C_CR1_SWRST_Pos (15U)
AnnaBridge 161:aa5281ff4a02 9163 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 9164 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
AnnaBridge 161:aa5281ff4a02 9165
AnnaBridge 161:aa5281ff4a02 9166 /******************* Bit definition for I2C_CR2 register ********************/
AnnaBridge 161:aa5281ff4a02 9167 #define I2C_CR2_FREQ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9168 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
AnnaBridge 161:aa5281ff4a02 9169 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
AnnaBridge 161:aa5281ff4a02 9170 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9171 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9172 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9173 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9174 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9175 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9176
AnnaBridge 161:aa5281ff4a02 9177 #define I2C_CR2_ITERREN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9178 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9179 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 9180 #define I2C_CR2_ITEVTEN_Pos (9U)
AnnaBridge 161:aa5281ff4a02 9181 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9182 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 9183 #define I2C_CR2_ITBUFEN_Pos (10U)
AnnaBridge 161:aa5281ff4a02 9184 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 9185 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 9186 #define I2C_CR2_DMAEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 9187 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9188 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
AnnaBridge 161:aa5281ff4a02 9189 #define I2C_CR2_LAST_Pos (12U)
AnnaBridge 161:aa5281ff4a02 9190 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9191 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
AnnaBridge 161:aa5281ff4a02 9192
AnnaBridge 161:aa5281ff4a02 9193 /******************* Bit definition for I2C_OAR1 register *******************/
AnnaBridge 161:aa5281ff4a02 9194 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
AnnaBridge 161:aa5281ff4a02 9195 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
AnnaBridge 161:aa5281ff4a02 9196
AnnaBridge 161:aa5281ff4a02 9197 #define I2C_OAR1_ADD0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9198 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9199 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
AnnaBridge 161:aa5281ff4a02 9200 #define I2C_OAR1_ADD1_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9201 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9202 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
AnnaBridge 161:aa5281ff4a02 9203 #define I2C_OAR1_ADD2_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9204 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9205 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
AnnaBridge 161:aa5281ff4a02 9206 #define I2C_OAR1_ADD3_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9207 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9208 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
AnnaBridge 161:aa5281ff4a02 9209 #define I2C_OAR1_ADD4_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9210 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9211 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
AnnaBridge 161:aa5281ff4a02 9212 #define I2C_OAR1_ADD5_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9213 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9214 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
AnnaBridge 161:aa5281ff4a02 9215 #define I2C_OAR1_ADD6_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9216 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9217 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
AnnaBridge 161:aa5281ff4a02 9218 #define I2C_OAR1_ADD7_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9219 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9220 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
AnnaBridge 161:aa5281ff4a02 9221 #define I2C_OAR1_ADD8_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9222 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9223 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
AnnaBridge 161:aa5281ff4a02 9224 #define I2C_OAR1_ADD9_Pos (9U)
AnnaBridge 161:aa5281ff4a02 9225 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9226 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
AnnaBridge 161:aa5281ff4a02 9227
AnnaBridge 161:aa5281ff4a02 9228 #define I2C_OAR1_ADDMODE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 9229 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 9230 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
AnnaBridge 161:aa5281ff4a02 9231
AnnaBridge 161:aa5281ff4a02 9232 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 161:aa5281ff4a02 9233 #define I2C_OAR2_ENDUAL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9234 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9235 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
AnnaBridge 161:aa5281ff4a02 9236 #define I2C_OAR2_ADD2_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9237 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
AnnaBridge 161:aa5281ff4a02 9238 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
AnnaBridge 161:aa5281ff4a02 9239
AnnaBridge 161:aa5281ff4a02 9240 /******************** Bit definition for I2C_DR register ********************/
AnnaBridge 161:aa5281ff4a02 9241 #define I2C_DR_DR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9242 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 9243 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
AnnaBridge 161:aa5281ff4a02 9244
AnnaBridge 161:aa5281ff4a02 9245 /******************* Bit definition for I2C_SR1 register ********************/
AnnaBridge 161:aa5281ff4a02 9246 #define I2C_SR1_SB_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9247 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9248 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
AnnaBridge 161:aa5281ff4a02 9249 #define I2C_SR1_ADDR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9250 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9251 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
AnnaBridge 161:aa5281ff4a02 9252 #define I2C_SR1_BTF_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9253 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9254 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
AnnaBridge 161:aa5281ff4a02 9255 #define I2C_SR1_ADD10_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9256 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9257 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
AnnaBridge 161:aa5281ff4a02 9258 #define I2C_SR1_STOPF_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9259 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9260 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
AnnaBridge 161:aa5281ff4a02 9261 #define I2C_SR1_RXNE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9262 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9263 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
AnnaBridge 161:aa5281ff4a02 9264 #define I2C_SR1_TXE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9265 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9266 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
AnnaBridge 161:aa5281ff4a02 9267 #define I2C_SR1_BERR_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9268 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9269 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
AnnaBridge 161:aa5281ff4a02 9270 #define I2C_SR1_ARLO_Pos (9U)
AnnaBridge 161:aa5281ff4a02 9271 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9272 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
AnnaBridge 161:aa5281ff4a02 9273 #define I2C_SR1_AF_Pos (10U)
AnnaBridge 161:aa5281ff4a02 9274 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 9275 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
AnnaBridge 161:aa5281ff4a02 9276 #define I2C_SR1_OVR_Pos (11U)
AnnaBridge 161:aa5281ff4a02 9277 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9278 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
AnnaBridge 161:aa5281ff4a02 9279 #define I2C_SR1_PECERR_Pos (12U)
AnnaBridge 161:aa5281ff4a02 9280 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9281 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
AnnaBridge 161:aa5281ff4a02 9282 #define I2C_SR1_TIMEOUT_Pos (14U)
AnnaBridge 161:aa5281ff4a02 9283 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9284 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
AnnaBridge 161:aa5281ff4a02 9285 #define I2C_SR1_SMBALERT_Pos (15U)
AnnaBridge 161:aa5281ff4a02 9286 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 9287 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
AnnaBridge 161:aa5281ff4a02 9288
AnnaBridge 161:aa5281ff4a02 9289 /******************* Bit definition for I2C_SR2 register ********************/
AnnaBridge 161:aa5281ff4a02 9290 #define I2C_SR2_MSL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9291 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9292 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
AnnaBridge 161:aa5281ff4a02 9293 #define I2C_SR2_BUSY_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9294 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9295 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
AnnaBridge 161:aa5281ff4a02 9296 #define I2C_SR2_TRA_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9297 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9298 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
AnnaBridge 161:aa5281ff4a02 9299 #define I2C_SR2_GENCALL_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9300 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9301 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
AnnaBridge 161:aa5281ff4a02 9302 #define I2C_SR2_SMBDEFAULT_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9303 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9304 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
AnnaBridge 161:aa5281ff4a02 9305 #define I2C_SR2_SMBHOST_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9306 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9307 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
AnnaBridge 161:aa5281ff4a02 9308 #define I2C_SR2_DUALF_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9309 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9310 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
AnnaBridge 161:aa5281ff4a02 9311 #define I2C_SR2_PEC_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9312 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 9313 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
AnnaBridge 161:aa5281ff4a02 9314
AnnaBridge 161:aa5281ff4a02 9315 /******************* Bit definition for I2C_CCR register ********************/
AnnaBridge 161:aa5281ff4a02 9316 #define I2C_CCR_CCR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9317 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 9318 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
AnnaBridge 161:aa5281ff4a02 9319 #define I2C_CCR_DUTY_Pos (14U)
AnnaBridge 161:aa5281ff4a02 9320 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9321 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
AnnaBridge 161:aa5281ff4a02 9322 #define I2C_CCR_FS_Pos (15U)
AnnaBridge 161:aa5281ff4a02 9323 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 9324 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
AnnaBridge 161:aa5281ff4a02 9325
AnnaBridge 161:aa5281ff4a02 9326 /****************** Bit definition for I2C_TRISE register *******************/
AnnaBridge 161:aa5281ff4a02 9327 #define I2C_TRISE_TRISE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9328 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
AnnaBridge 161:aa5281ff4a02 9329 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
AnnaBridge 161:aa5281ff4a02 9330
AnnaBridge 161:aa5281ff4a02 9331
AnnaBridge 161:aa5281ff4a02 9332 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 9333 /* */
AnnaBridge 161:aa5281ff4a02 9334 /* Independent WATCHDOG */
AnnaBridge 161:aa5281ff4a02 9335 /* */
AnnaBridge 161:aa5281ff4a02 9336 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 9337 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 161:aa5281ff4a02 9338 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9339 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 9340 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
AnnaBridge 161:aa5281ff4a02 9341
AnnaBridge 161:aa5281ff4a02 9342 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 161:aa5281ff4a02 9343 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9344 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 161:aa5281ff4a02 9345 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 161:aa5281ff4a02 9346 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 161:aa5281ff4a02 9347 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 161:aa5281ff4a02 9348 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
AnnaBridge 161:aa5281ff4a02 9349
AnnaBridge 161:aa5281ff4a02 9350 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 161:aa5281ff4a02 9351 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9352 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 9353 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
AnnaBridge 161:aa5281ff4a02 9354
AnnaBridge 161:aa5281ff4a02 9355 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 161:aa5281ff4a02 9356 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9357 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9358 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
AnnaBridge 161:aa5281ff4a02 9359 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9360 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9361 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
AnnaBridge 161:aa5281ff4a02 9362
AnnaBridge 161:aa5281ff4a02 9363
AnnaBridge 161:aa5281ff4a02 9364
AnnaBridge 161:aa5281ff4a02 9365 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 9366 /* */
AnnaBridge 161:aa5281ff4a02 9367 /* Power Control */
AnnaBridge 161:aa5281ff4a02 9368 /* */
AnnaBridge 161:aa5281ff4a02 9369 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 9370 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 161:aa5281ff4a02 9371 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9372 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9373 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
AnnaBridge 161:aa5281ff4a02 9374 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9375 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9376 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 161:aa5281ff4a02 9377 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9378 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9379 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 161:aa5281ff4a02 9380 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9381 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9382 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 161:aa5281ff4a02 9383 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9384 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9385 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 161:aa5281ff4a02 9386
AnnaBridge 161:aa5281ff4a02 9387 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9388 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 161:aa5281ff4a02 9389 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 161:aa5281ff4a02 9390 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9391 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9392 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9393
AnnaBridge 161:aa5281ff4a02 9394 /*!< PVD level configuration */
AnnaBridge 161:aa5281ff4a02 9395 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 161:aa5281ff4a02 9396 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
AnnaBridge 161:aa5281ff4a02 9397 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
AnnaBridge 161:aa5281ff4a02 9398 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
AnnaBridge 161:aa5281ff4a02 9399 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
AnnaBridge 161:aa5281ff4a02 9400 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
AnnaBridge 161:aa5281ff4a02 9401 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
AnnaBridge 161:aa5281ff4a02 9402 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
AnnaBridge 161:aa5281ff4a02 9403 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9404 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9405 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 161:aa5281ff4a02 9406 #define PWR_CR_FPDS_Pos (9U)
AnnaBridge 161:aa5281ff4a02 9407 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9408 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
AnnaBridge 161:aa5281ff4a02 9409 #define PWR_CR_VOS_Pos (14U)
AnnaBridge 161:aa5281ff4a02 9410 #define PWR_CR_VOS_Msk (0x1U << PWR_CR_VOS_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9411 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS bit (Regulator voltage scaling output selection) */
AnnaBridge 161:aa5281ff4a02 9412
AnnaBridge 161:aa5281ff4a02 9413 /* Legacy define */
AnnaBridge 161:aa5281ff4a02 9414 #define PWR_CR_PMODE PWR_CR_VOS
AnnaBridge 161:aa5281ff4a02 9415
AnnaBridge 161:aa5281ff4a02 9416 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 161:aa5281ff4a02 9417 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9418 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9419 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 161:aa5281ff4a02 9420 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9421 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9422 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 161:aa5281ff4a02 9423 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9424 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9425 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 161:aa5281ff4a02 9426 #define PWR_CSR_BRR_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9427 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9428 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
AnnaBridge 161:aa5281ff4a02 9429 #define PWR_CSR_EWUP_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9430 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9431 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
AnnaBridge 161:aa5281ff4a02 9432 #define PWR_CSR_BRE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 9433 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9434 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
AnnaBridge 161:aa5281ff4a02 9435 #define PWR_CSR_VOSRDY_Pos (14U)
AnnaBridge 161:aa5281ff4a02 9436 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9437 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
AnnaBridge 161:aa5281ff4a02 9438
AnnaBridge 161:aa5281ff4a02 9439 /* Legacy define */
AnnaBridge 161:aa5281ff4a02 9440 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
AnnaBridge 161:aa5281ff4a02 9441
AnnaBridge 161:aa5281ff4a02 9442 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 9443 /* */
AnnaBridge 161:aa5281ff4a02 9444 /* Reset and Clock Control */
AnnaBridge 161:aa5281ff4a02 9445 /* */
AnnaBridge 161:aa5281ff4a02 9446 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 9447 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 161:aa5281ff4a02 9448 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9449 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9450 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 161:aa5281ff4a02 9451 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9452 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9453 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 161:aa5281ff4a02 9454
AnnaBridge 161:aa5281ff4a02 9455 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9456 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 161:aa5281ff4a02 9457 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 161:aa5281ff4a02 9458 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9459 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9460 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9461 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9462 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9463
AnnaBridge 161:aa5281ff4a02 9464 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9465 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 9466 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 161:aa5281ff4a02 9467 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9468 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9469 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 9470 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9471 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9472 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 9473 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9474 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 9475
AnnaBridge 161:aa5281ff4a02 9476 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 161:aa5281ff4a02 9477 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 9478 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 161:aa5281ff4a02 9479 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 161:aa5281ff4a02 9480 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 9481 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 161:aa5281ff4a02 9482 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 161:aa5281ff4a02 9483 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 9484 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 161:aa5281ff4a02 9485 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 161:aa5281ff4a02 9486 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 9487 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 161:aa5281ff4a02 9488 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 161:aa5281ff4a02 9489 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 9490 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 161:aa5281ff4a02 9491 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 161:aa5281ff4a02 9492 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 9493 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 161:aa5281ff4a02 9494 /*
AnnaBridge 161:aa5281ff4a02 9495 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 161:aa5281ff4a02 9496 */
AnnaBridge 161:aa5281ff4a02 9497 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
AnnaBridge 161:aa5281ff4a02 9498
AnnaBridge 161:aa5281ff4a02 9499 #define RCC_CR_PLLI2SON_Pos (26U)
AnnaBridge 161:aa5281ff4a02 9500 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 9501 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
AnnaBridge 161:aa5281ff4a02 9502 #define RCC_CR_PLLI2SRDY_Pos (27U)
AnnaBridge 161:aa5281ff4a02 9503 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 9504 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
AnnaBridge 161:aa5281ff4a02 9505
AnnaBridge 161:aa5281ff4a02 9506 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 161:aa5281ff4a02 9507 #define RCC_PLLCFGR_PLLM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9508 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
AnnaBridge 161:aa5281ff4a02 9509 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 161:aa5281ff4a02 9510 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9511 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9512 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9513 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9514 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9515 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9516
AnnaBridge 161:aa5281ff4a02 9517 #define RCC_PLLCFGR_PLLN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9518 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
AnnaBridge 161:aa5281ff4a02 9519 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 161:aa5281ff4a02 9520 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9521 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9522 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9523 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9524 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 9525 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9526 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9527 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 9528 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9529
AnnaBridge 161:aa5281ff4a02 9530 #define RCC_PLLCFGR_PLLP_Pos (16U)
AnnaBridge 161:aa5281ff4a02 9531 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
AnnaBridge 161:aa5281ff4a02 9532 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 161:aa5281ff4a02 9533 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 9534 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 9535
AnnaBridge 161:aa5281ff4a02 9536 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
AnnaBridge 161:aa5281ff4a02 9537 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 9538 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 161:aa5281ff4a02 9539 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
AnnaBridge 161:aa5281ff4a02 9540 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 9541 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
AnnaBridge 161:aa5281ff4a02 9542 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 161:aa5281ff4a02 9543
AnnaBridge 161:aa5281ff4a02 9544 #define RCC_PLLCFGR_PLLQ_Pos (24U)
AnnaBridge 161:aa5281ff4a02 9545 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 9546 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 161:aa5281ff4a02 9547 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 9548 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 9549 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 9550 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 9551
AnnaBridge 161:aa5281ff4a02 9552
AnnaBridge 161:aa5281ff4a02 9553 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 161:aa5281ff4a02 9554 /*!< SW configuration */
AnnaBridge 161:aa5281ff4a02 9555 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9556 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 9557 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 161:aa5281ff4a02 9558 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9559 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9560
AnnaBridge 161:aa5281ff4a02 9561 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 161:aa5281ff4a02 9562 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 161:aa5281ff4a02 9563 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
AnnaBridge 161:aa5281ff4a02 9564
AnnaBridge 161:aa5281ff4a02 9565 /*!< SWS configuration */
AnnaBridge 161:aa5281ff4a02 9566 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9567 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 9568 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 161:aa5281ff4a02 9569 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9570 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9571
AnnaBridge 161:aa5281ff4a02 9572 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 161:aa5281ff4a02 9573 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 161:aa5281ff4a02 9574 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
AnnaBridge 161:aa5281ff4a02 9575
AnnaBridge 161:aa5281ff4a02 9576 /*!< HPRE configuration */
AnnaBridge 161:aa5281ff4a02 9577 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9578 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 9579 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 161:aa5281ff4a02 9580 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9581 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9582 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9583 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9584
AnnaBridge 161:aa5281ff4a02 9585 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 161:aa5281ff4a02 9586 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 161:aa5281ff4a02 9587 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 161:aa5281ff4a02 9588 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 161:aa5281ff4a02 9589 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 161:aa5281ff4a02 9590 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 161:aa5281ff4a02 9591 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 161:aa5281ff4a02 9592 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 161:aa5281ff4a02 9593 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
AnnaBridge 161:aa5281ff4a02 9594
AnnaBridge 161:aa5281ff4a02 9595 /*!< PPRE1 configuration */
AnnaBridge 161:aa5281ff4a02 9596 #define RCC_CFGR_PPRE1_Pos (10U)
AnnaBridge 161:aa5281ff4a02 9597 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
AnnaBridge 161:aa5281ff4a02 9598 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 161:aa5281ff4a02 9599 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 9600 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9601 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9602
AnnaBridge 161:aa5281ff4a02 9603 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 161:aa5281ff4a02 9604 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 161:aa5281ff4a02 9605 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 161:aa5281ff4a02 9606 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 161:aa5281ff4a02 9607 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
AnnaBridge 161:aa5281ff4a02 9608
AnnaBridge 161:aa5281ff4a02 9609 /*!< PPRE2 configuration */
AnnaBridge 161:aa5281ff4a02 9610 #define RCC_CFGR_PPRE2_Pos (13U)
AnnaBridge 161:aa5281ff4a02 9611 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
AnnaBridge 161:aa5281ff4a02 9612 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 161:aa5281ff4a02 9613 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 9614 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9615 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 9616
AnnaBridge 161:aa5281ff4a02 9617 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 161:aa5281ff4a02 9618 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 161:aa5281ff4a02 9619 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 161:aa5281ff4a02 9620 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 161:aa5281ff4a02 9621 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
AnnaBridge 161:aa5281ff4a02 9622
AnnaBridge 161:aa5281ff4a02 9623 /*!< RTCPRE configuration */
AnnaBridge 161:aa5281ff4a02 9624 #define RCC_CFGR_RTCPRE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 9625 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
AnnaBridge 161:aa5281ff4a02 9626 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
AnnaBridge 161:aa5281ff4a02 9627 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 9628 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 9629 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 9630 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 9631 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 9632
AnnaBridge 161:aa5281ff4a02 9633 /*!< MCO1 configuration */
AnnaBridge 161:aa5281ff4a02 9634 #define RCC_CFGR_MCO1_Pos (21U)
AnnaBridge 161:aa5281ff4a02 9635 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
AnnaBridge 161:aa5281ff4a02 9636 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
AnnaBridge 161:aa5281ff4a02 9637 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 9638 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 9639
AnnaBridge 161:aa5281ff4a02 9640 #define RCC_CFGR_I2SSRC_Pos (23U)
AnnaBridge 161:aa5281ff4a02 9641 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 9642 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
AnnaBridge 161:aa5281ff4a02 9643
AnnaBridge 161:aa5281ff4a02 9644 #define RCC_CFGR_MCO1PRE_Pos (24U)
AnnaBridge 161:aa5281ff4a02 9645 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
AnnaBridge 161:aa5281ff4a02 9646 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
AnnaBridge 161:aa5281ff4a02 9647 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 9648 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 9649 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 9650
AnnaBridge 161:aa5281ff4a02 9651 #define RCC_CFGR_MCO2PRE_Pos (27U)
AnnaBridge 161:aa5281ff4a02 9652 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
AnnaBridge 161:aa5281ff4a02 9653 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
AnnaBridge 161:aa5281ff4a02 9654 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 9655 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 9656 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 9657
AnnaBridge 161:aa5281ff4a02 9658 #define RCC_CFGR_MCO2_Pos (30U)
AnnaBridge 161:aa5281ff4a02 9659 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
AnnaBridge 161:aa5281ff4a02 9660 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
AnnaBridge 161:aa5281ff4a02 9661 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 9662 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 9663
AnnaBridge 161:aa5281ff4a02 9664 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 161:aa5281ff4a02 9665 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9666 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9667 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
AnnaBridge 161:aa5281ff4a02 9668 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9669 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9670 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
AnnaBridge 161:aa5281ff4a02 9671 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9672 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9673 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
AnnaBridge 161:aa5281ff4a02 9674 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9675 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9676 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
AnnaBridge 161:aa5281ff4a02 9677 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9678 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9679 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
AnnaBridge 161:aa5281ff4a02 9680 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9681 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9682 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
AnnaBridge 161:aa5281ff4a02 9683
AnnaBridge 161:aa5281ff4a02 9684 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9685 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9686 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
AnnaBridge 161:aa5281ff4a02 9687 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9688 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9689 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
AnnaBridge 161:aa5281ff4a02 9690 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 9691 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 9692 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
AnnaBridge 161:aa5281ff4a02 9693 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 9694 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 9695 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
AnnaBridge 161:aa5281ff4a02 9696 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 9697 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9698 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
AnnaBridge 161:aa5281ff4a02 9699 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 161:aa5281ff4a02 9700 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9701 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
AnnaBridge 161:aa5281ff4a02 9702 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 9703 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 9704 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
AnnaBridge 161:aa5281ff4a02 9705
AnnaBridge 161:aa5281ff4a02 9706 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 161:aa5281ff4a02 9707 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 9708 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
AnnaBridge 161:aa5281ff4a02 9709 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 161:aa5281ff4a02 9710 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 9711 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
AnnaBridge 161:aa5281ff4a02 9712 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 161:aa5281ff4a02 9713 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 9714 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
AnnaBridge 161:aa5281ff4a02 9715 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 161:aa5281ff4a02 9716 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 9717 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
AnnaBridge 161:aa5281ff4a02 9718 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 161:aa5281ff4a02 9719 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 9720 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
AnnaBridge 161:aa5281ff4a02 9721 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
AnnaBridge 161:aa5281ff4a02 9722 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 9723 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
AnnaBridge 161:aa5281ff4a02 9724
AnnaBridge 161:aa5281ff4a02 9725 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 161:aa5281ff4a02 9726 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 9727 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
AnnaBridge 161:aa5281ff4a02 9728
AnnaBridge 161:aa5281ff4a02 9729 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 161:aa5281ff4a02 9730 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9731 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9732 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
AnnaBridge 161:aa5281ff4a02 9733 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9734 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9735 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
AnnaBridge 161:aa5281ff4a02 9736 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9737 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9738 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
AnnaBridge 161:aa5281ff4a02 9739 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9740 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9741 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
AnnaBridge 161:aa5281ff4a02 9742 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9743 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9744 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
AnnaBridge 161:aa5281ff4a02 9745 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9746 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9747 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
AnnaBridge 161:aa5281ff4a02 9748 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9749 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9750 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
AnnaBridge 161:aa5281ff4a02 9751 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9752 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9753 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
AnnaBridge 161:aa5281ff4a02 9754 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9755 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9756 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
AnnaBridge 161:aa5281ff4a02 9757 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 161:aa5281ff4a02 9758 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9759 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 161:aa5281ff4a02 9760 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
AnnaBridge 161:aa5281ff4a02 9761 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 9762 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 161:aa5281ff4a02 9763 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
AnnaBridge 161:aa5281ff4a02 9764 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 9765 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 161:aa5281ff4a02 9766 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
AnnaBridge 161:aa5281ff4a02 9767 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 9768 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
AnnaBridge 161:aa5281ff4a02 9769 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
AnnaBridge 161:aa5281ff4a02 9770 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 9771 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
AnnaBridge 161:aa5281ff4a02 9772
AnnaBridge 161:aa5281ff4a02 9773 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 161:aa5281ff4a02 9774 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9775 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9776 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
AnnaBridge 161:aa5281ff4a02 9777 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9778 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9779 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
AnnaBridge 161:aa5281ff4a02 9780 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9781 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9782 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
AnnaBridge 161:aa5281ff4a02 9783 /******************** Bit definition for RCC_AHB3RSTR register **************/
AnnaBridge 161:aa5281ff4a02 9784 #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9785 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9786 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
AnnaBridge 161:aa5281ff4a02 9787
AnnaBridge 161:aa5281ff4a02 9788
AnnaBridge 161:aa5281ff4a02 9789 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 161:aa5281ff4a02 9790 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9791 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9792 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
AnnaBridge 161:aa5281ff4a02 9793 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9794 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9795 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
AnnaBridge 161:aa5281ff4a02 9796 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9797 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9798 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
AnnaBridge 161:aa5281ff4a02 9799 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9800 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9801 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
AnnaBridge 161:aa5281ff4a02 9802 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9803 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9804 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
AnnaBridge 161:aa5281ff4a02 9805 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9806 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9807 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
AnnaBridge 161:aa5281ff4a02 9808 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9809 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9810 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
AnnaBridge 161:aa5281ff4a02 9811 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9812 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9813 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
AnnaBridge 161:aa5281ff4a02 9814 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9815 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9816 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
AnnaBridge 161:aa5281ff4a02 9817 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 161:aa5281ff4a02 9818 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9819 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
AnnaBridge 161:aa5281ff4a02 9820 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 161:aa5281ff4a02 9821 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9822 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
AnnaBridge 161:aa5281ff4a02 9823 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
AnnaBridge 161:aa5281ff4a02 9824 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 9825 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
AnnaBridge 161:aa5281ff4a02 9826 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 161:aa5281ff4a02 9827 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 9828 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
AnnaBridge 161:aa5281ff4a02 9829 #define RCC_APB1RSTR_USART3RST_Pos (18U)
AnnaBridge 161:aa5281ff4a02 9830 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 9831 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
AnnaBridge 161:aa5281ff4a02 9832 #define RCC_APB1RSTR_UART4RST_Pos (19U)
AnnaBridge 161:aa5281ff4a02 9833 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 9834 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
AnnaBridge 161:aa5281ff4a02 9835 #define RCC_APB1RSTR_UART5RST_Pos (20U)
AnnaBridge 161:aa5281ff4a02 9836 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 9837 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
AnnaBridge 161:aa5281ff4a02 9838 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 161:aa5281ff4a02 9839 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 9840 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
AnnaBridge 161:aa5281ff4a02 9841 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 161:aa5281ff4a02 9842 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 9843 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
AnnaBridge 161:aa5281ff4a02 9844 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
AnnaBridge 161:aa5281ff4a02 9845 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 9846 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
AnnaBridge 161:aa5281ff4a02 9847 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
AnnaBridge 161:aa5281ff4a02 9848 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 9849 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
AnnaBridge 161:aa5281ff4a02 9850 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
AnnaBridge 161:aa5281ff4a02 9851 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 9852 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
AnnaBridge 161:aa5281ff4a02 9853 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 161:aa5281ff4a02 9854 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 9855 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
AnnaBridge 161:aa5281ff4a02 9856 #define RCC_APB1RSTR_DACRST_Pos (29U)
AnnaBridge 161:aa5281ff4a02 9857 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 9858 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
AnnaBridge 161:aa5281ff4a02 9859
AnnaBridge 161:aa5281ff4a02 9860 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 161:aa5281ff4a02 9861 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9862 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9863 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 161:aa5281ff4a02 9864 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9865 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9866 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
AnnaBridge 161:aa5281ff4a02 9867 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9868 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9869 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 161:aa5281ff4a02 9870 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9871 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9872 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 161:aa5281ff4a02 9873 #define RCC_APB2RSTR_ADCRST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9874 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9875 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
AnnaBridge 161:aa5281ff4a02 9876 #define RCC_APB2RSTR_SDIORST_Pos (11U)
AnnaBridge 161:aa5281ff4a02 9877 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 9878 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
AnnaBridge 161:aa5281ff4a02 9879 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 161:aa5281ff4a02 9880 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9881 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 161:aa5281ff4a02 9882 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
AnnaBridge 161:aa5281ff4a02 9883 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 9884 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 161:aa5281ff4a02 9885 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
AnnaBridge 161:aa5281ff4a02 9886 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 9887 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
AnnaBridge 161:aa5281ff4a02 9888 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
AnnaBridge 161:aa5281ff4a02 9889 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 9890 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
AnnaBridge 161:aa5281ff4a02 9891 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
AnnaBridge 161:aa5281ff4a02 9892 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 9893 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
AnnaBridge 161:aa5281ff4a02 9894
AnnaBridge 161:aa5281ff4a02 9895 /* Old SPI1RST bit definition, maintained for legacy purpose */
AnnaBridge 161:aa5281ff4a02 9896 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
AnnaBridge 161:aa5281ff4a02 9897
AnnaBridge 161:aa5281ff4a02 9898 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 161:aa5281ff4a02 9899 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9900 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9901 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
AnnaBridge 161:aa5281ff4a02 9902 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9903 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9904 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
AnnaBridge 161:aa5281ff4a02 9905 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9906 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9907 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
AnnaBridge 161:aa5281ff4a02 9908 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9909 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9910 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
AnnaBridge 161:aa5281ff4a02 9911 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9912 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 9913 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
AnnaBridge 161:aa5281ff4a02 9914 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 9915 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 9916 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
AnnaBridge 161:aa5281ff4a02 9917 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9918 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9919 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
AnnaBridge 161:aa5281ff4a02 9920 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9921 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9922 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
AnnaBridge 161:aa5281ff4a02 9923 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 9924 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 9925 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
AnnaBridge 161:aa5281ff4a02 9926 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 9927 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 9928 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 161:aa5281ff4a02 9929 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
AnnaBridge 161:aa5281ff4a02 9930 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 9931 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
AnnaBridge 161:aa5281ff4a02 9932 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
AnnaBridge 161:aa5281ff4a02 9933 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 9934 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
AnnaBridge 161:aa5281ff4a02 9935 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
AnnaBridge 161:aa5281ff4a02 9936 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 9937 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 161:aa5281ff4a02 9938 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
AnnaBridge 161:aa5281ff4a02 9939 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 9940 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 161:aa5281ff4a02 9941 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
AnnaBridge 161:aa5281ff4a02 9942 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 9943 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
AnnaBridge 161:aa5281ff4a02 9944 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
AnnaBridge 161:aa5281ff4a02 9945 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 9946 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
AnnaBridge 161:aa5281ff4a02 9947 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
AnnaBridge 161:aa5281ff4a02 9948 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 9949 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
AnnaBridge 161:aa5281ff4a02 9950 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
AnnaBridge 161:aa5281ff4a02 9951 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 9952 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
AnnaBridge 161:aa5281ff4a02 9953 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
AnnaBridge 161:aa5281ff4a02 9954 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 9955 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
AnnaBridge 161:aa5281ff4a02 9956 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
AnnaBridge 161:aa5281ff4a02 9957 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 9958 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
AnnaBridge 161:aa5281ff4a02 9959 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 161:aa5281ff4a02 9960 /*
AnnaBridge 161:aa5281ff4a02 9961 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 161:aa5281ff4a02 9962 */
AnnaBridge 161:aa5281ff4a02 9963 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
AnnaBridge 161:aa5281ff4a02 9964
AnnaBridge 161:aa5281ff4a02 9965 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9966 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9967 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
AnnaBridge 161:aa5281ff4a02 9968 #define RCC_AHB2ENR_RNGEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 9969 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 9970 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
AnnaBridge 161:aa5281ff4a02 9971 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
AnnaBridge 161:aa5281ff4a02 9972 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 9973 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
AnnaBridge 161:aa5281ff4a02 9974
AnnaBridge 161:aa5281ff4a02 9975 /******************** Bit definition for RCC_AHB3ENR register ***************/
AnnaBridge 161:aa5281ff4a02 9976 /*
AnnaBridge 161:aa5281ff4a02 9977 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 161:aa5281ff4a02 9978 */
AnnaBridge 161:aa5281ff4a02 9979 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
AnnaBridge 161:aa5281ff4a02 9980
AnnaBridge 161:aa5281ff4a02 9981 #define RCC_AHB3ENR_FSMCEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9982 #define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9983 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
AnnaBridge 161:aa5281ff4a02 9984
AnnaBridge 161:aa5281ff4a02 9985 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 161:aa5281ff4a02 9986 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 9987 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 9988 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
AnnaBridge 161:aa5281ff4a02 9989 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 9990 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 9991 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
AnnaBridge 161:aa5281ff4a02 9992 #define RCC_APB1ENR_TIM4EN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 9993 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 9994 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
AnnaBridge 161:aa5281ff4a02 9995 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 161:aa5281ff4a02 9996 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 9997 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
AnnaBridge 161:aa5281ff4a02 9998 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 9999 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10000 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
AnnaBridge 161:aa5281ff4a02 10001 #define RCC_APB1ENR_TIM7EN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 10002 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10003 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
AnnaBridge 161:aa5281ff4a02 10004 #define RCC_APB1ENR_TIM12EN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 10005 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10006 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
AnnaBridge 161:aa5281ff4a02 10007 #define RCC_APB1ENR_TIM13EN_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10008 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10009 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
AnnaBridge 161:aa5281ff4a02 10010 #define RCC_APB1ENR_TIM14EN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10011 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10012 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
AnnaBridge 161:aa5281ff4a02 10013 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 10014 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10015 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
AnnaBridge 161:aa5281ff4a02 10016 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 161:aa5281ff4a02 10017 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10018 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
AnnaBridge 161:aa5281ff4a02 10019 #define RCC_APB1ENR_SPI3EN_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10020 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10021 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
AnnaBridge 161:aa5281ff4a02 10022 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 161:aa5281ff4a02 10023 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10024 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
AnnaBridge 161:aa5281ff4a02 10025 #define RCC_APB1ENR_USART3EN_Pos (18U)
AnnaBridge 161:aa5281ff4a02 10026 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10027 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
AnnaBridge 161:aa5281ff4a02 10028 #define RCC_APB1ENR_UART4EN_Pos (19U)
AnnaBridge 161:aa5281ff4a02 10029 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 10030 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
AnnaBridge 161:aa5281ff4a02 10031 #define RCC_APB1ENR_UART5EN_Pos (20U)
AnnaBridge 161:aa5281ff4a02 10032 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 10033 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
AnnaBridge 161:aa5281ff4a02 10034 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 161:aa5281ff4a02 10035 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10036 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
AnnaBridge 161:aa5281ff4a02 10037 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 161:aa5281ff4a02 10038 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10039 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
AnnaBridge 161:aa5281ff4a02 10040 #define RCC_APB1ENR_I2C3EN_Pos (23U)
AnnaBridge 161:aa5281ff4a02 10041 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 10042 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
AnnaBridge 161:aa5281ff4a02 10043 #define RCC_APB1ENR_CAN1EN_Pos (25U)
AnnaBridge 161:aa5281ff4a02 10044 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 10045 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
AnnaBridge 161:aa5281ff4a02 10046 #define RCC_APB1ENR_CAN2EN_Pos (26U)
AnnaBridge 161:aa5281ff4a02 10047 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 10048 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
AnnaBridge 161:aa5281ff4a02 10049 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 161:aa5281ff4a02 10050 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 10051 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
AnnaBridge 161:aa5281ff4a02 10052 #define RCC_APB1ENR_DACEN_Pos (29U)
AnnaBridge 161:aa5281ff4a02 10053 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 10054 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
AnnaBridge 161:aa5281ff4a02 10055
AnnaBridge 161:aa5281ff4a02 10056 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 161:aa5281ff4a02 10057 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10058 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10059 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 161:aa5281ff4a02 10060 #define RCC_APB2ENR_TIM8EN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10061 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10062 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
AnnaBridge 161:aa5281ff4a02 10063 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10064 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10065 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 161:aa5281ff4a02 10066 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 10067 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10068 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 161:aa5281ff4a02 10069 #define RCC_APB2ENR_ADC1EN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10070 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10071 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
AnnaBridge 161:aa5281ff4a02 10072 #define RCC_APB2ENR_ADC2EN_Pos (9U)
AnnaBridge 161:aa5281ff4a02 10073 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10074 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
AnnaBridge 161:aa5281ff4a02 10075 #define RCC_APB2ENR_ADC3EN_Pos (10U)
AnnaBridge 161:aa5281ff4a02 10076 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10077 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
AnnaBridge 161:aa5281ff4a02 10078 #define RCC_APB2ENR_SDIOEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 10079 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10080 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
AnnaBridge 161:aa5281ff4a02 10081 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10082 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10083 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 161:aa5281ff4a02 10084 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
AnnaBridge 161:aa5281ff4a02 10085 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10086 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 161:aa5281ff4a02 10087 #define RCC_APB2ENR_TIM9EN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10088 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10089 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
AnnaBridge 161:aa5281ff4a02 10090 #define RCC_APB2ENR_TIM10EN_Pos (17U)
AnnaBridge 161:aa5281ff4a02 10091 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10092 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
AnnaBridge 161:aa5281ff4a02 10093 #define RCC_APB2ENR_TIM11EN_Pos (18U)
AnnaBridge 161:aa5281ff4a02 10094 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10095 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
AnnaBridge 161:aa5281ff4a02 10096
AnnaBridge 161:aa5281ff4a02 10097 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 161:aa5281ff4a02 10098 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10099 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10100 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
AnnaBridge 161:aa5281ff4a02 10101 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10102 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10103 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10104 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 10105 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10106 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10107 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
AnnaBridge 161:aa5281ff4a02 10108 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10109 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10110 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10111 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10112 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
AnnaBridge 161:aa5281ff4a02 10113 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 10114 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10115 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10116 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 10117 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10118 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10119 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10120 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10121 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10122 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10123 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10124 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
AnnaBridge 161:aa5281ff4a02 10125 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10126 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10127 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10128 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10129 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10130 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10131 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10132 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10133 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10134 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
AnnaBridge 161:aa5281ff4a02 10135 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10136 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10137 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
AnnaBridge 161:aa5281ff4a02 10138 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10139 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10140 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
AnnaBridge 161:aa5281ff4a02 10141 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10142 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10143 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
AnnaBridge 161:aa5281ff4a02 10144 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10145 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10146
AnnaBridge 161:aa5281ff4a02 10147 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
AnnaBridge 161:aa5281ff4a02 10148 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 10149 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10150 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
AnnaBridge 161:aa5281ff4a02 10151 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 10152 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10153 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
AnnaBridge 161:aa5281ff4a02 10154 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 10155 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10156 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
AnnaBridge 161:aa5281ff4a02 10157 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 10158 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10159 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
AnnaBridge 161:aa5281ff4a02 10160 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 10161 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10162 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
AnnaBridge 161:aa5281ff4a02 10163 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 10164 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
AnnaBridge 161:aa5281ff4a02 10165
AnnaBridge 161:aa5281ff4a02 10166 /******************** Bit definition for RCC_AHB2LPENR register *************/
AnnaBridge 161:aa5281ff4a02 10167 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10168 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10169 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
AnnaBridge 161:aa5281ff4a02 10170 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 10171 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10172 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10173 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10174 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10175 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10176
AnnaBridge 161:aa5281ff4a02 10177 /******************** Bit definition for RCC_AHB3LPENR register *************/
AnnaBridge 161:aa5281ff4a02 10178 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10179 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10180 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10181
AnnaBridge 161:aa5281ff4a02 10182 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 161:aa5281ff4a02 10183 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10184 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10185 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10186 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10187 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10188 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10189 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 10190 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10191 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10192 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 161:aa5281ff4a02 10193 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10194 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10195 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10196 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10197 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10198 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 10199 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10200 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10201 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 10202 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10203 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10204 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10205 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10206 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10207 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10208 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10209 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10210 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 10211 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10212 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10213 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 161:aa5281ff4a02 10214 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10215 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10216 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10217 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10218 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10219 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 161:aa5281ff4a02 10220 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10221 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10222 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
AnnaBridge 161:aa5281ff4a02 10223 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10224 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10225 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
AnnaBridge 161:aa5281ff4a02 10226 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 10227 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10228 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
AnnaBridge 161:aa5281ff4a02 10229 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 10230 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10231 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 161:aa5281ff4a02 10232 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10233 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10234 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 161:aa5281ff4a02 10235 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10236 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10237 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
AnnaBridge 161:aa5281ff4a02 10238 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 10239 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10240 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
AnnaBridge 161:aa5281ff4a02 10241 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 10242 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10243 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
AnnaBridge 161:aa5281ff4a02 10244 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 10245 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10246 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 161:aa5281ff4a02 10247 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 10248 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10249 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
AnnaBridge 161:aa5281ff4a02 10250 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 10251 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10252
AnnaBridge 161:aa5281ff4a02 10253 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 161:aa5281ff4a02 10254 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10255 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10256 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10257 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10258 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10259 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10260 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10261 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10262 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10263 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 10264 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10265 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10266 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10267 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10268 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10269 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
AnnaBridge 161:aa5281ff4a02 10270 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10271 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10272 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
AnnaBridge 161:aa5281ff4a02 10273 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10274 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10275 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 10276 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10277 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10278 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10279 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10280 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10281 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
AnnaBridge 161:aa5281ff4a02 10282 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10283 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
AnnaBridge 161:aa5281ff4a02 10284 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10285 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10286 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10287 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
AnnaBridge 161:aa5281ff4a02 10288 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10289 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10290 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
AnnaBridge 161:aa5281ff4a02 10291 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10292 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
AnnaBridge 161:aa5281ff4a02 10293
AnnaBridge 161:aa5281ff4a02 10294 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 161:aa5281ff4a02 10295 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10296 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10297 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 161:aa5281ff4a02 10298 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10299 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10300 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 161:aa5281ff4a02 10301 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 10302 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10303 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 161:aa5281ff4a02 10304
AnnaBridge 161:aa5281ff4a02 10305 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10306 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 10307 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 161:aa5281ff4a02 10308 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10309 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10310
AnnaBridge 161:aa5281ff4a02 10311 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10312 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10313 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 161:aa5281ff4a02 10314 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10315 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10316 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
AnnaBridge 161:aa5281ff4a02 10317
AnnaBridge 161:aa5281ff4a02 10318 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 161:aa5281ff4a02 10319 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10320 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10321 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 161:aa5281ff4a02 10322 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10323 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10324 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 161:aa5281ff4a02 10325 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 161:aa5281ff4a02 10326 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 10327 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 161:aa5281ff4a02 10328 #define RCC_CSR_BORRSTF_Pos (25U)
AnnaBridge 161:aa5281ff4a02 10329 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 10330 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
AnnaBridge 161:aa5281ff4a02 10331 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 161:aa5281ff4a02 10332 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 10333 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 161:aa5281ff4a02 10334 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 161:aa5281ff4a02 10335 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 10336 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
AnnaBridge 161:aa5281ff4a02 10337 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 161:aa5281ff4a02 10338 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 10339 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 161:aa5281ff4a02 10340 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 161:aa5281ff4a02 10341 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 10342 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 161:aa5281ff4a02 10343 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 161:aa5281ff4a02 10344 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 10345 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 161:aa5281ff4a02 10346 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 161:aa5281ff4a02 10347 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 10348 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 161:aa5281ff4a02 10349 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 10350 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
AnnaBridge 161:aa5281ff4a02 10351 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
AnnaBridge 161:aa5281ff4a02 10352
AnnaBridge 161:aa5281ff4a02 10353 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 161:aa5281ff4a02 10354 #define RCC_SSCGR_MODPER_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10355 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
AnnaBridge 161:aa5281ff4a02 10356 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
AnnaBridge 161:aa5281ff4a02 10357 #define RCC_SSCGR_INCSTEP_Pos (13U)
AnnaBridge 161:aa5281ff4a02 10358 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
AnnaBridge 161:aa5281ff4a02 10359 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
AnnaBridge 161:aa5281ff4a02 10360 #define RCC_SSCGR_SPREADSEL_Pos (30U)
AnnaBridge 161:aa5281ff4a02 10361 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 10362 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
AnnaBridge 161:aa5281ff4a02 10363 #define RCC_SSCGR_SSCGEN_Pos (31U)
AnnaBridge 161:aa5281ff4a02 10364 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 10365 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
AnnaBridge 161:aa5281ff4a02 10366
AnnaBridge 161:aa5281ff4a02 10367 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
AnnaBridge 161:aa5281ff4a02 10368 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
AnnaBridge 161:aa5281ff4a02 10369 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
AnnaBridge 161:aa5281ff4a02 10370 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
AnnaBridge 161:aa5281ff4a02 10371 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10372 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10373 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10374 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10375 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10376 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10377 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10378 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10379 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10380
AnnaBridge 161:aa5281ff4a02 10381 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
AnnaBridge 161:aa5281ff4a02 10382 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
AnnaBridge 161:aa5281ff4a02 10383 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
AnnaBridge 161:aa5281ff4a02 10384 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 10385 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 10386 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 10387
AnnaBridge 161:aa5281ff4a02 10388
AnnaBridge 161:aa5281ff4a02 10389 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 10390 /* */
AnnaBridge 161:aa5281ff4a02 10391 /* RNG */
AnnaBridge 161:aa5281ff4a02 10392 /* */
AnnaBridge 161:aa5281ff4a02 10393 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 10394 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 161:aa5281ff4a02 10395 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 10396 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10397 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 161:aa5281ff4a02 10398 #define RNG_CR_IE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 10399 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10400 #define RNG_CR_IE RNG_CR_IE_Msk
AnnaBridge 161:aa5281ff4a02 10401
AnnaBridge 161:aa5281ff4a02 10402 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 161:aa5281ff4a02 10403 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10404 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10405 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 161:aa5281ff4a02 10406 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10407 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10408 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 161:aa5281ff4a02 10409 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 10410 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10411 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 161:aa5281ff4a02 10412 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 161:aa5281ff4a02 10413 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10414 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 161:aa5281ff4a02 10415 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 161:aa5281ff4a02 10416 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10417 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
AnnaBridge 161:aa5281ff4a02 10418
AnnaBridge 161:aa5281ff4a02 10419 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 10420 /* */
AnnaBridge 161:aa5281ff4a02 10421 /* Real-Time Clock (RTC) */
AnnaBridge 161:aa5281ff4a02 10422 /* */
AnnaBridge 161:aa5281ff4a02 10423 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 10424 /*
AnnaBridge 161:aa5281ff4a02 10425 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 161:aa5281ff4a02 10426 */
AnnaBridge 161:aa5281ff4a02 10427 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
AnnaBridge 161:aa5281ff4a02 10428 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
AnnaBridge 161:aa5281ff4a02 10429 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 161:aa5281ff4a02 10430 #define RTC_TR_PM_Pos (22U)
AnnaBridge 161:aa5281ff4a02 10431 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10432 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 161:aa5281ff4a02 10433 #define RTC_TR_HT_Pos (20U)
AnnaBridge 161:aa5281ff4a02 10434 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 10435 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 161:aa5281ff4a02 10436 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 10437 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10438 #define RTC_TR_HU_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10439 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 10440 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 161:aa5281ff4a02 10441 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10442 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10443 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10444 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 10445 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10446 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 161:aa5281ff4a02 10447 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 161:aa5281ff4a02 10448 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10449 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10450 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10451 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10452 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 10453 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 161:aa5281ff4a02 10454 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10455 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10456 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10457 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10458 #define RTC_TR_ST_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10459 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 10460 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 161:aa5281ff4a02 10461 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10462 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10463 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10464 #define RTC_TR_SU_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10465 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 10466 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 161:aa5281ff4a02 10467 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10468 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10469 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10470 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10471
AnnaBridge 161:aa5281ff4a02 10472 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 161:aa5281ff4a02 10473 #define RTC_DR_YT_Pos (20U)
AnnaBridge 161:aa5281ff4a02 10474 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 161:aa5281ff4a02 10475 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 161:aa5281ff4a02 10476 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 10477 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10478 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10479 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 10480 #define RTC_DR_YU_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10481 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 10482 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 161:aa5281ff4a02 10483 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10484 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10485 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10486 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 10487 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 161:aa5281ff4a02 10488 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 161:aa5281ff4a02 10489 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 161:aa5281ff4a02 10490 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10491 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10492 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10493 #define RTC_DR_MT_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10494 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10495 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 161:aa5281ff4a02 10496 #define RTC_DR_MU_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10497 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 10498 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 161:aa5281ff4a02 10499 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10500 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10501 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10502 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10503 #define RTC_DR_DT_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10504 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 10505 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 161:aa5281ff4a02 10506 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10507 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10508 #define RTC_DR_DU_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10509 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 10510 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 161:aa5281ff4a02 10511 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10512 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10513 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10514 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10515
AnnaBridge 161:aa5281ff4a02 10516 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 161:aa5281ff4a02 10517 #define RTC_CR_COE_Pos (23U)
AnnaBridge 161:aa5281ff4a02 10518 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 10519 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 161:aa5281ff4a02 10520 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 161:aa5281ff4a02 10521 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 161:aa5281ff4a02 10522 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 161:aa5281ff4a02 10523 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10524 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10525 #define RTC_CR_POL_Pos (20U)
AnnaBridge 161:aa5281ff4a02 10526 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 10527 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 161:aa5281ff4a02 10528 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 161:aa5281ff4a02 10529 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 10530 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 161:aa5281ff4a02 10531 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 161:aa5281ff4a02 10532 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10533 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 161:aa5281ff4a02 10534 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 161:aa5281ff4a02 10535 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10536 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 161:aa5281ff4a02 10537 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10538 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10539 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 161:aa5281ff4a02 10540 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10541 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10542 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 161:aa5281ff4a02 10543 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 10544 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10545 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 161:aa5281ff4a02 10546 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 10547 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10548 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 161:aa5281ff4a02 10549 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10550 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10551 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 161:aa5281ff4a02 10552 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 10553 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10554 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 161:aa5281ff4a02 10555 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 10556 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10557 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 161:aa5281ff4a02 10558 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 10559 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10560 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 161:aa5281ff4a02 10561 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10562 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10563 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 161:aa5281ff4a02 10564 #define RTC_CR_DCE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10565 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10566 #define RTC_CR_DCE RTC_CR_DCE_Msk
AnnaBridge 161:aa5281ff4a02 10567 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 161:aa5281ff4a02 10568 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10569 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 161:aa5281ff4a02 10570 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 161:aa5281ff4a02 10571 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10572 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 161:aa5281ff4a02 10573 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10574 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10575 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 161:aa5281ff4a02 10576 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 10577 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10578 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 161:aa5281ff4a02 10579 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10580 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 161:aa5281ff4a02 10581 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 161:aa5281ff4a02 10582 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10583 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10584 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10585
AnnaBridge 161:aa5281ff4a02 10586 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 10587 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 161:aa5281ff4a02 10588
AnnaBridge 161:aa5281ff4a02 10589 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 161:aa5281ff4a02 10590 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10591 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10592 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 161:aa5281ff4a02 10593 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 161:aa5281ff4a02 10594 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10595 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 161:aa5281ff4a02 10596 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 161:aa5281ff4a02 10597 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10598 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 161:aa5281ff4a02 10599 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10600 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10601 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 161:aa5281ff4a02 10602 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 161:aa5281ff4a02 10603 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10604 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 161:aa5281ff4a02 10605 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 161:aa5281ff4a02 10606 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10607 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 161:aa5281ff4a02 10608 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 161:aa5281ff4a02 10609 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10610 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 161:aa5281ff4a02 10611 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10612 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10613 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 161:aa5281ff4a02 10614 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10615 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10616 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 161:aa5281ff4a02 10617 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 161:aa5281ff4a02 10618 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10619 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 161:aa5281ff4a02 10620 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 161:aa5281ff4a02 10621 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10622 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 161:aa5281ff4a02 10623 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10624 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10625 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 161:aa5281ff4a02 10626 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 161:aa5281ff4a02 10627 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10628 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 161:aa5281ff4a02 10629 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 161:aa5281ff4a02 10630 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10631 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 161:aa5281ff4a02 10632 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10633 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10634 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 161:aa5281ff4a02 10635 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10636 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10637 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 161:aa5281ff4a02 10638
AnnaBridge 161:aa5281ff4a02 10639 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 161:aa5281ff4a02 10640 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10641 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 161:aa5281ff4a02 10642 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 161:aa5281ff4a02 10643 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10644 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 161:aa5281ff4a02 10645 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 161:aa5281ff4a02 10646
AnnaBridge 161:aa5281ff4a02 10647 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 161:aa5281ff4a02 10648 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10649 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 10650 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 161:aa5281ff4a02 10651
AnnaBridge 161:aa5281ff4a02 10652 /******************** Bits definition for RTC_CALIBR register ***************/
AnnaBridge 161:aa5281ff4a02 10653 #define RTC_CALIBR_DCS_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10654 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10655 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
AnnaBridge 161:aa5281ff4a02 10656 #define RTC_CALIBR_DC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10657 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
AnnaBridge 161:aa5281ff4a02 10658 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
AnnaBridge 161:aa5281ff4a02 10659
AnnaBridge 161:aa5281ff4a02 10660 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 161:aa5281ff4a02 10661 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 161:aa5281ff4a02 10662 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 10663 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 161:aa5281ff4a02 10664 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 161:aa5281ff4a02 10665 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 10666 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 161:aa5281ff4a02 10667 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 161:aa5281ff4a02 10668 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 10669 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 161:aa5281ff4a02 10670 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 10671 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 10672 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 161:aa5281ff4a02 10673 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 10674 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 161:aa5281ff4a02 10675 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 10676 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 10677 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 10678 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 10679 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 161:aa5281ff4a02 10680 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 10681 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 161:aa5281ff4a02 10682 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 161:aa5281ff4a02 10683 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10684 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 161:aa5281ff4a02 10685 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 161:aa5281ff4a02 10686 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 10687 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 161:aa5281ff4a02 10688 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 10689 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10690 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10691 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 10692 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 161:aa5281ff4a02 10693 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10694 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10695 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10696 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 10697 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10698 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10699 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 161:aa5281ff4a02 10700 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10701 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 161:aa5281ff4a02 10702 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 161:aa5281ff4a02 10703 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10704 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10705 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10706 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10707 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 10708 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 161:aa5281ff4a02 10709 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10710 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10711 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10712 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10713 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10714 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10715 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 161:aa5281ff4a02 10716 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10717 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 10718 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 161:aa5281ff4a02 10719 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10720 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10721 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10722 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10723 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 10724 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 161:aa5281ff4a02 10725 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10726 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10727 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10728 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10729
AnnaBridge 161:aa5281ff4a02 10730 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 161:aa5281ff4a02 10731 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 161:aa5281ff4a02 10732 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 10733 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 161:aa5281ff4a02 10734 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 161:aa5281ff4a02 10735 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 10736 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 161:aa5281ff4a02 10737 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 161:aa5281ff4a02 10738 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 161:aa5281ff4a02 10739 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 161:aa5281ff4a02 10740 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 10741 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 10742 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 161:aa5281ff4a02 10743 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 10744 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 161:aa5281ff4a02 10745 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 10746 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 10747 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 10748 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 10749 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 161:aa5281ff4a02 10750 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 10751 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 161:aa5281ff4a02 10752 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 161:aa5281ff4a02 10753 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10754 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 161:aa5281ff4a02 10755 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 161:aa5281ff4a02 10756 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 10757 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 161:aa5281ff4a02 10758 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 10759 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10760 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10761 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 10762 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 161:aa5281ff4a02 10763 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10764 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10765 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10766 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 10767 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10768 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10769 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 161:aa5281ff4a02 10770 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10771 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 161:aa5281ff4a02 10772 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 161:aa5281ff4a02 10773 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10774 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10775 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10776 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10777 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 10778 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 161:aa5281ff4a02 10779 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10780 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10781 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10782 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10783 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10784 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10785 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 161:aa5281ff4a02 10786 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10787 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 10788 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 161:aa5281ff4a02 10789 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10790 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10791 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10792 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10793 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 10794 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 161:aa5281ff4a02 10795 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10796 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10797 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10798 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10799
AnnaBridge 161:aa5281ff4a02 10800 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 161:aa5281ff4a02 10801 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10802 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 10803 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 161:aa5281ff4a02 10804
AnnaBridge 161:aa5281ff4a02 10805 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 161:aa5281ff4a02 10806 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10807 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 10808 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 161:aa5281ff4a02 10809
AnnaBridge 161:aa5281ff4a02 10810 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 161:aa5281ff4a02 10811 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10812 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 161:aa5281ff4a02 10813 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 161:aa5281ff4a02 10814 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 161:aa5281ff4a02 10815 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 10816 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 161:aa5281ff4a02 10817
AnnaBridge 161:aa5281ff4a02 10818 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 161:aa5281ff4a02 10819 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 161:aa5281ff4a02 10820 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 10821 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 161:aa5281ff4a02 10822 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 161:aa5281ff4a02 10823 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 10824 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 161:aa5281ff4a02 10825 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 10826 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 10827 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10828 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 161:aa5281ff4a02 10829 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 161:aa5281ff4a02 10830 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10831 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10832 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10833 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 10834 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10835 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 161:aa5281ff4a02 10836 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 161:aa5281ff4a02 10837 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10838 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10839 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10840 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10841 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 10842 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 161:aa5281ff4a02 10843 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10844 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10845 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10846 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10847 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10848 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 10849 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 161:aa5281ff4a02 10850 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10851 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10852 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10853 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10854 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 10855 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 161:aa5281ff4a02 10856 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10857 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10858 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10859 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10860
AnnaBridge 161:aa5281ff4a02 10861 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 161:aa5281ff4a02 10862 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 161:aa5281ff4a02 10863 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 161:aa5281ff4a02 10864 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 161:aa5281ff4a02 10865 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10866 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10867 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10868 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 161:aa5281ff4a02 10869 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10870 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 161:aa5281ff4a02 10871 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10872 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 10873 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 161:aa5281ff4a02 10874 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10875 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10876 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10877 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10878 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10879 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 10880 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 161:aa5281ff4a02 10881 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10882 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10883 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10884 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 10885 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 161:aa5281ff4a02 10886 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10887 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10888 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10889 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10890
AnnaBridge 161:aa5281ff4a02 10891 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 161:aa5281ff4a02 10892 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10893 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 10894 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 161:aa5281ff4a02 10895
AnnaBridge 161:aa5281ff4a02 10896 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 161:aa5281ff4a02 10897 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10898 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10899 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 161:aa5281ff4a02 10900 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 161:aa5281ff4a02 10901 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10902 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 161:aa5281ff4a02 10903 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 161:aa5281ff4a02 10904 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10905 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 161:aa5281ff4a02 10906 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10907 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 161:aa5281ff4a02 10908 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 161:aa5281ff4a02 10909 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10910 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10911 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10912 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10913 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10914 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 10915 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 10916 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10917 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10918
AnnaBridge 161:aa5281ff4a02 10919 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 161:aa5281ff4a02 10920 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
AnnaBridge 161:aa5281ff4a02 10921 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 10922 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
AnnaBridge 161:aa5281ff4a02 10923 #define RTC_TAFCR_TSINSEL_Pos (17U)
AnnaBridge 161:aa5281ff4a02 10924 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 10925 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
AnnaBridge 161:aa5281ff4a02 10926 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
AnnaBridge 161:aa5281ff4a02 10927 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 10928 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
AnnaBridge 161:aa5281ff4a02 10929 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 161:aa5281ff4a02 10930 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 10931 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 161:aa5281ff4a02 10932 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 161:aa5281ff4a02 10933 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 161:aa5281ff4a02 10934 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 161:aa5281ff4a02 10935 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 10936 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 10937 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 161:aa5281ff4a02 10938 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 161:aa5281ff4a02 10939 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 161:aa5281ff4a02 10940 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 10941 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 10942 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 161:aa5281ff4a02 10943 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 161:aa5281ff4a02 10944 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 161:aa5281ff4a02 10945 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 10946 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 10947 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 10948 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 161:aa5281ff4a02 10949 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 10950 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 161:aa5281ff4a02 10951 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 161:aa5281ff4a02 10952 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 10953 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 161:aa5281ff4a02 10954 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 161:aa5281ff4a02 10955 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 10956 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 161:aa5281ff4a02 10957 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 10958 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 10959 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 161:aa5281ff4a02 10960 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 161:aa5281ff4a02 10961 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 10962 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 161:aa5281ff4a02 10963 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10964 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 10965 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 161:aa5281ff4a02 10966
AnnaBridge 161:aa5281ff4a02 10967 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 10968 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
AnnaBridge 161:aa5281ff4a02 10969
AnnaBridge 161:aa5281ff4a02 10970 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 161:aa5281ff4a02 10971 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 161:aa5281ff4a02 10972 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 10973 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 161:aa5281ff4a02 10974 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 10975 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 10976 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 10977 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 10978 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10979 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 161:aa5281ff4a02 10980 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 161:aa5281ff4a02 10981
AnnaBridge 161:aa5281ff4a02 10982 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 161:aa5281ff4a02 10983 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 161:aa5281ff4a02 10984 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 161:aa5281ff4a02 10985 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 161:aa5281ff4a02 10986 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 10987 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 10988 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 10989 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 10990 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10991 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 161:aa5281ff4a02 10992 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 161:aa5281ff4a02 10993
AnnaBridge 161:aa5281ff4a02 10994 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 161:aa5281ff4a02 10995 #define RTC_BKP0R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 10996 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 10997 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 161:aa5281ff4a02 10998
AnnaBridge 161:aa5281ff4a02 10999 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 161:aa5281ff4a02 11000 #define RTC_BKP1R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11001 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11002 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 161:aa5281ff4a02 11003
AnnaBridge 161:aa5281ff4a02 11004 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 161:aa5281ff4a02 11005 #define RTC_BKP2R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11006 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11007 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 161:aa5281ff4a02 11008
AnnaBridge 161:aa5281ff4a02 11009 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 161:aa5281ff4a02 11010 #define RTC_BKP3R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11011 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11012 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 161:aa5281ff4a02 11013
AnnaBridge 161:aa5281ff4a02 11014 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 161:aa5281ff4a02 11015 #define RTC_BKP4R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11016 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11017 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 161:aa5281ff4a02 11018
AnnaBridge 161:aa5281ff4a02 11019 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 161:aa5281ff4a02 11020 #define RTC_BKP5R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11021 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11022 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 161:aa5281ff4a02 11023
AnnaBridge 161:aa5281ff4a02 11024 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 161:aa5281ff4a02 11025 #define RTC_BKP6R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11026 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11027 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 161:aa5281ff4a02 11028
AnnaBridge 161:aa5281ff4a02 11029 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 161:aa5281ff4a02 11030 #define RTC_BKP7R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11031 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11032 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 161:aa5281ff4a02 11033
AnnaBridge 161:aa5281ff4a02 11034 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 161:aa5281ff4a02 11035 #define RTC_BKP8R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11036 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11037 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 161:aa5281ff4a02 11038
AnnaBridge 161:aa5281ff4a02 11039 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 161:aa5281ff4a02 11040 #define RTC_BKP9R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11041 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11042 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 161:aa5281ff4a02 11043
AnnaBridge 161:aa5281ff4a02 11044 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 161:aa5281ff4a02 11045 #define RTC_BKP10R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11046 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11047 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 161:aa5281ff4a02 11048
AnnaBridge 161:aa5281ff4a02 11049 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 161:aa5281ff4a02 11050 #define RTC_BKP11R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11051 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11052 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 161:aa5281ff4a02 11053
AnnaBridge 161:aa5281ff4a02 11054 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 161:aa5281ff4a02 11055 #define RTC_BKP12R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11056 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11057 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 161:aa5281ff4a02 11058
AnnaBridge 161:aa5281ff4a02 11059 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 161:aa5281ff4a02 11060 #define RTC_BKP13R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11061 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11062 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 161:aa5281ff4a02 11063
AnnaBridge 161:aa5281ff4a02 11064 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 161:aa5281ff4a02 11065 #define RTC_BKP14R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11066 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11067 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 161:aa5281ff4a02 11068
AnnaBridge 161:aa5281ff4a02 11069 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 161:aa5281ff4a02 11070 #define RTC_BKP15R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11071 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11072 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 161:aa5281ff4a02 11073
AnnaBridge 161:aa5281ff4a02 11074 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 161:aa5281ff4a02 11075 #define RTC_BKP16R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11076 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11077 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 161:aa5281ff4a02 11078
AnnaBridge 161:aa5281ff4a02 11079 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 161:aa5281ff4a02 11080 #define RTC_BKP17R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11081 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11082 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 161:aa5281ff4a02 11083
AnnaBridge 161:aa5281ff4a02 11084 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 161:aa5281ff4a02 11085 #define RTC_BKP18R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11086 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11087 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 161:aa5281ff4a02 11088
AnnaBridge 161:aa5281ff4a02 11089 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 161:aa5281ff4a02 11090 #define RTC_BKP19R_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11091 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11092 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 161:aa5281ff4a02 11093
AnnaBridge 161:aa5281ff4a02 11094 /******************** Number of backup registers ******************************/
AnnaBridge 161:aa5281ff4a02 11095 #define RTC_BKP_NUMBER 0x000000014U
AnnaBridge 161:aa5281ff4a02 11096
AnnaBridge 161:aa5281ff4a02 11097
AnnaBridge 161:aa5281ff4a02 11098 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 11099 /* */
AnnaBridge 161:aa5281ff4a02 11100 /* SD host Interface */
AnnaBridge 161:aa5281ff4a02 11101 /* */
AnnaBridge 161:aa5281ff4a02 11102 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 11103 /****************** Bit definition for SDIO_POWER register ******************/
AnnaBridge 161:aa5281ff4a02 11104 #define SDIO_POWER_PWRCTRL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11105 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 11106 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 161:aa5281ff4a02 11107 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
AnnaBridge 161:aa5281ff4a02 11108 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
AnnaBridge 161:aa5281ff4a02 11109
AnnaBridge 161:aa5281ff4a02 11110 /****************** Bit definition for SDIO_CLKCR register ******************/
AnnaBridge 161:aa5281ff4a02 11111 #define SDIO_CLKCR_CLKDIV_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11112 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 11113 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
AnnaBridge 161:aa5281ff4a02 11114 #define SDIO_CLKCR_CLKEN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11115 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11116 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
AnnaBridge 161:aa5281ff4a02 11117 #define SDIO_CLKCR_PWRSAV_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11118 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11119 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
AnnaBridge 161:aa5281ff4a02 11120 #define SDIO_CLKCR_BYPASS_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11121 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11122 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
AnnaBridge 161:aa5281ff4a02 11123
AnnaBridge 161:aa5281ff4a02 11124 #define SDIO_CLKCR_WIDBUS_Pos (11U)
AnnaBridge 161:aa5281ff4a02 11125 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
AnnaBridge 161:aa5281ff4a02 11126 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 161:aa5281ff4a02 11127 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
AnnaBridge 161:aa5281ff4a02 11128 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
AnnaBridge 161:aa5281ff4a02 11129
AnnaBridge 161:aa5281ff4a02 11130 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 11131 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 11132 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
AnnaBridge 161:aa5281ff4a02 11133 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
AnnaBridge 161:aa5281ff4a02 11134 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 11135 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
AnnaBridge 161:aa5281ff4a02 11136
AnnaBridge 161:aa5281ff4a02 11137 /******************* Bit definition for SDIO_ARG register *******************/
AnnaBridge 161:aa5281ff4a02 11138 #define SDIO_ARG_CMDARG_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11139 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11140 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
AnnaBridge 161:aa5281ff4a02 11141
AnnaBridge 161:aa5281ff4a02 11142 /******************* Bit definition for SDIO_CMD register *******************/
AnnaBridge 161:aa5281ff4a02 11143 #define SDIO_CMD_CMDINDEX_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11144 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
AnnaBridge 161:aa5281ff4a02 11145 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
AnnaBridge 161:aa5281ff4a02 11146
AnnaBridge 161:aa5281ff4a02 11147 #define SDIO_CMD_WAITRESP_Pos (6U)
AnnaBridge 161:aa5281ff4a02 11148 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 11149 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 161:aa5281ff4a02 11150 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 11151 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
AnnaBridge 161:aa5281ff4a02 11152
AnnaBridge 161:aa5281ff4a02 11153 #define SDIO_CMD_WAITINT_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11154 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11155 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
AnnaBridge 161:aa5281ff4a02 11156 #define SDIO_CMD_WAITPEND_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11157 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11158 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 161:aa5281ff4a02 11159 #define SDIO_CMD_CPSMEN_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11160 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11161 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 161:aa5281ff4a02 11162 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
AnnaBridge 161:aa5281ff4a02 11163 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 11164 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
AnnaBridge 161:aa5281ff4a02 11165 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11166 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 11167 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
AnnaBridge 161:aa5281ff4a02 11168 #define SDIO_CMD_NIEN_Pos (13U)
AnnaBridge 161:aa5281ff4a02 11169 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 11170 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11171 #define SDIO_CMD_CEATACMD_Pos (14U)
AnnaBridge 161:aa5281ff4a02 11172 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 11173 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
AnnaBridge 161:aa5281ff4a02 11174
AnnaBridge 161:aa5281ff4a02 11175 /***************** Bit definition for SDIO_RESPCMD register *****************/
AnnaBridge 161:aa5281ff4a02 11176 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11177 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
AnnaBridge 161:aa5281ff4a02 11178 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
AnnaBridge 161:aa5281ff4a02 11179
AnnaBridge 161:aa5281ff4a02 11180 /****************** Bit definition for SDIO_RESP0 register ******************/
AnnaBridge 161:aa5281ff4a02 11181 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11182 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11183 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
AnnaBridge 161:aa5281ff4a02 11184
AnnaBridge 161:aa5281ff4a02 11185 /****************** Bit definition for SDIO_RESP1 register ******************/
AnnaBridge 161:aa5281ff4a02 11186 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11187 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11188 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
AnnaBridge 161:aa5281ff4a02 11189
AnnaBridge 161:aa5281ff4a02 11190 /****************** Bit definition for SDIO_RESP2 register ******************/
AnnaBridge 161:aa5281ff4a02 11191 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11192 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11193 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
AnnaBridge 161:aa5281ff4a02 11194
AnnaBridge 161:aa5281ff4a02 11195 /****************** Bit definition for SDIO_RESP3 register ******************/
AnnaBridge 161:aa5281ff4a02 11196 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11197 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11198 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
AnnaBridge 161:aa5281ff4a02 11199
AnnaBridge 161:aa5281ff4a02 11200 /****************** Bit definition for SDIO_RESP4 register ******************/
AnnaBridge 161:aa5281ff4a02 11201 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11202 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11203 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
AnnaBridge 161:aa5281ff4a02 11204
AnnaBridge 161:aa5281ff4a02 11205 /****************** Bit definition for SDIO_DTIMER register *****************/
AnnaBridge 161:aa5281ff4a02 11206 #define SDIO_DTIMER_DATATIME_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11207 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11208 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
AnnaBridge 161:aa5281ff4a02 11209
AnnaBridge 161:aa5281ff4a02 11210 /****************** Bit definition for SDIO_DLEN register *******************/
AnnaBridge 161:aa5281ff4a02 11211 #define SDIO_DLEN_DATALENGTH_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11212 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
AnnaBridge 161:aa5281ff4a02 11213 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
AnnaBridge 161:aa5281ff4a02 11214
AnnaBridge 161:aa5281ff4a02 11215 /****************** Bit definition for SDIO_DCTRL register ******************/
AnnaBridge 161:aa5281ff4a02 11216 #define SDIO_DCTRL_DTEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11217 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11218 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
AnnaBridge 161:aa5281ff4a02 11219 #define SDIO_DCTRL_DTDIR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11220 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11221 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
AnnaBridge 161:aa5281ff4a02 11222 #define SDIO_DCTRL_DTMODE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11223 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11224 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
AnnaBridge 161:aa5281ff4a02 11225 #define SDIO_DCTRL_DMAEN_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11226 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11227 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
AnnaBridge 161:aa5281ff4a02 11228
AnnaBridge 161:aa5281ff4a02 11229 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11230 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 11231 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 161:aa5281ff4a02 11232 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 11233 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 11234 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 11235 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
AnnaBridge 161:aa5281ff4a02 11236
AnnaBridge 161:aa5281ff4a02 11237 #define SDIO_DCTRL_RWSTART_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11238 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11239 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
AnnaBridge 161:aa5281ff4a02 11240 #define SDIO_DCTRL_RWSTOP_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11241 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11242 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
AnnaBridge 161:aa5281ff4a02 11243 #define SDIO_DCTRL_RWMOD_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11244 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11245 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
AnnaBridge 161:aa5281ff4a02 11246 #define SDIO_DCTRL_SDIOEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 11247 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 11248 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
AnnaBridge 161:aa5281ff4a02 11249
AnnaBridge 161:aa5281ff4a02 11250 /****************** Bit definition for SDIO_DCOUNT register *****************/
AnnaBridge 161:aa5281ff4a02 11251 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11252 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
AnnaBridge 161:aa5281ff4a02 11253 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
AnnaBridge 161:aa5281ff4a02 11254
AnnaBridge 161:aa5281ff4a02 11255 /****************** Bit definition for SDIO_STA register ********************/
AnnaBridge 161:aa5281ff4a02 11256 #define SDIO_STA_CCRCFAIL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11257 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11258 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
AnnaBridge 161:aa5281ff4a02 11259 #define SDIO_STA_DCRCFAIL_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11260 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11261 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
AnnaBridge 161:aa5281ff4a02 11262 #define SDIO_STA_CTIMEOUT_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11263 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11264 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
AnnaBridge 161:aa5281ff4a02 11265 #define SDIO_STA_DTIMEOUT_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11266 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11267 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
AnnaBridge 161:aa5281ff4a02 11268 #define SDIO_STA_TXUNDERR_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11269 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 11270 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
AnnaBridge 161:aa5281ff4a02 11271 #define SDIO_STA_RXOVERR_Pos (5U)
AnnaBridge 161:aa5281ff4a02 11272 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 11273 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
AnnaBridge 161:aa5281ff4a02 11274 #define SDIO_STA_CMDREND_Pos (6U)
AnnaBridge 161:aa5281ff4a02 11275 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 11276 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
AnnaBridge 161:aa5281ff4a02 11277 #define SDIO_STA_CMDSENT_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11278 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11279 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
AnnaBridge 161:aa5281ff4a02 11280 #define SDIO_STA_DATAEND_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11281 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11282 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 161:aa5281ff4a02 11283 #define SDIO_STA_STBITERR_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11284 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11285 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
AnnaBridge 161:aa5281ff4a02 11286 #define SDIO_STA_DBCKEND_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11287 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11288 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
AnnaBridge 161:aa5281ff4a02 11289 #define SDIO_STA_CMDACT_Pos (11U)
AnnaBridge 161:aa5281ff4a02 11290 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 11291 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
AnnaBridge 161:aa5281ff4a02 11292 #define SDIO_STA_TXACT_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11293 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 11294 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
AnnaBridge 161:aa5281ff4a02 11295 #define SDIO_STA_RXACT_Pos (13U)
AnnaBridge 161:aa5281ff4a02 11296 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 11297 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
AnnaBridge 161:aa5281ff4a02 11298 #define SDIO_STA_TXFIFOHE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 11299 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 11300 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 161:aa5281ff4a02 11301 #define SDIO_STA_RXFIFOHF_Pos (15U)
AnnaBridge 161:aa5281ff4a02 11302 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 11303 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 161:aa5281ff4a02 11304 #define SDIO_STA_TXFIFOF_Pos (16U)
AnnaBridge 161:aa5281ff4a02 11305 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 11306 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
AnnaBridge 161:aa5281ff4a02 11307 #define SDIO_STA_RXFIFOF_Pos (17U)
AnnaBridge 161:aa5281ff4a02 11308 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 11309 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
AnnaBridge 161:aa5281ff4a02 11310 #define SDIO_STA_TXFIFOE_Pos (18U)
AnnaBridge 161:aa5281ff4a02 11311 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 11312 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
AnnaBridge 161:aa5281ff4a02 11313 #define SDIO_STA_RXFIFOE_Pos (19U)
AnnaBridge 161:aa5281ff4a02 11314 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 11315 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
AnnaBridge 161:aa5281ff4a02 11316 #define SDIO_STA_TXDAVL_Pos (20U)
AnnaBridge 161:aa5281ff4a02 11317 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 11318 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
AnnaBridge 161:aa5281ff4a02 11319 #define SDIO_STA_RXDAVL_Pos (21U)
AnnaBridge 161:aa5281ff4a02 11320 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 11321 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
AnnaBridge 161:aa5281ff4a02 11322 #define SDIO_STA_SDIOIT_Pos (22U)
AnnaBridge 161:aa5281ff4a02 11323 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 11324 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
AnnaBridge 161:aa5281ff4a02 11325 #define SDIO_STA_CEATAEND_Pos (23U)
AnnaBridge 161:aa5281ff4a02 11326 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 11327 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
AnnaBridge 161:aa5281ff4a02 11328
AnnaBridge 161:aa5281ff4a02 11329 /******************* Bit definition for SDIO_ICR register *******************/
AnnaBridge 161:aa5281ff4a02 11330 #define SDIO_ICR_CCRCFAILC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11331 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11332 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
AnnaBridge 161:aa5281ff4a02 11333 #define SDIO_ICR_DCRCFAILC_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11334 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11335 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
AnnaBridge 161:aa5281ff4a02 11336 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11337 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11338 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
AnnaBridge 161:aa5281ff4a02 11339 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11340 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11341 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
AnnaBridge 161:aa5281ff4a02 11342 #define SDIO_ICR_TXUNDERRC_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11343 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 11344 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
AnnaBridge 161:aa5281ff4a02 11345 #define SDIO_ICR_RXOVERRC_Pos (5U)
AnnaBridge 161:aa5281ff4a02 11346 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 11347 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
AnnaBridge 161:aa5281ff4a02 11348 #define SDIO_ICR_CMDRENDC_Pos (6U)
AnnaBridge 161:aa5281ff4a02 11349 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 11350 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
AnnaBridge 161:aa5281ff4a02 11351 #define SDIO_ICR_CMDSENTC_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11352 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11353 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
AnnaBridge 161:aa5281ff4a02 11354 #define SDIO_ICR_DATAENDC_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11355 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11356 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
AnnaBridge 161:aa5281ff4a02 11357 #define SDIO_ICR_STBITERRC_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11358 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11359 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
AnnaBridge 161:aa5281ff4a02 11360 #define SDIO_ICR_DBCKENDC_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11361 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11362 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
AnnaBridge 161:aa5281ff4a02 11363 #define SDIO_ICR_SDIOITC_Pos (22U)
AnnaBridge 161:aa5281ff4a02 11364 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 11365 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
AnnaBridge 161:aa5281ff4a02 11366 #define SDIO_ICR_CEATAENDC_Pos (23U)
AnnaBridge 161:aa5281ff4a02 11367 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 11368 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
AnnaBridge 161:aa5281ff4a02 11369
AnnaBridge 161:aa5281ff4a02 11370 /****************** Bit definition for SDIO_MASK register *******************/
AnnaBridge 161:aa5281ff4a02 11371 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11372 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11373 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11374 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11375 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11376 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11377 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11378 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11379 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11380 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11381 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11382 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11383 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11384 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 11385 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11386 #define SDIO_MASK_RXOVERRIE_Pos (5U)
AnnaBridge 161:aa5281ff4a02 11387 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 11388 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11389 #define SDIO_MASK_CMDRENDIE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 11390 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 11391 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11392 #define SDIO_MASK_CMDSENTIE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11393 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11394 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11395 #define SDIO_MASK_DATAENDIE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11396 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11397 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11398 #define SDIO_MASK_STBITERRIE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11399 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11400 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11401 #define SDIO_MASK_DBCKENDIE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11402 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11403 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11404 #define SDIO_MASK_CMDACTIE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 11405 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 11406 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11407 #define SDIO_MASK_TXACTIE_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11408 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 11409 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11410 #define SDIO_MASK_RXACTIE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 11411 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 11412 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
AnnaBridge 161:aa5281ff4a02 11413 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 11414 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 11415 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11416 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 11417 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 11418 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11419 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 11420 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 11421 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11422 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
AnnaBridge 161:aa5281ff4a02 11423 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 11424 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11425 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
AnnaBridge 161:aa5281ff4a02 11426 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 11427 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11428 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
AnnaBridge 161:aa5281ff4a02 11429 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 11430 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11431 #define SDIO_MASK_TXDAVLIE_Pos (20U)
AnnaBridge 161:aa5281ff4a02 11432 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 11433 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11434 #define SDIO_MASK_RXDAVLIE_Pos (21U)
AnnaBridge 161:aa5281ff4a02 11435 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 11436 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11437 #define SDIO_MASK_SDIOITIE_Pos (22U)
AnnaBridge 161:aa5281ff4a02 11438 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 11439 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11440 #define SDIO_MASK_CEATAENDIE_Pos (23U)
AnnaBridge 161:aa5281ff4a02 11441 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 11442 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11443
AnnaBridge 161:aa5281ff4a02 11444 /***************** Bit definition for SDIO_FIFOCNT register *****************/
AnnaBridge 161:aa5281ff4a02 11445 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11446 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
AnnaBridge 161:aa5281ff4a02 11447 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
AnnaBridge 161:aa5281ff4a02 11448
AnnaBridge 161:aa5281ff4a02 11449 /****************** Bit definition for SDIO_FIFO register *******************/
AnnaBridge 161:aa5281ff4a02 11450 #define SDIO_FIFO_FIFODATA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11451 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 11452 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
AnnaBridge 161:aa5281ff4a02 11453
AnnaBridge 161:aa5281ff4a02 11454 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 11455 /* */
AnnaBridge 161:aa5281ff4a02 11456 /* Serial Peripheral Interface */
AnnaBridge 161:aa5281ff4a02 11457 /* */
AnnaBridge 161:aa5281ff4a02 11458 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 11459 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
AnnaBridge 161:aa5281ff4a02 11460
AnnaBridge 161:aa5281ff4a02 11461 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 161:aa5281ff4a02 11462 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11463 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11464 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
AnnaBridge 161:aa5281ff4a02 11465 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11466 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11467 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 161:aa5281ff4a02 11468 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11469 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11470 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
AnnaBridge 161:aa5281ff4a02 11471
AnnaBridge 161:aa5281ff4a02 11472 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11473 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 161:aa5281ff4a02 11474 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
AnnaBridge 161:aa5281ff4a02 11475 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11476 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 11477 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 11478
AnnaBridge 161:aa5281ff4a02 11479 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 11480 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 11481 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
AnnaBridge 161:aa5281ff4a02 11482 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11483 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11484 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
AnnaBridge 161:aa5281ff4a02 11485 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11486 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11487 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
AnnaBridge 161:aa5281ff4a02 11488 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11489 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11490 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
AnnaBridge 161:aa5281ff4a02 11491 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11492 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11493 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
AnnaBridge 161:aa5281ff4a02 11494 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 161:aa5281ff4a02 11495 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 11496 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
AnnaBridge 161:aa5281ff4a02 11497 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11498 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 11499 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
AnnaBridge 161:aa5281ff4a02 11500 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 161:aa5281ff4a02 11501 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 11502 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
AnnaBridge 161:aa5281ff4a02 11503 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 11504 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 11505 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
AnnaBridge 161:aa5281ff4a02 11506 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 11507 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 11508 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
AnnaBridge 161:aa5281ff4a02 11509
AnnaBridge 161:aa5281ff4a02 11510 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 161:aa5281ff4a02 11511 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11512 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11513 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
AnnaBridge 161:aa5281ff4a02 11514 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11515 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11516 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
AnnaBridge 161:aa5281ff4a02 11517 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11518 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11519 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
AnnaBridge 161:aa5281ff4a02 11520 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11521 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 11522 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
AnnaBridge 161:aa5281ff4a02 11523 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 161:aa5281ff4a02 11524 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 11525 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11526 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 11527 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 11528 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11529 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11530 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11531 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 11532
AnnaBridge 161:aa5281ff4a02 11533 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 161:aa5281ff4a02 11534 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11535 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11536 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
AnnaBridge 161:aa5281ff4a02 11537 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11538 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11539 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
AnnaBridge 161:aa5281ff4a02 11540 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11541 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11542 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
AnnaBridge 161:aa5281ff4a02 11543 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11544 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11545 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
AnnaBridge 161:aa5281ff4a02 11546 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11547 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 11548 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
AnnaBridge 161:aa5281ff4a02 11549 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 161:aa5281ff4a02 11550 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 11551 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
AnnaBridge 161:aa5281ff4a02 11552 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 161:aa5281ff4a02 11553 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 11554 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 161:aa5281ff4a02 11555 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11556 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11557 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
AnnaBridge 161:aa5281ff4a02 11558 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11559 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11560 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
AnnaBridge 161:aa5281ff4a02 11561
AnnaBridge 161:aa5281ff4a02 11562 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 161:aa5281ff4a02 11563 #define SPI_DR_DR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11564 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 11565 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
AnnaBridge 161:aa5281ff4a02 11566
AnnaBridge 161:aa5281ff4a02 11567 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 161:aa5281ff4a02 11568 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11569 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 11570 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
AnnaBridge 161:aa5281ff4a02 11571
AnnaBridge 161:aa5281ff4a02 11572 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 161:aa5281ff4a02 11573 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11574 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 11575 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
AnnaBridge 161:aa5281ff4a02 11576
AnnaBridge 161:aa5281ff4a02 11577 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 161:aa5281ff4a02 11578 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11579 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 11580 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
AnnaBridge 161:aa5281ff4a02 11581
AnnaBridge 161:aa5281ff4a02 11582 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 161:aa5281ff4a02 11583 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11584 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11585 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 161:aa5281ff4a02 11586
AnnaBridge 161:aa5281ff4a02 11587 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11588 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 161:aa5281ff4a02 11589 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 161:aa5281ff4a02 11590 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11591 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11592
AnnaBridge 161:aa5281ff4a02 11593 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11594 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11595 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 161:aa5281ff4a02 11596
AnnaBridge 161:aa5281ff4a02 11597 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11598 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 11599 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 161:aa5281ff4a02 11600 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 11601 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 11602
AnnaBridge 161:aa5281ff4a02 11603 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11604 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11605 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 161:aa5281ff4a02 11606
AnnaBridge 161:aa5281ff4a02 11607 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11608 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 11609 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 161:aa5281ff4a02 11610 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11611 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11612
AnnaBridge 161:aa5281ff4a02 11613 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11614 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11615 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 161:aa5281ff4a02 11616 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 161:aa5281ff4a02 11617 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 11618 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 161:aa5281ff4a02 11619
AnnaBridge 161:aa5281ff4a02 11620 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 161:aa5281ff4a02 11621 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11622 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 11623 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 161:aa5281ff4a02 11624 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11625 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11626 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 161:aa5281ff4a02 11627 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11628 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11629 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 161:aa5281ff4a02 11630
AnnaBridge 161:aa5281ff4a02 11631 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 11632 /* */
AnnaBridge 161:aa5281ff4a02 11633 /* SYSCFG */
AnnaBridge 161:aa5281ff4a02 11634 /* */
AnnaBridge 161:aa5281ff4a02 11635 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 11636 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 161:aa5281ff4a02 11637 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11638 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 11639 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 161:aa5281ff4a02 11640 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11641 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11642 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 161:aa5281ff4a02 11643 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
AnnaBridge 161:aa5281ff4a02 11644 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 11645 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
AnnaBridge 161:aa5281ff4a02 11646 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
AnnaBridge 161:aa5281ff4a02 11647 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
AnnaBridge 161:aa5281ff4a02 11648
AnnaBridge 161:aa5281ff4a02 11649 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 161:aa5281ff4a02 11650 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11651 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 11652 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 161:aa5281ff4a02 11653 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11654 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 11655 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 161:aa5281ff4a02 11656 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11657 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 11658 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 161:aa5281ff4a02 11659 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11660 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 161:aa5281ff4a02 11661 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 161:aa5281ff4a02 11662 /**
AnnaBridge 161:aa5281ff4a02 11663 * @brief EXTI0 configuration
AnnaBridge 161:aa5281ff4a02 11664 */
AnnaBridge 161:aa5281ff4a02 11665 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 161:aa5281ff4a02 11666 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 161:aa5281ff4a02 11667 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 161:aa5281ff4a02 11668 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
AnnaBridge 161:aa5281ff4a02 11669 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
AnnaBridge 161:aa5281ff4a02 11670 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
AnnaBridge 161:aa5281ff4a02 11671 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
AnnaBridge 161:aa5281ff4a02 11672 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 161:aa5281ff4a02 11673 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
AnnaBridge 161:aa5281ff4a02 11674
AnnaBridge 161:aa5281ff4a02 11675 /**
AnnaBridge 161:aa5281ff4a02 11676 * @brief EXTI1 configuration
AnnaBridge 161:aa5281ff4a02 11677 */
AnnaBridge 161:aa5281ff4a02 11678 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 161:aa5281ff4a02 11679 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 161:aa5281ff4a02 11680 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 161:aa5281ff4a02 11681 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
AnnaBridge 161:aa5281ff4a02 11682 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
AnnaBridge 161:aa5281ff4a02 11683 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
AnnaBridge 161:aa5281ff4a02 11684 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
AnnaBridge 161:aa5281ff4a02 11685 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 161:aa5281ff4a02 11686 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
AnnaBridge 161:aa5281ff4a02 11687
AnnaBridge 161:aa5281ff4a02 11688 /**
AnnaBridge 161:aa5281ff4a02 11689 * @brief EXTI2 configuration
AnnaBridge 161:aa5281ff4a02 11690 */
AnnaBridge 161:aa5281ff4a02 11691 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 161:aa5281ff4a02 11692 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 161:aa5281ff4a02 11693 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 161:aa5281ff4a02 11694 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
AnnaBridge 161:aa5281ff4a02 11695 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
AnnaBridge 161:aa5281ff4a02 11696 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
AnnaBridge 161:aa5281ff4a02 11697 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
AnnaBridge 161:aa5281ff4a02 11698 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 161:aa5281ff4a02 11699 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
AnnaBridge 161:aa5281ff4a02 11700
AnnaBridge 161:aa5281ff4a02 11701 /**
AnnaBridge 161:aa5281ff4a02 11702 * @brief EXTI3 configuration
AnnaBridge 161:aa5281ff4a02 11703 */
AnnaBridge 161:aa5281ff4a02 11704 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 161:aa5281ff4a02 11705 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 161:aa5281ff4a02 11706 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 161:aa5281ff4a02 11707 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
AnnaBridge 161:aa5281ff4a02 11708 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
AnnaBridge 161:aa5281ff4a02 11709 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
AnnaBridge 161:aa5281ff4a02 11710 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
AnnaBridge 161:aa5281ff4a02 11711 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
AnnaBridge 161:aa5281ff4a02 11712 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
AnnaBridge 161:aa5281ff4a02 11713
AnnaBridge 161:aa5281ff4a02 11714 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 161:aa5281ff4a02 11715 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11716 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 11717 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 161:aa5281ff4a02 11718 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11719 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 11720 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 161:aa5281ff4a02 11721 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11722 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 11723 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 161:aa5281ff4a02 11724 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11725 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 161:aa5281ff4a02 11726 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 161:aa5281ff4a02 11727
AnnaBridge 161:aa5281ff4a02 11728 /**
AnnaBridge 161:aa5281ff4a02 11729 * @brief EXTI4 configuration
AnnaBridge 161:aa5281ff4a02 11730 */
AnnaBridge 161:aa5281ff4a02 11731 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 161:aa5281ff4a02 11732 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 161:aa5281ff4a02 11733 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 161:aa5281ff4a02 11734 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
AnnaBridge 161:aa5281ff4a02 11735 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
AnnaBridge 161:aa5281ff4a02 11736 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
AnnaBridge 161:aa5281ff4a02 11737 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
AnnaBridge 161:aa5281ff4a02 11738 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 161:aa5281ff4a02 11739 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
AnnaBridge 161:aa5281ff4a02 11740
AnnaBridge 161:aa5281ff4a02 11741 /**
AnnaBridge 161:aa5281ff4a02 11742 * @brief EXTI5 configuration
AnnaBridge 161:aa5281ff4a02 11743 */
AnnaBridge 161:aa5281ff4a02 11744 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 161:aa5281ff4a02 11745 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 161:aa5281ff4a02 11746 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 161:aa5281ff4a02 11747 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
AnnaBridge 161:aa5281ff4a02 11748 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
AnnaBridge 161:aa5281ff4a02 11749 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
AnnaBridge 161:aa5281ff4a02 11750 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
AnnaBridge 161:aa5281ff4a02 11751 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 161:aa5281ff4a02 11752 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
AnnaBridge 161:aa5281ff4a02 11753
AnnaBridge 161:aa5281ff4a02 11754 /**
AnnaBridge 161:aa5281ff4a02 11755 * @brief EXTI6 configuration
AnnaBridge 161:aa5281ff4a02 11756 */
AnnaBridge 161:aa5281ff4a02 11757 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 161:aa5281ff4a02 11758 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 161:aa5281ff4a02 11759 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 161:aa5281ff4a02 11760 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
AnnaBridge 161:aa5281ff4a02 11761 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
AnnaBridge 161:aa5281ff4a02 11762 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
AnnaBridge 161:aa5281ff4a02 11763 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
AnnaBridge 161:aa5281ff4a02 11764 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 161:aa5281ff4a02 11765 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
AnnaBridge 161:aa5281ff4a02 11766
AnnaBridge 161:aa5281ff4a02 11767 /**
AnnaBridge 161:aa5281ff4a02 11768 * @brief EXTI7 configuration
AnnaBridge 161:aa5281ff4a02 11769 */
AnnaBridge 161:aa5281ff4a02 11770 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 161:aa5281ff4a02 11771 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 161:aa5281ff4a02 11772 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 161:aa5281ff4a02 11773 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
AnnaBridge 161:aa5281ff4a02 11774 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
AnnaBridge 161:aa5281ff4a02 11775 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
AnnaBridge 161:aa5281ff4a02 11776 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
AnnaBridge 161:aa5281ff4a02 11777 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
AnnaBridge 161:aa5281ff4a02 11778 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
AnnaBridge 161:aa5281ff4a02 11779
AnnaBridge 161:aa5281ff4a02 11780 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 161:aa5281ff4a02 11781 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11782 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 11783 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 161:aa5281ff4a02 11784 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11785 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 11786 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 161:aa5281ff4a02 11787 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11788 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 11789 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 161:aa5281ff4a02 11790 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11791 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 161:aa5281ff4a02 11792 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 161:aa5281ff4a02 11793
AnnaBridge 161:aa5281ff4a02 11794 /**
AnnaBridge 161:aa5281ff4a02 11795 * @brief EXTI8 configuration
AnnaBridge 161:aa5281ff4a02 11796 */
AnnaBridge 161:aa5281ff4a02 11797 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 161:aa5281ff4a02 11798 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 161:aa5281ff4a02 11799 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 161:aa5281ff4a02 11800 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
AnnaBridge 161:aa5281ff4a02 11801 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
AnnaBridge 161:aa5281ff4a02 11802 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
AnnaBridge 161:aa5281ff4a02 11803 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
AnnaBridge 161:aa5281ff4a02 11804 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 161:aa5281ff4a02 11805 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
AnnaBridge 161:aa5281ff4a02 11806
AnnaBridge 161:aa5281ff4a02 11807 /**
AnnaBridge 161:aa5281ff4a02 11808 * @brief EXTI9 configuration
AnnaBridge 161:aa5281ff4a02 11809 */
AnnaBridge 161:aa5281ff4a02 11810 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 161:aa5281ff4a02 11811 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 161:aa5281ff4a02 11812 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 161:aa5281ff4a02 11813 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
AnnaBridge 161:aa5281ff4a02 11814 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
AnnaBridge 161:aa5281ff4a02 11815 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
AnnaBridge 161:aa5281ff4a02 11816 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
AnnaBridge 161:aa5281ff4a02 11817 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 161:aa5281ff4a02 11818 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
AnnaBridge 161:aa5281ff4a02 11819
AnnaBridge 161:aa5281ff4a02 11820 /**
AnnaBridge 161:aa5281ff4a02 11821 * @brief EXTI10 configuration
AnnaBridge 161:aa5281ff4a02 11822 */
AnnaBridge 161:aa5281ff4a02 11823 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 161:aa5281ff4a02 11824 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 161:aa5281ff4a02 11825 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 161:aa5281ff4a02 11826 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
AnnaBridge 161:aa5281ff4a02 11827 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
AnnaBridge 161:aa5281ff4a02 11828 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
AnnaBridge 161:aa5281ff4a02 11829 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
AnnaBridge 161:aa5281ff4a02 11830 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 161:aa5281ff4a02 11831 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
AnnaBridge 161:aa5281ff4a02 11832
AnnaBridge 161:aa5281ff4a02 11833 /**
AnnaBridge 161:aa5281ff4a02 11834 * @brief EXTI11 configuration
AnnaBridge 161:aa5281ff4a02 11835 */
AnnaBridge 161:aa5281ff4a02 11836 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 161:aa5281ff4a02 11837 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 161:aa5281ff4a02 11838 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 161:aa5281ff4a02 11839 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
AnnaBridge 161:aa5281ff4a02 11840 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
AnnaBridge 161:aa5281ff4a02 11841 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
AnnaBridge 161:aa5281ff4a02 11842 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
AnnaBridge 161:aa5281ff4a02 11843 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
AnnaBridge 161:aa5281ff4a02 11844 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
AnnaBridge 161:aa5281ff4a02 11845
AnnaBridge 161:aa5281ff4a02 11846 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 161:aa5281ff4a02 11847 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11848 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 11849 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 161:aa5281ff4a02 11850 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11851 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 11852 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 161:aa5281ff4a02 11853 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11854 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 11855 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 161:aa5281ff4a02 11856 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11857 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 161:aa5281ff4a02 11858 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 161:aa5281ff4a02 11859
AnnaBridge 161:aa5281ff4a02 11860 /**
AnnaBridge 161:aa5281ff4a02 11861 * @brief EXTI12 configuration
AnnaBridge 161:aa5281ff4a02 11862 */
AnnaBridge 161:aa5281ff4a02 11863 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 161:aa5281ff4a02 11864 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 161:aa5281ff4a02 11865 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 161:aa5281ff4a02 11866 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
AnnaBridge 161:aa5281ff4a02 11867 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
AnnaBridge 161:aa5281ff4a02 11868 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
AnnaBridge 161:aa5281ff4a02 11869 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
AnnaBridge 161:aa5281ff4a02 11870 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 161:aa5281ff4a02 11871
AnnaBridge 161:aa5281ff4a02 11872 /**
AnnaBridge 161:aa5281ff4a02 11873 * @brief EXTI13 configuration
AnnaBridge 161:aa5281ff4a02 11874 */
AnnaBridge 161:aa5281ff4a02 11875 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 161:aa5281ff4a02 11876 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 161:aa5281ff4a02 11877 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 161:aa5281ff4a02 11878 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
AnnaBridge 161:aa5281ff4a02 11879 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
AnnaBridge 161:aa5281ff4a02 11880 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
AnnaBridge 161:aa5281ff4a02 11881 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
AnnaBridge 161:aa5281ff4a02 11882 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 161:aa5281ff4a02 11883
AnnaBridge 161:aa5281ff4a02 11884 /**
AnnaBridge 161:aa5281ff4a02 11885 * @brief EXTI14 configuration
AnnaBridge 161:aa5281ff4a02 11886 */
AnnaBridge 161:aa5281ff4a02 11887 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 161:aa5281ff4a02 11888 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 161:aa5281ff4a02 11889 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 161:aa5281ff4a02 11890 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
AnnaBridge 161:aa5281ff4a02 11891 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
AnnaBridge 161:aa5281ff4a02 11892 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
AnnaBridge 161:aa5281ff4a02 11893 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
AnnaBridge 161:aa5281ff4a02 11894 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 161:aa5281ff4a02 11895
AnnaBridge 161:aa5281ff4a02 11896 /**
AnnaBridge 161:aa5281ff4a02 11897 * @brief EXTI15 configuration
AnnaBridge 161:aa5281ff4a02 11898 */
AnnaBridge 161:aa5281ff4a02 11899 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 161:aa5281ff4a02 11900 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 161:aa5281ff4a02 11901 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 161:aa5281ff4a02 11902 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
AnnaBridge 161:aa5281ff4a02 11903 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
AnnaBridge 161:aa5281ff4a02 11904 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
AnnaBridge 161:aa5281ff4a02 11905 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
AnnaBridge 161:aa5281ff4a02 11906 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 161:aa5281ff4a02 11907
AnnaBridge 161:aa5281ff4a02 11908 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 161:aa5281ff4a02 11909 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11910 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11911 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
AnnaBridge 161:aa5281ff4a02 11912 #define SYSCFG_CMPCR_READY_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11913 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11914 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
AnnaBridge 161:aa5281ff4a02 11915
AnnaBridge 161:aa5281ff4a02 11916 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 11917 /* */
AnnaBridge 161:aa5281ff4a02 11918 /* TIM */
AnnaBridge 161:aa5281ff4a02 11919 /* */
AnnaBridge 161:aa5281ff4a02 11920 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 11921 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 161:aa5281ff4a02 11922 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11923 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11924 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 161:aa5281ff4a02 11925 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 11926 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 11927 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 161:aa5281ff4a02 11928 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11929 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11930 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 161:aa5281ff4a02 11931 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11932 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11933 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 161:aa5281ff4a02 11934 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11935 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 11936 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 161:aa5281ff4a02 11937
AnnaBridge 161:aa5281ff4a02 11938 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 161:aa5281ff4a02 11939 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 161:aa5281ff4a02 11940 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 161:aa5281ff4a02 11941 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 11942 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 11943
AnnaBridge 161:aa5281ff4a02 11944 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11945 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11946 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 161:aa5281ff4a02 11947
AnnaBridge 161:aa5281ff4a02 11948 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11949 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 11950 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 161:aa5281ff4a02 11951 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
AnnaBridge 161:aa5281ff4a02 11952 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
AnnaBridge 161:aa5281ff4a02 11953
AnnaBridge 161:aa5281ff4a02 11954 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 161:aa5281ff4a02 11955 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11956 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 11957 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 161:aa5281ff4a02 11958 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 11959 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 11960 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 161:aa5281ff4a02 11961 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 161:aa5281ff4a02 11962 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 11963 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 161:aa5281ff4a02 11964
AnnaBridge 161:aa5281ff4a02 11965 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 11966 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 11967 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 161:aa5281ff4a02 11968 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 11969 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 11970 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 11971
AnnaBridge 161:aa5281ff4a02 11972 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 161:aa5281ff4a02 11973 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 11974 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 161:aa5281ff4a02 11975 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 161:aa5281ff4a02 11976 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 11977 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 161:aa5281ff4a02 11978 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 161:aa5281ff4a02 11979 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 11980 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 161:aa5281ff4a02 11981 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 161:aa5281ff4a02 11982 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 11983 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 161:aa5281ff4a02 11984 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 161:aa5281ff4a02 11985 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 11986 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 161:aa5281ff4a02 11987 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 161:aa5281ff4a02 11988 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 11989 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 161:aa5281ff4a02 11990 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 161:aa5281ff4a02 11991 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 11992 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 161:aa5281ff4a02 11993 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 161:aa5281ff4a02 11994 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 11995 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 161:aa5281ff4a02 11996
AnnaBridge 161:aa5281ff4a02 11997 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 161:aa5281ff4a02 11998 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 11999 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 161:aa5281ff4a02 12000 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 161:aa5281ff4a02 12001 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
AnnaBridge 161:aa5281ff4a02 12002 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
AnnaBridge 161:aa5281ff4a02 12003 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
AnnaBridge 161:aa5281ff4a02 12004
AnnaBridge 161:aa5281ff4a02 12005 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12006 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 12007 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 161:aa5281ff4a02 12008 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12009 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 12010 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12011
AnnaBridge 161:aa5281ff4a02 12012 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12013 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12014 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 161:aa5281ff4a02 12015
AnnaBridge 161:aa5281ff4a02 12016 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12017 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 161:aa5281ff4a02 12018 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 161:aa5281ff4a02 12019 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
AnnaBridge 161:aa5281ff4a02 12020 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
AnnaBridge 161:aa5281ff4a02 12021 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
AnnaBridge 161:aa5281ff4a02 12022 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
AnnaBridge 161:aa5281ff4a02 12023
AnnaBridge 161:aa5281ff4a02 12024 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12025 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 161:aa5281ff4a02 12026 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 161:aa5281ff4a02 12027 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
AnnaBridge 161:aa5281ff4a02 12028 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
AnnaBridge 161:aa5281ff4a02 12029
AnnaBridge 161:aa5281ff4a02 12030 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 12031 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 12032 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 161:aa5281ff4a02 12033 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 161:aa5281ff4a02 12034 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 12035 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 161:aa5281ff4a02 12036
AnnaBridge 161:aa5281ff4a02 12037 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 161:aa5281ff4a02 12038 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12039 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12040 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 161:aa5281ff4a02 12041 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12042 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12043 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 161:aa5281ff4a02 12044 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12045 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12046 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 161:aa5281ff4a02 12047 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12048 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12049 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 161:aa5281ff4a02 12050 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12051 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12052 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 161:aa5281ff4a02 12053 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12054 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12055 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 161:aa5281ff4a02 12056 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12057 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12058 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 161:aa5281ff4a02 12059 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12060 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12061 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 161:aa5281ff4a02 12062 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12063 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 12064 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 161:aa5281ff4a02 12065 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12066 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12067 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 161:aa5281ff4a02 12068 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12069 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12070 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 161:aa5281ff4a02 12071 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12072 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12073 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 161:aa5281ff4a02 12074 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12075 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 12076 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 161:aa5281ff4a02 12077 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 12078 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 12079 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 161:aa5281ff4a02 12080 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 12081 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 12082 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 161:aa5281ff4a02 12083
AnnaBridge 161:aa5281ff4a02 12084 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 161:aa5281ff4a02 12085 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12086 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12087 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12088 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12089 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12090 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12091 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12092 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12093 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12094 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12095 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12096 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12097 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12098 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12099 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12100 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12101 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12102 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12103 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12104 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12105 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12106 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12107 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12108 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12109 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12110 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12111 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 161:aa5281ff4a02 12112 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12113 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12114 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 161:aa5281ff4a02 12115 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12116 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12117 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 161:aa5281ff4a02 12118 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12119 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 12120 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 161:aa5281ff4a02 12121
AnnaBridge 161:aa5281ff4a02 12122 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 161:aa5281ff4a02 12123 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12124 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12125 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 161:aa5281ff4a02 12126 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12127 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12128 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 161:aa5281ff4a02 12129 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12130 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12131 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 161:aa5281ff4a02 12132 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12133 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12134 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 161:aa5281ff4a02 12135 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12136 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12137 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 161:aa5281ff4a02 12138 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12139 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12140 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 161:aa5281ff4a02 12141 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12142 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12143 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 161:aa5281ff4a02 12144 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12145 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12146 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 161:aa5281ff4a02 12147
AnnaBridge 161:aa5281ff4a02 12148 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 161:aa5281ff4a02 12149 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12150 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 12151 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 161:aa5281ff4a02 12152 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
AnnaBridge 161:aa5281ff4a02 12153 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
AnnaBridge 161:aa5281ff4a02 12154
AnnaBridge 161:aa5281ff4a02 12155 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12156 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12157 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 161:aa5281ff4a02 12158 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12159 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12160 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 161:aa5281ff4a02 12161
AnnaBridge 161:aa5281ff4a02 12162 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12163 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 12164 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 161:aa5281ff4a02 12165 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12166 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 12167 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12168
AnnaBridge 161:aa5281ff4a02 12169 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12170 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12171 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 161:aa5281ff4a02 12172
AnnaBridge 161:aa5281ff4a02 12173 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12174 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 12175 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 161:aa5281ff4a02 12176 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
AnnaBridge 161:aa5281ff4a02 12177 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
AnnaBridge 161:aa5281ff4a02 12178
AnnaBridge 161:aa5281ff4a02 12179 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12180 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12181 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 161:aa5281ff4a02 12182 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12183 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12184 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 161:aa5281ff4a02 12185
AnnaBridge 161:aa5281ff4a02 12186 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12187 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 161:aa5281ff4a02 12188 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 161:aa5281ff4a02 12189 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
AnnaBridge 161:aa5281ff4a02 12190 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
AnnaBridge 161:aa5281ff4a02 12191 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
AnnaBridge 161:aa5281ff4a02 12192
AnnaBridge 161:aa5281ff4a02 12193 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 12194 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 12195 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 161:aa5281ff4a02 12196
AnnaBridge 161:aa5281ff4a02 12197 /*----------------------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 12198
AnnaBridge 161:aa5281ff4a02 12199 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12200 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 12201 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 161:aa5281ff4a02 12202 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
AnnaBridge 161:aa5281ff4a02 12203 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
AnnaBridge 161:aa5281ff4a02 12204
AnnaBridge 161:aa5281ff4a02 12205 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12206 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 12207 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 161:aa5281ff4a02 12208 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12209 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 12210 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12211 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
AnnaBridge 161:aa5281ff4a02 12212
AnnaBridge 161:aa5281ff4a02 12213 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12214 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 161:aa5281ff4a02 12215 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 161:aa5281ff4a02 12216 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
AnnaBridge 161:aa5281ff4a02 12217 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
AnnaBridge 161:aa5281ff4a02 12218
AnnaBridge 161:aa5281ff4a02 12219 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12220 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 161:aa5281ff4a02 12221 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 161:aa5281ff4a02 12222 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
AnnaBridge 161:aa5281ff4a02 12223 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
AnnaBridge 161:aa5281ff4a02 12224 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
AnnaBridge 161:aa5281ff4a02 12225 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
AnnaBridge 161:aa5281ff4a02 12226
AnnaBridge 161:aa5281ff4a02 12227 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 161:aa5281ff4a02 12228 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12229 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 12230 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 161:aa5281ff4a02 12231 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
AnnaBridge 161:aa5281ff4a02 12232 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
AnnaBridge 161:aa5281ff4a02 12233
AnnaBridge 161:aa5281ff4a02 12234 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12235 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12236 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 161:aa5281ff4a02 12237 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12238 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12239 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 161:aa5281ff4a02 12240
AnnaBridge 161:aa5281ff4a02 12241 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12242 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 12243 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 161:aa5281ff4a02 12244 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12245 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 12246 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12247
AnnaBridge 161:aa5281ff4a02 12248 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12249 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12250 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 161:aa5281ff4a02 12251
AnnaBridge 161:aa5281ff4a02 12252 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12253 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 12254 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 161:aa5281ff4a02 12255 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
AnnaBridge 161:aa5281ff4a02 12256 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
AnnaBridge 161:aa5281ff4a02 12257
AnnaBridge 161:aa5281ff4a02 12258 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12259 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12260 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 161:aa5281ff4a02 12261 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12262 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12263 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 161:aa5281ff4a02 12264
AnnaBridge 161:aa5281ff4a02 12265 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12266 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 161:aa5281ff4a02 12267 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 161:aa5281ff4a02 12268 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
AnnaBridge 161:aa5281ff4a02 12269 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
AnnaBridge 161:aa5281ff4a02 12270 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
AnnaBridge 161:aa5281ff4a02 12271
AnnaBridge 161:aa5281ff4a02 12272 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 12273 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 12274 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 161:aa5281ff4a02 12275
AnnaBridge 161:aa5281ff4a02 12276 /*----------------------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 12277
AnnaBridge 161:aa5281ff4a02 12278 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12279 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 12280 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 161:aa5281ff4a02 12281 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
AnnaBridge 161:aa5281ff4a02 12282 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
AnnaBridge 161:aa5281ff4a02 12283
AnnaBridge 161:aa5281ff4a02 12284 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12285 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 161:aa5281ff4a02 12286 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 161:aa5281ff4a02 12287 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12288 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 12289 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12290 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
AnnaBridge 161:aa5281ff4a02 12291
AnnaBridge 161:aa5281ff4a02 12292 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12293 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 161:aa5281ff4a02 12294 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 161:aa5281ff4a02 12295 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
AnnaBridge 161:aa5281ff4a02 12296 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
AnnaBridge 161:aa5281ff4a02 12297
AnnaBridge 161:aa5281ff4a02 12298 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12299 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 161:aa5281ff4a02 12300 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 161:aa5281ff4a02 12301 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
AnnaBridge 161:aa5281ff4a02 12302 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
AnnaBridge 161:aa5281ff4a02 12303 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
AnnaBridge 161:aa5281ff4a02 12304 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
AnnaBridge 161:aa5281ff4a02 12305
AnnaBridge 161:aa5281ff4a02 12306 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 161:aa5281ff4a02 12307 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12308 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12309 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 161:aa5281ff4a02 12310 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12311 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12312 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 161:aa5281ff4a02 12313 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12314 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12315 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 161:aa5281ff4a02 12316 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12317 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12318 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 161:aa5281ff4a02 12319 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12320 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12321 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 161:aa5281ff4a02 12322 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12323 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12324 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 161:aa5281ff4a02 12325 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12326 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12327 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 161:aa5281ff4a02 12328 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12329 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12330 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 161:aa5281ff4a02 12331 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12332 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 12333 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 161:aa5281ff4a02 12334 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12335 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12336 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 161:aa5281ff4a02 12337 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12338 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12339 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 161:aa5281ff4a02 12340 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12341 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12342 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 161:aa5281ff4a02 12343 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12344 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 12345 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 161:aa5281ff4a02 12346 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 161:aa5281ff4a02 12347 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 12348 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 161:aa5281ff4a02 12349 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 161:aa5281ff4a02 12350 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 12351 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 161:aa5281ff4a02 12352
AnnaBridge 161:aa5281ff4a02 12353 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 161:aa5281ff4a02 12354 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12355 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 12356 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 161:aa5281ff4a02 12357
AnnaBridge 161:aa5281ff4a02 12358 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 161:aa5281ff4a02 12359 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12360 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 12361 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 161:aa5281ff4a02 12362
AnnaBridge 161:aa5281ff4a02 12363 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 161:aa5281ff4a02 12364 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12365 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 12366 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 161:aa5281ff4a02 12367
AnnaBridge 161:aa5281ff4a02 12368 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 161:aa5281ff4a02 12369 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12370 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 12371 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 161:aa5281ff4a02 12372
AnnaBridge 161:aa5281ff4a02 12373 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 161:aa5281ff4a02 12374 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12375 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 12376 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 161:aa5281ff4a02 12377
AnnaBridge 161:aa5281ff4a02 12378 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 161:aa5281ff4a02 12379 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12380 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 12381 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 161:aa5281ff4a02 12382
AnnaBridge 161:aa5281ff4a02 12383 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 161:aa5281ff4a02 12384 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12385 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 12386 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 161:aa5281ff4a02 12387
AnnaBridge 161:aa5281ff4a02 12388 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 161:aa5281ff4a02 12389 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12390 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 12391 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 161:aa5281ff4a02 12392
AnnaBridge 161:aa5281ff4a02 12393 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 161:aa5281ff4a02 12394 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12395 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 12396 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 161:aa5281ff4a02 12397 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
AnnaBridge 161:aa5281ff4a02 12398 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
AnnaBridge 161:aa5281ff4a02 12399 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
AnnaBridge 161:aa5281ff4a02 12400 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
AnnaBridge 161:aa5281ff4a02 12401 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12402 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 12403 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12404 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
AnnaBridge 161:aa5281ff4a02 12405
AnnaBridge 161:aa5281ff4a02 12406 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12407 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 12408 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 161:aa5281ff4a02 12409 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
AnnaBridge 161:aa5281ff4a02 12410 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
AnnaBridge 161:aa5281ff4a02 12411
AnnaBridge 161:aa5281ff4a02 12412 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12413 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12414 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 161:aa5281ff4a02 12415 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12416 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12417 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 161:aa5281ff4a02 12418 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12419 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 12420 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 161:aa5281ff4a02 12421 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 161:aa5281ff4a02 12422 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 12423 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 161:aa5281ff4a02 12424 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 12425 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 12426 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 161:aa5281ff4a02 12427 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 12428 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 12429 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 161:aa5281ff4a02 12430
AnnaBridge 161:aa5281ff4a02 12431 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 161:aa5281ff4a02 12432 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12433 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 161:aa5281ff4a02 12434 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 161:aa5281ff4a02 12435 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
AnnaBridge 161:aa5281ff4a02 12436 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
AnnaBridge 161:aa5281ff4a02 12437 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
AnnaBridge 161:aa5281ff4a02 12438 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
AnnaBridge 161:aa5281ff4a02 12439 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12440
AnnaBridge 161:aa5281ff4a02 12441 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12442 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 161:aa5281ff4a02 12443 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 161:aa5281ff4a02 12444 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
AnnaBridge 161:aa5281ff4a02 12445 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
AnnaBridge 161:aa5281ff4a02 12446 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
AnnaBridge 161:aa5281ff4a02 12447 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
AnnaBridge 161:aa5281ff4a02 12448 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
AnnaBridge 161:aa5281ff4a02 12449
AnnaBridge 161:aa5281ff4a02 12450 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 161:aa5281ff4a02 12451 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12452 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 12453 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 161:aa5281ff4a02 12454
AnnaBridge 161:aa5281ff4a02 12455 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 161:aa5281ff4a02 12456 #define TIM_OR_TI1_RMP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12457 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 12458 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
AnnaBridge 161:aa5281ff4a02 12459 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12460 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12461
AnnaBridge 161:aa5281ff4a02 12462 #define TIM_OR_TI4_RMP_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12463 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 12464 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 161:aa5281ff4a02 12465 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12466 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
AnnaBridge 161:aa5281ff4a02 12467 #define TIM_OR_ITR1_RMP_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12468 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
AnnaBridge 161:aa5281ff4a02 12469 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
AnnaBridge 161:aa5281ff4a02 12470 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
AnnaBridge 161:aa5281ff4a02 12471 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
AnnaBridge 161:aa5281ff4a02 12472
AnnaBridge 161:aa5281ff4a02 12473
AnnaBridge 161:aa5281ff4a02 12474 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 12475 /* */
AnnaBridge 161:aa5281ff4a02 12476 /* Universal Synchronous Asynchronous Receiver Transmitter */
AnnaBridge 161:aa5281ff4a02 12477 /* */
AnnaBridge 161:aa5281ff4a02 12478 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 12479 /******************* Bit definition for USART_SR register *******************/
AnnaBridge 161:aa5281ff4a02 12480 #define USART_SR_PE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12481 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12482 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
AnnaBridge 161:aa5281ff4a02 12483 #define USART_SR_FE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12484 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12485 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
AnnaBridge 161:aa5281ff4a02 12486 #define USART_SR_NE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12487 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12488 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
AnnaBridge 161:aa5281ff4a02 12489 #define USART_SR_ORE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12490 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12491 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
AnnaBridge 161:aa5281ff4a02 12492 #define USART_SR_IDLE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12493 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12494 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
AnnaBridge 161:aa5281ff4a02 12495 #define USART_SR_RXNE_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12496 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12497 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
AnnaBridge 161:aa5281ff4a02 12498 #define USART_SR_TC_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12499 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12500 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
AnnaBridge 161:aa5281ff4a02 12501 #define USART_SR_TXE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12502 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12503 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
AnnaBridge 161:aa5281ff4a02 12504 #define USART_SR_LBD_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12505 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 12506 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
AnnaBridge 161:aa5281ff4a02 12507 #define USART_SR_CTS_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12508 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12509 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
AnnaBridge 161:aa5281ff4a02 12510
AnnaBridge 161:aa5281ff4a02 12511 /******************* Bit definition for USART_DR register *******************/
AnnaBridge 161:aa5281ff4a02 12512 #define USART_DR_DR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12513 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
AnnaBridge 161:aa5281ff4a02 12514 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
AnnaBridge 161:aa5281ff4a02 12515
AnnaBridge 161:aa5281ff4a02 12516 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 161:aa5281ff4a02 12517 #define USART_BRR_DIV_Fraction_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12518 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 12519 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
AnnaBridge 161:aa5281ff4a02 12520 #define USART_BRR_DIV_Mantissa_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12521 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
AnnaBridge 161:aa5281ff4a02 12522 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
AnnaBridge 161:aa5281ff4a02 12523
AnnaBridge 161:aa5281ff4a02 12524 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 161:aa5281ff4a02 12525 #define USART_CR1_SBK_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12526 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12527 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
AnnaBridge 161:aa5281ff4a02 12528 #define USART_CR1_RWU_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12529 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12530 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
AnnaBridge 161:aa5281ff4a02 12531 #define USART_CR1_RE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12532 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12533 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
AnnaBridge 161:aa5281ff4a02 12534 #define USART_CR1_TE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12535 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12536 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
AnnaBridge 161:aa5281ff4a02 12537 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12538 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12539 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 12540 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12541 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12542 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 12543 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12544 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12545 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 12546 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12547 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 163:e59c8e839560 12548 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 12549 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12550 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 12551 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 12552 #define USART_CR1_PS_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12553 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12554 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
AnnaBridge 161:aa5281ff4a02 12555 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12556 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12557 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
AnnaBridge 161:aa5281ff4a02 12558 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12559 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12560 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
AnnaBridge 161:aa5281ff4a02 12561 #define USART_CR1_M_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12562 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 12563 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
AnnaBridge 161:aa5281ff4a02 12564 #define USART_CR1_UE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 12565 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 12566 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
AnnaBridge 161:aa5281ff4a02 12567 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 161:aa5281ff4a02 12568 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 12569 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
AnnaBridge 161:aa5281ff4a02 12570
AnnaBridge 161:aa5281ff4a02 12571 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 161:aa5281ff4a02 12572 #define USART_CR2_ADD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12573 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 12574 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
AnnaBridge 161:aa5281ff4a02 12575 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12576 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12577 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
AnnaBridge 161:aa5281ff4a02 12578 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12579 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12580 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 12581 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12582 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 12583 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
AnnaBridge 161:aa5281ff4a02 12584 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12585 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12586 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
AnnaBridge 161:aa5281ff4a02 12587 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12588 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12589 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 161:aa5281ff4a02 12590 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12591 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12592 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
AnnaBridge 161:aa5281ff4a02 12593
AnnaBridge 161:aa5281ff4a02 12594 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12595 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 161:aa5281ff4a02 12596 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
AnnaBridge 161:aa5281ff4a02 12597 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
AnnaBridge 161:aa5281ff4a02 12598 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
AnnaBridge 161:aa5281ff4a02 12599
AnnaBridge 161:aa5281ff4a02 12600 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 161:aa5281ff4a02 12601 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 12602 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
AnnaBridge 161:aa5281ff4a02 12603
AnnaBridge 161:aa5281ff4a02 12604 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 161:aa5281ff4a02 12605 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12606 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12607 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 12608 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12609 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12610 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
AnnaBridge 161:aa5281ff4a02 12611 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12612 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12613 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
AnnaBridge 161:aa5281ff4a02 12614 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12615 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12616 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
AnnaBridge 161:aa5281ff4a02 12617 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12618 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12619 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
AnnaBridge 161:aa5281ff4a02 12620 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12621 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12622 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
AnnaBridge 161:aa5281ff4a02 12623 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12624 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12625 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
AnnaBridge 161:aa5281ff4a02 12626 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12627 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12628 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
AnnaBridge 161:aa5281ff4a02 12629 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12630 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 12631 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
AnnaBridge 161:aa5281ff4a02 12632 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12633 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12634 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
AnnaBridge 161:aa5281ff4a02 12635 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12636 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12637 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
AnnaBridge 161:aa5281ff4a02 12638 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12639 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12640 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
AnnaBridge 161:aa5281ff4a02 12641
AnnaBridge 161:aa5281ff4a02 12642 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 161:aa5281ff4a02 12643 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12644 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 12645 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
AnnaBridge 161:aa5281ff4a02 12646 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
AnnaBridge 161:aa5281ff4a02 12647 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
AnnaBridge 161:aa5281ff4a02 12648 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
AnnaBridge 161:aa5281ff4a02 12649 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
AnnaBridge 161:aa5281ff4a02 12650 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12651 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 12652 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12653 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
AnnaBridge 161:aa5281ff4a02 12654
AnnaBridge 161:aa5281ff4a02 12655 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12656 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 161:aa5281ff4a02 12657 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
AnnaBridge 161:aa5281ff4a02 12658
AnnaBridge 161:aa5281ff4a02 12659 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 12660 /* */
AnnaBridge 161:aa5281ff4a02 12661 /* Window WATCHDOG */
AnnaBridge 161:aa5281ff4a02 12662 /* */
AnnaBridge 161:aa5281ff4a02 12663 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 12664 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 161:aa5281ff4a02 12665 #define WWDG_CR_T_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12666 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 161:aa5281ff4a02 12667 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 161:aa5281ff4a02 12668 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
AnnaBridge 161:aa5281ff4a02 12669 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
AnnaBridge 161:aa5281ff4a02 12670 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
AnnaBridge 161:aa5281ff4a02 12671 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
AnnaBridge 161:aa5281ff4a02 12672 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
AnnaBridge 161:aa5281ff4a02 12673 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
AnnaBridge 161:aa5281ff4a02 12674 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
AnnaBridge 161:aa5281ff4a02 12675 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 12676 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 161:aa5281ff4a02 12677 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 161:aa5281ff4a02 12678 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 161:aa5281ff4a02 12679 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 161:aa5281ff4a02 12680 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 161:aa5281ff4a02 12681 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 161:aa5281ff4a02 12682 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 161:aa5281ff4a02 12683
AnnaBridge 161:aa5281ff4a02 12684 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12685 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12686 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 161:aa5281ff4a02 12687
AnnaBridge 161:aa5281ff4a02 12688 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 161:aa5281ff4a02 12689 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12690 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 161:aa5281ff4a02 12691 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 161:aa5281ff4a02 12692 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
AnnaBridge 161:aa5281ff4a02 12693 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
AnnaBridge 161:aa5281ff4a02 12694 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
AnnaBridge 161:aa5281ff4a02 12695 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
AnnaBridge 161:aa5281ff4a02 12696 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
AnnaBridge 161:aa5281ff4a02 12697 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
AnnaBridge 161:aa5281ff4a02 12698 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
AnnaBridge 161:aa5281ff4a02 12699 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 12700 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 161:aa5281ff4a02 12701 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 161:aa5281ff4a02 12702 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 161:aa5281ff4a02 12703 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 161:aa5281ff4a02 12704 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 161:aa5281ff4a02 12705 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 161:aa5281ff4a02 12706 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 161:aa5281ff4a02 12707
AnnaBridge 161:aa5281ff4a02 12708 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12709 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 161:aa5281ff4a02 12710 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 161:aa5281ff4a02 12711 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
AnnaBridge 161:aa5281ff4a02 12712 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
AnnaBridge 161:aa5281ff4a02 12713 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 12714 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 161:aa5281ff4a02 12715 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 161:aa5281ff4a02 12716
AnnaBridge 161:aa5281ff4a02 12717 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12718 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12719 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 161:aa5281ff4a02 12720
AnnaBridge 161:aa5281ff4a02 12721 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 161:aa5281ff4a02 12722 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12723 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12724 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 161:aa5281ff4a02 12725
AnnaBridge 161:aa5281ff4a02 12726
AnnaBridge 161:aa5281ff4a02 12727 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 12728 /* */
AnnaBridge 161:aa5281ff4a02 12729 /* DBG */
AnnaBridge 161:aa5281ff4a02 12730 /* */
AnnaBridge 161:aa5281ff4a02 12731 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 12732 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 161:aa5281ff4a02 12733 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12734 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 12735 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 161:aa5281ff4a02 12736 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 161:aa5281ff4a02 12737 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 12738 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 161:aa5281ff4a02 12739
AnnaBridge 161:aa5281ff4a02 12740 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 161:aa5281ff4a02 12741 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12742 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12743 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 161:aa5281ff4a02 12744 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12745 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12746 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12747 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12748 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12749 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 161:aa5281ff4a02 12750 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12751 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12752 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 161:aa5281ff4a02 12753
AnnaBridge 161:aa5281ff4a02 12754 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12755 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 12756 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 161:aa5281ff4a02 12757 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12758 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12759
AnnaBridge 161:aa5281ff4a02 12760 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 161:aa5281ff4a02 12761 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12762 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12763 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12764 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12765 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12766 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12767 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12768 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12769 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12770 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12771 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12772 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12773 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12774 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12775 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12776 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12777 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12778 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12779 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12780 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12781 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12782 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12783 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12784 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12785 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12786 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 12787 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12788 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12789 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12790 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12791 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12792 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12793 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12794 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12795 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 12796 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12797 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 161:aa5281ff4a02 12798 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 12799 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 161:aa5281ff4a02 12800 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 161:aa5281ff4a02 12801 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 12802 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
AnnaBridge 161:aa5281ff4a02 12803 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
AnnaBridge 161:aa5281ff4a02 12804 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 12805 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
AnnaBridge 161:aa5281ff4a02 12806 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
AnnaBridge 161:aa5281ff4a02 12807 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 12808 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12809 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
AnnaBridge 161:aa5281ff4a02 12810 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 12811 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12812 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
AnnaBridge 161:aa5281ff4a02 12813 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
AnnaBridge 161:aa5281ff4a02 12814
AnnaBridge 161:aa5281ff4a02 12815 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 161:aa5281ff4a02 12816 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12817 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12818 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12819 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12820 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12821 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12822 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
AnnaBridge 161:aa5281ff4a02 12823 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 12824 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12825 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
AnnaBridge 161:aa5281ff4a02 12826 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 12827 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12828 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
AnnaBridge 161:aa5281ff4a02 12829 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 12830 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
AnnaBridge 161:aa5281ff4a02 12831
AnnaBridge 161:aa5281ff4a02 12832 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 12833 /* */
AnnaBridge 161:aa5281ff4a02 12834 /* Ethernet MAC Registers bits definitions */
AnnaBridge 161:aa5281ff4a02 12835 /* */
AnnaBridge 161:aa5281ff4a02 12836 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 12837 /* Bit definition for Ethernet MAC Control Register register */
AnnaBridge 161:aa5281ff4a02 12838 #define ETH_MACCR_WD_Pos (23U)
AnnaBridge 161:aa5281ff4a02 12839 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 12840 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
AnnaBridge 161:aa5281ff4a02 12841 #define ETH_MACCR_JD_Pos (22U)
AnnaBridge 161:aa5281ff4a02 12842 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 12843 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
AnnaBridge 161:aa5281ff4a02 12844 #define ETH_MACCR_IFG_Pos (17U)
AnnaBridge 161:aa5281ff4a02 12845 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
AnnaBridge 161:aa5281ff4a02 12846 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
AnnaBridge 161:aa5281ff4a02 12847 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
AnnaBridge 161:aa5281ff4a02 12848 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
AnnaBridge 161:aa5281ff4a02 12849 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
AnnaBridge 161:aa5281ff4a02 12850 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
AnnaBridge 161:aa5281ff4a02 12851 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
AnnaBridge 161:aa5281ff4a02 12852 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
AnnaBridge 161:aa5281ff4a02 12853 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
AnnaBridge 161:aa5281ff4a02 12854 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
AnnaBridge 161:aa5281ff4a02 12855 #define ETH_MACCR_CSD_Pos (16U)
AnnaBridge 161:aa5281ff4a02 12856 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 12857 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
AnnaBridge 161:aa5281ff4a02 12858 #define ETH_MACCR_FES_Pos (14U)
AnnaBridge 161:aa5281ff4a02 12859 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 12860 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
AnnaBridge 161:aa5281ff4a02 12861 #define ETH_MACCR_ROD_Pos (13U)
AnnaBridge 161:aa5281ff4a02 12862 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 12863 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
AnnaBridge 161:aa5281ff4a02 12864 #define ETH_MACCR_LM_Pos (12U)
AnnaBridge 161:aa5281ff4a02 12865 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 12866 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
AnnaBridge 161:aa5281ff4a02 12867 #define ETH_MACCR_DM_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12868 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 12869 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
AnnaBridge 161:aa5281ff4a02 12870 #define ETH_MACCR_IPCO_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12871 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12872 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
AnnaBridge 161:aa5281ff4a02 12873 #define ETH_MACCR_RD_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12874 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12875 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
AnnaBridge 161:aa5281ff4a02 12876 #define ETH_MACCR_APCS_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12877 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12878 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
AnnaBridge 161:aa5281ff4a02 12879 #define ETH_MACCR_BL_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12880 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
AnnaBridge 161:aa5281ff4a02 12881 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
AnnaBridge 161:aa5281ff4a02 12882 a transmission attempt during retries after a collision: 0 =< r <2^k */
AnnaBridge 161:aa5281ff4a02 12883 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
AnnaBridge 161:aa5281ff4a02 12884 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
AnnaBridge 161:aa5281ff4a02 12885 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
AnnaBridge 161:aa5281ff4a02 12886 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
AnnaBridge 161:aa5281ff4a02 12887 #define ETH_MACCR_DC_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12888 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12889 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
AnnaBridge 161:aa5281ff4a02 12890 #define ETH_MACCR_TE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12891 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12892 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
AnnaBridge 161:aa5281ff4a02 12893 #define ETH_MACCR_RE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12894 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12895 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
AnnaBridge 161:aa5281ff4a02 12896
AnnaBridge 161:aa5281ff4a02 12897 /* Bit definition for Ethernet MAC Frame Filter Register */
AnnaBridge 161:aa5281ff4a02 12898 #define ETH_MACFFR_RA_Pos (31U)
AnnaBridge 161:aa5281ff4a02 12899 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 12900 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
AnnaBridge 161:aa5281ff4a02 12901 #define ETH_MACFFR_HPF_Pos (10U)
AnnaBridge 161:aa5281ff4a02 12902 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 12903 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
AnnaBridge 161:aa5281ff4a02 12904 #define ETH_MACFFR_SAF_Pos (9U)
AnnaBridge 161:aa5281ff4a02 12905 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 12906 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
AnnaBridge 161:aa5281ff4a02 12907 #define ETH_MACFFR_SAIF_Pos (8U)
AnnaBridge 161:aa5281ff4a02 12908 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 12909 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
AnnaBridge 161:aa5281ff4a02 12910 #define ETH_MACFFR_PCF_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12911 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 12912 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
AnnaBridge 161:aa5281ff4a02 12913 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12914 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 12915 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
AnnaBridge 161:aa5281ff4a02 12916 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12917 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12918 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
AnnaBridge 161:aa5281ff4a02 12919 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12920 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
AnnaBridge 161:aa5281ff4a02 12921 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
AnnaBridge 161:aa5281ff4a02 12922 #define ETH_MACFFR_BFD_Pos (5U)
AnnaBridge 161:aa5281ff4a02 12923 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 12924 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
AnnaBridge 161:aa5281ff4a02 12925 #define ETH_MACFFR_PAM_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12926 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12927 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
AnnaBridge 161:aa5281ff4a02 12928 #define ETH_MACFFR_DAIF_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12929 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12930 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
AnnaBridge 161:aa5281ff4a02 12931 #define ETH_MACFFR_HM_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12932 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12933 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
AnnaBridge 161:aa5281ff4a02 12934 #define ETH_MACFFR_HU_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12935 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12936 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
AnnaBridge 161:aa5281ff4a02 12937 #define ETH_MACFFR_PM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12938 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12939 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
AnnaBridge 161:aa5281ff4a02 12940
AnnaBridge 161:aa5281ff4a02 12941 /* Bit definition for Ethernet MAC Hash Table High Register */
AnnaBridge 161:aa5281ff4a02 12942 #define ETH_MACHTHR_HTH_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12943 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 12944 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
AnnaBridge 161:aa5281ff4a02 12945
AnnaBridge 161:aa5281ff4a02 12946 /* Bit definition for Ethernet MAC Hash Table Low Register */
AnnaBridge 161:aa5281ff4a02 12947 #define ETH_MACHTLR_HTL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12948 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 12949 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
AnnaBridge 161:aa5281ff4a02 12950
AnnaBridge 161:aa5281ff4a02 12951 /* Bit definition for Ethernet MAC MII Address Register */
AnnaBridge 161:aa5281ff4a02 12952 #define ETH_MACMIIAR_PA_Pos (11U)
AnnaBridge 161:aa5281ff4a02 12953 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
AnnaBridge 161:aa5281ff4a02 12954 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
AnnaBridge 161:aa5281ff4a02 12955 #define ETH_MACMIIAR_MR_Pos (6U)
AnnaBridge 161:aa5281ff4a02 12956 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
AnnaBridge 161:aa5281ff4a02 12957 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
AnnaBridge 161:aa5281ff4a02 12958 #define ETH_MACMIIAR_CR_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12959 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
AnnaBridge 161:aa5281ff4a02 12960 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
AnnaBridge 161:aa5281ff4a02 12961 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
AnnaBridge 161:aa5281ff4a02 12962 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12963 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 12964 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
AnnaBridge 161:aa5281ff4a02 12965 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
AnnaBridge 161:aa5281ff4a02 12966 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 12967 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
AnnaBridge 161:aa5281ff4a02 12968 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
AnnaBridge 161:aa5281ff4a02 12969 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
AnnaBridge 161:aa5281ff4a02 12970 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
AnnaBridge 161:aa5281ff4a02 12971 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12972 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12973 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
AnnaBridge 161:aa5281ff4a02 12974 #define ETH_MACMIIAR_MW_Pos (1U)
AnnaBridge 161:aa5281ff4a02 12975 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 12976 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
AnnaBridge 161:aa5281ff4a02 12977 #define ETH_MACMIIAR_MB_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12978 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 12979 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
AnnaBridge 161:aa5281ff4a02 12980
AnnaBridge 161:aa5281ff4a02 12981 /* Bit definition for Ethernet MAC MII Data Register */
AnnaBridge 161:aa5281ff4a02 12982 #define ETH_MACMIIDR_MD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 12983 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 12984 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
AnnaBridge 161:aa5281ff4a02 12985
AnnaBridge 161:aa5281ff4a02 12986 /* Bit definition for Ethernet MAC Flow Control Register */
AnnaBridge 161:aa5281ff4a02 12987 #define ETH_MACFCR_PT_Pos (16U)
AnnaBridge 161:aa5281ff4a02 12988 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 12989 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
AnnaBridge 161:aa5281ff4a02 12990 #define ETH_MACFCR_ZQPD_Pos (7U)
AnnaBridge 161:aa5281ff4a02 12991 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 12992 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
AnnaBridge 161:aa5281ff4a02 12993 #define ETH_MACFCR_PLT_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12994 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 12995 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
AnnaBridge 161:aa5281ff4a02 12996 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
AnnaBridge 161:aa5281ff4a02 12997 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
AnnaBridge 161:aa5281ff4a02 12998 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 12999 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
AnnaBridge 161:aa5281ff4a02 13000 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13001 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13002 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
AnnaBridge 161:aa5281ff4a02 13003 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13004 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
AnnaBridge 161:aa5281ff4a02 13005 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
AnnaBridge 161:aa5281ff4a02 13006 #define ETH_MACFCR_UPFD_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13007 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13008 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
AnnaBridge 161:aa5281ff4a02 13009 #define ETH_MACFCR_RFCE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13010 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13011 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
AnnaBridge 161:aa5281ff4a02 13012 #define ETH_MACFCR_TFCE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13013 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13014 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
AnnaBridge 161:aa5281ff4a02 13015 #define ETH_MACFCR_FCBBPA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13016 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13017 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
AnnaBridge 161:aa5281ff4a02 13018
AnnaBridge 161:aa5281ff4a02 13019 /* Bit definition for Ethernet MAC VLAN Tag Register */
AnnaBridge 161:aa5281ff4a02 13020 #define ETH_MACVLANTR_VLANTC_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13021 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 13022 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
AnnaBridge 161:aa5281ff4a02 13023 #define ETH_MACVLANTR_VLANTI_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13024 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 13025 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
AnnaBridge 161:aa5281ff4a02 13026
AnnaBridge 161:aa5281ff4a02 13027 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
AnnaBridge 161:aa5281ff4a02 13028 #define ETH_MACRWUFFR_D_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13029 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13030 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
AnnaBridge 161:aa5281ff4a02 13031 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
AnnaBridge 161:aa5281ff4a02 13032 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
AnnaBridge 161:aa5281ff4a02 13033 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
AnnaBridge 161:aa5281ff4a02 13034 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
AnnaBridge 161:aa5281ff4a02 13035 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
AnnaBridge 161:aa5281ff4a02 13036 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
AnnaBridge 161:aa5281ff4a02 13037 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
AnnaBridge 161:aa5281ff4a02 13038 RSVD - Filter1 Command - RSVD - Filter0 Command
AnnaBridge 161:aa5281ff4a02 13039 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
AnnaBridge 161:aa5281ff4a02 13040 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
AnnaBridge 161:aa5281ff4a02 13041 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
AnnaBridge 161:aa5281ff4a02 13042
AnnaBridge 161:aa5281ff4a02 13043 /* Bit definition for Ethernet MAC PMT Control and Status Register */
AnnaBridge 161:aa5281ff4a02 13044 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
AnnaBridge 161:aa5281ff4a02 13045 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 13046 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
AnnaBridge 161:aa5281ff4a02 13047 #define ETH_MACPMTCSR_GU_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13048 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13049 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
AnnaBridge 161:aa5281ff4a02 13050 #define ETH_MACPMTCSR_WFR_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13051 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13052 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
AnnaBridge 161:aa5281ff4a02 13053 #define ETH_MACPMTCSR_MPR_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13054 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13055 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
AnnaBridge 161:aa5281ff4a02 13056 #define ETH_MACPMTCSR_WFE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13057 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13058 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
AnnaBridge 161:aa5281ff4a02 13059 #define ETH_MACPMTCSR_MPE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13060 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13061 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
AnnaBridge 161:aa5281ff4a02 13062 #define ETH_MACPMTCSR_PD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13063 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13064 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
AnnaBridge 161:aa5281ff4a02 13065
AnnaBridge 161:aa5281ff4a02 13066 /* Bit definition for Ethernet MAC debug Register */
AnnaBridge 161:aa5281ff4a02 13067 #define ETH_MACDBGR_TFF_Pos (25U)
AnnaBridge 161:aa5281ff4a02 13068 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 13069 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
AnnaBridge 161:aa5281ff4a02 13070 #define ETH_MACDBGR_TFNE_Pos (24U)
AnnaBridge 161:aa5281ff4a02 13071 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 13072 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
AnnaBridge 161:aa5281ff4a02 13073 #define ETH_MACDBGR_TFWA_Pos (22U)
AnnaBridge 161:aa5281ff4a02 13074 #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 13075 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
AnnaBridge 161:aa5281ff4a02 13076 #define ETH_MACDBGR_TFRS_Pos (20U)
AnnaBridge 161:aa5281ff4a02 13077 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 13078 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
AnnaBridge 161:aa5281ff4a02 13079 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
AnnaBridge 161:aa5281ff4a02 13080 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 13081 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge 161:aa5281ff4a02 13082 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
AnnaBridge 161:aa5281ff4a02 13083 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 13084 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
AnnaBridge 161:aa5281ff4a02 13085 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
AnnaBridge 161:aa5281ff4a02 13086 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 13087 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
AnnaBridge 161:aa5281ff4a02 13088 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
AnnaBridge 161:aa5281ff4a02 13089 #define ETH_MACDBGR_MTP_Pos (19U)
AnnaBridge 161:aa5281ff4a02 13090 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 13091 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
AnnaBridge 161:aa5281ff4a02 13092 #define ETH_MACDBGR_MTFCS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13093 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
AnnaBridge 161:aa5281ff4a02 13094 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
AnnaBridge 161:aa5281ff4a02 13095 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13096 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
AnnaBridge 161:aa5281ff4a02 13097 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
AnnaBridge 161:aa5281ff4a02 13098 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
AnnaBridge 161:aa5281ff4a02 13099 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 13100 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge 161:aa5281ff4a02 13101 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13102 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 13103 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge 161:aa5281ff4a02 13104 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
AnnaBridge 161:aa5281ff4a02 13105 #define ETH_MACDBGR_MMTEA_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13106 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 13107 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
AnnaBridge 161:aa5281ff4a02 13108 #define ETH_MACDBGR_RFFL_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13109 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 13110 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
AnnaBridge 161:aa5281ff4a02 13111 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13112 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
AnnaBridge 161:aa5281ff4a02 13113 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
AnnaBridge 161:aa5281ff4a02 13114 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13115 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13116 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
AnnaBridge 161:aa5281ff4a02 13117 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13118 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13119 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
AnnaBridge 161:aa5281ff4a02 13120 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
AnnaBridge 161:aa5281ff4a02 13121 #define ETH_MACDBGR_RFRCS_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13122 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
AnnaBridge 161:aa5281ff4a02 13123 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
AnnaBridge 161:aa5281ff4a02 13124 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13125 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
AnnaBridge 161:aa5281ff4a02 13126 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
AnnaBridge 161:aa5281ff4a02 13127 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13128 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13129 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
AnnaBridge 161:aa5281ff4a02 13130 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13131 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13132 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
AnnaBridge 161:aa5281ff4a02 13133 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
AnnaBridge 161:aa5281ff4a02 13134 #define ETH_MACDBGR_RFWRA_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13135 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13136 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
AnnaBridge 161:aa5281ff4a02 13137 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13138 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
AnnaBridge 161:aa5281ff4a02 13139 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
AnnaBridge 161:aa5281ff4a02 13140 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13141 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13142 #define ETH_MACDBGR_MMRPEA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13143 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13144 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
AnnaBridge 161:aa5281ff4a02 13145
AnnaBridge 161:aa5281ff4a02 13146 /* Bit definition for Ethernet MAC Status Register */
AnnaBridge 161:aa5281ff4a02 13147 #define ETH_MACSR_TSTS_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13148 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13149 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
AnnaBridge 161:aa5281ff4a02 13150 #define ETH_MACSR_MMCTS_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13151 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13152 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
AnnaBridge 161:aa5281ff4a02 13153 #define ETH_MACSR_MMMCRS_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13154 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13155 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
AnnaBridge 161:aa5281ff4a02 13156 #define ETH_MACSR_MMCS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13157 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13158 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
AnnaBridge 161:aa5281ff4a02 13159 #define ETH_MACSR_PMTS_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13160 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13161 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
AnnaBridge 161:aa5281ff4a02 13162
AnnaBridge 161:aa5281ff4a02 13163 /* Bit definition for Ethernet MAC Interrupt Mask Register */
AnnaBridge 161:aa5281ff4a02 13164 #define ETH_MACIMR_TSTIM_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13165 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13166 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
AnnaBridge 161:aa5281ff4a02 13167 #define ETH_MACIMR_PMTIM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13168 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13169 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
AnnaBridge 161:aa5281ff4a02 13170
AnnaBridge 161:aa5281ff4a02 13171 /* Bit definition for Ethernet MAC Address0 High Register */
AnnaBridge 161:aa5281ff4a02 13172 #define ETH_MACA0HR_MACA0H_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13173 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 13174 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
AnnaBridge 161:aa5281ff4a02 13175
AnnaBridge 161:aa5281ff4a02 13176 /* Bit definition for Ethernet MAC Address0 Low Register */
AnnaBridge 161:aa5281ff4a02 13177 #define ETH_MACA0LR_MACA0L_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13178 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13179 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
AnnaBridge 161:aa5281ff4a02 13180
AnnaBridge 161:aa5281ff4a02 13181 /* Bit definition for Ethernet MAC Address1 High Register */
AnnaBridge 161:aa5281ff4a02 13182 #define ETH_MACA1HR_AE_Pos (31U)
AnnaBridge 161:aa5281ff4a02 13183 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 13184 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
AnnaBridge 161:aa5281ff4a02 13185 #define ETH_MACA1HR_SA_Pos (30U)
AnnaBridge 161:aa5281ff4a02 13186 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 13187 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
AnnaBridge 161:aa5281ff4a02 13188 #define ETH_MACA1HR_MBC_Pos (24U)
AnnaBridge 161:aa5281ff4a02 13189 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 161:aa5281ff4a02 13190 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
AnnaBridge 161:aa5281ff4a02 13191 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 161:aa5281ff4a02 13192 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 161:aa5281ff4a02 13193 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 161:aa5281ff4a02 13194 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 161:aa5281ff4a02 13195 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 161:aa5281ff4a02 13196 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
AnnaBridge 161:aa5281ff4a02 13197 #define ETH_MACA1HR_MACA1H_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13198 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 13199 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
AnnaBridge 161:aa5281ff4a02 13200
AnnaBridge 161:aa5281ff4a02 13201 /* Bit definition for Ethernet MAC Address1 Low Register */
AnnaBridge 161:aa5281ff4a02 13202 #define ETH_MACA1LR_MACA1L_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13203 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13204 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
AnnaBridge 161:aa5281ff4a02 13205
AnnaBridge 161:aa5281ff4a02 13206 /* Bit definition for Ethernet MAC Address2 High Register */
AnnaBridge 161:aa5281ff4a02 13207 #define ETH_MACA2HR_AE_Pos (31U)
AnnaBridge 161:aa5281ff4a02 13208 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 13209 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
AnnaBridge 161:aa5281ff4a02 13210 #define ETH_MACA2HR_SA_Pos (30U)
AnnaBridge 161:aa5281ff4a02 13211 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 13212 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
AnnaBridge 161:aa5281ff4a02 13213 #define ETH_MACA2HR_MBC_Pos (24U)
AnnaBridge 161:aa5281ff4a02 13214 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 161:aa5281ff4a02 13215 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
AnnaBridge 161:aa5281ff4a02 13216 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 161:aa5281ff4a02 13217 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 161:aa5281ff4a02 13218 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 161:aa5281ff4a02 13219 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 161:aa5281ff4a02 13220 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 161:aa5281ff4a02 13221 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 161:aa5281ff4a02 13222 #define ETH_MACA2HR_MACA2H_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13223 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 13224 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
AnnaBridge 161:aa5281ff4a02 13225
AnnaBridge 161:aa5281ff4a02 13226 /* Bit definition for Ethernet MAC Address2 Low Register */
AnnaBridge 161:aa5281ff4a02 13227 #define ETH_MACA2LR_MACA2L_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13228 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13229 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
AnnaBridge 161:aa5281ff4a02 13230
AnnaBridge 161:aa5281ff4a02 13231 /* Bit definition for Ethernet MAC Address3 High Register */
AnnaBridge 161:aa5281ff4a02 13232 #define ETH_MACA3HR_AE_Pos (31U)
AnnaBridge 161:aa5281ff4a02 13233 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 13234 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
AnnaBridge 161:aa5281ff4a02 13235 #define ETH_MACA3HR_SA_Pos (30U)
AnnaBridge 161:aa5281ff4a02 13236 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 13237 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
AnnaBridge 161:aa5281ff4a02 13238 #define ETH_MACA3HR_MBC_Pos (24U)
AnnaBridge 161:aa5281ff4a02 13239 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 161:aa5281ff4a02 13240 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
AnnaBridge 161:aa5281ff4a02 13241 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 161:aa5281ff4a02 13242 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 161:aa5281ff4a02 13243 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 161:aa5281ff4a02 13244 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 161:aa5281ff4a02 13245 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 161:aa5281ff4a02 13246 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 161:aa5281ff4a02 13247 #define ETH_MACA3HR_MACA3H_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13248 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 13249 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
AnnaBridge 161:aa5281ff4a02 13250
AnnaBridge 161:aa5281ff4a02 13251 /* Bit definition for Ethernet MAC Address3 Low Register */
AnnaBridge 161:aa5281ff4a02 13252 #define ETH_MACA3LR_MACA3L_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13253 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13254 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
AnnaBridge 161:aa5281ff4a02 13255
AnnaBridge 161:aa5281ff4a02 13256 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 13257 /* Ethernet MMC Registers bits definition */
AnnaBridge 161:aa5281ff4a02 13258 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 13259
AnnaBridge 161:aa5281ff4a02 13260 /* Bit definition for Ethernet MMC Contol Register */
AnnaBridge 161:aa5281ff4a02 13261 #define ETH_MMCCR_MCFHP_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13262 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13263 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
AnnaBridge 161:aa5281ff4a02 13264 #define ETH_MMCCR_MCP_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13265 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13266 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
AnnaBridge 161:aa5281ff4a02 13267 #define ETH_MMCCR_MCF_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13268 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13269 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
AnnaBridge 161:aa5281ff4a02 13270 #define ETH_MMCCR_ROR_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13271 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13272 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
AnnaBridge 161:aa5281ff4a02 13273 #define ETH_MMCCR_CSR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13274 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13275 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
AnnaBridge 161:aa5281ff4a02 13276 #define ETH_MMCCR_CR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13277 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13278 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
AnnaBridge 161:aa5281ff4a02 13279
AnnaBridge 161:aa5281ff4a02 13280 /* Bit definition for Ethernet MMC Receive Interrupt Register */
AnnaBridge 161:aa5281ff4a02 13281 #define ETH_MMCRIR_RGUFS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13282 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 13283 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13284 #define ETH_MMCRIR_RFAES_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13285 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13286 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13287 #define ETH_MMCRIR_RFCES_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13288 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13289 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13290
AnnaBridge 161:aa5281ff4a02 13291 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
AnnaBridge 161:aa5281ff4a02 13292 #define ETH_MMCTIR_TGFS_Pos (21U)
AnnaBridge 161:aa5281ff4a02 13293 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 13294 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13295 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
AnnaBridge 161:aa5281ff4a02 13296 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 13297 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13298 #define ETH_MMCTIR_TGFSCS_Pos (14U)
AnnaBridge 161:aa5281ff4a02 13299 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 13300 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13301
AnnaBridge 161:aa5281ff4a02 13302 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
AnnaBridge 161:aa5281ff4a02 13303 #define ETH_MMCRIMR_RGUFM_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13304 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 13305 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13306 #define ETH_MMCRIMR_RFAEM_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13307 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13308 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13309 #define ETH_MMCRIMR_RFCEM_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13310 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13311 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13312
AnnaBridge 161:aa5281ff4a02 13313 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
AnnaBridge 161:aa5281ff4a02 13314 #define ETH_MMCTIMR_TGFM_Pos (21U)
AnnaBridge 161:aa5281ff4a02 13315 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 13316 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13317 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
AnnaBridge 161:aa5281ff4a02 13318 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 13319 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13320 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
AnnaBridge 161:aa5281ff4a02 13321 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 13322 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
AnnaBridge 161:aa5281ff4a02 13323
AnnaBridge 161:aa5281ff4a02 13324 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
AnnaBridge 161:aa5281ff4a02 13325 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13326 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13327 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
AnnaBridge 161:aa5281ff4a02 13328
AnnaBridge 161:aa5281ff4a02 13329 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
AnnaBridge 161:aa5281ff4a02 13330 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13331 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13332 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
AnnaBridge 161:aa5281ff4a02 13333
AnnaBridge 161:aa5281ff4a02 13334 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
AnnaBridge 161:aa5281ff4a02 13335 #define ETH_MMCTGFCR_TGFC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13336 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13337 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
AnnaBridge 161:aa5281ff4a02 13338
AnnaBridge 161:aa5281ff4a02 13339 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
AnnaBridge 161:aa5281ff4a02 13340 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13341 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13342 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
AnnaBridge 161:aa5281ff4a02 13343
AnnaBridge 161:aa5281ff4a02 13344 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
AnnaBridge 161:aa5281ff4a02 13345 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13346 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13347 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
AnnaBridge 161:aa5281ff4a02 13348
AnnaBridge 161:aa5281ff4a02 13349 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
AnnaBridge 161:aa5281ff4a02 13350 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13351 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13352 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
AnnaBridge 161:aa5281ff4a02 13353
AnnaBridge 161:aa5281ff4a02 13354 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 13355 /* Ethernet PTP Registers bits definition */
AnnaBridge 161:aa5281ff4a02 13356 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 13357
AnnaBridge 161:aa5281ff4a02 13358 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
AnnaBridge 161:aa5281ff4a02 13359 #define ETH_PTPTSCR_TSCNT_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13360 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
AnnaBridge 161:aa5281ff4a02 13361 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
AnnaBridge 161:aa5281ff4a02 13362 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
AnnaBridge 161:aa5281ff4a02 13363 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 13364 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
AnnaBridge 161:aa5281ff4a02 13365 #define ETH_PTPTSSR_TSSEME_Pos (14U)
AnnaBridge 161:aa5281ff4a02 13366 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 13367 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
AnnaBridge 161:aa5281ff4a02 13368 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 13369 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 13370 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
AnnaBridge 161:aa5281ff4a02 13371 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
AnnaBridge 161:aa5281ff4a02 13372 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 13373 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
AnnaBridge 161:aa5281ff4a02 13374 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 13375 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 13376 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
AnnaBridge 161:aa5281ff4a02 13377 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
AnnaBridge 161:aa5281ff4a02 13378 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 13379 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
AnnaBridge 161:aa5281ff4a02 13380 #define ETH_PTPTSSR_TSSSR_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13381 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13382 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
AnnaBridge 161:aa5281ff4a02 13383 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13384 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13385 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
AnnaBridge 161:aa5281ff4a02 13386
AnnaBridge 161:aa5281ff4a02 13387 #define ETH_PTPTSCR_TSARU_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13388 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13389 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
AnnaBridge 161:aa5281ff4a02 13390 #define ETH_PTPTSCR_TSITE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13391 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13392 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
AnnaBridge 161:aa5281ff4a02 13393 #define ETH_PTPTSCR_TSSTU_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13394 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13395 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
AnnaBridge 161:aa5281ff4a02 13396 #define ETH_PTPTSCR_TSSTI_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13397 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13398 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
AnnaBridge 161:aa5281ff4a02 13399 #define ETH_PTPTSCR_TSFCU_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13400 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13401 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
AnnaBridge 161:aa5281ff4a02 13402 #define ETH_PTPTSCR_TSE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13403 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13404 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
AnnaBridge 161:aa5281ff4a02 13405
AnnaBridge 161:aa5281ff4a02 13406 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
AnnaBridge 161:aa5281ff4a02 13407 #define ETH_PTPSSIR_STSSI_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13408 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
AnnaBridge 161:aa5281ff4a02 13409 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
AnnaBridge 161:aa5281ff4a02 13410
AnnaBridge 161:aa5281ff4a02 13411 /* Bit definition for Ethernet PTP Time Stamp High Register */
AnnaBridge 161:aa5281ff4a02 13412 #define ETH_PTPTSHR_STS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13413 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13414 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
AnnaBridge 161:aa5281ff4a02 13415
AnnaBridge 161:aa5281ff4a02 13416 /* Bit definition for Ethernet PTP Time Stamp Low Register */
AnnaBridge 161:aa5281ff4a02 13417 #define ETH_PTPTSLR_STPNS_Pos (31U)
AnnaBridge 161:aa5281ff4a02 13418 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 13419 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
AnnaBridge 161:aa5281ff4a02 13420 #define ETH_PTPTSLR_STSS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13421 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 161:aa5281ff4a02 13422 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
AnnaBridge 161:aa5281ff4a02 13423
AnnaBridge 161:aa5281ff4a02 13424 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
AnnaBridge 161:aa5281ff4a02 13425 #define ETH_PTPTSHUR_TSUS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13426 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13427 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
AnnaBridge 161:aa5281ff4a02 13428
AnnaBridge 161:aa5281ff4a02 13429 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
AnnaBridge 161:aa5281ff4a02 13430 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
AnnaBridge 161:aa5281ff4a02 13431 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 13432 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
AnnaBridge 161:aa5281ff4a02 13433 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13434 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 161:aa5281ff4a02 13435 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
AnnaBridge 161:aa5281ff4a02 13436
AnnaBridge 161:aa5281ff4a02 13437 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
AnnaBridge 161:aa5281ff4a02 13438 #define ETH_PTPTSAR_TSA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13439 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13440 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
AnnaBridge 161:aa5281ff4a02 13441
AnnaBridge 161:aa5281ff4a02 13442 /* Bit definition for Ethernet PTP Target Time High Register */
AnnaBridge 161:aa5281ff4a02 13443 #define ETH_PTPTTHR_TTSH_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13444 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13445 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
AnnaBridge 161:aa5281ff4a02 13446
AnnaBridge 161:aa5281ff4a02 13447 /* Bit definition for Ethernet PTP Target Time Low Register */
AnnaBridge 161:aa5281ff4a02 13448 #define ETH_PTPTTLR_TTSL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13449 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13450 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
AnnaBridge 161:aa5281ff4a02 13451
AnnaBridge 161:aa5281ff4a02 13452 /* Bit definition for Ethernet PTP Time Stamp Status Register */
AnnaBridge 161:aa5281ff4a02 13453 #define ETH_PTPTSSR_TSTTR_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13454 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13455 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
AnnaBridge 161:aa5281ff4a02 13456 #define ETH_PTPTSSR_TSSO_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13457 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13458 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
AnnaBridge 161:aa5281ff4a02 13459
AnnaBridge 161:aa5281ff4a02 13460 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 13461 /* Ethernet DMA Registers bits definition */
AnnaBridge 161:aa5281ff4a02 13462 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 13463
AnnaBridge 161:aa5281ff4a02 13464 /* Bit definition for Ethernet DMA Bus Mode Register */
AnnaBridge 161:aa5281ff4a02 13465 #define ETH_DMABMR_AAB_Pos (25U)
AnnaBridge 161:aa5281ff4a02 13466 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 13467 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
AnnaBridge 161:aa5281ff4a02 13468 #define ETH_DMABMR_FPM_Pos (24U)
AnnaBridge 161:aa5281ff4a02 13469 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 13470 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
AnnaBridge 161:aa5281ff4a02 13471 #define ETH_DMABMR_USP_Pos (23U)
AnnaBridge 161:aa5281ff4a02 13472 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 13473 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
AnnaBridge 161:aa5281ff4a02 13474 #define ETH_DMABMR_RDP_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13475 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
AnnaBridge 161:aa5281ff4a02 13476 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
AnnaBridge 161:aa5281ff4a02 13477 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
AnnaBridge 161:aa5281ff4a02 13478 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
AnnaBridge 161:aa5281ff4a02 13479 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 161:aa5281ff4a02 13480 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 161:aa5281ff4a02 13481 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 161:aa5281ff4a02 13482 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 161:aa5281ff4a02 13483 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 161:aa5281ff4a02 13484 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 161:aa5281ff4a02 13485 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 161:aa5281ff4a02 13486 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 161:aa5281ff4a02 13487 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
AnnaBridge 161:aa5281ff4a02 13488 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
AnnaBridge 161:aa5281ff4a02 13489 #define ETH_DMABMR_FB_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13490 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 13491 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
AnnaBridge 161:aa5281ff4a02 13492 #define ETH_DMABMR_RTPR_Pos (14U)
AnnaBridge 161:aa5281ff4a02 13493 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
AnnaBridge 161:aa5281ff4a02 13494 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
AnnaBridge 161:aa5281ff4a02 13495 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
AnnaBridge 161:aa5281ff4a02 13496 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
AnnaBridge 161:aa5281ff4a02 13497 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
AnnaBridge 161:aa5281ff4a02 13498 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
AnnaBridge 161:aa5281ff4a02 13499 #define ETH_DMABMR_PBL_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13500 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
AnnaBridge 161:aa5281ff4a02 13501 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
AnnaBridge 161:aa5281ff4a02 13502 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
AnnaBridge 161:aa5281ff4a02 13503 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
AnnaBridge 161:aa5281ff4a02 13504 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 161:aa5281ff4a02 13505 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 161:aa5281ff4a02 13506 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 161:aa5281ff4a02 13507 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 161:aa5281ff4a02 13508 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 161:aa5281ff4a02 13509 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 161:aa5281ff4a02 13510 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 161:aa5281ff4a02 13511 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 161:aa5281ff4a02 13512 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
AnnaBridge 161:aa5281ff4a02 13513 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
AnnaBridge 161:aa5281ff4a02 13514 #define ETH_DMABMR_EDE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 13515 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 13516 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
AnnaBridge 161:aa5281ff4a02 13517 #define ETH_DMABMR_DSL_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13518 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
AnnaBridge 161:aa5281ff4a02 13519 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
AnnaBridge 161:aa5281ff4a02 13520 #define ETH_DMABMR_DA_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13521 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13522 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
AnnaBridge 161:aa5281ff4a02 13523 #define ETH_DMABMR_SR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13524 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13525 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
AnnaBridge 161:aa5281ff4a02 13526
AnnaBridge 161:aa5281ff4a02 13527 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
AnnaBridge 161:aa5281ff4a02 13528 #define ETH_DMATPDR_TPD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13529 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13530 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
AnnaBridge 161:aa5281ff4a02 13531
AnnaBridge 161:aa5281ff4a02 13532 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
AnnaBridge 161:aa5281ff4a02 13533 #define ETH_DMARPDR_RPD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13534 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13535 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
AnnaBridge 161:aa5281ff4a02 13536
AnnaBridge 161:aa5281ff4a02 13537 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
AnnaBridge 161:aa5281ff4a02 13538 #define ETH_DMARDLAR_SRL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13539 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13540 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
AnnaBridge 161:aa5281ff4a02 13541
AnnaBridge 161:aa5281ff4a02 13542 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
AnnaBridge 161:aa5281ff4a02 13543 #define ETH_DMATDLAR_STL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13544 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13545 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
AnnaBridge 161:aa5281ff4a02 13546
AnnaBridge 161:aa5281ff4a02 13547 /* Bit definition for Ethernet DMA Status Register */
AnnaBridge 161:aa5281ff4a02 13548 #define ETH_DMASR_TSTS_Pos (29U)
AnnaBridge 161:aa5281ff4a02 13549 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 13550 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
AnnaBridge 161:aa5281ff4a02 13551 #define ETH_DMASR_PMTS_Pos (28U)
AnnaBridge 161:aa5281ff4a02 13552 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 13553 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
AnnaBridge 161:aa5281ff4a02 13554 #define ETH_DMASR_MMCS_Pos (27U)
AnnaBridge 161:aa5281ff4a02 13555 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 13556 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
AnnaBridge 161:aa5281ff4a02 13557 #define ETH_DMASR_EBS_Pos (23U)
AnnaBridge 161:aa5281ff4a02 13558 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
AnnaBridge 161:aa5281ff4a02 13559 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
AnnaBridge 161:aa5281ff4a02 13560 /* combination with EBS[2:0] for GetFlagStatus function */
AnnaBridge 161:aa5281ff4a02 13561 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
AnnaBridge 161:aa5281ff4a02 13562 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 13563 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
AnnaBridge 161:aa5281ff4a02 13564 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
AnnaBridge 161:aa5281ff4a02 13565 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 13566 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
AnnaBridge 161:aa5281ff4a02 13567 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
AnnaBridge 161:aa5281ff4a02 13568 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 13569 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
AnnaBridge 161:aa5281ff4a02 13570 #define ETH_DMASR_TPS_Pos (20U)
AnnaBridge 161:aa5281ff4a02 13571 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
AnnaBridge 161:aa5281ff4a02 13572 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
AnnaBridge 161:aa5281ff4a02 13573 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
AnnaBridge 161:aa5281ff4a02 13574 #define ETH_DMASR_TPS_Fetching_Pos (20U)
AnnaBridge 161:aa5281ff4a02 13575 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 13576 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
AnnaBridge 161:aa5281ff4a02 13577 #define ETH_DMASR_TPS_Waiting_Pos (21U)
AnnaBridge 161:aa5281ff4a02 13578 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 13579 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
AnnaBridge 161:aa5281ff4a02 13580 #define ETH_DMASR_TPS_Reading_Pos (20U)
AnnaBridge 161:aa5281ff4a02 13581 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 13582 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
AnnaBridge 161:aa5281ff4a02 13583 #define ETH_DMASR_TPS_Suspended_Pos (21U)
AnnaBridge 161:aa5281ff4a02 13584 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
AnnaBridge 161:aa5281ff4a02 13585 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
AnnaBridge 161:aa5281ff4a02 13586 #define ETH_DMASR_TPS_Closing_Pos (20U)
AnnaBridge 161:aa5281ff4a02 13587 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
AnnaBridge 161:aa5281ff4a02 13588 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
AnnaBridge 161:aa5281ff4a02 13589 #define ETH_DMASR_RPS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13590 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
AnnaBridge 161:aa5281ff4a02 13591 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
AnnaBridge 161:aa5281ff4a02 13592 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
AnnaBridge 161:aa5281ff4a02 13593 #define ETH_DMASR_RPS_Fetching_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13594 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 13595 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
AnnaBridge 161:aa5281ff4a02 13596 #define ETH_DMASR_RPS_Waiting_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13597 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
AnnaBridge 161:aa5281ff4a02 13598 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
AnnaBridge 161:aa5281ff4a02 13599 #define ETH_DMASR_RPS_Suspended_Pos (19U)
AnnaBridge 161:aa5281ff4a02 13600 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 13601 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
AnnaBridge 161:aa5281ff4a02 13602 #define ETH_DMASR_RPS_Closing_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13603 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
AnnaBridge 161:aa5281ff4a02 13604 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
AnnaBridge 161:aa5281ff4a02 13605 #define ETH_DMASR_RPS_Queuing_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13606 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
AnnaBridge 161:aa5281ff4a02 13607 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
AnnaBridge 161:aa5281ff4a02 13608 #define ETH_DMASR_NIS_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13609 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 13610 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
AnnaBridge 161:aa5281ff4a02 13611 #define ETH_DMASR_AIS_Pos (15U)
AnnaBridge 161:aa5281ff4a02 13612 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 13613 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
AnnaBridge 161:aa5281ff4a02 13614 #define ETH_DMASR_ERS_Pos (14U)
AnnaBridge 161:aa5281ff4a02 13615 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 13616 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
AnnaBridge 161:aa5281ff4a02 13617 #define ETH_DMASR_FBES_Pos (13U)
AnnaBridge 161:aa5281ff4a02 13618 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 13619 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
AnnaBridge 161:aa5281ff4a02 13620 #define ETH_DMASR_ETS_Pos (10U)
AnnaBridge 161:aa5281ff4a02 13621 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 13622 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
AnnaBridge 161:aa5281ff4a02 13623 #define ETH_DMASR_RWTS_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13624 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13625 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
AnnaBridge 161:aa5281ff4a02 13626 #define ETH_DMASR_RPSS_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13627 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13628 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
AnnaBridge 161:aa5281ff4a02 13629 #define ETH_DMASR_RBUS_Pos (7U)
AnnaBridge 161:aa5281ff4a02 13630 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 13631 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
AnnaBridge 161:aa5281ff4a02 13632 #define ETH_DMASR_RS_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13633 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13634 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
AnnaBridge 161:aa5281ff4a02 13635 #define ETH_DMASR_TUS_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13636 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13637 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
AnnaBridge 161:aa5281ff4a02 13638 #define ETH_DMASR_ROS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13639 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13640 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
AnnaBridge 161:aa5281ff4a02 13641 #define ETH_DMASR_TJTS_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13642 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13643 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
AnnaBridge 161:aa5281ff4a02 13644 #define ETH_DMASR_TBUS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13645 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13646 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
AnnaBridge 161:aa5281ff4a02 13647 #define ETH_DMASR_TPSS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13648 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13649 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
AnnaBridge 161:aa5281ff4a02 13650 #define ETH_DMASR_TS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13651 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13652 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
AnnaBridge 161:aa5281ff4a02 13653
AnnaBridge 161:aa5281ff4a02 13654 /* Bit definition for Ethernet DMA Operation Mode Register */
AnnaBridge 161:aa5281ff4a02 13655 #define ETH_DMAOMR_DTCEFD_Pos (26U)
AnnaBridge 161:aa5281ff4a02 13656 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 13657 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
AnnaBridge 161:aa5281ff4a02 13658 #define ETH_DMAOMR_RSF_Pos (25U)
AnnaBridge 161:aa5281ff4a02 13659 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 13660 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
AnnaBridge 161:aa5281ff4a02 13661 #define ETH_DMAOMR_DFRF_Pos (24U)
AnnaBridge 161:aa5281ff4a02 13662 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 13663 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
AnnaBridge 161:aa5281ff4a02 13664 #define ETH_DMAOMR_TSF_Pos (21U)
AnnaBridge 161:aa5281ff4a02 13665 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 13666 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
AnnaBridge 161:aa5281ff4a02 13667 #define ETH_DMAOMR_FTF_Pos (20U)
AnnaBridge 161:aa5281ff4a02 13668 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 13669 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
AnnaBridge 161:aa5281ff4a02 13670 #define ETH_DMAOMR_TTC_Pos (14U)
AnnaBridge 161:aa5281ff4a02 13671 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
AnnaBridge 161:aa5281ff4a02 13672 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
AnnaBridge 161:aa5281ff4a02 13673 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
AnnaBridge 161:aa5281ff4a02 13674 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
AnnaBridge 161:aa5281ff4a02 13675 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
AnnaBridge 161:aa5281ff4a02 13676 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
AnnaBridge 161:aa5281ff4a02 13677 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
AnnaBridge 161:aa5281ff4a02 13678 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
AnnaBridge 161:aa5281ff4a02 13679 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
AnnaBridge 161:aa5281ff4a02 13680 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
AnnaBridge 161:aa5281ff4a02 13681 #define ETH_DMAOMR_ST_Pos (13U)
AnnaBridge 161:aa5281ff4a02 13682 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 13683 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
AnnaBridge 161:aa5281ff4a02 13684 #define ETH_DMAOMR_FEF_Pos (7U)
AnnaBridge 161:aa5281ff4a02 13685 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 13686 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
AnnaBridge 161:aa5281ff4a02 13687 #define ETH_DMAOMR_FUGF_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13688 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13689 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
AnnaBridge 161:aa5281ff4a02 13690 #define ETH_DMAOMR_RTC_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13691 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
AnnaBridge 161:aa5281ff4a02 13692 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
AnnaBridge 161:aa5281ff4a02 13693 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
AnnaBridge 161:aa5281ff4a02 13694 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
AnnaBridge 161:aa5281ff4a02 13695 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
AnnaBridge 161:aa5281ff4a02 13696 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
AnnaBridge 161:aa5281ff4a02 13697 #define ETH_DMAOMR_OSF_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13698 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13699 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
AnnaBridge 161:aa5281ff4a02 13700 #define ETH_DMAOMR_SR_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13701 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13702 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
AnnaBridge 161:aa5281ff4a02 13703
AnnaBridge 161:aa5281ff4a02 13704 /* Bit definition for Ethernet DMA Interrupt Enable Register */
AnnaBridge 161:aa5281ff4a02 13705 #define ETH_DMAIER_NISE_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13706 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 13707 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
AnnaBridge 161:aa5281ff4a02 13708 #define ETH_DMAIER_AISE_Pos (15U)
AnnaBridge 161:aa5281ff4a02 13709 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 13710 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
AnnaBridge 161:aa5281ff4a02 13711 #define ETH_DMAIER_ERIE_Pos (14U)
AnnaBridge 161:aa5281ff4a02 13712 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 13713 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
AnnaBridge 161:aa5281ff4a02 13714 #define ETH_DMAIER_FBEIE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 13715 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 13716 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
AnnaBridge 161:aa5281ff4a02 13717 #define ETH_DMAIER_ETIE_Pos (10U)
AnnaBridge 161:aa5281ff4a02 13718 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 13719 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
AnnaBridge 161:aa5281ff4a02 13720 #define ETH_DMAIER_RWTIE_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13721 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13722 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
AnnaBridge 161:aa5281ff4a02 13723 #define ETH_DMAIER_RPSIE_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13724 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13725 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
AnnaBridge 161:aa5281ff4a02 13726 #define ETH_DMAIER_RBUIE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 13727 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 13728 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
AnnaBridge 161:aa5281ff4a02 13729 #define ETH_DMAIER_RIE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13730 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13731 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
AnnaBridge 161:aa5281ff4a02 13732 #define ETH_DMAIER_TUIE_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13733 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13734 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
AnnaBridge 161:aa5281ff4a02 13735 #define ETH_DMAIER_ROIE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13736 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13737 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
AnnaBridge 161:aa5281ff4a02 13738 #define ETH_DMAIER_TJTIE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13739 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13740 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
AnnaBridge 161:aa5281ff4a02 13741 #define ETH_DMAIER_TBUIE_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13742 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13743 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
AnnaBridge 161:aa5281ff4a02 13744 #define ETH_DMAIER_TPSIE_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13745 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13746 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
AnnaBridge 161:aa5281ff4a02 13747 #define ETH_DMAIER_TIE_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13748 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13749 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
AnnaBridge 161:aa5281ff4a02 13750
AnnaBridge 161:aa5281ff4a02 13751 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
AnnaBridge 161:aa5281ff4a02 13752 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
AnnaBridge 161:aa5281ff4a02 13753 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 13754 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
AnnaBridge 161:aa5281ff4a02 13755 #define ETH_DMAMFBOCR_MFA_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13756 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
AnnaBridge 161:aa5281ff4a02 13757 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
AnnaBridge 161:aa5281ff4a02 13758 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13759 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 13760 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
AnnaBridge 161:aa5281ff4a02 13761 #define ETH_DMAMFBOCR_MFC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13762 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 13763 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
AnnaBridge 161:aa5281ff4a02 13764
AnnaBridge 161:aa5281ff4a02 13765 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
AnnaBridge 161:aa5281ff4a02 13766 #define ETH_DMACHTDR_HTDAP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13767 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13768 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
AnnaBridge 161:aa5281ff4a02 13769
AnnaBridge 161:aa5281ff4a02 13770 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
AnnaBridge 161:aa5281ff4a02 13771 #define ETH_DMACHRDR_HRDAP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13772 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13773 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
AnnaBridge 161:aa5281ff4a02 13774
AnnaBridge 161:aa5281ff4a02 13775 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
AnnaBridge 161:aa5281ff4a02 13776 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13777 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13778 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
AnnaBridge 161:aa5281ff4a02 13779
AnnaBridge 161:aa5281ff4a02 13780 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
AnnaBridge 161:aa5281ff4a02 13781 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13782 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 13783 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
AnnaBridge 161:aa5281ff4a02 13784
AnnaBridge 161:aa5281ff4a02 13785 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 13786 /* */
AnnaBridge 161:aa5281ff4a02 13787 /* USB_OTG */
AnnaBridge 161:aa5281ff4a02 13788 /* */
AnnaBridge 161:aa5281ff4a02 13789 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 13790 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
AnnaBridge 161:aa5281ff4a02 13791 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13792 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13793 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
AnnaBridge 161:aa5281ff4a02 13794 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13795 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13796 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
AnnaBridge 161:aa5281ff4a02 13797 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13798 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13799 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
AnnaBridge 161:aa5281ff4a02 13800 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13801 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13802 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
AnnaBridge 161:aa5281ff4a02 13803 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
AnnaBridge 161:aa5281ff4a02 13804 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 13805 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
AnnaBridge 161:aa5281ff4a02 13806 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
AnnaBridge 161:aa5281ff4a02 13807 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 13808 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
AnnaBridge 161:aa5281ff4a02 13809 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13810 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 13811 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
AnnaBridge 161:aa5281ff4a02 13812 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13813 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 13814 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
AnnaBridge 161:aa5281ff4a02 13815 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
AnnaBridge 161:aa5281ff4a02 13816 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 13817 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
AnnaBridge 161:aa5281ff4a02 13818 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
AnnaBridge 161:aa5281ff4a02 13819 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 13820 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
AnnaBridge 161:aa5281ff4a02 13821
AnnaBridge 161:aa5281ff4a02 13822 /******************** Bit definition forUSB_OTG_HCFG register ********************/
AnnaBridge 161:aa5281ff4a02 13823
AnnaBridge 161:aa5281ff4a02 13824 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13825 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 13826 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
AnnaBridge 161:aa5281ff4a02 13827 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13828 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13829 #define USB_OTG_HCFG_FSLSS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13830 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13831 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
AnnaBridge 161:aa5281ff4a02 13832
AnnaBridge 161:aa5281ff4a02 13833 /******************** Bit definition for USB_OTG_DCFG register ********************/
AnnaBridge 161:aa5281ff4a02 13834
AnnaBridge 161:aa5281ff4a02 13835 #define USB_OTG_DCFG_DSPD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13836 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
AnnaBridge 161:aa5281ff4a02 13837 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
AnnaBridge 161:aa5281ff4a02 13838 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13839 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13840 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13841 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13842 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
AnnaBridge 161:aa5281ff4a02 13843
AnnaBridge 161:aa5281ff4a02 13844 #define USB_OTG_DCFG_DAD_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13845 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
AnnaBridge 161:aa5281ff4a02 13846 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
AnnaBridge 161:aa5281ff4a02 13847 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13848 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13849 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13850 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 13851 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13852 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13853 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 13854
AnnaBridge 161:aa5281ff4a02 13855 #define USB_OTG_DCFG_PFIVL_Pos (11U)
AnnaBridge 161:aa5281ff4a02 13856 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
AnnaBridge 161:aa5281ff4a02 13857 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
AnnaBridge 161:aa5281ff4a02 13858 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 13859 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 13860
AnnaBridge 161:aa5281ff4a02 13861 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
AnnaBridge 161:aa5281ff4a02 13862 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
AnnaBridge 161:aa5281ff4a02 13863 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
AnnaBridge 161:aa5281ff4a02 13864 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 13865 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 13866
AnnaBridge 161:aa5281ff4a02 13867 /******************** Bit definition for USB_OTG_PCGCR register ********************/
AnnaBridge 161:aa5281ff4a02 13868 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13869 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13870 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
AnnaBridge 161:aa5281ff4a02 13871 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13872 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13873 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
AnnaBridge 161:aa5281ff4a02 13874 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13875 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13876 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
AnnaBridge 161:aa5281ff4a02 13877
AnnaBridge 161:aa5281ff4a02 13878 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
AnnaBridge 161:aa5281ff4a02 13879 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13880 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13881 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
AnnaBridge 161:aa5281ff4a02 13882 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13883 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13884 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
AnnaBridge 161:aa5281ff4a02 13885 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13886 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13887 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
AnnaBridge 161:aa5281ff4a02 13888 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
AnnaBridge 161:aa5281ff4a02 13889 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 13890 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
AnnaBridge 161:aa5281ff4a02 13891 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
AnnaBridge 161:aa5281ff4a02 13892 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 13893 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
AnnaBridge 161:aa5281ff4a02 13894 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
AnnaBridge 161:aa5281ff4a02 13895 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 13896 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
AnnaBridge 161:aa5281ff4a02 13897
AnnaBridge 161:aa5281ff4a02 13898 /******************** Bit definition for USB_OTG_DCTL register ********************/
AnnaBridge 161:aa5281ff4a02 13899 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13900 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13901 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
AnnaBridge 161:aa5281ff4a02 13902 #define USB_OTG_DCTL_SDIS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13903 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13904 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
AnnaBridge 161:aa5281ff4a02 13905 #define USB_OTG_DCTL_GINSTS_Pos (2U)
AnnaBridge 161:aa5281ff4a02 13906 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13907 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
AnnaBridge 161:aa5281ff4a02 13908 #define USB_OTG_DCTL_GONSTS_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13909 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13910 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
AnnaBridge 161:aa5281ff4a02 13911
AnnaBridge 161:aa5281ff4a02 13912 #define USB_OTG_DCTL_TCTL_Pos (4U)
AnnaBridge 161:aa5281ff4a02 13913 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
AnnaBridge 161:aa5281ff4a02 13914 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
AnnaBridge 161:aa5281ff4a02 13915 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 13916 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13917 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13918 #define USB_OTG_DCTL_SGINAK_Pos (7U)
AnnaBridge 161:aa5281ff4a02 13919 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 13920 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
AnnaBridge 161:aa5281ff4a02 13921 #define USB_OTG_DCTL_CGINAK_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13922 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13923 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
AnnaBridge 161:aa5281ff4a02 13924 #define USB_OTG_DCTL_SGONAK_Pos (9U)
AnnaBridge 161:aa5281ff4a02 13925 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 13926 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
AnnaBridge 161:aa5281ff4a02 13927 #define USB_OTG_DCTL_CGONAK_Pos (10U)
AnnaBridge 161:aa5281ff4a02 13928 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 13929 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
AnnaBridge 161:aa5281ff4a02 13930 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
AnnaBridge 161:aa5281ff4a02 13931 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 13932 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
AnnaBridge 161:aa5281ff4a02 13933
AnnaBridge 161:aa5281ff4a02 13934 /******************** Bit definition for USB_OTG_HFIR register ********************/
AnnaBridge 161:aa5281ff4a02 13935 #define USB_OTG_HFIR_FRIVL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13936 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 13937 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
AnnaBridge 161:aa5281ff4a02 13938
AnnaBridge 161:aa5281ff4a02 13939 /******************** Bit definition for USB_OTG_HFNUM register ********************/
AnnaBridge 161:aa5281ff4a02 13940 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13941 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 13942 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
AnnaBridge 161:aa5281ff4a02 13943 #define USB_OTG_HFNUM_FTREM_Pos (16U)
AnnaBridge 161:aa5281ff4a02 13944 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 13945 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
AnnaBridge 161:aa5281ff4a02 13946
AnnaBridge 161:aa5281ff4a02 13947 /******************** Bit definition for USB_OTG_DSTS register ********************/
AnnaBridge 161:aa5281ff4a02 13948 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13949 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13950 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
AnnaBridge 161:aa5281ff4a02 13951
AnnaBridge 161:aa5281ff4a02 13952 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13953 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
AnnaBridge 161:aa5281ff4a02 13954 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
AnnaBridge 161:aa5281ff4a02 13955 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13956 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13957 #define USB_OTG_DSTS_EERR_Pos (3U)
AnnaBridge 161:aa5281ff4a02 13958 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 13959 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
AnnaBridge 161:aa5281ff4a02 13960 #define USB_OTG_DSTS_FNSOF_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13961 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
AnnaBridge 161:aa5281ff4a02 13962 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
AnnaBridge 161:aa5281ff4a02 13963
AnnaBridge 161:aa5281ff4a02 13964 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
AnnaBridge 161:aa5281ff4a02 13965 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13966 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13967 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
AnnaBridge 161:aa5281ff4a02 13968 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 13969 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
AnnaBridge 161:aa5281ff4a02 13970 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
AnnaBridge 161:aa5281ff4a02 13971 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
AnnaBridge 161:aa5281ff4a02 13972 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
AnnaBridge 161:aa5281ff4a02 13973 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
AnnaBridge 161:aa5281ff4a02 13974 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
AnnaBridge 161:aa5281ff4a02 13975 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
AnnaBridge 161:aa5281ff4a02 13976 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
AnnaBridge 161:aa5281ff4a02 13977 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 13978 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
AnnaBridge 161:aa5281ff4a02 13979 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
AnnaBridge 161:aa5281ff4a02 13980 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 13981 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
AnnaBridge 161:aa5281ff4a02 13982 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13983 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13984 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
AnnaBridge 161:aa5281ff4a02 13985
AnnaBridge 161:aa5281ff4a02 13986 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
AnnaBridge 161:aa5281ff4a02 13987
AnnaBridge 161:aa5281ff4a02 13988 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 13989 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
AnnaBridge 161:aa5281ff4a02 13990 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
AnnaBridge 161:aa5281ff4a02 13991 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 13992 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 13993 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 13994 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
AnnaBridge 161:aa5281ff4a02 13995 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 13996 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 161:aa5281ff4a02 13997 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
AnnaBridge 161:aa5281ff4a02 13998 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 13999 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
AnnaBridge 161:aa5281ff4a02 14000 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
AnnaBridge 161:aa5281ff4a02 14001 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14002 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
AnnaBridge 161:aa5281ff4a02 14003 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
AnnaBridge 161:aa5281ff4a02 14004 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
AnnaBridge 161:aa5281ff4a02 14005 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
AnnaBridge 161:aa5281ff4a02 14006 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14007 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 14008 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 14009 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14010 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
AnnaBridge 161:aa5281ff4a02 14011 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 14012 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
AnnaBridge 161:aa5281ff4a02 14013 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14014 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14015 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
AnnaBridge 161:aa5281ff4a02 14016 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
AnnaBridge 161:aa5281ff4a02 14017 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14018 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
AnnaBridge 161:aa5281ff4a02 14019 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
AnnaBridge 161:aa5281ff4a02 14020 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14021 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
AnnaBridge 161:aa5281ff4a02 14022 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
AnnaBridge 161:aa5281ff4a02 14023 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14024 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
AnnaBridge 161:aa5281ff4a02 14025 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
AnnaBridge 161:aa5281ff4a02 14026 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14027 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
AnnaBridge 161:aa5281ff4a02 14028 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
AnnaBridge 161:aa5281ff4a02 14029 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 14030 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
AnnaBridge 161:aa5281ff4a02 14031 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
AnnaBridge 161:aa5281ff4a02 14032 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 14033 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
AnnaBridge 161:aa5281ff4a02 14034 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
AnnaBridge 161:aa5281ff4a02 14035 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 14036 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
AnnaBridge 161:aa5281ff4a02 14037 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
AnnaBridge 161:aa5281ff4a02 14038 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 14039 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
AnnaBridge 161:aa5281ff4a02 14040 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14041 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14042 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
AnnaBridge 161:aa5281ff4a02 14043 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
AnnaBridge 161:aa5281ff4a02 14044 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14045 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
AnnaBridge 161:aa5281ff4a02 14046 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14047 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14048 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
AnnaBridge 161:aa5281ff4a02 14049
AnnaBridge 161:aa5281ff4a02 14050 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
AnnaBridge 161:aa5281ff4a02 14051 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14052 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14053 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
AnnaBridge 161:aa5281ff4a02 14054 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14055 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14056 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
AnnaBridge 161:aa5281ff4a02 14057 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
AnnaBridge 161:aa5281ff4a02 14058 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 14059 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
AnnaBridge 161:aa5281ff4a02 14060 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14061 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14062 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
AnnaBridge 161:aa5281ff4a02 14063 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14064 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14065 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
AnnaBridge 161:aa5281ff4a02 14066
AnnaBridge 161:aa5281ff4a02 14067
AnnaBridge 161:aa5281ff4a02 14068 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14069 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
AnnaBridge 161:aa5281ff4a02 14070 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 161:aa5281ff4a02 14071 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14072 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14073 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14074 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14075 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14076 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
AnnaBridge 161:aa5281ff4a02 14077 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14078 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
AnnaBridge 161:aa5281ff4a02 14079 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14080 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14081 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
AnnaBridge 161:aa5281ff4a02 14082
AnnaBridge 161:aa5281ff4a02 14083 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
AnnaBridge 161:aa5281ff4a02 14084 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14085 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14086 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 161:aa5281ff4a02 14087 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14088 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14089 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 161:aa5281ff4a02 14090 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14091 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14092 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 161:aa5281ff4a02 14093 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14094 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14095 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 161:aa5281ff4a02 14096 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14097 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14098 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 161:aa5281ff4a02 14099 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14100 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14101 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 161:aa5281ff4a02 14102 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
AnnaBridge 161:aa5281ff4a02 14103 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14104 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 161:aa5281ff4a02 14105 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
AnnaBridge 161:aa5281ff4a02 14106 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14107 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 161:aa5281ff4a02 14108
AnnaBridge 161:aa5281ff4a02 14109 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
AnnaBridge 161:aa5281ff4a02 14110 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14111 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14112 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
AnnaBridge 161:aa5281ff4a02 14113 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14114 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 14115 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
AnnaBridge 161:aa5281ff4a02 14116 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 14117 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14118 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14119 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14120 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14121 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14122 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 14123 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 14124
AnnaBridge 161:aa5281ff4a02 14125 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
AnnaBridge 161:aa5281ff4a02 14126 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
AnnaBridge 161:aa5281ff4a02 14127 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
AnnaBridge 161:aa5281ff4a02 14128 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 14129 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 14130 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 14131 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 14132 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 14133 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14134 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14135 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14136
AnnaBridge 161:aa5281ff4a02 14137 /******************** Bit definition for USB_OTG_HAINT register ********************/
AnnaBridge 161:aa5281ff4a02 14138 #define USB_OTG_HAINT_HAINT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14139 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14140 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
AnnaBridge 161:aa5281ff4a02 14141
AnnaBridge 161:aa5281ff4a02 14142 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
AnnaBridge 161:aa5281ff4a02 14143 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14144 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14145 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 161:aa5281ff4a02 14146 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14147 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14148 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 161:aa5281ff4a02 14149 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14150 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14151 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
AnnaBridge 161:aa5281ff4a02 14152 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14153 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14154 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
AnnaBridge 161:aa5281ff4a02 14155 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14156 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14157 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
AnnaBridge 161:aa5281ff4a02 14158 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
AnnaBridge 161:aa5281ff4a02 14159 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14160 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
AnnaBridge 161:aa5281ff4a02 14161 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
AnnaBridge 161:aa5281ff4a02 14162 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14163 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
AnnaBridge 161:aa5281ff4a02 14164
AnnaBridge 161:aa5281ff4a02 14165 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
AnnaBridge 161:aa5281ff4a02 14166 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14167 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14168 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
AnnaBridge 161:aa5281ff4a02 14169 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14170 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14171 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
AnnaBridge 161:aa5281ff4a02 14172 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
AnnaBridge 161:aa5281ff4a02 14173 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 14174 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
AnnaBridge 161:aa5281ff4a02 14175 #define USB_OTG_GINTSTS_SOF_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14176 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14177 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
AnnaBridge 161:aa5281ff4a02 14178 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14179 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14180 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
AnnaBridge 161:aa5281ff4a02 14181 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14182 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14183 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
AnnaBridge 161:aa5281ff4a02 14184 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14185 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14186 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
AnnaBridge 161:aa5281ff4a02 14187 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
AnnaBridge 161:aa5281ff4a02 14188 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14189 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
AnnaBridge 161:aa5281ff4a02 14190 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
AnnaBridge 161:aa5281ff4a02 14191 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14192 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
AnnaBridge 161:aa5281ff4a02 14193 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
AnnaBridge 161:aa5281ff4a02 14194 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 14195 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
AnnaBridge 161:aa5281ff4a02 14196 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
AnnaBridge 161:aa5281ff4a02 14197 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 14198 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
AnnaBridge 161:aa5281ff4a02 14199 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
AnnaBridge 161:aa5281ff4a02 14200 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14201 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
AnnaBridge 161:aa5281ff4a02 14202 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
AnnaBridge 161:aa5281ff4a02 14203 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 14204 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 161:aa5281ff4a02 14205 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
AnnaBridge 161:aa5281ff4a02 14206 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 14207 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
AnnaBridge 161:aa5281ff4a02 14208 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
AnnaBridge 161:aa5281ff4a02 14209 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14210 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
AnnaBridge 161:aa5281ff4a02 14211 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
AnnaBridge 161:aa5281ff4a02 14212 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14213 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
AnnaBridge 161:aa5281ff4a02 14214 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
AnnaBridge 161:aa5281ff4a02 14215 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14216 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
AnnaBridge 161:aa5281ff4a02 14217 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
AnnaBridge 161:aa5281ff4a02 14218 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14219 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
AnnaBridge 161:aa5281ff4a02 14220 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
AnnaBridge 161:aa5281ff4a02 14221 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 14222 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
AnnaBridge 161:aa5281ff4a02 14223 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
AnnaBridge 161:aa5281ff4a02 14224 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 14225 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
AnnaBridge 161:aa5281ff4a02 14226 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
AnnaBridge 161:aa5281ff4a02 14227 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 14228 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
AnnaBridge 161:aa5281ff4a02 14229 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
AnnaBridge 161:aa5281ff4a02 14230 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 14231 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
AnnaBridge 161:aa5281ff4a02 14232 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
AnnaBridge 161:aa5281ff4a02 14233 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 14234 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
AnnaBridge 161:aa5281ff4a02 14235 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14236 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14237 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
AnnaBridge 161:aa5281ff4a02 14238 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
AnnaBridge 161:aa5281ff4a02 14239 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14240 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
AnnaBridge 161:aa5281ff4a02 14241 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14242 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14243 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 161:aa5281ff4a02 14244
AnnaBridge 161:aa5281ff4a02 14245 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
AnnaBridge 161:aa5281ff4a02 14246 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14247 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14248 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
AnnaBridge 161:aa5281ff4a02 14249 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
AnnaBridge 161:aa5281ff4a02 14250 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 14251 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
AnnaBridge 161:aa5281ff4a02 14252 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14253 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14254 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
AnnaBridge 161:aa5281ff4a02 14255 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14256 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14257 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
AnnaBridge 161:aa5281ff4a02 14258 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14259 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14260 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 161:aa5281ff4a02 14261 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14262 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14263 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 161:aa5281ff4a02 14264 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
AnnaBridge 161:aa5281ff4a02 14265 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14266 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
AnnaBridge 161:aa5281ff4a02 14267 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
AnnaBridge 161:aa5281ff4a02 14268 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14269 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
AnnaBridge 161:aa5281ff4a02 14270 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
AnnaBridge 161:aa5281ff4a02 14271 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 14272 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
AnnaBridge 161:aa5281ff4a02 14273 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
AnnaBridge 161:aa5281ff4a02 14274 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 14275 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
AnnaBridge 161:aa5281ff4a02 14276 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
AnnaBridge 161:aa5281ff4a02 14277 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14278 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
AnnaBridge 161:aa5281ff4a02 14279 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
AnnaBridge 161:aa5281ff4a02 14280 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 14281 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 161:aa5281ff4a02 14282 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
AnnaBridge 161:aa5281ff4a02 14283 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 14284 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
AnnaBridge 161:aa5281ff4a02 14285 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14286 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14287 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
AnnaBridge 161:aa5281ff4a02 14288 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
AnnaBridge 161:aa5281ff4a02 14289 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14290 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
AnnaBridge 161:aa5281ff4a02 14291 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
AnnaBridge 161:aa5281ff4a02 14292 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14293 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
AnnaBridge 161:aa5281ff4a02 14294 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
AnnaBridge 161:aa5281ff4a02 14295 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14296 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 161:aa5281ff4a02 14297 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
AnnaBridge 161:aa5281ff4a02 14298 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14299 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
AnnaBridge 161:aa5281ff4a02 14300 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
AnnaBridge 161:aa5281ff4a02 14301 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 14302 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
AnnaBridge 161:aa5281ff4a02 14303 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
AnnaBridge 161:aa5281ff4a02 14304 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 14305 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
AnnaBridge 161:aa5281ff4a02 14306 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
AnnaBridge 161:aa5281ff4a02 14307 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 14308 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
AnnaBridge 161:aa5281ff4a02 14309 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
AnnaBridge 161:aa5281ff4a02 14310 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 14311 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
AnnaBridge 161:aa5281ff4a02 14312 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
AnnaBridge 161:aa5281ff4a02 14313 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 14314 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
AnnaBridge 161:aa5281ff4a02 14315 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14316 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14317 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
AnnaBridge 161:aa5281ff4a02 14318 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
AnnaBridge 161:aa5281ff4a02 14319 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14320 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
AnnaBridge 161:aa5281ff4a02 14321 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14322 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14323 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 161:aa5281ff4a02 14324
AnnaBridge 161:aa5281ff4a02 14325 /******************** Bit definition for USB_OTG_DAINT register ********************/
AnnaBridge 161:aa5281ff4a02 14326 #define USB_OTG_DAINT_IEPINT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14327 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14328 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
AnnaBridge 161:aa5281ff4a02 14329 #define USB_OTG_DAINT_OEPINT_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14330 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 14331 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
AnnaBridge 161:aa5281ff4a02 14332
AnnaBridge 161:aa5281ff4a02 14333 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
AnnaBridge 161:aa5281ff4a02 14334 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14335 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14336 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
AnnaBridge 161:aa5281ff4a02 14337
AnnaBridge 161:aa5281ff4a02 14338 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 161:aa5281ff4a02 14339 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14340 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 161:aa5281ff4a02 14341 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 161:aa5281ff4a02 14342 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14343 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 161:aa5281ff4a02 14344 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 161:aa5281ff4a02 14345 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
AnnaBridge 161:aa5281ff4a02 14346 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 161:aa5281ff4a02 14347 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 161:aa5281ff4a02 14348 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14349 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 161:aa5281ff4a02 14350 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 161:aa5281ff4a02 14351
AnnaBridge 161:aa5281ff4a02 14352 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
AnnaBridge 161:aa5281ff4a02 14353 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14354 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14355 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 161:aa5281ff4a02 14356 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14357 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 14358 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 161:aa5281ff4a02 14359
AnnaBridge 161:aa5281ff4a02 14360 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
AnnaBridge 161:aa5281ff4a02 14361 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14362 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14363 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
AnnaBridge 161:aa5281ff4a02 14364
AnnaBridge 161:aa5281ff4a02 14365 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
AnnaBridge 161:aa5281ff4a02 14366 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14367 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14368 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
AnnaBridge 161:aa5281ff4a02 14369
AnnaBridge 161:aa5281ff4a02 14370 /******************** Bit definition for OTG register ********************/
AnnaBridge 161:aa5281ff4a02 14371 #define USB_OTG_NPTXFSA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14372 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14373 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
AnnaBridge 161:aa5281ff4a02 14374 #define USB_OTG_NPTXFD_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14375 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 14376 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
AnnaBridge 161:aa5281ff4a02 14377 #define USB_OTG_TX0FSA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14378 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14379 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 161:aa5281ff4a02 14380 #define USB_OTG_TX0FD_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14381 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 14382 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
AnnaBridge 161:aa5281ff4a02 14383
AnnaBridge 161:aa5281ff4a02 14384 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
AnnaBridge 161:aa5281ff4a02 14385 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14386 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
AnnaBridge 161:aa5281ff4a02 14387 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
AnnaBridge 161:aa5281ff4a02 14388
AnnaBridge 161:aa5281ff4a02 14389 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
AnnaBridge 161:aa5281ff4a02 14390 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14391 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14392 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
AnnaBridge 161:aa5281ff4a02 14393
AnnaBridge 161:aa5281ff4a02 14394 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14395 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 161:aa5281ff4a02 14396 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
AnnaBridge 161:aa5281ff4a02 14397 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 14398 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14399 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14400 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14401 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14402 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14403 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 14404 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 14405
AnnaBridge 161:aa5281ff4a02 14406 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
AnnaBridge 161:aa5281ff4a02 14407 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
AnnaBridge 161:aa5281ff4a02 14408 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 161:aa5281ff4a02 14409 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 14410 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 14411 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 14412 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 14413 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 14414 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14415 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14416
AnnaBridge 161:aa5281ff4a02 14417 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
AnnaBridge 161:aa5281ff4a02 14418 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14419 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14420 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 161:aa5281ff4a02 14421 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14422 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14423 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
AnnaBridge 161:aa5281ff4a02 14424
AnnaBridge 161:aa5281ff4a02 14425 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
AnnaBridge 161:aa5281ff4a02 14426 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
AnnaBridge 161:aa5281ff4a02 14427 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
AnnaBridge 161:aa5281ff4a02 14428 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 14429 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14430 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14431 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14432 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14433 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14434 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14435 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14436 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14437 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14438 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 14439 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
AnnaBridge 161:aa5281ff4a02 14440
AnnaBridge 161:aa5281ff4a02 14441 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14442 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
AnnaBridge 161:aa5281ff4a02 14443 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
AnnaBridge 161:aa5281ff4a02 14444 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14445 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14446 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14447 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14448 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14449 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 14450 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 14451 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 14452 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 14453 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
AnnaBridge 161:aa5281ff4a02 14454 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 14455 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
AnnaBridge 161:aa5281ff4a02 14456
AnnaBridge 161:aa5281ff4a02 14457 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 161:aa5281ff4a02 14458 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14459 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14460 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 161:aa5281ff4a02 14461
AnnaBridge 161:aa5281ff4a02 14462 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
AnnaBridge 161:aa5281ff4a02 14463 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14464 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14465 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
AnnaBridge 161:aa5281ff4a02 14466 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14467 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14468 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 161:aa5281ff4a02 14469
AnnaBridge 161:aa5281ff4a02 14470 /******************** Bit definition for USB_OTG_GCCFG register ********************/
AnnaBridge 161:aa5281ff4a02 14471 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14472 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 14473 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
AnnaBridge 161:aa5281ff4a02 14474 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14475 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14476 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
AnnaBridge 161:aa5281ff4a02 14477 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
AnnaBridge 161:aa5281ff4a02 14478 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14479 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 161:aa5281ff4a02 14480 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
AnnaBridge 161:aa5281ff4a02 14481 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14482 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 161:aa5281ff4a02 14483 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
AnnaBridge 161:aa5281ff4a02 14484 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14485 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
AnnaBridge 161:aa5281ff4a02 14486 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
AnnaBridge 161:aa5281ff4a02 14487 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14488 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
AnnaBridge 161:aa5281ff4a02 14489
AnnaBridge 161:aa5281ff4a02 14490 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
AnnaBridge 161:aa5281ff4a02 14491 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14492 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14493 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 161:aa5281ff4a02 14494 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14495 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14496 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 161:aa5281ff4a02 14497
AnnaBridge 161:aa5281ff4a02 14498 /******************** Bit definition for USB_OTG_CID register ********************/
AnnaBridge 161:aa5281ff4a02 14499 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14500 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 14501 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
AnnaBridge 161:aa5281ff4a02 14502
AnnaBridge 161:aa5281ff4a02 14503 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 161:aa5281ff4a02 14504 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14505 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14506 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 161:aa5281ff4a02 14507 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14508 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14509 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 161:aa5281ff4a02 14510 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14511 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14512 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 161:aa5281ff4a02 14513 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14514 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14515 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 161:aa5281ff4a02 14516 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14517 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14518 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 161:aa5281ff4a02 14519 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14520 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14521 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 161:aa5281ff4a02 14522 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 161:aa5281ff4a02 14523 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14524 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 161:aa5281ff4a02 14525 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 161:aa5281ff4a02 14526 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14527 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 161:aa5281ff4a02 14528 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 161:aa5281ff4a02 14529 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14530 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 161:aa5281ff4a02 14531
AnnaBridge 161:aa5281ff4a02 14532 /******************** Bit definition for USB_OTG_HPRT register ********************/
AnnaBridge 161:aa5281ff4a02 14533 #define USB_OTG_HPRT_PCSTS_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14534 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14535 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
AnnaBridge 161:aa5281ff4a02 14536 #define USB_OTG_HPRT_PCDET_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14537 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14538 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
AnnaBridge 161:aa5281ff4a02 14539 #define USB_OTG_HPRT_PENA_Pos (2U)
AnnaBridge 161:aa5281ff4a02 14540 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 14541 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
AnnaBridge 161:aa5281ff4a02 14542 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14543 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14544 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
AnnaBridge 161:aa5281ff4a02 14545 #define USB_OTG_HPRT_POCA_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14546 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14547 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
AnnaBridge 161:aa5281ff4a02 14548 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14549 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14550 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
AnnaBridge 161:aa5281ff4a02 14551 #define USB_OTG_HPRT_PRES_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14552 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14553 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
AnnaBridge 161:aa5281ff4a02 14554 #define USB_OTG_HPRT_PSUSP_Pos (7U)
AnnaBridge 161:aa5281ff4a02 14555 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14556 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
AnnaBridge 161:aa5281ff4a02 14557 #define USB_OTG_HPRT_PRST_Pos (8U)
AnnaBridge 161:aa5281ff4a02 14558 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14559 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
AnnaBridge 161:aa5281ff4a02 14560
AnnaBridge 161:aa5281ff4a02 14561 #define USB_OTG_HPRT_PLSTS_Pos (10U)
AnnaBridge 161:aa5281ff4a02 14562 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
AnnaBridge 161:aa5281ff4a02 14563 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
AnnaBridge 161:aa5281ff4a02 14564 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14565 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 14566 #define USB_OTG_HPRT_PPWR_Pos (12U)
AnnaBridge 161:aa5281ff4a02 14567 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 14568 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
AnnaBridge 161:aa5281ff4a02 14569
AnnaBridge 161:aa5281ff4a02 14570 #define USB_OTG_HPRT_PTCTL_Pos (13U)
AnnaBridge 161:aa5281ff4a02 14571 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
AnnaBridge 161:aa5281ff4a02 14572 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
AnnaBridge 161:aa5281ff4a02 14573 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14574 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 14575 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 14576 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 14577
AnnaBridge 161:aa5281ff4a02 14578 #define USB_OTG_HPRT_PSPD_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14579 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
AnnaBridge 161:aa5281ff4a02 14580 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
AnnaBridge 161:aa5281ff4a02 14581 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14582 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14583
AnnaBridge 161:aa5281ff4a02 14584 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 161:aa5281ff4a02 14585 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14586 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14587 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 161:aa5281ff4a02 14588 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14589 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14590 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 161:aa5281ff4a02 14591 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14592 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14593 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
AnnaBridge 161:aa5281ff4a02 14594 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14595 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14596 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 161:aa5281ff4a02 14597 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14598 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14599 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 161:aa5281ff4a02 14600 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14601 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14602 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 161:aa5281ff4a02 14603 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 161:aa5281ff4a02 14604 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14605 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
AnnaBridge 161:aa5281ff4a02 14606 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 161:aa5281ff4a02 14607 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14608 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 161:aa5281ff4a02 14609 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
AnnaBridge 161:aa5281ff4a02 14610 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 14611 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
AnnaBridge 161:aa5281ff4a02 14612 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 161:aa5281ff4a02 14613 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14614 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 161:aa5281ff4a02 14615 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
AnnaBridge 161:aa5281ff4a02 14616 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 14617 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
AnnaBridge 161:aa5281ff4a02 14618
AnnaBridge 161:aa5281ff4a02 14619 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
AnnaBridge 161:aa5281ff4a02 14620 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14621 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14622 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
AnnaBridge 161:aa5281ff4a02 14623 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14624 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 14625 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
AnnaBridge 161:aa5281ff4a02 14626
AnnaBridge 161:aa5281ff4a02 14627 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
AnnaBridge 161:aa5281ff4a02 14628 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14629 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 161:aa5281ff4a02 14630 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 161:aa5281ff4a02 14631 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
AnnaBridge 161:aa5281ff4a02 14632 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 14633 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 161:aa5281ff4a02 14634 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14635 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 14636 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
AnnaBridge 161:aa5281ff4a02 14637 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14638 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14639 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 161:aa5281ff4a02 14640
AnnaBridge 161:aa5281ff4a02 14641 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
AnnaBridge 161:aa5281ff4a02 14642 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 161:aa5281ff4a02 14643 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 161:aa5281ff4a02 14644 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14645 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14646 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
AnnaBridge 161:aa5281ff4a02 14647 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14648 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 161:aa5281ff4a02 14649
AnnaBridge 161:aa5281ff4a02 14650 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
AnnaBridge 161:aa5281ff4a02 14651 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
AnnaBridge 161:aa5281ff4a02 14652 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 161:aa5281ff4a02 14653 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 14654 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 14655 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 14656 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 14657 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
AnnaBridge 161:aa5281ff4a02 14658 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 14659 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 161:aa5281ff4a02 14660 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
AnnaBridge 161:aa5281ff4a02 14661 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 14662 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 161:aa5281ff4a02 14663 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 161:aa5281ff4a02 14664 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 14665 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 161:aa5281ff4a02 14666 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14667 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14668 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 161:aa5281ff4a02 14669 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
AnnaBridge 161:aa5281ff4a02 14670 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14671 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 161:aa5281ff4a02 14672 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14673 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14674 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 161:aa5281ff4a02 14675
AnnaBridge 161:aa5281ff4a02 14676 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
AnnaBridge 161:aa5281ff4a02 14677 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14678 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 161:aa5281ff4a02 14679 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 161:aa5281ff4a02 14680
AnnaBridge 161:aa5281ff4a02 14681 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
AnnaBridge 161:aa5281ff4a02 14682 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
AnnaBridge 161:aa5281ff4a02 14683 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 161:aa5281ff4a02 14684 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 14685 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 14686 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14687 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 14688 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
AnnaBridge 161:aa5281ff4a02 14689 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 14690 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
AnnaBridge 161:aa5281ff4a02 14691 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14692 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14693 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
AnnaBridge 161:aa5281ff4a02 14694
AnnaBridge 161:aa5281ff4a02 14695 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
AnnaBridge 161:aa5281ff4a02 14696 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 161:aa5281ff4a02 14697 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 161:aa5281ff4a02 14698 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14699 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14700
AnnaBridge 161:aa5281ff4a02 14701 #define USB_OTG_HCCHAR_MC_Pos (20U)
AnnaBridge 161:aa5281ff4a02 14702 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
AnnaBridge 161:aa5281ff4a02 14703 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 161:aa5281ff4a02 14704 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14705 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14706
AnnaBridge 161:aa5281ff4a02 14707 #define USB_OTG_HCCHAR_DAD_Pos (22U)
AnnaBridge 161:aa5281ff4a02 14708 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
AnnaBridge 161:aa5281ff4a02 14709 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
AnnaBridge 161:aa5281ff4a02 14710 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
AnnaBridge 161:aa5281ff4a02 14711 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
AnnaBridge 161:aa5281ff4a02 14712 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 14713 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
AnnaBridge 161:aa5281ff4a02 14714 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 14715 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 14716 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 14717 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14718 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14719 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
AnnaBridge 161:aa5281ff4a02 14720 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
AnnaBridge 161:aa5281ff4a02 14721 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14722 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
AnnaBridge 161:aa5281ff4a02 14723 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14724 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14725 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
AnnaBridge 161:aa5281ff4a02 14726
AnnaBridge 161:aa5281ff4a02 14727 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
AnnaBridge 161:aa5281ff4a02 14728
AnnaBridge 161:aa5281ff4a02 14729 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14730 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
AnnaBridge 161:aa5281ff4a02 14731 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
AnnaBridge 161:aa5281ff4a02 14732 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14733 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14734 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 14735 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14736 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14737 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14738 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14739
AnnaBridge 161:aa5281ff4a02 14740 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
AnnaBridge 161:aa5281ff4a02 14741 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
AnnaBridge 161:aa5281ff4a02 14742 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
AnnaBridge 161:aa5281ff4a02 14743 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14744 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14745 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14746 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14747 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 14748 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 14749 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14750
AnnaBridge 161:aa5281ff4a02 14751 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
AnnaBridge 161:aa5281ff4a02 14752 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
AnnaBridge 161:aa5281ff4a02 14753 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
AnnaBridge 161:aa5281ff4a02 14754 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 14755 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 14756 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14757 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
AnnaBridge 161:aa5281ff4a02 14758 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
AnnaBridge 161:aa5281ff4a02 14759 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14760 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14761 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
AnnaBridge 161:aa5281ff4a02 14762
AnnaBridge 161:aa5281ff4a02 14763 /******************** Bit definition for USB_OTG_HCINT register ********************/
AnnaBridge 161:aa5281ff4a02 14764 #define USB_OTG_HCINT_XFRC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14765 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14766 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
AnnaBridge 161:aa5281ff4a02 14767 #define USB_OTG_HCINT_CHH_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14768 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14769 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
AnnaBridge 161:aa5281ff4a02 14770 #define USB_OTG_HCINT_AHBERR_Pos (2U)
AnnaBridge 161:aa5281ff4a02 14771 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 14772 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
AnnaBridge 161:aa5281ff4a02 14773 #define USB_OTG_HCINT_STALL_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14774 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14775 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
AnnaBridge 161:aa5281ff4a02 14776 #define USB_OTG_HCINT_NAK_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14777 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14778 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
AnnaBridge 161:aa5281ff4a02 14779 #define USB_OTG_HCINT_ACK_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14780 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14781 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
AnnaBridge 161:aa5281ff4a02 14782 #define USB_OTG_HCINT_NYET_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14783 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14784 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
AnnaBridge 161:aa5281ff4a02 14785 #define USB_OTG_HCINT_TXERR_Pos (7U)
AnnaBridge 161:aa5281ff4a02 14786 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14787 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
AnnaBridge 161:aa5281ff4a02 14788 #define USB_OTG_HCINT_BBERR_Pos (8U)
AnnaBridge 161:aa5281ff4a02 14789 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14790 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
AnnaBridge 161:aa5281ff4a02 14791 #define USB_OTG_HCINT_FRMOR_Pos (9U)
AnnaBridge 161:aa5281ff4a02 14792 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14793 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
AnnaBridge 161:aa5281ff4a02 14794 #define USB_OTG_HCINT_DTERR_Pos (10U)
AnnaBridge 161:aa5281ff4a02 14795 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14796 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
AnnaBridge 161:aa5281ff4a02 14797
AnnaBridge 161:aa5281ff4a02 14798 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
AnnaBridge 161:aa5281ff4a02 14799 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14800 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14801 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 161:aa5281ff4a02 14802 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14803 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14804 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 161:aa5281ff4a02 14805 #define USB_OTG_DIEPINT_TOC_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14806 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14807 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
AnnaBridge 161:aa5281ff4a02 14808 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14809 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14810 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
AnnaBridge 161:aa5281ff4a02 14811 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14812 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14813 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
AnnaBridge 161:aa5281ff4a02 14814 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
AnnaBridge 161:aa5281ff4a02 14815 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14816 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
AnnaBridge 161:aa5281ff4a02 14817 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
AnnaBridge 161:aa5281ff4a02 14818 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14819 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
AnnaBridge 161:aa5281ff4a02 14820 #define USB_OTG_DIEPINT_BNA_Pos (9U)
AnnaBridge 161:aa5281ff4a02 14821 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14822 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
AnnaBridge 161:aa5281ff4a02 14823 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
AnnaBridge 161:aa5281ff4a02 14824 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
AnnaBridge 161:aa5281ff4a02 14825 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
AnnaBridge 161:aa5281ff4a02 14826 #define USB_OTG_DIEPINT_BERR_Pos (12U)
AnnaBridge 161:aa5281ff4a02 14827 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
AnnaBridge 161:aa5281ff4a02 14828 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
AnnaBridge 161:aa5281ff4a02 14829 #define USB_OTG_DIEPINT_NAK_Pos (13U)
AnnaBridge 161:aa5281ff4a02 14830 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
AnnaBridge 161:aa5281ff4a02 14831 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
AnnaBridge 161:aa5281ff4a02 14832
AnnaBridge 161:aa5281ff4a02 14833 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
AnnaBridge 161:aa5281ff4a02 14834 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14835 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14836 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
AnnaBridge 161:aa5281ff4a02 14837 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14838 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14839 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
AnnaBridge 161:aa5281ff4a02 14840 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
AnnaBridge 161:aa5281ff4a02 14841 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 161:aa5281ff4a02 14842 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
AnnaBridge 161:aa5281ff4a02 14843 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14844 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14845 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
AnnaBridge 161:aa5281ff4a02 14846 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14847 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14848 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
AnnaBridge 161:aa5281ff4a02 14849 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
AnnaBridge 161:aa5281ff4a02 14850 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
AnnaBridge 161:aa5281ff4a02 14851 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 161:aa5281ff4a02 14852 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14853 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14854 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
AnnaBridge 161:aa5281ff4a02 14855 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
AnnaBridge 161:aa5281ff4a02 14856 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
AnnaBridge 161:aa5281ff4a02 14857 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
AnnaBridge 161:aa5281ff4a02 14858 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
AnnaBridge 161:aa5281ff4a02 14859 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
AnnaBridge 161:aa5281ff4a02 14860 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
AnnaBridge 161:aa5281ff4a02 14861 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
AnnaBridge 161:aa5281ff4a02 14862 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
AnnaBridge 161:aa5281ff4a02 14863 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
AnnaBridge 161:aa5281ff4a02 14864 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
AnnaBridge 161:aa5281ff4a02 14865 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
AnnaBridge 161:aa5281ff4a02 14866 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
AnnaBridge 161:aa5281ff4a02 14867
AnnaBridge 161:aa5281ff4a02 14868 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
AnnaBridge 161:aa5281ff4a02 14869
AnnaBridge 161:aa5281ff4a02 14870 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14871 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 161:aa5281ff4a02 14872 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 161:aa5281ff4a02 14873 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 161:aa5281ff4a02 14874 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 161:aa5281ff4a02 14875 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 161:aa5281ff4a02 14876 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14877 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
AnnaBridge 161:aa5281ff4a02 14878 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
AnnaBridge 161:aa5281ff4a02 14879 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
AnnaBridge 161:aa5281ff4a02 14880 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14881 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 161:aa5281ff4a02 14882 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 161:aa5281ff4a02 14883 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
AnnaBridge 161:aa5281ff4a02 14884 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 161:aa5281ff4a02 14885 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 161:aa5281ff4a02 14886 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14887 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14888 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
AnnaBridge 161:aa5281ff4a02 14889 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14890 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
AnnaBridge 161:aa5281ff4a02 14891 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
AnnaBridge 161:aa5281ff4a02 14892 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14893 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14894
AnnaBridge 161:aa5281ff4a02 14895 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
AnnaBridge 161:aa5281ff4a02 14896 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14897 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 14898 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 161:aa5281ff4a02 14899
AnnaBridge 161:aa5281ff4a02 14900 /******************** Bit definition for USB_OTG_HCDMA register ********************/
AnnaBridge 161:aa5281ff4a02 14901 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14902 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 161:aa5281ff4a02 14903 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 161:aa5281ff4a02 14904
AnnaBridge 161:aa5281ff4a02 14905 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
AnnaBridge 161:aa5281ff4a02 14906 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14907 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14908 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
AnnaBridge 161:aa5281ff4a02 14909
AnnaBridge 161:aa5281ff4a02 14910 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
AnnaBridge 161:aa5281ff4a02 14911 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14912 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 161:aa5281ff4a02 14913 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 161:aa5281ff4a02 14914 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
AnnaBridge 161:aa5281ff4a02 14915 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 161:aa5281ff4a02 14916 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
AnnaBridge 161:aa5281ff4a02 14917
AnnaBridge 161:aa5281ff4a02 14918 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
AnnaBridge 161:aa5281ff4a02 14919
AnnaBridge 161:aa5281ff4a02 14920 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14921 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 161:aa5281ff4a02 14922 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 161:aa5281ff4a02 14923 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
AnnaBridge 161:aa5281ff4a02 14924 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 161:aa5281ff4a02 14925 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 161:aa5281ff4a02 14926 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
AnnaBridge 161:aa5281ff4a02 14927 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 161:aa5281ff4a02 14928 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 161:aa5281ff4a02 14929 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 161:aa5281ff4a02 14930 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 161:aa5281ff4a02 14931 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 161:aa5281ff4a02 14932 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14933 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14934 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 161:aa5281ff4a02 14935 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
AnnaBridge 161:aa5281ff4a02 14936 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 161:aa5281ff4a02 14937 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 161:aa5281ff4a02 14938 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 161:aa5281ff4a02 14939 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 161:aa5281ff4a02 14940 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
AnnaBridge 161:aa5281ff4a02 14941 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
AnnaBridge 161:aa5281ff4a02 14942 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
AnnaBridge 161:aa5281ff4a02 14943 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
AnnaBridge 161:aa5281ff4a02 14944 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 161:aa5281ff4a02 14945 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 161:aa5281ff4a02 14946 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
AnnaBridge 161:aa5281ff4a02 14947 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 161:aa5281ff4a02 14948 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 161:aa5281ff4a02 14949 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
AnnaBridge 161:aa5281ff4a02 14950 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 161:aa5281ff4a02 14951 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 161:aa5281ff4a02 14952 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
AnnaBridge 161:aa5281ff4a02 14953 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14954 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 161:aa5281ff4a02 14955 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
AnnaBridge 161:aa5281ff4a02 14956 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 161:aa5281ff4a02 14957 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 161:aa5281ff4a02 14958
AnnaBridge 161:aa5281ff4a02 14959 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
AnnaBridge 161:aa5281ff4a02 14960 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14961 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14962 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 161:aa5281ff4a02 14963 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14964 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 14965 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 161:aa5281ff4a02 14966 #define USB_OTG_DOEPINT_STUP_Pos (3U)
AnnaBridge 161:aa5281ff4a02 14967 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
AnnaBridge 161:aa5281ff4a02 14968 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
AnnaBridge 161:aa5281ff4a02 14969 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
AnnaBridge 161:aa5281ff4a02 14970 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 14971 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
AnnaBridge 161:aa5281ff4a02 14972 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
AnnaBridge 161:aa5281ff4a02 14973 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 161:aa5281ff4a02 14974 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
AnnaBridge 161:aa5281ff4a02 14975 #define USB_OTG_DOEPINT_NYET_Pos (14U)
AnnaBridge 161:aa5281ff4a02 14976 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
AnnaBridge 161:aa5281ff4a02 14977 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
AnnaBridge 161:aa5281ff4a02 14978
AnnaBridge 161:aa5281ff4a02 14979 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
AnnaBridge 161:aa5281ff4a02 14980
AnnaBridge 161:aa5281ff4a02 14981 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14982 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 161:aa5281ff4a02 14983 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 161:aa5281ff4a02 14984 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 161:aa5281ff4a02 14985 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 161:aa5281ff4a02 14986 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 161:aa5281ff4a02 14987
AnnaBridge 161:aa5281ff4a02 14988 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
AnnaBridge 161:aa5281ff4a02 14989 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
AnnaBridge 161:aa5281ff4a02 14990 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
AnnaBridge 161:aa5281ff4a02 14991 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
AnnaBridge 161:aa5281ff4a02 14992 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
AnnaBridge 161:aa5281ff4a02 14993
AnnaBridge 161:aa5281ff4a02 14994 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 161:aa5281ff4a02 14995 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
AnnaBridge 161:aa5281ff4a02 14996 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 161:aa5281ff4a02 14997 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
AnnaBridge 161:aa5281ff4a02 14998 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
AnnaBridge 161:aa5281ff4a02 14999 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
AnnaBridge 161:aa5281ff4a02 15000 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
AnnaBridge 161:aa5281ff4a02 15001 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
AnnaBridge 161:aa5281ff4a02 15002 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 161:aa5281ff4a02 15003 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
AnnaBridge 161:aa5281ff4a02 15004
AnnaBridge 163:e59c8e839560 15005 /* Legacy define */
AnnaBridge 163:e59c8e839560 15006 /******************** Bit definition for OTG register ********************/
AnnaBridge 163:e59c8e839560 15007 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 163:e59c8e839560 15008 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 163:e59c8e839560 15009 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 163:e59c8e839560 15010 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 163:e59c8e839560 15011 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 163:e59c8e839560 15012 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 163:e59c8e839560 15013 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 163:e59c8e839560 15014 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 163:e59c8e839560 15015 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 163:e59c8e839560 15016 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 163:e59c8e839560 15017
AnnaBridge 163:e59c8e839560 15018 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 163:e59c8e839560 15019 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 163:e59c8e839560 15020 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 163:e59c8e839560 15021 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 163:e59c8e839560 15022 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 163:e59c8e839560 15023
AnnaBridge 163:e59c8e839560 15024 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 163:e59c8e839560 15025 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 163:e59c8e839560 15026 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 163:e59c8e839560 15027 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 163:e59c8e839560 15028 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 163:e59c8e839560 15029 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 163:e59c8e839560 15030 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 163:e59c8e839560 15031
AnnaBridge 163:e59c8e839560 15032 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 163:e59c8e839560 15033 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 163:e59c8e839560 15034 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 163:e59c8e839560 15035 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 163:e59c8e839560 15036 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 163:e59c8e839560 15037 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 163:e59c8e839560 15038 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 163:e59c8e839560 15039
AnnaBridge 163:e59c8e839560 15040 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 163:e59c8e839560 15041 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 163:e59c8e839560 15042 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 163:e59c8e839560 15043 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 163:e59c8e839560 15044 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 163:e59c8e839560 15045 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 163:e59c8e839560 15046 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 161:aa5281ff4a02 15047 /**
AnnaBridge 161:aa5281ff4a02 15048 * @}
AnnaBridge 161:aa5281ff4a02 15049 */
AnnaBridge 161:aa5281ff4a02 15050
AnnaBridge 161:aa5281ff4a02 15051 /**
AnnaBridge 161:aa5281ff4a02 15052 * @}
AnnaBridge 161:aa5281ff4a02 15053 */
AnnaBridge 161:aa5281ff4a02 15054
AnnaBridge 161:aa5281ff4a02 15055 /** @addtogroup Exported_macros
AnnaBridge 161:aa5281ff4a02 15056 * @{
AnnaBridge 161:aa5281ff4a02 15057 */
AnnaBridge 161:aa5281ff4a02 15058
AnnaBridge 161:aa5281ff4a02 15059 /******************************* ADC Instances ********************************/
AnnaBridge 161:aa5281ff4a02 15060 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
AnnaBridge 161:aa5281ff4a02 15061 ((INSTANCE) == ADC2) || \
AnnaBridge 161:aa5281ff4a02 15062 ((INSTANCE) == ADC3))
AnnaBridge 161:aa5281ff4a02 15063
AnnaBridge 161:aa5281ff4a02 15064 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 161:aa5281ff4a02 15065
AnnaBridge 161:aa5281ff4a02 15066 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
AnnaBridge 161:aa5281ff4a02 15067
AnnaBridge 161:aa5281ff4a02 15068 /******************************* CAN Instances ********************************/
AnnaBridge 161:aa5281ff4a02 15069 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
AnnaBridge 161:aa5281ff4a02 15070 ((INSTANCE) == CAN2))
AnnaBridge 161:aa5281ff4a02 15071 /******************************* CRC Instances ********************************/
AnnaBridge 161:aa5281ff4a02 15072 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 161:aa5281ff4a02 15073
AnnaBridge 161:aa5281ff4a02 15074 /******************************* DAC Instances ********************************/
AnnaBridge 161:aa5281ff4a02 15075 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
AnnaBridge 161:aa5281ff4a02 15076
AnnaBridge 161:aa5281ff4a02 15077 /******************************* DCMI Instances *******************************/
AnnaBridge 161:aa5281ff4a02 15078 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
AnnaBridge 161:aa5281ff4a02 15079
AnnaBridge 161:aa5281ff4a02 15080 /******************************** DMA Instances *******************************/
AnnaBridge 161:aa5281ff4a02 15081 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 161:aa5281ff4a02 15082 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 161:aa5281ff4a02 15083 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 161:aa5281ff4a02 15084 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 161:aa5281ff4a02 15085 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 161:aa5281ff4a02 15086 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 161:aa5281ff4a02 15087 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 161:aa5281ff4a02 15088 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 161:aa5281ff4a02 15089 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 161:aa5281ff4a02 15090 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 161:aa5281ff4a02 15091 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 161:aa5281ff4a02 15092 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 161:aa5281ff4a02 15093 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 161:aa5281ff4a02 15094 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 161:aa5281ff4a02 15095 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 161:aa5281ff4a02 15096 ((INSTANCE) == DMA2_Stream7))
AnnaBridge 161:aa5281ff4a02 15097
AnnaBridge 161:aa5281ff4a02 15098 /******************************* GPIO Instances *******************************/
AnnaBridge 161:aa5281ff4a02 15099 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 161:aa5281ff4a02 15100 ((INSTANCE) == GPIOB) || \
AnnaBridge 161:aa5281ff4a02 15101 ((INSTANCE) == GPIOC) || \
AnnaBridge 161:aa5281ff4a02 15102 ((INSTANCE) == GPIOD) || \
AnnaBridge 161:aa5281ff4a02 15103 ((INSTANCE) == GPIOE) || \
AnnaBridge 161:aa5281ff4a02 15104 ((INSTANCE) == GPIOF) || \
AnnaBridge 161:aa5281ff4a02 15105 ((INSTANCE) == GPIOG) || \
AnnaBridge 161:aa5281ff4a02 15106 ((INSTANCE) == GPIOH) || \
AnnaBridge 161:aa5281ff4a02 15107 ((INSTANCE) == GPIOI))
AnnaBridge 161:aa5281ff4a02 15108
AnnaBridge 161:aa5281ff4a02 15109 /******************************** I2C Instances *******************************/
AnnaBridge 161:aa5281ff4a02 15110 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 161:aa5281ff4a02 15111 ((INSTANCE) == I2C2) || \
AnnaBridge 161:aa5281ff4a02 15112 ((INSTANCE) == I2C3))
AnnaBridge 161:aa5281ff4a02 15113
AnnaBridge 161:aa5281ff4a02 15114 /******************************* SMBUS Instances ******************************/
AnnaBridge 161:aa5281ff4a02 15115 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
AnnaBridge 161:aa5281ff4a02 15116
AnnaBridge 161:aa5281ff4a02 15117 /******************************** I2S Instances *******************************/
AnnaBridge 161:aa5281ff4a02 15118
AnnaBridge 161:aa5281ff4a02 15119 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
AnnaBridge 161:aa5281ff4a02 15120 ((INSTANCE) == SPI3))
AnnaBridge 161:aa5281ff4a02 15121
AnnaBridge 161:aa5281ff4a02 15122 /*************************** I2S Extended Instances ***************************/
AnnaBridge 161:aa5281ff4a02 15123 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
AnnaBridge 161:aa5281ff4a02 15124 ((INSTANCE) == I2S3ext))
AnnaBridge 161:aa5281ff4a02 15125 /* Legacy Defines */
AnnaBridge 161:aa5281ff4a02 15126 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
AnnaBridge 161:aa5281ff4a02 15127
AnnaBridge 161:aa5281ff4a02 15128 /******************************* RNG Instances ********************************/
AnnaBridge 161:aa5281ff4a02 15129 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
AnnaBridge 161:aa5281ff4a02 15130
AnnaBridge 161:aa5281ff4a02 15131 /****************************** RTC Instances *********************************/
AnnaBridge 161:aa5281ff4a02 15132 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 161:aa5281ff4a02 15133
AnnaBridge 161:aa5281ff4a02 15134
AnnaBridge 161:aa5281ff4a02 15135 /******************************** SPI Instances *******************************/
AnnaBridge 161:aa5281ff4a02 15136 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 161:aa5281ff4a02 15137 ((INSTANCE) == SPI2) || \
AnnaBridge 161:aa5281ff4a02 15138 ((INSTANCE) == SPI3))
AnnaBridge 161:aa5281ff4a02 15139
AnnaBridge 161:aa5281ff4a02 15140
AnnaBridge 161:aa5281ff4a02 15141 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 161:aa5281ff4a02 15142 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15143 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15144 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15145 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15146 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15147 ((INSTANCE) == TIM6) || \
AnnaBridge 161:aa5281ff4a02 15148 ((INSTANCE) == TIM7) || \
AnnaBridge 161:aa5281ff4a02 15149 ((INSTANCE) == TIM8) || \
AnnaBridge 161:aa5281ff4a02 15150 ((INSTANCE) == TIM9) || \
AnnaBridge 161:aa5281ff4a02 15151 ((INSTANCE) == TIM10)|| \
AnnaBridge 161:aa5281ff4a02 15152 ((INSTANCE) == TIM11)|| \
AnnaBridge 161:aa5281ff4a02 15153 ((INSTANCE) == TIM12)|| \
AnnaBridge 161:aa5281ff4a02 15154 ((INSTANCE) == TIM13)|| \
AnnaBridge 161:aa5281ff4a02 15155 ((INSTANCE) == TIM14))
AnnaBridge 161:aa5281ff4a02 15156
AnnaBridge 161:aa5281ff4a02 15157 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 161:aa5281ff4a02 15158 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15159 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15160 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15161 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15162 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15163 ((INSTANCE) == TIM8) || \
AnnaBridge 161:aa5281ff4a02 15164 ((INSTANCE) == TIM9) || \
AnnaBridge 161:aa5281ff4a02 15165 ((INSTANCE) == TIM10) || \
AnnaBridge 161:aa5281ff4a02 15166 ((INSTANCE) == TIM11) || \
AnnaBridge 161:aa5281ff4a02 15167 ((INSTANCE) == TIM12) || \
AnnaBridge 161:aa5281ff4a02 15168 ((INSTANCE) == TIM13) || \
AnnaBridge 161:aa5281ff4a02 15169 ((INSTANCE) == TIM14))
AnnaBridge 161:aa5281ff4a02 15170
AnnaBridge 161:aa5281ff4a02 15171 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 161:aa5281ff4a02 15172 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15173 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15174 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15175 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15176 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15177 ((INSTANCE) == TIM8) || \
AnnaBridge 161:aa5281ff4a02 15178 ((INSTANCE) == TIM9) || \
AnnaBridge 161:aa5281ff4a02 15179 ((INSTANCE) == TIM12))
AnnaBridge 161:aa5281ff4a02 15180
AnnaBridge 161:aa5281ff4a02 15181 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 161:aa5281ff4a02 15182 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15183 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15184 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15185 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15186 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15187 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15188
AnnaBridge 161:aa5281ff4a02 15189 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 161:aa5281ff4a02 15190 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15191 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15192 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15193 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15194 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15195 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15196
AnnaBridge 161:aa5281ff4a02 15197 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 161:aa5281ff4a02 15198 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15199 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15200
AnnaBridge 161:aa5281ff4a02 15201 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 161:aa5281ff4a02 15202 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15203 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15204 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15205 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15206 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15207 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15208
AnnaBridge 161:aa5281ff4a02 15209 /****************** TIM Instances : DMA requests generation (UDE) *************/
AnnaBridge 161:aa5281ff4a02 15210 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15211 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15212 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15213 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15214 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15215 ((INSTANCE) == TIM6) || \
AnnaBridge 161:aa5281ff4a02 15216 ((INSTANCE) == TIM7) || \
AnnaBridge 161:aa5281ff4a02 15217 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15218
AnnaBridge 161:aa5281ff4a02 15219 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 161:aa5281ff4a02 15220 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15221 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15222 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15223 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15224 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15225 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15226
AnnaBridge 161:aa5281ff4a02 15227 /************ TIM Instances : DMA requests generation (COMDE) *****************/
AnnaBridge 161:aa5281ff4a02 15228 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15229 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15230 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15231 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15232 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15233 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15234
AnnaBridge 161:aa5281ff4a02 15235 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 161:aa5281ff4a02 15236 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15237 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15238 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15239 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15240 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15241 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15242
AnnaBridge 161:aa5281ff4a02 15243 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 161:aa5281ff4a02 15244 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15245 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15246 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15247 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15248 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15249 ((INSTANCE) == TIM6) || \
AnnaBridge 161:aa5281ff4a02 15250 ((INSTANCE) == TIM7) || \
AnnaBridge 161:aa5281ff4a02 15251 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15252
AnnaBridge 161:aa5281ff4a02 15253 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 161:aa5281ff4a02 15254 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15255 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15256 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15257 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15258 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15259 ((INSTANCE) == TIM8) || \
AnnaBridge 161:aa5281ff4a02 15260 ((INSTANCE) == TIM9) || \
AnnaBridge 161:aa5281ff4a02 15261 ((INSTANCE) == TIM12))
AnnaBridge 161:aa5281ff4a02 15262
AnnaBridge 161:aa5281ff4a02 15263 /********************** TIM Instances : 32 bit Counter ************************/
AnnaBridge 161:aa5281ff4a02 15264 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15265 ((INSTANCE) == TIM5))
AnnaBridge 161:aa5281ff4a02 15266
AnnaBridge 161:aa5281ff4a02 15267 /***************** TIM Instances : external trigger input availabe ************/
AnnaBridge 161:aa5281ff4a02 15268 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15269 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15270 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15271 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15272 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15273 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15274
AnnaBridge 161:aa5281ff4a02 15275 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 161:aa5281ff4a02 15276 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15277 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15278 ((INSTANCE) == TIM11))
AnnaBridge 161:aa5281ff4a02 15279
AnnaBridge 161:aa5281ff4a02 15280 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 161:aa5281ff4a02 15281 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 161:aa5281ff4a02 15282 ((((INSTANCE) == TIM1) && \
AnnaBridge 161:aa5281ff4a02 15283 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15284 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 161:aa5281ff4a02 15285 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 161:aa5281ff4a02 15286 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 161:aa5281ff4a02 15287 || \
AnnaBridge 161:aa5281ff4a02 15288 (((INSTANCE) == TIM2) && \
AnnaBridge 161:aa5281ff4a02 15289 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15290 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 161:aa5281ff4a02 15291 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 161:aa5281ff4a02 15292 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 161:aa5281ff4a02 15293 || \
AnnaBridge 161:aa5281ff4a02 15294 (((INSTANCE) == TIM3) && \
AnnaBridge 161:aa5281ff4a02 15295 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15296 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 161:aa5281ff4a02 15297 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 161:aa5281ff4a02 15298 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 161:aa5281ff4a02 15299 || \
AnnaBridge 161:aa5281ff4a02 15300 (((INSTANCE) == TIM4) && \
AnnaBridge 161:aa5281ff4a02 15301 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15302 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 161:aa5281ff4a02 15303 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 161:aa5281ff4a02 15304 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 161:aa5281ff4a02 15305 || \
AnnaBridge 161:aa5281ff4a02 15306 (((INSTANCE) == TIM5) && \
AnnaBridge 161:aa5281ff4a02 15307 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15308 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 161:aa5281ff4a02 15309 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 161:aa5281ff4a02 15310 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 161:aa5281ff4a02 15311 || \
AnnaBridge 161:aa5281ff4a02 15312 (((INSTANCE) == TIM8) && \
AnnaBridge 161:aa5281ff4a02 15313 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15314 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 161:aa5281ff4a02 15315 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 161:aa5281ff4a02 15316 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 161:aa5281ff4a02 15317 || \
AnnaBridge 161:aa5281ff4a02 15318 (((INSTANCE) == TIM9) && \
AnnaBridge 161:aa5281ff4a02 15319 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15320 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 161:aa5281ff4a02 15321 || \
AnnaBridge 161:aa5281ff4a02 15322 (((INSTANCE) == TIM10) && \
AnnaBridge 161:aa5281ff4a02 15323 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 161:aa5281ff4a02 15324 || \
AnnaBridge 161:aa5281ff4a02 15325 (((INSTANCE) == TIM11) && \
AnnaBridge 161:aa5281ff4a02 15326 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 161:aa5281ff4a02 15327 || \
AnnaBridge 161:aa5281ff4a02 15328 (((INSTANCE) == TIM12) && \
AnnaBridge 161:aa5281ff4a02 15329 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15330 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 161:aa5281ff4a02 15331 || \
AnnaBridge 161:aa5281ff4a02 15332 (((INSTANCE) == TIM13) && \
AnnaBridge 161:aa5281ff4a02 15333 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 161:aa5281ff4a02 15334 || \
AnnaBridge 161:aa5281ff4a02 15335 (((INSTANCE) == TIM14) && \
AnnaBridge 161:aa5281ff4a02 15336 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 161:aa5281ff4a02 15337
AnnaBridge 161:aa5281ff4a02 15338 /************ TIM Instances : complementary output(s) available ***************/
AnnaBridge 161:aa5281ff4a02 15339 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 161:aa5281ff4a02 15340 ((((INSTANCE) == TIM1) && \
AnnaBridge 161:aa5281ff4a02 15341 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15342 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 161:aa5281ff4a02 15343 ((CHANNEL) == TIM_CHANNEL_3))) \
AnnaBridge 161:aa5281ff4a02 15344 || \
AnnaBridge 161:aa5281ff4a02 15345 (((INSTANCE) == TIM8) && \
AnnaBridge 161:aa5281ff4a02 15346 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 161:aa5281ff4a02 15347 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 161:aa5281ff4a02 15348 ((CHANNEL) == TIM_CHANNEL_3))))
AnnaBridge 161:aa5281ff4a02 15349
AnnaBridge 161:aa5281ff4a02 15350 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 161:aa5281ff4a02 15351 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15352 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15353 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15354 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15355 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15356 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15357
AnnaBridge 161:aa5281ff4a02 15358 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 161:aa5281ff4a02 15359 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15360 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15361 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15362 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15363 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15364 ((INSTANCE) == TIM8) || \
AnnaBridge 161:aa5281ff4a02 15365 ((INSTANCE) == TIM9) || \
AnnaBridge 161:aa5281ff4a02 15366 ((INSTANCE) == TIM10)|| \
AnnaBridge 161:aa5281ff4a02 15367 ((INSTANCE) == TIM11)|| \
AnnaBridge 161:aa5281ff4a02 15368 ((INSTANCE) == TIM12)|| \
AnnaBridge 161:aa5281ff4a02 15369 ((INSTANCE) == TIM13)|| \
AnnaBridge 161:aa5281ff4a02 15370 ((INSTANCE) == TIM14))
AnnaBridge 161:aa5281ff4a02 15371
AnnaBridge 161:aa5281ff4a02 15372 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 161:aa5281ff4a02 15373 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
AnnaBridge 161:aa5281ff4a02 15374 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15375
AnnaBridge 161:aa5281ff4a02 15376
AnnaBridge 161:aa5281ff4a02 15377 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 161:aa5281ff4a02 15378 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15379 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15380 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15381 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15382 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15383 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15384
AnnaBridge 161:aa5281ff4a02 15385 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 161:aa5281ff4a02 15386 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15387 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15388 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15389 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15390 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15391 ((INSTANCE) == TIM8) || \
AnnaBridge 161:aa5281ff4a02 15392 ((INSTANCE) == TIM9) || \
AnnaBridge 161:aa5281ff4a02 15393 ((INSTANCE) == TIM12))
AnnaBridge 161:aa5281ff4a02 15394
AnnaBridge 161:aa5281ff4a02 15395 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 161:aa5281ff4a02 15396 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15397 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15398 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15399 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15400 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15401 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15402
AnnaBridge 161:aa5281ff4a02 15403 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 161:aa5281ff4a02 15404 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15405 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15406
AnnaBridge 161:aa5281ff4a02 15407 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 161:aa5281ff4a02 15408 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15409 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15410 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15411 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15412 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15413 ((INSTANCE) == TIM8) || \
AnnaBridge 161:aa5281ff4a02 15414 ((INSTANCE) == TIM9) || \
AnnaBridge 161:aa5281ff4a02 15415 ((INSTANCE) == TIM12))
AnnaBridge 161:aa5281ff4a02 15416 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 161:aa5281ff4a02 15417 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15418 ((INSTANCE) == TIM2) || \
AnnaBridge 161:aa5281ff4a02 15419 ((INSTANCE) == TIM3) || \
AnnaBridge 161:aa5281ff4a02 15420 ((INSTANCE) == TIM4) || \
AnnaBridge 161:aa5281ff4a02 15421 ((INSTANCE) == TIM5) || \
AnnaBridge 161:aa5281ff4a02 15422 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15423 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 161:aa5281ff4a02 15424 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 161:aa5281ff4a02 15425 ((INSTANCE) == TIM8))
AnnaBridge 161:aa5281ff4a02 15426
AnnaBridge 161:aa5281ff4a02 15427 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 161:aa5281ff4a02 15428 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 161:aa5281ff4a02 15429 ((INSTANCE) == USART2) || \
AnnaBridge 161:aa5281ff4a02 15430 ((INSTANCE) == USART3) || \
AnnaBridge 161:aa5281ff4a02 15431 ((INSTANCE) == USART6))
AnnaBridge 161:aa5281ff4a02 15432
AnnaBridge 161:aa5281ff4a02 15433 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 161:aa5281ff4a02 15434 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 161:aa5281ff4a02 15435 ((INSTANCE) == USART2) || \
AnnaBridge 161:aa5281ff4a02 15436 ((INSTANCE) == USART3) || \
AnnaBridge 161:aa5281ff4a02 15437 ((INSTANCE) == UART4) || \
AnnaBridge 161:aa5281ff4a02 15438 ((INSTANCE) == UART5) || \
AnnaBridge 161:aa5281ff4a02 15439 ((INSTANCE) == USART6))
AnnaBridge 161:aa5281ff4a02 15440
AnnaBridge 161:aa5281ff4a02 15441 /* Legacy defines */
AnnaBridge 161:aa5281ff4a02 15442 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 161:aa5281ff4a02 15443
AnnaBridge 161:aa5281ff4a02 15444 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 161:aa5281ff4a02 15445 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 161:aa5281ff4a02 15446 ((INSTANCE) == USART2) || \
AnnaBridge 161:aa5281ff4a02 15447 ((INSTANCE) == USART3) || \
AnnaBridge 161:aa5281ff4a02 15448 ((INSTANCE) == USART6))
AnnaBridge 161:aa5281ff4a02 15449 /******************** UART Instances : LIN mode **********************/
AnnaBridge 161:aa5281ff4a02 15450 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 161:aa5281ff4a02 15451
AnnaBridge 161:aa5281ff4a02 15452 /********************* UART Instances : Smart card mode ***********************/
AnnaBridge 161:aa5281ff4a02 15453 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 161:aa5281ff4a02 15454 ((INSTANCE) == USART2) || \
AnnaBridge 161:aa5281ff4a02 15455 ((INSTANCE) == USART3) || \
AnnaBridge 161:aa5281ff4a02 15456 ((INSTANCE) == USART6))
AnnaBridge 161:aa5281ff4a02 15457
AnnaBridge 161:aa5281ff4a02 15458 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 161:aa5281ff4a02 15459 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 161:aa5281ff4a02 15460 ((INSTANCE) == USART2) || \
AnnaBridge 161:aa5281ff4a02 15461 ((INSTANCE) == USART3) || \
AnnaBridge 161:aa5281ff4a02 15462 ((INSTANCE) == UART4) || \
AnnaBridge 161:aa5281ff4a02 15463 ((INSTANCE) == UART5) || \
AnnaBridge 161:aa5281ff4a02 15464 ((INSTANCE) == USART6))
AnnaBridge 161:aa5281ff4a02 15465
AnnaBridge 161:aa5281ff4a02 15466
AnnaBridge 161:aa5281ff4a02 15467 /*********************** PCD Instances ****************************************/
AnnaBridge 161:aa5281ff4a02 15468 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
AnnaBridge 161:aa5281ff4a02 15469 ((INSTANCE) == USB_OTG_HS))
AnnaBridge 161:aa5281ff4a02 15470
AnnaBridge 161:aa5281ff4a02 15471 /*********************** HCD Instances ****************************************/
AnnaBridge 161:aa5281ff4a02 15472 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
AnnaBridge 161:aa5281ff4a02 15473 ((INSTANCE) == USB_OTG_HS))
AnnaBridge 161:aa5281ff4a02 15474
AnnaBridge 161:aa5281ff4a02 15475 /****************************** SDIO Instances ********************************/
AnnaBridge 161:aa5281ff4a02 15476 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
AnnaBridge 161:aa5281ff4a02 15477
AnnaBridge 161:aa5281ff4a02 15478 /****************************** IWDG Instances ********************************/
AnnaBridge 161:aa5281ff4a02 15479 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 161:aa5281ff4a02 15480
AnnaBridge 161:aa5281ff4a02 15481 /****************************** WWDG Instances ********************************/
AnnaBridge 161:aa5281ff4a02 15482 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 161:aa5281ff4a02 15483
AnnaBridge 161:aa5281ff4a02 15484 /****************************** USB Exported Constants ************************/
AnnaBridge 161:aa5281ff4a02 15485 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
AnnaBridge 161:aa5281ff4a02 15486 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
AnnaBridge 161:aa5281ff4a02 15487 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
AnnaBridge 161:aa5281ff4a02 15488 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
AnnaBridge 161:aa5281ff4a02 15489
AnnaBridge 161:aa5281ff4a02 15490 /*
AnnaBridge 161:aa5281ff4a02 15491 * @brief Specific devices reset values definitions
AnnaBridge 161:aa5281ff4a02 15492 */
AnnaBridge 161:aa5281ff4a02 15493 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
AnnaBridge 161:aa5281ff4a02 15494 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
AnnaBridge 161:aa5281ff4a02 15495
AnnaBridge 161:aa5281ff4a02 15496 #define RCC_MAX_FREQUENCY 168000000U /*!< Max frequency of family in Hz*/
AnnaBridge 161:aa5281ff4a02 15497 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
AnnaBridge 161:aa5281ff4a02 15498 #define RCC_MAX_FREQUENCY_SCALE2 144000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
AnnaBridge 161:aa5281ff4a02 15499 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
AnnaBridge 161:aa5281ff4a02 15500 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
AnnaBridge 161:aa5281ff4a02 15501 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
AnnaBridge 161:aa5281ff4a02 15502 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
AnnaBridge 161:aa5281ff4a02 15503
AnnaBridge 161:aa5281ff4a02 15504 #define RCC_PLLN_MIN_VALUE 50U
AnnaBridge 161:aa5281ff4a02 15505 #define RCC_PLLN_MAX_VALUE 432U
AnnaBridge 161:aa5281ff4a02 15506
AnnaBridge 161:aa5281ff4a02 15507 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
AnnaBridge 161:aa5281ff4a02 15508 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
AnnaBridge 161:aa5281ff4a02 15509 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
AnnaBridge 161:aa5281ff4a02 15510 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
AnnaBridge 161:aa5281ff4a02 15511 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
AnnaBridge 161:aa5281ff4a02 15512
AnnaBridge 161:aa5281ff4a02 15513 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
AnnaBridge 161:aa5281ff4a02 15514 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
AnnaBridge 161:aa5281ff4a02 15515 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
AnnaBridge 161:aa5281ff4a02 15516 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
AnnaBridge 161:aa5281ff4a02 15517
AnnaBridge 161:aa5281ff4a02 15518 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
AnnaBridge 161:aa5281ff4a02 15519 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
AnnaBridge 161:aa5281ff4a02 15520 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
AnnaBridge 161:aa5281ff4a02 15521 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
AnnaBridge 161:aa5281ff4a02 15522 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 15523 /* For a painless codes migration between the STM32F4xx device product */
AnnaBridge 161:aa5281ff4a02 15524 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 161:aa5281ff4a02 15525 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 161:aa5281ff4a02 15526 /* No need to update developed interrupt code when moving across */
AnnaBridge 161:aa5281ff4a02 15527 /* product lines within the same STM32F4 Family */
AnnaBridge 161:aa5281ff4a02 15528 /******************************************************************************/
AnnaBridge 161:aa5281ff4a02 15529 /* Aliases for __IRQn */
AnnaBridge 161:aa5281ff4a02 15530 #define FMC_IRQn FSMC_IRQn
AnnaBridge 161:aa5281ff4a02 15531
AnnaBridge 161:aa5281ff4a02 15532 /* Aliases for __IRQHandler */
AnnaBridge 161:aa5281ff4a02 15533 #define FMC_IRQHandler FSMC_IRQHandler
AnnaBridge 161:aa5281ff4a02 15534
AnnaBridge 161:aa5281ff4a02 15535 /**
AnnaBridge 161:aa5281ff4a02 15536 * @}
AnnaBridge 161:aa5281ff4a02 15537 */
AnnaBridge 161:aa5281ff4a02 15538
AnnaBridge 161:aa5281ff4a02 15539 /**
AnnaBridge 161:aa5281ff4a02 15540 * @}
AnnaBridge 161:aa5281ff4a02 15541 */
AnnaBridge 161:aa5281ff4a02 15542
AnnaBridge 161:aa5281ff4a02 15543 /**
AnnaBridge 161:aa5281ff4a02 15544 * @}
AnnaBridge 161:aa5281ff4a02 15545 */
AnnaBridge 161:aa5281ff4a02 15546
AnnaBridge 161:aa5281ff4a02 15547 #ifdef __cplusplus
AnnaBridge 161:aa5281ff4a02 15548 }
AnnaBridge 161:aa5281ff4a02 15549 #endif /* __cplusplus */
AnnaBridge 161:aa5281ff4a02 15550
AnnaBridge 161:aa5281ff4a02 15551 #endif /* __STM32F407xx_H */
AnnaBridge 161:aa5281ff4a02 15552
AnnaBridge 161:aa5281ff4a02 15553
AnnaBridge 161:aa5281ff4a02 15554
AnnaBridge 161:aa5281ff4a02 15555 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/