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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Parent:: 128:9bcdf88f62b0

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_ll_system.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.7.1
AnnaBridge	145:64910690c574	6	* @date 21-April-2017
Kojto	122:f9eeca106725	7	* @brief Header file of SYSTEM LL module.
Kojto	122:f9eeca106725	8	@verbatim
Kojto	122:f9eeca106725	9	==============================================================================
Kojto	122:f9eeca106725	10	##### How to use this driver #####
Kojto	122:f9eeca106725	11	==============================================================================
Kojto	122:f9eeca106725	12	[..]
Kojto	122:f9eeca106725	13	The LL SYSTEM driver contains a set of generic APIs that can be
Kojto	122:f9eeca106725	14	used by user:
Kojto	122:f9eeca106725	15	(+) Some of the FLASH features need to be handled in the SYSTEM file.
Kojto	122:f9eeca106725	16	(+) Access to DBGCMU registers
Kojto	122:f9eeca106725	17	(+) Access to SYSCFG registers
Kojto	122:f9eeca106725	18	(+) Access to VREFBUF registers
Kojto	122:f9eeca106725	19
Kojto	122:f9eeca106725	20	@endverbatim
Kojto	122:f9eeca106725	21	******************************************************************************
Kojto	122:f9eeca106725	22	* @attention
Kojto	122:f9eeca106725	23	*
AnnaBridge	145:64910690c574	24	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	25	*
Kojto	122:f9eeca106725	26	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	27	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	28	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	29	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	30	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	31	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	32	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	33	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	34	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	35	* without specific prior written permission.
Kojto	122:f9eeca106725	36	*
Kojto	122:f9eeca106725	37	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	38	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	39	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	40	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	41	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	42	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	43	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	44	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	45	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	46	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	47	*
Kojto	122:f9eeca106725	48	******************************************************************************
Kojto	122:f9eeca106725	49	*/
Kojto	122:f9eeca106725	50
Kojto	122:f9eeca106725	51	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	52	#ifndef __STM32L4xx_LL_SYSTEM_H
Kojto	122:f9eeca106725	53	#define __STM32L4xx_LL_SYSTEM_H
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	#ifdef __cplusplus
Kojto	122:f9eeca106725	56	extern "C" {
Kojto	122:f9eeca106725	57	#endif
Kojto	122:f9eeca106725	58
Kojto	122:f9eeca106725	59	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	60	#include "stm32l4xx.h"
Kojto	122:f9eeca106725	61
Kojto	122:f9eeca106725	62	/** @addtogroup STM32L4xx_LL_Driver
Kojto	122:f9eeca106725	63	* @{
Kojto	122:f9eeca106725	64	*/
Kojto	122:f9eeca106725	65
Kojto	122:f9eeca106725	66	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined (VREFBUF)
Kojto	122:f9eeca106725	67
Kojto	122:f9eeca106725	68	/** @defgroup SYSTEM_LL SYSTEM
Kojto	122:f9eeca106725	69	* @{
Kojto	122:f9eeca106725	70	*/
Kojto	122:f9eeca106725	71
Kojto	122:f9eeca106725	72	/* Private types -------------------------------------------------------------*/
Kojto	122:f9eeca106725	73	/* Private variables ---------------------------------------------------------*/
Kojto	122:f9eeca106725	74
Kojto	122:f9eeca106725	75	/* Private constants ---------------------------------------------------------*/
Kojto	122:f9eeca106725	76	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
Kojto	122:f9eeca106725	77	* @{
Kojto	122:f9eeca106725	78	*/
Kojto	122:f9eeca106725	79
Kojto	122:f9eeca106725	80	/* Defines used for position in the register */
Kojto	122:f9eeca106725	81	#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
Kojto	122:f9eeca106725	82
Kojto	122:f9eeca106725	83	/**
Kojto	122:f9eeca106725	84	* @brief Power-down in Run mode Flash key
Kojto	122:f9eeca106725	85	*/
Kojto	122:f9eeca106725	86	#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /!< Flash power down key1 /
Kojto	122:f9eeca106725	87	#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
Kojto	122:f9eeca106725	88	to unlock the RUN_PD bit in FLASH_ACR */
Kojto	122:f9eeca106725	89
Kojto	122:f9eeca106725	90	/**
Kojto	122:f9eeca106725	91	* @}
Kojto	122:f9eeca106725	92	*/
Kojto	122:f9eeca106725	93
Kojto	122:f9eeca106725	94	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	95
Kojto	122:f9eeca106725	96	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	97	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	98	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
Kojto	122:f9eeca106725	99	* @{
Kojto	122:f9eeca106725	100	*/
Kojto	122:f9eeca106725	101
Kojto	122:f9eeca106725	102	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
Kojto	122:f9eeca106725	103	* @{
Kojto	122:f9eeca106725	104	*/
AnnaBridge	145:64910690c574	105	#define LL_SYSCFG_REMAP_FLASH 0x00000000U /!< Main Flash memory mapped at 0x00000000 /
Kojto	122:f9eeca106725	106	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
Kojto	122:f9eeca106725	107	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /!< SRAM1 mapped at 0x00000000 /
Kojto	122:f9eeca106725	108	#if defined(FMC_Bank1_R)
Kojto	122:f9eeca106725	109	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 /
Kojto	122:f9eeca106725	110	#endif /* FMC_Bank1_R */
Kojto	122:f9eeca106725	111	#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 \| SYSCFG_MEMRMP_MEM_MODE_1) /!< QUADSPI memory mapped at 0x00000000 /
Kojto	122:f9eeca106725	112	/**
Kojto	122:f9eeca106725	113	* @}
Kojto	122:f9eeca106725	114	*/
Kojto	122:f9eeca106725	115
Kojto	122:f9eeca106725	116	#if defined(SYSCFG_MEMRMP_FB_MODE)
Kojto	122:f9eeca106725	117	/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
Kojto	122:f9eeca106725	118	* @{
Kojto	122:f9eeca106725	119	*/
AnnaBridge	145:64910690c574	120	#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
Kojto	122:f9eeca106725	121	and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
Kojto	122:f9eeca106725	122	#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
Kojto	122:f9eeca106725	123	and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
Kojto	122:f9eeca106725	124	/**
Kojto	122:f9eeca106725	125	* @}
Kojto	122:f9eeca106725	126	*/
Kojto	122:f9eeca106725	127
Kojto	122:f9eeca106725	128	#endif /* SYSCFG_MEMRMP_FB_MODE */
Kojto	122:f9eeca106725	129	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
Kojto	122:f9eeca106725	130	* @{
Kojto	122:f9eeca106725	131	*/
Kojto	122:f9eeca106725	132	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /!< Enable Fast Mode Plus on PB6 /
Kojto	122:f9eeca106725	133	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /!< Enable Fast Mode Plus on PB7 /
Kojto	122:f9eeca106725	134	#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
Kojto	122:f9eeca106725	135	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /!< Enable Fast Mode Plus on PB8 /
Kojto	122:f9eeca106725	136	#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
Kojto	122:f9eeca106725	137	#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
Kojto	122:f9eeca106725	138	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /!< Enable Fast Mode Plus on PB9 /
Kojto	122:f9eeca106725	139	#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
Kojto	122:f9eeca106725	140	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /!< Enable Fast Mode Plus on I2C1 pins /
Kojto	122:f9eeca106725	141	#if defined(I2C2)
Kojto	122:f9eeca106725	142	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /!< Enable Fast Mode Plus on I2C2 pins /
Kojto	122:f9eeca106725	143	#endif /* I2C2 */
Kojto	122:f9eeca106725	144	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /!< Enable Fast Mode Plus on I2C3 pins /
AnnaBridge	145:64910690c574	145	#if defined(I2C4)
AnnaBridge	145:64910690c574	146	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /!< Enable Fast Mode Plus on I2C4 pins /
AnnaBridge	145:64910690c574	147	#endif /* I2C4 */
Kojto	122:f9eeca106725	148	/**
Kojto	122:f9eeca106725	149	* @}
Kojto	122:f9eeca106725	150	*/
Kojto	122:f9eeca106725	151
Kojto	122:f9eeca106725	152	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
Kojto	122:f9eeca106725	153	* @{
Kojto	122:f9eeca106725	154	*/
AnnaBridge	145:64910690c574	155	#define LL_SYSCFG_EXTI_PORTA 0U /!< EXTI PORT A /
AnnaBridge	145:64910690c574	156	#define LL_SYSCFG_EXTI_PORTB 1U /!< EXTI PORT B /
AnnaBridge	145:64910690c574	157	#define LL_SYSCFG_EXTI_PORTC 2U /!< EXTI PORT C /
AnnaBridge	145:64910690c574	158	#define LL_SYSCFG_EXTI_PORTD 3U /!< EXTI PORT D /
AnnaBridge	145:64910690c574	159	#define LL_SYSCFG_EXTI_PORTE 4U /!< EXTI PORT E /
Kojto	122:f9eeca106725	160	#if defined(GPIOF)
AnnaBridge	145:64910690c574	161	#define LL_SYSCFG_EXTI_PORTF 5U /!< EXTI PORT F /
Kojto	122:f9eeca106725	162	#endif /* GPIOF */
Kojto	122:f9eeca106725	163	#if defined(GPIOG)
AnnaBridge	145:64910690c574	164	#define LL_SYSCFG_EXTI_PORTG 6U /!< EXTI PORT G /
Kojto	122:f9eeca106725	165	#endif /* GPIOG */
AnnaBridge	145:64910690c574	166	#define LL_SYSCFG_EXTI_PORTH 7U /!< EXTI PORT H /
AnnaBridge	145:64910690c574	167	#if defined(GPIOI)
AnnaBridge	145:64910690c574	168	#define LL_SYSCFG_EXTI_PORTI 8U /!< EXTI PORT I /
AnnaBridge	145:64910690c574	169	#endif /* GPIOI */
Kojto	122:f9eeca106725	170	/**
Kojto	122:f9eeca106725	171	* @}
Kojto	122:f9eeca106725	172	*/
Kojto	122:f9eeca106725	173
Kojto	122:f9eeca106725	174	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
Kojto	122:f9eeca106725	175	* @{
Kojto	122:f9eeca106725	176	*/
AnnaBridge	145:64910690c574	177	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U \| 0U) /* !< EXTI_POSITION_0 \| EXTICR[0] */
AnnaBridge	145:64910690c574	178	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U \| 0U) /* !< EXTI_POSITION_4 \| EXTICR[0] */
AnnaBridge	145:64910690c574	179	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U \| 0U) /* !< EXTI_POSITION_8 \| EXTICR[0] */
AnnaBridge	145:64910690c574	180	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U \| 0U) /* !< EXTI_POSITION_12 \| EXTICR[0] */
AnnaBridge	145:64910690c574	181	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U \| 1U) /* !< EXTI_POSITION_0 \| EXTICR[1] */
AnnaBridge	145:64910690c574	182	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U \| 1U) /* !< EXTI_POSITION_4 \| EXTICR[1] */
AnnaBridge	145:64910690c574	183	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U \| 1U) /* !< EXTI_POSITION_8 \| EXTICR[1] */
AnnaBridge	145:64910690c574	184	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U \| 1U) /* !< EXTI_POSITION_12 \| EXTICR[1] */
AnnaBridge	145:64910690c574	185	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U \| 2U) /* !< EXTI_POSITION_0 \| EXTICR[2] */
AnnaBridge	145:64910690c574	186	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U \| 2U) /* !< EXTI_POSITION_4 \| EXTICR[2] */
AnnaBridge	145:64910690c574	187	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U \| 2U) /* !< EXTI_POSITION_8 \| EXTICR[2] */
AnnaBridge	145:64910690c574	188	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U \| 2U) /* !< EXTI_POSITION_12 \| EXTICR[2] */
AnnaBridge	145:64910690c574	189	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U \| 3U) /* !< EXTI_POSITION_0 \| EXTICR[3] */
AnnaBridge	145:64910690c574	190	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U \| 3U) /* !< EXTI_POSITION_4 \| EXTICR[3] */
AnnaBridge	145:64910690c574	191	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U \| 3U) /* !< EXTI_POSITION_8 \| EXTICR[3] */
AnnaBridge	145:64910690c574	192	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U \| 3U) /* !< EXTI_POSITION_12 \| EXTICR[3] */
Kojto	122:f9eeca106725	193	/**
Kojto	122:f9eeca106725	194	* @}
Kojto	122:f9eeca106725	195	*/
Kojto	122:f9eeca106725	196
Kojto	122:f9eeca106725	197	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
Kojto	122:f9eeca106725	198	* @{
Kojto	122:f9eeca106725	199	*/
Kojto	122:f9eeca106725	200	#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
Kojto	122:f9eeca106725	201	with Break Input of TIM1/8/15/16/17 */
Kojto	122:f9eeca106725	202	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
Kojto	122:f9eeca106725	203	with TIM1/8/15/16/17 Break Input
Kojto	122:f9eeca106725	204	and also the PVDE and PLS bits of the Power Control Interface */
Kojto	122:f9eeca106725	205	#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
Kojto	122:f9eeca106725	206	with Break Input of TIM1/8/15/16/17 */
Kojto	122:f9eeca106725	207	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
Kojto	122:f9eeca106725	208	with Break Input of TIM1/15/16/17 */
Kojto	122:f9eeca106725	209	/**
Kojto	122:f9eeca106725	210	* @}
Kojto	122:f9eeca106725	211	*/
Kojto	122:f9eeca106725	212
Kojto	122:f9eeca106725	213	/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
Kojto	122:f9eeca106725	214	* @{
Kojto	122:f9eeca106725	215	*/
Kojto	122:f9eeca106725	216	#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /!< SRAM2 Write protection page 0 /
Kojto	122:f9eeca106725	217	#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /!< SRAM2 Write protection page 1 /
Kojto	122:f9eeca106725	218	#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /!< SRAM2 Write protection page 2 /
Kojto	122:f9eeca106725	219	#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /!< SRAM2 Write protection page 3 /
Kojto	122:f9eeca106725	220	#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /!< SRAM2 Write protection page 4 /
Kojto	122:f9eeca106725	221	#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /!< SRAM2 Write protection page 5 /
Kojto	122:f9eeca106725	222	#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /!< SRAM2 Write protection page 6 /
Kojto	122:f9eeca106725	223	#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /!< SRAM2 Write protection page 7 /
Kojto	122:f9eeca106725	224	#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /!< SRAM2 Write protection page 8 /
Kojto	122:f9eeca106725	225	#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /!< SRAM2 Write protection page 9 /
Kojto	122:f9eeca106725	226	#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /!< SRAM2 Write protection page 10 /
Kojto	122:f9eeca106725	227	#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /!< SRAM2 Write protection page 11 /
Kojto	122:f9eeca106725	228	#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /!< SRAM2 Write protection page 12 /
Kojto	122:f9eeca106725	229	#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /!< SRAM2 Write protection page 13 /
Kojto	122:f9eeca106725	230	#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /!< SRAM2 Write protection page 14 /
Kojto	122:f9eeca106725	231	#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /!< SRAM2 Write protection page 15 /
AnnaBridge	145:64910690c574	232	#if defined(SYSCFG_SWPR_PAGE31)
Kojto	122:f9eeca106725	233	#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /!< SRAM2 Write protection page 16 /
Kojto	122:f9eeca106725	234	#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /!< SRAM2 Write protection page 17 /
Kojto	122:f9eeca106725	235	#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /!< SRAM2 Write protection page 18 /
Kojto	122:f9eeca106725	236	#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /!< SRAM2 Write protection page 19 /
Kojto	122:f9eeca106725	237	#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /!< SRAM2 Write protection page 20 /
Kojto	122:f9eeca106725	238	#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /!< SRAM2 Write protection page 21 /
Kojto	122:f9eeca106725	239	#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /!< SRAM2 Write protection page 22 /
Kojto	122:f9eeca106725	240	#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /!< SRAM2 Write protection page 23 /
Kojto	122:f9eeca106725	241	#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /!< SRAM2 Write protection page 24 /
Kojto	122:f9eeca106725	242	#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /!< SRAM2 Write protection page 25 /
Kojto	122:f9eeca106725	243	#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /!< SRAM2 Write protection page 26 /
Kojto	122:f9eeca106725	244	#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /!< SRAM2 Write protection page 27 /
Kojto	122:f9eeca106725	245	#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /!< SRAM2 Write protection page 28 /
Kojto	122:f9eeca106725	246	#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /!< SRAM2 Write protection page 29 /
Kojto	122:f9eeca106725	247	#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /!< SRAM2 Write protection page 30 /
Kojto	122:f9eeca106725	248	#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /!< SRAM2 Write protection page 31 /
AnnaBridge	145:64910690c574	249	#endif /* SYSCFG_SWPR_PAGE31 */
AnnaBridge	145:64910690c574	250	#if defined(SYSCFG_SWPR2_PAGE63)
AnnaBridge	145:64910690c574	251	#define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /!< SRAM2 Write protection page 32 /
AnnaBridge	145:64910690c574	252	#define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /!< SRAM2 Write protection page 33 /
AnnaBridge	145:64910690c574	253	#define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /!< SRAM2 Write protection page 34 /
AnnaBridge	145:64910690c574	254	#define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /!< SRAM2 Write protection page 35 /
AnnaBridge	145:64910690c574	255	#define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /!< SRAM2 Write protection page 36 /
AnnaBridge	145:64910690c574	256	#define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /!< SRAM2 Write protection page 37 /
AnnaBridge	145:64910690c574	257	#define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /!< SRAM2 Write protection page 38 /
AnnaBridge	145:64910690c574	258	#define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /!< SRAM2 Write protection page 39 /
AnnaBridge	145:64910690c574	259	#define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /!< SRAM2 Write protection page 40 /
AnnaBridge	145:64910690c574	260	#define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /!< SRAM2 Write protection page 41 /
AnnaBridge	145:64910690c574	261	#define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /!< SRAM2 Write protection page 42 /
AnnaBridge	145:64910690c574	262	#define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /!< SRAM2 Write protection page 43 /
AnnaBridge	145:64910690c574	263	#define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /!< SRAM2 Write protection page 44 /
AnnaBridge	145:64910690c574	264	#define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /!< SRAM2 Write protection page 45 /
AnnaBridge	145:64910690c574	265	#define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /!< SRAM2 Write protection page 46 /
AnnaBridge	145:64910690c574	266	#define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /!< SRAM2 Write protection page 47 /
AnnaBridge	145:64910690c574	267	#define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /!< SRAM2 Write protection page 48 /
AnnaBridge	145:64910690c574	268	#define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /!< SRAM2 Write protection page 49 /
AnnaBridge	145:64910690c574	269	#define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /!< SRAM2 Write protection page 50 /
AnnaBridge	145:64910690c574	270	#define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /!< SRAM2 Write protection page 51 /
AnnaBridge	145:64910690c574	271	#define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /!< SRAM2 Write protection page 52 /
AnnaBridge	145:64910690c574	272	#define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /!< SRAM2 Write protection page 53 /
AnnaBridge	145:64910690c574	273	#define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /!< SRAM2 Write protection page 54 /
AnnaBridge	145:64910690c574	274	#define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /!< SRAM2 Write protection page 55 /
AnnaBridge	145:64910690c574	275	#define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /!< SRAM2 Write protection page 56 /
AnnaBridge	145:64910690c574	276	#define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /!< SRAM2 Write protection page 57 /
AnnaBridge	145:64910690c574	277	#define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /!< SRAM2 Write protection page 58 /
AnnaBridge	145:64910690c574	278	#define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /!< SRAM2 Write protection page 59 /
AnnaBridge	145:64910690c574	279	#define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /!< SRAM2 Write protection page 60 /
AnnaBridge	145:64910690c574	280	#define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /!< SRAM2 Write protection page 61 /
AnnaBridge	145:64910690c574	281	#define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /!< SRAM2 Write protection page 62 /
AnnaBridge	145:64910690c574	282	#define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /!< SRAM2 Write protection page 63 /
AnnaBridge	145:64910690c574	283	#endif /* SYSCFG_SWPR2_PAGE63 */
Kojto	122:f9eeca106725	284	/**
Kojto	122:f9eeca106725	285	* @}
Kojto	122:f9eeca106725	286	*/
Kojto	122:f9eeca106725	287
Kojto	122:f9eeca106725	288	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
Kojto	122:f9eeca106725	289	* @{
Kojto	122:f9eeca106725	290	*/
AnnaBridge	145:64910690c574	291	#define LL_DBGMCU_TRACE_NONE 0x00000000U /!< TRACE pins not assigned (default state) /
Kojto	122:f9eeca106725	292	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
Kojto	122:f9eeca106725	293	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
Kojto	122:f9eeca106725	294	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
Kojto	122:f9eeca106725	295	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
Kojto	122:f9eeca106725	296	/**
Kojto	122:f9eeca106725	297	* @}
Kojto	122:f9eeca106725	298	*/
Kojto	122:f9eeca106725	299
Kojto	122:f9eeca106725	300	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
Kojto	122:f9eeca106725	301	* @{
Kojto	122:f9eeca106725	302	*/
Kojto	122:f9eeca106725	303	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /!< The counter clock of TIM2 is stopped when the core is halted/
Kojto	122:f9eeca106725	304	#if defined(TIM3)
Kojto	122:f9eeca106725	305	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /!< The counter clock of TIM3 is stopped when the core is halted/
Kojto	122:f9eeca106725	306	#endif /* TIM3 */
Kojto	122:f9eeca106725	307	#if defined(TIM4)
Kojto	122:f9eeca106725	308	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /!< The counter clock of TIM4 is stopped when the core is halted/
Kojto	122:f9eeca106725	309	#endif /* TIM4 */
Kojto	122:f9eeca106725	310	#if defined(TIM5)
Kojto	122:f9eeca106725	311	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /!< The counter clock of TIM5 is stopped when the core is halted/
Kojto	122:f9eeca106725	312	#endif /* TIM5 */
Kojto	122:f9eeca106725	313	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /!< The counter clock of TIM6 is stopped when the core is halted/
Kojto	122:f9eeca106725	314	#if defined(TIM7)
Kojto	122:f9eeca106725	315	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /!< The counter clock of TIM7 is stopped when the core is halted/
Kojto	122:f9eeca106725	316	#endif /* TIM7 */
Kojto	122:f9eeca106725	317	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /!< The clock of the RTC counter is stopped when the core is halted/
Kojto	122:f9eeca106725	318	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /!< The window watchdog counter clock is stopped when the core is halted/
Kojto	122:f9eeca106725	319	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /!< The independent watchdog counter clock is stopped when the core is halted/
Kojto	122:f9eeca106725	320	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /!< The I2C1 SMBus timeout is frozen/
Kojto	122:f9eeca106725	321	#if defined(I2C2)
Kojto	122:f9eeca106725	322	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /!< The I2C2 SMBus timeout is frozen/
Kojto	122:f9eeca106725	323	#endif /* I2C2 */
Kojto	122:f9eeca106725	324	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /!< The I2C3 SMBus timeout is frozen/
Kojto	122:f9eeca106725	325	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /!< The bxCAN receive registers are frozen/
AnnaBridge	145:64910690c574	326	#if defined(CAN2)
AnnaBridge	145:64910690c574	327	#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /!< The bxCAN2 receive registers are frozen/
AnnaBridge	145:64910690c574	328	#endif /* CAN2 */
Kojto	122:f9eeca106725	329	#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /!< The counter clock of LPTIM1 is stopped when the core is halted/
Kojto	122:f9eeca106725	330	/**
Kojto	122:f9eeca106725	331	* @}
Kojto	122:f9eeca106725	332	*/
Kojto	122:f9eeca106725	333
Kojto	122:f9eeca106725	334	/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
Kojto	122:f9eeca106725	335	* @{
Kojto	122:f9eeca106725	336	*/
AnnaBridge	145:64910690c574	337	#if defined(I2C4)
AnnaBridge	145:64910690c574	338	#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /!< The I2C4 SMBus timeout is frozen/
AnnaBridge	145:64910690c574	339	#endif /* I2C4 */
Kojto	122:f9eeca106725	340	#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /!< The counter clock of LPTIM2 is stopped when the core is halted/
Kojto	122:f9eeca106725	341	/**
Kojto	122:f9eeca106725	342	* @}
Kojto	122:f9eeca106725	343	*/
Kojto	122:f9eeca106725	344
Kojto	122:f9eeca106725	345	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
Kojto	122:f9eeca106725	346	* @{
Kojto	122:f9eeca106725	347	*/
Kojto	122:f9eeca106725	348	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /!< The counter clock of TIM1 is stopped when the core is halted/
Kojto	122:f9eeca106725	349	#if defined(TIM8)
Kojto	122:f9eeca106725	350	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /!< The counter clock of TIM8 is stopped when the core is halted/
Kojto	122:f9eeca106725	351	#endif /* TIM8 */
Kojto	122:f9eeca106725	352	#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /!< The counter clock of TIM15 is stopped when the core is halted/
Kojto	122:f9eeca106725	353	#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /!< The counter clock of TIM16 is stopped when the core is halted/
Kojto	122:f9eeca106725	354	#if defined(TIM17)
Kojto	122:f9eeca106725	355	#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /!< The counter clock of TIM17 is stopped when the core is halted/
Kojto	122:f9eeca106725	356	#endif /* TIM17 */
Kojto	122:f9eeca106725	357	/**
Kojto	122:f9eeca106725	358	* @}
Kojto	122:f9eeca106725	359	*/
Kojto	122:f9eeca106725	360
Kojto	122:f9eeca106725	361	#if defined(VREFBUF)
Kojto	122:f9eeca106725	362	/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
Kojto	122:f9eeca106725	363	* @{
Kojto	122:f9eeca106725	364	*/
Kojto	122:f9eeca106725	365	#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /!< Voltage reference scale 0 (VREF_OUT1) /
Kojto	122:f9eeca106725	366	#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /!< Voltage reference scale 1 (VREF_OUT2) /
Kojto	122:f9eeca106725	367	/**
Kojto	122:f9eeca106725	368	* @}
Kojto	122:f9eeca106725	369	*/
Kojto	122:f9eeca106725	370	#endif /* VREFBUF */
Kojto	122:f9eeca106725	371
Kojto	122:f9eeca106725	372	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
Kojto	122:f9eeca106725	373	* @{
Kojto	122:f9eeca106725	374	*/
Kojto	122:f9eeca106725	375	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
Kojto	122:f9eeca106725	376	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
Kojto	122:f9eeca106725	377	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
Kojto	122:f9eeca106725	378	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
Kojto	122:f9eeca106725	379	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
Kojto	122:f9eeca106725	380	/**
Kojto	122:f9eeca106725	381	* @}
Kojto	122:f9eeca106725	382	*/
Kojto	122:f9eeca106725	383
Kojto	122:f9eeca106725	384	/**
Kojto	122:f9eeca106725	385	* @}
Kojto	122:f9eeca106725	386	*/
Kojto	122:f9eeca106725	387
Kojto	122:f9eeca106725	388	/* Exported macro ------------------------------------------------------------*/
Kojto	122:f9eeca106725	389
Kojto	122:f9eeca106725	390	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	391	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
Kojto	122:f9eeca106725	392	* @{
Kojto	122:f9eeca106725	393	*/
Kojto	122:f9eeca106725	394
Kojto	122:f9eeca106725	395	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
Kojto	122:f9eeca106725	396	* @{
Kojto	122:f9eeca106725	397	*/
Kojto	122:f9eeca106725	398
Kojto	122:f9eeca106725	399	/**
Kojto	122:f9eeca106725	400	* @brief Set memory mapping at address 0x00000000
Kojto	122:f9eeca106725	401	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
Kojto	122:f9eeca106725	402	* @param Memory This parameter can be one of the following values:
Kojto	122:f9eeca106725	403	* @arg @ref LL_SYSCFG_REMAP_FLASH
Kojto	122:f9eeca106725	404	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
Kojto	122:f9eeca106725	405	* @arg @ref LL_SYSCFG_REMAP_SRAM
Kojto	122:f9eeca106725	406	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
Kojto	122:f9eeca106725	407	* @arg @ref LL_SYSCFG_REMAP_QUADSPI
Kojto	122:f9eeca106725	408	*
Kojto	122:f9eeca106725	409	* (*) value not defined in all devices
Kojto	122:f9eeca106725	410	* @retval None
Kojto	122:f9eeca106725	411	*/
Kojto	122:f9eeca106725	412	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
Kojto	122:f9eeca106725	413	{
Kojto	122:f9eeca106725	414	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
Kojto	122:f9eeca106725	415	}
Kojto	122:f9eeca106725	416
Kojto	122:f9eeca106725	417	/**
Kojto	122:f9eeca106725	418	* @brief Get memory mapping at address 0x00000000
Kojto	122:f9eeca106725	419	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
Kojto	122:f9eeca106725	420	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	421	* @arg @ref LL_SYSCFG_REMAP_FLASH
Kojto	122:f9eeca106725	422	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
Kojto	122:f9eeca106725	423	* @arg @ref LL_SYSCFG_REMAP_SRAM
Kojto	122:f9eeca106725	424	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
Kojto	122:f9eeca106725	425	* @arg @ref LL_SYSCFG_REMAP_QUADSPI
Kojto	122:f9eeca106725	426	*
Kojto	122:f9eeca106725	427	* (*) value not defined in all devices
Kojto	122:f9eeca106725	428	*/
Kojto	122:f9eeca106725	429	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
Kojto	122:f9eeca106725	430	{
Kojto	122:f9eeca106725	431	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
Kojto	122:f9eeca106725	432	}
Kojto	122:f9eeca106725	433
Kojto	122:f9eeca106725	434	#if defined(SYSCFG_MEMRMP_FB_MODE)
Kojto	122:f9eeca106725	435	/**
Kojto	122:f9eeca106725	436	* @brief Select Flash bank mode (Bank flashed at 0x08000000)
Kojto	122:f9eeca106725	437	* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
Kojto	122:f9eeca106725	438	* @param Bank This parameter can be one of the following values:
Kojto	122:f9eeca106725	439	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
Kojto	122:f9eeca106725	440	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
Kojto	122:f9eeca106725	441	* @retval None
Kojto	122:f9eeca106725	442	*/
Kojto	122:f9eeca106725	443	__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
Kojto	122:f9eeca106725	444	{
Kojto	122:f9eeca106725	445	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
Kojto	122:f9eeca106725	446	}
Kojto	122:f9eeca106725	447
Kojto	122:f9eeca106725	448	/**
Kojto	122:f9eeca106725	449	* @brief Get Flash bank mode (Bank flashed at 0x08000000)
Kojto	122:f9eeca106725	450	* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
Kojto	122:f9eeca106725	451	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	452	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
Kojto	122:f9eeca106725	453	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
Kojto	122:f9eeca106725	454	*/
Kojto	122:f9eeca106725	455	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
Kojto	122:f9eeca106725	456	{
Kojto	122:f9eeca106725	457	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
Kojto	122:f9eeca106725	458	}
Kojto	122:f9eeca106725	459	#endif /* SYSCFG_MEMRMP_FB_MODE */
Kojto	122:f9eeca106725	460
Kojto	122:f9eeca106725	461	/**
Kojto	122:f9eeca106725	462	* @brief Firewall protection enabled
Kojto	122:f9eeca106725	463	* @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
Kojto	122:f9eeca106725	464	* @retval None
Kojto	122:f9eeca106725	465	*/
Kojto	122:f9eeca106725	466	__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
Kojto	122:f9eeca106725	467	{
Kojto	122:f9eeca106725	468	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
Kojto	122:f9eeca106725	469	}
Kojto	122:f9eeca106725	470
Kojto	122:f9eeca106725	471	/**
Kojto	122:f9eeca106725	472	* @brief Check if Firewall protection is enabled or not
Kojto	122:f9eeca106725	473	* @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
Kojto	122:f9eeca106725	474	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	475	*/
Kojto	122:f9eeca106725	476	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
Kojto	122:f9eeca106725	477	{
Kojto	122:f9eeca106725	478	return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
Kojto	122:f9eeca106725	479	}
Kojto	122:f9eeca106725	480
Kojto	122:f9eeca106725	481	/**
Kojto	122:f9eeca106725	482	* @brief Enable I/O analog switch voltage booster.
Kojto	122:f9eeca106725	483	* @note When voltage booster is enabled, I/O analog switches are supplied
Kojto	122:f9eeca106725	484	* by a dedicated voltage booster, from VDD power domain. This is
Kojto	122:f9eeca106725	485	* the recommended configuration with low VDDA voltage operation.
Kojto	122:f9eeca106725	486	* @note The I/O analog switch voltage booster is relevant for peripherals
Kojto	122:f9eeca106725	487	* using I/O in analog input: ADC, COMP, OPAMP.
Kojto	122:f9eeca106725	488	* However, COMP and OPAMP inputs have a high impedance and
Kojto	122:f9eeca106725	489	* voltage booster do not impact performance significantly.
Kojto	122:f9eeca106725	490	* Therefore, the voltage booster is mainly intended for
Kojto	122:f9eeca106725	491	* usage with ADC.
Kojto	122:f9eeca106725	492	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
Kojto	122:f9eeca106725	493	* @retval None
Kojto	122:f9eeca106725	494	*/
Kojto	122:f9eeca106725	495	__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
Kojto	122:f9eeca106725	496	{
Kojto	122:f9eeca106725	497	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
Kojto	122:f9eeca106725	498	}
Kojto	122:f9eeca106725	499
Kojto	122:f9eeca106725	500	/**
Kojto	122:f9eeca106725	501	* @brief Disable I/O analog switch voltage booster.
Kojto	122:f9eeca106725	502	* @note When voltage booster is enabled, I/O analog switches are supplied
Kojto	122:f9eeca106725	503	* by a dedicated voltage booster, from VDD power domain. This is
Kojto	122:f9eeca106725	504	* the recommended configuration with low VDDA voltage operation.
Kojto	122:f9eeca106725	505	* @note The I/O analog switch voltage booster is relevant for peripherals
Kojto	122:f9eeca106725	506	* using I/O in analog input: ADC, COMP, OPAMP.
Kojto	122:f9eeca106725	507	* However, COMP and OPAMP inputs have a high impedance and
Kojto	122:f9eeca106725	508	* voltage booster do not impact performance significantly.
Kojto	122:f9eeca106725	509	* Therefore, the voltage booster is mainly intended for
Kojto	122:f9eeca106725	510	* usage with ADC.
Kojto	122:f9eeca106725	511	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
Kojto	122:f9eeca106725	512	* @retval None
Kojto	122:f9eeca106725	513	*/
Kojto	122:f9eeca106725	514	__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
Kojto	122:f9eeca106725	515	{
Kojto	122:f9eeca106725	516	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
Kojto	122:f9eeca106725	517	}
Kojto	122:f9eeca106725	518
Kojto	122:f9eeca106725	519	/**
Kojto	122:f9eeca106725	520	* @brief Enable the I2C fast mode plus driving capability.
Kojto	122:f9eeca106725	521	* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
Kojto	122:f9eeca106725	522	* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
Kojto	122:f9eeca106725	523	* @param ConfigFastModePlus This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	524	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
Kojto	122:f9eeca106725	525	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
Kojto	122:f9eeca106725	526	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
Kojto	122:f9eeca106725	527	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
Kojto	122:f9eeca106725	528	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
Kojto	122:f9eeca106725	529	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
Kojto	122:f9eeca106725	530	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
AnnaBridge	145:64910690c574	531	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
Kojto	122:f9eeca106725	532	*
Kojto	122:f9eeca106725	533	* (*) value not defined in all devices
Kojto	122:f9eeca106725	534	* @retval None
Kojto	122:f9eeca106725	535	*/
Kojto	122:f9eeca106725	536	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
Kojto	122:f9eeca106725	537	{
Kojto	122:f9eeca106725	538	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
Kojto	122:f9eeca106725	539	}
Kojto	122:f9eeca106725	540
Kojto	122:f9eeca106725	541	/**
Kojto	122:f9eeca106725	542	* @brief Disable the I2C fast mode plus driving capability.
Kojto	122:f9eeca106725	543	* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
Kojto	122:f9eeca106725	544	* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
Kojto	122:f9eeca106725	545	* @param ConfigFastModePlus This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	546	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
Kojto	122:f9eeca106725	547	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
Kojto	122:f9eeca106725	548	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
Kojto	122:f9eeca106725	549	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
Kojto	122:f9eeca106725	550	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
Kojto	122:f9eeca106725	551	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
Kojto	122:f9eeca106725	552	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
AnnaBridge	145:64910690c574	553	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
Kojto	122:f9eeca106725	554	*
Kojto	122:f9eeca106725	555	* (*) value not defined in all devices
Kojto	122:f9eeca106725	556	* @retval None
Kojto	122:f9eeca106725	557	*/
Kojto	122:f9eeca106725	558	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
Kojto	122:f9eeca106725	559	{
Kojto	122:f9eeca106725	560	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
Kojto	122:f9eeca106725	561	}
Kojto	122:f9eeca106725	562
Kojto	122:f9eeca106725	563	/**
Kojto	122:f9eeca106725	564	* @brief Enable Floating Point Unit Invalid operation Interrupt
Kojto	122:f9eeca106725	565	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
Kojto	122:f9eeca106725	566	* @retval None
Kojto	122:f9eeca106725	567	*/
Kojto	122:f9eeca106725	568	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
Kojto	122:f9eeca106725	569	{
Kojto	122:f9eeca106725	570	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
Kojto	122:f9eeca106725	571	}
Kojto	122:f9eeca106725	572
Kojto	122:f9eeca106725	573	/**
Kojto	122:f9eeca106725	574	* @brief Enable Floating Point Unit Divide-by-zero Interrupt
Kojto	122:f9eeca106725	575	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
Kojto	122:f9eeca106725	576	* @retval None
Kojto	122:f9eeca106725	577	*/
Kojto	122:f9eeca106725	578	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
Kojto	122:f9eeca106725	579	{
Kojto	122:f9eeca106725	580	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
Kojto	122:f9eeca106725	581	}
Kojto	122:f9eeca106725	582
Kojto	122:f9eeca106725	583	/**
Kojto	122:f9eeca106725	584	* @brief Enable Floating Point Unit Underflow Interrupt
Kojto	122:f9eeca106725	585	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
Kojto	122:f9eeca106725	586	* @retval None
Kojto	122:f9eeca106725	587	*/
Kojto	122:f9eeca106725	588	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
Kojto	122:f9eeca106725	589	{
Kojto	122:f9eeca106725	590	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
Kojto	122:f9eeca106725	591	}
Kojto	122:f9eeca106725	592
Kojto	122:f9eeca106725	593	/**
Kojto	122:f9eeca106725	594	* @brief Enable Floating Point Unit Overflow Interrupt
Kojto	122:f9eeca106725	595	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
Kojto	122:f9eeca106725	596	* @retval None
Kojto	122:f9eeca106725	597	*/
Kojto	122:f9eeca106725	598	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
Kojto	122:f9eeca106725	599	{
Kojto	122:f9eeca106725	600	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
Kojto	122:f9eeca106725	601	}
Kojto	122:f9eeca106725	602
Kojto	122:f9eeca106725	603	/**
Kojto	122:f9eeca106725	604	* @brief Enable Floating Point Unit Input denormal Interrupt
Kojto	122:f9eeca106725	605	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
Kojto	122:f9eeca106725	606	* @retval None
Kojto	122:f9eeca106725	607	*/
Kojto	122:f9eeca106725	608	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
Kojto	122:f9eeca106725	609	{
Kojto	122:f9eeca106725	610	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
Kojto	122:f9eeca106725	611	}
Kojto	122:f9eeca106725	612
Kojto	122:f9eeca106725	613	/**
Kojto	122:f9eeca106725	614	* @brief Enable Floating Point Unit Inexact Interrupt
Kojto	122:f9eeca106725	615	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
Kojto	122:f9eeca106725	616	* @retval None
Kojto	122:f9eeca106725	617	*/
Kojto	122:f9eeca106725	618	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
Kojto	122:f9eeca106725	619	{
Kojto	122:f9eeca106725	620	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
Kojto	122:f9eeca106725	621	}
Kojto	122:f9eeca106725	622
Kojto	122:f9eeca106725	623	/**
Kojto	122:f9eeca106725	624	* @brief Disable Floating Point Unit Invalid operation Interrupt
Kojto	122:f9eeca106725	625	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
Kojto	122:f9eeca106725	626	* @retval None
Kojto	122:f9eeca106725	627	*/
Kojto	122:f9eeca106725	628	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
Kojto	122:f9eeca106725	629	{
Kojto	122:f9eeca106725	630	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
Kojto	122:f9eeca106725	631	}
Kojto	122:f9eeca106725	632
Kojto	122:f9eeca106725	633	/**
Kojto	122:f9eeca106725	634	* @brief Disable Floating Point Unit Divide-by-zero Interrupt
Kojto	122:f9eeca106725	635	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
Kojto	122:f9eeca106725	636	* @retval None
Kojto	122:f9eeca106725	637	*/
Kojto	122:f9eeca106725	638	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
Kojto	122:f9eeca106725	639	{
Kojto	122:f9eeca106725	640	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
Kojto	122:f9eeca106725	641	}
Kojto	122:f9eeca106725	642
Kojto	122:f9eeca106725	643	/**
Kojto	122:f9eeca106725	644	* @brief Disable Floating Point Unit Underflow Interrupt
Kojto	122:f9eeca106725	645	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
Kojto	122:f9eeca106725	646	* @retval None
Kojto	122:f9eeca106725	647	*/
Kojto	122:f9eeca106725	648	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
Kojto	122:f9eeca106725	649	{
Kojto	122:f9eeca106725	650	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
Kojto	122:f9eeca106725	651	}
Kojto	122:f9eeca106725	652
Kojto	122:f9eeca106725	653	/**
Kojto	122:f9eeca106725	654	* @brief Disable Floating Point Unit Overflow Interrupt
Kojto	122:f9eeca106725	655	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
Kojto	122:f9eeca106725	656	* @retval None
Kojto	122:f9eeca106725	657	*/
Kojto	122:f9eeca106725	658	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
Kojto	122:f9eeca106725	659	{
Kojto	122:f9eeca106725	660	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
Kojto	122:f9eeca106725	661	}
Kojto	122:f9eeca106725	662
Kojto	122:f9eeca106725	663	/**
Kojto	122:f9eeca106725	664	* @brief Disable Floating Point Unit Input denormal Interrupt
Kojto	122:f9eeca106725	665	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
Kojto	122:f9eeca106725	666	* @retval None
Kojto	122:f9eeca106725	667	*/
Kojto	122:f9eeca106725	668	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
Kojto	122:f9eeca106725	669	{
Kojto	122:f9eeca106725	670	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
Kojto	122:f9eeca106725	671	}
Kojto	122:f9eeca106725	672
Kojto	122:f9eeca106725	673	/**
Kojto	122:f9eeca106725	674	* @brief Disable Floating Point Unit Inexact Interrupt
Kojto	122:f9eeca106725	675	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
Kojto	122:f9eeca106725	676	* @retval None
Kojto	122:f9eeca106725	677	*/
Kojto	122:f9eeca106725	678	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
Kojto	122:f9eeca106725	679	{
Kojto	122:f9eeca106725	680	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
Kojto	122:f9eeca106725	681	}
Kojto	122:f9eeca106725	682
Kojto	122:f9eeca106725	683	/**
Kojto	122:f9eeca106725	684	* @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	685	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
Kojto	122:f9eeca106725	686	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	687	*/
Kojto	122:f9eeca106725	688	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
Kojto	122:f9eeca106725	689	{
Kojto	122:f9eeca106725	690	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
Kojto	122:f9eeca106725	691	}
Kojto	122:f9eeca106725	692
Kojto	122:f9eeca106725	693	/**
Kojto	122:f9eeca106725	694	* @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	695	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
Kojto	122:f9eeca106725	696	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	697	*/
Kojto	122:f9eeca106725	698	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
Kojto	122:f9eeca106725	699	{
Kojto	122:f9eeca106725	700	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
Kojto	122:f9eeca106725	701	}
Kojto	122:f9eeca106725	702
Kojto	122:f9eeca106725	703	/**
Kojto	122:f9eeca106725	704	* @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	705	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
Kojto	122:f9eeca106725	706	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	707	*/
Kojto	122:f9eeca106725	708	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
Kojto	122:f9eeca106725	709	{
Kojto	122:f9eeca106725	710	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
Kojto	122:f9eeca106725	711	}
Kojto	122:f9eeca106725	712
Kojto	122:f9eeca106725	713	/**
Kojto	122:f9eeca106725	714	* @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	715	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
Kojto	122:f9eeca106725	716	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	717	*/
Kojto	122:f9eeca106725	718	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
Kojto	122:f9eeca106725	719	{
Kojto	122:f9eeca106725	720	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
Kojto	122:f9eeca106725	721	}
Kojto	122:f9eeca106725	722
Kojto	122:f9eeca106725	723	/**
Kojto	122:f9eeca106725	724	* @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	725	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
Kojto	122:f9eeca106725	726	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	727	*/
Kojto	122:f9eeca106725	728	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
Kojto	122:f9eeca106725	729	{
Kojto	122:f9eeca106725	730	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
Kojto	122:f9eeca106725	731	}
Kojto	122:f9eeca106725	732
Kojto	122:f9eeca106725	733	/**
Kojto	122:f9eeca106725	734	* @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	735	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
Kojto	122:f9eeca106725	736	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	737	*/
Kojto	122:f9eeca106725	738	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
Kojto	122:f9eeca106725	739	{
Kojto	122:f9eeca106725	740	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
Kojto	122:f9eeca106725	741	}
Kojto	122:f9eeca106725	742
Kojto	122:f9eeca106725	743	/**
Kojto	122:f9eeca106725	744	* @brief Configure source input for the EXTI external interrupt.
Kojto	122:f9eeca106725	745	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
Kojto	122:f9eeca106725	746	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
Kojto	122:f9eeca106725	747	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
Kojto	122:f9eeca106725	748	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
Kojto	122:f9eeca106725	749	* @param Port This parameter can be one of the following values:
Kojto	122:f9eeca106725	750	* @arg @ref LL_SYSCFG_EXTI_PORTA
Kojto	122:f9eeca106725	751	* @arg @ref LL_SYSCFG_EXTI_PORTB
Kojto	122:f9eeca106725	752	* @arg @ref LL_SYSCFG_EXTI_PORTC
Kojto	122:f9eeca106725	753	* @arg @ref LL_SYSCFG_EXTI_PORTD
Kojto	122:f9eeca106725	754	* @arg @ref LL_SYSCFG_EXTI_PORTE
Kojto	122:f9eeca106725	755	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
Kojto	122:f9eeca106725	756	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
Kojto	122:f9eeca106725	757	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	145:64910690c574	758	* @arg @ref LL_SYSCFG_EXTI_PORTI (*)
Kojto	122:f9eeca106725	759	*
Kojto	122:f9eeca106725	760	* (*) value not defined in all devices
Kojto	122:f9eeca106725	761	* @param Line This parameter can be one of the following values:
Kojto	122:f9eeca106725	762	* @arg @ref LL_SYSCFG_EXTI_LINE0
Kojto	122:f9eeca106725	763	* @arg @ref LL_SYSCFG_EXTI_LINE1
Kojto	122:f9eeca106725	764	* @arg @ref LL_SYSCFG_EXTI_LINE2
Kojto	122:f9eeca106725	765	* @arg @ref LL_SYSCFG_EXTI_LINE3
Kojto	122:f9eeca106725	766	* @arg @ref LL_SYSCFG_EXTI_LINE4
Kojto	122:f9eeca106725	767	* @arg @ref LL_SYSCFG_EXTI_LINE5
Kojto	122:f9eeca106725	768	* @arg @ref LL_SYSCFG_EXTI_LINE6
Kojto	122:f9eeca106725	769	* @arg @ref LL_SYSCFG_EXTI_LINE7
Kojto	122:f9eeca106725	770	* @arg @ref LL_SYSCFG_EXTI_LINE8
Kojto	122:f9eeca106725	771	* @arg @ref LL_SYSCFG_EXTI_LINE9
Kojto	122:f9eeca106725	772	* @arg @ref LL_SYSCFG_EXTI_LINE10
Kojto	122:f9eeca106725	773	* @arg @ref LL_SYSCFG_EXTI_LINE11
Kojto	122:f9eeca106725	774	* @arg @ref LL_SYSCFG_EXTI_LINE12
Kojto	122:f9eeca106725	775	* @arg @ref LL_SYSCFG_EXTI_LINE13
Kojto	122:f9eeca106725	776	* @arg @ref LL_SYSCFG_EXTI_LINE14
Kojto	122:f9eeca106725	777	* @arg @ref LL_SYSCFG_EXTI_LINE15
Kojto	122:f9eeca106725	778	* @retval None
Kojto	122:f9eeca106725	779	*/
Kojto	122:f9eeca106725	780	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
Kojto	122:f9eeca106725	781	{
AnnaBridge	145:64910690c574	782	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
Kojto	122:f9eeca106725	783	}
Kojto	122:f9eeca106725	784
Kojto	122:f9eeca106725	785	/**
Kojto	122:f9eeca106725	786	* @brief Get the configured defined for specific EXTI Line
Kojto	122:f9eeca106725	787	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
Kojto	122:f9eeca106725	788	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
Kojto	122:f9eeca106725	789	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
Kojto	122:f9eeca106725	790	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
Kojto	122:f9eeca106725	791	* @param Line This parameter can be one of the following values:
Kojto	122:f9eeca106725	792	* @arg @ref LL_SYSCFG_EXTI_LINE0
Kojto	122:f9eeca106725	793	* @arg @ref LL_SYSCFG_EXTI_LINE1
Kojto	122:f9eeca106725	794	* @arg @ref LL_SYSCFG_EXTI_LINE2
Kojto	122:f9eeca106725	795	* @arg @ref LL_SYSCFG_EXTI_LINE3
Kojto	122:f9eeca106725	796	* @arg @ref LL_SYSCFG_EXTI_LINE4
Kojto	122:f9eeca106725	797	* @arg @ref LL_SYSCFG_EXTI_LINE5
Kojto	122:f9eeca106725	798	* @arg @ref LL_SYSCFG_EXTI_LINE6
Kojto	122:f9eeca106725	799	* @arg @ref LL_SYSCFG_EXTI_LINE7
Kojto	122:f9eeca106725	800	* @arg @ref LL_SYSCFG_EXTI_LINE8
Kojto	122:f9eeca106725	801	* @arg @ref LL_SYSCFG_EXTI_LINE9
Kojto	122:f9eeca106725	802	* @arg @ref LL_SYSCFG_EXTI_LINE10
Kojto	122:f9eeca106725	803	* @arg @ref LL_SYSCFG_EXTI_LINE11
Kojto	122:f9eeca106725	804	* @arg @ref LL_SYSCFG_EXTI_LINE12
Kojto	122:f9eeca106725	805	* @arg @ref LL_SYSCFG_EXTI_LINE13
Kojto	122:f9eeca106725	806	* @arg @ref LL_SYSCFG_EXTI_LINE14
Kojto	122:f9eeca106725	807	* @arg @ref LL_SYSCFG_EXTI_LINE15
Kojto	122:f9eeca106725	808	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	809	* @arg @ref LL_SYSCFG_EXTI_PORTA
Kojto	122:f9eeca106725	810	* @arg @ref LL_SYSCFG_EXTI_PORTB
Kojto	122:f9eeca106725	811	* @arg @ref LL_SYSCFG_EXTI_PORTC
Kojto	122:f9eeca106725	812	* @arg @ref LL_SYSCFG_EXTI_PORTD
Kojto	122:f9eeca106725	813	* @arg @ref LL_SYSCFG_EXTI_PORTE
Kojto	122:f9eeca106725	814	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
Kojto	122:f9eeca106725	815	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
Kojto	122:f9eeca106725	816	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	145:64910690c574	817	* @arg @ref LL_SYSCFG_EXTI_PORTI (*)
Kojto	122:f9eeca106725	818	*
Kojto	122:f9eeca106725	819	* (*) value not defined in all devices
Kojto	122:f9eeca106725	820	*/
Kojto	122:f9eeca106725	821	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
Kojto	122:f9eeca106725	822	{
AnnaBridge	145:64910690c574	823	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
Kojto	122:f9eeca106725	824	}
Kojto	122:f9eeca106725	825
Kojto	122:f9eeca106725	826	/**
Kojto	122:f9eeca106725	827	* @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
Kojto	122:f9eeca106725	828	* automatically cleared at the end of the SRAM2 erase operation.)
Kojto	122:f9eeca106725	829	* @note This bit is write-protected: setting this bit is possible only after the
AnnaBridge	145:64910690c574	830	* correct key sequence is written in the SYSCFG_SKR register as described in
AnnaBridge	145:64910690c574	831	* the Reference Manual.
Kojto	122:f9eeca106725	832	* @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
Kojto	122:f9eeca106725	833	* @retval None
Kojto	122:f9eeca106725	834	*/
Kojto	122:f9eeca106725	835	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
Kojto	122:f9eeca106725	836	{
Kojto	122:f9eeca106725	837	/* Starts a hardware SRAM2 erase operation*/
Kojto	122:f9eeca106725	838	SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
Kojto	122:f9eeca106725	839	}
Kojto	122:f9eeca106725	840
Kojto	122:f9eeca106725	841	/**
Kojto	122:f9eeca106725	842	* @brief Check if SRAM2 erase operation is on going
Kojto	122:f9eeca106725	843	* @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
Kojto	122:f9eeca106725	844	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	845	*/
Kojto	122:f9eeca106725	846	__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
Kojto	122:f9eeca106725	847	{
Kojto	122:f9eeca106725	848	return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
Kojto	122:f9eeca106725	849	}
Kojto	122:f9eeca106725	850
Kojto	122:f9eeca106725	851	/**
Kojto	122:f9eeca106725	852	* @brief Set connections to TIM1/8/15/16/17 Break inputs
Kojto	122:f9eeca106725	853	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
Kojto	122:f9eeca106725	854	* SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
Kojto	122:f9eeca106725	855	* SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
Kojto	122:f9eeca106725	856	* SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
Kojto	122:f9eeca106725	857	* @param Break This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	858	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
Kojto	122:f9eeca106725	859	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
Kojto	122:f9eeca106725	860	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
Kojto	122:f9eeca106725	861	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
Kojto	122:f9eeca106725	862	* @retval None
Kojto	122:f9eeca106725	863	*/
Kojto	122:f9eeca106725	864	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
Kojto	122:f9eeca106725	865	{
Kojto	122:f9eeca106725	866	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL, Break);
Kojto	122:f9eeca106725	867	}
Kojto	122:f9eeca106725	868
Kojto	122:f9eeca106725	869	/**
Kojto	122:f9eeca106725	870	* @brief Get connections to TIM1/8/15/16/17 Break inputs
Kojto	122:f9eeca106725	871	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
Kojto	122:f9eeca106725	872	* SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
Kojto	122:f9eeca106725	873	* SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
Kojto	122:f9eeca106725	874	* SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
Kojto	122:f9eeca106725	875	* @retval Returned value can be can be a combination of the following values:
Kojto	122:f9eeca106725	876	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
Kojto	122:f9eeca106725	877	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
Kojto	122:f9eeca106725	878	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
Kojto	122:f9eeca106725	879	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
Kojto	122:f9eeca106725	880	*/
Kojto	122:f9eeca106725	881	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
Kojto	122:f9eeca106725	882	{
Kojto	122:f9eeca106725	883	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL));
Kojto	122:f9eeca106725	884	}
Kojto	122:f9eeca106725	885
Kojto	122:f9eeca106725	886	/**
Kojto	122:f9eeca106725	887	* @brief Check if SRAM2 parity error detected
Kojto	122:f9eeca106725	888	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
Kojto	122:f9eeca106725	889	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	890	*/
Kojto	122:f9eeca106725	891	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
Kojto	122:f9eeca106725	892	{
Kojto	122:f9eeca106725	893	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
Kojto	122:f9eeca106725	894	}
Kojto	122:f9eeca106725	895
Kojto	122:f9eeca106725	896	/**
Kojto	122:f9eeca106725	897	* @brief Clear SRAM2 parity error flag
Kojto	122:f9eeca106725	898	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
Kojto	122:f9eeca106725	899	* @retval None
Kojto	122:f9eeca106725	900	*/
Kojto	122:f9eeca106725	901	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
Kojto	122:f9eeca106725	902	{
Kojto	122:f9eeca106725	903	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
Kojto	122:f9eeca106725	904	}
Kojto	122:f9eeca106725	905
Kojto	122:f9eeca106725	906	/**
AnnaBridge	145:64910690c574	907	* @brief Enable SRAM2 page write protection for Pages in range 0 to 31
Kojto	122:f9eeca106725	908	* @note Write protection is cleared only by a system reset
AnnaBridge	145:64910690c574	909	* @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
Kojto	122:f9eeca106725	910	* @param SRAM2WRP This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	911	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
Kojto	122:f9eeca106725	912	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
Kojto	122:f9eeca106725	913	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
Kojto	122:f9eeca106725	914	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
Kojto	122:f9eeca106725	915	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
Kojto	122:f9eeca106725	916	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
Kojto	122:f9eeca106725	917	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
Kojto	122:f9eeca106725	918	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
Kojto	122:f9eeca106725	919	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
Kojto	122:f9eeca106725	920	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
Kojto	122:f9eeca106725	921	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
Kojto	122:f9eeca106725	922	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
Kojto	122:f9eeca106725	923	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
Kojto	122:f9eeca106725	924	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
Kojto	122:f9eeca106725	925	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
Kojto	122:f9eeca106725	926	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
Kojto	122:f9eeca106725	927	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
Kojto	122:f9eeca106725	928	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
Kojto	122:f9eeca106725	929	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
Kojto	122:f9eeca106725	930	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
Kojto	122:f9eeca106725	931	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
Kojto	122:f9eeca106725	932	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
Kojto	122:f9eeca106725	933	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
Kojto	122:f9eeca106725	934	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
Kojto	122:f9eeca106725	935	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
Kojto	122:f9eeca106725	936	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
Kojto	122:f9eeca106725	937	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
Kojto	122:f9eeca106725	938	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
Kojto	122:f9eeca106725	939	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
Kojto	122:f9eeca106725	940	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
Kojto	122:f9eeca106725	941	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
Kojto	122:f9eeca106725	942	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
Kojto	122:f9eeca106725	943	*
Kojto	122:f9eeca106725	944	* (*) value not defined in all devices
Kojto	122:f9eeca106725	945	* @retval None
Kojto	122:f9eeca106725	946	*/
AnnaBridge	145:64910690c574	947	/* Legacy define */
AnnaBridge	145:64910690c574	948	#define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
AnnaBridge	145:64910690c574	949	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
Kojto	122:f9eeca106725	950	{
Kojto	122:f9eeca106725	951	SET_BIT(SYSCFG->SWPR, SRAM2WRP);
Kojto	122:f9eeca106725	952	}
Kojto	122:f9eeca106725	953
AnnaBridge	145:64910690c574	954	#if defined(SYSCFG_SWPR2_PAGE63)
AnnaBridge	145:64910690c574	955	/**
AnnaBridge	145:64910690c574	956	* @brief Enable SRAM2 page write protection for Pages in range 32 to 63
AnnaBridge	145:64910690c574	957	* @note Write protection is cleared only by a system reset
AnnaBridge	145:64910690c574	958	* @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
AnnaBridge	145:64910690c574	959	* @param SRAM2WRP This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	960	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)
AnnaBridge	145:64910690c574	961	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)
AnnaBridge	145:64910690c574	962	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)
AnnaBridge	145:64910690c574	963	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)
AnnaBridge	145:64910690c574	964	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)
AnnaBridge	145:64910690c574	965	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)
AnnaBridge	145:64910690c574	966	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)
AnnaBridge	145:64910690c574	967	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)
AnnaBridge	145:64910690c574	968	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)
AnnaBridge	145:64910690c574	969	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)
AnnaBridge	145:64910690c574	970	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)
AnnaBridge	145:64910690c574	971	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)
AnnaBridge	145:64910690c574	972	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)
AnnaBridge	145:64910690c574	973	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)
AnnaBridge	145:64910690c574	974	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)
AnnaBridge	145:64910690c574	975	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)
AnnaBridge	145:64910690c574	976	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)
AnnaBridge	145:64910690c574	977	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)
AnnaBridge	145:64910690c574	978	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)
AnnaBridge	145:64910690c574	979	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)
AnnaBridge	145:64910690c574	980	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)
AnnaBridge	145:64910690c574	981	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)
AnnaBridge	145:64910690c574	982	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)
AnnaBridge	145:64910690c574	983	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)
AnnaBridge	145:64910690c574	984	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)
AnnaBridge	145:64910690c574	985	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)
AnnaBridge	145:64910690c574	986	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)
AnnaBridge	145:64910690c574	987	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)
AnnaBridge	145:64910690c574	988	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)
AnnaBridge	145:64910690c574	989	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)
AnnaBridge	145:64910690c574	990	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)
AnnaBridge	145:64910690c574	991	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)
AnnaBridge	145:64910690c574	992	*
AnnaBridge	145:64910690c574	993	* (*) value not defined in all devices
AnnaBridge	145:64910690c574	994	* @retval None
AnnaBridge	145:64910690c574	995	*/
AnnaBridge	145:64910690c574	996	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
AnnaBridge	145:64910690c574	997	{
AnnaBridge	145:64910690c574	998	SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
AnnaBridge	145:64910690c574	999	}
AnnaBridge	145:64910690c574	1000	#endif /* SYSCFG_SWPR2_PAGE63 */
AnnaBridge	145:64910690c574	1001
Kojto	122:f9eeca106725	1002	/**
Kojto	122:f9eeca106725	1003	* @brief SRAM2 page write protection lock prior to erase
Kojto	122:f9eeca106725	1004	* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
Kojto	122:f9eeca106725	1005	* @retval None
Kojto	122:f9eeca106725	1006	*/
Kojto	122:f9eeca106725	1007	__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
Kojto	122:f9eeca106725	1008	{
Kojto	122:f9eeca106725	1009	/* Writing a wrong key reactivates the write protection */
Kojto	122:f9eeca106725	1010	WRITE_REG(SYSCFG->SKR, 0x00);
Kojto	122:f9eeca106725	1011	}
Kojto	122:f9eeca106725	1012
Kojto	122:f9eeca106725	1013	/**
Kojto	122:f9eeca106725	1014	* @brief SRAM2 page write protection unlock prior to erase
Kojto	122:f9eeca106725	1015	* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
Kojto	122:f9eeca106725	1016	* @retval None
Kojto	122:f9eeca106725	1017	*/
Kojto	122:f9eeca106725	1018	__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
Kojto	122:f9eeca106725	1019	{
Kojto	122:f9eeca106725	1020	/* unlock the write protection of the SRAM2ER bit */
Kojto	122:f9eeca106725	1021	WRITE_REG(SYSCFG->SKR, 0xCA);
Kojto	122:f9eeca106725	1022	WRITE_REG(SYSCFG->SKR, 0x53);
Kojto	122:f9eeca106725	1023	}
Kojto	122:f9eeca106725	1024
Kojto	122:f9eeca106725	1025	/**
Kojto	122:f9eeca106725	1026	* @}
Kojto	122:f9eeca106725	1027	*/
Kojto	122:f9eeca106725	1028
Kojto	122:f9eeca106725	1029
Kojto	122:f9eeca106725	1030	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
Kojto	122:f9eeca106725	1031	* @{
Kojto	122:f9eeca106725	1032	*/
Kojto	122:f9eeca106725	1033
Kojto	122:f9eeca106725	1034	/**
Kojto	122:f9eeca106725	1035	* @brief Return the device identifier
Kojto	122:f9eeca106725	1036	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
Kojto	122:f9eeca106725	1037	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
Kojto	122:f9eeca106725	1038	*/
Kojto	122:f9eeca106725	1039	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
Kojto	122:f9eeca106725	1040	{
Kojto	122:f9eeca106725	1041	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
Kojto	122:f9eeca106725	1042	}
Kojto	122:f9eeca106725	1043
Kojto	122:f9eeca106725	1044	/**
Kojto	122:f9eeca106725	1045	* @brief Return the device revision identifier
Kojto	122:f9eeca106725	1046	* @note This field indicates the revision of the device.
Kojto	122:f9eeca106725	1047	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
Kojto	122:f9eeca106725	1048	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
Kojto	122:f9eeca106725	1049	*/
Kojto	122:f9eeca106725	1050	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
Kojto	122:f9eeca106725	1051	{
Kojto	122:f9eeca106725	1052	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
Kojto	122:f9eeca106725	1053	}
Kojto	122:f9eeca106725	1054
Kojto	122:f9eeca106725	1055	/**
Kojto	122:f9eeca106725	1056	* @brief Enable the Debug Module during SLEEP mode
Kojto	122:f9eeca106725	1057	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
Kojto	122:f9eeca106725	1058	* @retval None
Kojto	122:f9eeca106725	1059	*/
Kojto	122:f9eeca106725	1060	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
Kojto	122:f9eeca106725	1061	{
Kojto	122:f9eeca106725	1062	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
Kojto	122:f9eeca106725	1063	}
Kojto	122:f9eeca106725	1064
Kojto	122:f9eeca106725	1065	/**
Kojto	122:f9eeca106725	1066	* @brief Disable the Debug Module during SLEEP mode
Kojto	122:f9eeca106725	1067	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
Kojto	122:f9eeca106725	1068	* @retval None
Kojto	122:f9eeca106725	1069	*/
Kojto	122:f9eeca106725	1070	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
Kojto	122:f9eeca106725	1071	{
Kojto	122:f9eeca106725	1072	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
Kojto	122:f9eeca106725	1073	}
Kojto	122:f9eeca106725	1074
Kojto	122:f9eeca106725	1075	/**
Kojto	122:f9eeca106725	1076	* @brief Enable the Debug Module during STOP mode
Kojto	122:f9eeca106725	1077	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
Kojto	122:f9eeca106725	1078	* @retval None
Kojto	122:f9eeca106725	1079	*/
Kojto	122:f9eeca106725	1080	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
Kojto	122:f9eeca106725	1081	{
Kojto	122:f9eeca106725	1082	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
Kojto	122:f9eeca106725	1083	}
Kojto	122:f9eeca106725	1084
Kojto	122:f9eeca106725	1085	/**
Kojto	122:f9eeca106725	1086	* @brief Disable the Debug Module during STOP mode
Kojto	122:f9eeca106725	1087	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
Kojto	122:f9eeca106725	1088	* @retval None
Kojto	122:f9eeca106725	1089	*/
Kojto	122:f9eeca106725	1090	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
Kojto	122:f9eeca106725	1091	{
Kojto	122:f9eeca106725	1092	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
Kojto	122:f9eeca106725	1093	}
Kojto	122:f9eeca106725	1094
Kojto	122:f9eeca106725	1095	/**
Kojto	122:f9eeca106725	1096	* @brief Enable the Debug Module during STANDBY mode
Kojto	122:f9eeca106725	1097	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
Kojto	122:f9eeca106725	1098	* @retval None
Kojto	122:f9eeca106725	1099	*/
Kojto	122:f9eeca106725	1100	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
Kojto	122:f9eeca106725	1101	{
Kojto	122:f9eeca106725	1102	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
Kojto	122:f9eeca106725	1103	}
Kojto	122:f9eeca106725	1104
Kojto	122:f9eeca106725	1105	/**
Kojto	122:f9eeca106725	1106	* @brief Disable the Debug Module during STANDBY mode
Kojto	122:f9eeca106725	1107	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
Kojto	122:f9eeca106725	1108	* @retval None
Kojto	122:f9eeca106725	1109	*/
Kojto	122:f9eeca106725	1110	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
Kojto	122:f9eeca106725	1111	{
Kojto	122:f9eeca106725	1112	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
Kojto	122:f9eeca106725	1113	}
Kojto	122:f9eeca106725	1114
Kojto	122:f9eeca106725	1115	/**
Kojto	122:f9eeca106725	1116	* @brief Set Trace pin assignment control
Kojto	122:f9eeca106725	1117	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
Kojto	122:f9eeca106725	1118	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
Kojto	122:f9eeca106725	1119	* @param PinAssignment This parameter can be one of the following values:
Kojto	122:f9eeca106725	1120	* @arg @ref LL_DBGMCU_TRACE_NONE
Kojto	122:f9eeca106725	1121	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
Kojto	122:f9eeca106725	1122	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
Kojto	122:f9eeca106725	1123	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
Kojto	122:f9eeca106725	1124	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
Kojto	122:f9eeca106725	1125	* @retval None
Kojto	122:f9eeca106725	1126	*/
Kojto	122:f9eeca106725	1127	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
Kojto	122:f9eeca106725	1128	{
Kojto	122:f9eeca106725	1129	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
Kojto	122:f9eeca106725	1130	}
Kojto	122:f9eeca106725	1131
Kojto	122:f9eeca106725	1132	/**
Kojto	122:f9eeca106725	1133	* @brief Get Trace pin assignment control
Kojto	122:f9eeca106725	1134	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
Kojto	122:f9eeca106725	1135	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
Kojto	122:f9eeca106725	1136	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1137	* @arg @ref LL_DBGMCU_TRACE_NONE
Kojto	122:f9eeca106725	1138	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
Kojto	122:f9eeca106725	1139	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
Kojto	122:f9eeca106725	1140	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
Kojto	122:f9eeca106725	1141	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
Kojto	122:f9eeca106725	1142	*/
Kojto	122:f9eeca106725	1143	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
Kojto	122:f9eeca106725	1144	{
Kojto	122:f9eeca106725	1145	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
Kojto	122:f9eeca106725	1146	}
Kojto	122:f9eeca106725	1147
Kojto	122:f9eeca106725	1148	/**
Kojto	122:f9eeca106725	1149	* @brief Freeze APB1 peripherals (group1 peripherals)
Kojto	122:f9eeca106725	1150	* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
Kojto	122:f9eeca106725	1151	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1152	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
Kojto	122:f9eeca106725	1153	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
Kojto	122:f9eeca106725	1154	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
Kojto	122:f9eeca106725	1155	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
Kojto	122:f9eeca106725	1156	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
Kojto	122:f9eeca106725	1157	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
Kojto	122:f9eeca106725	1158	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
Kojto	122:f9eeca106725	1159	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
Kojto	122:f9eeca106725	1160	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
Kojto	122:f9eeca106725	1161	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
Kojto	122:f9eeca106725	1162	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
Kojto	122:f9eeca106725	1163	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
Kojto	122:f9eeca106725	1164	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
AnnaBridge	145:64910690c574	1165	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
Kojto	122:f9eeca106725	1166	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
Kojto	122:f9eeca106725	1167	*
Kojto	122:f9eeca106725	1168	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1169	* @retval None
Kojto	122:f9eeca106725	1170	*/
Kojto	122:f9eeca106725	1171	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
Kojto	122:f9eeca106725	1172	{
Kojto	122:f9eeca106725	1173	SET_BIT(DBGMCU->APB1FZR1, Periphs);
Kojto	122:f9eeca106725	1174	}
Kojto	122:f9eeca106725	1175
Kojto	122:f9eeca106725	1176	/**
Kojto	122:f9eeca106725	1177	* @brief Freeze APB1 peripherals (group2 peripherals)
Kojto	122:f9eeca106725	1178	* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
Kojto	122:f9eeca106725	1179	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1180	* @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
Kojto	122:f9eeca106725	1181	* @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
AnnaBridge	145:64910690c574	1182	*
AnnaBridge	145:64910690c574	1183	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1184	* @retval None
Kojto	122:f9eeca106725	1185	*/
Kojto	122:f9eeca106725	1186	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
Kojto	122:f9eeca106725	1187	{
Kojto	122:f9eeca106725	1188	SET_BIT(DBGMCU->APB1FZR2, Periphs);
Kojto	122:f9eeca106725	1189	}
Kojto	122:f9eeca106725	1190
Kojto	122:f9eeca106725	1191	/**
Kojto	122:f9eeca106725	1192	* @brief Unfreeze APB1 peripherals (group1 peripherals)
Kojto	122:f9eeca106725	1193	* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
Kojto	122:f9eeca106725	1194	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1195	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
Kojto	122:f9eeca106725	1196	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
Kojto	122:f9eeca106725	1197	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
Kojto	122:f9eeca106725	1198	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
Kojto	122:f9eeca106725	1199	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
Kojto	122:f9eeca106725	1200	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
Kojto	122:f9eeca106725	1201	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
Kojto	122:f9eeca106725	1202	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
Kojto	122:f9eeca106725	1203	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
Kojto	122:f9eeca106725	1204	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
Kojto	122:f9eeca106725	1205	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
Kojto	122:f9eeca106725	1206	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
Kojto	122:f9eeca106725	1207	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
AnnaBridge	145:64910690c574	1208	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
Kojto	122:f9eeca106725	1209	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
Kojto	122:f9eeca106725	1210	*
Kojto	122:f9eeca106725	1211	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1212	* @retval None
Kojto	122:f9eeca106725	1213	*/
Kojto	122:f9eeca106725	1214	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
Kojto	122:f9eeca106725	1215	{
Kojto	122:f9eeca106725	1216	CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
Kojto	122:f9eeca106725	1217	}
Kojto	122:f9eeca106725	1218
Kojto	122:f9eeca106725	1219	/**
Kojto	122:f9eeca106725	1220	* @brief Unfreeze APB1 peripherals (group2 peripherals)
Kojto	122:f9eeca106725	1221	* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
Kojto	122:f9eeca106725	1222	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1223	* @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
Kojto	122:f9eeca106725	1224	* @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
AnnaBridge	145:64910690c574	1225	*
AnnaBridge	145:64910690c574	1226	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1227	* @retval None
Kojto	122:f9eeca106725	1228	*/
Kojto	122:f9eeca106725	1229	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
Kojto	122:f9eeca106725	1230	{
Kojto	122:f9eeca106725	1231	CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
Kojto	122:f9eeca106725	1232	}
Kojto	122:f9eeca106725	1233
Kojto	122:f9eeca106725	1234	/**
Kojto	122:f9eeca106725	1235	* @brief Freeze APB2 peripherals
Kojto	122:f9eeca106725	1236	* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
Kojto	122:f9eeca106725	1237	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1238	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
Kojto	122:f9eeca106725	1239	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
Kojto	122:f9eeca106725	1240	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
Kojto	122:f9eeca106725	1241	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
Kojto	122:f9eeca106725	1242	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
Kojto	122:f9eeca106725	1243	*
Kojto	122:f9eeca106725	1244	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1245	* @retval None
Kojto	122:f9eeca106725	1246	*/
Kojto	122:f9eeca106725	1247	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
Kojto	122:f9eeca106725	1248	{
Kojto	122:f9eeca106725	1249	SET_BIT(DBGMCU->APB2FZ, Periphs);
Kojto	122:f9eeca106725	1250	}
Kojto	122:f9eeca106725	1251
Kojto	122:f9eeca106725	1252	/**
Kojto	122:f9eeca106725	1253	* @brief Unfreeze APB2 peripherals
Kojto	122:f9eeca106725	1254	* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
Kojto	122:f9eeca106725	1255	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1256	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
Kojto	122:f9eeca106725	1257	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
Kojto	122:f9eeca106725	1258	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
Kojto	122:f9eeca106725	1259	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
Kojto	122:f9eeca106725	1260	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
Kojto	122:f9eeca106725	1261	*
Kojto	122:f9eeca106725	1262	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1263	* @retval None
Kojto	122:f9eeca106725	1264	*/
Kojto	122:f9eeca106725	1265	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
Kojto	122:f9eeca106725	1266	{
Kojto	122:f9eeca106725	1267	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
Kojto	122:f9eeca106725	1268	}
Kojto	122:f9eeca106725	1269
Kojto	122:f9eeca106725	1270	/**
Kojto	122:f9eeca106725	1271	* @}
Kojto	122:f9eeca106725	1272	*/
Kojto	122:f9eeca106725	1273
Kojto	122:f9eeca106725	1274	#if defined(VREFBUF)
Kojto	122:f9eeca106725	1275	/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
Kojto	122:f9eeca106725	1276	* @{
Kojto	122:f9eeca106725	1277	*/
Kojto	122:f9eeca106725	1278
Kojto	122:f9eeca106725	1279	/**
Kojto	122:f9eeca106725	1280	* @brief Enable Internal voltage reference
Kojto	122:f9eeca106725	1281	* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
Kojto	122:f9eeca106725	1282	* @retval None
Kojto	122:f9eeca106725	1283	*/
Kojto	122:f9eeca106725	1284	__STATIC_INLINE void LL_VREFBUF_Enable(void)
Kojto	122:f9eeca106725	1285	{
Kojto	122:f9eeca106725	1286	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
Kojto	122:f9eeca106725	1287	}
Kojto	122:f9eeca106725	1288
Kojto	122:f9eeca106725	1289	/**
Kojto	122:f9eeca106725	1290	* @brief Disable Internal voltage reference
Kojto	122:f9eeca106725	1291	* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
Kojto	122:f9eeca106725	1292	* @retval None
Kojto	122:f9eeca106725	1293	*/
Kojto	122:f9eeca106725	1294	__STATIC_INLINE void LL_VREFBUF_Disable(void)
Kojto	122:f9eeca106725	1295	{
Kojto	122:f9eeca106725	1296	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
Kojto	122:f9eeca106725	1297	}
Kojto	122:f9eeca106725	1298
Kojto	122:f9eeca106725	1299	/**
Kojto	122:f9eeca106725	1300	* @brief Enable high impedance (VREF+pin is high impedance)
Kojto	122:f9eeca106725	1301	* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
Kojto	122:f9eeca106725	1302	* @retval None
Kojto	122:f9eeca106725	1303	*/
Kojto	122:f9eeca106725	1304	__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
Kojto	122:f9eeca106725	1305	{
Kojto	122:f9eeca106725	1306	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
Kojto	122:f9eeca106725	1307	}
Kojto	122:f9eeca106725	1308
Kojto	122:f9eeca106725	1309	/**
Kojto	122:f9eeca106725	1310	* @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
Kojto	122:f9eeca106725	1311	* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
Kojto	122:f9eeca106725	1312	* @retval None
Kojto	122:f9eeca106725	1313	*/
Kojto	122:f9eeca106725	1314	__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
Kojto	122:f9eeca106725	1315	{
Kojto	122:f9eeca106725	1316	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
Kojto	122:f9eeca106725	1317	}
Kojto	122:f9eeca106725	1318
Kojto	122:f9eeca106725	1319	/**
Kojto	122:f9eeca106725	1320	* @brief Set the Voltage reference scale
Kojto	122:f9eeca106725	1321	* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
Kojto	122:f9eeca106725	1322	* @param Scale This parameter can be one of the following values:
Kojto	122:f9eeca106725	1323	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
Kojto	122:f9eeca106725	1324	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
Kojto	122:f9eeca106725	1325	* @retval None
Kojto	122:f9eeca106725	1326	*/
Kojto	122:f9eeca106725	1327	__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
Kojto	122:f9eeca106725	1328	{
Kojto	122:f9eeca106725	1329	MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
Kojto	122:f9eeca106725	1330	}
Kojto	122:f9eeca106725	1331
Kojto	122:f9eeca106725	1332	/**
Kojto	122:f9eeca106725	1333	* @brief Get the Voltage reference scale
Kojto	122:f9eeca106725	1334	* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
Kojto	122:f9eeca106725	1335	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1336	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
Kojto	122:f9eeca106725	1337	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
Kojto	122:f9eeca106725	1338	*/
Kojto	122:f9eeca106725	1339	__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
Kojto	122:f9eeca106725	1340	{
Kojto	122:f9eeca106725	1341	return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
Kojto	122:f9eeca106725	1342	}
Kojto	122:f9eeca106725	1343
Kojto	122:f9eeca106725	1344	/**
Kojto	122:f9eeca106725	1345	* @brief Check if Voltage reference buffer is ready
Kojto	122:f9eeca106725	1346	* @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
Kojto	122:f9eeca106725	1347	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1348	*/
Kojto	122:f9eeca106725	1349	__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
Kojto	122:f9eeca106725	1350	{
Kojto	122:f9eeca106725	1351	return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
Kojto	122:f9eeca106725	1352	}
Kojto	122:f9eeca106725	1353
Kojto	122:f9eeca106725	1354	/**
Kojto	122:f9eeca106725	1355	* @brief Get the trimming code for VREFBUF calibration
Kojto	122:f9eeca106725	1356	* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
Kojto	122:f9eeca106725	1357	* @retval Between 0 and 0x3F
Kojto	122:f9eeca106725	1358	*/
Kojto	122:f9eeca106725	1359	__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
Kojto	122:f9eeca106725	1360	{
Kojto	122:f9eeca106725	1361	return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
Kojto	122:f9eeca106725	1362	}
Kojto	122:f9eeca106725	1363
Kojto	122:f9eeca106725	1364	/**
Kojto	122:f9eeca106725	1365	* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
Kojto	122:f9eeca106725	1366	* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
Kojto	122:f9eeca106725	1367	* @param Value Between 0 and 0x3F
Kojto	122:f9eeca106725	1368	* @retval None
Kojto	122:f9eeca106725	1369	*/
Kojto	122:f9eeca106725	1370	__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
Kojto	122:f9eeca106725	1371	{
Kojto	122:f9eeca106725	1372	WRITE_REG(VREFBUF->CCR, Value);
Kojto	122:f9eeca106725	1373	}
Kojto	122:f9eeca106725	1374
Kojto	122:f9eeca106725	1375	/**
Kojto	122:f9eeca106725	1376	* @}
Kojto	122:f9eeca106725	1377	*/
Kojto	122:f9eeca106725	1378	#endif /* VREFBUF */
Kojto	122:f9eeca106725	1379
Kojto	122:f9eeca106725	1380	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
Kojto	122:f9eeca106725	1381	* @{
Kojto	122:f9eeca106725	1382	*/
Kojto	122:f9eeca106725	1383
Kojto	122:f9eeca106725	1384	/**
Kojto	122:f9eeca106725	1385	* @brief Set FLASH Latency
Kojto	122:f9eeca106725	1386	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
Kojto	122:f9eeca106725	1387	* @param Latency This parameter can be one of the following values:
Kojto	122:f9eeca106725	1388	* @arg @ref LL_FLASH_LATENCY_0
Kojto	122:f9eeca106725	1389	* @arg @ref LL_FLASH_LATENCY_1
Kojto	122:f9eeca106725	1390	* @arg @ref LL_FLASH_LATENCY_2
Kojto	122:f9eeca106725	1391	* @arg @ref LL_FLASH_LATENCY_3
Kojto	122:f9eeca106725	1392	* @arg @ref LL_FLASH_LATENCY_4
Kojto	122:f9eeca106725	1393	* @retval None
Kojto	122:f9eeca106725	1394	*/
Kojto	122:f9eeca106725	1395	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
Kojto	122:f9eeca106725	1396	{
Kojto	122:f9eeca106725	1397	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
Kojto	122:f9eeca106725	1398	}
Kojto	122:f9eeca106725	1399
Kojto	122:f9eeca106725	1400	/**
Kojto	122:f9eeca106725	1401	* @brief Get FLASH Latency
Kojto	122:f9eeca106725	1402	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
Kojto	122:f9eeca106725	1403	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1404	* @arg @ref LL_FLASH_LATENCY_0
Kojto	122:f9eeca106725	1405	* @arg @ref LL_FLASH_LATENCY_1
Kojto	122:f9eeca106725	1406	* @arg @ref LL_FLASH_LATENCY_2
Kojto	122:f9eeca106725	1407	* @arg @ref LL_FLASH_LATENCY_3
Kojto	122:f9eeca106725	1408	* @arg @ref LL_FLASH_LATENCY_4
Kojto	122:f9eeca106725	1409	*/
Kojto	122:f9eeca106725	1410	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
Kojto	122:f9eeca106725	1411	{
Kojto	122:f9eeca106725	1412	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
Kojto	122:f9eeca106725	1413	}
Kojto	122:f9eeca106725	1414
Kojto	122:f9eeca106725	1415	/**
Kojto	122:f9eeca106725	1416	* @brief Enable Prefetch
Kojto	122:f9eeca106725	1417	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
Kojto	122:f9eeca106725	1418	* @retval None
Kojto	122:f9eeca106725	1419	*/
Kojto	122:f9eeca106725	1420	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
Kojto	122:f9eeca106725	1421	{
Kojto	122:f9eeca106725	1422	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
Kojto	122:f9eeca106725	1423	}
Kojto	122:f9eeca106725	1424
Kojto	122:f9eeca106725	1425	/**
Kojto	122:f9eeca106725	1426	* @brief Disable Prefetch
Kojto	122:f9eeca106725	1427	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
Kojto	122:f9eeca106725	1428	* @retval None
Kojto	122:f9eeca106725	1429	*/
Kojto	122:f9eeca106725	1430	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
Kojto	122:f9eeca106725	1431	{
Kojto	122:f9eeca106725	1432	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
Kojto	122:f9eeca106725	1433	}
Kojto	122:f9eeca106725	1434
Kojto	122:f9eeca106725	1435	/**
Kojto	122:f9eeca106725	1436	* @brief Check if Prefetch buffer is enabled
Kojto	122:f9eeca106725	1437	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
Kojto	122:f9eeca106725	1438	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1439	*/
Kojto	122:f9eeca106725	1440	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
Kojto	122:f9eeca106725	1441	{
Kojto	122:f9eeca106725	1442	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
Kojto	122:f9eeca106725	1443	}
Kojto	122:f9eeca106725	1444
Kojto	122:f9eeca106725	1445	/**
Kojto	122:f9eeca106725	1446	* @brief Enable Instruction cache
Kojto	122:f9eeca106725	1447	* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
Kojto	122:f9eeca106725	1448	* @retval None
Kojto	122:f9eeca106725	1449	*/
Kojto	122:f9eeca106725	1450	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
Kojto	122:f9eeca106725	1451	{
Kojto	122:f9eeca106725	1452	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
Kojto	122:f9eeca106725	1453	}
Kojto	122:f9eeca106725	1454
Kojto	122:f9eeca106725	1455	/**
Kojto	122:f9eeca106725	1456	* @brief Disable Instruction cache
Kojto	122:f9eeca106725	1457	* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
Kojto	122:f9eeca106725	1458	* @retval None
Kojto	122:f9eeca106725	1459	*/
Kojto	122:f9eeca106725	1460	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
Kojto	122:f9eeca106725	1461	{
Kojto	122:f9eeca106725	1462	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
Kojto	122:f9eeca106725	1463	}
Kojto	122:f9eeca106725	1464
Kojto	122:f9eeca106725	1465	/**
Kojto	122:f9eeca106725	1466	* @brief Enable Data cache
Kojto	122:f9eeca106725	1467	* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
Kojto	122:f9eeca106725	1468	* @retval None
Kojto	122:f9eeca106725	1469	*/
Kojto	122:f9eeca106725	1470	__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
Kojto	122:f9eeca106725	1471	{
Kojto	122:f9eeca106725	1472	SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
Kojto	122:f9eeca106725	1473	}
Kojto	122:f9eeca106725	1474
Kojto	122:f9eeca106725	1475	/**
Kojto	122:f9eeca106725	1476	* @brief Disable Data cache
Kojto	122:f9eeca106725	1477	* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
Kojto	122:f9eeca106725	1478	* @retval None
Kojto	122:f9eeca106725	1479	*/
Kojto	122:f9eeca106725	1480	__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
Kojto	122:f9eeca106725	1481	{
Kojto	122:f9eeca106725	1482	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
Kojto	122:f9eeca106725	1483	}
Kojto	122:f9eeca106725	1484
Kojto	122:f9eeca106725	1485	/**
Kojto	122:f9eeca106725	1486	* @brief Enable Instruction cache reset
Kojto	122:f9eeca106725	1487	* @note bit can be written only when the instruction cache is disabled
Kojto	122:f9eeca106725	1488	* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
Kojto	122:f9eeca106725	1489	* @retval None
Kojto	122:f9eeca106725	1490	*/
Kojto	122:f9eeca106725	1491	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
Kojto	122:f9eeca106725	1492	{
Kojto	122:f9eeca106725	1493	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
Kojto	122:f9eeca106725	1494	}
Kojto	122:f9eeca106725	1495
Kojto	122:f9eeca106725	1496	/**
Kojto	122:f9eeca106725	1497	* @brief Disable Instruction cache reset
Kojto	122:f9eeca106725	1498	* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
Kojto	122:f9eeca106725	1499	* @retval None
Kojto	122:f9eeca106725	1500	*/
Kojto	122:f9eeca106725	1501	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
Kojto	122:f9eeca106725	1502	{
Kojto	122:f9eeca106725	1503	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
Kojto	122:f9eeca106725	1504	}
Kojto	122:f9eeca106725	1505
Kojto	122:f9eeca106725	1506	/**
Kojto	122:f9eeca106725	1507	* @brief Enable Data cache reset
Kojto	122:f9eeca106725	1508	* @note bit can be written only when the data cache is disabled
Kojto	122:f9eeca106725	1509	* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
Kojto	122:f9eeca106725	1510	* @retval None
Kojto	122:f9eeca106725	1511	*/
Kojto	122:f9eeca106725	1512	__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
Kojto	122:f9eeca106725	1513	{
Kojto	122:f9eeca106725	1514	SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
Kojto	122:f9eeca106725	1515	}
Kojto	122:f9eeca106725	1516
Kojto	122:f9eeca106725	1517	/**
Kojto	122:f9eeca106725	1518	* @brief Disable Data cache reset
Kojto	122:f9eeca106725	1519	* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
Kojto	122:f9eeca106725	1520	* @retval None
Kojto	122:f9eeca106725	1521	*/
Kojto	122:f9eeca106725	1522	__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
Kojto	122:f9eeca106725	1523	{
Kojto	122:f9eeca106725	1524	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
Kojto	122:f9eeca106725	1525	}
Kojto	122:f9eeca106725	1526
Kojto	122:f9eeca106725	1527	/**
Kojto	122:f9eeca106725	1528	* @brief Enable Flash Power-down mode during run mode or Low-power run mode
Kojto	122:f9eeca106725	1529	* @note Flash memory can be put in power-down mode only when the code is executed
Kojto	122:f9eeca106725	1530	* from RAM
Kojto	122:f9eeca106725	1531	* @note Flash must not be accessed when power down is enabled
Kojto	122:f9eeca106725	1532	* @note Flash must not be put in power-down while a program or an erase operation
Kojto	122:f9eeca106725	1533	* is on-going
Kojto	122:f9eeca106725	1534	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
Kojto	122:f9eeca106725	1535	* FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
Kojto	122:f9eeca106725	1536	* FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
Kojto	122:f9eeca106725	1537	* @retval None
Kojto	122:f9eeca106725	1538	*/
Kojto	122:f9eeca106725	1539	__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
Kojto	122:f9eeca106725	1540	{
Kojto	122:f9eeca106725	1541	/* Following values must be written consecutively to unlock the RUN_PD bit in
Kojto	122:f9eeca106725	1542	FLASH_ACR */
Kojto	122:f9eeca106725	1543	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
Kojto	122:f9eeca106725	1544	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
Kojto	122:f9eeca106725	1545	SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
Kojto	122:f9eeca106725	1546	}
Kojto	122:f9eeca106725	1547
Kojto	122:f9eeca106725	1548	/**
Kojto	122:f9eeca106725	1549	* @brief Disable Flash Power-down mode during run mode or Low-power run mode
Kojto	122:f9eeca106725	1550	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
Kojto	122:f9eeca106725	1551	* FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
Kojto	122:f9eeca106725	1552	* FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
Kojto	122:f9eeca106725	1553	* @retval None
Kojto	122:f9eeca106725	1554	*/
Kojto	122:f9eeca106725	1555	__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
Kojto	122:f9eeca106725	1556	{
Kojto	122:f9eeca106725	1557	/* Following values must be written consecutively to unlock the RUN_PD bit in
Kojto	122:f9eeca106725	1558	FLASH_ACR */
Kojto	122:f9eeca106725	1559	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
Kojto	122:f9eeca106725	1560	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
Kojto	122:f9eeca106725	1561	CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
Kojto	122:f9eeca106725	1562	}
Kojto	122:f9eeca106725	1563
Kojto	122:f9eeca106725	1564	/**
Kojto	122:f9eeca106725	1565	* @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
Kojto	122:f9eeca106725	1566	* @note Flash must not be put in power-down while a program or an erase operation
Kojto	122:f9eeca106725	1567	* is on-going
Kojto	122:f9eeca106725	1568	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
Kojto	122:f9eeca106725	1569	* @retval None
Kojto	122:f9eeca106725	1570	*/
Kojto	122:f9eeca106725	1571	__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
Kojto	122:f9eeca106725	1572	{
Kojto	122:f9eeca106725	1573	SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
Kojto	122:f9eeca106725	1574	}
Kojto	122:f9eeca106725	1575
Kojto	122:f9eeca106725	1576	/**
Kojto	122:f9eeca106725	1577	* @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
Kojto	122:f9eeca106725	1578	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
Kojto	122:f9eeca106725	1579	* @retval None
Kojto	122:f9eeca106725	1580	*/
Kojto	122:f9eeca106725	1581	__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
Kojto	122:f9eeca106725	1582	{
Kojto	122:f9eeca106725	1583	CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
Kojto	122:f9eeca106725	1584	}
Kojto	122:f9eeca106725	1585
Kojto	122:f9eeca106725	1586	/**
Kojto	122:f9eeca106725	1587	* @}
Kojto	122:f9eeca106725	1588	*/
Kojto	122:f9eeca106725	1589
Kojto	122:f9eeca106725	1590	/**
Kojto	122:f9eeca106725	1591	* @}
Kojto	122:f9eeca106725	1592	*/
Kojto	122:f9eeca106725	1593
Kojto	122:f9eeca106725	1594	/**
Kojto	122:f9eeca106725	1595	* @}
Kojto	122:f9eeca106725	1596	*/
Kojto	122:f9eeca106725	1597
Kojto	122:f9eeca106725	1598	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined (VREFBUF) */
Kojto	122:f9eeca106725	1599
Kojto	122:f9eeca106725	1600	/**
Kojto	122:f9eeca106725	1601	* @}
Kojto	122:f9eeca106725	1602	*/
Kojto	122:f9eeca106725	1603
Kojto	122:f9eeca106725	1604	#ifdef __cplusplus
Kojto	122:f9eeca106725	1605	}
Kojto	122:f9eeca106725	1606	#endif
Kojto	122:f9eeca106725	1607
Kojto	122:f9eeca106725	1608	#endif /* __STM32L4xx_LL_SYSTEM_H */
Kojto	122:f9eeca106725	1609
Kojto	122:f9eeca106725	1610	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/