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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Parent:: 128:9bcdf88f62b0

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_ll_sdmmc.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.7.1
AnnaBridge	145:64910690c574	6	* @date 21-April-2017
Kojto	122:f9eeca106725	7	* @brief Header file of low layer SDMMC HAL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32L4xx_LL_SDMMC_H
Kojto	122:f9eeca106725	40	#define __STM32L4xx_LL_SDMMC_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
Kojto	122:f9eeca106725	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	#if defined(SDMMC1)
Kojto	122:f9eeca106725	47
Kojto	122:f9eeca106725	48	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	49	#include "stm32l4xx_hal_def.h"
Kojto	122:f9eeca106725	50
Kojto	122:f9eeca106725	51	/** @addtogroup STM32L4xx_Driver
Kojto	122:f9eeca106725	52	* @{
Kojto	122:f9eeca106725	53	*/
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	/** @addtogroup SDMMC_LL
Kojto	122:f9eeca106725	56	* @{
Kojto	122:f9eeca106725	57	*/
Kojto	122:f9eeca106725	58
Kojto	122:f9eeca106725	59	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	60	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
Kojto	122:f9eeca106725	61	* @{
Kojto	122:f9eeca106725	62	*/
Kojto	122:f9eeca106725	63
Kojto	122:f9eeca106725	64	/**
Kojto	122:f9eeca106725	65	* @brief SDMMC Configuration Structure definition
Kojto	122:f9eeca106725	66	*/
Kojto	122:f9eeca106725	67	typedef struct
Kojto	122:f9eeca106725	68	{
Kojto	122:f9eeca106725	69	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
Kojto	122:f9eeca106725	70	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
Kojto	122:f9eeca106725	71
Kojto	122:f9eeca106725	72	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
Kojto	122:f9eeca106725	73	enabled or disabled.
Kojto	122:f9eeca106725	74	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
Kojto	122:f9eeca106725	75
Kojto	122:f9eeca106725	76	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
Kojto	122:f9eeca106725	77	disabled when the bus is idle.
Kojto	122:f9eeca106725	78	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
Kojto	122:f9eeca106725	79
Kojto	122:f9eeca106725	80	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
Kojto	122:f9eeca106725	81	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
Kojto	122:f9eeca106725	82
Kojto	122:f9eeca106725	83	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
Kojto	122:f9eeca106725	84	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
Kojto	122:f9eeca106725	85
Kojto	122:f9eeca106725	86	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
Kojto	122:f9eeca106725	87	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	145:64910690c574	88
Kojto	122:f9eeca106725	89	}SDMMC_InitTypeDef;
Kojto	122:f9eeca106725	90
Kojto	122:f9eeca106725	91
Kojto	122:f9eeca106725	92	/**
Kojto	122:f9eeca106725	93	* @brief SDMMC Command Control structure
Kojto	122:f9eeca106725	94	*/
Kojto	122:f9eeca106725	95	typedef struct
Kojto	122:f9eeca106725	96	{
Kojto	122:f9eeca106725	97	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
Kojto	122:f9eeca106725	98	to a card as part of a command message. If a command
Kojto	122:f9eeca106725	99	contains an argument, it must be loaded into this register
Kojto	122:f9eeca106725	100	before writing the command to the command register. */
Kojto	122:f9eeca106725	101
Kojto	122:f9eeca106725	102	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
Kojto	122:f9eeca106725	103	Max_Data = 64 */
Kojto	122:f9eeca106725	104
Kojto	122:f9eeca106725	105	uint32_t Response; /*!< Specifies the SDMMC response type.
Kojto	122:f9eeca106725	106	This parameter can be a value of @ref SDMMC_LL_Response_Type */
Kojto	122:f9eeca106725	107
Kojto	122:f9eeca106725	108	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
Kojto	122:f9eeca106725	109	enabled or disabled.
Kojto	122:f9eeca106725	110	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
Kojto	122:f9eeca106725	111
Kojto	122:f9eeca106725	112	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
Kojto	122:f9eeca106725	113	is enabled or disabled.
Kojto	122:f9eeca106725	114	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
Kojto	122:f9eeca106725	115	}SDMMC_CmdInitTypeDef;
Kojto	122:f9eeca106725	116
Kojto	122:f9eeca106725	117
Kojto	122:f9eeca106725	118	/**
Kojto	122:f9eeca106725	119	* @brief SDMMC Data Control structure
Kojto	122:f9eeca106725	120	*/
Kojto	122:f9eeca106725	121	typedef struct
Kojto	122:f9eeca106725	122	{
Kojto	122:f9eeca106725	123	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
Kojto	122:f9eeca106725	124
Kojto	122:f9eeca106725	125	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
Kojto	122:f9eeca106725	126
Kojto	122:f9eeca106725	127	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
Kojto	122:f9eeca106725	128	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
Kojto	122:f9eeca106725	129
Kojto	122:f9eeca106725	130	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
Kojto	122:f9eeca106725	131	is a read or write.
Kojto	122:f9eeca106725	132	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
Kojto	122:f9eeca106725	133
Kojto	122:f9eeca106725	134	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
Kojto	122:f9eeca106725	135	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
Kojto	122:f9eeca106725	136
Kojto	122:f9eeca106725	137	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
Kojto	122:f9eeca106725	138	is enabled or disabled.
Kojto	122:f9eeca106725	139	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
Kojto	122:f9eeca106725	140	}SDMMC_DataInitTypeDef;
Kojto	122:f9eeca106725	141
Kojto	122:f9eeca106725	142	/**
Kojto	122:f9eeca106725	143	* @}
Kojto	122:f9eeca106725	144	*/
Kojto	122:f9eeca106725	145
Kojto	122:f9eeca106725	146	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	147	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
Kojto	122:f9eeca106725	148	* @{
Kojto	122:f9eeca106725	149	*/
AnnaBridge	145:64910690c574	150	#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
AnnaBridge	145:64910690c574	151	#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /!< Command response received (but CRC check failed) /
AnnaBridge	145:64910690c574	152	#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /!< Data block sent/received (CRC check failed) /
AnnaBridge	145:64910690c574	153	#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /!< Command response timeout /
AnnaBridge	145:64910690c574	154	#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /!< Data timeout /
AnnaBridge	145:64910690c574	155	#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /!< Transmit FIFO underrun /
AnnaBridge	145:64910690c574	156	#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /!< Receive FIFO overrun /
AnnaBridge	145:64910690c574	157	#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /!< Misaligned address /
AnnaBridge	145:64910690c574	158	#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
AnnaBridge	145:64910690c574	159	number of transferred bytes does not match the block length */
AnnaBridge	145:64910690c574	160	#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /!< An error in the sequence of erase command occurs /
AnnaBridge	145:64910690c574	161	#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /!< An invalid selection for erase groups /
AnnaBridge	145:64910690c574	162	#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /!< Attempt to program a write protect block /
AnnaBridge	145:64910690c574	163	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
AnnaBridge	145:64910690c574	164	command or if there was an attempt to access a locked card */
AnnaBridge	145:64910690c574	165	#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /!< CRC check of the previous command failed /
AnnaBridge	145:64910690c574	166	#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /!< Command is not legal for the card state /
AnnaBridge	145:64910690c574	167	#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /!< Card internal ECC was applied but failed to correct the data /
AnnaBridge	145:64910690c574	168	#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /!< Internal card controller error /
AnnaBridge	145:64910690c574	169	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /!< General or unknown error /
AnnaBridge	145:64910690c574	170	#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /!< The card could not sustain data reading in stream rmode /
AnnaBridge	145:64910690c574	171	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /!< The card could not sustain data programming in stream mode /
AnnaBridge	145:64910690c574	172	#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /!< CID/CSD overwrite error /
AnnaBridge	145:64910690c574	173	#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /!< Only partial address space was erased /
AnnaBridge	145:64910690c574	174	#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /!< Command has been executed without using internal ECC /
AnnaBridge	145:64910690c574	175	#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
AnnaBridge	145:64910690c574	176	of erase sequence command was received */
AnnaBridge	145:64910690c574	177	#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /!< Error in sequence of authentication /
AnnaBridge	145:64910690c574	178	#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /!< Error in case of invalid voltage range /
AnnaBridge	145:64910690c574	179	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /!< Error when addressed block is out of range /
AnnaBridge	145:64910690c574	180	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /!< Error when command request is not applicable /
AnnaBridge	145:64910690c574	181	#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /!< the used parameter is not valid /
AnnaBridge	145:64910690c574	182	#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /!< Error when feature is not insupported /
AnnaBridge	145:64910690c574	183	#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /!< Error when transfer process is busy /
AnnaBridge	145:64910690c574	184	#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /!< Error while DMA transfer /
AnnaBridge	145:64910690c574	185	#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /!< Timeout error /
AnnaBridge	145:64910690c574	186
AnnaBridge	145:64910690c574	187	/**
AnnaBridge	145:64910690c574	188	* @brief SDMMC Commands Index
AnnaBridge	145:64910690c574	189	*/
AnnaBridge	145:64910690c574	190	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /!< Resets the SD memory card. /
AnnaBridge	145:64910690c574	191	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /!< Sends host capacity support information and activates the card's initialization process. /
AnnaBridge	145:64910690c574	192	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
AnnaBridge	145:64910690c574	193	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /!< Asks the card to publish a new relative address (RCA). /
AnnaBridge	145:64910690c574	194	#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /!< Programs the DSR of all cards. /
AnnaBridge	145:64910690c574	195	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge	145:64910690c574	196	operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	145:64910690c574	197	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
AnnaBridge	145:64910690c574	198	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /!< Selects the card by its own relative address and gets deselected by any other address /
AnnaBridge	145:64910690c574	199	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge	145:64910690c574	200	and asks the card whether card supports voltage. */
AnnaBridge	145:64910690c574	201	#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
AnnaBridge	145:64910690c574	202	#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /!< Addressed card sends its card identification (CID) on the CMD line. /
AnnaBridge	145:64910690c574	203	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /!< SD card doesn't support it. /
AnnaBridge	145:64910690c574	204	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /!< Forces the card to stop transmission. /
AnnaBridge	145:64910690c574	205	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /!< Addressed card sends its status register. /
AnnaBridge	145:64910690c574	206	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /!< Reserved /
AnnaBridge	145:64910690c574	207	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /!< Sends an addressed card into the inactive state. /
AnnaBridge	145:64910690c574	208	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge	145:64910690c574	209	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge	145:64910690c574	210	for SDHS and SDXC. */
AnnaBridge	145:64910690c574	211	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	145:64910690c574	212	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	145:64910690c574	213	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge	145:64910690c574	214	STOP_TRANSMISSION command. */
AnnaBridge	145:64910690c574	215	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
AnnaBridge	145:64910690c574	216	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /!< Speed class control command. /
AnnaBridge	145:64910690c574	217	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /!< Specify block count for CMD18 and CMD25. /
AnnaBridge	145:64910690c574	218	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	145:64910690c574	219	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	145:64910690c574	220	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
AnnaBridge	145:64910690c574	221	#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /!< Reserved for manufacturers. /
AnnaBridge	145:64910690c574	222	#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /!< Programming of the programmable bits of the CSD. /
AnnaBridge	145:64910690c574	223	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /!< Sets the write protection bit of the addressed group. /
AnnaBridge	145:64910690c574	224	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /!< Clears the write protection bit of the addressed group. /
AnnaBridge	145:64910690c574	225	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /!< Asks the card to send the status of the write protection bits. /
AnnaBridge	145:64910690c574	226	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /!< Sets the address of the first write block to be erased. (For SD card only). /
AnnaBridge	145:64910690c574	227	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /!< Sets the address of the last write block of the continuous range to be erased. /
AnnaBridge	145:64910690c574	228	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge	145:64910690c574	229	system set by switch function command (CMD6). */
AnnaBridge	145:64910690c574	230	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge	145:64910690c574	231	Reserved for each command system set by switch function command (CMD6). */
AnnaBridge	145:64910690c574	232	#define SDMMC_CMD_ERASE ((uint8_t)38U) /!< Reserved for SD security applications. /
AnnaBridge	145:64910690c574	233	#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	145:64910690c574	234	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	145:64910690c574	235	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge	145:64910690c574	236	the SET_BLOCK_LEN command. */
AnnaBridge	145:64910690c574	237	#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge	145:64910690c574	238	than a standard command. */
AnnaBridge	145:64910690c574	239	#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge	145:64910690c574	240	for general purpose/application specific commands. */
AnnaBridge	145:64910690c574	241	#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /!< No command /
AnnaBridge	145:64910690c574	242
AnnaBridge	145:64910690c574	243	/**
AnnaBridge	145:64910690c574	244	* @brief Following commands are SD Card Specific commands.
AnnaBridge	145:64910690c574	245	* SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge	145:64910690c574	246	*/
AnnaBridge	145:64910690c574	247	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge	145:64910690c574	248	widths are given in SCR register. */
AnnaBridge	145:64910690c574	249	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /!< (ACMD13) Sends the SD status. /
AnnaBridge	145:64910690c574	250	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge	145:64910690c574	251	32bit+CRC data block. */
AnnaBridge	145:64910690c574	252	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge	145:64910690c574	253	send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	145:64910690c574	254	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
AnnaBridge	145:64910690c574	255	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /!< Reads the SD Configuration Register (SCR). /
AnnaBridge	145:64910690c574	256	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	145:64910690c574	257	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	145:64910690c574	258
AnnaBridge	145:64910690c574	259	/**
AnnaBridge	145:64910690c574	260	* @brief Following commands are SD Card Specific security commands.
AnnaBridge	145:64910690c574	261	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge	145:64910690c574	262	*/
AnnaBridge	145:64910690c574	263	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
AnnaBridge	145:64910690c574	264	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
AnnaBridge	145:64910690c574	265	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
AnnaBridge	145:64910690c574	266	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
AnnaBridge	145:64910690c574	267	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
AnnaBridge	145:64910690c574	268	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
AnnaBridge	145:64910690c574	269	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
AnnaBridge	145:64910690c574	270	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
AnnaBridge	145:64910690c574	271	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
AnnaBridge	145:64910690c574	272	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
AnnaBridge	145:64910690c574	273	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
AnnaBridge	145:64910690c574	274
AnnaBridge	145:64910690c574	275	/**
AnnaBridge	145:64910690c574	276	* @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge	145:64910690c574	277	*/
AnnaBridge	145:64910690c574	278	#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
AnnaBridge	145:64910690c574	279	#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
AnnaBridge	145:64910690c574	280	#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
AnnaBridge	145:64910690c574	281	#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
AnnaBridge	145:64910690c574	282	#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
AnnaBridge	145:64910690c574	283	#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
AnnaBridge	145:64910690c574	284	#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
AnnaBridge	145:64910690c574	285	#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
AnnaBridge	145:64910690c574	286	#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
AnnaBridge	145:64910690c574	287	#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
AnnaBridge	145:64910690c574	288	#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
AnnaBridge	145:64910690c574	289	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
AnnaBridge	145:64910690c574	290	#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
AnnaBridge	145:64910690c574	291	#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
AnnaBridge	145:64910690c574	292	#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
AnnaBridge	145:64910690c574	293	#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
AnnaBridge	145:64910690c574	294	#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
AnnaBridge	145:64910690c574	295	#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
AnnaBridge	145:64910690c574	296	#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
AnnaBridge	145:64910690c574	297	#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
AnnaBridge	145:64910690c574	298
AnnaBridge	145:64910690c574	299	/**
AnnaBridge	145:64910690c574	300	* @brief Masks for R6 Response
AnnaBridge	145:64910690c574	301	*/
AnnaBridge	145:64910690c574	302	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
AnnaBridge	145:64910690c574	303	#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
AnnaBridge	145:64910690c574	304	#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
AnnaBridge	145:64910690c574	305
AnnaBridge	145:64910690c574	306	#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
AnnaBridge	145:64910690c574	307	#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
AnnaBridge	145:64910690c574	308	#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
AnnaBridge	145:64910690c574	309	#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
AnnaBridge	145:64910690c574	310
AnnaBridge	145:64910690c574	311	#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	145:64910690c574	312
AnnaBridge	145:64910690c574	313	#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	145:64910690c574	314
AnnaBridge	145:64910690c574	315	#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
AnnaBridge	145:64910690c574	316
AnnaBridge	145:64910690c574	317	#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
AnnaBridge	145:64910690c574	318	#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
AnnaBridge	145:64910690c574	319	#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
AnnaBridge	145:64910690c574	320
AnnaBridge	145:64910690c574	321	#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
AnnaBridge	145:64910690c574	322
AnnaBridge	145:64910690c574	323	#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
AnnaBridge	145:64910690c574	324	#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
AnnaBridge	145:64910690c574	325	#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
AnnaBridge	145:64910690c574	326	#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
AnnaBridge	145:64910690c574	327	#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
AnnaBridge	145:64910690c574	328
AnnaBridge	145:64910690c574	329	#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
AnnaBridge	145:64910690c574	330	#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
AnnaBridge	145:64910690c574	331
AnnaBridge	145:64910690c574	332	/**
AnnaBridge	145:64910690c574	333	* @brief Command Class supported
AnnaBridge	145:64910690c574	334	*/
AnnaBridge	145:64910690c574	335	#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
AnnaBridge	145:64910690c574	336
AnnaBridge	145:64910690c574	337	#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
AnnaBridge	145:64910690c574	338	#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
AnnaBridge	145:64910690c574	339	#define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
Kojto	122:f9eeca106725	340
Kojto	122:f9eeca106725	341	/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
Kojto	122:f9eeca106725	342	* @{
Kojto	122:f9eeca106725	343	*/
AnnaBridge	145:64910690c574	344	#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	345	#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
Kojto	122:f9eeca106725	346
Kojto	122:f9eeca106725	347	#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) \|\| \
Kojto	122:f9eeca106725	348	((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
Kojto	122:f9eeca106725	349	/**
Kojto	122:f9eeca106725	350	* @}
Kojto	122:f9eeca106725	351	*/
Kojto	122:f9eeca106725	352
Kojto	122:f9eeca106725	353	/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
Kojto	122:f9eeca106725	354	* @{
Kojto	122:f9eeca106725	355	*/
AnnaBridge	145:64910690c574	356	#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	357	#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
Kojto	122:f9eeca106725	358
Kojto	122:f9eeca106725	359	#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) \|\| \
Kojto	122:f9eeca106725	360	((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
Kojto	122:f9eeca106725	361	/**
Kojto	122:f9eeca106725	362	* @}
Kojto	122:f9eeca106725	363	*/
Kojto	122:f9eeca106725	364
Kojto	122:f9eeca106725	365	/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
Kojto	122:f9eeca106725	366	* @{
Kojto	122:f9eeca106725	367	*/
AnnaBridge	145:64910690c574	368	#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	369	#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
Kojto	122:f9eeca106725	370
Kojto	122:f9eeca106725	371	#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) \|\| \
Kojto	122:f9eeca106725	372	((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
Kojto	122:f9eeca106725	373	/**
Kojto	122:f9eeca106725	374	* @}
Kojto	122:f9eeca106725	375	*/
Kojto	122:f9eeca106725	376
Kojto	122:f9eeca106725	377	/** @defgroup SDMMC_LL_Bus_Wide Bus Width
Kojto	122:f9eeca106725	378	* @{
Kojto	122:f9eeca106725	379	*/
AnnaBridge	145:64910690c574	380	#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	381	#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
Kojto	122:f9eeca106725	382	#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
Kojto	122:f9eeca106725	383
Kojto	122:f9eeca106725	384	#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) \|\| \
Kojto	122:f9eeca106725	385	((WIDE) == SDMMC_BUS_WIDE_4B) \|\| \
Kojto	122:f9eeca106725	386	((WIDE) == SDMMC_BUS_WIDE_8B))
Kojto	122:f9eeca106725	387	/**
Kojto	122:f9eeca106725	388	* @}
Kojto	122:f9eeca106725	389	*/
Kojto	122:f9eeca106725	390
Kojto	122:f9eeca106725	391	/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
Kojto	122:f9eeca106725	392	* @{
Kojto	122:f9eeca106725	393	*/
AnnaBridge	145:64910690c574	394	#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	395	#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
Kojto	122:f9eeca106725	396
Kojto	122:f9eeca106725	397	#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
Kojto	122:f9eeca106725	398	((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
Kojto	122:f9eeca106725	399	/**
Kojto	122:f9eeca106725	400	* @}
Kojto	122:f9eeca106725	401	*/
Kojto	122:f9eeca106725	402
Kojto	122:f9eeca106725	403	/** @defgroup SDMMC_LL_Clock_Division Clock Division
Kojto	122:f9eeca106725	404	* @{
Kojto	122:f9eeca106725	405	*/
Kojto	122:f9eeca106725	406	#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
Kojto	122:f9eeca106725	407	/**
Kojto	122:f9eeca106725	408	* @}
Kojto	122:f9eeca106725	409	*/
Kojto	122:f9eeca106725	410
AnnaBridge	145:64910690c574	411
Kojto	122:f9eeca106725	412	/** @defgroup SDMMC_LL_Command_Index Command Index
Kojto	122:f9eeca106725	413	* @{
Kojto	122:f9eeca106725	414	*/
Kojto	122:f9eeca106725	415	#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
Kojto	122:f9eeca106725	416	/**
Kojto	122:f9eeca106725	417	* @}
Kojto	122:f9eeca106725	418	*/
Kojto	122:f9eeca106725	419
Kojto	122:f9eeca106725	420	/** @defgroup SDMMC_LL_Response_Type Response Type
Kojto	122:f9eeca106725	421	* @{
Kojto	122:f9eeca106725	422	*/
AnnaBridge	145:64910690c574	423	#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	424	#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
Kojto	122:f9eeca106725	425	#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
Kojto	122:f9eeca106725	426
Kojto	122:f9eeca106725	427	#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) \|\| \
Kojto	122:f9eeca106725	428	((RESPONSE) == SDMMC_RESPONSE_SHORT) \|\| \
Kojto	122:f9eeca106725	429	((RESPONSE) == SDMMC_RESPONSE_LONG))
Kojto	122:f9eeca106725	430	/**
Kojto	122:f9eeca106725	431	* @}
Kojto	122:f9eeca106725	432	*/
Kojto	122:f9eeca106725	433
Kojto	122:f9eeca106725	434	/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
Kojto	122:f9eeca106725	435	* @{
Kojto	122:f9eeca106725	436	*/
AnnaBridge	145:64910690c574	437	#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	438	#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
Kojto	122:f9eeca106725	439	#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
Kojto	122:f9eeca106725	440
Kojto	122:f9eeca106725	441	#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) \|\| \
Kojto	122:f9eeca106725	442	((WAIT) == SDMMC_WAIT_IT) \|\| \
Kojto	122:f9eeca106725	443	((WAIT) == SDMMC_WAIT_PEND))
Kojto	122:f9eeca106725	444	/**
Kojto	122:f9eeca106725	445	* @}
Kojto	122:f9eeca106725	446	*/
Kojto	122:f9eeca106725	447
Kojto	122:f9eeca106725	448	/** @defgroup SDMMC_LL_CPSM_State CPSM State
Kojto	122:f9eeca106725	449	* @{
Kojto	122:f9eeca106725	450	*/
AnnaBridge	145:64910690c574	451	#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	452	#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
Kojto	122:f9eeca106725	453
Kojto	122:f9eeca106725	454	#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) \|\| \
Kojto	122:f9eeca106725	455	((CPSM) == SDMMC_CPSM_ENABLE))
Kojto	122:f9eeca106725	456	/**
Kojto	122:f9eeca106725	457	* @}
Kojto	122:f9eeca106725	458	*/
Kojto	122:f9eeca106725	459
Kojto	122:f9eeca106725	460	/** @defgroup SDMMC_LL_Response_Registers Response Register
Kojto	122:f9eeca106725	461	* @{
Kojto	122:f9eeca106725	462	*/
AnnaBridge	145:64910690c574	463	#define SDMMC_RESP1 ((uint32_t)0x00000000U)
AnnaBridge	145:64910690c574	464	#define SDMMC_RESP2 ((uint32_t)0x00000004U)
AnnaBridge	145:64910690c574	465	#define SDMMC_RESP3 ((uint32_t)0x00000008U)
AnnaBridge	145:64910690c574	466	#define SDMMC_RESP4 ((uint32_t)0x0000000CU)
Kojto	122:f9eeca106725	467
Kojto	122:f9eeca106725	468	#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) \|\| \
Kojto	122:f9eeca106725	469	((RESP) == SDMMC_RESP2) \|\| \
Kojto	122:f9eeca106725	470	((RESP) == SDMMC_RESP3) \|\| \
Kojto	122:f9eeca106725	471	((RESP) == SDMMC_RESP4))
AnnaBridge	145:64910690c574	472
Kojto	122:f9eeca106725	473	/**
Kojto	122:f9eeca106725	474	* @}
Kojto	122:f9eeca106725	475	*/
Kojto	122:f9eeca106725	476
Kojto	122:f9eeca106725	477	/** @defgroup SDMMC_LL_Data_Length Data Lenght
Kojto	122:f9eeca106725	478	* @{
Kojto	122:f9eeca106725	479	*/
Kojto	122:f9eeca106725	480	#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
Kojto	122:f9eeca106725	481	/**
Kojto	122:f9eeca106725	482	* @}
Kojto	122:f9eeca106725	483	*/
Kojto	122:f9eeca106725	484
Kojto	122:f9eeca106725	485	/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
Kojto	122:f9eeca106725	486	* @{
Kojto	122:f9eeca106725	487	*/
AnnaBridge	145:64910690c574	488	#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	489	#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
Kojto	122:f9eeca106725	490	#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
Kojto	122:f9eeca106725	491	#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1)
Kojto	122:f9eeca106725	492	#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
Kojto	122:f9eeca106725	493	#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2)
Kojto	122:f9eeca106725	494	#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
Kojto	122:f9eeca106725	495	#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
Kojto	122:f9eeca106725	496	#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
Kojto	122:f9eeca106725	497	#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_3)
Kojto	122:f9eeca106725	498	#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
Kojto	122:f9eeca106725	499	#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
Kojto	122:f9eeca106725	500	#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
Kojto	122:f9eeca106725	501	#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
Kojto	122:f9eeca106725	502	#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
Kojto	122:f9eeca106725	503
Kojto	122:f9eeca106725	504	#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) \|\| \
Kojto	122:f9eeca106725	505	((SIZE) == SDMMC_DATABLOCK_SIZE_2B) \|\| \
Kojto	122:f9eeca106725	506	((SIZE) == SDMMC_DATABLOCK_SIZE_4B) \|\| \
Kojto	122:f9eeca106725	507	((SIZE) == SDMMC_DATABLOCK_SIZE_8B) \|\| \
Kojto	122:f9eeca106725	508	((SIZE) == SDMMC_DATABLOCK_SIZE_16B) \|\| \
Kojto	122:f9eeca106725	509	((SIZE) == SDMMC_DATABLOCK_SIZE_32B) \|\| \
Kojto	122:f9eeca106725	510	((SIZE) == SDMMC_DATABLOCK_SIZE_64B) \|\| \
Kojto	122:f9eeca106725	511	((SIZE) == SDMMC_DATABLOCK_SIZE_128B) \|\| \
Kojto	122:f9eeca106725	512	((SIZE) == SDMMC_DATABLOCK_SIZE_256B) \|\| \
Kojto	122:f9eeca106725	513	((SIZE) == SDMMC_DATABLOCK_SIZE_512B) \|\| \
Kojto	122:f9eeca106725	514	((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) \|\| \
Kojto	122:f9eeca106725	515	((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) \|\| \
Kojto	122:f9eeca106725	516	((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) \|\| \
Kojto	122:f9eeca106725	517	((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) \|\| \
Kojto	122:f9eeca106725	518	((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
Kojto	122:f9eeca106725	519	/**
Kojto	122:f9eeca106725	520	* @}
Kojto	122:f9eeca106725	521	*/
Kojto	122:f9eeca106725	522
Kojto	122:f9eeca106725	523	/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
Kojto	122:f9eeca106725	524	* @{
Kojto	122:f9eeca106725	525	*/
AnnaBridge	145:64910690c574	526	#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	527	#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
Kojto	122:f9eeca106725	528
Kojto	122:f9eeca106725	529	#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) \|\| \
Kojto	122:f9eeca106725	530	((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
Kojto	122:f9eeca106725	531	/**
Kojto	122:f9eeca106725	532	* @}
Kojto	122:f9eeca106725	533	*/
Kojto	122:f9eeca106725	534
Kojto	122:f9eeca106725	535	/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
Kojto	122:f9eeca106725	536	* @{
Kojto	122:f9eeca106725	537	*/
AnnaBridge	145:64910690c574	538	#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	539	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
Kojto	122:f9eeca106725	540
Kojto	122:f9eeca106725	541	#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) \|\| \
Kojto	122:f9eeca106725	542	((MODE) == SDMMC_TRANSFER_MODE_STREAM))
Kojto	122:f9eeca106725	543	/**
Kojto	122:f9eeca106725	544	* @}
Kojto	122:f9eeca106725	545	*/
Kojto	122:f9eeca106725	546
Kojto	122:f9eeca106725	547	/** @defgroup SDMMC_LL_DPSM_State DPSM State
Kojto	122:f9eeca106725	548	* @{
Kojto	122:f9eeca106725	549	*/
AnnaBridge	145:64910690c574	550	#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	551	#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
Kojto	122:f9eeca106725	552
Kojto	122:f9eeca106725	553	#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) \|\|\
Kojto	122:f9eeca106725	554	((DPSM) == SDMMC_DPSM_ENABLE))
Kojto	122:f9eeca106725	555	/**
Kojto	122:f9eeca106725	556	* @}
Kojto	122:f9eeca106725	557	*/
Kojto	122:f9eeca106725	558
Kojto	122:f9eeca106725	559	/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
Kojto	122:f9eeca106725	560	* @{
Kojto	122:f9eeca106725	561	*/
AnnaBridge	145:64910690c574	562	#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	563	#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
Kojto	122:f9eeca106725	564
Kojto	122:f9eeca106725	565	#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) \|\| \
AnnaBridge	145:64910690c574	566	((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
Kojto	122:f9eeca106725	567	/**
Kojto	122:f9eeca106725	568	* @}
Kojto	122:f9eeca106725	569	*/
Kojto	122:f9eeca106725	570
Kojto	122:f9eeca106725	571	/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
Kojto	122:f9eeca106725	572	* @{
Kojto	122:f9eeca106725	573	*/
Kojto	122:f9eeca106725	574	#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
Kojto	122:f9eeca106725	575	#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
Kojto	122:f9eeca106725	576	#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
Kojto	122:f9eeca106725	577	#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
Kojto	122:f9eeca106725	578	#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
Kojto	122:f9eeca106725	579	#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
Kojto	122:f9eeca106725	580	#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
Kojto	122:f9eeca106725	581	#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
Kojto	122:f9eeca106725	582	#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
Kojto	122:f9eeca106725	583	#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
Kojto	122:f9eeca106725	584	#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
Kojto	122:f9eeca106725	585	#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
Kojto	122:f9eeca106725	586	#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
Kojto	122:f9eeca106725	587	#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
Kojto	122:f9eeca106725	588	#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
Kojto	122:f9eeca106725	589	#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
AnnaBridge	145:64910690c574	590	#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
AnnaBridge	145:64910690c574	591	#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
AnnaBridge	145:64910690c574	592	#define SDMMC_IT_TXACT SDMMC_STA_TXACT
AnnaBridge	145:64910690c574	593	#define SDMMC_IT_RXACT SDMMC_STA_RXACT
Kojto	122:f9eeca106725	594	#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
Kojto	122:f9eeca106725	595	#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
Kojto	122:f9eeca106725	596	/**
Kojto	122:f9eeca106725	597	* @}
Kojto	122:f9eeca106725	598	*/
Kojto	122:f9eeca106725	599
Kojto	122:f9eeca106725	600	/** @defgroup SDMMC_LL_Flags Flags
Kojto	122:f9eeca106725	601	* @{
Kojto	122:f9eeca106725	602	*/
Kojto	122:f9eeca106725	603	#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
Kojto	122:f9eeca106725	604	#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
Kojto	122:f9eeca106725	605	#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
Kojto	122:f9eeca106725	606	#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
Kojto	122:f9eeca106725	607	#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
Kojto	122:f9eeca106725	608	#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
Kojto	122:f9eeca106725	609	#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
Kojto	122:f9eeca106725	610	#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
Kojto	122:f9eeca106725	611	#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
Kojto	122:f9eeca106725	612	#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
Kojto	122:f9eeca106725	613	#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
Kojto	122:f9eeca106725	614	#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
Kojto	122:f9eeca106725	615	#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
Kojto	122:f9eeca106725	616	#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
Kojto	122:f9eeca106725	617	#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
Kojto	122:f9eeca106725	618	#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
AnnaBridge	145:64910690c574	619	#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
AnnaBridge	145:64910690c574	620	#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
AnnaBridge	145:64910690c574	621	#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
AnnaBridge	145:64910690c574	622	#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
Kojto	122:f9eeca106725	623	#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
Kojto	122:f9eeca106725	624	#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
AnnaBridge	145:64910690c574	625
AnnaBridge	145:64910690c574	626	#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_CTIMEOUT \|\
AnnaBridge	145:64910690c574	627	SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \| SDMMC_FLAG_RXOVERR \|\
AnnaBridge	145:64910690c574	628	SDMMC_FLAG_CMDREND \| SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_DATAEND \|\
AnnaBridge	145:64910690c574	629	SDMMC_FLAG_DBCKEND))
AnnaBridge	145:64910690c574	630
Kojto	122:f9eeca106725	631	/**
Kojto	122:f9eeca106725	632	* @}
Kojto	122:f9eeca106725	633	*/
Kojto	122:f9eeca106725	634
Kojto	122:f9eeca106725	635	/**
Kojto	122:f9eeca106725	636	* @}
Kojto	122:f9eeca106725	637	*/
Kojto	122:f9eeca106725	638
Kojto	122:f9eeca106725	639	/* Exported macro ------------------------------------------------------------*/
Kojto	122:f9eeca106725	640	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
Kojto	122:f9eeca106725	641	* @{
Kojto	122:f9eeca106725	642	*/
Kojto	122:f9eeca106725	643
Kojto	122:f9eeca106725	644	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
Kojto	122:f9eeca106725	645	* @brief SDMMC_LL registers bit address in the alias region
Kojto	122:f9eeca106725	646	* @{
Kojto	122:f9eeca106725	647	*/
Kojto	122:f9eeca106725	648	/* ---------------------- SDMMC registers bit mask --------------------------- */
Kojto	122:f9eeca106725	649	/* --- CLKCR Register ---*/
AnnaBridge	145:64910690c574	650	/* CLKCR register clear mask */
Kojto	122:f9eeca106725	651	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
Kojto	122:f9eeca106725	652	SDMMC_CLKCR_BYPASS \| SDMMC_CLKCR_WIDBUS \|\
Kojto	122:f9eeca106725	653	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
Kojto	122:f9eeca106725	654
Kojto	122:f9eeca106725	655	/* --- DCTRL Register ---*/
Kojto	122:f9eeca106725	656	/* SDMMC DCTRL Clear Mask */
Kojto	122:f9eeca106725	657	#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN \| SDMMC_DCTRL_DTDIR \|\
Kojto	122:f9eeca106725	658	SDMMC_DCTRL_DTMODE \| SDMMC_DCTRL_DBLOCKSIZE))
Kojto	122:f9eeca106725	659
Kojto	122:f9eeca106725	660	/* --- CMD Register ---*/
Kojto	122:f9eeca106725	661	/* CMD Register clear mask */
Kojto	122:f9eeca106725	662	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
Kojto	122:f9eeca106725	663	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
Kojto	122:f9eeca106725	664	SDMMC_CMD_CPSMEN \| SDMMC_CMD_SDIOSUSPEND))
Kojto	122:f9eeca106725	665
AnnaBridge	145:64910690c574	666	/* SDMMC Initialization Frequency (400KHz max) */
Kojto	122:f9eeca106725	667	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
Kojto	122:f9eeca106725	668
Kojto	122:f9eeca106725	669	/* SDMMC Data Transfer Frequency (25MHz max) */
Kojto	122:f9eeca106725	670	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
Kojto	122:f9eeca106725	671
Kojto	122:f9eeca106725	672	/**
Kojto	122:f9eeca106725	673	* @}
Kojto	122:f9eeca106725	674	*/
Kojto	122:f9eeca106725	675
Kojto	122:f9eeca106725	676	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
Kojto	122:f9eeca106725	677	* @brief macros to handle interrupts and specific clock configurations
Kojto	122:f9eeca106725	678	* @{
Kojto	122:f9eeca106725	679	*/
Kojto	122:f9eeca106725	680
Kojto	122:f9eeca106725	681	/**
Kojto	122:f9eeca106725	682	* @brief Enable the SDMMC device.
Kojto	122:f9eeca106725	683	* @param __INSTANCE__: SDMMC Instance
Kojto	122:f9eeca106725	684	* @retval None
Kojto	122:f9eeca106725	685	*/
Kojto	122:f9eeca106725	686	#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN)
Kojto	122:f9eeca106725	687
Kojto	122:f9eeca106725	688	/**
Kojto	122:f9eeca106725	689	* @brief Disable the SDMMC device.
Kojto	122:f9eeca106725	690	* @param __INSTANCE__: SDMMC Instance
Kojto	122:f9eeca106725	691	* @retval None
Kojto	122:f9eeca106725	692	*/
Kojto	122:f9eeca106725	693	#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
Kojto	122:f9eeca106725	694
Kojto	122:f9eeca106725	695	/**
Kojto	122:f9eeca106725	696	* @brief Enable the SDMMC DMA transfer.
AnnaBridge	145:64910690c574	697	* @param __INSTANCE__: SDMMC Instance
Kojto	122:f9eeca106725	698	* @retval None
Kojto	122:f9eeca106725	699	*/
Kojto	122:f9eeca106725	700	#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN)
Kojto	122:f9eeca106725	701	/**
Kojto	122:f9eeca106725	702	* @brief Disable the SDMMC DMA transfer.
AnnaBridge	145:64910690c574	703	* @param __INSTANCE__: SDMMC Instance
Kojto	122:f9eeca106725	704	* @retval None
Kojto	122:f9eeca106725	705	*/
Kojto	122:f9eeca106725	706	#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
Kojto	122:f9eeca106725	707
Kojto	122:f9eeca106725	708	/**
Kojto	122:f9eeca106725	709	* @brief Enable the SDMMC device interrupt.
Kojto	122:f9eeca106725	710	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	711	* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
Kojto	122:f9eeca106725	712	* This parameter can be one or a combination of the following values:
Kojto	122:f9eeca106725	713	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Kojto	122:f9eeca106725	714	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Kojto	122:f9eeca106725	715	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
Kojto	122:f9eeca106725	716	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
Kojto	122:f9eeca106725	717	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Kojto	122:f9eeca106725	718	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
Kojto	122:f9eeca106725	719	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
Kojto	122:f9eeca106725	720	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
Kojto	122:f9eeca106725	721	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Kojto	122:f9eeca106725	722	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Kojto	122:f9eeca106725	723	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
Kojto	122:f9eeca106725	724	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Kojto	122:f9eeca106725	725	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Kojto	122:f9eeca106725	726	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
Kojto	122:f9eeca106725	727	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
Kojto	122:f9eeca106725	728	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
Kojto	122:f9eeca106725	729	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	145:64910690c574	730	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	145:64910690c574	731	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	145:64910690c574	732	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	145:64910690c574	733	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	145:64910690c574	734	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	145:64910690c574	735	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	145:64910690c574	736	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	145:64910690c574	737	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	145:64910690c574	738	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	145:64910690c574	739	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	145:64910690c574	740	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	145:64910690c574	741	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	145:64910690c574	742	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
Kojto	122:f9eeca106725	743	* @retval None
Kojto	122:f9eeca106725	744	*/
Kojto	122:f9eeca106725	745	#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
Kojto	122:f9eeca106725	746
Kojto	122:f9eeca106725	747	/**
Kojto	122:f9eeca106725	748	* @brief Disable the SDMMC device interrupt.
Kojto	122:f9eeca106725	749	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	750	* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
Kojto	122:f9eeca106725	751	* This parameter can be one or a combination of the following values:
Kojto	122:f9eeca106725	752	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Kojto	122:f9eeca106725	753	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Kojto	122:f9eeca106725	754	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
Kojto	122:f9eeca106725	755	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
Kojto	122:f9eeca106725	756	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Kojto	122:f9eeca106725	757	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
Kojto	122:f9eeca106725	758	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
Kojto	122:f9eeca106725	759	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
Kojto	122:f9eeca106725	760	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Kojto	122:f9eeca106725	761	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Kojto	122:f9eeca106725	762	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
Kojto	122:f9eeca106725	763	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Kojto	122:f9eeca106725	764	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Kojto	122:f9eeca106725	765	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
Kojto	122:f9eeca106725	766	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
Kojto	122:f9eeca106725	767	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
Kojto	122:f9eeca106725	768	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	145:64910690c574	769	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	145:64910690c574	770	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	145:64910690c574	771	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	145:64910690c574	772	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	145:64910690c574	773	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	145:64910690c574	774	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	145:64910690c574	775	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	145:64910690c574	776	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	145:64910690c574	777	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	145:64910690c574	778	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	145:64910690c574	779	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	145:64910690c574	780	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	145:64910690c574	781	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
Kojto	122:f9eeca106725	782	* @retval None
Kojto	122:f9eeca106725	783	*/
Kojto	122:f9eeca106725	784	#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
Kojto	122:f9eeca106725	785
Kojto	122:f9eeca106725	786	/**
Kojto	122:f9eeca106725	787	* @brief Checks whether the specified SDMMC flag is set or not.
Kojto	122:f9eeca106725	788	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	789	* @param __FLAG__: specifies the flag to check.
Kojto	122:f9eeca106725	790	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	791	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
Kojto	122:f9eeca106725	792	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
Kojto	122:f9eeca106725	793	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
Kojto	122:f9eeca106725	794	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
Kojto	122:f9eeca106725	795	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
Kojto	122:f9eeca106725	796	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
Kojto	122:f9eeca106725	797	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
Kojto	122:f9eeca106725	798	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
Kojto	122:f9eeca106725	799	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
Kojto	122:f9eeca106725	800	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
Kojto	122:f9eeca106725	801	* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
Kojto	122:f9eeca106725	802	* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
Kojto	122:f9eeca106725	803	* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
Kojto	122:f9eeca106725	804	* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
Kojto	122:f9eeca106725	805	* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
Kojto	122:f9eeca106725	806	* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
Kojto	122:f9eeca106725	807	* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge	145:64910690c574	808	* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	145:64910690c574	809	* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge	145:64910690c574	810	* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge	145:64910690c574	811	* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge	145:64910690c574	812	* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge	145:64910690c574	813	* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge	145:64910690c574	814	* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge	145:64910690c574	815	* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge	145:64910690c574	816	* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge	145:64910690c574	817	* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge	145:64910690c574	818	* @arg SDMMC_FLAG_TXACT: Data transmit in progress
AnnaBridge	145:64910690c574	819	* @arg SDMMC_FLAG_RXACT: Data receive in progress
AnnaBridge	145:64910690c574	820	* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
AnnaBridge	145:64910690c574	821	* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
Kojto	122:f9eeca106725	822	* @retval The new state of SDMMC_FLAG (SET or RESET).
Kojto	122:f9eeca106725	823	*/
Kojto	122:f9eeca106725	824	#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
Kojto	122:f9eeca106725	825
Kojto	122:f9eeca106725	826
Kojto	122:f9eeca106725	827	/**
Kojto	122:f9eeca106725	828	* @brief Clears the SDMMC pending flags.
Kojto	122:f9eeca106725	829	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	830	* @param __FLAG__: specifies the flag to clear.
Kojto	122:f9eeca106725	831	* This parameter can be one or a combination of the following values:
Kojto	122:f9eeca106725	832	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
Kojto	122:f9eeca106725	833	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
Kojto	122:f9eeca106725	834	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
Kojto	122:f9eeca106725	835	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
Kojto	122:f9eeca106725	836	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
Kojto	122:f9eeca106725	837	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
Kojto	122:f9eeca106725	838	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
Kojto	122:f9eeca106725	839	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
Kojto	122:f9eeca106725	840	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
Kojto	122:f9eeca106725	841	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	145:64910690c574	842	* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	145:64910690c574	843	* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge	145:64910690c574	844	* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge	145:64910690c574	845	* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge	145:64910690c574	846	* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge	145:64910690c574	847	* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge	145:64910690c574	848	* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge	145:64910690c574	849	* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge	145:64910690c574	850	* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge	145:64910690c574	851	* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
Kojto	122:f9eeca106725	852	* @retval None
Kojto	122:f9eeca106725	853	*/
Kojto	122:f9eeca106725	854	#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
Kojto	122:f9eeca106725	855
Kojto	122:f9eeca106725	856	/**
Kojto	122:f9eeca106725	857	* @brief Checks whether the specified SDMMC interrupt has occurred or not.
Kojto	122:f9eeca106725	858	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	859	* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
Kojto	122:f9eeca106725	860	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	861	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Kojto	122:f9eeca106725	862	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Kojto	122:f9eeca106725	863	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
Kojto	122:f9eeca106725	864	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
Kojto	122:f9eeca106725	865	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Kojto	122:f9eeca106725	866	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
Kojto	122:f9eeca106725	867	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
Kojto	122:f9eeca106725	868	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
Kojto	122:f9eeca106725	869	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Kojto	122:f9eeca106725	870	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Kojto	122:f9eeca106725	871	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
Kojto	122:f9eeca106725	872	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Kojto	122:f9eeca106725	873	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Kojto	122:f9eeca106725	874	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
Kojto	122:f9eeca106725	875	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
Kojto	122:f9eeca106725	876	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
Kojto	122:f9eeca106725	877	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
Kojto	122:f9eeca106725	878	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	145:64910690c574	879	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	145:64910690c574	880	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	145:64910690c574	881	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	145:64910690c574	882	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	145:64910690c574	883	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	145:64910690c574	884	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	145:64910690c574	885	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	145:64910690c574	886	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	145:64910690c574	887	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	145:64910690c574	888	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	145:64910690c574	889	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	145:64910690c574	890	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
Kojto	122:f9eeca106725	891	* @retval The new state of SDMMC_IT (SET or RESET).
Kojto	122:f9eeca106725	892	*/
Kojto	122:f9eeca106725	893	#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
Kojto	122:f9eeca106725	894
Kojto	122:f9eeca106725	895	/**
Kojto	122:f9eeca106725	896	* @brief Clears the SDMMC's interrupt pending bits.
Kojto	122:f9eeca106725	897	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	898	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	122:f9eeca106725	899	* This parameter can be one or a combination of the following values:
Kojto	122:f9eeca106725	900	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Kojto	122:f9eeca106725	901	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Kojto	122:f9eeca106725	902	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
Kojto	122:f9eeca106725	903	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
Kojto	122:f9eeca106725	904	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Kojto	122:f9eeca106725	905	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
Kojto	122:f9eeca106725	906	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
Kojto	122:f9eeca106725	907	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
Kojto	122:f9eeca106725	908	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
Kojto	122:f9eeca106725	909	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	145:64910690c574	910	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	145:64910690c574	911	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	145:64910690c574	912	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	145:64910690c574	913	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	145:64910690c574	914	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	145:64910690c574	915	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	145:64910690c574	916	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	145:64910690c574	917	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
Kojto	122:f9eeca106725	918	* @retval None
Kojto	122:f9eeca106725	919	*/
Kojto	122:f9eeca106725	920	#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
Kojto	122:f9eeca106725	921
Kojto	122:f9eeca106725	922	/**
Kojto	122:f9eeca106725	923	* @brief Enable Start the SD I/O Read Wait operation.
Kojto	122:f9eeca106725	924	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	925	* @retval None
Kojto	122:f9eeca106725	926	*/
Kojto	122:f9eeca106725	927	#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART)
Kojto	122:f9eeca106725	928
Kojto	122:f9eeca106725	929	/**
Kojto	122:f9eeca106725	930	* @brief Disable Start the SD I/O Read Wait operations.
Kojto	122:f9eeca106725	931	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	932	* @retval None
Kojto	122:f9eeca106725	933	*/
Kojto	122:f9eeca106725	934	#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
Kojto	122:f9eeca106725	935
Kojto	122:f9eeca106725	936	/**
Kojto	122:f9eeca106725	937	* @brief Enable Start the SD I/O Read Wait operation.
Kojto	122:f9eeca106725	938	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	939	* @retval None
Kojto	122:f9eeca106725	940	*/
Kojto	122:f9eeca106725	941	#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP)
Kojto	122:f9eeca106725	942
Kojto	122:f9eeca106725	943	/**
Kojto	122:f9eeca106725	944	* @brief Disable Stop the SD I/O Read Wait operations.
Kojto	122:f9eeca106725	945	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	946	* @retval None
Kojto	122:f9eeca106725	947	*/
Kojto	122:f9eeca106725	948	#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
Kojto	122:f9eeca106725	949
Kojto	122:f9eeca106725	950	/**
Kojto	122:f9eeca106725	951	* @brief Enable the SD I/O Mode Operation.
Kojto	122:f9eeca106725	952	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	953	* @retval None
Kojto	122:f9eeca106725	954	*/
Kojto	122:f9eeca106725	955	#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_SDIOEN)
Kojto	122:f9eeca106725	956
Kojto	122:f9eeca106725	957	/**
Kojto	122:f9eeca106725	958	* @brief Disable the SD I/O Mode Operation.
Kojto	122:f9eeca106725	959	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	960	* @retval None
Kojto	122:f9eeca106725	961	*/
Kojto	122:f9eeca106725	962	#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
Kojto	122:f9eeca106725	963
Kojto	122:f9eeca106725	964	/**
Kojto	122:f9eeca106725	965	* @brief Enable the SD I/O Suspend command sending.
Kojto	122:f9eeca106725	966	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	967	* @retval None
Kojto	122:f9eeca106725	968	*/
Kojto	122:f9eeca106725	969	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_SDIOSUSPEND)
Kojto	122:f9eeca106725	970
Kojto	122:f9eeca106725	971	/**
Kojto	122:f9eeca106725	972	* @brief Disable the SD I/O Suspend command sending.
Kojto	122:f9eeca106725	973	* @param __INSTANCE__: Pointer to SDMMC register base
Kojto	122:f9eeca106725	974	* @retval None
Kojto	122:f9eeca106725	975	*/
Kojto	122:f9eeca106725	976	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
Kojto	122:f9eeca106725	977
Kojto	122:f9eeca106725	978	/**
AnnaBridge	145:64910690c574	979	* @brief Enable the CMDTRANS mode.
AnnaBridge	145:64910690c574	980	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	145:64910690c574	981	* @retval None
AnnaBridge	145:64910690c574	982	*/
AnnaBridge	145:64910690c574	983	#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_CMDTRANS)
AnnaBridge	145:64910690c574	984
AnnaBridge	145:64910690c574	985	/**
AnnaBridge	145:64910690c574	986	* @brief Disable the CMDTRANS mode.
AnnaBridge	145:64910690c574	987	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	145:64910690c574	988	* @retval None
AnnaBridge	145:64910690c574	989	*/
AnnaBridge	145:64910690c574	990	#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
AnnaBridge	145:64910690c574	991	/**
Kojto	122:f9eeca106725	992	* @}
Kojto	122:f9eeca106725	993	*/
Kojto	122:f9eeca106725	994
Kojto	122:f9eeca106725	995	/**
Kojto	122:f9eeca106725	996	* @}
Kojto	122:f9eeca106725	997	*/
Kojto	122:f9eeca106725	998
Kojto	122:f9eeca106725	999	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	1000	/** @addtogroup SDMMC_LL_Exported_Functions
Kojto	122:f9eeca106725	1001	* @{
Kojto	122:f9eeca106725	1002	*/
Kojto	122:f9eeca106725	1003
Kojto	122:f9eeca106725	1004	/* Initialization/de-initialization functions **********************************/
Kojto	122:f9eeca106725	1005	/** @addtogroup HAL_SDMMC_LL_Group1
Kojto	122:f9eeca106725	1006	* @{
Kojto	122:f9eeca106725	1007	*/
Kojto	122:f9eeca106725	1008	HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
Kojto	122:f9eeca106725	1009	/**
Kojto	122:f9eeca106725	1010	* @}
Kojto	122:f9eeca106725	1011	*/
Kojto	122:f9eeca106725	1012
Kojto	122:f9eeca106725	1013	/* I/O operation functions *****************************************************/
Kojto	122:f9eeca106725	1014	/** @addtogroup HAL_SDMMC_LL_Group2
Kojto	122:f9eeca106725	1015	* @{
Kojto	122:f9eeca106725	1016	*/
Kojto	122:f9eeca106725	1017	uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
Kojto	122:f9eeca106725	1018	HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef SDMMCx, uint32_t pWriteData);
Kojto	122:f9eeca106725	1019	/**
Kojto	122:f9eeca106725	1020	* @}
Kojto	122:f9eeca106725	1021	*/
Kojto	122:f9eeca106725	1022
Kojto	122:f9eeca106725	1023	/* Peripheral Control functions ************************************************/
Kojto	122:f9eeca106725	1024	/** @addtogroup HAL_SDMMC_LL_Group3
Kojto	122:f9eeca106725	1025	* @{
Kojto	122:f9eeca106725	1026	*/
Kojto	122:f9eeca106725	1027	HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
Kojto	122:f9eeca106725	1028	HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
Kojto	122:f9eeca106725	1029	uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
Kojto	122:f9eeca106725	1030
Kojto	122:f9eeca106725	1031	/* Command path state machine (CPSM) management functions */
Kojto	122:f9eeca106725	1032	HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef SDMMCx, SDMMC_CmdInitTypeDef Command);
Kojto	122:f9eeca106725	1033	uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
Kojto	122:f9eeca106725	1034	uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
Kojto	122:f9eeca106725	1035
Kojto	122:f9eeca106725	1036	/* Data path state machine (DPSM) management functions */
AnnaBridge	145:64910690c574	1037	HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef SDMMCx, SDMMC_DataInitTypeDef Data);
Kojto	122:f9eeca106725	1038	uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
Kojto	122:f9eeca106725	1039	uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
Kojto	122:f9eeca106725	1040
Kojto	122:f9eeca106725	1041	/* SDMMC Cards mode management functions */
Kojto	122:f9eeca106725	1042	HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
Kojto	122:f9eeca106725	1043
AnnaBridge	145:64910690c574	1044	/* SDMMC Commands management functions */
AnnaBridge	145:64910690c574	1045	uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
AnnaBridge	145:64910690c574	1046	uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	145:64910690c574	1047	uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	145:64910690c574	1048	uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	145:64910690c574	1049	uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	145:64910690c574	1050	uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	145:64910690c574	1051	uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	145:64910690c574	1052	uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	145:64910690c574	1053	uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	145:64910690c574	1054	uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
AnnaBridge	145:64910690c574	1055	uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
AnnaBridge	145:64910690c574	1056	uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
AnnaBridge	145:64910690c574	1057	uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	145:64910690c574	1058	uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
AnnaBridge	145:64910690c574	1059	uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	145:64910690c574	1060	uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	145:64910690c574	1061	uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
AnnaBridge	145:64910690c574	1062	uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
AnnaBridge	145:64910690c574	1063	uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
AnnaBridge	145:64910690c574	1064	uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	145:64910690c574	1065	uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef SDMMCx, uint16_t pRCA);
AnnaBridge	145:64910690c574	1066	uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	145:64910690c574	1067	uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
AnnaBridge	145:64910690c574	1068	uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	145:64910690c574	1069	uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	145:64910690c574	1070
Kojto	122:f9eeca106725	1071	/**
Kojto	122:f9eeca106725	1072	* @}
Kojto	122:f9eeca106725	1073	*/
Kojto	122:f9eeca106725	1074
Kojto	122:f9eeca106725	1075	/**
Kojto	122:f9eeca106725	1076	* @}
Kojto	122:f9eeca106725	1077	*/
Kojto	122:f9eeca106725	1078
Kojto	122:f9eeca106725	1079	/**
Kojto	122:f9eeca106725	1080	* @}
Kojto	122:f9eeca106725	1081	*/
Kojto	122:f9eeca106725	1082
Kojto	122:f9eeca106725	1083	/**
Kojto	122:f9eeca106725	1084	* @}
Kojto	122:f9eeca106725	1085	*/
Kojto	122:f9eeca106725	1086
Kojto	122:f9eeca106725	1087	#endif /* SDMMC1 */
Kojto	122:f9eeca106725	1088
Kojto	122:f9eeca106725	1089	#ifdef __cplusplus
Kojto	122:f9eeca106725	1090	}
Kojto	122:f9eeca106725	1091	#endif
Kojto	122:f9eeca106725	1092
Kojto	122:f9eeca106725	1093	#endif /* __STM32L4xx_LL_SDMMC_H */
Kojto	122:f9eeca106725	1094
Kojto	122:f9eeca106725	1095	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/