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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h@145:64910690c574, 2017-06-21 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Jun 21 17:31:38 2017 +0100
- Revision:
- 145:64910690c574
- Parent:
- 128:9bcdf88f62b0
Release 145 of the mbed library.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Kojto | 122:f9eeca106725 | 1 | /** |
Kojto | 122:f9eeca106725 | 2 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 3 | * @file stm32l4xx_hal_sram.h |
Kojto | 122:f9eeca106725 | 4 | * @author MCD Application Team |
AnnaBridge | 145:64910690c574 | 5 | * @version V1.7.1 |
AnnaBridge | 145:64910690c574 | 6 | * @date 21-April-2017 |
Kojto | 122:f9eeca106725 | 7 | * @brief Header file of SRAM HAL module. |
Kojto | 122:f9eeca106725 | 8 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 9 | * @attention |
Kojto | 122:f9eeca106725 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
Kojto | 122:f9eeca106725 | 12 | * |
Kojto | 122:f9eeca106725 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
Kojto | 122:f9eeca106725 | 14 | * are permitted provided that the following conditions are met: |
Kojto | 122:f9eeca106725 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
Kojto | 122:f9eeca106725 | 16 | * this list of conditions and the following disclaimer. |
Kojto | 122:f9eeca106725 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
Kojto | 122:f9eeca106725 | 18 | * this list of conditions and the following disclaimer in the documentation |
Kojto | 122:f9eeca106725 | 19 | * and/or other materials provided with the distribution. |
Kojto | 122:f9eeca106725 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
Kojto | 122:f9eeca106725 | 21 | * may be used to endorse or promote products derived from this software |
Kojto | 122:f9eeca106725 | 22 | * without specific prior written permission. |
Kojto | 122:f9eeca106725 | 23 | * |
Kojto | 122:f9eeca106725 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
Kojto | 122:f9eeca106725 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
Kojto | 122:f9eeca106725 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Kojto | 122:f9eeca106725 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
Kojto | 122:f9eeca106725 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
Kojto | 122:f9eeca106725 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
Kojto | 122:f9eeca106725 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
Kojto | 122:f9eeca106725 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
Kojto | 122:f9eeca106725 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
Kojto | 122:f9eeca106725 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Kojto | 122:f9eeca106725 | 34 | * |
Kojto | 122:f9eeca106725 | 35 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 36 | */ |
Kojto | 122:f9eeca106725 | 37 | |
Kojto | 122:f9eeca106725 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
Kojto | 122:f9eeca106725 | 39 | #ifndef __STM32L4xx_HAL_SRAM_H |
Kojto | 122:f9eeca106725 | 40 | #define __STM32L4xx_HAL_SRAM_H |
Kojto | 122:f9eeca106725 | 41 | |
Kojto | 122:f9eeca106725 | 42 | #ifdef __cplusplus |
Kojto | 122:f9eeca106725 | 43 | extern "C" { |
Kojto | 122:f9eeca106725 | 44 | #endif |
Kojto | 122:f9eeca106725 | 45 | |
AnnaBridge | 145:64910690c574 | 46 | #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ |
AnnaBridge | 145:64910690c574 | 47 | defined(STM32L496xx) || defined(STM32L4A6xx) |
Kojto | 122:f9eeca106725 | 48 | |
Kojto | 122:f9eeca106725 | 49 | /* Includes ------------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 50 | #include "stm32l4xx_ll_fmc.h" |
Kojto | 122:f9eeca106725 | 51 | |
Kojto | 122:f9eeca106725 | 52 | /** @addtogroup STM32L4xx_HAL_Driver |
Kojto | 122:f9eeca106725 | 53 | * @{ |
Kojto | 122:f9eeca106725 | 54 | */ |
Kojto | 122:f9eeca106725 | 55 | |
Kojto | 122:f9eeca106725 | 56 | /** @addtogroup SRAM |
Kojto | 122:f9eeca106725 | 57 | * @{ |
Kojto | 122:f9eeca106725 | 58 | */ |
Kojto | 122:f9eeca106725 | 59 | |
Kojto | 122:f9eeca106725 | 60 | /* Exported typedef ----------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 61 | |
Kojto | 122:f9eeca106725 | 62 | /** @defgroup SRAM_Exported_Types SRAM Exported Types |
Kojto | 122:f9eeca106725 | 63 | * @{ |
Kojto | 122:f9eeca106725 | 64 | */ |
Kojto | 122:f9eeca106725 | 65 | /** |
Kojto | 122:f9eeca106725 | 66 | * @brief HAL SRAM State structures definition |
Kojto | 122:f9eeca106725 | 67 | */ |
Kojto | 122:f9eeca106725 | 68 | typedef enum |
Kojto | 122:f9eeca106725 | 69 | { |
Kojto | 122:f9eeca106725 | 70 | HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ |
Kojto | 122:f9eeca106725 | 71 | HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ |
Kojto | 122:f9eeca106725 | 72 | HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ |
Kojto | 122:f9eeca106725 | 73 | HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ |
Kojto | 122:f9eeca106725 | 74 | HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ |
Kojto | 122:f9eeca106725 | 75 | |
Kojto | 122:f9eeca106725 | 76 | }HAL_SRAM_StateTypeDef; |
Kojto | 122:f9eeca106725 | 77 | |
Kojto | 122:f9eeca106725 | 78 | /** |
Kojto | 122:f9eeca106725 | 79 | * @brief SRAM handle Structure definition |
Kojto | 122:f9eeca106725 | 80 | */ |
Kojto | 122:f9eeca106725 | 81 | typedef struct |
Kojto | 122:f9eeca106725 | 82 | { |
Kojto | 122:f9eeca106725 | 83 | FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
Kojto | 122:f9eeca106725 | 84 | |
Kojto | 122:f9eeca106725 | 85 | FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
Kojto | 122:f9eeca106725 | 86 | |
Kojto | 122:f9eeca106725 | 87 | FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ |
Kojto | 122:f9eeca106725 | 88 | |
Kojto | 122:f9eeca106725 | 89 | HAL_LockTypeDef Lock; /*!< SRAM locking object */ |
Kojto | 122:f9eeca106725 | 90 | |
Kojto | 122:f9eeca106725 | 91 | __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ |
Kojto | 122:f9eeca106725 | 92 | |
Kojto | 122:f9eeca106725 | 93 | DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
Kojto | 122:f9eeca106725 | 94 | |
Kojto | 122:f9eeca106725 | 95 | }SRAM_HandleTypeDef; |
Kojto | 122:f9eeca106725 | 96 | |
Kojto | 122:f9eeca106725 | 97 | /** |
Kojto | 122:f9eeca106725 | 98 | * @} |
Kojto | 122:f9eeca106725 | 99 | */ |
Kojto | 122:f9eeca106725 | 100 | |
Kojto | 122:f9eeca106725 | 101 | /* Exported constants --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 102 | /* Exported macro ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 103 | |
Kojto | 122:f9eeca106725 | 104 | /** @defgroup SRAM_Exported_Macros SRAM Exported Macros |
Kojto | 122:f9eeca106725 | 105 | * @{ |
Kojto | 122:f9eeca106725 | 106 | */ |
Kojto | 122:f9eeca106725 | 107 | |
Kojto | 122:f9eeca106725 | 108 | /** @brief Reset SRAM handle state. |
Kojto | 122:f9eeca106725 | 109 | * @param __HANDLE__: SRAM handle |
Kojto | 122:f9eeca106725 | 110 | * @retval None |
Kojto | 122:f9eeca106725 | 111 | */ |
Kojto | 122:f9eeca106725 | 112 | #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) |
Kojto | 122:f9eeca106725 | 113 | |
Kojto | 122:f9eeca106725 | 114 | /** |
Kojto | 122:f9eeca106725 | 115 | * @} |
Kojto | 122:f9eeca106725 | 116 | */ |
Kojto | 122:f9eeca106725 | 117 | |
Kojto | 122:f9eeca106725 | 118 | /* Exported functions --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 119 | /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions |
Kojto | 122:f9eeca106725 | 120 | * @{ |
Kojto | 122:f9eeca106725 | 121 | */ |
Kojto | 122:f9eeca106725 | 122 | |
Kojto | 122:f9eeca106725 | 123 | /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
Kojto | 122:f9eeca106725 | 124 | * @{ |
Kojto | 122:f9eeca106725 | 125 | */ |
Kojto | 122:f9eeca106725 | 126 | |
Kojto | 122:f9eeca106725 | 127 | /* Initialization/de-initialization functions ********************************/ |
Kojto | 122:f9eeca106725 | 128 | HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); |
Kojto | 122:f9eeca106725 | 129 | HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); |
Kojto | 122:f9eeca106725 | 130 | void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); |
Kojto | 122:f9eeca106725 | 131 | void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); |
Kojto | 122:f9eeca106725 | 132 | |
Kojto | 122:f9eeca106725 | 133 | void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
Kojto | 122:f9eeca106725 | 134 | void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
Kojto | 122:f9eeca106725 | 135 | |
Kojto | 122:f9eeca106725 | 136 | /** |
Kojto | 122:f9eeca106725 | 137 | * @} |
Kojto | 122:f9eeca106725 | 138 | */ |
Kojto | 122:f9eeca106725 | 139 | |
Kojto | 122:f9eeca106725 | 140 | /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions |
Kojto | 122:f9eeca106725 | 141 | * @{ |
Kojto | 122:f9eeca106725 | 142 | */ |
Kojto | 122:f9eeca106725 | 143 | |
Kojto | 122:f9eeca106725 | 144 | /* I/O operation functions ***************************************************/ |
Kojto | 122:f9eeca106725 | 145 | HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); |
Kojto | 122:f9eeca106725 | 146 | HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); |
Kojto | 122:f9eeca106725 | 147 | HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); |
Kojto | 122:f9eeca106725 | 148 | HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); |
Kojto | 122:f9eeca106725 | 149 | HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); |
Kojto | 122:f9eeca106725 | 150 | HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); |
Kojto | 122:f9eeca106725 | 151 | HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); |
Kojto | 122:f9eeca106725 | 152 | HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); |
Kojto | 122:f9eeca106725 | 153 | |
Kojto | 122:f9eeca106725 | 154 | /** |
Kojto | 122:f9eeca106725 | 155 | * @} |
Kojto | 122:f9eeca106725 | 156 | */ |
Kojto | 122:f9eeca106725 | 157 | |
Kojto | 122:f9eeca106725 | 158 | /** @addtogroup SRAM_Exported_Functions_Group3 Control functions |
Kojto | 122:f9eeca106725 | 159 | * @{ |
Kojto | 122:f9eeca106725 | 160 | */ |
Kojto | 122:f9eeca106725 | 161 | |
Kojto | 122:f9eeca106725 | 162 | /* SRAM Control functions ****************************************************/ |
Kojto | 122:f9eeca106725 | 163 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); |
Kojto | 122:f9eeca106725 | 164 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); |
Kojto | 122:f9eeca106725 | 165 | |
Kojto | 122:f9eeca106725 | 166 | /** |
Kojto | 122:f9eeca106725 | 167 | * @} |
Kojto | 122:f9eeca106725 | 168 | */ |
Kojto | 122:f9eeca106725 | 169 | |
Kojto | 122:f9eeca106725 | 170 | /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions |
Kojto | 122:f9eeca106725 | 171 | * @{ |
Kojto | 122:f9eeca106725 | 172 | */ |
Kojto | 122:f9eeca106725 | 173 | |
Kojto | 122:f9eeca106725 | 174 | /* SRAM Peripheral State functions ********************************************/ |
Kojto | 122:f9eeca106725 | 175 | HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); |
Kojto | 122:f9eeca106725 | 176 | |
Kojto | 122:f9eeca106725 | 177 | /** |
Kojto | 122:f9eeca106725 | 178 | * @} |
Kojto | 122:f9eeca106725 | 179 | */ |
Kojto | 122:f9eeca106725 | 180 | |
Kojto | 122:f9eeca106725 | 181 | /** |
Kojto | 122:f9eeca106725 | 182 | * @} |
Kojto | 122:f9eeca106725 | 183 | */ |
Kojto | 122:f9eeca106725 | 184 | |
Kojto | 122:f9eeca106725 | 185 | /** |
Kojto | 122:f9eeca106725 | 186 | * @} |
Kojto | 122:f9eeca106725 | 187 | */ |
Kojto | 122:f9eeca106725 | 188 | |
Kojto | 122:f9eeca106725 | 189 | /** |
Kojto | 122:f9eeca106725 | 190 | * @} |
Kojto | 122:f9eeca106725 | 191 | */ |
Kojto | 122:f9eeca106725 | 192 | |
AnnaBridge | 145:64910690c574 | 193 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
AnnaBridge | 145:64910690c574 | 194 | /* STM32L496xx || STM32L4A6xx || */ |
Kojto | 122:f9eeca106725 | 195 | |
Kojto | 122:f9eeca106725 | 196 | #ifdef __cplusplus |
Kojto | 122:f9eeca106725 | 197 | } |
Kojto | 122:f9eeca106725 | 198 | #endif |
Kojto | 122:f9eeca106725 | 199 | |
Kojto | 122:f9eeca106725 | 200 | #endif /* __STM32L4xx_HAL_SRAM_H */ |
Kojto | 122:f9eeca106725 | 201 | |
Kojto | 122:f9eeca106725 | 202 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |