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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Parent:: 128:9bcdf88f62b0

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_hal_spi.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.7.1
AnnaBridge	145:64910690c574	6	* @date 21-April-2017
Kojto	122:f9eeca106725	7	* @brief Header file of SPI HAL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32L4xx_HAL_SPI_H
Kojto	122:f9eeca106725	40	#define __STM32L4xx_HAL_SPI_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
AnnaBridge	145:64910690c574	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	47	#include "stm32l4xx_hal_def.h"
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** @addtogroup STM32L4xx_HAL_Driver
Kojto	122:f9eeca106725	50	* @{
Kojto	122:f9eeca106725	51	*/
Kojto	122:f9eeca106725	52
Kojto	122:f9eeca106725	53	/** @addtogroup SPI
Kojto	122:f9eeca106725	54	* @{
Kojto	122:f9eeca106725	55	*/
Kojto	122:f9eeca106725	56
Kojto	122:f9eeca106725	57	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	58	/** @defgroup SPI_Exported_Types SPI Exported Types
Kojto	122:f9eeca106725	59	* @{
Kojto	122:f9eeca106725	60	*/
Kojto	122:f9eeca106725	61
Kojto	122:f9eeca106725	62	/**
Kojto	122:f9eeca106725	63	* @brief SPI Configuration Structure definition
Kojto	122:f9eeca106725	64	*/
Kojto	122:f9eeca106725	65	typedef struct
Kojto	122:f9eeca106725	66	{
Kojto	122:f9eeca106725	67	uint32_t Mode; /*!< Specifies the SPI operating mode.
Kojto	122:f9eeca106725	68	This parameter can be a value of @ref SPI_Mode */
Kojto	122:f9eeca106725	69
Kojto	122:f9eeca106725	70	uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
Kojto	122:f9eeca106725	71	This parameter can be a value of @ref SPI_Direction */
Kojto	122:f9eeca106725	72
Kojto	122:f9eeca106725	73	uint32_t DataSize; /*!< Specifies the SPI data size.
Kojto	122:f9eeca106725	74	This parameter can be a value of @ref SPI_Data_Size */
Kojto	122:f9eeca106725	75
Kojto	122:f9eeca106725	76	uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
Kojto	122:f9eeca106725	77	This parameter can be a value of @ref SPI_Clock_Polarity */
Kojto	122:f9eeca106725	78
Kojto	122:f9eeca106725	79	uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
Kojto	122:f9eeca106725	80	This parameter can be a value of @ref SPI_Clock_Phase */
Kojto	122:f9eeca106725	81
Kojto	122:f9eeca106725	82	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
Kojto	122:f9eeca106725	83	hardware (NSS pin) or by software using the SSI bit.
Kojto	122:f9eeca106725	84	This parameter can be a value of @ref SPI_Slave_Select_management */
Kojto	122:f9eeca106725	85
Kojto	122:f9eeca106725	86	uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
Kojto	122:f9eeca106725	87	used to configure the transmit and receive SCK clock.
Kojto	122:f9eeca106725	88	This parameter can be a value of @ref SPI_BaudRate_Prescaler
Kojto	122:f9eeca106725	89	@note The communication clock is derived from the master
Kojto	122:f9eeca106725	90	clock. The slave clock does not need to be set. */
Kojto	122:f9eeca106725	91
Kojto	122:f9eeca106725	92	uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
Kojto	122:f9eeca106725	93	This parameter can be a value of @ref SPI_MSB_LSB_transmission */
Kojto	122:f9eeca106725	94
AnnaBridge	145:64910690c574	95	uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
Kojto	122:f9eeca106725	96	This parameter can be a value of @ref SPI_TI_mode */
Kojto	122:f9eeca106725	97
Kojto	122:f9eeca106725	98	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
Kojto	122:f9eeca106725	99	This parameter can be a value of @ref SPI_CRC_Calculation */
Kojto	122:f9eeca106725	100
Kojto	122:f9eeca106725	101	uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	145:64910690c574	102	This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
Kojto	122:f9eeca106725	103
Kojto	122:f9eeca106725	104	uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
Kojto	122:f9eeca106725	105	CRC Length is only used with Data8 and Data16, not other data size
Kojto	122:f9eeca106725	106	This parameter can be a value of @ref SPI_CRC_length */
Kojto	122:f9eeca106725	107
Kojto	122:f9eeca106725	108	uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
Kojto	122:f9eeca106725	109	This parameter can be a value of @ref SPI_NSSP_Mode
Kojto	122:f9eeca106725	110	This mode is activated by the NSSP bit in the SPIx_CR2 register and
Kojto	122:f9eeca106725	111	it takes effect only if the SPI interface is configured as Motorola SPI
Kojto	122:f9eeca106725	112	master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
Kojto	122:f9eeca106725	113	CPOL setting is ignored).. */
Kojto	122:f9eeca106725	114	} SPI_InitTypeDef;
Kojto	122:f9eeca106725	115
Kojto	122:f9eeca106725	116	/**
AnnaBridge	145:64910690c574	117	* @brief HAL SPI State structure definition
Kojto	122:f9eeca106725	118	*/
Kojto	122:f9eeca106725	119	typedef enum
Kojto	122:f9eeca106725	120	{
AnnaBridge	145:64910690c574	121	HAL_SPI_STATE_RESET = 0x00U, /!< Peripheral not Initialized /
AnnaBridge	145:64910690c574	122	HAL_SPI_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
AnnaBridge	145:64910690c574	123	HAL_SPI_STATE_BUSY = 0x02U, /!< an internal process is ongoing /
AnnaBridge	145:64910690c574	124	HAL_SPI_STATE_BUSY_TX = 0x03U, /!< Data Transmission process is ongoing /
AnnaBridge	145:64910690c574	125	HAL_SPI_STATE_BUSY_RX = 0x04U, /!< Data Reception process is ongoing /
AnnaBridge	145:64910690c574	126	HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /!< Data Transmission and Reception process is ongoing /
AnnaBridge	145:64910690c574	127	HAL_SPI_STATE_ERROR = 0x06U, /!< SPI error state /
AnnaBridge	145:64910690c574	128	HAL_SPI_STATE_ABORT = 0x07U /!< SPI abort is ongoing /
AnnaBridge	145:64910690c574	129	} HAL_SPI_StateTypeDef;
Kojto	122:f9eeca106725	130
Kojto	122:f9eeca106725	131	/**
Kojto	122:f9eeca106725	132	* @brief SPI handle Structure definition
Kojto	122:f9eeca106725	133	*/
Kojto	122:f9eeca106725	134	typedef struct __SPI_HandleTypeDef
Kojto	122:f9eeca106725	135	{
Kojto	122:f9eeca106725	136	SPI_TypeDef Instance; /!< SPI registers base address */
Kojto	122:f9eeca106725	137
Kojto	122:f9eeca106725	138	SPI_InitTypeDef Init; /!< SPI communication parameters /
Kojto	122:f9eeca106725	139
Kojto	122:f9eeca106725	140	uint8_t pTxBuffPtr; /!< Pointer to SPI Tx transfer Buffer */
Kojto	122:f9eeca106725	141
Kojto	122:f9eeca106725	142	uint16_t TxXferSize; /!< SPI Tx Transfer size /
Kojto	122:f9eeca106725	143
AnnaBridge	145:64910690c574	144	__IO uint16_t TxXferCount; /!< SPI Tx Transfer Counter /
Kojto	122:f9eeca106725	145
Kojto	122:f9eeca106725	146	uint8_t pRxBuffPtr; /!< Pointer to SPI Rx transfer Buffer */
Kojto	122:f9eeca106725	147
Kojto	122:f9eeca106725	148	uint16_t RxXferSize; /!< SPI Rx Transfer size /
Kojto	122:f9eeca106725	149
AnnaBridge	145:64910690c574	150	__IO uint16_t RxXferCount; /!< SPI Rx Transfer Counter /
Kojto	122:f9eeca106725	151
Kojto	122:f9eeca106725	152	uint32_t CRCSize; /!< SPI CRC size used for the transfer /
Kojto	122:f9eeca106725	153
AnnaBridge	145:64910690c574	154	void (RxISR)(struct __SPI_HandleTypeDef hspi); /!< function pointer on Rx ISR /
Kojto	122:f9eeca106725	155
AnnaBridge	145:64910690c574	156	void (TxISR)(struct __SPI_HandleTypeDef hspi); /!< function pointer on Tx ISR /
Kojto	122:f9eeca106725	157
Kojto	122:f9eeca106725	158	DMA_HandleTypeDef hdmatx; /!< SPI Tx DMA Handle parameters */
Kojto	122:f9eeca106725	159
Kojto	122:f9eeca106725	160	DMA_HandleTypeDef hdmarx; /!< SPI Rx DMA Handle parameters */
Kojto	122:f9eeca106725	161
Kojto	122:f9eeca106725	162	HAL_LockTypeDef Lock; /!< Locking object /
Kojto	122:f9eeca106725	163
Kojto	122:f9eeca106725	164	__IO HAL_SPI_StateTypeDef State; /!< SPI communication state /
Kojto	122:f9eeca106725	165
Kojto	122:f9eeca106725	166	__IO uint32_t ErrorCode; /!< SPI Error code /
Kojto	122:f9eeca106725	167
AnnaBridge	145:64910690c574	168	} SPI_HandleTypeDef;
Kojto	122:f9eeca106725	169
Kojto	122:f9eeca106725	170	/**
Kojto	122:f9eeca106725	171	* @}
Kojto	122:f9eeca106725	172	*/
Kojto	122:f9eeca106725	173
Kojto	122:f9eeca106725	174	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	175	/** @defgroup SPI_Exported_Constants SPI Exported Constants
Kojto	122:f9eeca106725	176	* @{
Kojto	122:f9eeca106725	177	*/
Kojto	122:f9eeca106725	178
Kojto	122:f9eeca106725	179	/** @defgroup SPI_Error_Code SPI Error Code
Kojto	122:f9eeca106725	180	* @{
Kojto	122:f9eeca106725	181	*/
AnnaBridge	145:64910690c574	182	#define HAL_SPI_ERROR_NONE (0x00000000U) /!< No error /
AnnaBridge	145:64910690c574	183	#define HAL_SPI_ERROR_MODF (0x00000001U) /!< MODF error /
AnnaBridge	145:64910690c574	184	#define HAL_SPI_ERROR_CRC (0x00000002U) /!< CRC error /
AnnaBridge	145:64910690c574	185	#define HAL_SPI_ERROR_OVR (0x00000004U) /!< OVR error /
AnnaBridge	145:64910690c574	186	#define HAL_SPI_ERROR_FRE (0x00000008U) /!< FRE error /
AnnaBridge	145:64910690c574	187	#define HAL_SPI_ERROR_DMA (0x00000010U) /!< DMA transfer error /
AnnaBridge	145:64910690c574	188	#define HAL_SPI_ERROR_FLAG (0x00000020U) /!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag /
AnnaBridge	145:64910690c574	189	#define HAL_SPI_ERROR_ABORT (0x00000040U) /!< Error during SPI Abort procedure /
Kojto	122:f9eeca106725	190	/**
Kojto	122:f9eeca106725	191	* @}
Kojto	122:f9eeca106725	192	*/
Kojto	122:f9eeca106725	193
Kojto	122:f9eeca106725	194	/** @defgroup SPI_Mode SPI Mode
Kojto	122:f9eeca106725	195	* @{
Kojto	122:f9eeca106725	196	*/
AnnaBridge	145:64910690c574	197	#define SPI_MODE_SLAVE (0x00000000U)
Kojto	122:f9eeca106725	198	#define SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI)
Kojto	122:f9eeca106725	199	/**
Kojto	122:f9eeca106725	200	* @}
Kojto	122:f9eeca106725	201	*/
Kojto	122:f9eeca106725	202
Kojto	122:f9eeca106725	203	/** @defgroup SPI_Direction SPI Direction Mode
Kojto	122:f9eeca106725	204	* @{
Kojto	122:f9eeca106725	205	*/
AnnaBridge	145:64910690c574	206	#define SPI_DIRECTION_2LINES (0x00000000U)
Kojto	122:f9eeca106725	207	#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
Kojto	122:f9eeca106725	208	#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
Kojto	122:f9eeca106725	209	/**
Kojto	122:f9eeca106725	210	* @}
Kojto	122:f9eeca106725	211	*/
Kojto	122:f9eeca106725	212
Kojto	122:f9eeca106725	213	/** @defgroup SPI_Data_Size SPI Data Size
Kojto	122:f9eeca106725	214	* @{
Kojto	122:f9eeca106725	215	*/
AnnaBridge	145:64910690c574	216	#define SPI_DATASIZE_4BIT (0x00000300U)
AnnaBridge	145:64910690c574	217	#define SPI_DATASIZE_5BIT (0x00000400U)
AnnaBridge	145:64910690c574	218	#define SPI_DATASIZE_6BIT (0x00000500U)
AnnaBridge	145:64910690c574	219	#define SPI_DATASIZE_7BIT (0x00000600U)
AnnaBridge	145:64910690c574	220	#define SPI_DATASIZE_8BIT (0x00000700U)
AnnaBridge	145:64910690c574	221	#define SPI_DATASIZE_9BIT (0x00000800U)
AnnaBridge	145:64910690c574	222	#define SPI_DATASIZE_10BIT (0x00000900U)
AnnaBridge	145:64910690c574	223	#define SPI_DATASIZE_11BIT (0x00000A00U)
AnnaBridge	145:64910690c574	224	#define SPI_DATASIZE_12BIT (0x00000B00U)
AnnaBridge	145:64910690c574	225	#define SPI_DATASIZE_13BIT (0x00000C00U)
AnnaBridge	145:64910690c574	226	#define SPI_DATASIZE_14BIT (0x00000D00U)
AnnaBridge	145:64910690c574	227	#define SPI_DATASIZE_15BIT (0x00000E00U)
AnnaBridge	145:64910690c574	228	#define SPI_DATASIZE_16BIT (0x00000F00U)
Kojto	122:f9eeca106725	229	/**
Kojto	122:f9eeca106725	230	* @}
Kojto	122:f9eeca106725	231	*/
Kojto	122:f9eeca106725	232
Kojto	122:f9eeca106725	233	/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
Kojto	122:f9eeca106725	234	* @{
Kojto	122:f9eeca106725	235	*/
AnnaBridge	145:64910690c574	236	#define SPI_POLARITY_LOW (0x00000000U)
Kojto	122:f9eeca106725	237	#define SPI_POLARITY_HIGH SPI_CR1_CPOL
Kojto	122:f9eeca106725	238	/**
Kojto	122:f9eeca106725	239	* @}
Kojto	122:f9eeca106725	240	*/
Kojto	122:f9eeca106725	241
Kojto	122:f9eeca106725	242	/** @defgroup SPI_Clock_Phase SPI Clock Phase
Kojto	122:f9eeca106725	243	* @{
Kojto	122:f9eeca106725	244	*/
AnnaBridge	145:64910690c574	245	#define SPI_PHASE_1EDGE (0x00000000U)
Kojto	122:f9eeca106725	246	#define SPI_PHASE_2EDGE SPI_CR1_CPHA
Kojto	122:f9eeca106725	247	/**
Kojto	122:f9eeca106725	248	* @}
Kojto	122:f9eeca106725	249	*/
Kojto	122:f9eeca106725	250
AnnaBridge	145:64910690c574	251	/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
Kojto	122:f9eeca106725	252	* @{
Kojto	122:f9eeca106725	253	*/
Kojto	122:f9eeca106725	254	#define SPI_NSS_SOFT SPI_CR1_SSM
AnnaBridge	145:64910690c574	255	#define SPI_NSS_HARD_INPUT (0x00000000U)
AnnaBridge	145:64910690c574	256	#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
Kojto	122:f9eeca106725	257	/**
Kojto	122:f9eeca106725	258	* @}
Kojto	122:f9eeca106725	259	*/
Kojto	122:f9eeca106725	260
Kojto	122:f9eeca106725	261	/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
Kojto	122:f9eeca106725	262	* @{
Kojto	122:f9eeca106725	263	*/
Kojto	122:f9eeca106725	264	#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
AnnaBridge	145:64910690c574	265	#define SPI_NSS_PULSE_DISABLE (0x00000000U)
Kojto	122:f9eeca106725	266	/**
Kojto	122:f9eeca106725	267	* @}
Kojto	122:f9eeca106725	268	*/
Kojto	122:f9eeca106725	269
Kojto	122:f9eeca106725	270	/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
Kojto	122:f9eeca106725	271	* @{
Kojto	122:f9eeca106725	272	*/
AnnaBridge	145:64910690c574	273	#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
AnnaBridge	145:64910690c574	274	#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
AnnaBridge	145:64910690c574	275	#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
AnnaBridge	145:64910690c574	276	#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0)
AnnaBridge	145:64910690c574	277	#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
AnnaBridge	145:64910690c574	278	#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0)
AnnaBridge	145:64910690c574	279	#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1)
AnnaBridge	145:64910690c574	280	#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0)
Kojto	122:f9eeca106725	281	/**
Kojto	122:f9eeca106725	282	* @}
Kojto	122:f9eeca106725	283	*/
Kojto	122:f9eeca106725	284
AnnaBridge	145:64910690c574	285	/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
Kojto	122:f9eeca106725	286	* @{
Kojto	122:f9eeca106725	287	*/
AnnaBridge	145:64910690c574	288	#define SPI_FIRSTBIT_MSB (0x00000000U)
Kojto	122:f9eeca106725	289	#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
Kojto	122:f9eeca106725	290	/**
Kojto	122:f9eeca106725	291	* @}
Kojto	122:f9eeca106725	292	*/
Kojto	122:f9eeca106725	293
AnnaBridge	145:64910690c574	294	/** @defgroup SPI_TI_mode SPI TI Mode
Kojto	122:f9eeca106725	295	* @{
Kojto	122:f9eeca106725	296	*/
AnnaBridge	145:64910690c574	297	#define SPI_TIMODE_DISABLE (0x00000000U)
Kojto	122:f9eeca106725	298	#define SPI_TIMODE_ENABLE SPI_CR2_FRF
Kojto	122:f9eeca106725	299	/**
Kojto	122:f9eeca106725	300	* @}
Kojto	122:f9eeca106725	301	*/
Kojto	122:f9eeca106725	302
Kojto	122:f9eeca106725	303	/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
Kojto	122:f9eeca106725	304	* @{
Kojto	122:f9eeca106725	305	*/
AnnaBridge	145:64910690c574	306	#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
Kojto	122:f9eeca106725	307	#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
Kojto	122:f9eeca106725	308	/**
Kojto	122:f9eeca106725	309	* @}
Kojto	122:f9eeca106725	310	*/
Kojto	122:f9eeca106725	311
Kojto	122:f9eeca106725	312	/** @defgroup SPI_CRC_length SPI CRC Length
Kojto	122:f9eeca106725	313	* @{
Kojto	122:f9eeca106725	314	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	315	* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
Kojto	122:f9eeca106725	316	* SPI_CRC_LENGTH_8BIT : CRC 8bit
Kojto	122:f9eeca106725	317	* SPI_CRC_LENGTH_16BIT : CRC 16bit
Kojto	122:f9eeca106725	318	*/
AnnaBridge	145:64910690c574	319	#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
AnnaBridge	145:64910690c574	320	#define SPI_CRC_LENGTH_8BIT (0x00000001U)
AnnaBridge	145:64910690c574	321	#define SPI_CRC_LENGTH_16BIT (0x00000002U)
Kojto	122:f9eeca106725	322	/**
Kojto	122:f9eeca106725	323	* @}
Kojto	122:f9eeca106725	324	*/
Kojto	122:f9eeca106725	325
Kojto	122:f9eeca106725	326	/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
Kojto	122:f9eeca106725	327	* @{
Kojto	122:f9eeca106725	328	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	329	* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
Kojto	122:f9eeca106725	330	* RXNE event is generated if the FIFO
Kojto	122:f9eeca106725	331	* level is greater or equal to 1/2(16-bits).
Kojto	122:f9eeca106725	332	* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
Kojto	122:f9eeca106725	333	* level is greater or equal to 1/4(8 bits). */
Kojto	122:f9eeca106725	334	#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
Kojto	122:f9eeca106725	335	#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
AnnaBridge	145:64910690c574	336	#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
Kojto	122:f9eeca106725	337
Kojto	122:f9eeca106725	338	/**
Kojto	122:f9eeca106725	339	* @}
Kojto	122:f9eeca106725	340	*/
Kojto	122:f9eeca106725	341
AnnaBridge	145:64910690c574	342	/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
Kojto	122:f9eeca106725	343	* @{
Kojto	122:f9eeca106725	344	*/
Kojto	122:f9eeca106725	345	#define SPI_IT_TXE SPI_CR2_TXEIE
Kojto	122:f9eeca106725	346	#define SPI_IT_RXNE SPI_CR2_RXNEIE
Kojto	122:f9eeca106725	347	#define SPI_IT_ERR SPI_CR2_ERRIE
Kojto	122:f9eeca106725	348	/**
Kojto	122:f9eeca106725	349	* @}
Kojto	122:f9eeca106725	350	*/
Kojto	122:f9eeca106725	351
AnnaBridge	145:64910690c574	352	/** @defgroup SPI_Flags_definition SPI Flags Definition
Kojto	122:f9eeca106725	353	* @{
Kojto	122:f9eeca106725	354	*/
AnnaBridge	145:64910690c574	355	#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
AnnaBridge	145:64910690c574	356	#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
AnnaBridge	145:64910690c574	357	#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
AnnaBridge	145:64910690c574	358	#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
AnnaBridge	145:64910690c574	359	#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
AnnaBridge	145:64910690c574	360	#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
Kojto	122:f9eeca106725	361	#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
AnnaBridge	145:64910690c574	362	#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
AnnaBridge	145:64910690c574	363	#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
Kojto	122:f9eeca106725	364	/**
Kojto	122:f9eeca106725	365	* @}
Kojto	122:f9eeca106725	366	*/
Kojto	122:f9eeca106725	367
Kojto	122:f9eeca106725	368	/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
Kojto	122:f9eeca106725	369	* @{
Kojto	122:f9eeca106725	370	*/
AnnaBridge	145:64910690c574	371	#define SPI_FTLVL_EMPTY (0x00000000U)
AnnaBridge	145:64910690c574	372	#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
AnnaBridge	145:64910690c574	373	#define SPI_FTLVL_HALF_FULL (0x00001000U)
AnnaBridge	145:64910690c574	374	#define SPI_FTLVL_FULL (0x00001800U)
Kojto	122:f9eeca106725	375
Kojto	122:f9eeca106725	376	/**
Kojto	122:f9eeca106725	377	* @}
Kojto	122:f9eeca106725	378	*/
Kojto	122:f9eeca106725	379
Kojto	122:f9eeca106725	380	/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
Kojto	122:f9eeca106725	381	* @{
Kojto	122:f9eeca106725	382	*/
AnnaBridge	145:64910690c574	383	#define SPI_FRLVL_EMPTY (0x00000000U)
AnnaBridge	145:64910690c574	384	#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
AnnaBridge	145:64910690c574	385	#define SPI_FRLVL_HALF_FULL (0x00000400U)
AnnaBridge	145:64910690c574	386	#define SPI_FRLVL_FULL (0x00000600U)
Kojto	122:f9eeca106725	387	/**
Kojto	122:f9eeca106725	388	* @}
Kojto	122:f9eeca106725	389	*/
Kojto	122:f9eeca106725	390
Kojto	122:f9eeca106725	391	/**
Kojto	122:f9eeca106725	392	* @}
Kojto	122:f9eeca106725	393	*/
Kojto	122:f9eeca106725	394
AnnaBridge	145:64910690c574	395	/* Exported macros -----------------------------------------------------------*/
Kojto	122:f9eeca106725	396	/** @defgroup SPI_Exported_Macros SPI Exported Macros
Kojto	122:f9eeca106725	397	* @{
Kojto	122:f9eeca106725	398	*/
Kojto	122:f9eeca106725	399
Kojto	122:f9eeca106725	400	/** @brief Reset SPI handle state.
AnnaBridge	145:64910690c574	401	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	145:64910690c574	402	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	403	* @retval None
Kojto	122:f9eeca106725	404	*/
Kojto	122:f9eeca106725	405	#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Kojto	122:f9eeca106725	406
AnnaBridge	145:64910690c574	407	/** @brief Enable the specified SPI interrupts.
Kojto	122:f9eeca106725	408	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	409	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge	145:64910690c574	410	* @param __INTERRUPT__: specifies the interrupt source to enable.
AnnaBridge	145:64910690c574	411	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	412	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
Kojto	122:f9eeca106725	413	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
Kojto	122:f9eeca106725	414	* @arg SPI_IT_ERR: Error interrupt enable
Kojto	122:f9eeca106725	415	* @retval None
Kojto	122:f9eeca106725	416	*/
AnnaBridge	145:64910690c574	417	#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
AnnaBridge	145:64910690c574	418
AnnaBridge	145:64910690c574	419	/** @brief Disable the specified SPI interrupts.
AnnaBridge	145:64910690c574	420	* @param __HANDLE__: specifies the SPI handle.
AnnaBridge	145:64910690c574	421	* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge	145:64910690c574	422	* @param __INTERRUPT__: specifies the interrupt source to disable.
AnnaBridge	145:64910690c574	423	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	424	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
AnnaBridge	145:64910690c574	425	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
AnnaBridge	145:64910690c574	426	* @arg SPI_IT_ERR: Error interrupt enable
AnnaBridge	145:64910690c574	427	* @retval None
AnnaBridge	145:64910690c574	428	*/
AnnaBridge	145:64910690c574	429	#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Kojto	122:f9eeca106725	430
Kojto	122:f9eeca106725	431	/** @brief Check whether the specified SPI interrupt source is enabled or not.
Kojto	122:f9eeca106725	432	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	433	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	434	* @param __INTERRUPT__: specifies the SPI interrupt source to check.
Kojto	122:f9eeca106725	435	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	436	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
Kojto	122:f9eeca106725	437	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
Kojto	122:f9eeca106725	438	* @arg SPI_IT_ERR: Error interrupt enable
Kojto	122:f9eeca106725	439	* @retval The new state of __IT__ (TRUE or FALSE).
Kojto	122:f9eeca106725	440	*/
Kojto	122:f9eeca106725	441	#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Kojto	122:f9eeca106725	442
Kojto	122:f9eeca106725	443	/** @brief Check whether the specified SPI flag is set or not.
Kojto	122:f9eeca106725	444	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	445	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	446	* @param __FLAG__: specifies the flag to check.
AnnaBridge	145:64910690c574	447	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	448	* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
Kojto	122:f9eeca106725	449	* @arg SPI_FLAG_TXE: Transmit buffer empty flag
Kojto	122:f9eeca106725	450	* @arg SPI_FLAG_CRCERR: CRC error flag
Kojto	122:f9eeca106725	451	* @arg SPI_FLAG_MODF: Mode fault flag
Kojto	122:f9eeca106725	452	* @arg SPI_FLAG_OVR: Overrun flag
Kojto	122:f9eeca106725	453	* @arg SPI_FLAG_BSY: Busy flag
Kojto	122:f9eeca106725	454	* @arg SPI_FLAG_FRE: Frame format error flag
Kojto	122:f9eeca106725	455	* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
Kojto	122:f9eeca106725	456	* @arg SPI_FLAG_FRLVL: SPI fifo reception level
Kojto	122:f9eeca106725	457	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	122:f9eeca106725	458	*/
Kojto	122:f9eeca106725	459	#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Kojto	122:f9eeca106725	460
Kojto	122:f9eeca106725	461	/** @brief Clear the SPI CRCERR pending flag.
Kojto	122:f9eeca106725	462	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	463	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	464	* @retval None
Kojto	122:f9eeca106725	465	*/
Kojto	122:f9eeca106725	466	#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Kojto	122:f9eeca106725	467
Kojto	122:f9eeca106725	468	/** @brief Clear the SPI MODF pending flag.
Kojto	122:f9eeca106725	469	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	470	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	471	* @retval None
Kojto	122:f9eeca106725	472	*/
AnnaBridge	145:64910690c574	473	#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
AnnaBridge	145:64910690c574	474	do{ \
AnnaBridge	145:64910690c574	475	__IO uint32_t tmpreg_modf = 0x00U; \
AnnaBridge	145:64910690c574	476	tmpreg_modf = (__HANDLE__)->Instance->SR; \
AnnaBridge	145:64910690c574	477	CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
AnnaBridge	145:64910690c574	478	UNUSED(tmpreg_modf); \
AnnaBridge	145:64910690c574	479	} while(0U)
Kojto	122:f9eeca106725	480
Kojto	122:f9eeca106725	481	/** @brief Clear the SPI OVR pending flag.
Kojto	122:f9eeca106725	482	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	483	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	484	* @retval None
Kojto	122:f9eeca106725	485	*/
AnnaBridge	145:64910690c574	486	#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
AnnaBridge	145:64910690c574	487	do{ \
AnnaBridge	145:64910690c574	488	__IO uint32_t tmpreg_ovr = 0x00U; \
AnnaBridge	145:64910690c574	489	tmpreg_ovr = (__HANDLE__)->Instance->DR; \
AnnaBridge	145:64910690c574	490	tmpreg_ovr = (__HANDLE__)->Instance->SR; \
AnnaBridge	145:64910690c574	491	UNUSED(tmpreg_ovr); \
AnnaBridge	145:64910690c574	492	} while(0U)
Kojto	122:f9eeca106725	493
Kojto	122:f9eeca106725	494	/** @brief Clear the SPI FRE pending flag.
Kojto	122:f9eeca106725	495	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	496	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	497	* @retval None
Kojto	122:f9eeca106725	498	*/
AnnaBridge	145:64910690c574	499	#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
AnnaBridge	145:64910690c574	500	do{ \
AnnaBridge	145:64910690c574	501	__IO uint32_t tmpreg_fre = 0x00U; \
AnnaBridge	145:64910690c574	502	tmpreg_fre = (__HANDLE__)->Instance->SR; \
AnnaBridge	145:64910690c574	503	UNUSED(tmpreg_fre); \
AnnaBridge	145:64910690c574	504	}while(0U)
Kojto	122:f9eeca106725	505
Kojto	122:f9eeca106725	506	/** @brief Enable the SPI peripheral.
Kojto	122:f9eeca106725	507	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	508	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	509	* @retval None
Kojto	122:f9eeca106725	510	*/
AnnaBridge	145:64910690c574	511	#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Kojto	122:f9eeca106725	512
Kojto	122:f9eeca106725	513	/** @brief Disable the SPI peripheral.
Kojto	122:f9eeca106725	514	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	515	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	516	* @retval None
Kojto	122:f9eeca106725	517	*/
AnnaBridge	145:64910690c574	518	#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Kojto	122:f9eeca106725	519
Kojto	122:f9eeca106725	520	/**
Kojto	122:f9eeca106725	521	* @}
Kojto	122:f9eeca106725	522	*/
Kojto	122:f9eeca106725	523
AnnaBridge	145:64910690c574	524	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	525	/** @defgroup SPI_Private_Macros SPI Private Macros
Kojto	122:f9eeca106725	526	* @{
Kojto	122:f9eeca106725	527	*/
Kojto	122:f9eeca106725	528
Kojto	122:f9eeca106725	529	/** @brief Set the SPI transmit-only mode.
Kojto	122:f9eeca106725	530	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	531	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	532	* @retval None
Kojto	122:f9eeca106725	533	*/
AnnaBridge	145:64910690c574	534	#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Kojto	122:f9eeca106725	535
Kojto	122:f9eeca106725	536	/** @brief Set the SPI receive-only mode.
Kojto	122:f9eeca106725	537	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	538	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	539	* @retval None
Kojto	122:f9eeca106725	540	*/
AnnaBridge	145:64910690c574	541	#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Kojto	122:f9eeca106725	542
Kojto	122:f9eeca106725	543	/** @brief Reset the CRC calculation of the SPI.
Kojto	122:f9eeca106725	544	* @param __HANDLE__: specifies the SPI Handle.
Kojto	122:f9eeca106725	545	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	122:f9eeca106725	546	* @retval None
Kojto	122:f9eeca106725	547	*/
AnnaBridge	145:64910690c574	548	#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
AnnaBridge	145:64910690c574	549	SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
Kojto	122:f9eeca106725	550
Kojto	122:f9eeca106725	551	#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) \|\| \
Kojto	122:f9eeca106725	552	((MODE) == SPI_MODE_MASTER))
Kojto	122:f9eeca106725	553
AnnaBridge	145:64910690c574	554	#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) \|\| \
AnnaBridge	145:64910690c574	555	((MODE) == SPI_DIRECTION_2LINES_RXONLY) \|\| \
AnnaBridge	145:64910690c574	556	((MODE) == SPI_DIRECTION_1LINE))
Kojto	122:f9eeca106725	557
Kojto	122:f9eeca106725	558	#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
Kojto	122:f9eeca106725	559
AnnaBridge	145:64910690c574	560	#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) \|\| \
AnnaBridge	145:64910690c574	561	((MODE) == SPI_DIRECTION_1LINE))
Kojto	122:f9eeca106725	562
Kojto	122:f9eeca106725	563	#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) \|\| \
Kojto	122:f9eeca106725	564	((DATASIZE) == SPI_DATASIZE_15BIT) \|\| \
Kojto	122:f9eeca106725	565	((DATASIZE) == SPI_DATASIZE_14BIT) \|\| \
Kojto	122:f9eeca106725	566	((DATASIZE) == SPI_DATASIZE_13BIT) \|\| \
Kojto	122:f9eeca106725	567	((DATASIZE) == SPI_DATASIZE_12BIT) \|\| \
Kojto	122:f9eeca106725	568	((DATASIZE) == SPI_DATASIZE_11BIT) \|\| \
Kojto	122:f9eeca106725	569	((DATASIZE) == SPI_DATASIZE_10BIT) \|\| \
Kojto	122:f9eeca106725	570	((DATASIZE) == SPI_DATASIZE_9BIT) \|\| \
Kojto	122:f9eeca106725	571	((DATASIZE) == SPI_DATASIZE_8BIT) \|\| \
Kojto	122:f9eeca106725	572	((DATASIZE) == SPI_DATASIZE_7BIT) \|\| \
Kojto	122:f9eeca106725	573	((DATASIZE) == SPI_DATASIZE_6BIT) \|\| \
Kojto	122:f9eeca106725	574	((DATASIZE) == SPI_DATASIZE_5BIT) \|\| \
Kojto	122:f9eeca106725	575	((DATASIZE) == SPI_DATASIZE_4BIT))
Kojto	122:f9eeca106725	576
Kojto	122:f9eeca106725	577	#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) \|\| \
Kojto	122:f9eeca106725	578	((CPOL) == SPI_POLARITY_HIGH))
Kojto	122:f9eeca106725	579
Kojto	122:f9eeca106725	580	#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) \|\| \
Kojto	122:f9eeca106725	581	((CPHA) == SPI_PHASE_2EDGE))
Kojto	122:f9eeca106725	582
AnnaBridge	145:64910690c574	583	#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) \|\| \
Kojto	122:f9eeca106725	584	((NSS) == SPI_NSS_HARD_INPUT) \|\| \
Kojto	122:f9eeca106725	585	((NSS) == SPI_NSS_HARD_OUTPUT))
Kojto	122:f9eeca106725	586
Kojto	122:f9eeca106725	587	#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) \|\| \
Kojto	122:f9eeca106725	588	((NSSP) == SPI_NSS_PULSE_DISABLE))
Kojto	122:f9eeca106725	589
AnnaBridge	145:64910690c574	590	#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) \|\| \
AnnaBridge	145:64910690c574	591	((PRESCALER) == SPI_BAUDRATEPRESCALER_4) \|\| \
AnnaBridge	145:64910690c574	592	((PRESCALER) == SPI_BAUDRATEPRESCALER_8) \|\| \
AnnaBridge	145:64910690c574	593	((PRESCALER) == SPI_BAUDRATEPRESCALER_16) \|\| \
AnnaBridge	145:64910690c574	594	((PRESCALER) == SPI_BAUDRATEPRESCALER_32) \|\| \
AnnaBridge	145:64910690c574	595	((PRESCALER) == SPI_BAUDRATEPRESCALER_64) \|\| \
Kojto	122:f9eeca106725	596	((PRESCALER) == SPI_BAUDRATEPRESCALER_128) \|\| \
Kojto	122:f9eeca106725	597	((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
Kojto	122:f9eeca106725	598
Kojto	122:f9eeca106725	599	#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) \|\| \
Kojto	122:f9eeca106725	600	((BIT) == SPI_FIRSTBIT_LSB))
Kojto	122:f9eeca106725	601
Kojto	122:f9eeca106725	602	#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) \|\| \
Kojto	122:f9eeca106725	603	((MODE) == SPI_TIMODE_ENABLE))
Kojto	122:f9eeca106725	604
Kojto	122:f9eeca106725	605	#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) \|\| \
Kojto	122:f9eeca106725	606	((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
Kojto	122:f9eeca106725	607
Kojto	122:f9eeca106725	608	#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) \|\|\
Kojto	122:f9eeca106725	609	((LENGTH) == SPI_CRC_LENGTH_8BIT) \|\| \
Kojto	122:f9eeca106725	610	((LENGTH) == SPI_CRC_LENGTH_16BIT))
Kojto	122:f9eeca106725	611
AnnaBridge	145:64910690c574	612	#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
Kojto	122:f9eeca106725	613
Kojto	122:f9eeca106725	614
Kojto	122:f9eeca106725	615	/**
Kojto	122:f9eeca106725	616	* @}
Kojto	122:f9eeca106725	617	*/
Kojto	122:f9eeca106725	618
Kojto	122:f9eeca106725	619	/* Include SPI HAL Extended module */
Kojto	122:f9eeca106725	620	#include "stm32l4xx_hal_spi_ex.h"
Kojto	122:f9eeca106725	621
Kojto	122:f9eeca106725	622	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	623	/** @addtogroup SPI_Exported_Functions
Kojto	122:f9eeca106725	624	* @{
Kojto	122:f9eeca106725	625	*/
Kojto	122:f9eeca106725	626
Kojto	122:f9eeca106725	627	/** @addtogroup SPI_Exported_Functions_Group1
Kojto	122:f9eeca106725	628	* @{
Kojto	122:f9eeca106725	629	*/
AnnaBridge	145:64910690c574	630	/* Initialization/de-initialization functions ********************************/
Kojto	122:f9eeca106725	631	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
AnnaBridge	145:64910690c574	632	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	633	void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	634	void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	635	/**
Kojto	122:f9eeca106725	636	* @}
Kojto	122:f9eeca106725	637	*/
Kojto	122:f9eeca106725	638
Kojto	122:f9eeca106725	639	/** @addtogroup SPI_Exported_Functions_Group2
Kojto	122:f9eeca106725	640	* @{
Kojto	122:f9eeca106725	641	*/
AnnaBridge	145:64910690c574	642	/* I/O operation functions ***************************************************/
Kojto	122:f9eeca106725	643	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
Kojto	122:f9eeca106725	644	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
AnnaBridge	145:64910690c574	645	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size,
AnnaBridge	145:64910690c574	646	uint32_t Timeout);
Kojto	122:f9eeca106725	647	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
Kojto	122:f9eeca106725	648	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
AnnaBridge	145:64910690c574	649	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
AnnaBridge	145:64910690c574	650	uint16_t Size);
Kojto	122:f9eeca106725	651	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
Kojto	122:f9eeca106725	652	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
AnnaBridge	145:64910690c574	653	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
AnnaBridge	145:64910690c574	654	uint16_t Size);
Kojto	122:f9eeca106725	655	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	656	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	657	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
AnnaBridge	145:64910690c574	658	/* Transfer Abort functions */
AnnaBridge	145:64910690c574	659	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
AnnaBridge	145:64910690c574	660	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	661
Kojto	122:f9eeca106725	662	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	663	void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	664	void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	665	void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	666	void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	667	void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	668	void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	669	void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	145:64910690c574	670	void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	671	/**
Kojto	122:f9eeca106725	672	* @}
Kojto	122:f9eeca106725	673	*/
Kojto	122:f9eeca106725	674
Kojto	122:f9eeca106725	675	/** @addtogroup SPI_Exported_Functions_Group3
Kojto	122:f9eeca106725	676	* @{
Kojto	122:f9eeca106725	677	*/
AnnaBridge	145:64910690c574	678	/* Peripheral State and Error functions ***************************************/
Kojto	122:f9eeca106725	679	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	680	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
Kojto	122:f9eeca106725	681	/**
Kojto	122:f9eeca106725	682	* @}
Kojto	122:f9eeca106725	683	*/
Kojto	122:f9eeca106725	684
Kojto	122:f9eeca106725	685	/**
Kojto	122:f9eeca106725	686	* @}
Kojto	122:f9eeca106725	687	*/
Kojto	122:f9eeca106725	688
Kojto	122:f9eeca106725	689	/**
Kojto	122:f9eeca106725	690	* @}
Kojto	122:f9eeca106725	691	*/
Kojto	122:f9eeca106725	692
Kojto	122:f9eeca106725	693	/**
Kojto	122:f9eeca106725	694	* @}
Kojto	122:f9eeca106725	695	*/
Kojto	122:f9eeca106725	696
Kojto	122:f9eeca106725	697	#ifdef __cplusplus
Kojto	122:f9eeca106725	698	}
Kojto	122:f9eeca106725	699	#endif
Kojto	122:f9eeca106725	700
Kojto	122:f9eeca106725	701	#endif /* __STM32L4xx_HAL_SPI_H */
Kojto	122:f9eeca106725	702
Kojto	122:f9eeca106725	703	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/