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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Parent:: 128:9bcdf88f62b0

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_hal_qspi.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.7.1
AnnaBridge	145:64910690c574	6	* @date 21-April-2017
Kojto	122:f9eeca106725	7	* @brief Header file of QSPI HAL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32L4xx_HAL_QSPI_H
Kojto	122:f9eeca106725	40	#define __STM32L4xx_HAL_QSPI_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
Kojto	122:f9eeca106725	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	47	#include "stm32l4xx_hal_def.h"
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** @addtogroup STM32L4xx_HAL_Driver
Kojto	122:f9eeca106725	50	* @{
Kojto	122:f9eeca106725	51	*/
Kojto	122:f9eeca106725	52
Kojto	122:f9eeca106725	53	/** @addtogroup QSPI
Kojto	122:f9eeca106725	54	* @{
Kojto	122:f9eeca106725	55	*/
Kojto	122:f9eeca106725	56
Kojto	122:f9eeca106725	57	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	58	/** @defgroup QSPI_Exported_Types QSPI Exported Types
Kojto	122:f9eeca106725	59	* @{
Kojto	122:f9eeca106725	60	*/
Kojto	122:f9eeca106725	61
Kojto	122:f9eeca106725	62	/**
Kojto	122:f9eeca106725	63	* @brief QSPI Init structure definition
Kojto	122:f9eeca106725	64	*/
Kojto	122:f9eeca106725	65	typedef struct
Kojto	122:f9eeca106725	66	{
Kojto	122:f9eeca106725	67	uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
Kojto	122:f9eeca106725	68	This parameter can be a number between 0 and 255 */
Kojto	122:f9eeca106725	69	uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
Kojto	122:f9eeca106725	70	This parameter can be a value between 1 and 16 */
Kojto	122:f9eeca106725	71	uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
Kojto	122:f9eeca106725	72	take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
Kojto	122:f9eeca106725	73	This parameter can be a value of @ref QSPI_SampleShifting */
Kojto	122:f9eeca106725	74	uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
Kojto	122:f9eeca106725	75	required to address the flash memory. The flash capacity can be up to 4GB
Kojto	122:f9eeca106725	76	(addressed using 32 bits) in indirect mode, but the addressable space in
Kojto	122:f9eeca106725	77	memory-mapped mode is limited to 256MB
Kojto	122:f9eeca106725	78	This parameter can be a number between 0 and 31 */
Kojto	122:f9eeca106725	79	uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
Kojto	122:f9eeca106725	80	of clock cycles which the chip select must remain high between commands.
Kojto	122:f9eeca106725	81	This parameter can be a value of @ref QSPI_ChipSelectHighTime */
Kojto	122:f9eeca106725	82	uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
Kojto	122:f9eeca106725	83	This parameter can be a value of @ref QSPI_ClockMode */
AnnaBridge	145:64910690c574	84	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| \
AnnaBridge	145:64910690c574	85	defined(STM32L443xx) \|\| defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx) \|\| \
AnnaBridge	145:64910690c574	86	defined(STM32L496xx) \|\| defined(STM32L4A6xx)
Kojto	122:f9eeca106725	87	uint32_t FlashID; /* Specifies the Flash which will be used,
Kojto	122:f9eeca106725	88	This parameter can be a value of @ref QSPI_Flash_Select */
Kojto	122:f9eeca106725	89	uint32_t DualFlash; /* Specifies the Dual Flash Mode State
Kojto	122:f9eeca106725	90	This parameter can be a value of @ref QSPI_DualFlash_Mode */
Kojto	122:f9eeca106725	91	#endif
Kojto	122:f9eeca106725	92	}QSPI_InitTypeDef;
Kojto	122:f9eeca106725	93
Kojto	122:f9eeca106725	94	/**
Kojto	122:f9eeca106725	95	* @brief HAL QSPI State structures definition
Kojto	122:f9eeca106725	96	*/
Kojto	122:f9eeca106725	97	typedef enum
Kojto	122:f9eeca106725	98	{
Kojto	122:f9eeca106725	99	HAL_QSPI_STATE_RESET = 0x00, /!< Peripheral not initialized /
Kojto	122:f9eeca106725	100	HAL_QSPI_STATE_READY = 0x01, /!< Peripheral initialized and ready for use /
Kojto	122:f9eeca106725	101	HAL_QSPI_STATE_BUSY = 0x02, /!< Peripheral in indirect mode and busy /
Kojto	122:f9eeca106725	102	HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /!< Peripheral in indirect mode with transmission ongoing /
Kojto	122:f9eeca106725	103	HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /!< Peripheral in indirect mode with reception ongoing /
Kojto	122:f9eeca106725	104	HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /!< Peripheral in auto polling mode ongoing /
Kojto	122:f9eeca106725	105	HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /!< Peripheral in memory mapped mode ongoing /
Kojto	122:f9eeca106725	106	HAL_QSPI_STATE_ABORT = 0x08, /!< Peripheral with abort request ongoing /
Kojto	122:f9eeca106725	107	HAL_QSPI_STATE_ERROR = 0x04 /!< Peripheral in error /
Kojto	122:f9eeca106725	108	}HAL_QSPI_StateTypeDef;
Kojto	122:f9eeca106725	109
Kojto	122:f9eeca106725	110	/**
Kojto	122:f9eeca106725	111	* @brief QSPI Handle Structure definition
Kojto	122:f9eeca106725	112	*/
Kojto	122:f9eeca106725	113	typedef struct
Kojto	122:f9eeca106725	114	{
Kojto	122:f9eeca106725	115	QUADSPI_TypeDef Instance; / QSPI registers base address */
Kojto	122:f9eeca106725	116	QSPI_InitTypeDef Init; /* QSPI communication parameters */
Kojto	122:f9eeca106725	117	uint8_t pTxBuffPtr; / Pointer to QSPI Tx transfer Buffer */
AnnaBridge	145:64910690c574	118	__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
AnnaBridge	145:64910690c574	119	__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
Kojto	122:f9eeca106725	120	uint8_t pRxBuffPtr; / Pointer to QSPI Rx transfer Buffer */
AnnaBridge	145:64910690c574	121	__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
AnnaBridge	145:64910690c574	122	__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
Kojto	122:f9eeca106725	123	DMA_HandleTypeDef hdma; / QSPI Rx/Tx DMA Handle parameters */
Kojto	122:f9eeca106725	124	__IO HAL_LockTypeDef Lock; /* Locking object */
Kojto	122:f9eeca106725	125	__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
Kojto	122:f9eeca106725	126	__IO uint32_t ErrorCode; /* QSPI Error code */
Kojto	122:f9eeca106725	127	uint32_t Timeout; /* Timeout for the QSPI memory access */
Kojto	122:f9eeca106725	128	}QSPI_HandleTypeDef;
Kojto	122:f9eeca106725	129
Kojto	122:f9eeca106725	130	/**
Kojto	122:f9eeca106725	131	* @brief QSPI Command structure definition
Kojto	122:f9eeca106725	132	*/
Kojto	122:f9eeca106725	133	typedef struct
Kojto	122:f9eeca106725	134	{
Kojto	122:f9eeca106725	135	uint32_t Instruction; /* Specifies the Instruction to be sent
Kojto	122:f9eeca106725	136	This parameter can be a value (8-bit) between 0x00 and 0xFF */
Kojto	122:f9eeca106725	137	uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
Kojto	122:f9eeca106725	138	This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
Kojto	122:f9eeca106725	139	uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
Kojto	122:f9eeca106725	140	This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
Kojto	122:f9eeca106725	141	uint32_t AddressSize; /* Specifies the Address Size
Kojto	122:f9eeca106725	142	This parameter can be a value of @ref QSPI_AddressSize */
Kojto	122:f9eeca106725	143	uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
Kojto	122:f9eeca106725	144	This parameter can be a value of @ref QSPI_AlternateBytesSize */
Kojto	122:f9eeca106725	145	uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
Kojto	122:f9eeca106725	146	This parameter can be a number between 0 and 31 */
Kojto	122:f9eeca106725	147	uint32_t InstructionMode; /* Specifies the Instruction Mode
Kojto	122:f9eeca106725	148	This parameter can be a value of @ref QSPI_InstructionMode */
Kojto	122:f9eeca106725	149	uint32_t AddressMode; /* Specifies the Address Mode
Kojto	122:f9eeca106725	150	This parameter can be a value of @ref QSPI_AddressMode */
Kojto	122:f9eeca106725	151	uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
Kojto	122:f9eeca106725	152	This parameter can be a value of @ref QSPI_AlternateBytesMode */
Kojto	122:f9eeca106725	153	uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
Kojto	122:f9eeca106725	154	This parameter can be a value of @ref QSPI_DataMode */
Kojto	122:f9eeca106725	155	uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
Kojto	122:f9eeca106725	156	This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
Kojto	122:f9eeca106725	157	until end of memory)*/
Kojto	122:f9eeca106725	158	uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
Kojto	122:f9eeca106725	159	This parameter can be a value of @ref QSPI_DdrMode */
Kojto	122:f9eeca106725	160	uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
Kojto	122:f9eeca106725	161	system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
Kojto	122:f9eeca106725	162	This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
Kojto	122:f9eeca106725	163	uint32_t SIOOMode; /* Specifies the send instruction only once mode
Kojto	122:f9eeca106725	164	This parameter can be a value of @ref QSPI_SIOOMode */
Kojto	122:f9eeca106725	165	}QSPI_CommandTypeDef;
Kojto	122:f9eeca106725	166
Kojto	122:f9eeca106725	167	/**
Kojto	122:f9eeca106725	168	* @brief QSPI Auto Polling mode configuration structure definition
Kojto	122:f9eeca106725	169	*/
Kojto	122:f9eeca106725	170	typedef struct
Kojto	122:f9eeca106725	171	{
Kojto	122:f9eeca106725	172	uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
Kojto	122:f9eeca106725	173	This parameter can be any value between 0 and 0xFFFFFFFF */
Kojto	122:f9eeca106725	174	uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
Kojto	122:f9eeca106725	175	This parameter can be any value between 0 and 0xFFFFFFFF */
Kojto	122:f9eeca106725	176	uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
Kojto	122:f9eeca106725	177	This parameter can be any value between 0 and 0xFFFF */
Kojto	122:f9eeca106725	178	uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
Kojto	122:f9eeca106725	179	This parameter can be any value between 1 and 4 */
Kojto	122:f9eeca106725	180	uint32_t MatchMode; /* Specifies the method used for determining a match.
Kojto	122:f9eeca106725	181	This parameter can be a value of @ref QSPI_MatchMode */
Kojto	122:f9eeca106725	182	uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
Kojto	122:f9eeca106725	183	This parameter can be a value of @ref QSPI_AutomaticStop */
Kojto	122:f9eeca106725	184	}QSPI_AutoPollingTypeDef;
Kojto	122:f9eeca106725	185
Kojto	122:f9eeca106725	186	/**
Kojto	122:f9eeca106725	187	* @brief QSPI Memory Mapped mode configuration structure definition
Kojto	122:f9eeca106725	188	*/
Kojto	122:f9eeca106725	189	typedef struct
Kojto	122:f9eeca106725	190	{
Kojto	122:f9eeca106725	191	uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
Kojto	122:f9eeca106725	192	This parameter can be any value between 0 and 0xFFFF */
Kojto	122:f9eeca106725	193	uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
Kojto	122:f9eeca106725	194	This parameter can be a value of @ref QSPI_TimeOutActivation */
Kojto	122:f9eeca106725	195	}QSPI_MemoryMappedTypeDef;
Kojto	122:f9eeca106725	196
Kojto	122:f9eeca106725	197	/**
Kojto	122:f9eeca106725	198	* @}
Kojto	122:f9eeca106725	199	*/
Kojto	122:f9eeca106725	200
Kojto	122:f9eeca106725	201	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	202	/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
Kojto	122:f9eeca106725	203	* @{
Kojto	122:f9eeca106725	204	*/
Kojto	122:f9eeca106725	205
Kojto	122:f9eeca106725	206	/** @defgroup QSPI_ErrorCode QSPI Error Code
Kojto	122:f9eeca106725	207	* @{
Kojto	122:f9eeca106725	208	*/
Kojto	122:f9eeca106725	209	#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /!< No error /
Kojto	122:f9eeca106725	210	#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /!< Timeout error /
Kojto	122:f9eeca106725	211	#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /!< Transfer error /
Kojto	122:f9eeca106725	212	#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /!< DMA transfer error /
Kojto	122:f9eeca106725	213	#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /!< Invalid parameters error /
Kojto	122:f9eeca106725	214	/**
Kojto	122:f9eeca106725	215	* @}
Kojto	122:f9eeca106725	216	*/
Kojto	122:f9eeca106725	217
Kojto	122:f9eeca106725	218	/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
Kojto	122:f9eeca106725	219	* @{
Kojto	122:f9eeca106725	220	*/
Kojto	122:f9eeca106725	221	#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /!<No clock cycle shift to sample data/
Kojto	122:f9eeca106725	222	#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /!<1/2 clock cycle shift to sample data/
Kojto	122:f9eeca106725	223	/**
Kojto	122:f9eeca106725	224	* @}
Kojto	122:f9eeca106725	225	*/
Kojto	122:f9eeca106725	226
Kojto	122:f9eeca106725	227	/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
Kojto	122:f9eeca106725	228	* @{
Kojto	122:f9eeca106725	229	*/
Kojto	122:f9eeca106725	230	#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /!<nCS stay high for at least 1 clock cycle between commands/
Kojto	122:f9eeca106725	231	#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /!<nCS stay high for at least 2 clock cycles between commands/
Kojto	122:f9eeca106725	232	#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 3 clock cycles between commands/
Kojto	122:f9eeca106725	233	#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 \| QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 4 clock cycles between commands/
Kojto	122:f9eeca106725	234	#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /!<nCS stay high for at least 5 clock cycles between commands/
Kojto	122:f9eeca106725	235	#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 \| QUADSPI_DCR_CSHT_0) /!<nCS stay high for at least 6 clock cycles between commands/
Kojto	122:f9eeca106725	236	#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 \| QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 7 clock cycles between commands/
Kojto	122:f9eeca106725	237	#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /!<nCS stay high for at least 8 clock cycles between commands/
Kojto	122:f9eeca106725	238	/**
Kojto	122:f9eeca106725	239	* @}
Kojto	122:f9eeca106725	240	*/
Kojto	122:f9eeca106725	241
Kojto	122:f9eeca106725	242	/** @defgroup QSPI_ClockMode QSPI Clock Mode
Kojto	122:f9eeca106725	243	* @{
Kojto	122:f9eeca106725	244	*/
Kojto	122:f9eeca106725	245	#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /!<Clk stays low while nCS is released/
Kojto	122:f9eeca106725	246	#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /!<Clk goes high while nCS is released/
Kojto	122:f9eeca106725	247	/**
Kojto	122:f9eeca106725	248	* @}
Kojto	122:f9eeca106725	249	*/
Kojto	122:f9eeca106725	250
AnnaBridge	145:64910690c574	251	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| \
AnnaBridge	145:64910690c574	252	defined(STM32L443xx) \|\| defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx) \|\| \
AnnaBridge	145:64910690c574	253	defined(STM32L496xx) \|\| defined(STM32L4A6xx)
Kojto	122:f9eeca106725	254	/** @defgroup QSPI_Flash_Select QSPI Flash Select
Kojto	122:f9eeca106725	255	* @{
Kojto	122:f9eeca106725	256	*/
Kojto	122:f9eeca106725	257	#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /!<FLASH 1 selected/
Kojto	122:f9eeca106725	258	#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /!<FLASH 2 selected/
Kojto	122:f9eeca106725	259	/**
Kojto	122:f9eeca106725	260	* @}
Kojto	122:f9eeca106725	261	*/
Kojto	122:f9eeca106725	262
Kojto	122:f9eeca106725	263	/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
Kojto	122:f9eeca106725	264	* @{
Kojto	122:f9eeca106725	265	*/
Kojto	122:f9eeca106725	266	#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /!<Dual-flash mode enabled/
Kojto	122:f9eeca106725	267	#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /!<Dual-flash mode disabled/
Kojto	122:f9eeca106725	268	/**
Kojto	122:f9eeca106725	269	* @}
Kojto	122:f9eeca106725	270	*/
Kojto	122:f9eeca106725	271	#endif
Kojto	122:f9eeca106725	272
Kojto	122:f9eeca106725	273	/** @defgroup QSPI_AddressSize QSPI Address Size
Kojto	122:f9eeca106725	274	* @{
Kojto	122:f9eeca106725	275	*/
Kojto	122:f9eeca106725	276	#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /!<8-bit address/
Kojto	122:f9eeca106725	277	#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /!<16-bit address/
Kojto	122:f9eeca106725	278	#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /!<24-bit address/
Kojto	122:f9eeca106725	279	#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /!<32-bit address/
Kojto	122:f9eeca106725	280	/**
Kojto	122:f9eeca106725	281	* @}
Kojto	122:f9eeca106725	282	*/
Kojto	122:f9eeca106725	283
Kojto	122:f9eeca106725	284	/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
Kojto	122:f9eeca106725	285	* @{
Kojto	122:f9eeca106725	286	*/
Kojto	122:f9eeca106725	287	#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /!<8-bit alternate bytes/
Kojto	122:f9eeca106725	288	#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /!<16-bit alternate bytes/
Kojto	122:f9eeca106725	289	#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /!<24-bit alternate bytes/
Kojto	122:f9eeca106725	290	#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /!<32-bit alternate bytes/
Kojto	122:f9eeca106725	291	/**
Kojto	122:f9eeca106725	292	* @}
Kojto	122:f9eeca106725	293	*/
Kojto	122:f9eeca106725	294
Kojto	122:f9eeca106725	295	/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
Kojto	122:f9eeca106725	296	* @{
Kojto	122:f9eeca106725	297	*/
Kojto	122:f9eeca106725	298	#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /!<No instruction/
Kojto	122:f9eeca106725	299	#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /!<Instruction on a single line/
Kojto	122:f9eeca106725	300	#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /!<Instruction on two lines/
Kojto	122:f9eeca106725	301	#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /!<Instruction on four lines/
Kojto	122:f9eeca106725	302	/**
Kojto	122:f9eeca106725	303	* @}
Kojto	122:f9eeca106725	304	*/
Kojto	122:f9eeca106725	305
Kojto	122:f9eeca106725	306	/** @defgroup QSPI_AddressMode QSPI Address Mode
Kojto	122:f9eeca106725	307	* @{
Kojto	122:f9eeca106725	308	*/
Kojto	122:f9eeca106725	309	#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /!<No address/
Kojto	122:f9eeca106725	310	#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /!<Address on a single line/
Kojto	122:f9eeca106725	311	#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /!<Address on two lines/
Kojto	122:f9eeca106725	312	#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /!<Address on four lines/
Kojto	122:f9eeca106725	313	/**
Kojto	122:f9eeca106725	314	* @}
Kojto	122:f9eeca106725	315	*/
Kojto	122:f9eeca106725	316
Kojto	122:f9eeca106725	317	/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
Kojto	122:f9eeca106725	318	* @{
Kojto	122:f9eeca106725	319	*/
Kojto	122:f9eeca106725	320	#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /!<No alternate bytes/
Kojto	122:f9eeca106725	321	#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /!<Alternate bytes on a single line/
Kojto	122:f9eeca106725	322	#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /!<Alternate bytes on two lines/
Kojto	122:f9eeca106725	323	#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /!<Alternate bytes on four lines/
Kojto	122:f9eeca106725	324	/**
Kojto	122:f9eeca106725	325	* @}
Kojto	122:f9eeca106725	326	*/
Kojto	122:f9eeca106725	327
Kojto	122:f9eeca106725	328	/** @defgroup QSPI_DataMode QSPI Data Mode
Kojto	122:f9eeca106725	329	* @{
Kojto	122:f9eeca106725	330	*/
Kojto	122:f9eeca106725	331	#define QSPI_DATA_NONE ((uint32_t)0X00000000) /!<No data/
Kojto	122:f9eeca106725	332	#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /!<Data on a single line/
Kojto	122:f9eeca106725	333	#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /!<Data on two lines/
Kojto	122:f9eeca106725	334	#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /!<Data on four lines/
Kojto	122:f9eeca106725	335	/**
Kojto	122:f9eeca106725	336	* @}
Kojto	122:f9eeca106725	337	*/
Kojto	122:f9eeca106725	338
Kojto	122:f9eeca106725	339	/** @defgroup QSPI_DdrMode QSPI DDR Mode
Kojto	122:f9eeca106725	340	* @{
Kojto	122:f9eeca106725	341	*/
Kojto	122:f9eeca106725	342	#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /!<Double data rate mode disabled/
Kojto	122:f9eeca106725	343	#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /!<Double data rate mode enabled/
Kojto	122:f9eeca106725	344	/**
Kojto	122:f9eeca106725	345	* @}
Kojto	122:f9eeca106725	346	*/
Kojto	122:f9eeca106725	347
Kojto	122:f9eeca106725	348	/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
Kojto	122:f9eeca106725	349	* @{
Kojto	122:f9eeca106725	350	*/
Kojto	122:f9eeca106725	351	#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /!<Delay the data output using analog delay in DDR mode/
AnnaBridge	145:64910690c574	352	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| \
AnnaBridge	145:64910690c574	353	defined(STM32L443xx) \|\| defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx) \|\| \
AnnaBridge	145:64910690c574	354	defined(STM32L496xx) \|\| defined(STM32L4A6xx)
Kojto	122:f9eeca106725	355	#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /!<Delay the data output by 1/2 clock cycle in DDR mode/
Kojto	122:f9eeca106725	356	#endif
Kojto	122:f9eeca106725	357	/**
Kojto	122:f9eeca106725	358	* @}
Kojto	122:f9eeca106725	359	*/
Kojto	122:f9eeca106725	360
Kojto	122:f9eeca106725	361	/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
Kojto	122:f9eeca106725	362	* @{
Kojto	122:f9eeca106725	363	*/
Kojto	122:f9eeca106725	364	#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /!<Send instruction on every transaction/
Kojto	122:f9eeca106725	365	#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /!<Send instruction only for the first command/
Kojto	122:f9eeca106725	366	/**
Kojto	122:f9eeca106725	367	* @}
Kojto	122:f9eeca106725	368	*/
Kojto	122:f9eeca106725	369
Kojto	122:f9eeca106725	370	/** @defgroup QSPI_MatchMode QSPI Match Mode
Kojto	122:f9eeca106725	371	* @{
Kojto	122:f9eeca106725	372	*/
Kojto	122:f9eeca106725	373	#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /!<AND match mode between unmasked bits/
Kojto	122:f9eeca106725	374	#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /!<OR match mode between unmasked bits/
Kojto	122:f9eeca106725	375	/**
Kojto	122:f9eeca106725	376	* @}
Kojto	122:f9eeca106725	377	*/
Kojto	122:f9eeca106725	378
Kojto	122:f9eeca106725	379	/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
Kojto	122:f9eeca106725	380	* @{
Kojto	122:f9eeca106725	381	*/
Kojto	122:f9eeca106725	382	#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /!<AutoPolling stops only with abort or QSPI disabling/
Kojto	122:f9eeca106725	383	#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /!<AutoPolling stops as soon as there is a match/
Kojto	122:f9eeca106725	384	/**
Kojto	122:f9eeca106725	385	* @}
Kojto	122:f9eeca106725	386	*/
Kojto	122:f9eeca106725	387
Kojto	122:f9eeca106725	388	/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
Kojto	122:f9eeca106725	389	* @{
Kojto	122:f9eeca106725	390	*/
Kojto	122:f9eeca106725	391	#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /!<Timeout counter disabled, nCS remains active/
Kojto	122:f9eeca106725	392	#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /!<Timeout counter enabled, nCS released when timeout expires/
Kojto	122:f9eeca106725	393	/**
Kojto	122:f9eeca106725	394	* @}
Kojto	122:f9eeca106725	395	*/
Kojto	122:f9eeca106725	396
Kojto	122:f9eeca106725	397	/** @defgroup QSPI_Flags QSPI Flags
Kojto	122:f9eeca106725	398	* @{
Kojto	122:f9eeca106725	399	*/
Kojto	122:f9eeca106725	400	#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /!<Busy flag: operation is ongoing/
Kojto	122:f9eeca106725	401	#define QSPI_FLAG_TO QUADSPI_SR_TOF /!<Timeout flag: timeout occurs in memory-mapped mode/
Kojto	122:f9eeca106725	402	#define QSPI_FLAG_SM QUADSPI_SR_SMF /!<Status match flag: received data matches in autopolling mode/
Kojto	122:f9eeca106725	403	#define QSPI_FLAG_FT QUADSPI_SR_FTF /!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete/
Kojto	122:f9eeca106725	404	#define QSPI_FLAG_TC QUADSPI_SR_TCF /!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted/
Kojto	122:f9eeca106725	405	#define QSPI_FLAG_TE QUADSPI_SR_TEF /!<Transfer error flag: invalid address is being accessed/
Kojto	122:f9eeca106725	406	/**
Kojto	122:f9eeca106725	407	* @}
Kojto	122:f9eeca106725	408	*/
Kojto	122:f9eeca106725	409
Kojto	122:f9eeca106725	410	/** @defgroup QSPI_Interrupts QSPI Interrupts
Kojto	122:f9eeca106725	411	* @{
Kojto	122:f9eeca106725	412	*/
Kojto	122:f9eeca106725	413	#define QSPI_IT_TO QUADSPI_CR_TOIE /!<Interrupt on the timeout flag/
Kojto	122:f9eeca106725	414	#define QSPI_IT_SM QUADSPI_CR_SMIE /!<Interrupt on the status match flag/
Kojto	122:f9eeca106725	415	#define QSPI_IT_FT QUADSPI_CR_FTIE /!<Interrupt on the fifo threshold flag/
Kojto	122:f9eeca106725	416	#define QSPI_IT_TC QUADSPI_CR_TCIE /!<Interrupt on the transfer complete flag/
Kojto	122:f9eeca106725	417	#define QSPI_IT_TE QUADSPI_CR_TEIE /!<Interrupt on the transfer error flag/
Kojto	122:f9eeca106725	418	/**
Kojto	122:f9eeca106725	419	* @}
Kojto	122:f9eeca106725	420	*/
Kojto	122:f9eeca106725	421
Kojto	122:f9eeca106725	422	/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
Kojto	122:f9eeca106725	423	* @brief QSPI Timeout definition
Kojto	122:f9eeca106725	424	* @{
Kojto	122:f9eeca106725	425	*/
Kojto	122:f9eeca106725	426	#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
Kojto	122:f9eeca106725	427	/**
Kojto	122:f9eeca106725	428	* @}
Kojto	122:f9eeca106725	429	*/
Kojto	122:f9eeca106725	430
Kojto	122:f9eeca106725	431	/**
Kojto	122:f9eeca106725	432	* @}
Kojto	122:f9eeca106725	433	*/
Kojto	122:f9eeca106725	434
Kojto	122:f9eeca106725	435	/* Exported macros -----------------------------------------------------------*/
Kojto	122:f9eeca106725	436	/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
Kojto	122:f9eeca106725	437	* @{
Kojto	122:f9eeca106725	438	*/
Kojto	122:f9eeca106725	439	/** @brief Reset QSPI handle state.
Kojto	122:f9eeca106725	440	* @param __HANDLE__: QSPI handle.
Kojto	122:f9eeca106725	441	* @retval None
Kojto	122:f9eeca106725	442	*/
Kojto	122:f9eeca106725	443	#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
Kojto	122:f9eeca106725	444
Kojto	122:f9eeca106725	445	/** @brief Enable the QSPI peripheral.
Kojto	122:f9eeca106725	446	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	122:f9eeca106725	447	* @retval None
Kojto	122:f9eeca106725	448	*/
Kojto	122:f9eeca106725	449	#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Kojto	122:f9eeca106725	450
Kojto	122:f9eeca106725	451	/** @brief Disable the QSPI peripheral.
Kojto	122:f9eeca106725	452	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	122:f9eeca106725	453	* @retval None
Kojto	122:f9eeca106725	454	*/
Kojto	122:f9eeca106725	455	#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Kojto	122:f9eeca106725	456
Kojto	122:f9eeca106725	457	/** @brief Enable the specified QSPI interrupt.
Kojto	122:f9eeca106725	458	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	122:f9eeca106725	459	* @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
Kojto	122:f9eeca106725	460	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	461	* @arg QSPI_IT_TO: QSPI Timeout interrupt
Kojto	122:f9eeca106725	462	* @arg QSPI_IT_SM: QSPI Status match interrupt
Kojto	122:f9eeca106725	463	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
Kojto	122:f9eeca106725	464	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
Kojto	122:f9eeca106725	465	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
Kojto	122:f9eeca106725	466	* @retval None
Kojto	122:f9eeca106725	467	*/
Kojto	122:f9eeca106725	468	#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Kojto	122:f9eeca106725	469
Kojto	122:f9eeca106725	470
Kojto	122:f9eeca106725	471	/** @brief Disable the specified QSPI interrupt.
Kojto	122:f9eeca106725	472	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	122:f9eeca106725	473	* @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
Kojto	122:f9eeca106725	474	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	475	* @arg QSPI_IT_TO: QSPI Timeout interrupt
Kojto	122:f9eeca106725	476	* @arg QSPI_IT_SM: QSPI Status match interrupt
Kojto	122:f9eeca106725	477	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
Kojto	122:f9eeca106725	478	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
Kojto	122:f9eeca106725	479	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
Kojto	122:f9eeca106725	480	* @retval None
Kojto	122:f9eeca106725	481	*/
Kojto	122:f9eeca106725	482	#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Kojto	122:f9eeca106725	483
Kojto	122:f9eeca106725	484	/** @brief Check whether the specified QSPI interrupt source is enabled or not.
Kojto	122:f9eeca106725	485	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	122:f9eeca106725	486	* @param __INTERRUPT__: specifies the QSPI interrupt source to check.
Kojto	122:f9eeca106725	487	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	488	* @arg QSPI_IT_TO: QSPI Timeout interrupt
Kojto	122:f9eeca106725	489	* @arg QSPI_IT_SM: QSPI Status match interrupt
Kojto	122:f9eeca106725	490	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
Kojto	122:f9eeca106725	491	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
Kojto	122:f9eeca106725	492	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
Kojto	122:f9eeca106725	493	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	122:f9eeca106725	494	*/
Kojto	122:f9eeca106725	495	#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	122:f9eeca106725	496
Kojto	122:f9eeca106725	497	/**
Kojto	122:f9eeca106725	498	* @brief Check whether the selected QSPI flag is set or not.
Kojto	122:f9eeca106725	499	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	122:f9eeca106725	500	* @param __FLAG__: specifies the QSPI flag to check.
Kojto	122:f9eeca106725	501	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	502	* @arg QSPI_FLAG_BUSY: QSPI Busy flag
Kojto	122:f9eeca106725	503	* @arg QSPI_FLAG_TO: QSPI Timeout flag
Kojto	122:f9eeca106725	504	* @arg QSPI_FLAG_SM: QSPI Status match flag
Kojto	122:f9eeca106725	505	* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
Kojto	122:f9eeca106725	506	* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
Kojto	122:f9eeca106725	507	* @arg QSPI_FLAG_TE: QSPI Transfer error flag
Kojto	122:f9eeca106725	508	* @retval None
Kojto	122:f9eeca106725	509	*/
Kojto	122:f9eeca106725	510	#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
Kojto	122:f9eeca106725	511
Kojto	122:f9eeca106725	512	/** @brief Clears the specified QSPI's flag status.
Kojto	122:f9eeca106725	513	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	122:f9eeca106725	514	* @param __FLAG__: specifies the QSPI clear register flag that needs to be set
Kojto	122:f9eeca106725	515	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	516	* @arg QSPI_FLAG_TO: QSPI Timeout flag
Kojto	122:f9eeca106725	517	* @arg QSPI_FLAG_SM: QSPI Status match flag
Kojto	122:f9eeca106725	518	* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
Kojto	122:f9eeca106725	519	* @arg QSPI_FLAG_TE: QSPI Transfer error flag
Kojto	122:f9eeca106725	520	* @retval None
Kojto	122:f9eeca106725	521	*/
Kojto	122:f9eeca106725	522	#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Kojto	122:f9eeca106725	523	/**
Kojto	122:f9eeca106725	524	* @}
Kojto	122:f9eeca106725	525	*/
Kojto	122:f9eeca106725	526
Kojto	122:f9eeca106725	527	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	528	/** @addtogroup QSPI_Exported_Functions
Kojto	122:f9eeca106725	529	* @{
Kojto	122:f9eeca106725	530	*/
Kojto	122:f9eeca106725	531	/* Initialization/de-initialization functions ********************************/
Kojto	122:f9eeca106725	532	HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	533	HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	534	void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	535	void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	536
Kojto	122:f9eeca106725	537	/* IO operation functions *****************************************************/
Kojto	122:f9eeca106725	538	/* QSPI IRQ handler method */
Kojto	122:f9eeca106725	539	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	540
Kojto	122:f9eeca106725	541	/* QSPI indirect mode */
Kojto	122:f9eeca106725	542	HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout);
Kojto	122:f9eeca106725	543	HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout);
Kojto	122:f9eeca106725	544	HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout);
Kojto	122:f9eeca106725	545	HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd);
Kojto	122:f9eeca106725	546	HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef hqspi, uint8_t pData);
Kojto	122:f9eeca106725	547	HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef hqspi, uint8_t pData);
Kojto	122:f9eeca106725	548	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef hqspi, uint8_t pData);
Kojto	122:f9eeca106725	549	HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef hqspi, uint8_t pData);
Kojto	122:f9eeca106725	550
Kojto	122:f9eeca106725	551	/* QSPI status flag polling mode */
Kojto	122:f9eeca106725	552	HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
Kojto	122:f9eeca106725	553	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg);
Kojto	122:f9eeca106725	554
Kojto	122:f9eeca106725	555	/* QSPI memory-mapped mode */
Kojto	122:f9eeca106725	556	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg);
Kojto	122:f9eeca106725	557
Kojto	122:f9eeca106725	558	/* Callback functions in non-blocking modes ***********************************/
Kojto	122:f9eeca106725	559	void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	560	void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	561	void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	562
Kojto	122:f9eeca106725	563	/* QSPI indirect mode */
Kojto	122:f9eeca106725	564	void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	565	void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	566	void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	567	void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	568	void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	569
Kojto	122:f9eeca106725	570	/* QSPI status flag polling mode */
Kojto	122:f9eeca106725	571	void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	572
Kojto	122:f9eeca106725	573	/* QSPI memory-mapped mode */
Kojto	122:f9eeca106725	574	void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	575
Kojto	122:f9eeca106725	576	/* Peripheral Control and State functions ************************************/
Kojto	122:f9eeca106725	577	HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	578	uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	579	HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	580	HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	581	void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
Kojto	122:f9eeca106725	582	HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
Kojto	122:f9eeca106725	583	uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	584	/**
Kojto	122:f9eeca106725	585	* @}
Kojto	122:f9eeca106725	586	*/
Kojto	122:f9eeca106725	587	/* End of exported functions -------------------------------------------------*/
Kojto	122:f9eeca106725	588
Kojto	122:f9eeca106725	589	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	590	/** @defgroup QSPI_Private_Macros QSPI Private Macros
Kojto	122:f9eeca106725	591	* @{
Kojto	122:f9eeca106725	592	*/
Kojto	122:f9eeca106725	593	#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
Kojto	122:f9eeca106725	594
Kojto	122:f9eeca106725	595	#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))
Kojto	122:f9eeca106725	596
Kojto	122:f9eeca106725	597	#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) \|\| \
Kojto	122:f9eeca106725	598	((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
Kojto	122:f9eeca106725	599
Kojto	122:f9eeca106725	600	#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
Kojto	122:f9eeca106725	601
Kojto	122:f9eeca106725	602	#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) \|\| \
Kojto	122:f9eeca106725	603	((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) \|\| \
Kojto	122:f9eeca106725	604	((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) \|\| \
Kojto	122:f9eeca106725	605	((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) \|\| \
Kojto	122:f9eeca106725	606	((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) \|\| \
Kojto	122:f9eeca106725	607	((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) \|\| \
Kojto	122:f9eeca106725	608	((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) \|\| \
Kojto	122:f9eeca106725	609	((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
Kojto	122:f9eeca106725	610
Kojto	122:f9eeca106725	611	#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) \|\| \
Kojto	122:f9eeca106725	612	((CLKMODE) == QSPI_CLOCK_MODE_3))
Kojto	122:f9eeca106725	613
AnnaBridge	145:64910690c574	614	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| \
AnnaBridge	145:64910690c574	615	defined(STM32L443xx) \|\| defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx) \|\| \
AnnaBridge	145:64910690c574	616	defined(STM32L496xx) \|\| defined(STM32L4A6xx)
Kojto	122:f9eeca106725	617	#define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) \|\| \
Kojto	122:f9eeca106725	618	((FLASH) == QSPI_FLASH_ID_2))
Kojto	122:f9eeca106725	619
Kojto	122:f9eeca106725	620	#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) \|\| \
Kojto	122:f9eeca106725	621	((MODE) == QSPI_DUALFLASH_DISABLE))
Kojto	122:f9eeca106725	622	#endif
Kojto	122:f9eeca106725	623
Kojto	122:f9eeca106725	624	#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
Kojto	122:f9eeca106725	625
Kojto	122:f9eeca106725	626	#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) \|\| \
Kojto	122:f9eeca106725	627	((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) \|\| \
Kojto	122:f9eeca106725	628	((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) \|\| \
Kojto	122:f9eeca106725	629	((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
Kojto	122:f9eeca106725	630
Kojto	122:f9eeca106725	631	#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) \|\| \
Kojto	122:f9eeca106725	632	((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) \|\| \
Kojto	122:f9eeca106725	633	((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) \|\| \
Kojto	122:f9eeca106725	634	((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
Kojto	122:f9eeca106725	635
Kojto	122:f9eeca106725	636	#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
Kojto	122:f9eeca106725	637
Kojto	122:f9eeca106725	638	#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) \|\| \
Kojto	122:f9eeca106725	639	((MODE) == QSPI_INSTRUCTION_1_LINE) \|\| \
Kojto	122:f9eeca106725	640	((MODE) == QSPI_INSTRUCTION_2_LINES) \|\| \
Kojto	122:f9eeca106725	641	((MODE) == QSPI_INSTRUCTION_4_LINES))
Kojto	122:f9eeca106725	642
Kojto	122:f9eeca106725	643	#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) \|\| \
Kojto	122:f9eeca106725	644	((MODE) == QSPI_ADDRESS_1_LINE) \|\| \
Kojto	122:f9eeca106725	645	((MODE) == QSPI_ADDRESS_2_LINES) \|\| \
Kojto	122:f9eeca106725	646	((MODE) == QSPI_ADDRESS_4_LINES))
Kojto	122:f9eeca106725	647
Kojto	122:f9eeca106725	648	#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) \|\| \
Kojto	122:f9eeca106725	649	((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) \|\| \
Kojto	122:f9eeca106725	650	((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) \|\| \
Kojto	122:f9eeca106725	651	((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
Kojto	122:f9eeca106725	652
Kojto	122:f9eeca106725	653	#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) \|\| \
Kojto	122:f9eeca106725	654	((MODE) == QSPI_DATA_1_LINE) \|\| \
Kojto	122:f9eeca106725	655	((MODE) == QSPI_DATA_2_LINES) \|\| \
Kojto	122:f9eeca106725	656	((MODE) == QSPI_DATA_4_LINES))
Kojto	122:f9eeca106725	657
Kojto	122:f9eeca106725	658	#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) \|\| \
Kojto	122:f9eeca106725	659	((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
Kojto	122:f9eeca106725	660
AnnaBridge	145:64910690c574	661	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| \
AnnaBridge	145:64910690c574	662	defined(STM32L443xx) \|\| defined(STM32L451xx) \|\| defined(STM32L452xx) \|\| defined(STM32L462xx) \|\| \
AnnaBridge	145:64910690c574	663	defined(STM32L496xx) \|\| defined(STM32L4A6xx)
Kojto	122:f9eeca106725	664	#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) \|\| \
Kojto	122:f9eeca106725	665	((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
Kojto	122:f9eeca106725	666	#else
Kojto	122:f9eeca106725	667	#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
Kojto	122:f9eeca106725	668	#endif
Kojto	122:f9eeca106725	669
Kojto	122:f9eeca106725	670	#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) \|\| \
Kojto	122:f9eeca106725	671	((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
Kojto	122:f9eeca106725	672
Kojto	122:f9eeca106725	673	#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
Kojto	122:f9eeca106725	674
Kojto	122:f9eeca106725	675	#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
Kojto	122:f9eeca106725	676
Kojto	122:f9eeca106725	677	#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) \|\| \
Kojto	122:f9eeca106725	678	((MODE) == QSPI_MATCH_MODE_OR))
Kojto	122:f9eeca106725	679
Kojto	122:f9eeca106725	680	#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) \|\| \
Kojto	122:f9eeca106725	681	((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
Kojto	122:f9eeca106725	682
Kojto	122:f9eeca106725	683	#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) \|\| \
Kojto	122:f9eeca106725	684	((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
Kojto	122:f9eeca106725	685
Kojto	122:f9eeca106725	686	#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
Kojto	122:f9eeca106725	687	/**
Kojto	122:f9eeca106725	688	* @}
Kojto	122:f9eeca106725	689	*/
Kojto	122:f9eeca106725	690	/* End of private macros -----------------------------------------------------*/
Kojto	122:f9eeca106725	691
Kojto	122:f9eeca106725	692	/**
Kojto	122:f9eeca106725	693	* @}
Kojto	122:f9eeca106725	694	*/
Kojto	122:f9eeca106725	695
Kojto	122:f9eeca106725	696	/**
Kojto	122:f9eeca106725	697	* @}
Kojto	122:f9eeca106725	698	*/
Kojto	122:f9eeca106725	699
Kojto	122:f9eeca106725	700	#ifdef __cplusplus
Kojto	122:f9eeca106725	701	}
Kojto	122:f9eeca106725	702	#endif
Kojto	122:f9eeca106725	703
Kojto	122:f9eeca106725	704	#endif /* __STM32L4xx_HAL_QSPI_H */
Kojto	122:f9eeca106725	705
Kojto	122:f9eeca106725	706	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/