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TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Parent:: 128:9bcdf88f62b0

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_ll_pwr.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.7.1
AnnaBridge	145:64910690c574	6	* @date 21-April-2017
Kojto	122:f9eeca106725	7	* @brief Header file of PWR LL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32L4xx_LL_PWR_H
Kojto	122:f9eeca106725	40	#define __STM32L4xx_LL_PWR_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
Kojto	122:f9eeca106725	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	47	#include "stm32l4xx.h"
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** @addtogroup STM32L4xx_LL_Driver
Kojto	122:f9eeca106725	50	* @{
Kojto	122:f9eeca106725	51	*/
Kojto	122:f9eeca106725	52
Kojto	122:f9eeca106725	53	#if defined(PWR)
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	/** @defgroup PWR_LL PWR
Kojto	122:f9eeca106725	56	* @{
Kojto	122:f9eeca106725	57	*/
Kojto	122:f9eeca106725	58
Kojto	122:f9eeca106725	59	/* Private types -------------------------------------------------------------*/
Kojto	122:f9eeca106725	60	/* Private variables ---------------------------------------------------------*/
Kojto	122:f9eeca106725	61
Kojto	122:f9eeca106725	62	/* Private constants ---------------------------------------------------------*/
Kojto	122:f9eeca106725	63
Kojto	122:f9eeca106725	64	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	65
Kojto	122:f9eeca106725	66	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	67	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	68	/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
Kojto	122:f9eeca106725	69	* @{
Kojto	122:f9eeca106725	70	*/
Kojto	122:f9eeca106725	71
Kojto	122:f9eeca106725	72	/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
Kojto	122:f9eeca106725	73	* @brief Flags defines which can be used with LL_PWR_WriteReg function
Kojto	122:f9eeca106725	74	* @{
Kojto	122:f9eeca106725	75	*/
Kojto	122:f9eeca106725	76	#define LL_PWR_SCR_CSBF PWR_SCR_CSBF
Kojto	122:f9eeca106725	77	#define LL_PWR_SCR_CWUF PWR_SCR_CWUF
Kojto	122:f9eeca106725	78	#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
Kojto	122:f9eeca106725	79	#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
Kojto	122:f9eeca106725	80	#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
Kojto	122:f9eeca106725	81	#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
Kojto	122:f9eeca106725	82	#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
Kojto	122:f9eeca106725	83	/**
Kojto	122:f9eeca106725	84	* @}
Kojto	122:f9eeca106725	85	*/
Kojto	122:f9eeca106725	86
Kojto	122:f9eeca106725	87	/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
Kojto	122:f9eeca106725	88	* @brief Flags defines which can be used with LL_PWR_ReadReg function
Kojto	122:f9eeca106725	89	* @{
Kojto	122:f9eeca106725	90	*/
Kojto	122:f9eeca106725	91	#define LL_PWR_SR1_WUFI PWR_SR1_WUFI
Kojto	122:f9eeca106725	92	#define LL_PWR_SR1_SBF PWR_SR1_SBF
Kojto	122:f9eeca106725	93	#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
Kojto	122:f9eeca106725	94	#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
Kojto	122:f9eeca106725	95	#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
Kojto	122:f9eeca106725	96	#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
Kojto	122:f9eeca106725	97	#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
AnnaBridge	145:64910690c574	98	#if defined(PWR_SR2_PVMO4)
Kojto	122:f9eeca106725	99	#define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
AnnaBridge	145:64910690c574	100	#endif /* PWR_SR2_PVMO4 */
AnnaBridge	145:64910690c574	101	#if defined(PWR_SR2_PVMO3)
Kojto	122:f9eeca106725	102	#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
AnnaBridge	145:64910690c574	103	#endif /* PWR_SR2_PVMO3 */
Kojto	122:f9eeca106725	104	#if defined(PWR_SR2_PVMO2)
Kojto	122:f9eeca106725	105	#define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
Kojto	122:f9eeca106725	106	#endif /* PWR_SR2_PVMO2 */
AnnaBridge	145:64910690c574	107	#if defined(PWR_SR2_PVMO1)
Kojto	122:f9eeca106725	108	#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
AnnaBridge	145:64910690c574	109	#endif /* PWR_SR2_PVMO1 */
Kojto	122:f9eeca106725	110	#define LL_PWR_SR2_PVDO PWR_SR2_PVDO
Kojto	122:f9eeca106725	111	#define LL_PWR_SR2_VOSF PWR_SR2_VOSF
Kojto	122:f9eeca106725	112	#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
Kojto	122:f9eeca106725	113	#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
Kojto	122:f9eeca106725	114	/**
Kojto	122:f9eeca106725	115	* @}
Kojto	122:f9eeca106725	116	*/
Kojto	122:f9eeca106725	117
Kojto	122:f9eeca106725	118	/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
Kojto	122:f9eeca106725	119	* @{
Kojto	122:f9eeca106725	120	*/
Kojto	122:f9eeca106725	121	#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
Kojto	122:f9eeca106725	122	#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
Kojto	122:f9eeca106725	123	/**
Kojto	122:f9eeca106725	124	* @}
Kojto	122:f9eeca106725	125	*/
Kojto	122:f9eeca106725	126
Kojto	122:f9eeca106725	127	/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
Kojto	122:f9eeca106725	128	* @{
Kojto	122:f9eeca106725	129	*/
Kojto	122:f9eeca106725	130	#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
Kojto	122:f9eeca106725	131	#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
Kojto	122:f9eeca106725	132	#define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)
Kojto	122:f9eeca106725	133	#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
Kojto	122:f9eeca106725	134	#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
Kojto	122:f9eeca106725	135	/**
Kojto	122:f9eeca106725	136	* @}
Kojto	122:f9eeca106725	137	*/
Kojto	122:f9eeca106725	138
AnnaBridge	145:64910690c574	139	/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
Kojto	122:f9eeca106725	140	* @{
Kojto	122:f9eeca106725	141	*/
AnnaBridge	145:64910690c574	142	#if defined(PWR_CR2_PVME1)
Kojto	122:f9eeca106725	143	#define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
AnnaBridge	145:64910690c574	144	#endif
Kojto	122:f9eeca106725	145	#if defined(PWR_CR2_PVME2)
Kojto	122:f9eeca106725	146	#define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */
AnnaBridge	145:64910690c574	147	#endif
AnnaBridge	145:64910690c574	148	#if defined(PWR_CR2_PVME3)
Kojto	122:f9eeca106725	149	#define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
AnnaBridge	145:64910690c574	150	#endif
AnnaBridge	145:64910690c574	151	#if defined(PWR_CR2_PVME4)
Kojto	122:f9eeca106725	152	#define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */
AnnaBridge	145:64910690c574	153	#endif
Kojto	122:f9eeca106725	154	/**
Kojto	122:f9eeca106725	155	* @}
Kojto	122:f9eeca106725	156	*/
AnnaBridge	145:64910690c574	157
Kojto	122:f9eeca106725	158	/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
Kojto	122:f9eeca106725	159	* @{
Kojto	122:f9eeca106725	160	*/
Kojto	122:f9eeca106725	161	#define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
Kojto	122:f9eeca106725	162	#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
Kojto	122:f9eeca106725	163	#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
Kojto	122:f9eeca106725	164	#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
Kojto	122:f9eeca106725	165	#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
Kojto	122:f9eeca106725	166	#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
Kojto	122:f9eeca106725	167	#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
Kojto	122:f9eeca106725	168	#define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
Kojto	122:f9eeca106725	169	/**
Kojto	122:f9eeca106725	170	* @}
Kojto	122:f9eeca106725	171	*/
Kojto	122:f9eeca106725	172
Kojto	122:f9eeca106725	173	/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
Kojto	122:f9eeca106725	174	* @{
Kojto	122:f9eeca106725	175	*/
Kojto	122:f9eeca106725	176	#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
Kojto	122:f9eeca106725	177	#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
Kojto	122:f9eeca106725	178	#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
Kojto	122:f9eeca106725	179	#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
Kojto	122:f9eeca106725	180	#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
Kojto	122:f9eeca106725	181	/**
Kojto	122:f9eeca106725	182	* @}
Kojto	122:f9eeca106725	183	*/
Kojto	122:f9eeca106725	184
Kojto	122:f9eeca106725	185	/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
Kojto	122:f9eeca106725	186	* @{
Kojto	122:f9eeca106725	187	*/
Kojto	122:f9eeca106725	188	#define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
Kojto	122:f9eeca106725	189	#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
Kojto	122:f9eeca106725	190	/**
Kojto	122:f9eeca106725	191	* @}
Kojto	122:f9eeca106725	192	*/
Kojto	122:f9eeca106725	193
Kojto	122:f9eeca106725	194	/** @defgroup PWR_LL_EC_GPIO GPIO
Kojto	122:f9eeca106725	195	* @{
Kojto	122:f9eeca106725	196	*/
Kojto	122:f9eeca106725	197	#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
Kojto	122:f9eeca106725	198	#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
Kojto	122:f9eeca106725	199	#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
Kojto	122:f9eeca106725	200	#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
Kojto	122:f9eeca106725	201	#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
Kojto	122:f9eeca106725	202	#if defined(GPIOF)
Kojto	122:f9eeca106725	203	#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
AnnaBridge	145:64910690c574	204	#endif
Kojto	122:f9eeca106725	205	#if defined(GPIOG)
Kojto	122:f9eeca106725	206	#define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
AnnaBridge	145:64910690c574	207	#endif
AnnaBridge	145:64910690c574	208	#if defined(GPIOH)
Kojto	122:f9eeca106725	209	#define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
AnnaBridge	145:64910690c574	210	#endif
AnnaBridge	145:64910690c574	211	#if defined(GPIOI)
AnnaBridge	145:64910690c574	212	#define LL_PWR_GPIO_I ((uint32_t)(&(PWR->PUCRI)))
AnnaBridge	145:64910690c574	213	#endif
Kojto	122:f9eeca106725	214	/**
Kojto	122:f9eeca106725	215	* @}
Kojto	122:f9eeca106725	216	*/
Kojto	122:f9eeca106725	217
Kojto	122:f9eeca106725	218	/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
Kojto	122:f9eeca106725	219	* @{
Kojto	122:f9eeca106725	220	*/
Kojto	122:f9eeca106725	221	#define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
Kojto	122:f9eeca106725	222	#define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
Kojto	122:f9eeca106725	223	#define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
Kojto	122:f9eeca106725	224	#define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
Kojto	122:f9eeca106725	225	#define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
Kojto	122:f9eeca106725	226	#define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
Kojto	122:f9eeca106725	227	#define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
Kojto	122:f9eeca106725	228	#define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
Kojto	122:f9eeca106725	229	#define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
Kojto	122:f9eeca106725	230	#define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
Kojto	122:f9eeca106725	231	#define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
Kojto	122:f9eeca106725	232	#define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
Kojto	122:f9eeca106725	233	#define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
Kojto	122:f9eeca106725	234	#define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
Kojto	122:f9eeca106725	235	#define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
Kojto	122:f9eeca106725	236	#define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
Kojto	122:f9eeca106725	237	/**
Kojto	122:f9eeca106725	238	* @}
Kojto	122:f9eeca106725	239	*/
Kojto	122:f9eeca106725	240
Kojto	122:f9eeca106725	241	/**
Kojto	122:f9eeca106725	242	* @}
Kojto	122:f9eeca106725	243	*/
Kojto	122:f9eeca106725	244
Kojto	122:f9eeca106725	245	/* Exported macro ------------------------------------------------------------*/
Kojto	122:f9eeca106725	246	/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
Kojto	122:f9eeca106725	247	* @{
Kojto	122:f9eeca106725	248	*/
Kojto	122:f9eeca106725	249
Kojto	122:f9eeca106725	250	/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
Kojto	122:f9eeca106725	251	* @{
Kojto	122:f9eeca106725	252	*/
Kojto	122:f9eeca106725	253
Kojto	122:f9eeca106725	254	/**
Kojto	122:f9eeca106725	255	* @brief Write a value in PWR register
Kojto	122:f9eeca106725	256	* @param __REG__ Register to be written
Kojto	122:f9eeca106725	257	* @param __VALUE__ Value to be written in the register
Kojto	122:f9eeca106725	258	* @retval None
Kojto	122:f9eeca106725	259	*/
Kojto	122:f9eeca106725	260	#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Kojto	122:f9eeca106725	261
Kojto	122:f9eeca106725	262	/**
Kojto	122:f9eeca106725	263	* @brief Read a value in PWR register
Kojto	122:f9eeca106725	264	* @param __REG__ Register to be read
Kojto	122:f9eeca106725	265	* @retval Register value
Kojto	122:f9eeca106725	266	*/
Kojto	122:f9eeca106725	267	#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Kojto	122:f9eeca106725	268	/**
Kojto	122:f9eeca106725	269	* @}
Kojto	122:f9eeca106725	270	*/
Kojto	122:f9eeca106725	271
Kojto	122:f9eeca106725	272	/**
Kojto	122:f9eeca106725	273	* @}
Kojto	122:f9eeca106725	274	*/
Kojto	122:f9eeca106725	275
Kojto	122:f9eeca106725	276
Kojto	122:f9eeca106725	277	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	278	/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
Kojto	122:f9eeca106725	279	* @{
Kojto	122:f9eeca106725	280	*/
Kojto	122:f9eeca106725	281
Kojto	122:f9eeca106725	282	/** @defgroup PWR_LL_EF_Configuration Configuration
Kojto	122:f9eeca106725	283	* @{
Kojto	122:f9eeca106725	284	*/
Kojto	122:f9eeca106725	285
Kojto	122:f9eeca106725	286	/**
Kojto	122:f9eeca106725	287	* @brief Switch the regulator from main mode to low-power mode
Kojto	122:f9eeca106725	288	* @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
Kojto	122:f9eeca106725	289	* @retval None
Kojto	122:f9eeca106725	290	*/
Kojto	122:f9eeca106725	291	__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
Kojto	122:f9eeca106725	292	{
Kojto	122:f9eeca106725	293	SET_BIT(PWR->CR1, PWR_CR1_LPR);
Kojto	122:f9eeca106725	294	}
Kojto	122:f9eeca106725	295
Kojto	122:f9eeca106725	296	/**
Kojto	122:f9eeca106725	297	* @brief Switch the regulator from low-power mode to main mode
Kojto	122:f9eeca106725	298	* @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
Kojto	122:f9eeca106725	299	* @retval None
Kojto	122:f9eeca106725	300	*/
Kojto	122:f9eeca106725	301	__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
Kojto	122:f9eeca106725	302	{
Kojto	122:f9eeca106725	303	CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
Kojto	122:f9eeca106725	304	}
Kojto	122:f9eeca106725	305
Kojto	122:f9eeca106725	306	/**
Kojto	122:f9eeca106725	307	* @brief Check if the regulator is in low-power mode
Kojto	122:f9eeca106725	308	* @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
Kojto	122:f9eeca106725	309	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	310	*/
Kojto	122:f9eeca106725	311	__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
Kojto	122:f9eeca106725	312	{
Kojto	122:f9eeca106725	313	return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR));
Kojto	122:f9eeca106725	314	}
Kojto	122:f9eeca106725	315
Kojto	122:f9eeca106725	316	/**
Kojto	122:f9eeca106725	317	* @brief Switch from run main mode to run low-power mode.
Kojto	122:f9eeca106725	318	* @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
Kojto	122:f9eeca106725	319	* @retval None
Kojto	122:f9eeca106725	320	*/
Kojto	122:f9eeca106725	321	__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
Kojto	122:f9eeca106725	322	{
Kojto	122:f9eeca106725	323	LL_PWR_EnableLowPowerRunMode();
Kojto	122:f9eeca106725	324	}
Kojto	122:f9eeca106725	325
Kojto	122:f9eeca106725	326	/**
Kojto	122:f9eeca106725	327	* @brief Switch from run main mode to low-power mode.
Kojto	122:f9eeca106725	328	* @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
Kojto	122:f9eeca106725	329	* @retval None
Kojto	122:f9eeca106725	330	*/
Kojto	122:f9eeca106725	331	__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
Kojto	122:f9eeca106725	332	{
Kojto	122:f9eeca106725	333	LL_PWR_DisableLowPowerRunMode();
Kojto	122:f9eeca106725	334	}
Kojto	122:f9eeca106725	335
Kojto	122:f9eeca106725	336	/**
Kojto	122:f9eeca106725	337	* @brief Set the main internal regulator output voltage
Kojto	122:f9eeca106725	338	* @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
Kojto	122:f9eeca106725	339	* @param VoltageScaling This parameter can be one of the following values:
Kojto	122:f9eeca106725	340	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
Kojto	122:f9eeca106725	341	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
Kojto	122:f9eeca106725	342	* @retval None
Kojto	122:f9eeca106725	343	*/
Kojto	122:f9eeca106725	344	__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
Kojto	122:f9eeca106725	345	{
Kojto	122:f9eeca106725	346	MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
Kojto	122:f9eeca106725	347	}
Kojto	122:f9eeca106725	348
Kojto	122:f9eeca106725	349	/**
Kojto	122:f9eeca106725	350	* @brief Get the main internal regulator output voltage
Kojto	122:f9eeca106725	351	* @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
Kojto	122:f9eeca106725	352	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	353	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
Kojto	122:f9eeca106725	354	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
Kojto	122:f9eeca106725	355	*/
Kojto	122:f9eeca106725	356	__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
Kojto	122:f9eeca106725	357	{
Kojto	122:f9eeca106725	358	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
Kojto	122:f9eeca106725	359	}
Kojto	122:f9eeca106725	360
Kojto	122:f9eeca106725	361	/**
Kojto	122:f9eeca106725	362	* @brief Enable access to the backup domain
Kojto	122:f9eeca106725	363	* @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
Kojto	122:f9eeca106725	364	* @retval None
Kojto	122:f9eeca106725	365	*/
Kojto	122:f9eeca106725	366	__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
Kojto	122:f9eeca106725	367	{
Kojto	122:f9eeca106725	368	SET_BIT(PWR->CR1, PWR_CR1_DBP);
Kojto	122:f9eeca106725	369	}
Kojto	122:f9eeca106725	370
Kojto	122:f9eeca106725	371	/**
Kojto	122:f9eeca106725	372	* @brief Disable access to the backup domain
Kojto	122:f9eeca106725	373	* @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
Kojto	122:f9eeca106725	374	* @retval None
Kojto	122:f9eeca106725	375	*/
Kojto	122:f9eeca106725	376	__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
Kojto	122:f9eeca106725	377	{
Kojto	122:f9eeca106725	378	CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
Kojto	122:f9eeca106725	379	}
Kojto	122:f9eeca106725	380
Kojto	122:f9eeca106725	381	/**
Kojto	122:f9eeca106725	382	* @brief Check if the backup domain is enabled
Kojto	122:f9eeca106725	383	* @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
Kojto	122:f9eeca106725	384	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	385	*/
Kojto	122:f9eeca106725	386	__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
Kojto	122:f9eeca106725	387	{
Kojto	122:f9eeca106725	388	return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));
Kojto	122:f9eeca106725	389	}
Kojto	122:f9eeca106725	390
Kojto	122:f9eeca106725	391	/**
Kojto	122:f9eeca106725	392	* @brief Set Low-Power mode
Kojto	122:f9eeca106725	393	* @rmtoll CR1 LPMS LL_PWR_SetPowerMode
Kojto	122:f9eeca106725	394	* @param LowPowerMode This parameter can be one of the following values:
Kojto	122:f9eeca106725	395	* @arg @ref LL_PWR_MODE_STOP0
Kojto	122:f9eeca106725	396	* @arg @ref LL_PWR_MODE_STOP1
Kojto	122:f9eeca106725	397	* @arg @ref LL_PWR_MODE_STOP2
Kojto	122:f9eeca106725	398	* @arg @ref LL_PWR_MODE_STANDBY
Kojto	122:f9eeca106725	399	* @arg @ref LL_PWR_MODE_SHUTDOWN
Kojto	122:f9eeca106725	400	* @retval None
Kojto	122:f9eeca106725	401	*/
Kojto	122:f9eeca106725	402	__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
Kojto	122:f9eeca106725	403	{
Kojto	122:f9eeca106725	404	MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
Kojto	122:f9eeca106725	405	}
Kojto	122:f9eeca106725	406
Kojto	122:f9eeca106725	407	/**
Kojto	122:f9eeca106725	408	* @brief Get Low-Power mode
Kojto	122:f9eeca106725	409	* @rmtoll CR1 LPMS LL_PWR_GetPowerMode
Kojto	122:f9eeca106725	410	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	411	* @arg @ref LL_PWR_MODE_STOP0
Kojto	122:f9eeca106725	412	* @arg @ref LL_PWR_MODE_STOP1
Kojto	122:f9eeca106725	413	* @arg @ref LL_PWR_MODE_STOP2
Kojto	122:f9eeca106725	414	* @arg @ref LL_PWR_MODE_STANDBY
Kojto	122:f9eeca106725	415	* @arg @ref LL_PWR_MODE_SHUTDOWN
Kojto	122:f9eeca106725	416	*/
Kojto	122:f9eeca106725	417	__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
Kojto	122:f9eeca106725	418	{
Kojto	122:f9eeca106725	419	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
Kojto	122:f9eeca106725	420	}
Kojto	122:f9eeca106725	421
AnnaBridge	145:64910690c574	422	#if defined(PWR_CR2_PVME1)
Kojto	122:f9eeca106725	423	/**
Kojto	122:f9eeca106725	424	* @brief Enable VDDUSB supply
Kojto	122:f9eeca106725	425	* @rmtoll CR2 USV LL_PWR_EnableVddUSB
Kojto	122:f9eeca106725	426	* @retval None
Kojto	122:f9eeca106725	427	*/
Kojto	122:f9eeca106725	428	__STATIC_INLINE void LL_PWR_EnableVddUSB(void)
Kojto	122:f9eeca106725	429	{
Kojto	122:f9eeca106725	430	SET_BIT(PWR->CR2, PWR_CR2_USV);
Kojto	122:f9eeca106725	431	}
Kojto	122:f9eeca106725	432
Kojto	122:f9eeca106725	433	/**
Kojto	122:f9eeca106725	434	* @brief Disable VDDUSB supply
Kojto	122:f9eeca106725	435	* @rmtoll CR2 USV LL_PWR_DisableVddUSB
Kojto	122:f9eeca106725	436	* @retval None
Kojto	122:f9eeca106725	437	*/
Kojto	122:f9eeca106725	438	__STATIC_INLINE void LL_PWR_DisableVddUSB(void)
Kojto	122:f9eeca106725	439	{
Kojto	122:f9eeca106725	440	CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
Kojto	122:f9eeca106725	441	}
Kojto	122:f9eeca106725	442
Kojto	122:f9eeca106725	443	/**
Kojto	122:f9eeca106725	444	* @brief Check if VDDUSB supply is enabled
Kojto	122:f9eeca106725	445	* @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
Kojto	122:f9eeca106725	446	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	447	*/
Kojto	122:f9eeca106725	448	__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
Kojto	122:f9eeca106725	449	{
Kojto	122:f9eeca106725	450	return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV));
Kojto	122:f9eeca106725	451	}
AnnaBridge	145:64910690c574	452	#endif
Kojto	122:f9eeca106725	453
Kojto	122:f9eeca106725	454	#if defined(PWR_CR2_IOSV)
Kojto	122:f9eeca106725	455	/**
Kojto	122:f9eeca106725	456	* @brief Enable VDDIO2 supply
Kojto	122:f9eeca106725	457	* @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
Kojto	122:f9eeca106725	458	* @retval None
Kojto	122:f9eeca106725	459	*/
Kojto	122:f9eeca106725	460	__STATIC_INLINE void LL_PWR_EnableVddIO2(void)
Kojto	122:f9eeca106725	461	{
Kojto	122:f9eeca106725	462	SET_BIT(PWR->CR2, PWR_CR2_IOSV);
Kojto	122:f9eeca106725	463	}
Kojto	122:f9eeca106725	464
Kojto	122:f9eeca106725	465	/**
Kojto	122:f9eeca106725	466	* @brief Disable VDDIO2 supply
Kojto	122:f9eeca106725	467	* @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
Kojto	122:f9eeca106725	468	* @retval None
Kojto	122:f9eeca106725	469	*/
Kojto	122:f9eeca106725	470	__STATIC_INLINE void LL_PWR_DisableVddIO2(void)
Kojto	122:f9eeca106725	471	{
Kojto	122:f9eeca106725	472	CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
Kojto	122:f9eeca106725	473	}
Kojto	122:f9eeca106725	474
Kojto	122:f9eeca106725	475	/**
Kojto	122:f9eeca106725	476	* @brief Check if VDDIO2 supply is enabled
Kojto	122:f9eeca106725	477	* @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
Kojto	122:f9eeca106725	478	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	479	*/
Kojto	122:f9eeca106725	480	__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
Kojto	122:f9eeca106725	481	{
Kojto	122:f9eeca106725	482	return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV));
Kojto	122:f9eeca106725	483	}
AnnaBridge	145:64910690c574	484	#endif
Kojto	122:f9eeca106725	485
Kojto	122:f9eeca106725	486	/**
Kojto	122:f9eeca106725	487	* @brief Enable the Power Voltage Monitoring on a peripheral
Kojto	122:f9eeca106725	488	* @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
Kojto	122:f9eeca106725	489	* CR2 PVME2 LL_PWR_EnablePVM\n
Kojto	122:f9eeca106725	490	* CR2 PVME3 LL_PWR_EnablePVM\n
Kojto	122:f9eeca106725	491	* CR2 PVME4 LL_PWR_EnablePVM
Kojto	122:f9eeca106725	492	* @param PeriphVoltage This parameter can be one of the following values:
Kojto	122:f9eeca106725	493	* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
Kojto	122:f9eeca106725	494	* @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
Kojto	122:f9eeca106725	495	* @arg @ref LL_PWR_PVM_VDDA_1_62V
Kojto	122:f9eeca106725	496	* @arg @ref LL_PWR_PVM_VDDA_2_2V
Kojto	122:f9eeca106725	497	*
Kojto	122:f9eeca106725	498	* (*) value not defined in all devices
Kojto	122:f9eeca106725	499	* @retval None
Kojto	122:f9eeca106725	500	*/
Kojto	122:f9eeca106725	501	__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
Kojto	122:f9eeca106725	502	{
Kojto	122:f9eeca106725	503	SET_BIT(PWR->CR2, PeriphVoltage);
Kojto	122:f9eeca106725	504	}
Kojto	122:f9eeca106725	505
Kojto	122:f9eeca106725	506	/**
Kojto	122:f9eeca106725	507	* @brief Disable the Power Voltage Monitoring on a peripheral
Kojto	122:f9eeca106725	508	* @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
Kojto	122:f9eeca106725	509	* CR2 PVME2 LL_PWR_DisablePVM\n
Kojto	122:f9eeca106725	510	* CR2 PVME3 LL_PWR_DisablePVM\n
Kojto	122:f9eeca106725	511	* CR2 PVME4 LL_PWR_DisablePVM
Kojto	122:f9eeca106725	512	* @param PeriphVoltage This parameter can be one of the following values:
Kojto	122:f9eeca106725	513	* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
Kojto	122:f9eeca106725	514	* @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
Kojto	122:f9eeca106725	515	* @arg @ref LL_PWR_PVM_VDDA_1_62V
Kojto	122:f9eeca106725	516	* @arg @ref LL_PWR_PVM_VDDA_2_2V
Kojto	122:f9eeca106725	517	*
Kojto	122:f9eeca106725	518	* (*) value not defined in all devices
Kojto	122:f9eeca106725	519	* @retval None
Kojto	122:f9eeca106725	520	*/
Kojto	122:f9eeca106725	521	__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
Kojto	122:f9eeca106725	522	{
Kojto	122:f9eeca106725	523	CLEAR_BIT(PWR->CR2, PeriphVoltage);
Kojto	122:f9eeca106725	524	}
Kojto	122:f9eeca106725	525
Kojto	122:f9eeca106725	526	/**
AnnaBridge	145:64910690c574	527	* @brief Check if Power Voltage Monitoring is enabled on a peripheral
Kojto	122:f9eeca106725	528	* @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
Kojto	122:f9eeca106725	529	* CR2 PVME2 LL_PWR_IsEnabledPVM\n
Kojto	122:f9eeca106725	530	* CR2 PVME3 LL_PWR_IsEnabledPVM\n
Kojto	122:f9eeca106725	531	* CR2 PVME4 LL_PWR_IsEnabledPVM
Kojto	122:f9eeca106725	532	* @param PeriphVoltage This parameter can be one of the following values:
Kojto	122:f9eeca106725	533	* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
Kojto	122:f9eeca106725	534	* @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
Kojto	122:f9eeca106725	535	* @arg @ref LL_PWR_PVM_VDDA_1_62V
Kojto	122:f9eeca106725	536	* @arg @ref LL_PWR_PVM_VDDA_2_2V
Kojto	122:f9eeca106725	537	*
Kojto	122:f9eeca106725	538	* (*) value not defined in all devices
Kojto	122:f9eeca106725	539	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	540	*/
Kojto	122:f9eeca106725	541	__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
Kojto	122:f9eeca106725	542	{
Kojto	122:f9eeca106725	543	return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage));
Kojto	122:f9eeca106725	544	}
Kojto	122:f9eeca106725	545
Kojto	122:f9eeca106725	546	/**
Kojto	122:f9eeca106725	547	* @brief Configure the voltage threshold detected by the Power Voltage Detector
Kojto	122:f9eeca106725	548	* @rmtoll CR2 PLS LL_PWR_SetPVDLevel
Kojto	122:f9eeca106725	549	* @param PVDLevel This parameter can be one of the following values:
Kojto	122:f9eeca106725	550	* @arg @ref LL_PWR_PVDLEVEL_0
Kojto	122:f9eeca106725	551	* @arg @ref LL_PWR_PVDLEVEL_1
Kojto	122:f9eeca106725	552	* @arg @ref LL_PWR_PVDLEVEL_2
Kojto	122:f9eeca106725	553	* @arg @ref LL_PWR_PVDLEVEL_3
Kojto	122:f9eeca106725	554	* @arg @ref LL_PWR_PVDLEVEL_4
Kojto	122:f9eeca106725	555	* @arg @ref LL_PWR_PVDLEVEL_5
Kojto	122:f9eeca106725	556	* @arg @ref LL_PWR_PVDLEVEL_6
Kojto	122:f9eeca106725	557	* @arg @ref LL_PWR_PVDLEVEL_7
Kojto	122:f9eeca106725	558	* @retval None
Kojto	122:f9eeca106725	559	*/
Kojto	122:f9eeca106725	560	__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
Kojto	122:f9eeca106725	561	{
Kojto	122:f9eeca106725	562	MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
Kojto	122:f9eeca106725	563	}
Kojto	122:f9eeca106725	564
Kojto	122:f9eeca106725	565	/**
Kojto	122:f9eeca106725	566	* @brief Get the voltage threshold detection
Kojto	122:f9eeca106725	567	* @rmtoll CR2 PLS LL_PWR_GetPVDLevel
Kojto	122:f9eeca106725	568	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	569	* @arg @ref LL_PWR_PVDLEVEL_0
Kojto	122:f9eeca106725	570	* @arg @ref LL_PWR_PVDLEVEL_1
Kojto	122:f9eeca106725	571	* @arg @ref LL_PWR_PVDLEVEL_2
Kojto	122:f9eeca106725	572	* @arg @ref LL_PWR_PVDLEVEL_3
Kojto	122:f9eeca106725	573	* @arg @ref LL_PWR_PVDLEVEL_4
Kojto	122:f9eeca106725	574	* @arg @ref LL_PWR_PVDLEVEL_5
Kojto	122:f9eeca106725	575	* @arg @ref LL_PWR_PVDLEVEL_6
Kojto	122:f9eeca106725	576	* @arg @ref LL_PWR_PVDLEVEL_7
Kojto	122:f9eeca106725	577	*/
Kojto	122:f9eeca106725	578	__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
Kojto	122:f9eeca106725	579	{
Kojto	122:f9eeca106725	580	return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
Kojto	122:f9eeca106725	581	}
Kojto	122:f9eeca106725	582
Kojto	122:f9eeca106725	583	/**
Kojto	122:f9eeca106725	584	* @brief Enable Power Voltage Detector
Kojto	122:f9eeca106725	585	* @rmtoll CR2 PVDE LL_PWR_EnablePVD
Kojto	122:f9eeca106725	586	* @retval None
Kojto	122:f9eeca106725	587	*/
Kojto	122:f9eeca106725	588	__STATIC_INLINE void LL_PWR_EnablePVD(void)
Kojto	122:f9eeca106725	589	{
Kojto	122:f9eeca106725	590	SET_BIT(PWR->CR2, PWR_CR2_PVDE);
Kojto	122:f9eeca106725	591	}
Kojto	122:f9eeca106725	592
Kojto	122:f9eeca106725	593	/**
Kojto	122:f9eeca106725	594	* @brief Disable Power Voltage Detector
Kojto	122:f9eeca106725	595	* @rmtoll CR2 PVDE LL_PWR_DisablePVD
Kojto	122:f9eeca106725	596	* @retval None
Kojto	122:f9eeca106725	597	*/
Kojto	122:f9eeca106725	598	__STATIC_INLINE void LL_PWR_DisablePVD(void)
Kojto	122:f9eeca106725	599	{
Kojto	122:f9eeca106725	600	CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
Kojto	122:f9eeca106725	601	}
Kojto	122:f9eeca106725	602
Kojto	122:f9eeca106725	603	/**
Kojto	122:f9eeca106725	604	* @brief Check if Power Voltage Detector is enabled
Kojto	122:f9eeca106725	605	* @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
Kojto	122:f9eeca106725	606	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	607	*/
Kojto	122:f9eeca106725	608	__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
Kojto	122:f9eeca106725	609	{
Kojto	122:f9eeca106725	610	return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE));
Kojto	122:f9eeca106725	611	}
Kojto	122:f9eeca106725	612
Kojto	122:f9eeca106725	613	/**
Kojto	122:f9eeca106725	614	* @brief Enable Internal Wake-up line
Kojto	122:f9eeca106725	615	* @rmtoll CR3 EIWF LL_PWR_EnableInternWU
Kojto	122:f9eeca106725	616	* @retval None
Kojto	122:f9eeca106725	617	*/
Kojto	122:f9eeca106725	618	__STATIC_INLINE void LL_PWR_EnableInternWU(void)
Kojto	122:f9eeca106725	619	{
Kojto	122:f9eeca106725	620	SET_BIT(PWR->CR3, PWR_CR3_EIWF);
Kojto	122:f9eeca106725	621	}
Kojto	122:f9eeca106725	622
Kojto	122:f9eeca106725	623	/**
Kojto	122:f9eeca106725	624	* @brief Disable Internal Wake-up line
Kojto	122:f9eeca106725	625	* @rmtoll CR3 EIWF LL_PWR_DisableInternWU
Kojto	122:f9eeca106725	626	* @retval None
Kojto	122:f9eeca106725	627	*/
Kojto	122:f9eeca106725	628	__STATIC_INLINE void LL_PWR_DisableInternWU(void)
Kojto	122:f9eeca106725	629	{
Kojto	122:f9eeca106725	630	CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
Kojto	122:f9eeca106725	631	}
Kojto	122:f9eeca106725	632
Kojto	122:f9eeca106725	633	/**
Kojto	122:f9eeca106725	634	* @brief Check if Internal Wake-up line is enabled
Kojto	122:f9eeca106725	635	* @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
Kojto	122:f9eeca106725	636	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	637	*/
Kojto	122:f9eeca106725	638	__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
Kojto	122:f9eeca106725	639	{
Kojto	122:f9eeca106725	640	return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF));
Kojto	122:f9eeca106725	641	}
Kojto	122:f9eeca106725	642
Kojto	122:f9eeca106725	643	/**
Kojto	122:f9eeca106725	644	* @brief Enable pull-up and pull-down configuration
Kojto	122:f9eeca106725	645	* @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
Kojto	122:f9eeca106725	646	* @retval None
Kojto	122:f9eeca106725	647	*/
Kojto	122:f9eeca106725	648	__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
Kojto	122:f9eeca106725	649	{
Kojto	122:f9eeca106725	650	SET_BIT(PWR->CR3, PWR_CR3_APC);
Kojto	122:f9eeca106725	651	}
Kojto	122:f9eeca106725	652
Kojto	122:f9eeca106725	653	/**
Kojto	122:f9eeca106725	654	* @brief Disable pull-up and pull-down configuration
Kojto	122:f9eeca106725	655	* @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
Kojto	122:f9eeca106725	656	* @retval None
Kojto	122:f9eeca106725	657	*/
Kojto	122:f9eeca106725	658	__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
Kojto	122:f9eeca106725	659	{
Kojto	122:f9eeca106725	660	CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
Kojto	122:f9eeca106725	661	}
Kojto	122:f9eeca106725	662
Kojto	122:f9eeca106725	663	/**
Kojto	122:f9eeca106725	664	* @brief Check if pull-up and pull-down configuration is enabled
Kojto	122:f9eeca106725	665	* @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
Kojto	122:f9eeca106725	666	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	667	*/
Kojto	122:f9eeca106725	668	__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
Kojto	122:f9eeca106725	669	{
Kojto	122:f9eeca106725	670	return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC));
Kojto	122:f9eeca106725	671	}
Kojto	122:f9eeca106725	672
Kojto	122:f9eeca106725	673	/**
Kojto	122:f9eeca106725	674	* @brief Enable SRAM2 content retention in Standby mode
Kojto	122:f9eeca106725	675	* @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
Kojto	122:f9eeca106725	676	* @retval None
Kojto	122:f9eeca106725	677	*/
Kojto	122:f9eeca106725	678	__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
Kojto	122:f9eeca106725	679	{
Kojto	122:f9eeca106725	680	SET_BIT(PWR->CR3, PWR_CR3_RRS);
Kojto	122:f9eeca106725	681	}
Kojto	122:f9eeca106725	682
Kojto	122:f9eeca106725	683	/**
Kojto	122:f9eeca106725	684	* @brief Disable SRAM2 content retention in Standby mode
Kojto	122:f9eeca106725	685	* @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
Kojto	122:f9eeca106725	686	* @retval None
Kojto	122:f9eeca106725	687	*/
Kojto	122:f9eeca106725	688	__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
Kojto	122:f9eeca106725	689	{
Kojto	122:f9eeca106725	690	CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
Kojto	122:f9eeca106725	691	}
Kojto	122:f9eeca106725	692
Kojto	122:f9eeca106725	693	/**
Kojto	122:f9eeca106725	694	* @brief Check if SRAM2 content retention in Standby mode is enabled
Kojto	122:f9eeca106725	695	* @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
Kojto	122:f9eeca106725	696	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	697	*/
Kojto	122:f9eeca106725	698	__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
Kojto	122:f9eeca106725	699	{
Kojto	122:f9eeca106725	700	return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS));
Kojto	122:f9eeca106725	701	}
Kojto	122:f9eeca106725	702
Kojto	122:f9eeca106725	703	/**
Kojto	122:f9eeca106725	704	* @brief Enable the WakeUp PINx functionality
Kojto	122:f9eeca106725	705	* @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
Kojto	122:f9eeca106725	706	* CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
Kojto	122:f9eeca106725	707	* CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
Kojto	122:f9eeca106725	708	* CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
AnnaBridge	145:64910690c574	709	* CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
Kojto	122:f9eeca106725	710	* @param WakeUpPin This parameter can be one of the following values:
Kojto	122:f9eeca106725	711	* @arg @ref LL_PWR_WAKEUP_PIN1
Kojto	122:f9eeca106725	712	* @arg @ref LL_PWR_WAKEUP_PIN2
Kojto	122:f9eeca106725	713	* @arg @ref LL_PWR_WAKEUP_PIN3
Kojto	122:f9eeca106725	714	* @arg @ref LL_PWR_WAKEUP_PIN4
Kojto	122:f9eeca106725	715	* @arg @ref LL_PWR_WAKEUP_PIN5
Kojto	122:f9eeca106725	716	* @retval None
Kojto	122:f9eeca106725	717	*/
Kojto	122:f9eeca106725	718	__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
Kojto	122:f9eeca106725	719	{
Kojto	122:f9eeca106725	720	SET_BIT(PWR->CR3, WakeUpPin);
Kojto	122:f9eeca106725	721	}
Kojto	122:f9eeca106725	722
Kojto	122:f9eeca106725	723	/**
Kojto	122:f9eeca106725	724	* @brief Disable the WakeUp PINx functionality
Kojto	122:f9eeca106725	725	* @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
Kojto	122:f9eeca106725	726	* CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
Kojto	122:f9eeca106725	727	* CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
Kojto	122:f9eeca106725	728	* CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
AnnaBridge	145:64910690c574	729	* CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
Kojto	122:f9eeca106725	730	* @param WakeUpPin This parameter can be one of the following values:
Kojto	122:f9eeca106725	731	* @arg @ref LL_PWR_WAKEUP_PIN1
Kojto	122:f9eeca106725	732	* @arg @ref LL_PWR_WAKEUP_PIN2
Kojto	122:f9eeca106725	733	* @arg @ref LL_PWR_WAKEUP_PIN3
Kojto	122:f9eeca106725	734	* @arg @ref LL_PWR_WAKEUP_PIN4
Kojto	122:f9eeca106725	735	* @arg @ref LL_PWR_WAKEUP_PIN5
Kojto	122:f9eeca106725	736	* @retval None
Kojto	122:f9eeca106725	737	*/
Kojto	122:f9eeca106725	738	__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
Kojto	122:f9eeca106725	739	{
Kojto	122:f9eeca106725	740	CLEAR_BIT(PWR->CR3, WakeUpPin);
Kojto	122:f9eeca106725	741	}
Kojto	122:f9eeca106725	742
Kojto	122:f9eeca106725	743	/**
Kojto	122:f9eeca106725	744	* @brief Check if the WakeUp PINx functionality is enabled
Kojto	122:f9eeca106725	745	* @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
Kojto	122:f9eeca106725	746	* CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
Kojto	122:f9eeca106725	747	* CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
Kojto	122:f9eeca106725	748	* CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	145:64910690c574	749	* CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
Kojto	122:f9eeca106725	750	* @param WakeUpPin This parameter can be one of the following values:
Kojto	122:f9eeca106725	751	* @arg @ref LL_PWR_WAKEUP_PIN1
Kojto	122:f9eeca106725	752	* @arg @ref LL_PWR_WAKEUP_PIN2
Kojto	122:f9eeca106725	753	* @arg @ref LL_PWR_WAKEUP_PIN3
Kojto	122:f9eeca106725	754	* @arg @ref LL_PWR_WAKEUP_PIN4
Kojto	122:f9eeca106725	755	* @arg @ref LL_PWR_WAKEUP_PIN5
Kojto	122:f9eeca106725	756	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	757	*/
Kojto	122:f9eeca106725	758	__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
Kojto	122:f9eeca106725	759	{
Kojto	122:f9eeca106725	760	return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin));
Kojto	122:f9eeca106725	761	}
Kojto	122:f9eeca106725	762
Kojto	122:f9eeca106725	763	/**
Kojto	122:f9eeca106725	764	* @brief Set the resistor impedance
Kojto	122:f9eeca106725	765	* @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
Kojto	122:f9eeca106725	766	* @param Resistor This parameter can be one of the following values:
Kojto	122:f9eeca106725	767	* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
Kojto	122:f9eeca106725	768	* @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
Kojto	122:f9eeca106725	769	* @retval None
Kojto	122:f9eeca106725	770	*/
Kojto	122:f9eeca106725	771	__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
Kojto	122:f9eeca106725	772	{
Kojto	122:f9eeca106725	773	MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
Kojto	122:f9eeca106725	774	}
Kojto	122:f9eeca106725	775
Kojto	122:f9eeca106725	776	/**
Kojto	122:f9eeca106725	777	* @brief Get the resistor impedance
Kojto	122:f9eeca106725	778	* @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
Kojto	122:f9eeca106725	779	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	780	* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
Kojto	122:f9eeca106725	781	* @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
Kojto	122:f9eeca106725	782	*/
Kojto	122:f9eeca106725	783	__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
Kojto	122:f9eeca106725	784	{
Kojto	122:f9eeca106725	785	return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
Kojto	122:f9eeca106725	786	}
Kojto	122:f9eeca106725	787
Kojto	122:f9eeca106725	788	/**
Kojto	122:f9eeca106725	789	* @brief Enable battery charging
Kojto	122:f9eeca106725	790	* @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
Kojto	122:f9eeca106725	791	* @retval None
Kojto	122:f9eeca106725	792	*/
Kojto	122:f9eeca106725	793	__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
Kojto	122:f9eeca106725	794	{
Kojto	122:f9eeca106725	795	SET_BIT(PWR->CR4, PWR_CR4_VBE);
Kojto	122:f9eeca106725	796	}
Kojto	122:f9eeca106725	797
Kojto	122:f9eeca106725	798	/**
Kojto	122:f9eeca106725	799	* @brief Disable battery charging
Kojto	122:f9eeca106725	800	* @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
Kojto	122:f9eeca106725	801	* @retval None
Kojto	122:f9eeca106725	802	*/
Kojto	122:f9eeca106725	803	__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
Kojto	122:f9eeca106725	804	{
Kojto	122:f9eeca106725	805	CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
Kojto	122:f9eeca106725	806	}
Kojto	122:f9eeca106725	807
Kojto	122:f9eeca106725	808	/**
Kojto	122:f9eeca106725	809	* @brief Check if battery charging is enabled
Kojto	122:f9eeca106725	810	* @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
Kojto	122:f9eeca106725	811	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	812	*/
Kojto	122:f9eeca106725	813	__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
Kojto	122:f9eeca106725	814	{
Kojto	122:f9eeca106725	815	return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE));
Kojto	122:f9eeca106725	816	}
Kojto	122:f9eeca106725	817
Kojto	122:f9eeca106725	818	/**
Kojto	122:f9eeca106725	819	* @brief Set the Wake-Up pin polarity low for the event detection
Kojto	122:f9eeca106725	820	* @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
Kojto	122:f9eeca106725	821	* CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
Kojto	122:f9eeca106725	822	* CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
Kojto	122:f9eeca106725	823	* CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
Kojto	122:f9eeca106725	824	* CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
Kojto	122:f9eeca106725	825	* @param WakeUpPin This parameter can be one of the following values:
Kojto	122:f9eeca106725	826	* @arg @ref LL_PWR_WAKEUP_PIN1
Kojto	122:f9eeca106725	827	* @arg @ref LL_PWR_WAKEUP_PIN2
Kojto	122:f9eeca106725	828	* @arg @ref LL_PWR_WAKEUP_PIN3
Kojto	122:f9eeca106725	829	* @arg @ref LL_PWR_WAKEUP_PIN4
Kojto	122:f9eeca106725	830	* @arg @ref LL_PWR_WAKEUP_PIN5
Kojto	122:f9eeca106725	831	* @retval None
Kojto	122:f9eeca106725	832	*/
Kojto	122:f9eeca106725	833	__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
Kojto	122:f9eeca106725	834	{
Kojto	122:f9eeca106725	835	SET_BIT(PWR->CR4, WakeUpPin);
Kojto	122:f9eeca106725	836	}
Kojto	122:f9eeca106725	837
Kojto	122:f9eeca106725	838	/**
Kojto	122:f9eeca106725	839	* @brief Set the Wake-Up pin polarity high for the event detection
Kojto	122:f9eeca106725	840	* @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
Kojto	122:f9eeca106725	841	* CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
Kojto	122:f9eeca106725	842	* CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
Kojto	122:f9eeca106725	843	* CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
Kojto	122:f9eeca106725	844	* CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
Kojto	122:f9eeca106725	845	* @param WakeUpPin This parameter can be one of the following values:
Kojto	122:f9eeca106725	846	* @arg @ref LL_PWR_WAKEUP_PIN1
Kojto	122:f9eeca106725	847	* @arg @ref LL_PWR_WAKEUP_PIN2
Kojto	122:f9eeca106725	848	* @arg @ref LL_PWR_WAKEUP_PIN3
Kojto	122:f9eeca106725	849	* @arg @ref LL_PWR_WAKEUP_PIN4
Kojto	122:f9eeca106725	850	* @arg @ref LL_PWR_WAKEUP_PIN5
Kojto	122:f9eeca106725	851	* @retval None
Kojto	122:f9eeca106725	852	*/
Kojto	122:f9eeca106725	853	__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
Kojto	122:f9eeca106725	854	{
Kojto	122:f9eeca106725	855	CLEAR_BIT(PWR->CR4, WakeUpPin);
Kojto	122:f9eeca106725	856	}
Kojto	122:f9eeca106725	857
Kojto	122:f9eeca106725	858	/**
Kojto	122:f9eeca106725	859	* @brief Get the Wake-Up pin polarity for the event detection
Kojto	122:f9eeca106725	860	* @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
Kojto	122:f9eeca106725	861	* CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
Kojto	122:f9eeca106725	862	* CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
Kojto	122:f9eeca106725	863	* CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
Kojto	122:f9eeca106725	864	* CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
Kojto	122:f9eeca106725	865	* @param WakeUpPin This parameter can be one of the following values:
Kojto	122:f9eeca106725	866	* @arg @ref LL_PWR_WAKEUP_PIN1
Kojto	122:f9eeca106725	867	* @arg @ref LL_PWR_WAKEUP_PIN2
Kojto	122:f9eeca106725	868	* @arg @ref LL_PWR_WAKEUP_PIN3
Kojto	122:f9eeca106725	869	* @arg @ref LL_PWR_WAKEUP_PIN4
Kojto	122:f9eeca106725	870	* @arg @ref LL_PWR_WAKEUP_PIN5
Kojto	122:f9eeca106725	871	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	872	*/
Kojto	122:f9eeca106725	873	__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
Kojto	122:f9eeca106725	874	{
Kojto	122:f9eeca106725	875	return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin));
Kojto	122:f9eeca106725	876	}
Kojto	122:f9eeca106725	877
Kojto	122:f9eeca106725	878	/**
Kojto	122:f9eeca106725	879	* @brief Enable GPIO pull-up state in Standby and Shutdown modes
Kojto	122:f9eeca106725	880	* @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
Kojto	122:f9eeca106725	881	* PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
Kojto	122:f9eeca106725	882	* PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
Kojto	122:f9eeca106725	883	* PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
Kojto	122:f9eeca106725	884	* PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
Kojto	122:f9eeca106725	885	* PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
Kojto	122:f9eeca106725	886	* PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
AnnaBridge	145:64910690c574	887	* PUCRH PU0-15 LL_PWR_EnableGPIOPullUp\n
AnnaBridge	145:64910690c574	888	* PUCRI PU0-11 LL_PWR_EnableGPIOPullUp
Kojto	122:f9eeca106725	889	* @param GPIO This parameter can be one of the following values:
Kojto	122:f9eeca106725	890	* @arg @ref LL_PWR_GPIO_A
Kojto	122:f9eeca106725	891	* @arg @ref LL_PWR_GPIO_B
Kojto	122:f9eeca106725	892	* @arg @ref LL_PWR_GPIO_C
Kojto	122:f9eeca106725	893	* @arg @ref LL_PWR_GPIO_D
Kojto	122:f9eeca106725	894	* @arg @ref LL_PWR_GPIO_E
Kojto	122:f9eeca106725	895	* @arg @ref LL_PWR_GPIO_F (*)
Kojto	122:f9eeca106725	896	* @arg @ref LL_PWR_GPIO_G (*)
Kojto	122:f9eeca106725	897	* @arg @ref LL_PWR_GPIO_H
AnnaBridge	145:64910690c574	898	* @arg @ref LL_PWR_GPIO_I (*)
Kojto	122:f9eeca106725	899	*
Kojto	122:f9eeca106725	900	* (*) value not defined in all devices
Kojto	122:f9eeca106725	901	* @param GPIONumber This parameter can be one of the following values:
Kojto	122:f9eeca106725	902	* @arg @ref LL_PWR_GPIO_BIT_0
Kojto	122:f9eeca106725	903	* @arg @ref LL_PWR_GPIO_BIT_1
Kojto	122:f9eeca106725	904	* @arg @ref LL_PWR_GPIO_BIT_2
Kojto	122:f9eeca106725	905	* @arg @ref LL_PWR_GPIO_BIT_3
Kojto	122:f9eeca106725	906	* @arg @ref LL_PWR_GPIO_BIT_4
Kojto	122:f9eeca106725	907	* @arg @ref LL_PWR_GPIO_BIT_5
Kojto	122:f9eeca106725	908	* @arg @ref LL_PWR_GPIO_BIT_6
Kojto	122:f9eeca106725	909	* @arg @ref LL_PWR_GPIO_BIT_7
Kojto	122:f9eeca106725	910	* @arg @ref LL_PWR_GPIO_BIT_8
Kojto	122:f9eeca106725	911	* @arg @ref LL_PWR_GPIO_BIT_9
Kojto	122:f9eeca106725	912	* @arg @ref LL_PWR_GPIO_BIT_10
Kojto	122:f9eeca106725	913	* @arg @ref LL_PWR_GPIO_BIT_11
Kojto	122:f9eeca106725	914	* @arg @ref LL_PWR_GPIO_BIT_12
Kojto	122:f9eeca106725	915	* @arg @ref LL_PWR_GPIO_BIT_13
Kojto	122:f9eeca106725	916	* @arg @ref LL_PWR_GPIO_BIT_14
Kojto	122:f9eeca106725	917	* @arg @ref LL_PWR_GPIO_BIT_15
Kojto	122:f9eeca106725	918	* @retval None
Kojto	122:f9eeca106725	919	*/
Kojto	122:f9eeca106725	920	__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
Kojto	122:f9eeca106725	921	{
Kojto	122:f9eeca106725	922	SET_BIT(((uint32_t )GPIO), GPIONumber);
Kojto	122:f9eeca106725	923	}
Kojto	122:f9eeca106725	924
Kojto	122:f9eeca106725	925	/**
Kojto	122:f9eeca106725	926	* @brief Disable GPIO pull-up state in Standby and Shutdown modes
Kojto	122:f9eeca106725	927	* @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
Kojto	122:f9eeca106725	928	* PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
Kojto	122:f9eeca106725	929	* PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
Kojto	122:f9eeca106725	930	* PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
Kojto	122:f9eeca106725	931	* PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
Kojto	122:f9eeca106725	932	* PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
Kojto	122:f9eeca106725	933	* PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
AnnaBridge	145:64910690c574	934	* PUCRH PU0-15 LL_PWR_DisableGPIOPullUp\n
AnnaBridge	145:64910690c574	935	* PUCRI PU0-11 LL_PWR_DisableGPIOPullUp
Kojto	122:f9eeca106725	936	* @param GPIO This parameter can be one of the following values:
Kojto	122:f9eeca106725	937	* @arg @ref LL_PWR_GPIO_A
Kojto	122:f9eeca106725	938	* @arg @ref LL_PWR_GPIO_B
Kojto	122:f9eeca106725	939	* @arg @ref LL_PWR_GPIO_C
Kojto	122:f9eeca106725	940	* @arg @ref LL_PWR_GPIO_D
Kojto	122:f9eeca106725	941	* @arg @ref LL_PWR_GPIO_E
Kojto	122:f9eeca106725	942	* @arg @ref LL_PWR_GPIO_F (*)
Kojto	122:f9eeca106725	943	* @arg @ref LL_PWR_GPIO_G (*)
Kojto	122:f9eeca106725	944	* @arg @ref LL_PWR_GPIO_H
AnnaBridge	145:64910690c574	945	* @arg @ref LL_PWR_GPIO_I (*)
Kojto	122:f9eeca106725	946	*
Kojto	122:f9eeca106725	947	* (*) value not defined in all devices
Kojto	122:f9eeca106725	948	* @param GPIONumber This parameter can be one of the following values:
Kojto	122:f9eeca106725	949	* @arg @ref LL_PWR_GPIO_BIT_0
Kojto	122:f9eeca106725	950	* @arg @ref LL_PWR_GPIO_BIT_1
Kojto	122:f9eeca106725	951	* @arg @ref LL_PWR_GPIO_BIT_2
Kojto	122:f9eeca106725	952	* @arg @ref LL_PWR_GPIO_BIT_3
Kojto	122:f9eeca106725	953	* @arg @ref LL_PWR_GPIO_BIT_4
Kojto	122:f9eeca106725	954	* @arg @ref LL_PWR_GPIO_BIT_5
Kojto	122:f9eeca106725	955	* @arg @ref LL_PWR_GPIO_BIT_6
Kojto	122:f9eeca106725	956	* @arg @ref LL_PWR_GPIO_BIT_7
Kojto	122:f9eeca106725	957	* @arg @ref LL_PWR_GPIO_BIT_8
Kojto	122:f9eeca106725	958	* @arg @ref LL_PWR_GPIO_BIT_9
Kojto	122:f9eeca106725	959	* @arg @ref LL_PWR_GPIO_BIT_10
Kojto	122:f9eeca106725	960	* @arg @ref LL_PWR_GPIO_BIT_11
Kojto	122:f9eeca106725	961	* @arg @ref LL_PWR_GPIO_BIT_12
Kojto	122:f9eeca106725	962	* @arg @ref LL_PWR_GPIO_BIT_13
Kojto	122:f9eeca106725	963	* @arg @ref LL_PWR_GPIO_BIT_14
Kojto	122:f9eeca106725	964	* @arg @ref LL_PWR_GPIO_BIT_15
Kojto	122:f9eeca106725	965	* @retval None
Kojto	122:f9eeca106725	966	*/
Kojto	122:f9eeca106725	967	__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
Kojto	122:f9eeca106725	968	{
Kojto	122:f9eeca106725	969	CLEAR_BIT(((uint32_t )GPIO), GPIONumber);
Kojto	122:f9eeca106725	970	}
Kojto	122:f9eeca106725	971
Kojto	122:f9eeca106725	972	/**
Kojto	122:f9eeca106725	973	* @brief Check if GPIO pull-up state is enabled
Kojto	122:f9eeca106725	974	* @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
Kojto	122:f9eeca106725	975	* PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
Kojto	122:f9eeca106725	976	* PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
Kojto	122:f9eeca106725	977	* PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
Kojto	122:f9eeca106725	978	* PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
Kojto	122:f9eeca106725	979	* PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
Kojto	122:f9eeca106725	980	* PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
AnnaBridge	145:64910690c574	981	* PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
AnnaBridge	145:64910690c574	982	* PUCRI PU0-11 LL_PWR_IsEnabledGPIOPullUp
Kojto	122:f9eeca106725	983	* @param GPIO This parameter can be one of the following values:
Kojto	122:f9eeca106725	984	* @arg @ref LL_PWR_GPIO_A
Kojto	122:f9eeca106725	985	* @arg @ref LL_PWR_GPIO_B
Kojto	122:f9eeca106725	986	* @arg @ref LL_PWR_GPIO_C
Kojto	122:f9eeca106725	987	* @arg @ref LL_PWR_GPIO_D
Kojto	122:f9eeca106725	988	* @arg @ref LL_PWR_GPIO_E
Kojto	122:f9eeca106725	989	* @arg @ref LL_PWR_GPIO_F (*)
Kojto	122:f9eeca106725	990	* @arg @ref LL_PWR_GPIO_G (*)
Kojto	122:f9eeca106725	991	* @arg @ref LL_PWR_GPIO_H
AnnaBridge	145:64910690c574	992	* @arg @ref LL_PWR_GPIO_I (*)
Kojto	122:f9eeca106725	993	*
Kojto	122:f9eeca106725	994	* (*) value not defined in all devices
Kojto	122:f9eeca106725	995	* @param GPIONumber This parameter can be one of the following values:
Kojto	122:f9eeca106725	996	* @arg @ref LL_PWR_GPIO_BIT_0
Kojto	122:f9eeca106725	997	* @arg @ref LL_PWR_GPIO_BIT_1
Kojto	122:f9eeca106725	998	* @arg @ref LL_PWR_GPIO_BIT_2
Kojto	122:f9eeca106725	999	* @arg @ref LL_PWR_GPIO_BIT_3
Kojto	122:f9eeca106725	1000	* @arg @ref LL_PWR_GPIO_BIT_4
Kojto	122:f9eeca106725	1001	* @arg @ref LL_PWR_GPIO_BIT_5
Kojto	122:f9eeca106725	1002	* @arg @ref LL_PWR_GPIO_BIT_6
Kojto	122:f9eeca106725	1003	* @arg @ref LL_PWR_GPIO_BIT_7
Kojto	122:f9eeca106725	1004	* @arg @ref LL_PWR_GPIO_BIT_8
Kojto	122:f9eeca106725	1005	* @arg @ref LL_PWR_GPIO_BIT_9
Kojto	122:f9eeca106725	1006	* @arg @ref LL_PWR_GPIO_BIT_10
Kojto	122:f9eeca106725	1007	* @arg @ref LL_PWR_GPIO_BIT_11
Kojto	122:f9eeca106725	1008	* @arg @ref LL_PWR_GPIO_BIT_12
Kojto	122:f9eeca106725	1009	* @arg @ref LL_PWR_GPIO_BIT_13
Kojto	122:f9eeca106725	1010	* @arg @ref LL_PWR_GPIO_BIT_14
Kojto	122:f9eeca106725	1011	* @arg @ref LL_PWR_GPIO_BIT_15
Kojto	122:f9eeca106725	1012	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1013	*/
Kojto	122:f9eeca106725	1014	__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
Kojto	122:f9eeca106725	1015	{
Kojto	122:f9eeca106725	1016	return (READ_BIT(((uint32_t )(GPIO)), GPIONumber) == (GPIONumber));
Kojto	122:f9eeca106725	1017	}
Kojto	122:f9eeca106725	1018
Kojto	122:f9eeca106725	1019	/**
Kojto	122:f9eeca106725	1020	* @brief Enable GPIO pull-down state in Standby and Shutdown modes
Kojto	122:f9eeca106725	1021	* @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
Kojto	122:f9eeca106725	1022	* PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
Kojto	122:f9eeca106725	1023	* PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
Kojto	122:f9eeca106725	1024	* PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
Kojto	122:f9eeca106725	1025	* PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
Kojto	122:f9eeca106725	1026	* PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
Kojto	122:f9eeca106725	1027	* PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
AnnaBridge	145:64910690c574	1028	* PDCRH PD0-15 LL_PWR_EnableGPIOPullDown\n
AnnaBridge	145:64910690c574	1029	* PDCRI PD0-11 LL_PWR_EnableGPIOPullDown
Kojto	122:f9eeca106725	1030	* @param GPIO This parameter can be one of the following values:
Kojto	122:f9eeca106725	1031	* @arg @ref LL_PWR_GPIO_A
Kojto	122:f9eeca106725	1032	* @arg @ref LL_PWR_GPIO_B
Kojto	122:f9eeca106725	1033	* @arg @ref LL_PWR_GPIO_C
Kojto	122:f9eeca106725	1034	* @arg @ref LL_PWR_GPIO_D
Kojto	122:f9eeca106725	1035	* @arg @ref LL_PWR_GPIO_E
Kojto	122:f9eeca106725	1036	* @arg @ref LL_PWR_GPIO_F (*)
Kojto	122:f9eeca106725	1037	* @arg @ref LL_PWR_GPIO_G (*)
Kojto	122:f9eeca106725	1038	* @arg @ref LL_PWR_GPIO_H
AnnaBridge	145:64910690c574	1039	* @arg @ref LL_PWR_GPIO_I (*)
Kojto	122:f9eeca106725	1040	*
Kojto	122:f9eeca106725	1041	* (*) value not defined in all devices
Kojto	122:f9eeca106725	1042	* @param GPIONumber This parameter can be one of the following values:
Kojto	122:f9eeca106725	1043	* @arg @ref LL_PWR_GPIO_BIT_0
Kojto	122:f9eeca106725	1044	* @arg @ref LL_PWR_GPIO_BIT_1
Kojto	122:f9eeca106725	1045	* @arg @ref LL_PWR_GPIO_BIT_2
Kojto	122:f9eeca106725	1046	* @arg @ref LL_PWR_GPIO_BIT_3
Kojto	122:f9eeca106725	1047	* @arg @ref LL_PWR_GPIO_BIT_4
Kojto	122:f9eeca106725	1048	* @arg @ref LL_PWR_GPIO_BIT_5
Kojto	122:f9eeca106725	1049	* @arg @ref LL_PWR_GPIO_BIT_6
Kojto	122:f9eeca106725	1050	* @arg @ref LL_PWR_GPIO_BIT_7
Kojto	122:f9eeca106725	1051	* @arg @ref LL_PWR_GPIO_BIT_8
Kojto	122:f9eeca106725	1052	* @arg @ref LL_PWR_GPIO_BIT_9
Kojto	122:f9eeca106725	1053	* @arg @ref LL_PWR_GPIO_BIT_10
Kojto	122:f9eeca106725	1054	* @arg @ref LL_PWR_GPIO_BIT_11
Kojto	122:f9eeca106725	1055	* @arg @ref LL_PWR_GPIO_BIT_12
Kojto	122:f9eeca106725	1056	* @arg @ref LL_PWR_GPIO_BIT_13
Kojto	122:f9eeca106725	1057	* @arg @ref LL_PWR_GPIO_BIT_14
Kojto	122:f9eeca106725	1058	* @arg @ref LL_PWR_GPIO_BIT_15
Kojto	122:f9eeca106725	1059	* @retval None
Kojto	122:f9eeca106725	1060	*/
Kojto	122:f9eeca106725	1061	__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
Kojto	122:f9eeca106725	1062	{
Kojto	122:f9eeca106725	1063	register uint32_t temp = (uint32_t)(GPIO) + 4;
Kojto	122:f9eeca106725	1064	SET_BIT(((uint32_t )(temp)), GPIONumber);
Kojto	122:f9eeca106725	1065	}
Kojto	122:f9eeca106725	1066
Kojto	122:f9eeca106725	1067	/**
Kojto	122:f9eeca106725	1068	* @brief Disable GPIO pull-down state in Standby and Shutdown modes
Kojto	122:f9eeca106725	1069	* @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
Kojto	122:f9eeca106725	1070	* PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
Kojto	122:f9eeca106725	1071	* PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
Kojto	122:f9eeca106725	1072	* PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
Kojto	122:f9eeca106725	1073	* PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
Kojto	122:f9eeca106725	1074	* PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
Kojto	122:f9eeca106725	1075	* PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
AnnaBridge	145:64910690c574	1076	* PDCRH PD0-15 LL_PWR_DisableGPIOPullDown\n
AnnaBridge	145:64910690c574	1077	* PDCRI PD0-11 LL_PWR_DisableGPIOPullDown
Kojto	122:f9eeca106725	1078	* @param GPIO This parameter can be one of the following values:
Kojto	122:f9eeca106725	1079	* @arg @ref LL_PWR_GPIO_A
Kojto	122:f9eeca106725	1080	* @arg @ref LL_PWR_GPIO_B
Kojto	122:f9eeca106725	1081	* @arg @ref LL_PWR_GPIO_C
Kojto	122:f9eeca106725	1082	* @arg @ref LL_PWR_GPIO_D
Kojto	122:f9eeca106725	1083	* @arg @ref LL_PWR_GPIO_E
Kojto	122:f9eeca106725	1084	* @arg @ref LL_PWR_GPIO_F (*)
Kojto	122:f9eeca106725	1085	* @arg @ref LL_PWR_GPIO_G (*)
Kojto	122:f9eeca106725	1086	* @arg @ref LL_PWR_GPIO_H
AnnaBridge	145:64910690c574	1087	* @arg @ref LL_PWR_GPIO_I (*)
Kojto	122:f9eeca106725	1088	*
Kojto	122:f9eeca106725	1089	* (*) value not defined in all devices
Kojto	122:f9eeca106725	1090	* @param GPIONumber This parameter can be one of the following values:
Kojto	122:f9eeca106725	1091	* @arg @ref LL_PWR_GPIO_BIT_0
Kojto	122:f9eeca106725	1092	* @arg @ref LL_PWR_GPIO_BIT_1
Kojto	122:f9eeca106725	1093	* @arg @ref LL_PWR_GPIO_BIT_2
Kojto	122:f9eeca106725	1094	* @arg @ref LL_PWR_GPIO_BIT_3
Kojto	122:f9eeca106725	1095	* @arg @ref LL_PWR_GPIO_BIT_4
Kojto	122:f9eeca106725	1096	* @arg @ref LL_PWR_GPIO_BIT_5
Kojto	122:f9eeca106725	1097	* @arg @ref LL_PWR_GPIO_BIT_6
Kojto	122:f9eeca106725	1098	* @arg @ref LL_PWR_GPIO_BIT_7
Kojto	122:f9eeca106725	1099	* @arg @ref LL_PWR_GPIO_BIT_8
Kojto	122:f9eeca106725	1100	* @arg @ref LL_PWR_GPIO_BIT_9
Kojto	122:f9eeca106725	1101	* @arg @ref LL_PWR_GPIO_BIT_10
Kojto	122:f9eeca106725	1102	* @arg @ref LL_PWR_GPIO_BIT_11
Kojto	122:f9eeca106725	1103	* @arg @ref LL_PWR_GPIO_BIT_12
Kojto	122:f9eeca106725	1104	* @arg @ref LL_PWR_GPIO_BIT_13
Kojto	122:f9eeca106725	1105	* @arg @ref LL_PWR_GPIO_BIT_14
Kojto	122:f9eeca106725	1106	* @arg @ref LL_PWR_GPIO_BIT_15
Kojto	122:f9eeca106725	1107	* @retval None
Kojto	122:f9eeca106725	1108	*/
Kojto	122:f9eeca106725	1109	__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
Kojto	122:f9eeca106725	1110	{
Kojto	122:f9eeca106725	1111	register uint32_t temp = (uint32_t)(GPIO) + 4;
Kojto	122:f9eeca106725	1112	CLEAR_BIT(((uint32_t )(temp)), GPIONumber);
Kojto	122:f9eeca106725	1113	}
Kojto	122:f9eeca106725	1114
Kojto	122:f9eeca106725	1115	/**
Kojto	122:f9eeca106725	1116	* @brief Check if GPIO pull-down state is enabled
Kojto	122:f9eeca106725	1117	* @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
Kojto	122:f9eeca106725	1118	* PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
Kojto	122:f9eeca106725	1119	* PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
Kojto	122:f9eeca106725	1120	* PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
Kojto	122:f9eeca106725	1121	* PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
Kojto	122:f9eeca106725	1122	* PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
Kojto	122:f9eeca106725	1123	* PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
AnnaBridge	145:64910690c574	1124	* PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
AnnaBridge	145:64910690c574	1125	* PDCRI PD0-11 LL_PWR_IsEnabledGPIOPullDown
Kojto	122:f9eeca106725	1126	* @param GPIO This parameter can be one of the following values:
Kojto	122:f9eeca106725	1127	* @arg @ref LL_PWR_GPIO_A
Kojto	122:f9eeca106725	1128	* @arg @ref LL_PWR_GPIO_B
Kojto	122:f9eeca106725	1129	* @arg @ref LL_PWR_GPIO_C
Kojto	122:f9eeca106725	1130	* @arg @ref LL_PWR_GPIO_D
Kojto	122:f9eeca106725	1131	* @arg @ref LL_PWR_GPIO_E
Kojto	122:f9eeca106725	1132	* @arg @ref LL_PWR_GPIO_F (*)
Kojto	122:f9eeca106725	1133	* @arg @ref LL_PWR_GPIO_G (*)
Kojto	122:f9eeca106725	1134	* @arg @ref LL_PWR_GPIO_H
AnnaBridge	145:64910690c574	1135	* @arg @ref LL_PWR_GPIO_I (*)
Kojto	122:f9eeca106725	1136	*
Kojto	122:f9eeca106725	1137	* (*) value not defined in all devices
Kojto	122:f9eeca106725	1138	* @param GPIONumber This parameter can be one of the following values:
Kojto	122:f9eeca106725	1139	* @arg @ref LL_PWR_GPIO_BIT_0
Kojto	122:f9eeca106725	1140	* @arg @ref LL_PWR_GPIO_BIT_1
Kojto	122:f9eeca106725	1141	* @arg @ref LL_PWR_GPIO_BIT_2
Kojto	122:f9eeca106725	1142	* @arg @ref LL_PWR_GPIO_BIT_3
Kojto	122:f9eeca106725	1143	* @arg @ref LL_PWR_GPIO_BIT_4
Kojto	122:f9eeca106725	1144	* @arg @ref LL_PWR_GPIO_BIT_5
Kojto	122:f9eeca106725	1145	* @arg @ref LL_PWR_GPIO_BIT_6
Kojto	122:f9eeca106725	1146	* @arg @ref LL_PWR_GPIO_BIT_7
Kojto	122:f9eeca106725	1147	* @arg @ref LL_PWR_GPIO_BIT_8
Kojto	122:f9eeca106725	1148	* @arg @ref LL_PWR_GPIO_BIT_9
Kojto	122:f9eeca106725	1149	* @arg @ref LL_PWR_GPIO_BIT_10
Kojto	122:f9eeca106725	1150	* @arg @ref LL_PWR_GPIO_BIT_11
Kojto	122:f9eeca106725	1151	* @arg @ref LL_PWR_GPIO_BIT_12
Kojto	122:f9eeca106725	1152	* @arg @ref LL_PWR_GPIO_BIT_13
Kojto	122:f9eeca106725	1153	* @arg @ref LL_PWR_GPIO_BIT_14
Kojto	122:f9eeca106725	1154	* @arg @ref LL_PWR_GPIO_BIT_15
Kojto	122:f9eeca106725	1155	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1156	*/
Kojto	122:f9eeca106725	1157	__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
Kojto	122:f9eeca106725	1158	{
Kojto	122:f9eeca106725	1159	register uint32_t temp = (uint32_t)(GPIO) + 4;
Kojto	122:f9eeca106725	1160	return (READ_BIT(((uint32_t )(temp)), GPIONumber) == (GPIONumber));
Kojto	122:f9eeca106725	1161	}
Kojto	122:f9eeca106725	1162
Kojto	122:f9eeca106725	1163	/**
Kojto	122:f9eeca106725	1164	* @}
Kojto	122:f9eeca106725	1165	*/
Kojto	122:f9eeca106725	1166
Kojto	122:f9eeca106725	1167	/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
Kojto	122:f9eeca106725	1168	* @{
Kojto	122:f9eeca106725	1169	*/
Kojto	122:f9eeca106725	1170
Kojto	122:f9eeca106725	1171	/**
Kojto	122:f9eeca106725	1172	* @brief Get Internal Wake-up line Flag
Kojto	122:f9eeca106725	1173	* @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
Kojto	122:f9eeca106725	1174	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1175	*/
Kojto	122:f9eeca106725	1176	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
Kojto	122:f9eeca106725	1177	{
Kojto	122:f9eeca106725	1178	return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI));
Kojto	122:f9eeca106725	1179	}
Kojto	122:f9eeca106725	1180
Kojto	122:f9eeca106725	1181	/**
Kojto	122:f9eeca106725	1182	* @brief Get Stand-By Flag
Kojto	122:f9eeca106725	1183	* @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
Kojto	122:f9eeca106725	1184	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1185	*/
Kojto	122:f9eeca106725	1186	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
Kojto	122:f9eeca106725	1187	{
Kojto	122:f9eeca106725	1188	return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF));
Kojto	122:f9eeca106725	1189	}
Kojto	122:f9eeca106725	1190
Kojto	122:f9eeca106725	1191	/**
Kojto	122:f9eeca106725	1192	* @brief Get Wake-up Flag 5
Kojto	122:f9eeca106725	1193	* @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
Kojto	122:f9eeca106725	1194	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1195	*/
Kojto	122:f9eeca106725	1196	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
Kojto	122:f9eeca106725	1197	{
Kojto	122:f9eeca106725	1198	return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5));
Kojto	122:f9eeca106725	1199	}
Kojto	122:f9eeca106725	1200
Kojto	122:f9eeca106725	1201	/**
Kojto	122:f9eeca106725	1202	* @brief Get Wake-up Flag 4
Kojto	122:f9eeca106725	1203	* @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
Kojto	122:f9eeca106725	1204	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1205	*/
Kojto	122:f9eeca106725	1206	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
Kojto	122:f9eeca106725	1207	{
Kojto	122:f9eeca106725	1208	return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4));
Kojto	122:f9eeca106725	1209	}
Kojto	122:f9eeca106725	1210
Kojto	122:f9eeca106725	1211	/**
Kojto	122:f9eeca106725	1212	* @brief Get Wake-up Flag 3
Kojto	122:f9eeca106725	1213	* @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
Kojto	122:f9eeca106725	1214	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1215	*/
Kojto	122:f9eeca106725	1216	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
Kojto	122:f9eeca106725	1217	{
Kojto	122:f9eeca106725	1218	return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3));
Kojto	122:f9eeca106725	1219	}
Kojto	122:f9eeca106725	1220
Kojto	122:f9eeca106725	1221	/**
Kojto	122:f9eeca106725	1222	* @brief Get Wake-up Flag 2
Kojto	122:f9eeca106725	1223	* @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
Kojto	122:f9eeca106725	1224	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1225	*/
Kojto	122:f9eeca106725	1226	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
Kojto	122:f9eeca106725	1227	{
Kojto	122:f9eeca106725	1228	return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2));
Kojto	122:f9eeca106725	1229	}
Kojto	122:f9eeca106725	1230
Kojto	122:f9eeca106725	1231	/**
Kojto	122:f9eeca106725	1232	* @brief Get Wake-up Flag 1
Kojto	122:f9eeca106725	1233	* @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
Kojto	122:f9eeca106725	1234	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1235	*/
Kojto	122:f9eeca106725	1236	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
Kojto	122:f9eeca106725	1237	{
Kojto	122:f9eeca106725	1238	return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1));
Kojto	122:f9eeca106725	1239	}
Kojto	122:f9eeca106725	1240
Kojto	122:f9eeca106725	1241	/**
Kojto	122:f9eeca106725	1242	* @brief Clear Stand-By Flag
Kojto	122:f9eeca106725	1243	* @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
Kojto	122:f9eeca106725	1244	* @retval None
Kojto	122:f9eeca106725	1245	*/
Kojto	122:f9eeca106725	1246	__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
Kojto	122:f9eeca106725	1247	{
Kojto	122:f9eeca106725	1248	WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
Kojto	122:f9eeca106725	1249	}
Kojto	122:f9eeca106725	1250
Kojto	122:f9eeca106725	1251	/**
Kojto	122:f9eeca106725	1252	* @brief Clear Wake-up Flags
Kojto	122:f9eeca106725	1253	* @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
Kojto	122:f9eeca106725	1254	* @retval None
Kojto	122:f9eeca106725	1255	*/
Kojto	122:f9eeca106725	1256	__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
Kojto	122:f9eeca106725	1257	{
Kojto	122:f9eeca106725	1258	WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
Kojto	122:f9eeca106725	1259	}
Kojto	122:f9eeca106725	1260
Kojto	122:f9eeca106725	1261	/**
Kojto	122:f9eeca106725	1262	* @brief Clear Wake-up Flag 5
Kojto	122:f9eeca106725	1263	* @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
Kojto	122:f9eeca106725	1264	* @retval None
Kojto	122:f9eeca106725	1265	*/
Kojto	122:f9eeca106725	1266	__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
Kojto	122:f9eeca106725	1267	{
Kojto	122:f9eeca106725	1268	WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
Kojto	122:f9eeca106725	1269	}
Kojto	122:f9eeca106725	1270
Kojto	122:f9eeca106725	1271	/**
Kojto	122:f9eeca106725	1272	* @brief Clear Wake-up Flag 4
Kojto	122:f9eeca106725	1273	* @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
Kojto	122:f9eeca106725	1274	* @retval None
Kojto	122:f9eeca106725	1275	*/
Kojto	122:f9eeca106725	1276	__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
Kojto	122:f9eeca106725	1277	{
Kojto	122:f9eeca106725	1278	WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
Kojto	122:f9eeca106725	1279	}
Kojto	122:f9eeca106725	1280
Kojto	122:f9eeca106725	1281	/**
Kojto	122:f9eeca106725	1282	* @brief Clear Wake-up Flag 3
Kojto	122:f9eeca106725	1283	* @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
Kojto	122:f9eeca106725	1284	* @retval None
Kojto	122:f9eeca106725	1285	*/
Kojto	122:f9eeca106725	1286	__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
Kojto	122:f9eeca106725	1287	{
Kojto	122:f9eeca106725	1288	WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
Kojto	122:f9eeca106725	1289	}
Kojto	122:f9eeca106725	1290
Kojto	122:f9eeca106725	1291	/**
Kojto	122:f9eeca106725	1292	* @brief Clear Wake-up Flag 2
Kojto	122:f9eeca106725	1293	* @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
Kojto	122:f9eeca106725	1294	* @retval None
Kojto	122:f9eeca106725	1295	*/
Kojto	122:f9eeca106725	1296	__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
Kojto	122:f9eeca106725	1297	{
Kojto	122:f9eeca106725	1298	WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
Kojto	122:f9eeca106725	1299	}
Kojto	122:f9eeca106725	1300
Kojto	122:f9eeca106725	1301	/**
Kojto	122:f9eeca106725	1302	* @brief Clear Wake-up Flag 1
Kojto	122:f9eeca106725	1303	* @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
Kojto	122:f9eeca106725	1304	* @retval None
Kojto	122:f9eeca106725	1305	*/
Kojto	122:f9eeca106725	1306	__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
Kojto	122:f9eeca106725	1307	{
Kojto	122:f9eeca106725	1308	WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
Kojto	122:f9eeca106725	1309	}
Kojto	122:f9eeca106725	1310
Kojto	122:f9eeca106725	1311	/**
Kojto	122:f9eeca106725	1312	* @brief Indicate whether VDDA voltage is below or above PVM4 threshold
Kojto	122:f9eeca106725	1313	* @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
Kojto	122:f9eeca106725	1314	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1315	*/
Kojto	122:f9eeca106725	1316	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
Kojto	122:f9eeca106725	1317	{
Kojto	122:f9eeca106725	1318	return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4));
Kojto	122:f9eeca106725	1319	}
Kojto	122:f9eeca106725	1320
Kojto	122:f9eeca106725	1321	/**
Kojto	122:f9eeca106725	1322	* @brief Indicate whether VDDA voltage is below or above PVM3 threshold
Kojto	122:f9eeca106725	1323	* @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
Kojto	122:f9eeca106725	1324	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1325	*/
Kojto	122:f9eeca106725	1326	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
Kojto	122:f9eeca106725	1327	{
Kojto	122:f9eeca106725	1328	return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3));
Kojto	122:f9eeca106725	1329	}
Kojto	122:f9eeca106725	1330
Kojto	122:f9eeca106725	1331	#if defined(PWR_SR2_PVMO2)
Kojto	122:f9eeca106725	1332	/**
Kojto	122:f9eeca106725	1333	* @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
Kojto	122:f9eeca106725	1334	* @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
Kojto	122:f9eeca106725	1335	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1336	*/
Kojto	122:f9eeca106725	1337	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
Kojto	122:f9eeca106725	1338	{
Kojto	122:f9eeca106725	1339	return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2));
Kojto	122:f9eeca106725	1340	}
Kojto	122:f9eeca106725	1341	#endif /* PWR_SR2_PVMO2 */
Kojto	122:f9eeca106725	1342
AnnaBridge	145:64910690c574	1343	#if defined(PWR_SR2_PVMO1)
Kojto	122:f9eeca106725	1344	/**
Kojto	122:f9eeca106725	1345	* @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
Kojto	122:f9eeca106725	1346	* @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
Kojto	122:f9eeca106725	1347	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1348	*/
Kojto	122:f9eeca106725	1349	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
Kojto	122:f9eeca106725	1350	{
Kojto	122:f9eeca106725	1351	return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1));
Kojto	122:f9eeca106725	1352	}
AnnaBridge	145:64910690c574	1353	#endif /* PWR_SR2_PVMO1 */
Kojto	122:f9eeca106725	1354
Kojto	122:f9eeca106725	1355	/**
Kojto	122:f9eeca106725	1356	* @brief Indicate whether VDD voltage is below or above the selected PVD threshold
Kojto	122:f9eeca106725	1357	* @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
Kojto	122:f9eeca106725	1358	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1359	*/
Kojto	122:f9eeca106725	1360	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
Kojto	122:f9eeca106725	1361	{
Kojto	122:f9eeca106725	1362	return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO));
Kojto	122:f9eeca106725	1363	}
Kojto	122:f9eeca106725	1364
Kojto	122:f9eeca106725	1365	/**
Kojto	122:f9eeca106725	1366	* @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
AnnaBridge	145:64910690c574	1367	* @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
Kojto	122:f9eeca106725	1368	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1369	*/
AnnaBridge	145:64910690c574	1370	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
Kojto	122:f9eeca106725	1371	{
Kojto	122:f9eeca106725	1372	return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF));
Kojto	122:f9eeca106725	1373	}
Kojto	122:f9eeca106725	1374
Kojto	122:f9eeca106725	1375	/**
Kojto	122:f9eeca106725	1376	* @brief Indicate whether the regulator is ready in main mode or is in low-power mode
Kojto	122:f9eeca106725	1377	* @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
Kojto	122:f9eeca106725	1378	* @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
Kojto	122:f9eeca106725	1379	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1380	*/
Kojto	122:f9eeca106725	1381	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
Kojto	122:f9eeca106725	1382	{
Kojto	122:f9eeca106725	1383	return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF));
Kojto	122:f9eeca106725	1384	}
Kojto	122:f9eeca106725	1385
Kojto	122:f9eeca106725	1386	/**
Kojto	122:f9eeca106725	1387	* @brief Indicate whether or not the low-power regulator is ready
Kojto	122:f9eeca106725	1388	* @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
Kojto	122:f9eeca106725	1389	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1390	*/
Kojto	122:f9eeca106725	1391	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
Kojto	122:f9eeca106725	1392	{
Kojto	122:f9eeca106725	1393	return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS));
Kojto	122:f9eeca106725	1394	}
Kojto	122:f9eeca106725	1395
AnnaBridge	145:64910690c574	1396	/**
AnnaBridge	145:64910690c574	1397	* @}
AnnaBridge	145:64910690c574	1398	*/
AnnaBridge	145:64910690c574	1399
Kojto	122:f9eeca106725	1400	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	1401	/** @defgroup PWR_LL_EF_Init De-initialization function
Kojto	122:f9eeca106725	1402	* @{
Kojto	122:f9eeca106725	1403	*/
Kojto	122:f9eeca106725	1404	ErrorStatus LL_PWR_DeInit(void);
Kojto	122:f9eeca106725	1405	/**
Kojto	122:f9eeca106725	1406	* @}
Kojto	122:f9eeca106725	1407	*/
Kojto	122:f9eeca106725	1408	#endif /* USE_FULL_LL_DRIVER */
Kojto	122:f9eeca106725	1409
AnnaBridge	145:64910690c574	1410	/** Legacy definitions for compatibility purpose
AnnaBridge	145:64910690c574	1411	@cond 0
AnnaBridge	145:64910690c574	1412	*/
AnnaBridge	145:64910690c574	1413	/* Old functions name kept for legacy purpose, to be replaced by the */
AnnaBridge	145:64910690c574	1414	/* current functions name. */
AnnaBridge	145:64910690c574	1415	#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
Kojto	122:f9eeca106725	1416	/**
AnnaBridge	145:64910690c574	1417	@endcond
Kojto	122:f9eeca106725	1418	*/
Kojto	122:f9eeca106725	1419
Kojto	122:f9eeca106725	1420	/**
Kojto	122:f9eeca106725	1421	* @}
Kojto	122:f9eeca106725	1422	*/
Kojto	122:f9eeca106725	1423
Kojto	122:f9eeca106725	1424	/**
Kojto	122:f9eeca106725	1425	* @}
Kojto	122:f9eeca106725	1426	*/
Kojto	122:f9eeca106725	1427
Kojto	122:f9eeca106725	1428	#endif /* defined(PWR) */
Kojto	122:f9eeca106725	1429
Kojto	122:f9eeca106725	1430	/**
Kojto	122:f9eeca106725	1431	* @}
Kojto	122:f9eeca106725	1432	*/
Kojto	122:f9eeca106725	1433
Kojto	122:f9eeca106725	1434	#ifdef __cplusplus
Kojto	122:f9eeca106725	1435	}
Kojto	122:f9eeca106725	1436	#endif
Kojto	122:f9eeca106725	1437
Kojto	122:f9eeca106725	1438	#endif /* __STM32L4xx_LL_PWR_H */
Kojto	122:f9eeca106725	1439
Kojto	122:f9eeca106725	1440	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/