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TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Parent:
128:9bcdf88f62b0 
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32l4xx_ll_cortex.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 21-April-2017
Kojto 122:f9eeca106725 7 * @brief Header file of CORTEX LL module.
Kojto 122:f9eeca106725 8 @verbatim
Kojto 122:f9eeca106725 9 ==============================================================================
Kojto 122:f9eeca106725 10 ##### How to use this driver #####
Kojto 122:f9eeca106725 11 ==============================================================================
Kojto 122:f9eeca106725 12 [..]
Kojto 122:f9eeca106725 13 The LL CORTEX driver contains a set of generic APIs that can be
Kojto 122:f9eeca106725 14 used by user:
Kojto 122:f9eeca106725 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
Kojto 122:f9eeca106725 16 functions
Kojto 122:f9eeca106725 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
Kojto 122:f9eeca106725 18 (+) MPU API to configure and enable regions
Kojto 122:f9eeca106725 19 (+) API to access to MCU info (CPUID register)
Kojto 122:f9eeca106725 20 (+) API to enable fault handler (SHCSR accesses)
Kojto 122:f9eeca106725 21
Kojto 122:f9eeca106725 22 @endverbatim
Kojto 122:f9eeca106725 23 ******************************************************************************
Kojto 122:f9eeca106725 24 * @attention
Kojto 122:f9eeca106725 25 *
AnnaBridge 145:64910690c574 26 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 27 *
Kojto 122:f9eeca106725 28 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 29 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 30 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 31 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 33 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 34 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 36 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 37 * without specific prior written permission.
Kojto 122:f9eeca106725 38 *
Kojto 122:f9eeca106725 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 49 *
Kojto 122:f9eeca106725 50 ******************************************************************************
Kojto 122:f9eeca106725 51 */
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 54 #ifndef __STM32L4xx_LL_CORTEX_H
Kojto 122:f9eeca106725 55 #define __STM32L4xx_LL_CORTEX_H
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57 #ifdef __cplusplus
Kojto 122:f9eeca106725 58 extern "C" {
Kojto 122:f9eeca106725 59 #endif
Kojto 122:f9eeca106725 60
Kojto 122:f9eeca106725 61 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 62 #include "stm32l4xx.h"
Kojto 122:f9eeca106725 63
Kojto 122:f9eeca106725 64 /** @addtogroup STM32L4xx_LL_Driver
Kojto 122:f9eeca106725 65 * @{
Kojto 122:f9eeca106725 66 */
Kojto 122:f9eeca106725 67
Kojto 122:f9eeca106725 68 /** @defgroup CORTEX_LL CORTEX
Kojto 122:f9eeca106725 69 * @{
Kojto 122:f9eeca106725 70 */
Kojto 122:f9eeca106725 71
Kojto 122:f9eeca106725 72 /* Private types -------------------------------------------------------------*/
Kojto 122:f9eeca106725 73 /* Private variables ---------------------------------------------------------*/
Kojto 122:f9eeca106725 74
Kojto 122:f9eeca106725 75 /* Private constants ---------------------------------------------------------*/
Kojto 122:f9eeca106725 76
Kojto 122:f9eeca106725 77 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 80 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 81 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
Kojto 122:f9eeca106725 82 * @{
Kojto 122:f9eeca106725 83 */
Kojto 122:f9eeca106725 84
Kojto 122:f9eeca106725 85 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
Kojto 122:f9eeca106725 86 * @{
Kojto 122:f9eeca106725 87 */
AnnaBridge 145:64910690c574 88 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 145:64910690c574 89 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
Kojto 122:f9eeca106725 90 /**
Kojto 122:f9eeca106725 91 * @}
Kojto 122:f9eeca106725 92 */
Kojto 122:f9eeca106725 93
Kojto 122:f9eeca106725 94 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
Kojto 122:f9eeca106725 95 * @{
Kojto 122:f9eeca106725 96 */
Kojto 122:f9eeca106725 97 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
Kojto 122:f9eeca106725 98 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
Kojto 122:f9eeca106725 99 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
Kojto 122:f9eeca106725 100 /**
Kojto 122:f9eeca106725 101 * @}
Kojto 122:f9eeca106725 102 */
Kojto 122:f9eeca106725 103
Kojto 122:f9eeca106725 104 #if __MPU_PRESENT
Kojto 122:f9eeca106725 105
Kojto 122:f9eeca106725 106 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
Kojto 122:f9eeca106725 107 * @{
Kojto 122:f9eeca106725 108 */
AnnaBridge 145:64910690c574 109 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
Kojto 122:f9eeca106725 110 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
Kojto 122:f9eeca106725 111 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
Kojto 122:f9eeca106725 112 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
Kojto 122:f9eeca106725 113 /**
Kojto 122:f9eeca106725 114 * @}
Kojto 122:f9eeca106725 115 */
Kojto 122:f9eeca106725 116
Kojto 122:f9eeca106725 117 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
Kojto 122:f9eeca106725 118 * @{
Kojto 122:f9eeca106725 119 */
AnnaBridge 145:64910690c574 120 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 145:64910690c574 121 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 145:64910690c574 122 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 145:64910690c574 123 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 145:64910690c574 124 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 145:64910690c574 125 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 145:64910690c574 126 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 145:64910690c574 127 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
Kojto 122:f9eeca106725 128 /**
Kojto 122:f9eeca106725 129 * @}
Kojto 122:f9eeca106725 130 */
Kojto 122:f9eeca106725 131
Kojto 122:f9eeca106725 132 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
Kojto 122:f9eeca106725 133 * @{
Kojto 122:f9eeca106725 134 */
AnnaBridge 145:64910690c574 135 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 145:64910690c574 136 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 145:64910690c574 137 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 145:64910690c574 138 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 145:64910690c574 139 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 145:64910690c574 140 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 141 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 142 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 143 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 144 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 145 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 146 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 147 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 148 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 149 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 150 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 151 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 152 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 153 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 154 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 155 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 156 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 157 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 158 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 159 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 160 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 145:64910690c574 161 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 145:64910690c574 162 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
Kojto 122:f9eeca106725 163 /**
Kojto 122:f9eeca106725 164 * @}
Kojto 122:f9eeca106725 165 */
Kojto 122:f9eeca106725 166
Kojto 122:f9eeca106725 167 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
Kojto 122:f9eeca106725 168 * @{
Kojto 122:f9eeca106725 169 */
AnnaBridge 145:64910690c574 170 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 145:64910690c574 171 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 145:64910690c574 172 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 145:64910690c574 173 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 145:64910690c574 174 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 145:64910690c574 175 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
Kojto 122:f9eeca106725 176 /**
Kojto 122:f9eeca106725 177 * @}
Kojto 122:f9eeca106725 178 */
Kojto 122:f9eeca106725 179
Kojto 122:f9eeca106725 180 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
Kojto 122:f9eeca106725 181 * @{
Kojto 122:f9eeca106725 182 */
AnnaBridge 145:64910690c574 183 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 145:64910690c574 184 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 145:64910690c574 185 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 145:64910690c574 186 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
Kojto 122:f9eeca106725 187 /**
Kojto 122:f9eeca106725 188 * @}
Kojto 122:f9eeca106725 189 */
Kojto 122:f9eeca106725 190
Kojto 122:f9eeca106725 191 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
Kojto 122:f9eeca106725 192 * @{
Kojto 122:f9eeca106725 193 */
AnnaBridge 145:64910690c574 194 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
Kojto 122:f9eeca106725 195 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
Kojto 122:f9eeca106725 196 /**
Kojto 122:f9eeca106725 197 * @}
Kojto 122:f9eeca106725 198 */
Kojto 122:f9eeca106725 199
Kojto 122:f9eeca106725 200 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
Kojto 122:f9eeca106725 201 * @{
Kojto 122:f9eeca106725 202 */
Kojto 122:f9eeca106725 203 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 145:64910690c574 204 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
Kojto 122:f9eeca106725 205 /**
Kojto 122:f9eeca106725 206 * @}
Kojto 122:f9eeca106725 207 */
Kojto 122:f9eeca106725 208
Kojto 122:f9eeca106725 209 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
Kojto 122:f9eeca106725 210 * @{
Kojto 122:f9eeca106725 211 */
Kojto 122:f9eeca106725 212 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 145:64910690c574 213 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
Kojto 122:f9eeca106725 214 /**
Kojto 122:f9eeca106725 215 * @}
Kojto 122:f9eeca106725 216 */
Kojto 122:f9eeca106725 217
Kojto 122:f9eeca106725 218 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
Kojto 122:f9eeca106725 219 * @{
Kojto 122:f9eeca106725 220 */
Kojto 122:f9eeca106725 221 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 145:64910690c574 222 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
Kojto 122:f9eeca106725 223 /**
Kojto 122:f9eeca106725 224 * @}
Kojto 122:f9eeca106725 225 */
Kojto 122:f9eeca106725 226 #endif /* __MPU_PRESENT */
Kojto 122:f9eeca106725 227 /**
Kojto 122:f9eeca106725 228 * @}
Kojto 122:f9eeca106725 229 */
Kojto 122:f9eeca106725 230
Kojto 122:f9eeca106725 231 /* Exported macro ------------------------------------------------------------*/
Kojto 122:f9eeca106725 232
Kojto 122:f9eeca106725 233 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 234 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
Kojto 122:f9eeca106725 235 * @{
Kojto 122:f9eeca106725 236 */
Kojto 122:f9eeca106725 237
Kojto 122:f9eeca106725 238 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
Kojto 122:f9eeca106725 239 * @{
Kojto 122:f9eeca106725 240 */
Kojto 122:f9eeca106725 241
Kojto 122:f9eeca106725 242 /**
Kojto 122:f9eeca106725 243 * @brief This function checks if the Systick counter flag is active or not.
Kojto 122:f9eeca106725 244 * @note It can be used in timeout function on application side.
Kojto 122:f9eeca106725 245 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Kojto 122:f9eeca106725 246 * @retval State of bit (1 or 0).
Kojto 122:f9eeca106725 247 */
Kojto 122:f9eeca106725 248 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
Kojto 122:f9eeca106725 249 {
Kojto 122:f9eeca106725 250 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
Kojto 122:f9eeca106725 251 }
Kojto 122:f9eeca106725 252
Kojto 122:f9eeca106725 253 /**
Kojto 122:f9eeca106725 254 * @brief Configures the SysTick clock source
Kojto 122:f9eeca106725 255 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Kojto 122:f9eeca106725 256 * @param Source This parameter can be one of the following values:
Kojto 122:f9eeca106725 257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
Kojto 122:f9eeca106725 258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
Kojto 122:f9eeca106725 259 * @retval None
Kojto 122:f9eeca106725 260 */
Kojto 122:f9eeca106725 261 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
Kojto 122:f9eeca106725 262 {
Kojto 122:f9eeca106725 263 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
Kojto 122:f9eeca106725 264 {
Kojto 122:f9eeca106725 265 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 122:f9eeca106725 266 }
Kojto 122:f9eeca106725 267 else
Kojto 122:f9eeca106725 268 {
Kojto 122:f9eeca106725 269 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 122:f9eeca106725 270 }
Kojto 122:f9eeca106725 271 }
Kojto 122:f9eeca106725 272
Kojto 122:f9eeca106725 273 /**
Kojto 122:f9eeca106725 274 * @brief Get the SysTick clock source
Kojto 122:f9eeca106725 275 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Kojto 122:f9eeca106725 276 * @retval Returned value can be one of the following values:
Kojto 122:f9eeca106725 277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
Kojto 122:f9eeca106725 278 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
Kojto 122:f9eeca106725 279 */
Kojto 122:f9eeca106725 280 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
Kojto 122:f9eeca106725 281 {
Kojto 122:f9eeca106725 282 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
Kojto 122:f9eeca106725 283 }
Kojto 122:f9eeca106725 284
Kojto 122:f9eeca106725 285 /**
Kojto 122:f9eeca106725 286 * @brief Enable SysTick exception request
Kojto 122:f9eeca106725 287 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
Kojto 122:f9eeca106725 288 * @retval None
Kojto 122:f9eeca106725 289 */
Kojto 122:f9eeca106725 290 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
Kojto 122:f9eeca106725 291 {
Kojto 122:f9eeca106725 292 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
Kojto 122:f9eeca106725 293 }
Kojto 122:f9eeca106725 294
Kojto 122:f9eeca106725 295 /**
Kojto 122:f9eeca106725 296 * @brief Disable SysTick exception request
Kojto 122:f9eeca106725 297 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
Kojto 122:f9eeca106725 298 * @retval None
Kojto 122:f9eeca106725 299 */
Kojto 122:f9eeca106725 300 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
Kojto 122:f9eeca106725 301 {
Kojto 122:f9eeca106725 302 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
Kojto 122:f9eeca106725 303 }
Kojto 122:f9eeca106725 304
Kojto 122:f9eeca106725 305 /**
Kojto 122:f9eeca106725 306 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
Kojto 122:f9eeca106725 307 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Kojto 122:f9eeca106725 308 * @retval State of bit (1 or 0).
Kojto 122:f9eeca106725 309 */
Kojto 122:f9eeca106725 310 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
Kojto 122:f9eeca106725 311 {
Kojto 122:f9eeca106725 312 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
Kojto 122:f9eeca106725 313 }
Kojto 122:f9eeca106725 314
Kojto 122:f9eeca106725 315 /**
Kojto 122:f9eeca106725 316 * @}
Kojto 122:f9eeca106725 317 */
Kojto 122:f9eeca106725 318
Kojto 122:f9eeca106725 319 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
Kojto 122:f9eeca106725 320 * @{
Kojto 122:f9eeca106725 321 */
Kojto 122:f9eeca106725 322
Kojto 122:f9eeca106725 323 /**
Kojto 122:f9eeca106725 324 * @brief Processor uses sleep as its low power mode
Kojto 122:f9eeca106725 325 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Kojto 122:f9eeca106725 326 * @retval None
Kojto 122:f9eeca106725 327 */
Kojto 122:f9eeca106725 328 __STATIC_INLINE void LL_LPM_EnableSleep(void)
Kojto 122:f9eeca106725 329 {
Kojto 122:f9eeca106725 330 /* Clear SLEEPDEEP bit of Cortex System Control Register */
Kojto 122:f9eeca106725 331 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
Kojto 122:f9eeca106725 332 }
Kojto 122:f9eeca106725 333
Kojto 122:f9eeca106725 334 /**
Kojto 122:f9eeca106725 335 * @brief Processor uses deep sleep as its low power mode
Kojto 122:f9eeca106725 336 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Kojto 122:f9eeca106725 337 * @retval None
Kojto 122:f9eeca106725 338 */
Kojto 122:f9eeca106725 339 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
Kojto 122:f9eeca106725 340 {
Kojto 122:f9eeca106725 341 /* Set SLEEPDEEP bit of Cortex System Control Register */
Kojto 122:f9eeca106725 342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
Kojto 122:f9eeca106725 343 }
Kojto 122:f9eeca106725 344
Kojto 122:f9eeca106725 345 /**
Kojto 122:f9eeca106725 346 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
Kojto 122:f9eeca106725 347 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
Kojto 122:f9eeca106725 348 * empty main application.
Kojto 122:f9eeca106725 349 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Kojto 122:f9eeca106725 350 * @retval None
Kojto 122:f9eeca106725 351 */
Kojto 122:f9eeca106725 352 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
Kojto 122:f9eeca106725 353 {
Kojto 122:f9eeca106725 354 /* Set SLEEPONEXIT bit of Cortex System Control Register */
Kojto 122:f9eeca106725 355 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
Kojto 122:f9eeca106725 356 }
Kojto 122:f9eeca106725 357
Kojto 122:f9eeca106725 358 /**
Kojto 122:f9eeca106725 359 * @brief Do not sleep when returning to Thread mode.
Kojto 122:f9eeca106725 360 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Kojto 122:f9eeca106725 361 * @retval None
Kojto 122:f9eeca106725 362 */
Kojto 122:f9eeca106725 363 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
Kojto 122:f9eeca106725 364 {
Kojto 122:f9eeca106725 365 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
Kojto 122:f9eeca106725 366 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
Kojto 122:f9eeca106725 367 }
Kojto 122:f9eeca106725 368
Kojto 122:f9eeca106725 369 /**
Kojto 122:f9eeca106725 370 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
Kojto 122:f9eeca106725 371 * processor.
Kojto 122:f9eeca106725 372 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Kojto 122:f9eeca106725 373 * @retval None
Kojto 122:f9eeca106725 374 */
Kojto 122:f9eeca106725 375 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
Kojto 122:f9eeca106725 376 {
Kojto 122:f9eeca106725 377 /* Set SEVEONPEND bit of Cortex System Control Register */
Kojto 122:f9eeca106725 378 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
Kojto 122:f9eeca106725 379 }
Kojto 122:f9eeca106725 380
Kojto 122:f9eeca106725 381 /**
Kojto 122:f9eeca106725 382 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
Kojto 122:f9eeca106725 383 * excluded
Kojto 122:f9eeca106725 384 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Kojto 122:f9eeca106725 385 * @retval None
Kojto 122:f9eeca106725 386 */
Kojto 122:f9eeca106725 387 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
Kojto 122:f9eeca106725 388 {
Kojto 122:f9eeca106725 389 /* Clear SEVEONPEND bit of Cortex System Control Register */
Kojto 122:f9eeca106725 390 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
Kojto 122:f9eeca106725 391 }
Kojto 122:f9eeca106725 392
Kojto 122:f9eeca106725 393 /**
Kojto 122:f9eeca106725 394 * @}
Kojto 122:f9eeca106725 395 */
Kojto 122:f9eeca106725 396
Kojto 122:f9eeca106725 397 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
Kojto 122:f9eeca106725 398 * @{
Kojto 122:f9eeca106725 399 */
Kojto 122:f9eeca106725 400
Kojto 122:f9eeca106725 401 /**
Kojto 122:f9eeca106725 402 * @brief Enable a fault in System handler control register (SHCSR)
Kojto 122:f9eeca106725 403 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
Kojto 122:f9eeca106725 404 * @param Fault This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 405 * @arg @ref LL_HANDLER_FAULT_USG
Kojto 122:f9eeca106725 406 * @arg @ref LL_HANDLER_FAULT_BUS
Kojto 122:f9eeca106725 407 * @arg @ref LL_HANDLER_FAULT_MEM
Kojto 122:f9eeca106725 408 * @retval None
Kojto 122:f9eeca106725 409 */
Kojto 122:f9eeca106725 410 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
Kojto 122:f9eeca106725 411 {
Kojto 122:f9eeca106725 412 /* Enable the system handler fault */
Kojto 122:f9eeca106725 413 SET_BIT(SCB->SHCSR, Fault);
Kojto 122:f9eeca106725 414 }
Kojto 122:f9eeca106725 415
Kojto 122:f9eeca106725 416 /**
Kojto 122:f9eeca106725 417 * @brief Disable a fault in System handler control register (SHCSR)
Kojto 122:f9eeca106725 418 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
Kojto 122:f9eeca106725 419 * @param Fault This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 420 * @arg @ref LL_HANDLER_FAULT_USG
Kojto 122:f9eeca106725 421 * @arg @ref LL_HANDLER_FAULT_BUS
Kojto 122:f9eeca106725 422 * @arg @ref LL_HANDLER_FAULT_MEM
Kojto 122:f9eeca106725 423 * @retval None
Kojto 122:f9eeca106725 424 */
Kojto 122:f9eeca106725 425 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
Kojto 122:f9eeca106725 426 {
Kojto 122:f9eeca106725 427 /* Disable the system handler fault */
Kojto 122:f9eeca106725 428 CLEAR_BIT(SCB->SHCSR, Fault);
Kojto 122:f9eeca106725 429 }
Kojto 122:f9eeca106725 430
Kojto 122:f9eeca106725 431 /**
Kojto 122:f9eeca106725 432 * @}
Kojto 122:f9eeca106725 433 */
Kojto 122:f9eeca106725 434
Kojto 122:f9eeca106725 435 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
Kojto 122:f9eeca106725 436 * @{
Kojto 122:f9eeca106725 437 */
Kojto 122:f9eeca106725 438
Kojto 122:f9eeca106725 439 /**
Kojto 122:f9eeca106725 440 * @brief Get Implementer code
Kojto 122:f9eeca106725 441 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Kojto 122:f9eeca106725 442 * @retval Value should be equal to 0x41 for ARM
Kojto 122:f9eeca106725 443 */
Kojto 122:f9eeca106725 444 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
Kojto 122:f9eeca106725 445 {
Kojto 122:f9eeca106725 446 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
Kojto 122:f9eeca106725 447 }
Kojto 122:f9eeca106725 448
Kojto 122:f9eeca106725 449 /**
Kojto 122:f9eeca106725 450 * @brief Get Variant number (The r value in the rnpn product revision identifier)
Kojto 122:f9eeca106725 451 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
Kojto 122:f9eeca106725 452 * @retval Value between 0 and 255 (0x0: revision 0)
Kojto 122:f9eeca106725 453 */
Kojto 122:f9eeca106725 454 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
Kojto 122:f9eeca106725 455 {
Kojto 122:f9eeca106725 456 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
Kojto 122:f9eeca106725 457 }
Kojto 122:f9eeca106725 458
Kojto 122:f9eeca106725 459 /**
Kojto 122:f9eeca106725 460 * @brief Get Constant number
Kojto 122:f9eeca106725 461 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
Kojto 122:f9eeca106725 462 * @retval Value should be equal to 0xF for Cortex-M4 devices
Kojto 122:f9eeca106725 463 */
Kojto 122:f9eeca106725 464 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
Kojto 122:f9eeca106725 465 {
Kojto 122:f9eeca106725 466 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
Kojto 122:f9eeca106725 467 }
Kojto 122:f9eeca106725 468
Kojto 122:f9eeca106725 469 /**
Kojto 122:f9eeca106725 470 * @brief Get Part number
Kojto 122:f9eeca106725 471 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
Kojto 122:f9eeca106725 472 * @retval Value should be equal to 0xC24 for Cortex-M4
Kojto 122:f9eeca106725 473 */
Kojto 122:f9eeca106725 474 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
Kojto 122:f9eeca106725 475 {
Kojto 122:f9eeca106725 476 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
Kojto 122:f9eeca106725 477 }
Kojto 122:f9eeca106725 478
Kojto 122:f9eeca106725 479 /**
Kojto 122:f9eeca106725 480 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
Kojto 122:f9eeca106725 481 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
Kojto 122:f9eeca106725 482 * @retval Value between 0 and 255 (0x1: patch 1)
Kojto 122:f9eeca106725 483 */
Kojto 122:f9eeca106725 484 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
Kojto 122:f9eeca106725 485 {
Kojto 122:f9eeca106725 486 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
Kojto 122:f9eeca106725 487 }
Kojto 122:f9eeca106725 488
Kojto 122:f9eeca106725 489 /**
Kojto 122:f9eeca106725 490 * @}
Kojto 122:f9eeca106725 491 */
Kojto 122:f9eeca106725 492
Kojto 122:f9eeca106725 493 #if __MPU_PRESENT
Kojto 122:f9eeca106725 494 /** @defgroup CORTEX_LL_EF_MPU MPU
Kojto 122:f9eeca106725 495 * @{
Kojto 122:f9eeca106725 496 */
Kojto 122:f9eeca106725 497
Kojto 122:f9eeca106725 498 /**
Kojto 122:f9eeca106725 499 * @brief Enable MPU with input options
Kojto 122:f9eeca106725 500 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
Kojto 122:f9eeca106725 501 * @param Options This parameter can be one of the following values:
Kojto 122:f9eeca106725 502 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
Kojto 122:f9eeca106725 503 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
Kojto 122:f9eeca106725 504 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
Kojto 122:f9eeca106725 505 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
Kojto 122:f9eeca106725 506 * @retval None
Kojto 122:f9eeca106725 507 */
Kojto 122:f9eeca106725 508 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
Kojto 122:f9eeca106725 509 {
Kojto 122:f9eeca106725 510 /* Enable the MPU*/
Kojto 122:f9eeca106725 511 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
Kojto 122:f9eeca106725 512 /* Ensure MPU settings take effects */
Kojto 122:f9eeca106725 513 __DSB();
Kojto 122:f9eeca106725 514 /* Sequence instruction fetches using update settings */
Kojto 122:f9eeca106725 515 __ISB();
Kojto 122:f9eeca106725 516 }
Kojto 122:f9eeca106725 517
Kojto 122:f9eeca106725 518 /**
Kojto 122:f9eeca106725 519 * @brief Disable MPU
Kojto 122:f9eeca106725 520 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
Kojto 122:f9eeca106725 521 * @retval None
Kojto 122:f9eeca106725 522 */
Kojto 122:f9eeca106725 523 __STATIC_INLINE void LL_MPU_Disable(void)
Kojto 122:f9eeca106725 524 {
Kojto 122:f9eeca106725 525 /* Make sure outstanding transfers are done */
Kojto 122:f9eeca106725 526 __DMB();
Kojto 122:f9eeca106725 527 /* Disable MPU*/
Kojto 122:f9eeca106725 528 WRITE_REG(MPU->CTRL, 0U);
Kojto 122:f9eeca106725 529 }
Kojto 122:f9eeca106725 530
Kojto 122:f9eeca106725 531 /**
Kojto 122:f9eeca106725 532 * @brief Check if MPU is enabled or not
Kojto 122:f9eeca106725 533 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
Kojto 122:f9eeca106725 534 * @retval State of bit (1 or 0).
Kojto 122:f9eeca106725 535 */
Kojto 122:f9eeca106725 536 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
Kojto 122:f9eeca106725 537 {
Kojto 122:f9eeca106725 538 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
Kojto 122:f9eeca106725 539 }
Kojto 122:f9eeca106725 540
Kojto 122:f9eeca106725 541 /**
Kojto 122:f9eeca106725 542 * @brief Enable a MPU region
Kojto 122:f9eeca106725 543 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
Kojto 122:f9eeca106725 544 * @param Region This parameter can be one of the following values:
Kojto 122:f9eeca106725 545 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 122:f9eeca106725 546 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 122:f9eeca106725 547 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 122:f9eeca106725 548 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 122:f9eeca106725 549 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 122:f9eeca106725 550 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 122:f9eeca106725 551 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 122:f9eeca106725 552 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 122:f9eeca106725 553 * @retval None
Kojto 122:f9eeca106725 554 */
Kojto 122:f9eeca106725 555 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
Kojto 122:f9eeca106725 556 {
Kojto 122:f9eeca106725 557 /* Set Region number */
Kojto 122:f9eeca106725 558 WRITE_REG(MPU->RNR, Region);
Kojto 122:f9eeca106725 559 /* Enable the MPU region */
Kojto 122:f9eeca106725 560 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
Kojto 122:f9eeca106725 561 }
Kojto 122:f9eeca106725 562
Kojto 122:f9eeca106725 563 /**
Kojto 122:f9eeca106725 564 * @brief Configure and enable a region
Kojto 122:f9eeca106725 565 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
Kojto 122:f9eeca106725 566 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
Kojto 122:f9eeca106725 567 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
Kojto 122:f9eeca106725 568 * MPU_RASR XN LL_MPU_ConfigRegion\n
Kojto 122:f9eeca106725 569 * MPU_RASR AP LL_MPU_ConfigRegion\n
Kojto 122:f9eeca106725 570 * MPU_RASR S LL_MPU_ConfigRegion\n
Kojto 122:f9eeca106725 571 * MPU_RASR C LL_MPU_ConfigRegion\n
Kojto 122:f9eeca106725 572 * MPU_RASR B LL_MPU_ConfigRegion\n
Kojto 122:f9eeca106725 573 * MPU_RASR SIZE LL_MPU_ConfigRegion
Kojto 122:f9eeca106725 574 * @param Region This parameter can be one of the following values:
Kojto 122:f9eeca106725 575 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 122:f9eeca106725 576 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 122:f9eeca106725 577 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 122:f9eeca106725 578 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 122:f9eeca106725 579 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 122:f9eeca106725 580 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 122:f9eeca106725 581 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 122:f9eeca106725 582 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 122:f9eeca106725 583 * @param Address Value of region base address
Kojto 122:f9eeca106725 584 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Kojto 122:f9eeca106725 585 * @param Attributes This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 586 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
Kojto 122:f9eeca106725 587 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
Kojto 122:f9eeca106725 588 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
Kojto 122:f9eeca106725 589 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
Kojto 122:f9eeca106725 590 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
Kojto 122:f9eeca106725 591 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
Kojto 122:f9eeca106725 592 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
Kojto 122:f9eeca106725 593 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
Kojto 122:f9eeca106725 594 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
Kojto 122:f9eeca106725 595 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
Kojto 122:f9eeca106725 596 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
Kojto 122:f9eeca106725 597 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
Kojto 122:f9eeca106725 598 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
Kojto 122:f9eeca106725 599 * @retval None
Kojto 122:f9eeca106725 600 */
Kojto 122:f9eeca106725 601 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Kojto 122:f9eeca106725 602 {
Kojto 122:f9eeca106725 603 /* Set Region number */
Kojto 122:f9eeca106725 604 WRITE_REG(MPU->RNR, Region);
Kojto 122:f9eeca106725 605 /* Set base address */
Kojto 122:f9eeca106725 606 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
Kojto 122:f9eeca106725 607 /* Configure MPU */
Kojto 122:f9eeca106725 608 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
Kojto 122:f9eeca106725 609 }
Kojto 122:f9eeca106725 610
Kojto 122:f9eeca106725 611 /**
Kojto 122:f9eeca106725 612 * @brief Disable a region
Kojto 122:f9eeca106725 613 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
Kojto 122:f9eeca106725 614 * MPU_RASR ENABLE LL_MPU_DisableRegion
Kojto 122:f9eeca106725 615 * @param Region This parameter can be one of the following values:
Kojto 122:f9eeca106725 616 * @arg @ref LL_MPU_REGION_NUMBER0
Kojto 122:f9eeca106725 617 * @arg @ref LL_MPU_REGION_NUMBER1
Kojto 122:f9eeca106725 618 * @arg @ref LL_MPU_REGION_NUMBER2
Kojto 122:f9eeca106725 619 * @arg @ref LL_MPU_REGION_NUMBER3
Kojto 122:f9eeca106725 620 * @arg @ref LL_MPU_REGION_NUMBER4
Kojto 122:f9eeca106725 621 * @arg @ref LL_MPU_REGION_NUMBER5
Kojto 122:f9eeca106725 622 * @arg @ref LL_MPU_REGION_NUMBER6
Kojto 122:f9eeca106725 623 * @arg @ref LL_MPU_REGION_NUMBER7
Kojto 122:f9eeca106725 624 * @retval None
Kojto 122:f9eeca106725 625 */
Kojto 122:f9eeca106725 626 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
Kojto 122:f9eeca106725 627 {
Kojto 122:f9eeca106725 628 /* Set Region number */
Kojto 122:f9eeca106725 629 WRITE_REG(MPU->RNR, Region);
Kojto 122:f9eeca106725 630 /* Disable the MPU region */
Kojto 122:f9eeca106725 631 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
Kojto 122:f9eeca106725 632 }
Kojto 122:f9eeca106725 633
Kojto 122:f9eeca106725 634 /**
Kojto 122:f9eeca106725 635 * @}
Kojto 122:f9eeca106725 636 */
Kojto 122:f9eeca106725 637
Kojto 122:f9eeca106725 638 #endif /* __MPU_PRESENT */
Kojto 122:f9eeca106725 639 /**
Kojto 122:f9eeca106725 640 * @}
Kojto 122:f9eeca106725 641 */
Kojto 122:f9eeca106725 642
Kojto 122:f9eeca106725 643 /**
Kojto 122:f9eeca106725 644 * @}
Kojto 122:f9eeca106725 645 */
Kojto 122:f9eeca106725 646
Kojto 122:f9eeca106725 647 /**
Kojto 122:f9eeca106725 648 * @}
Kojto 122:f9eeca106725 649 */
Kojto 122:f9eeca106725 650
Kojto 122:f9eeca106725 651 #ifdef __cplusplus
Kojto 122:f9eeca106725 652 }
Kojto 122:f9eeca106725 653 #endif
Kojto 122:f9eeca106725 654
Kojto 122:f9eeca106725 655 #endif /* __STM32L4xx_LL_CORTEX_H */
Kojto 122:f9eeca106725 656
Kojto 122:f9eeca106725 657 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/