mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F446ZE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Parent:: 128:9bcdf88f62b0

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	89:552587b429a1	1	/**
bogdanm	89:552587b429a1	2	******************************************************************************
bogdanm	89:552587b429a1	3	* @file stm32f4xx_hal_rcc_ex.h
bogdanm	89:552587b429a1	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.7.1
AnnaBridge	145:64910690c574	6	* @date 14-April-2017
bogdanm	89:552587b429a1	7	* @brief Header file of RCC HAL Extension module.
bogdanm	89:552587b429a1	8	******************************************************************************
bogdanm	89:552587b429a1	9	* @attention
bogdanm	89:552587b429a1	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
bogdanm	89:552587b429a1	12	*
bogdanm	89:552587b429a1	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	89:552587b429a1	14	* are permitted provided that the following conditions are met:
bogdanm	89:552587b429a1	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	89:552587b429a1	16	* this list of conditions and the following disclaimer.
bogdanm	89:552587b429a1	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	89:552587b429a1	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	89:552587b429a1	19	* and/or other materials provided with the distribution.
bogdanm	89:552587b429a1	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	89:552587b429a1	21	* may be used to endorse or promote products derived from this software
bogdanm	89:552587b429a1	22	* without specific prior written permission.
bogdanm	89:552587b429a1	23	*
bogdanm	89:552587b429a1	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	89:552587b429a1	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	89:552587b429a1	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	89:552587b429a1	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	89:552587b429a1	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	89:552587b429a1	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	89:552587b429a1	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	89:552587b429a1	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	89:552587b429a1	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	89:552587b429a1	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	89:552587b429a1	34	*
bogdanm	89:552587b429a1	35	******************************************************************************
bogdanm	89:552587b429a1	36	*/
bogdanm	89:552587b429a1	37
bogdanm	89:552587b429a1	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	89:552587b429a1	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
bogdanm	89:552587b429a1	40	#define __STM32F4xx_HAL_RCC_EX_H
bogdanm	89:552587b429a1	41
bogdanm	89:552587b429a1	42	#ifdef __cplusplus
bogdanm	89:552587b429a1	43	extern "C" {
bogdanm	89:552587b429a1	44	#endif
bogdanm	89:552587b429a1	45
bogdanm	89:552587b429a1	46	/* Includes ------------------------------------------------------------------*/
bogdanm	89:552587b429a1	47	#include "stm32f4xx_hal_def.h"
bogdanm	89:552587b429a1	48
bogdanm	89:552587b429a1	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	89:552587b429a1	50	* @{
bogdanm	89:552587b429a1	51	*/
bogdanm	89:552587b429a1	52
bogdanm	89:552587b429a1	53	/** @addtogroup RCCEx
bogdanm	89:552587b429a1	54	* @{
bogdanm	89:552587b429a1	55	*/
bogdanm	89:552587b429a1	56
Kojto	99:dbbf35b96557	57	/* Exported types ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	99:dbbf35b96557	59	* @{
Kojto	99:dbbf35b96557	60	*/
Kojto	99:dbbf35b96557	61
Kojto	99:dbbf35b96557	62	/**
Kojto	99:dbbf35b96557	63	* @brief RCC PLL configuration structure definition
Kojto	99:dbbf35b96557	64	*/
Kojto	99:dbbf35b96557	65	typedef struct
Kojto	99:dbbf35b96557	66	{
Kojto	99:dbbf35b96557	67	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	99:dbbf35b96557	68	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	99:dbbf35b96557	69
Kojto	99:dbbf35b96557	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	110:165afa46840b	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	99:dbbf35b96557	72
Kojto	99:dbbf35b96557	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto	110:165afa46840b	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto	99:dbbf35b96557	75
Kojto	99:dbbf35b96557	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto	122:f9eeca106725	77	This parameter must be a number between Min_Data = 50 and Max_Data = 432
Kojto	122:f9eeca106725	78	except for STM32F411xE devices where the Min_Data = 192 */
Kojto	99:dbbf35b96557	79
Kojto	99:dbbf35b96557	80	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto	99:dbbf35b96557	81	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto	99:dbbf35b96557	82
Kojto	99:dbbf35b96557	83	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
AnnaBridge	145:64910690c574	84	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
Kojto	110:165afa46840b	85	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	145:64910690c574	86	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	145:64910690c574	87	defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	99:dbbf35b96557	88	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	122:f9eeca106725	89	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
AnnaBridge	145:64910690c574	90	and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
Kojto	99:dbbf35b96557	91	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
AnnaBridge	145:64910690c574	92	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	99:dbbf35b96557	93	}RCC_PLLInitTypeDef;
Kojto	99:dbbf35b96557	94
Kojto	99:dbbf35b96557	95	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	96	/**
Kojto	99:dbbf35b96557	97	* @brief PLLI2S Clock structure definition
Kojto	99:dbbf35b96557	98	*/
Kojto	99:dbbf35b96557	99	typedef struct
Kojto	99:dbbf35b96557	100	{
Kojto	99:dbbf35b96557	101	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto	110:165afa46840b	102	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	99:dbbf35b96557	103
Kojto	99:dbbf35b96557	104	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	105	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
Kojto	99:dbbf35b96557	106
Kojto	99:dbbf35b96557	107	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
Kojto	99:dbbf35b96557	108	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
Kojto	99:dbbf35b96557	109
Kojto	99:dbbf35b96557	110	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto	99:dbbf35b96557	111	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	112	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	113
Kojto	99:dbbf35b96557	114	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	99:dbbf35b96557	115	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	116	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	99:dbbf35b96557	117	}RCC_PLLI2SInitTypeDef;
Kojto	99:dbbf35b96557	118
Kojto	99:dbbf35b96557	119	/**
Kojto	99:dbbf35b96557	120	* @brief PLLSAI Clock structure definition
Kojto	99:dbbf35b96557	121	*/
Kojto	99:dbbf35b96557	122	typedef struct
Kojto	99:dbbf35b96557	123	{
Kojto	99:dbbf35b96557	124	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
Kojto	110:165afa46840b	125	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	99:dbbf35b96557	126
Kojto	99:dbbf35b96557	127	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	128	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
Kojto	99:dbbf35b96557	129
Kojto	99:dbbf35b96557	130	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	131	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	99:dbbf35b96557	132
Kojto	99:dbbf35b96557	133	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
Kojto	99:dbbf35b96557	134	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	135	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	136	}RCC_PLLSAIInitTypeDef;
Kojto	122:f9eeca106725	137
Kojto	99:dbbf35b96557	138	/**
Kojto	99:dbbf35b96557	139	* @brief RCC extended clocks structure definition
Kojto	99:dbbf35b96557	140	*/
Kojto	99:dbbf35b96557	141	typedef struct
Kojto	99:dbbf35b96557	142	{
Kojto	99:dbbf35b96557	143	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	99:dbbf35b96557	144	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	99:dbbf35b96557	145
Kojto	99:dbbf35b96557	146	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	99:dbbf35b96557	147	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	99:dbbf35b96557	148
Kojto	99:dbbf35b96557	149	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	99:dbbf35b96557	150	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	99:dbbf35b96557	151
Kojto	99:dbbf35b96557	152	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	153	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	99:dbbf35b96557	154	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	155
Kojto	99:dbbf35b96557	156	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	157	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	99:dbbf35b96557	158	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	159
Kojto	99:dbbf35b96557	160	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
Kojto	99:dbbf35b96557	161	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto	99:dbbf35b96557	162
Kojto	99:dbbf35b96557	163	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
Kojto	99:dbbf35b96557	164	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto	99:dbbf35b96557	165
Kojto	99:dbbf35b96557	166	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto	99:dbbf35b96557	167	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto	99:dbbf35b96557	168
Kojto	99:dbbf35b96557	169	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto	99:dbbf35b96557	170	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto	99:dbbf35b96557	171
Kojto	99:dbbf35b96557	172	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	99:dbbf35b96557	173	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	99:dbbf35b96557	174
Kojto	99:dbbf35b96557	175	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	99:dbbf35b96557	176	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	99:dbbf35b96557	177
Kojto	99:dbbf35b96557	178	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
Kojto	99:dbbf35b96557	179	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	99:dbbf35b96557	180
Kojto	99:dbbf35b96557	181	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	99:dbbf35b96557	182	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	99:dbbf35b96557	183
Kojto	99:dbbf35b96557	184	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
Kojto	99:dbbf35b96557	185	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
Kojto	99:dbbf35b96557	186
Kojto	122:f9eeca106725	187	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	122:f9eeca106725	188	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto	99:dbbf35b96557	189
Kojto	99:dbbf35b96557	190	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	99:dbbf35b96557	191	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	99:dbbf35b96557	192	}RCC_PeriphCLKInitTypeDef;
Kojto	99:dbbf35b96557	193	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	194
Kojto	110:165afa46840b	195	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	196	/**
Kojto	110:165afa46840b	197	* @brief RCC extended clocks structure definition
Kojto	110:165afa46840b	198	*/
Kojto	110:165afa46840b	199	typedef struct
Kojto	110:165afa46840b	200	{
Kojto	110:165afa46840b	201	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	110:165afa46840b	202	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	110:165afa46840b	203
Kojto	110:165afa46840b	204	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	110:165afa46840b	205	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
Kojto	110:165afa46840b	206
Kojto	110:165afa46840b	207	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	110:165afa46840b	208	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	110:165afa46840b	209
Kojto	110:165afa46840b	210	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
Kojto	110:165afa46840b	211	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto	110:165afa46840b	212
Kojto	110:165afa46840b	213	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	122:f9eeca106725	214	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	122:f9eeca106725	215
Kojto	110:165afa46840b	216	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	110:165afa46840b	217	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	110:165afa46840b	218	}RCC_PeriphCLKInitTypeDef;
Kojto	110:165afa46840b	219	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	220
AnnaBridge	145:64910690c574	221	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	222	/**
Kojto	122:f9eeca106725	223	* @brief PLLI2S Clock structure definition
Kojto	122:f9eeca106725	224	*/
Kojto	122:f9eeca106725	225	typedef struct
Kojto	122:f9eeca106725	226	{
Kojto	122:f9eeca106725	227	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto	122:f9eeca106725	228	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	122:f9eeca106725	229
Kojto	122:f9eeca106725	230	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	231	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
Kojto	122:f9eeca106725	232
Kojto	122:f9eeca106725	233	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto	122:f9eeca106725	234	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	122:f9eeca106725	235	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	122:f9eeca106725	236
Kojto	122:f9eeca106725	237	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	122:f9eeca106725	238	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	122:f9eeca106725	239	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	122:f9eeca106725	240	}RCC_PLLI2SInitTypeDef;
Kojto	122:f9eeca106725	241
Kojto	122:f9eeca106725	242	/**
Kojto	122:f9eeca106725	243	* @brief RCC extended clocks structure definition
Kojto	122:f9eeca106725	244	*/
Kojto	122:f9eeca106725	245	typedef struct
Kojto	122:f9eeca106725	246	{
Kojto	122:f9eeca106725	247	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	122:f9eeca106725	248	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	122:f9eeca106725	249
Kojto	122:f9eeca106725	250	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	122:f9eeca106725	251	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
AnnaBridge	145:64910690c574	252
AnnaBridge	145:64910690c574	253	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	254	uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
AnnaBridge	145:64910690c574	255	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	145:64910690c574	256	This parameter will be used only when PLL is selected as Clock Source SAI */
AnnaBridge	145:64910690c574	257
AnnaBridge	145:64910690c574	258	uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	145:64910690c574	259	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	145:64910690c574	260	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	145:64910690c574	261	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	262
Kojto	122:f9eeca106725	263	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto	122:f9eeca106725	264	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto	122:f9eeca106725	265
Kojto	122:f9eeca106725	266	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto	122:f9eeca106725	267	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto	122:f9eeca106725	268
Kojto	122:f9eeca106725	269	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	122:f9eeca106725	270	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	122:f9eeca106725	271
Kojto	122:f9eeca106725	272	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	122:f9eeca106725	273	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	122:f9eeca106725	274
Kojto	122:f9eeca106725	275	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	122:f9eeca106725	276	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	122:f9eeca106725	277
Kojto	122:f9eeca106725	278	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	122:f9eeca106725	279	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto	122:f9eeca106725	280
Kojto	122:f9eeca106725	281	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
Kojto	122:f9eeca106725	282	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
Kojto	122:f9eeca106725	283
Kojto	122:f9eeca106725	284	uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
Kojto	122:f9eeca106725	285	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
AnnaBridge	145:64910690c574	286
AnnaBridge	145:64910690c574	287	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	288	uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
AnnaBridge	145:64910690c574	289	This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
AnnaBridge	145:64910690c574	290
AnnaBridge	145:64910690c574	291	uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
AnnaBridge	145:64910690c574	292	This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
AnnaBridge	145:64910690c574	293
AnnaBridge	145:64910690c574	294	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
AnnaBridge	145:64910690c574	295	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	145:64910690c574	296
AnnaBridge	145:64910690c574	297	uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
AnnaBridge	145:64910690c574	298	This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
AnnaBridge	145:64910690c574	299
AnnaBridge	145:64910690c574	300	uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
AnnaBridge	145:64910690c574	301	This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
AnnaBridge	145:64910690c574	302	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	303
Kojto	122:f9eeca106725	304	uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
Kojto	122:f9eeca106725	305	This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
Kojto	122:f9eeca106725	306
Kojto	122:f9eeca106725	307	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	122:f9eeca106725	308	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	122:f9eeca106725	309	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	145:64910690c574	310	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	311
Kojto	110:165afa46840b	312	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	89:552587b429a1	313	/**
bogdanm	89:552587b429a1	314	* @brief PLLI2S Clock structure definition
bogdanm	89:552587b429a1	315	*/
bogdanm	89:552587b429a1	316	typedef struct
bogdanm	89:552587b429a1	317	{
bogdanm	89:552587b429a1	318	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	319	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
bogdanm	89:552587b429a1	320	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	321
bogdanm	89:552587b429a1	322	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	89:552587b429a1	323	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	89:552587b429a1	324	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	325
bogdanm	89:552587b429a1	326	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	89:552587b429a1	327	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	89:552587b429a1	328	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	89:552587b429a1	329	}RCC_PLLI2SInitTypeDef;
bogdanm	89:552587b429a1	330
bogdanm	89:552587b429a1	331	/**
bogdanm	89:552587b429a1	332	* @brief PLLSAI Clock structure definition
bogdanm	89:552587b429a1	333	*/
bogdanm	89:552587b429a1	334	typedef struct
bogdanm	89:552587b429a1	335	{
bogdanm	89:552587b429a1	336	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	337	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
bogdanm	89:552587b429a1	338	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	110:165afa46840b	339	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	340	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
Kojto	110:165afa46840b	341	This parameter is only available in STM32F469xx/STM32F479xx devices.
Kojto	110:165afa46840b	342	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	110:165afa46840b	343	#endif /* STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	344
bogdanm	89:552587b429a1	345	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	89:552587b429a1	346	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	89:552587b429a1	347	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm	89:552587b429a1	348
bogdanm	89:552587b429a1	349	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm	89:552587b429a1	350	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	89:552587b429a1	351	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
bogdanm	89:552587b429a1	352
bogdanm	89:552587b429a1	353	}RCC_PLLSAIInitTypeDef;
Kojto	122:f9eeca106725	354
bogdanm	89:552587b429a1	355	/**
bogdanm	89:552587b429a1	356	* @brief RCC extended clocks structure definition
bogdanm	89:552587b429a1	357	*/
bogdanm	89:552587b429a1	358	typedef struct
bogdanm	89:552587b429a1	359	{
bogdanm	89:552587b429a1	360	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	89:552587b429a1	361	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	89:552587b429a1	362
bogdanm	89:552587b429a1	363	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	89:552587b429a1	364	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	365
bogdanm	89:552587b429a1	366	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
bogdanm	89:552587b429a1	367	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
bogdanm	89:552587b429a1	368
bogdanm	89:552587b429a1	369	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	89:552587b429a1	370	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	89:552587b429a1	371	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	89:552587b429a1	372
bogdanm	89:552587b429a1	373	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	89:552587b429a1	374	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	89:552587b429a1	375	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm	89:552587b429a1	376
bogdanm	89:552587b429a1	377	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
bogdanm	89:552587b429a1	378	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
bogdanm	89:552587b429a1	379
bogdanm	89:552587b429a1	380	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm	89:552587b429a1	381	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	89:552587b429a1	382
bogdanm	89:552587b429a1	383	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
bogdanm	89:552587b429a1	384	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	110:165afa46840b	385	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	386	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	122:f9eeca106725	387	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto	110:165afa46840b	388
Kojto	110:165afa46840b	389	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	110:165afa46840b	390	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	110:165afa46840b	391	#endif /* STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	392	}RCC_PeriphCLKInitTypeDef;
Kojto	122:f9eeca106725	393
Kojto	110:165afa46840b	394	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	395
Kojto	110:165afa46840b	396	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
bogdanm	92:4fc01daae5a5	397	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	89:552587b429a1	398	/**
bogdanm	89:552587b429a1	399	* @brief PLLI2S Clock structure definition
bogdanm	89:552587b429a1	400	*/
bogdanm	89:552587b429a1	401	typedef struct
bogdanm	89:552587b429a1	402	{
Kojto	110:165afa46840b	403	#if defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	404	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
bogdanm	92:4fc01daae5a5	405	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
bogdanm	92:4fc01daae5a5	406	#endif /* STM32F411xE */
bogdanm	92:4fc01daae5a5	407
bogdanm	89:552587b429a1	408	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	409	This parameter must be a number between Min_Data = 50 and Max_Data = 432
Kojto	122:f9eeca106725	410	Except for STM32F411xE devices where the Min_Data = 192.
bogdanm	89:552587b429a1	411	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	412
bogdanm	89:552587b429a1	413	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	89:552587b429a1	414	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	89:552587b429a1	415	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	416
bogdanm	89:552587b429a1	417	}RCC_PLLI2SInitTypeDef;
bogdanm	89:552587b429a1	418
bogdanm	89:552587b429a1	419	/**
bogdanm	89:552587b429a1	420	* @brief RCC extended clocks structure definition
bogdanm	89:552587b429a1	421	*/
bogdanm	89:552587b429a1	422	typedef struct
bogdanm	89:552587b429a1	423	{
bogdanm	89:552587b429a1	424	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	89:552587b429a1	425	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	89:552587b429a1	426
bogdanm	89:552587b429a1	427	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	89:552587b429a1	428	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	429
bogdanm	89:552587b429a1	430	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto	110:165afa46840b	431	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	122:f9eeca106725	432	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	122:f9eeca106725	433	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	122:f9eeca106725	434	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	122:f9eeca106725	435	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	89:552587b429a1	436	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	437	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	438	/**
Kojto	99:dbbf35b96557	439	* @}
Kojto	99:dbbf35b96557	440	*/
Kojto	99:dbbf35b96557	441
bogdanm	89:552587b429a1	442	/* Exported constants --------------------------------------------------------*/
Kojto	99:dbbf35b96557	443	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm	89:552587b429a1	444	* @{
bogdanm	89:552587b429a1	445	*/
bogdanm	89:552587b429a1	446
Kojto	99:dbbf35b96557	447	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
bogdanm	89:552587b429a1	448	* @{
bogdanm	89:552587b429a1	449	*/
Kojto	122:f9eeca106725	450	/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
AnnaBridge	145:64910690c574	451	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	145:64910690c574	452	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	453	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
AnnaBridge	145:64910690c574	454	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
AnnaBridge	145:64910690c574	455	#define RCC_PERIPHCLK_TIM 0x00000004U
AnnaBridge	145:64910690c574	456	#define RCC_PERIPHCLK_RTC 0x00000008U
AnnaBridge	145:64910690c574	457	#define RCC_PERIPHCLK_FMPI2C1 0x00000010U
AnnaBridge	145:64910690c574	458	#define RCC_PERIPHCLK_CLK48 0x00000020U
AnnaBridge	145:64910690c574	459	#define RCC_PERIPHCLK_SDIO 0x00000040U
AnnaBridge	145:64910690c574	460	#define RCC_PERIPHCLK_PLLI2S 0x00000080U
AnnaBridge	145:64910690c574	461	#define RCC_PERIPHCLK_DFSDM1 0x00000100U
AnnaBridge	145:64910690c574	462	#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
Kojto	122:f9eeca106725	463	#endif /* STM32F412Zx \|\| STM32F412Vx) \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	145:64910690c574	464	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	465	#define RCC_PERIPHCLK_DFSDM2 0x00000400U
AnnaBridge	145:64910690c574	466	#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
AnnaBridge	145:64910690c574	467	#define RCC_PERIPHCLK_LPTIM1 0x00001000U
AnnaBridge	145:64910690c574	468	#define RCC_PERIPHCLK_SAIA 0x00002000U
AnnaBridge	145:64910690c574	469	#define RCC_PERIPHCLK_SAIB 0x00004000U
AnnaBridge	145:64910690c574	470	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	471	/----------------------------------------------------------------------------/
Kojto	122:f9eeca106725	472
Kojto	110:165afa46840b	473	/------------------- Peripheral Clock source for STM32F410xx ----------------/
Kojto	110:165afa46840b	474	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	145:64910690c574	475	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	145:64910690c574	476	#define RCC_PERIPHCLK_TIM 0x00000002U
AnnaBridge	145:64910690c574	477	#define RCC_PERIPHCLK_RTC 0x00000004U
AnnaBridge	145:64910690c574	478	#define RCC_PERIPHCLK_FMPI2C1 0x00000008U
AnnaBridge	145:64910690c574	479	#define RCC_PERIPHCLK_LPTIM1 0x00000010U
Kojto	110:165afa46840b	480	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	481	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	482
Kojto	110:165afa46840b	483	/------------------- Peripheral Clock source for STM32F446xx ----------------/
Kojto	99:dbbf35b96557	484	#if defined(STM32F446xx)
AnnaBridge	145:64910690c574	485	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
AnnaBridge	145:64910690c574	486	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
AnnaBridge	145:64910690c574	487	#define RCC_PERIPHCLK_SAI1 0x00000004U
AnnaBridge	145:64910690c574	488	#define RCC_PERIPHCLK_SAI2 0x00000008U
AnnaBridge	145:64910690c574	489	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	145:64910690c574	490	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	145:64910690c574	491	#define RCC_PERIPHCLK_CEC 0x00000040U
AnnaBridge	145:64910690c574	492	#define RCC_PERIPHCLK_FMPI2C1 0x00000080U
AnnaBridge	145:64910690c574	493	#define RCC_PERIPHCLK_CLK48 0x00000100U
AnnaBridge	145:64910690c574	494	#define RCC_PERIPHCLK_SDIO 0x00000200U
AnnaBridge	145:64910690c574	495	#define RCC_PERIPHCLK_SPDIFRX 0x00000400U
AnnaBridge	145:64910690c574	496	#define RCC_PERIPHCLK_PLLI2S 0x00000800U
Kojto	99:dbbf35b96557	497	#endif /* STM32F446xx */
Kojto	110:165afa46840b	498	/-----------------------------------------------------------------------------/
Kojto	110:165afa46840b	499
Kojto	110:165afa46840b	500	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
Kojto	110:165afa46840b	501	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	145:64910690c574	502	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	145:64910690c574	503	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
AnnaBridge	145:64910690c574	504	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
AnnaBridge	145:64910690c574	505	#define RCC_PERIPHCLK_LTDC 0x00000008U
AnnaBridge	145:64910690c574	506	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	145:64910690c574	507	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	145:64910690c574	508	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
AnnaBridge	145:64910690c574	509	#define RCC_PERIPHCLK_CLK48 0x00000080U
AnnaBridge	145:64910690c574	510	#define RCC_PERIPHCLK_SDIO 0x00000100U
Kojto	110:165afa46840b	511	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	512	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	513
Kojto	110:165afa46840b	514	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
Kojto	99:dbbf35b96557	515	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	145:64910690c574	516	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	145:64910690c574	517	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
AnnaBridge	145:64910690c574	518	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
AnnaBridge	145:64910690c574	519	#define RCC_PERIPHCLK_LTDC 0x00000008U
AnnaBridge	145:64910690c574	520	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	145:64910690c574	521	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	145:64910690c574	522	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
bogdanm	89:552587b429a1	523	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	110:165afa46840b	524	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	525
Kojto	110:165afa46840b	526	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
bogdanm	92:4fc01daae5a5	527	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	92:4fc01daae5a5	528	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	145:64910690c574	529	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	145:64910690c574	530	#define RCC_PERIPHCLK_RTC 0x00000002U
AnnaBridge	145:64910690c574	531	#define RCC_PERIPHCLK_PLLI2S 0x00000004U
bogdanm	92:4fc01daae5a5	532	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	122:f9eeca106725	533	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	145:64910690c574	534	#define RCC_PERIPHCLK_TIM 0x00000008U
Kojto	122:f9eeca106725	535	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	110:165afa46840b	536	/----------------------------------------------------------------------------/
bogdanm	89:552587b429a1	537	/**
bogdanm	89:552587b429a1	538	* @}
bogdanm	89:552587b429a1	539	*/
Kojto	110:165afa46840b	540	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	541	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	145:64910690c574	542	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\| \
AnnaBridge	145:64910690c574	543	defined(STM32F479xx)
Kojto	110:165afa46840b	544	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
Kojto	110:165afa46840b	545	* @{
Kojto	110:165afa46840b	546	*/
AnnaBridge	145:64910690c574	547	#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	145:64910690c574	548	#define RCC_I2SCLKSOURCE_EXT 0x00000001U
Kojto	110:165afa46840b	549	/**
Kojto	110:165afa46840b	550	* @}
Kojto	110:165afa46840b	551	*/
Kojto	110:165afa46840b	552	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	145:64910690c574	553	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	554
Kojto	99:dbbf35b96557	555	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
bogdanm	89:552587b429a1	556	* @{
Kojto	99:dbbf35b96557	557	*/
Kojto	110:165afa46840b	558	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	559	defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	145:64910690c574	560	#define RCC_PLLSAIDIVR_2 0x00000000U
AnnaBridge	145:64910690c574	561	#define RCC_PLLSAIDIVR_4 0x00010000U
AnnaBridge	145:64910690c574	562	#define RCC_PLLSAIDIVR_8 0x00020000U
AnnaBridge	145:64910690c574	563	#define RCC_PLLSAIDIVR_16 0x00030000U
Kojto	110:165afa46840b	564	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	565	/**
bogdanm	89:552587b429a1	566	* @}
bogdanm	89:552587b429a1	567	*/
bogdanm	89:552587b429a1	568
Kojto	99:dbbf35b96557	569	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
bogdanm	89:552587b429a1	570	* @{
bogdanm	89:552587b429a1	571	*/
Kojto	122:f9eeca106725	572	#if defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	573	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
AnnaBridge	145:64910690c574	574	#define RCC_PLLI2SP_DIV2 0x00000002U
AnnaBridge	145:64910690c574	575	#define RCC_PLLI2SP_DIV4 0x00000004U
AnnaBridge	145:64910690c574	576	#define RCC_PLLI2SP_DIV6 0x00000006U
AnnaBridge	145:64910690c574	577	#define RCC_PLLI2SP_DIV8 0x00000008U
Kojto	122:f9eeca106725	578	#endif /* STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
bogdanm	89:552587b429a1	579	/**
bogdanm	89:552587b429a1	580	* @}
bogdanm	89:552587b429a1	581	*/
bogdanm	89:552587b429a1	582
Kojto	99:dbbf35b96557	583	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
bogdanm	89:552587b429a1	584	* @{
Kojto	99:dbbf35b96557	585	*/
Kojto	110:165afa46840b	586	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	145:64910690c574	587	#define RCC_PLLSAIP_DIV2 0x00000002U
AnnaBridge	145:64910690c574	588	#define RCC_PLLSAIP_DIV4 0x00000004U
AnnaBridge	145:64910690c574	589	#define RCC_PLLSAIP_DIV6 0x00000006U
AnnaBridge	145:64910690c574	590	#define RCC_PLLSAIP_DIV8 0x00000008U
Kojto	110:165afa46840b	591	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	592	/**
bogdanm	89:552587b429a1	593	* @}
bogdanm	89:552587b429a1	594	*/
bogdanm	89:552587b429a1	595
Kojto	110:165afa46840b	596	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	597	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
bogdanm	89:552587b429a1	598	* @{
bogdanm	89:552587b429a1	599	*/
AnnaBridge	145:64910690c574	600	#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	145:64910690c574	601	#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
AnnaBridge	145:64910690c574	602	#define RCC_SAIACLKSOURCE_EXT 0x00200000U
bogdanm	89:552587b429a1	603	/**
bogdanm	89:552587b429a1	604	* @}
bogdanm	89:552587b429a1	605	*/
bogdanm	89:552587b429a1	606
Kojto	99:dbbf35b96557	607	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
bogdanm	89:552587b429a1	608	* @{
bogdanm	89:552587b429a1	609	*/
AnnaBridge	145:64910690c574	610	#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	145:64910690c574	611	#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
AnnaBridge	145:64910690c574	612	#define RCC_SAIBCLKSOURCE_EXT 0x00800000U
bogdanm	89:552587b429a1	613	/**
bogdanm	89:552587b429a1	614	* @}
bogdanm	89:552587b429a1	615	*/
Kojto	110:165afa46840b	616	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	617
Kojto	110:165afa46840b	618	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	619	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
Kojto	122:f9eeca106725	620	* @{
Kojto	122:f9eeca106725	621	*/
AnnaBridge	145:64910690c574	622	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
Kojto	122:f9eeca106725	623	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
Kojto	110:165afa46840b	624	/**
Kojto	110:165afa46840b	625	* @}
Kojto	110:165afa46840b	626	*/
Kojto	110:165afa46840b	627
Kojto	110:165afa46840b	628	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	110:165afa46840b	629	* @{
Kojto	110:165afa46840b	630	*/
AnnaBridge	145:64910690c574	631	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
Kojto	110:165afa46840b	632	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
Kojto	110:165afa46840b	633	/**
Kojto	110:165afa46840b	634	* @}
Kojto	110:165afa46840b	635	*/
Kojto	110:165afa46840b	636
Kojto	110:165afa46840b	637	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
Kojto	110:165afa46840b	638	* @{
Kojto	110:165afa46840b	639	*/
AnnaBridge	145:64910690c574	640	#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
Kojto	110:165afa46840b	641	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
Kojto	110:165afa46840b	642	/**
Kojto	110:165afa46840b	643	* @}
Kojto	110:165afa46840b	644	*/
Kojto	110:165afa46840b	645	#endif /* STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	646
Kojto	99:dbbf35b96557	647	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	648	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
Kojto	99:dbbf35b96557	649	* @{
Kojto	99:dbbf35b96557	650	*/
AnnaBridge	145:64910690c574	651	#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
Kojto	99:dbbf35b96557	652	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
Kojto	99:dbbf35b96557	653	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
Kojto	99:dbbf35b96557	654	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
Kojto	99:dbbf35b96557	655	/**
Kojto	99:dbbf35b96557	656	* @}
Kojto	99:dbbf35b96557	657	*/
Kojto	99:dbbf35b96557	658
Kojto	99:dbbf35b96557	659	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
Kojto	99:dbbf35b96557	660	* @{
Kojto	99:dbbf35b96557	661	*/
AnnaBridge	145:64910690c574	662	#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
Kojto	99:dbbf35b96557	663	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
Kojto	99:dbbf35b96557	664	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
Kojto	99:dbbf35b96557	665	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
Kojto	99:dbbf35b96557	666	/**
Kojto	99:dbbf35b96557	667	* @}
Kojto	99:dbbf35b96557	668	*/
Kojto	99:dbbf35b96557	669
Kojto	99:dbbf35b96557	670	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto	99:dbbf35b96557	671	* @{
Kojto	99:dbbf35b96557	672	*/
AnnaBridge	145:64910690c574	673	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
Kojto	99:dbbf35b96557	674	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
Kojto	99:dbbf35b96557	675	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
Kojto	99:dbbf35b96557	676	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto	99:dbbf35b96557	677	/**
Kojto	99:dbbf35b96557	678	* @}
Kojto	99:dbbf35b96557	679	*/
Kojto	99:dbbf35b96557	680
Kojto	99:dbbf35b96557	681	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto	99:dbbf35b96557	682	* @{
Kojto	99:dbbf35b96557	683	*/
AnnaBridge	145:64910690c574	684	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
Kojto	99:dbbf35b96557	685	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
Kojto	99:dbbf35b96557	686	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
Kojto	99:dbbf35b96557	687	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto	99:dbbf35b96557	688	/**
Kojto	99:dbbf35b96557	689	* @}
Kojto	99:dbbf35b96557	690	*/
Kojto	99:dbbf35b96557	691
Kojto	99:dbbf35b96557	692	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	99:dbbf35b96557	693	* @{
Kojto	99:dbbf35b96557	694	*/
AnnaBridge	145:64910690c574	695	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	145:64910690c574	696	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
AnnaBridge	145:64910690c574	697	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	99:dbbf35b96557	698	/**
Kojto	99:dbbf35b96557	699	* @}
Kojto	99:dbbf35b96557	700	*/
Kojto	99:dbbf35b96557	701
Kojto	99:dbbf35b96557	702	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
Kojto	99:dbbf35b96557	703	* @{
Kojto	99:dbbf35b96557	704	*/
AnnaBridge	145:64910690c574	705	#define RCC_CECCLKSOURCE_HSI 0x00000000U
Kojto	99:dbbf35b96557	706	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
Kojto	99:dbbf35b96557	707	/**
Kojto	99:dbbf35b96557	708	* @}
Kojto	99:dbbf35b96557	709	*/
Kojto	99:dbbf35b96557	710
Kojto	122:f9eeca106725	711	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
Kojto	122:f9eeca106725	712	* @{
Kojto	122:f9eeca106725	713	*/
AnnaBridge	145:64910690c574	714	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
Kojto	122:f9eeca106725	715	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto	99:dbbf35b96557	716	/**
Kojto	99:dbbf35b96557	717	* @}
Kojto	99:dbbf35b96557	718	*/
Kojto	99:dbbf35b96557	719
Kojto	99:dbbf35b96557	720	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	99:dbbf35b96557	721	* @{
Kojto	99:dbbf35b96557	722	*/
AnnaBridge	145:64910690c574	723	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
Kojto	99:dbbf35b96557	724	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto	99:dbbf35b96557	725	/**
Kojto	99:dbbf35b96557	726	* @}
Kojto	99:dbbf35b96557	727	*/
Kojto	99:dbbf35b96557	728
Kojto	99:dbbf35b96557	729	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
Kojto	99:dbbf35b96557	730	* @{
Kojto	99:dbbf35b96557	731	*/
AnnaBridge	145:64910690c574	732	#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
AnnaBridge	145:64910690c574	733	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
Kojto	99:dbbf35b96557	734	/**
Kojto	99:dbbf35b96557	735	* @}
Kojto	99:dbbf35b96557	736	*/
Kojto	99:dbbf35b96557	737	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	738
AnnaBridge	145:64910690c574	739	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	740	/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
AnnaBridge	145:64910690c574	741	* @{
AnnaBridge	145:64910690c574	742	*/
AnnaBridge	145:64910690c574	743	#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
AnnaBridge	145:64910690c574	744	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
AnnaBridge	145:64910690c574	745	#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
AnnaBridge	145:64910690c574	746	#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 \| RCC_DCKCFGR_SAI1ASRC_1)
AnnaBridge	145:64910690c574	747	/**
AnnaBridge	145:64910690c574	748	* @}
AnnaBridge	145:64910690c574	749	*/
AnnaBridge	145:64910690c574	750
AnnaBridge	145:64910690c574	751	/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
AnnaBridge	145:64910690c574	752	* @{
AnnaBridge	145:64910690c574	753	*/
AnnaBridge	145:64910690c574	754	#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
AnnaBridge	145:64910690c574	755	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
AnnaBridge	145:64910690c574	756	#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
AnnaBridge	145:64910690c574	757	#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 \| RCC_DCKCFGR_SAI1BSRC_1)
AnnaBridge	145:64910690c574	758	/**
AnnaBridge	145:64910690c574	759	* @}
AnnaBridge	145:64910690c574	760	*/
AnnaBridge	145:64910690c574	761
AnnaBridge	145:64910690c574	762	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
AnnaBridge	145:64910690c574	763	* @{
AnnaBridge	145:64910690c574	764	*/
AnnaBridge	145:64910690c574	765	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	145:64910690c574	766	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
AnnaBridge	145:64910690c574	767	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	145:64910690c574	768	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	145:64910690c574	769	/**
AnnaBridge	145:64910690c574	770	* @}
AnnaBridge	145:64910690c574	771	*/
AnnaBridge	145:64910690c574	772
AnnaBridge	145:64910690c574	773
AnnaBridge	145:64910690c574	774	/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
AnnaBridge	145:64910690c574	775	* @{
AnnaBridge	145:64910690c574	776	*/
AnnaBridge	145:64910690c574	777	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
AnnaBridge	145:64910690c574	778	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
AnnaBridge	145:64910690c574	779	/**
AnnaBridge	145:64910690c574	780	* @}
AnnaBridge	145:64910690c574	781	*/
AnnaBridge	145:64910690c574	782
AnnaBridge	145:64910690c574	783	/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
AnnaBridge	145:64910690c574	784	* @{
AnnaBridge	145:64910690c574	785	*/
AnnaBridge	145:64910690c574	786	#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
AnnaBridge	145:64910690c574	787	#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
AnnaBridge	145:64910690c574	788	/**
AnnaBridge	145:64910690c574	789	* @}
AnnaBridge	145:64910690c574	790	*/
AnnaBridge	145:64910690c574	791
AnnaBridge	145:64910690c574	792	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	793
AnnaBridge	145:64910690c574	794	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	795	/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
Kojto	122:f9eeca106725	796	* @{
Kojto	122:f9eeca106725	797	*/
AnnaBridge	145:64910690c574	798	#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
AnnaBridge	145:64910690c574	799	#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
Kojto	122:f9eeca106725	800	/**
Kojto	122:f9eeca106725	801	* @}
Kojto	122:f9eeca106725	802	*/
Kojto	122:f9eeca106725	803
Kojto	122:f9eeca106725	804	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
Kojto	122:f9eeca106725	805	* @{
Kojto	122:f9eeca106725	806	*/
AnnaBridge	145:64910690c574	807	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
AnnaBridge	145:64910690c574	808	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
Kojto	122:f9eeca106725	809	/**
Kojto	122:f9eeca106725	810	* @}
Kojto	122:f9eeca106725	811	*/
Kojto	122:f9eeca106725	812
Kojto	122:f9eeca106725	813	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
Kojto	122:f9eeca106725	814	* @{
Kojto	122:f9eeca106725	815	*/
AnnaBridge	145:64910690c574	816	#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
AnnaBridge	145:64910690c574	817	#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
Kojto	122:f9eeca106725	818	/**
Kojto	122:f9eeca106725	819	* @}
Kojto	122:f9eeca106725	820	*/
Kojto	122:f9eeca106725	821
Kojto	122:f9eeca106725	822	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto	122:f9eeca106725	823	* @{
Kojto	122:f9eeca106725	824	*/
AnnaBridge	145:64910690c574	825	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	145:64910690c574	826	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
AnnaBridge	145:64910690c574	827	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
AnnaBridge	145:64910690c574	828	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto	122:f9eeca106725	829	/**
Kojto	122:f9eeca106725	830	* @}
Kojto	122:f9eeca106725	831	*/
Kojto	122:f9eeca106725	832
Kojto	122:f9eeca106725	833	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto	122:f9eeca106725	834	* @{
Kojto	122:f9eeca106725	835	*/
AnnaBridge	145:64910690c574	836	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	145:64910690c574	837	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
AnnaBridge	145:64910690c574	838	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
AnnaBridge	145:64910690c574	839	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto	122:f9eeca106725	840	/**
Kojto	122:f9eeca106725	841	* @}
Kojto	122:f9eeca106725	842	*/
Kojto	122:f9eeca106725	843
Kojto	122:f9eeca106725	844	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	122:f9eeca106725	845	* @{
Kojto	122:f9eeca106725	846	*/
AnnaBridge	145:64910690c574	847	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	145:64910690c574	848	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
AnnaBridge	145:64910690c574	849	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	122:f9eeca106725	850	/**
Kojto	122:f9eeca106725	851	* @}
Kojto	122:f9eeca106725	852	*/
Kojto	122:f9eeca106725	853
Kojto	122:f9eeca106725	854	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
Kojto	122:f9eeca106725	855	* @{
Kojto	122:f9eeca106725	856	*/
AnnaBridge	145:64910690c574	857	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
AnnaBridge	145:64910690c574	858	#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto	122:f9eeca106725	859	/**
Kojto	122:f9eeca106725	860	* @}
Kojto	122:f9eeca106725	861	*/
Kojto	122:f9eeca106725	862
Kojto	122:f9eeca106725	863	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	122:f9eeca106725	864	* @{
Kojto	122:f9eeca106725	865	*/
AnnaBridge	145:64910690c574	866	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
Kojto	122:f9eeca106725	867	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto	122:f9eeca106725	868	/**
Kojto	122:f9eeca106725	869	* @}
Kojto	122:f9eeca106725	870	*/
AnnaBridge	145:64910690c574	871	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	872
Kojto	110:165afa46840b	873	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	874	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
Kojto	110:165afa46840b	875	* @{
Kojto	110:165afa46840b	876	*/
AnnaBridge	145:64910690c574	877	#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
Kojto	110:165afa46840b	878	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
Kojto	110:165afa46840b	879	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
Kojto	110:165afa46840b	880	/**
Kojto	110:165afa46840b	881	* @}
Kojto	110:165afa46840b	882	*/
Kojto	110:165afa46840b	883
Kojto	110:165afa46840b	884	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	110:165afa46840b	885	* @{
Kojto	110:165afa46840b	886	*/
AnnaBridge	145:64910690c574	887	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
Kojto	110:165afa46840b	888	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	110:165afa46840b	889	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	110:165afa46840b	890	/**
Kojto	110:165afa46840b	891	* @}
Kojto	110:165afa46840b	892	*/
Kojto	110:165afa46840b	893
Kojto	110:165afa46840b	894	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
Kojto	110:165afa46840b	895	* @{
Kojto	110:165afa46840b	896	*/
AnnaBridge	145:64910690c574	897	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
Kojto	110:165afa46840b	898	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
Kojto	110:165afa46840b	899	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
Kojto	110:165afa46840b	900	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
Kojto	110:165afa46840b	901	/**
Kojto	110:165afa46840b	902	* @}
Kojto	110:165afa46840b	903	*/
Kojto	110:165afa46840b	904	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	905
Kojto	110:165afa46840b	906	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	122:f9eeca106725	907	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
Kojto	122:f9eeca106725	908	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	122:f9eeca106725	909	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	145:64910690c574	910	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	110:165afa46840b	911	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
Kojto	110:165afa46840b	912	* @{
Kojto	110:165afa46840b	913	*/
AnnaBridge	145:64910690c574	914	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
AnnaBridge	145:64910690c574	915	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
Kojto	110:165afa46840b	916	/**
Kojto	110:165afa46840b	917	* @}
Kojto	110:165afa46840b	918	*/
Kojto	110:165afa46840b	919	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
Kojto	122:f9eeca106725	920	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
AnnaBridge	145:64910690c574	921	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	110:165afa46840b	922
Kojto	110:165afa46840b	923	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
Kojto	122:f9eeca106725	924	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
AnnaBridge	145:64910690c574	925	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
AnnaBridge	145:64910690c574	926	defined(STM32F423xx)
Kojto	99:dbbf35b96557	927	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
bogdanm	92:4fc01daae5a5	928	* @{
bogdanm	92:4fc01daae5a5	929	*/
AnnaBridge	145:64910690c574	930	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
AnnaBridge	145:64910690c574	931	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
Kojto	122:f9eeca106725	932	/**
Kojto	122:f9eeca106725	933	* @}
Kojto	122:f9eeca106725	934	*/
Kojto	122:f9eeca106725	935	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
Kojto	122:f9eeca106725	936	STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	937
Kojto	110:165afa46840b	938	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	939	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	940	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	941	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	145:64910690c574	942	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	110:165afa46840b	943	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto	110:165afa46840b	944	* @{
Kojto	110:165afa46840b	945	*/
AnnaBridge	145:64910690c574	946	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
Kojto	110:165afa46840b	947	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
Kojto	110:165afa46840b	948	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	110:165afa46840b	949	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	110:165afa46840b	950	/**
Kojto	110:165afa46840b	951	* @}
Kojto	110:165afa46840b	952	*/
Kojto	110:165afa46840b	953	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	954	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	145:64910690c574	955	STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
Kojto	110:165afa46840b	956
Kojto	110:165afa46840b	957	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	958	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto	110:165afa46840b	959	* @{
Kojto	110:165afa46840b	960	*/
AnnaBridge	145:64910690c574	961	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
Kojto	110:165afa46840b	962	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
Kojto	110:165afa46840b	963	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	110:165afa46840b	964	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	110:165afa46840b	965	/**
Kojto	110:165afa46840b	966	* @}
Kojto	110:165afa46840b	967	*/
Kojto	110:165afa46840b	968	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	969
bogdanm	89:552587b429a1	970	/**
bogdanm	89:552587b429a1	971	* @}
bogdanm	89:552587b429a1	972	*/
bogdanm	89:552587b429a1	973
bogdanm	89:552587b429a1	974	/* Exported macro ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	975	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	99:dbbf35b96557	976	* @{
Kojto	99:dbbf35b96557	977	*/
Kojto	110:165afa46840b	978	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
Kojto	110:165afa46840b	979	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	980	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	981	* @brief Enables or disables the AHB1 peripheral clock.
bogdanm	89:552587b429a1	982	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	983	* is disabled and the application software has to enable this clock before
bogdanm	89:552587b429a1	984	* using it.
Kojto	122:f9eeca106725	985	* @{
bogdanm	89:552587b429a1	986	*/
Kojto	110:165afa46840b	987	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	988	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	989	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	990	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	991	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	992	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	993	} while(0U)
Kojto	110:165afa46840b	994	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	995	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	996	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	997	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	998	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	999	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1000	} while(0U)
Kojto	110:165afa46840b	1001	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1002	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1003	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	1004	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1005	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	1006	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1007	} while(0U)
Kojto	122:f9eeca106725	1008	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1009	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1010	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	1011	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1012	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	1013	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1014	} while(0U)
Kojto	122:f9eeca106725	1015	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1016	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1017	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	1018	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1019	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	1020	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1021	} while(0U)
Kojto	99:dbbf35b96557	1022	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1023	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1024	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	1025	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1026	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	1027	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1028	} while(0U)
Kojto	99:dbbf35b96557	1029	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1030	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1031	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1032	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1033	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1034	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1035	} while(0U)
Kojto	99:dbbf35b96557	1036	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1037	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1038	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1039	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1040	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1041	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1042	} while(0U)
Kojto	99:dbbf35b96557	1043	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1044	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1045	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	99:dbbf35b96557	1046	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1047	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	99:dbbf35b96557	1048	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1049	} while(0U)
Kojto	99:dbbf35b96557	1050	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1051	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1052	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	99:dbbf35b96557	1053	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1054	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	99:dbbf35b96557	1055	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1056	} while(0U)
Kojto	99:dbbf35b96557	1057	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1058	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1059	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	99:dbbf35b96557	1060	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1061	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	99:dbbf35b96557	1062	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1063	} while(0U)
Kojto	99:dbbf35b96557	1064	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1065	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1066	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	1067	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1068	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	1069	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1070	} while(0U)
Kojto	99:dbbf35b96557	1071	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1072	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1073	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	1074	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1075	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	1076	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1077	} while(0U)
Kojto	99:dbbf35b96557	1078	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1079	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1080	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	1081	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1082	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	1083	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1084	} while(0U)
Kojto	99:dbbf35b96557	1085	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1086	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1087	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	1088	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1089	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	1090	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1091	} while(0U)
Kojto	99:dbbf35b96557	1092	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1093	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1094	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1095	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1096	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1097	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1098	} while(0U)
Kojto	99:dbbf35b96557	1099	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1100	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1101	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1102	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1103	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1104	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1105	} while(0U)
Kojto	110:165afa46840b	1106	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	1107	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	1108	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	1109	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	1110	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	99:dbbf35b96557	1111	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto	99:dbbf35b96557	1112	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto	99:dbbf35b96557	1113	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto	99:dbbf35b96557	1114	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	99:dbbf35b96557	1115	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	99:dbbf35b96557	1116	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	99:dbbf35b96557	1117	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	99:dbbf35b96557	1118	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	1119	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	1120	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	1121	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	1122	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm	92:4fc01daae5a5	1123
bogdanm	92:4fc01daae5a5	1124	/**
bogdanm	92:4fc01daae5a5	1125	* @brief Enable ETHERNET clock.
bogdanm	92:4fc01daae5a5	1126	*/
Kojto	99:dbbf35b96557	1127	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1128	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1129	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1130	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge	145:64910690c574	1131	} while(0U)
bogdanm	92:4fc01daae5a5	1132	/**
bogdanm	92:4fc01daae5a5	1133	* @brief Disable ETHERNET clock.
bogdanm	92:4fc01daae5a5	1134	*/
Kojto	99:dbbf35b96557	1135	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	99:dbbf35b96557	1136	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1137	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1138	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge	145:64910690c574	1139	} while(0U)
Kojto	110:165afa46840b	1140	/**
Kojto	110:165afa46840b	1141	* @}
Kojto	110:165afa46840b	1142	*/
Kojto	122:f9eeca106725	1143
Kojto	122:f9eeca106725	1144	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1145	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	1146	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1147	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1148	* using it.
Kojto	122:f9eeca106725	1149	* @{
Kojto	122:f9eeca106725	1150	*/
Kojto	122:f9eeca106725	1151	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	1152	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	1153	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	1154	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	122:f9eeca106725	1155	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
Kojto	122:f9eeca106725	1156	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
Kojto	122:f9eeca106725	1157	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
Kojto	122:f9eeca106725	1158	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
Kojto	122:f9eeca106725	1159	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Kojto	122:f9eeca106725	1160	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
Kojto	122:f9eeca106725	1161	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
Kojto	122:f9eeca106725	1162	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
Kojto	122:f9eeca106725	1163	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto	122:f9eeca106725	1164	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto	122:f9eeca106725	1165	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	122:f9eeca106725	1166	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
Kojto	122:f9eeca106725	1167	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	1168	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
Kojto	122:f9eeca106725	1169	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
Kojto	122:f9eeca106725	1170	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
Kojto	122:f9eeca106725	1171
Kojto	122:f9eeca106725	1172	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	1173	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	1174	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	1175	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	122:f9eeca106725	1176	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
Kojto	122:f9eeca106725	1177	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
Kojto	122:f9eeca106725	1178	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
Kojto	122:f9eeca106725	1179	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
Kojto	122:f9eeca106725	1180	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Kojto	122:f9eeca106725	1181	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
Kojto	122:f9eeca106725	1182	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
Kojto	122:f9eeca106725	1183	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
Kojto	122:f9eeca106725	1184	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto	122:f9eeca106725	1185	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
Kojto	122:f9eeca106725	1186	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	122:f9eeca106725	1187	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	1188	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	1189	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
Kojto	122:f9eeca106725	1190	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
Kojto	122:f9eeca106725	1191	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
Kojto	122:f9eeca106725	1192	/**
Kojto	122:f9eeca106725	1193	* @}
Kojto	122:f9eeca106725	1194	*/
Kojto	122:f9eeca106725	1195
Kojto	110:165afa46840b	1196	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1197	* @brief Enable or disable the AHB2 peripheral clock.
bogdanm	92:4fc01daae5a5	1198	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1199	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	1200	* using it.
Kojto	122:f9eeca106725	1201	* @{
bogdanm	92:4fc01daae5a5	1202	*/
Kojto	110:165afa46840b	1203	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1204	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1205	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1206	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1207	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1208	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1209	} while(0U)
Kojto	99:dbbf35b96557	1210	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	92:4fc01daae5a5	1211
Kojto	110:165afa46840b	1212	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1213	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1214	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1215	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	1216	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1217	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	1218	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1219	} while(0U)
Kojto	99:dbbf35b96557	1220	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1221	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1222	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	1223	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1224	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	1225	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1226	} while(0U)
bogdanm	92:4fc01daae5a5	1227
Kojto	99:dbbf35b96557	1228	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	99:dbbf35b96557	1229	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	110:165afa46840b	1230	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1231
Kojto	110:165afa46840b	1232	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	1233	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	145:64910690c574	1234	}while(0U)
Kojto	110:165afa46840b	1235
Kojto	122:f9eeca106725	1236	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	110:165afa46840b	1237
Kojto	110:165afa46840b	1238	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1239	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1240	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	1241	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1242	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	1243	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1244	} while(0U)
Kojto	110:165afa46840b	1245	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	1246	/**
Kojto	110:165afa46840b	1247	* @}
Kojto	110:165afa46840b	1248	*/
Kojto	122:f9eeca106725	1249
Kojto	122:f9eeca106725	1250	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1251	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	1252	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1253	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1254	* using it.
Kojto	122:f9eeca106725	1255	* @{
Kojto	122:f9eeca106725	1256	*/
Kojto	122:f9eeca106725	1257	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto	122:f9eeca106725	1258	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto	122:f9eeca106725	1259
Kojto	122:f9eeca106725	1260	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1261	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
Kojto	122:f9eeca106725	1262	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
Kojto	122:f9eeca106725	1263
Kojto	122:f9eeca106725	1264	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
Kojto	122:f9eeca106725	1265	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
Kojto	122:f9eeca106725	1266	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1267
Kojto	122:f9eeca106725	1268	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	1269	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	1270
Kojto	122:f9eeca106725	1271	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	122:f9eeca106725	1272	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	1273	/**
Kojto	122:f9eeca106725	1274	* @}
Kojto	122:f9eeca106725	1275	*/
Kojto	110:165afa46840b	1276
Kojto	110:165afa46840b	1277	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1278	* @brief Enables or disables the AHB3 peripheral clock.
bogdanm	92:4fc01daae5a5	1279	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1280	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1281	* using it.
Kojto	122:f9eeca106725	1282	* @{
bogdanm	92:4fc01daae5a5	1283	*/
Kojto	99:dbbf35b96557	1284	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1285	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1286	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	1287	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1288	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	1289	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1290	} while(0U)
Kojto	99:dbbf35b96557	1291	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	110:165afa46840b	1292	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1293	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1294	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1295	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	110:165afa46840b	1296	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1297	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	110:165afa46840b	1298	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1299	} while(0U)
Kojto	110:165afa46840b	1300	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	110:165afa46840b	1301	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1302	/**
Kojto	110:165afa46840b	1303	* @}
Kojto	110:165afa46840b	1304	*/
Kojto	110:165afa46840b	1305
Kojto	122:f9eeca106725	1306
Kojto	122:f9eeca106725	1307	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1308	* @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	122:f9eeca106725	1309	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1310	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1311	* using it.
Kojto	122:f9eeca106725	1312	* @{
Kojto	122:f9eeca106725	1313	*/
Kojto	122:f9eeca106725	1314	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Kojto	122:f9eeca106725	1315	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Kojto	122:f9eeca106725	1316	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1317	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto	122:f9eeca106725	1318	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto	122:f9eeca106725	1319	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1320	/**
Kojto	122:f9eeca106725	1321	* @}
Kojto	122:f9eeca106725	1322	*/
Kojto	122:f9eeca106725	1323
Kojto	110:165afa46840b	1324	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1325	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	92:4fc01daae5a5	1326	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1327	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1328	* using it.
Kojto	122:f9eeca106725	1329	* @{
bogdanm	92:4fc01daae5a5	1330	*/
Kojto	99:dbbf35b96557	1331	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1332	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1333	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1334	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1335	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1336	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1337	} while(0U)
Kojto	99:dbbf35b96557	1338	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1339	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1340	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1341	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1342	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1343	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1344	} while(0U)
Kojto	99:dbbf35b96557	1345	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1346	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1347	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1348	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1349	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1350	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1351	} while(0U)
Kojto	99:dbbf35b96557	1352	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1353	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1354	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1355	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1356	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1357	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1358	} while(0U)
Kojto	99:dbbf35b96557	1359	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1360	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1361	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1362	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1363	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1364	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1365	} while(0U)
Kojto	99:dbbf35b96557	1366	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1367	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1368	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1369	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1370	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1371	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1372	} while(0U)
Kojto	99:dbbf35b96557	1373	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1374	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1375	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1376	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1377	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1378	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1379	} while(0U)
Kojto	99:dbbf35b96557	1380	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1381	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1382	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1383	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1384	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1385	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1386	} while(0U)
Kojto	99:dbbf35b96557	1387	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1388	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1389	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1390	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1391	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1392	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1393	} while(0U)
Kojto	99:dbbf35b96557	1394	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1395	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1396	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1397	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1398	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1399	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1400	} while(0U)
Kojto	99:dbbf35b96557	1401	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1402	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1403	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1404	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1405	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1406	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1407	} while(0U)
Kojto	99:dbbf35b96557	1408	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1409	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1410	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1411	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1412	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1413	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1414	} while(0U)
Kojto	99:dbbf35b96557	1415	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1416	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1417	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	99:dbbf35b96557	1418	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1419	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	99:dbbf35b96557	1420	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1421	} while(0U)
Kojto	99:dbbf35b96557	1422	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1423	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1424	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	99:dbbf35b96557	1425	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1426	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	99:dbbf35b96557	1427	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1428	} while(0U)
Kojto	110:165afa46840b	1429	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1430	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1431	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	1432	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1433	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	1434	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1435	} while(0U)
Kojto	110:165afa46840b	1436	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1437	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1438	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	1439	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1440	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	1441	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1442	} while(0U)
Kojto	110:165afa46840b	1443	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1444	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1445	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	1446	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1447	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	1448	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1449	} while(0U)
Kojto	110:165afa46840b	1450	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1451	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1452	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	1453	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1454	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	1455	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1456	} while(0U)
Kojto	110:165afa46840b	1457	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1458	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1459	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	1460	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1461	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	1462	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1463	} while(0U)
Kojto	110:165afa46840b	1464	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	1465	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	1466	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	1467	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	1468	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	1469	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	1470	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	1471	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	1472	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	1473	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	1474	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	1475	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	1476	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	1477	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	1478	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	1479	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	99:dbbf35b96557	1480	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto	99:dbbf35b96557	1481	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto	110:165afa46840b	1482	/**
Kojto	110:165afa46840b	1483	* @}
Kojto	110:165afa46840b	1484	*/
Kojto	110:165afa46840b	1485
Kojto	122:f9eeca106725	1486	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1487	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	1488	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1489	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1490	* using it.
Kojto	122:f9eeca106725	1491	* @{
Kojto	122:f9eeca106725	1492	*/
Kojto	122:f9eeca106725	1493	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	1494	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	1495	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	1496	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	1497	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	1498	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	1499	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	122:f9eeca106725	1500	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	122:f9eeca106725	1501	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto	122:f9eeca106725	1502	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	122:f9eeca106725	1503	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	122:f9eeca106725	1504	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto	122:f9eeca106725	1505	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto	122:f9eeca106725	1506	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	122:f9eeca106725	1507	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto	122:f9eeca106725	1508	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	122:f9eeca106725	1509	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
Kojto	122:f9eeca106725	1510	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
Kojto	122:f9eeca106725	1511
Kojto	122:f9eeca106725	1512	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	1513	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	1514	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	1515	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	1516	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	1517	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	1518	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	122:f9eeca106725	1519	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	122:f9eeca106725	1520	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	122:f9eeca106725	1521	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	122:f9eeca106725	1522	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	122:f9eeca106725	1523	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto	122:f9eeca106725	1524	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto	122:f9eeca106725	1525	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	122:f9eeca106725	1526	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto	122:f9eeca106725	1527	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	122:f9eeca106725	1528	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
Kojto	122:f9eeca106725	1529	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
Kojto	122:f9eeca106725	1530	/**
Kojto	122:f9eeca106725	1531	* @}
Kojto	122:f9eeca106725	1532	*/
Kojto	122:f9eeca106725	1533
Kojto	110:165afa46840b	1534	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1535	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	92:4fc01daae5a5	1536	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1537	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	1538	* using it.
Kojto	122:f9eeca106725	1539	* @{
bogdanm	92:4fc01daae5a5	1540	*/
Kojto	99:dbbf35b96557	1541	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1542	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1543	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1544	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1545	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1546	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1547	} while(0U)
Kojto	99:dbbf35b96557	1548	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1549	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1550	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1551	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1552	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1553	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1554	} while(0U)
Kojto	99:dbbf35b96557	1555	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1556	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1557	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1558	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1559	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1560	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1561	} while(0U)
Kojto	99:dbbf35b96557	1562	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1563	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1564	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	1565	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1566	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	1567	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1568	} while(0U)
Kojto	99:dbbf35b96557	1569	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1570	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1571	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	99:dbbf35b96557	1572	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1573	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	99:dbbf35b96557	1574	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1575	} while(0U)
Kojto	99:dbbf35b96557	1576	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1577	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1578	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	1579	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1580	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	1581	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1582	} while(0U)
Kojto	110:165afa46840b	1583	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1584	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1585	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	1586	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1587	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	1588	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1589	} while(0U)
Kojto	110:165afa46840b	1590	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1591	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1592	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	1593	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1594	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	1595	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1596	} while(0U)
Kojto	110:165afa46840b	1597	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1598	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1599	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	1600	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1601	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	1602	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1603	} while(0U)
Kojto	110:165afa46840b	1604	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	1605	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	1606	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	1607	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	1608	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	1609	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	1610	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	1611	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto	110:165afa46840b	1612	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	110:165afa46840b	1613
Kojto	110:165afa46840b	1614	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1615	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1616	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1617	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	110:165afa46840b	1618	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1619	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	110:165afa46840b	1620	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1621	} while(0U)
bogdanm	92:4fc01daae5a5	1622
Kojto	99:dbbf35b96557	1623	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto	110:165afa46840b	1624	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1625
Kojto	110:165afa46840b	1626	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1627	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1628	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1629	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto	110:165afa46840b	1630	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1631	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto	110:165afa46840b	1632	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	1633	} while(0U)
Kojto	110:165afa46840b	1634
Kojto	110:165afa46840b	1635	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
Kojto	110:165afa46840b	1636	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1637	/**
Kojto	110:165afa46840b	1638	* @}
Kojto	110:165afa46840b	1639	*/
Kojto	122:f9eeca106725	1640
Kojto	122:f9eeca106725	1641	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1642	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	1643	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1644	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1645	* using it.
Kojto	122:f9eeca106725	1646	* @{
Kojto	122:f9eeca106725	1647	*/
Kojto	122:f9eeca106725	1648	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto	122:f9eeca106725	1649	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto	122:f9eeca106725	1650	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto	122:f9eeca106725	1651	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto	122:f9eeca106725	1652	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
Kojto	122:f9eeca106725	1653	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
Kojto	122:f9eeca106725	1654	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	1655	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	1656	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
Kojto	122:f9eeca106725	1657
Kojto	122:f9eeca106725	1658	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	1659	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	1660	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
Kojto	122:f9eeca106725	1661	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto	122:f9eeca106725	1662	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto	122:f9eeca106725	1663	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto	122:f9eeca106725	1664	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto	122:f9eeca106725	1665	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
Kojto	122:f9eeca106725	1666	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
Kojto	122:f9eeca106725	1667
Kojto	122:f9eeca106725	1668	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1669	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
Kojto	122:f9eeca106725	1670	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
Kojto	122:f9eeca106725	1671	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1672
Kojto	122:f9eeca106725	1673	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1674	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
Kojto	122:f9eeca106725	1675	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
Kojto	122:f9eeca106725	1676	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1677	/**
Kojto	122:f9eeca106725	1678	* @}
Kojto	122:f9eeca106725	1679	*/
Kojto	110:165afa46840b	1680
Kojto	110:165afa46840b	1681	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	1682	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	1683	* @{
Kojto	110:165afa46840b	1684	*/
Kojto	110:165afa46840b	1685	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	1686	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	1687	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1688	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1689	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	1690	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	1691	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	1692	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
Kojto	99:dbbf35b96557	1693	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
Kojto	99:dbbf35b96557	1694	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
Kojto	110:165afa46840b	1695	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	1696
Kojto	110:165afa46840b	1697	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	1698	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	1699	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1700	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1701	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	1702	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	1703	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	1704	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto	99:dbbf35b96557	1705	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto	99:dbbf35b96557	1706	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto	110:165afa46840b	1707	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	1708	/**
Kojto	110:165afa46840b	1709	* @}
Kojto	110:165afa46840b	1710	*/
Kojto	110:165afa46840b	1711
Kojto	110:165afa46840b	1712	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	1713	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	1714	* @{
Kojto	110:165afa46840b	1715	*/
Kojto	122:f9eeca106725	1716	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	1717	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	122:f9eeca106725	1718	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	1719	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	1720
Kojto	122:f9eeca106725	1721	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	1722	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	122:f9eeca106725	1723	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	1724	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	92:4fc01daae5a5	1725
Kojto	110:165afa46840b	1726	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1727	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	1728	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	92:4fc01daae5a5	1729
Kojto	99:dbbf35b96557	1730	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	1731	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	110:165afa46840b	1732	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1733	/**
Kojto	110:165afa46840b	1734	* @}
Kojto	110:165afa46840b	1735	*/
Kojto	110:165afa46840b	1736
Kojto	110:165afa46840b	1737	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	1738	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	1739	* @{
bogdanm	92:4fc01daae5a5	1740	*/
Kojto	122:f9eeca106725	1741	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	1742	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	99:dbbf35b96557	1743	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	1744	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	110:165afa46840b	1745
Kojto	122:f9eeca106725	1746	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1747	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	1748	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	1749	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1750	/**
Kojto	110:165afa46840b	1751	* @}
Kojto	110:165afa46840b	1752	*/
Kojto	110:165afa46840b	1753
Kojto	110:165afa46840b	1754	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	1755	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	1756	* @{
bogdanm	92:4fc01daae5a5	1757	*/
Kojto	99:dbbf35b96557	1758	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1759	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1760	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1761	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1762	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1763	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1764	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1765	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1766	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1767	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1768	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	1769	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
Kojto	99:dbbf35b96557	1770	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
Kojto	110:165afa46840b	1771	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	1772	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	1773	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	1774	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	1775	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	1776
Kojto	110:165afa46840b	1777	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	1778	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	1779	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	1780	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	1781	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	1782	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1783	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1784	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1785	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1786	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1787	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1788	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1789	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1790	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1791	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1792	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	1793	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto	99:dbbf35b96557	1794	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto	110:165afa46840b	1795	/**
Kojto	110:165afa46840b	1796	* @}
Kojto	110:165afa46840b	1797	*/
Kojto	110:165afa46840b	1798
Kojto	110:165afa46840b	1799	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	1800	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	1801	* @{
bogdanm	92:4fc01daae5a5	1802	*/
Kojto	99:dbbf35b96557	1803	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1804	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	1805	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
Kojto	99:dbbf35b96557	1806	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	1807	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	1808	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	1809	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	122:f9eeca106725	1810
Kojto	110:165afa46840b	1811	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	1812	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	1813	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	99:dbbf35b96557	1814	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1815	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	1816	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto	99:dbbf35b96557	1817	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
bogdanm	92:4fc01daae5a5	1818
Kojto	110:165afa46840b	1819	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1820	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
Kojto	99:dbbf35b96557	1821	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto	110:165afa46840b	1822	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1823
Kojto	110:165afa46840b	1824	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1825	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
Kojto	110:165afa46840b	1826	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
Kojto	110:165afa46840b	1827	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1828	/**
Kojto	110:165afa46840b	1829	* @}
Kojto	110:165afa46840b	1830	*/
Kojto	110:165afa46840b	1831
Kojto	110:165afa46840b	1832	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1833	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1834	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1835	* power consumption.
bogdanm	92:4fc01daae5a5	1836	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1837	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	1838	* @{
Kojto	110:165afa46840b	1839	*/
Kojto	110:165afa46840b	1840	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	1841	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	1842	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1843	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1844	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	1845	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1846	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1847	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1848	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1849	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1850	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1851	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1852	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto	99:dbbf35b96557	1853	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto	99:dbbf35b96557	1854	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto	99:dbbf35b96557	1855	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto	110:165afa46840b	1856	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	1857	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	1858	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	1859	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	1860
Kojto	110:165afa46840b	1861	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	1862	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	1863	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1864	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1865	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	1866	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1867	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1868	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1869	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1870	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1871	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1872	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1873	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto	99:dbbf35b96557	1874	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto	99:dbbf35b96557	1875	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto	110:165afa46840b	1876	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	1877	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	1878	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	1879	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	1880	/**
Kojto	110:165afa46840b	1881	* @}
Kojto	110:165afa46840b	1882	*/
Kojto	122:f9eeca106725	1883
Kojto	110:165afa46840b	1884	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1885	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1886	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1887	* power consumption.
Kojto	110:165afa46840b	1888	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1889	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	1890	* @{
Kojto	110:165afa46840b	1891	*/
Kojto	110:165afa46840b	1892	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	1893	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	1894
Kojto	110:165afa46840b	1895	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	1896	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	1897
Kojto	99:dbbf35b96557	1898	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	1899	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	92:4fc01daae5a5	1900
Kojto	110:165afa46840b	1901	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1902	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1903	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	92:4fc01daae5a5	1904
Kojto	99:dbbf35b96557	1905	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1906	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	110:165afa46840b	1907	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1908	/**
Kojto	110:165afa46840b	1909	* @}
Kojto	110:165afa46840b	1910	*/
Kojto	122:f9eeca106725	1911
Kojto	110:165afa46840b	1912	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1913	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1914	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1915	* power consumption.
bogdanm	92:4fc01daae5a5	1916	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1917	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	1918	* @{
bogdanm	92:4fc01daae5a5	1919	*/
Kojto	99:dbbf35b96557	1920	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	1921	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
bogdanm	92:4fc01daae5a5	1922
Kojto	110:165afa46840b	1923	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1924	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	1925	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	1926	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1927	/**
Kojto	110:165afa46840b	1928	* @}
Kojto	110:165afa46840b	1929	*/
Kojto	122:f9eeca106725	1930
Kojto	110:165afa46840b	1931	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1932	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1933	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1934	* power consumption.
bogdanm	92:4fc01daae5a5	1935	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1936	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	1937	* @{
bogdanm	92:4fc01daae5a5	1938	*/
Kojto	99:dbbf35b96557	1939	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1940	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1941	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1942	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1943	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1944	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1945	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1946	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1947	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1948	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1949	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1950	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
Kojto	99:dbbf35b96557	1951	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
Kojto	110:165afa46840b	1952	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	1953	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	1954	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	1955	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	1956	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	1957
Kojto	110:165afa46840b	1958	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	1959	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	1960	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	1961	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	1962	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	1963	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1964	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1965	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1966	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1967	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1968	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1969	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1970	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1971	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1972	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1973	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1974	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto	99:dbbf35b96557	1975	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto	110:165afa46840b	1976	/**
Kojto	110:165afa46840b	1977	* @}
Kojto	110:165afa46840b	1978	*/
Kojto	110:165afa46840b	1979
Kojto	110:165afa46840b	1980	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1981	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1982	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1983	* power consumption.
bogdanm	92:4fc01daae5a5	1984	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1985	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	1986	* @{
bogdanm	92:4fc01daae5a5	1987	*/
Kojto	99:dbbf35b96557	1988	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1989	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1990	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1991	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1992	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
Kojto	99:dbbf35b96557	1993	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	110:165afa46840b	1994	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	1995	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	1996	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	1997
Kojto	110:165afa46840b	1998	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	1999	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2000	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	2001	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	2002	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	2003	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	2004	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	2005	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto	99:dbbf35b96557	2006	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
bogdanm	92:4fc01daae5a5	2007
Kojto	110:165afa46840b	2008	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	2009	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
bogdanm	92:4fc01daae5a5	2010
Kojto	99:dbbf35b96557	2011	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto	110:165afa46840b	2012	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	2013
Kojto	110:165afa46840b	2014	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	2015	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
Kojto	110:165afa46840b	2016	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
Kojto	110:165afa46840b	2017	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	2018	/**
Kojto	110:165afa46840b	2019	* @}
Kojto	110:165afa46840b	2020	*/
Kojto	110:165afa46840b	2021	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	2022	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	2023
Kojto	110:165afa46840b	2024	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
bogdanm	92:4fc01daae5a5	2025	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	110:165afa46840b	2026	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2027	* @brief Enables or disables the AHB1 peripheral clock.
bogdanm	92:4fc01daae5a5	2028	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	2029	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	2030	* using it.
Kojto	122:f9eeca106725	2031	* @{
bogdanm	92:4fc01daae5a5	2032	*/
Kojto	110:165afa46840b	2033	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2034	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2035	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	2036	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2037	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	2038	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2039	} while(0U)
Kojto	110:165afa46840b	2040	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2041	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2042	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2043	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2044	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2045	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2046	} while(0U)
Kojto	110:165afa46840b	2047	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2048	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2049	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2050	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2051	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2052	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2053	} while(0U)
Kojto	122:f9eeca106725	2054	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2055	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2056	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2057	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2058	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2059	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2060	} while(0U)
Kojto	122:f9eeca106725	2061	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2062	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2063	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2064	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2065	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2066	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2067	} while(0U)
Kojto	99:dbbf35b96557	2068	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2069	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2070	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	2071	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2072	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	2073	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2074	} while(0U)
Kojto	99:dbbf35b96557	2075	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2076	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2077	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	2078	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2079	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	2080	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2081	} while(0U)
Kojto	99:dbbf35b96557	2082	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2083	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2084	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	2085	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2086	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	2087	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2088	} while(0U)
Kojto	99:dbbf35b96557	2089	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2090	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2091	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	2092	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2093	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	2094	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2095	} while(0U)
Kojto	99:dbbf35b96557	2096	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2097	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2098	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	2099	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2100	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	2101	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2102	} while(0U)
Kojto	110:165afa46840b	2103	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	2104	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	2105	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	2106	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	2107	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	99:dbbf35b96557	2108	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	2109	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	2110	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	2111	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	2112	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm	92:4fc01daae5a5	2113	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	2114	/**
bogdanm	92:4fc01daae5a5	2115	* @brief Enable ETHERNET clock.
bogdanm	92:4fc01daae5a5	2116	*/
Kojto	99:dbbf35b96557	2117	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2118	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2119	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	2120	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2121	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	2122	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2123	} while(0U)
Kojto	99:dbbf35b96557	2124	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2125	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2126	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	2127	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2128	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	2129	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2130	} while(0U)
Kojto	99:dbbf35b96557	2131	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2132	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2133	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	2134	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2135	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	2136	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2137	} while(0U)
Kojto	99:dbbf35b96557	2138	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2139	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2140	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	2141	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2142	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	2143	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2144	} while(0U)
Kojto	99:dbbf35b96557	2145	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	2146	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	2147	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	2148	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge	145:64910690c574	2149	} while(0U)
bogdanm	89:552587b429a1	2150
bogdanm	89:552587b429a1	2151	/**
bogdanm	89:552587b429a1	2152	* @brief Disable ETHERNET clock.
bogdanm	89:552587b429a1	2153	*/
Kojto	99:dbbf35b96557	2154	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	99:dbbf35b96557	2155	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	99:dbbf35b96557	2156	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	99:dbbf35b96557	2157	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	99:dbbf35b96557	2158	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
AnnaBridge	145:64910690c574	2159	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
AnnaBridge	145:64910690c574	2160	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
AnnaBridge	145:64910690c574	2161	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge	145:64910690c574	2162	} while(0U)
bogdanm	92:4fc01daae5a5	2163	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2164	/**
Kojto	110:165afa46840b	2165	* @}
Kojto	110:165afa46840b	2166	*/
Kojto	122:f9eeca106725	2167
Kojto	122:f9eeca106725	2168	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2169	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	2170	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2171	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2172	* using it.
Kojto	122:f9eeca106725	2173	* @{
Kojto	122:f9eeca106725	2174	*/
Kojto	122:f9eeca106725	2175	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	122:f9eeca106725	2176	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
Kojto	122:f9eeca106725	2177	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	2178	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	2179	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	2180	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
Kojto	122:f9eeca106725	2181	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	2182	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	122:f9eeca106725	2183	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto	122:f9eeca106725	2184	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto	122:f9eeca106725	2185
Kojto	122:f9eeca106725	2186	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	2187	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	2188	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	2189	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	122:f9eeca106725	2190	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
Kojto	122:f9eeca106725	2191	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto	122:f9eeca106725	2192	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
Kojto	122:f9eeca106725	2193	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	122:f9eeca106725	2194	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	2195	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	2196	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	122:f9eeca106725	2197	/**
Kojto	122:f9eeca106725	2198	* @brief Enable ETHERNET clock.
Kojto	122:f9eeca106725	2199	*/
Kojto	122:f9eeca106725	2200	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Kojto	122:f9eeca106725	2201	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
Kojto	122:f9eeca106725	2202	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
Kojto	122:f9eeca106725	2203	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
Kojto	122:f9eeca106725	2204	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
Kojto	122:f9eeca106725	2205	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
Kojto	122:f9eeca106725	2206	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
Kojto	122:f9eeca106725	2207	/**
Kojto	122:f9eeca106725	2208	* @brief Disable ETHERNET clock.
Kojto	122:f9eeca106725	2209	*/
Kojto	122:f9eeca106725	2210	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Kojto	122:f9eeca106725	2211	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
Kojto	122:f9eeca106725	2212	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
Kojto	122:f9eeca106725	2213	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
Kojto	122:f9eeca106725	2214	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
Kojto	122:f9eeca106725	2215	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
Kojto	122:f9eeca106725	2216	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
Kojto	122:f9eeca106725	2217	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	122:f9eeca106725	2218	/**
Kojto	122:f9eeca106725	2219	* @}
Kojto	122:f9eeca106725	2220	*/
Kojto	122:f9eeca106725	2221
Kojto	110:165afa46840b	2222	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2223	* @brief Enable or disable the AHB2 peripheral clock.
bogdanm	89:552587b429a1	2224	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	2225	* is disabled and the application software has to enable this clock before
bogdanm	89:552587b429a1	2226	* using it.
Kojto	122:f9eeca106725	2227	* @{
bogdanm	89:552587b429a1	2228	*/
Kojto	110:165afa46840b	2229	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	2230	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	145:64910690c574	2231	}while(0U)
Kojto	110:165afa46840b	2232
Kojto	122:f9eeca106725	2233	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	110:165afa46840b	2234
Kojto	110:165afa46840b	2235	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2236	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2237	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	2238	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2239	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	2240	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2241	} while(0U)
Kojto	110:165afa46840b	2242	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	2243
bogdanm	92:4fc01daae5a5	2244	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2245	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2246	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2247	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	2248	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2249	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	2250	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2251	} while(0U)
Kojto	99:dbbf35b96557	2252	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	92:4fc01daae5a5	2253	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	89:552587b429a1	2254
bogdanm	92:4fc01daae5a5	2255	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2256	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2257	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2258	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	2259	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2260	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	2261	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2262	} while(0U)
Kojto	99:dbbf35b96557	2263	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2264	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2265	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	2266	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2267	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	2268	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2269	} while(0U)
Kojto	99:dbbf35b96557	2270	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	99:dbbf35b96557	2271	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm	92:4fc01daae5a5	2272	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2273	/**
Kojto	110:165afa46840b	2274	* @}
Kojto	110:165afa46840b	2275	*/
Kojto	110:165afa46840b	2276
Kojto	122:f9eeca106725	2277
Kojto	122:f9eeca106725	2278	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2279	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	2280	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2281	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2282	* using it.
Kojto	122:f9eeca106725	2283	* @{
Kojto	122:f9eeca106725	2284	*/
Kojto	122:f9eeca106725	2285	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	2286	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	2287
Kojto	122:f9eeca106725	2288	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	122:f9eeca106725	2289	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	2290
Kojto	122:f9eeca106725	2291	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	122:f9eeca106725	2292	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto	122:f9eeca106725	2293	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto	122:f9eeca106725	2294	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	122:f9eeca106725	2295
Kojto	122:f9eeca106725	2296	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	122:f9eeca106725	2297	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
Kojto	122:f9eeca106725	2298	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
Kojto	122:f9eeca106725	2299
Kojto	122:f9eeca106725	2300	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
Kojto	122:f9eeca106725	2301	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
Kojto	122:f9eeca106725	2302	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	122:f9eeca106725	2303	/**
Kojto	122:f9eeca106725	2304	* @}
Kojto	122:f9eeca106725	2305	*/
Kojto	122:f9eeca106725	2306
Kojto	110:165afa46840b	2307	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2308	* @brief Enables or disables the AHB3 peripheral clock.
bogdanm	89:552587b429a1	2309	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	2310	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2311	* using it.
Kojto	122:f9eeca106725	2312	* @{
bogdanm	89:552587b429a1	2313	*/
Kojto	99:dbbf35b96557	2314	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2315	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2316	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	99:dbbf35b96557	2317	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2318	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	99:dbbf35b96557	2319	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2320	} while(0U)
Kojto	99:dbbf35b96557	2321	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto	110:165afa46840b	2322	/**
Kojto	110:165afa46840b	2323	* @}
Kojto	110:165afa46840b	2324	*/
Kojto	110:165afa46840b	2325
Kojto	122:f9eeca106725	2326	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2327	* @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	122:f9eeca106725	2328	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2329	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2330	* using it.
Kojto	122:f9eeca106725	2331	* @{
Kojto	122:f9eeca106725	2332	*/
Kojto	122:f9eeca106725	2333	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
Kojto	122:f9eeca106725	2334	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
Kojto	122:f9eeca106725	2335	/**
Kojto	122:f9eeca106725	2336	* @}
Kojto	122:f9eeca106725	2337	*/
Kojto	122:f9eeca106725	2338
Kojto	110:165afa46840b	2339	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2340	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	89:552587b429a1	2341	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	2342	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2343	* using it.
Kojto	122:f9eeca106725	2344	* @{
bogdanm	89:552587b429a1	2345	*/
Kojto	99:dbbf35b96557	2346	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2347	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	2349	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	2351	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2352	} while(0U)
Kojto	99:dbbf35b96557	2353	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2354	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	2356	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	2358	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2359	} while(0U)
Kojto	99:dbbf35b96557	2360	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2361	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	2363	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	2365	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2366	} while(0U)
Kojto	99:dbbf35b96557	2367	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2368	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	2370	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	2372	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2373	} while(0U)
Kojto	99:dbbf35b96557	2374	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2375	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2376	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	2377	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2378	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	2379	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2380	} while(0U)
Kojto	99:dbbf35b96557	2381	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2382	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2383	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	2384	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2385	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	2386	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2387	} while(0U)
Kojto	99:dbbf35b96557	2388	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2389	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2390	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	2391	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2392	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	2393	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2394	} while(0U)
Kojto	99:dbbf35b96557	2395	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2396	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2397	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	2398	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2399	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	2400	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2401	} while(0U)
Kojto	99:dbbf35b96557	2402	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2403	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2404	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	2405	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2406	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	2407	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2408	} while(0U)
Kojto	99:dbbf35b96557	2409	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2410	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2411	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	2412	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2413	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	2414	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2415	} while(0U)
Kojto	99:dbbf35b96557	2416	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2417	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2418	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	2419	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2420	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	2421	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2422	} while(0U)
Kojto	110:165afa46840b	2423	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2424	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2425	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2426	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2427	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2428	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2429	} while(0U)
Kojto	110:165afa46840b	2430	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2431	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2432	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2433	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2434	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2435	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2436	} while(0U)
Kojto	110:165afa46840b	2437	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2438	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2439	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2440	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2441	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2442	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2443	} while(0U)
Kojto	110:165afa46840b	2444	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2445	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2446	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2447	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2448	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2449	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2450	} while(0U)
Kojto	110:165afa46840b	2451	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2452	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2453	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2454	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2455	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2456	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2457	} while(0U)
Kojto	110:165afa46840b	2458	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	2459	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	2460	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	2461	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	2462	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	2463	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	2464	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	2465	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	2466	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	2467	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	2468	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	2469	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	2470	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	2471	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	2472	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	2473	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	2474	/**
Kojto	110:165afa46840b	2475	* @}
Kojto	110:165afa46840b	2476	*/
Kojto	122:f9eeca106725	2477
Kojto	122:f9eeca106725	2478	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2479	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	2480	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2481	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2482	* using it.
Kojto	122:f9eeca106725	2483	* @{
Kojto	122:f9eeca106725	2484	*/
Kojto	122:f9eeca106725	2485	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	2486	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	2487	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	2488	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	2489	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	2490	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	2491	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	122:f9eeca106725	2492	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	122:f9eeca106725	2493	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto	122:f9eeca106725	2494	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	122:f9eeca106725	2495	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	122:f9eeca106725	2496	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto	122:f9eeca106725	2497	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto	122:f9eeca106725	2498	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	122:f9eeca106725	2499	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto	122:f9eeca106725	2500	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	122:f9eeca106725	2501
Kojto	122:f9eeca106725	2502	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	2503	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	2504	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	2505	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	2506	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	2507	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	2508	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	122:f9eeca106725	2509	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	122:f9eeca106725	2510	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	122:f9eeca106725	2511	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	122:f9eeca106725	2512	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	122:f9eeca106725	2513	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto	122:f9eeca106725	2514	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto	122:f9eeca106725	2515	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	122:f9eeca106725	2516	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto	122:f9eeca106725	2517	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	122:f9eeca106725	2518	/**
Kojto	122:f9eeca106725	2519	* @}
Kojto	122:f9eeca106725	2520	*/
Kojto	122:f9eeca106725	2521
Kojto	110:165afa46840b	2522	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2523	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	89:552587b429a1	2524	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	2525	* is disabled and the application software has to enable this clock before
bogdanm	89:552587b429a1	2526	* using it.
Kojto	122:f9eeca106725	2527	* @{
Kojto	122:f9eeca106725	2528	*/
Kojto	99:dbbf35b96557	2529	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2530	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2531	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	2532	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2533	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	2534	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2535	} while(0U)
Kojto	99:dbbf35b96557	2536	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2537	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2538	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	2539	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2540	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	2541	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2542	} while(0U)
Kojto	99:dbbf35b96557	2543	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2544	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2545	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	2546	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2547	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	2548	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2549	} while(0U)
Kojto	110:165afa46840b	2550	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2551	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2552	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2553	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2554	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2555	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2556	} while(0U)
Kojto	110:165afa46840b	2557	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2558	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2559	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2560	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2561	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2562	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2563	} while(0U)
Kojto	110:165afa46840b	2564	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2565	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2566	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	2567	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2568	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	2569	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2570	} while(0U)
Kojto	110:165afa46840b	2571
Kojto	110:165afa46840b	2572	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	2573	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	2574	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	2575	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	2576	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	2577	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	2578	/**
Kojto	110:165afa46840b	2579	* @}
Kojto	110:165afa46840b	2580	*/
Kojto	110:165afa46840b	2581
Kojto	122:f9eeca106725	2582	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2583	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	2584	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2585	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2586	* using it.
Kojto	122:f9eeca106725	2587	* @{
Kojto	122:f9eeca106725	2588	*/
Kojto	122:f9eeca106725	2589	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	2590	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	2591	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto	122:f9eeca106725	2592	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto	122:f9eeca106725	2593	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto	122:f9eeca106725	2594	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto	122:f9eeca106725	2595
Kojto	122:f9eeca106725	2596	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	2597	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	2598	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	2599	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto	122:f9eeca106725	2600	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto	122:f9eeca106725	2601	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto	122:f9eeca106725	2602	/**
Kojto	122:f9eeca106725	2603	* @}
Kojto	122:f9eeca106725	2604	*/
Kojto	122:f9eeca106725	2605
Kojto	110:165afa46840b	2606	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	2607	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	2608	* @{
Kojto	110:165afa46840b	2609	*/
Kojto	110:165afa46840b	2610	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2611	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	2612	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	2613	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	2614	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	2615	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	2616	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	2617	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2618
Kojto	110:165afa46840b	2619	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2620	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	2621	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	2622	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	2623	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	2624	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	2625	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	2626	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2627	/**
Kojto	110:165afa46840b	2628	* @}
Kojto	110:165afa46840b	2629	*/
Kojto	110:165afa46840b	2630
Kojto	110:165afa46840b	2631	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	2632	* @brief Force or release AHB2 peripheral reset.
Kojto	122:f9eeca106725	2633	* @{
Kojto	122:f9eeca106725	2634	*/
Kojto	122:f9eeca106725	2635	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	2636	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	2637
bogdanm	92:4fc01daae5a5	2638	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2639	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	99:dbbf35b96557	2640	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	92:4fc01daae5a5	2641	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	89:552587b429a1	2642
bogdanm	92:4fc01daae5a5	2643	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2644	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	2645	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	89:552587b429a1	2646
Kojto	99:dbbf35b96557	2647	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	2648	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm	92:4fc01daae5a5	2649	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2650
Kojto	110:165afa46840b	2651	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2652	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2653
Kojto	110:165afa46840b	2654	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	110:165afa46840b	2655	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	110:165afa46840b	2656	/**
Kojto	110:165afa46840b	2657	* @}
Kojto	110:165afa46840b	2658	*/
Kojto	110:165afa46840b	2659
Kojto	110:165afa46840b	2660	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	2661	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	2662	* @{
Kojto	110:165afa46840b	2663	*/
Kojto	122:f9eeca106725	2664	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	2665	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	110:165afa46840b	2666
Kojto	99:dbbf35b96557	2667	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
Kojto	99:dbbf35b96557	2668	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto	110:165afa46840b	2669	/**
Kojto	110:165afa46840b	2670	* @}
Kojto	110:165afa46840b	2671	*/
Kojto	110:165afa46840b	2672
Kojto	110:165afa46840b	2673	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	2674	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	2675	* @{
Kojto	122:f9eeca106725	2676	*/
Kojto	99:dbbf35b96557	2677	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	2678	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	2679	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	2680	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	2681	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	2682	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	2683	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	2684	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	2685	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	2686	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	2687	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	2688	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	2689	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	2690	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	2691	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	2692	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	2693
Kojto	110:165afa46840b	2694	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	2695	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	2696	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	2697	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	2698	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	2699	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	2700	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	2701	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	2702	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	2703	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	2704	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	2705	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	2706	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	2707	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	2708	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	2709	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	2710	/**
Kojto	110:165afa46840b	2711	* @}
Kojto	110:165afa46840b	2712	*/
Kojto	110:165afa46840b	2713
Kojto	110:165afa46840b	2714	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	2715	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	2716	* @{
bogdanm	89:552587b429a1	2717	*/
Kojto	99:dbbf35b96557	2718	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	2719	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	2720	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	2721	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	2722
Kojto	110:165afa46840b	2723	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	2724	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	2725	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	99:dbbf35b96557	2726	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	2727	/**
Kojto	110:165afa46840b	2728	* @}
Kojto	110:165afa46840b	2729	*/
Kojto	110:165afa46840b	2730
Kojto	110:165afa46840b	2731	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2732	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	2733	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	2734	* power consumption.
bogdanm	89:552587b429a1	2735	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	2736	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	2737	* @{
Kojto	110:165afa46840b	2738	*/
Kojto	110:165afa46840b	2739	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	2740	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	2741	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	2742	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	2743	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	2744	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	2745	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	2746	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	2747	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	2748	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	2749	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	2750	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	2751	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2752	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2753	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2754	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	2755
Kojto	110:165afa46840b	2756	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	2757	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	2758	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	2759	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	2760	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	2761	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	2762	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	2763	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	2764	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	2765	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	2766	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	2767	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	2768	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2769	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2770	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2771	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	2772	/**
Kojto	110:165afa46840b	2773	* @}
Kojto	110:165afa46840b	2774	*/
Kojto	110:165afa46840b	2775
Kojto	110:165afa46840b	2776	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2777	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	2778	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	2779	* power consumption.
Kojto	110:165afa46840b	2780	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	2781	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2782	* @{
Kojto	110:165afa46840b	2783	*/
Kojto	110:165afa46840b	2784	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	2785	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	2786
Kojto	110:165afa46840b	2787	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	2788	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	2789
bogdanm	92:4fc01daae5a5	2790	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2791	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	2792	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	92:4fc01daae5a5	2793	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	89:552587b429a1	2794
bogdanm	92:4fc01daae5a5	2795	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2796	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	2797	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	89:552587b429a1	2798
Kojto	99:dbbf35b96557	2799	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	2800	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm	92:4fc01daae5a5	2801	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2802	/**
Kojto	110:165afa46840b	2803	* @}
Kojto	110:165afa46840b	2804	*/
Kojto	110:165afa46840b	2805
Kojto	110:165afa46840b	2806	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2807	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	2808	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	2809	* power consumption.
bogdanm	89:552587b429a1	2810	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	2811	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	2812	* @{
bogdanm	89:552587b429a1	2813	*/
Kojto	99:dbbf35b96557	2814	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
Kojto	99:dbbf35b96557	2815	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto	110:165afa46840b	2816	/**
Kojto	110:165afa46840b	2817	* @}
Kojto	110:165afa46840b	2818	*/
Kojto	110:165afa46840b	2819
Kojto	110:165afa46840b	2820	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2821	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	2822	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	2823	* power consumption.
bogdanm	89:552587b429a1	2824	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	2825	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	2826	* @{
bogdanm	89:552587b429a1	2827	*/
Kojto	99:dbbf35b96557	2828	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	2829	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	2830	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	2831	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	2832	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	2833	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	2834	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	2835	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	2836	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	2837	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	2838	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	2839	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	2840	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	2841	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	2842	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	2843	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	2844
Kojto	110:165afa46840b	2845	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	2846	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	2847	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	2848	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	2849	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	2850	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	2851	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	2852	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	2853	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	2854	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	2855	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	2856	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	2857	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	2858	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	2859	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	2860	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	2861	/**
Kojto	110:165afa46840b	2862	* @}
Kojto	110:165afa46840b	2863	*/
Kojto	110:165afa46840b	2864
Kojto	110:165afa46840b	2865	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2866	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	2867	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	2868	* power consumption.
Kojto	99:dbbf35b96557	2869	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	2870	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	2871	* @{
Kojto	122:f9eeca106725	2872	*/
Kojto	99:dbbf35b96557	2873	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	2874	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	2875	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	110:165afa46840b	2876	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	2877	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2878	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	2879
Kojto	110:165afa46840b	2880	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	2881	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2882	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	2883	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	2884	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	2885	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	110:165afa46840b	2886	/**
Kojto	110:165afa46840b	2887	* @}
Kojto	110:165afa46840b	2888	*/
Kojto	99:dbbf35b96557	2889	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2890	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	2891
Kojto	110:165afa46840b	2892	/------------------------- STM32F401xE/STM32F401xC --------------------------/
Kojto	110:165afa46840b	2893	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
Kojto	110:165afa46840b	2894	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2895	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	110:165afa46840b	2896	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2897	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2898	* using it.
Kojto	110:165afa46840b	2899	* @{
Kojto	110:165afa46840b	2900	*/
Kojto	122:f9eeca106725	2901	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2902	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2903	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2904	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2905	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2906	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2907	} while(0U)
Kojto	122:f9eeca106725	2908	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2909	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2910	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2911	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2912	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2913	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2914	} while(0U)
Kojto	122:f9eeca106725	2915	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2916	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2917	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2918	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2919	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2920	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2921	} while(0U)
Kojto	110:165afa46840b	2922	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2923	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2924	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2925	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2926	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2927	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	2928	} while(0U)
Kojto	110:165afa46840b	2929
Kojto	110:165afa46840b	2930	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	2931	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	110:165afa46840b	2932	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	2933	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	2934	/**
Kojto	110:165afa46840b	2935	* @}
Kojto	110:165afa46840b	2936	*/
Kojto	110:165afa46840b	2937
Kojto	122:f9eeca106725	2938	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2939	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	2940	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2941	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2942	* using it.
Kojto	122:f9eeca106725	2943	* @{
Kojto	122:f9eeca106725	2944	*/
Kojto	122:f9eeca106725	2945	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	2946	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	2947	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	2948	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
Kojto	122:f9eeca106725	2949
Kojto	122:f9eeca106725	2950	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	2951	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	2952	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	2953	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	2954	/**
Kojto	122:f9eeca106725	2955	* @}
Kojto	122:f9eeca106725	2956	*/
Kojto	122:f9eeca106725	2957
Kojto	110:165afa46840b	2958	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2959	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	110:165afa46840b	2960	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2961	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2962	* using it.
Kojto	110:165afa46840b	2963	* @{
Kojto	110:165afa46840b	2964	*/
Kojto	110:165afa46840b	2965	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	2966	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	145:64910690c574	2967	}while(0U)
Kojto	110:165afa46840b	2968
Kojto	122:f9eeca106725	2969	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	122:f9eeca106725	2970	/**
Kojto	122:f9eeca106725	2971	* @}
Kojto	122:f9eeca106725	2972	*/
Kojto	122:f9eeca106725	2973
Kojto	122:f9eeca106725	2974	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2975	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	2976	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2977	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2978	* using it.
Kojto	122:f9eeca106725	2979	* @{
Kojto	122:f9eeca106725	2980	*/
AnnaBridge	145:64910690c574	2981	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	145:64910690c574	2982	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	2983	/**
Kojto	122:f9eeca106725	2984	* @}
Kojto	122:f9eeca106725	2985	*/
Kojto	122:f9eeca106725	2986
Kojto	110:165afa46840b	2987	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2988	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	110:165afa46840b	2989	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2990	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2991	* using it.
Kojto	110:165afa46840b	2992	* @{
Kojto	110:165afa46840b	2993	*/
Kojto	110:165afa46840b	2994	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2995	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2996	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2997	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2998	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2999	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3000	} while(0U)
Kojto	110:165afa46840b	3001	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3002	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3003	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	3004	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3005	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	3006	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3007	} while(0U)
Kojto	110:165afa46840b	3008	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3009	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3010	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	3011	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3012	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	3013	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3014	} while(0U)
Kojto	110:165afa46840b	3015	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3016	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3017	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	3018	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3019	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	3020	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3021	} while(0U)
Kojto	110:165afa46840b	3022	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3023	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3024	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	3025	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3026	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	3027	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3028	} while(0U)
Kojto	110:165afa46840b	3029	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	3030	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	3031	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	3032	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	3033	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	110:165afa46840b	3034	/**
Kojto	110:165afa46840b	3035	* @}
Kojto	110:165afa46840b	3036	*/
Kojto	110:165afa46840b	3037
Kojto	122:f9eeca106725	3038	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3039	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	3040	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3041	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3042	* using it.
Kojto	122:f9eeca106725	3043	* @{
Kojto	122:f9eeca106725	3044	*/
Kojto	122:f9eeca106725	3045	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	3046	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	3047	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	3048	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	3049	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	3050
Kojto	122:f9eeca106725	3051	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	3052	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	3053	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	3054	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	3055	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	3056	/**
Kojto	122:f9eeca106725	3057	* @}
Kojto	122:f9eeca106725	3058	*/
Kojto	122:f9eeca106725	3059
Kojto	122:f9eeca106725	3060	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3061	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	110:165afa46840b	3062	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3063	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3064	* using it.
Kojto	110:165afa46840b	3065	* @{
Kojto	110:165afa46840b	3066	*/
Kojto	110:165afa46840b	3067	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3068	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3069	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	3070	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3071	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	3072	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3073	} while(0U)
Kojto	110:165afa46840b	3074	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3075	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3076	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	3077	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3078	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	3079	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3080	} while(0U)
Kojto	110:165afa46840b	3081	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3082	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3083	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3084	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3085	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3086	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3087	} while(0U)
Kojto	110:165afa46840b	3088
Kojto	110:165afa46840b	3089	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	3090	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	3091	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	3092	/**
Kojto	110:165afa46840b	3093	* @}
Kojto	110:165afa46840b	3094	*/
Kojto	122:f9eeca106725	3095
Kojto	122:f9eeca106725	3096	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3097	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	3098	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3099	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3100	* using it.
Kojto	122:f9eeca106725	3101	* @{
AnnaBridge	145:64910690c574	3102	*/
AnnaBridge	145:64910690c574	3103	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	145:64910690c574	3104	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	145:64910690c574	3105	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	145:64910690c574	3106
Kojto	122:f9eeca106725	3107	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	3108	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	3109	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	3110	/**
Kojto	122:f9eeca106725	3111	* @}
Kojto	122:f9eeca106725	3112	*/
Kojto	110:165afa46840b	3113	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	3114	* @brief Force or release AHB1 peripheral reset.
Kojto	110:165afa46840b	3115	* @{
Kojto	110:165afa46840b	3116	*/
Kojto	122:f9eeca106725	3117	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3118	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3119	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	3120	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3121
Kojto	122:f9eeca106725	3122	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
Kojto	110:165afa46840b	3123	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3124	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	3125	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3126	/**
Kojto	110:165afa46840b	3127	* @}
Kojto	110:165afa46840b	3128	*/
Kojto	110:165afa46840b	3129
Kojto	110:165afa46840b	3130	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	3131	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	3132	* @{
Kojto	110:165afa46840b	3133	*/
Kojto	122:f9eeca106725	3134	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3135	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3136
Kojto	122:f9eeca106725	3137	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	3138	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3139	/**
Kojto	110:165afa46840b	3140	* @}
Kojto	110:165afa46840b	3141	*/
Kojto	110:165afa46840b	3142
Kojto	110:165afa46840b	3143	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	3144	* @brief Force or release APB1 peripheral reset.
Kojto	110:165afa46840b	3145	* @{
Kojto	110:165afa46840b	3146	*/
Kojto	122:f9eeca106725	3147	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3148	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3149	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3150	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3151	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3152	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3153
Kojto	122:f9eeca106725	3154	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
Kojto	110:165afa46840b	3155	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3156	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3157	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3158	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3159	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3160	/**
Kojto	110:165afa46840b	3161	* @}
Kojto	110:165afa46840b	3162	*/
Kojto	110:165afa46840b	3163
Kojto	110:165afa46840b	3164	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	3165	* @brief Force or release APB2 peripheral reset.
Kojto	110:165afa46840b	3166	* @{
Kojto	110:165afa46840b	3167	*/
Kojto	122:f9eeca106725	3168	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3169	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3170	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3171	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3172
Kojto	122:f9eeca106725	3173	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
Kojto	110:165afa46840b	3174	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3175	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3176	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3177	/**
Kojto	110:165afa46840b	3178	* @}
Kojto	110:165afa46840b	3179	*/
Kojto	110:165afa46840b	3180
Kojto	110:165afa46840b	3181	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	3182	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	3183	* @{
Kojto	110:165afa46840b	3184	*/
Kojto	122:f9eeca106725	3185	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	3186	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	110:165afa46840b	3187	/**
Kojto	110:165afa46840b	3188	* @}
Kojto	110:165afa46840b	3189	*/
Kojto	110:165afa46840b	3190
Kojto	110:165afa46840b	3191	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3192	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3193	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3194	* power consumption.
Kojto	110:165afa46840b	3195	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3196	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3197	* @{
Kojto	110:165afa46840b	3198	*/
Kojto	110:165afa46840b	3199	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3200	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3201	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3202	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3203	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3204
Kojto	110:165afa46840b	3205	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3206	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3207	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3208	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3209	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3210	/**
Kojto	110:165afa46840b	3211	* @}
Kojto	110:165afa46840b	3212	*/
Kojto	110:165afa46840b	3213
Kojto	110:165afa46840b	3214	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3215	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3216	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3217	* power consumption.
Kojto	110:165afa46840b	3218	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3219	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3220	* @{
Kojto	110:165afa46840b	3221	*/
Kojto	110:165afa46840b	3222	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3223
Kojto	110:165afa46840b	3224	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3225	/**
Kojto	110:165afa46840b	3226	* @}
Kojto	110:165afa46840b	3227	*/
Kojto	110:165afa46840b	3228
Kojto	110:165afa46840b	3229	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3230	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3231	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3232	* power consumption.
Kojto	110:165afa46840b	3233	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3234	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3235	* @{
Kojto	110:165afa46840b	3236	*/
Kojto	110:165afa46840b	3237	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3238	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3239	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3240	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3241	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3242
Kojto	110:165afa46840b	3243	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3244	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3245	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3246	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3247	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3248	/**
Kojto	110:165afa46840b	3249	* @}
Kojto	110:165afa46840b	3250	*/
Kojto	110:165afa46840b	3251
Kojto	110:165afa46840b	3252	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3253	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3254	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3255	* power consumption.
Kojto	110:165afa46840b	3256	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3257	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3258	* @{
Kojto	110:165afa46840b	3259	*/
Kojto	110:165afa46840b	3260	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3261	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3262	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3263
Kojto	110:165afa46840b	3264	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3265	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3266	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3267	/**
Kojto	110:165afa46840b	3268	* @}
Kojto	110:165afa46840b	3269	*/
Kojto	110:165afa46840b	3270	#endif /* STM32F401xC \|\| STM32F401xE*/
Kojto	110:165afa46840b	3271	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3272
Kojto	110:165afa46840b	3273	/-------------------------------- STM32F410xx -------------------------------/
Kojto	110:165afa46840b	3274	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	3275	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3276	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	3277	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3278	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3279	* using it.
Kojto	122:f9eeca106725	3280	* @{
Kojto	110:165afa46840b	3281	*/
Kojto	110:165afa46840b	3282	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3283	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3284	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3285	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3286	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3287	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3288	} while(0U)
Kojto	110:165afa46840b	3289	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3290	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3291	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
Kojto	110:165afa46840b	3292	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3293	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
Kojto	110:165afa46840b	3294	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3295	} while(0U)
Kojto	110:165afa46840b	3296	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	3297	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
Kojto	110:165afa46840b	3298	/**
Kojto	110:165afa46840b	3299	* @}
Kojto	110:165afa46840b	3300	*/
Kojto	110:165afa46840b	3301
Kojto	122:f9eeca106725	3302	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3303	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	3304	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3305	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3306	* using it.
Kojto	122:f9eeca106725	3307	* @{
Kojto	122:f9eeca106725	3308	*/
AnnaBridge	145:64910690c574	3309	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	145:64910690c574	3310	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
AnnaBridge	145:64910690c574	3311
AnnaBridge	145:64910690c574	3312	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	145:64910690c574	3313	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	3314	/**
Kojto	122:f9eeca106725	3315	* @}
Kojto	122:f9eeca106725	3316	*/
Kojto	122:f9eeca106725	3317
Kojto	110:165afa46840b	3318	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3319	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
Kojto	122:f9eeca106725	3320	* @{
Kojto	110:165afa46840b	3321	*/
Kojto	110:165afa46840b	3322	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3323	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3324	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	110:165afa46840b	3325	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3326	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	110:165afa46840b	3327	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3328	} while(0U)
Kojto	110:165afa46840b	3329	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3330	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3331	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	110:165afa46840b	3332	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3333	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	110:165afa46840b	3334	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3335	} while(0U)
Kojto	110:165afa46840b	3336	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3337	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3338	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	110:165afa46840b	3339	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3340	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	110:165afa46840b	3341	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3342	} while(0U)
Kojto	110:165afa46840b	3343	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3344	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3345	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	110:165afa46840b	3346	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3347	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	110:165afa46840b	3348	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3349	} while(0U)
Kojto	110:165afa46840b	3350	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3351	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3352	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	110:165afa46840b	3353	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3354	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	110:165afa46840b	3355	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3356	} while(0U)
Kojto	110:165afa46840b	3357
Kojto	110:165afa46840b	3358	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	110:165afa46840b	3359	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
Kojto	110:165afa46840b	3360	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
Kojto	110:165afa46840b	3361	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	110:165afa46840b	3362	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	3363	/**
Kojto	110:165afa46840b	3364	* @}
Kojto	110:165afa46840b	3365	*/
Kojto	122:f9eeca106725	3366
Kojto	122:f9eeca106725	3367	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3368	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	3369	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3370	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3371	* using it.
Kojto	122:f9eeca106725	3372	* @{
Kojto	122:f9eeca106725	3373	*/
Kojto	122:f9eeca106725	3374	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	3375	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
Kojto	122:f9eeca106725	3376	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
Kojto	122:f9eeca106725	3377	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
Kojto	122:f9eeca106725	3378	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	122:f9eeca106725	3379
Kojto	122:f9eeca106725	3380	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	3381	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
Kojto	122:f9eeca106725	3382	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
Kojto	122:f9eeca106725	3383	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
Kojto	122:f9eeca106725	3384	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	122:f9eeca106725	3385	/**
Kojto	122:f9eeca106725	3386	* @}
Kojto	122:f9eeca106725	3387	*/
Kojto	122:f9eeca106725	3388
Kojto	110:165afa46840b	3389	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3390	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	122:f9eeca106725	3391	* @{
Kojto	122:f9eeca106725	3392	*/
Kojto	99:dbbf35b96557	3393	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3394	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3395	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	3396	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3397	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	3398	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3399	} while(0U)
Kojto	110:165afa46840b	3400	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3401	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3402	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	110:165afa46840b	3403	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3404	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	110:165afa46840b	3405	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3406	} while(0U)
Kojto	110:165afa46840b	3407	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	3408	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
Kojto	110:165afa46840b	3409	/**
Kojto	110:165afa46840b	3410	* @}
Kojto	110:165afa46840b	3411	*/
Kojto	122:f9eeca106725	3412
Kojto	122:f9eeca106725	3413	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3414	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	3415	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3416	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3417	* using it.
Kojto	122:f9eeca106725	3418	* @{
Kojto	122:f9eeca106725	3419	*/
Kojto	122:f9eeca106725	3420	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto	122:f9eeca106725	3421	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
Kojto	122:f9eeca106725	3422
Kojto	122:f9eeca106725	3423	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto	122:f9eeca106725	3424	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
Kojto	122:f9eeca106725	3425	/**
Kojto	122:f9eeca106725	3426	* @}
Kojto	122:f9eeca106725	3427	*/
Kojto	122:f9eeca106725	3428
Kojto	110:165afa46840b	3429	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	3430	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	3431	* @{
Kojto	122:f9eeca106725	3432	*/
Kojto	110:165afa46840b	3433	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3434	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
Kojto	110:165afa46840b	3435	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3436	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
Kojto	110:165afa46840b	3437	/**
Kojto	110:165afa46840b	3438	* @}
Kojto	110:165afa46840b	3439	*/
Kojto	110:165afa46840b	3440
Kojto	110:165afa46840b	3441	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	3442	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	3443	* @{
Kojto	110:165afa46840b	3444	*/
Kojto	110:165afa46840b	3445	#define __HAL_RCC_AHB2_FORCE_RESET()
Kojto	110:165afa46840b	3446	#define __HAL_RCC_AHB2_RELEASE_RESET()
Kojto	110:165afa46840b	3447	/**
Kojto	110:165afa46840b	3448	* @}
Kojto	110:165afa46840b	3449	*/
Kojto	110:165afa46840b	3450
Kojto	110:165afa46840b	3451	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	3452	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	3453	* @{
Kojto	99:dbbf35b96557	3454	*/
Kojto	110:165afa46840b	3455	#define __HAL_RCC_AHB3_FORCE_RESET()
Kojto	110:165afa46840b	3456	#define __HAL_RCC_AHB3_RELEASE_RESET()
Kojto	110:165afa46840b	3457	/**
Kojto	110:165afa46840b	3458	* @}
Kojto	110:165afa46840b	3459	*/
Kojto	110:165afa46840b	3460
Kojto	110:165afa46840b	3461	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	3462	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	3463	* @{
Kojto	110:165afa46840b	3464	*/
Kojto	110:165afa46840b	3465	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	110:165afa46840b	3466	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
Kojto	110:165afa46840b	3467	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	110:165afa46840b	3468	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	3469
Kojto	110:165afa46840b	3470	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	110:165afa46840b	3471	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
Kojto	110:165afa46840b	3472	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	110:165afa46840b	3473	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	3474	/**
Kojto	110:165afa46840b	3475	* @}
Kojto	110:165afa46840b	3476	*/
Kojto	110:165afa46840b	3477
Kojto	110:165afa46840b	3478	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	3479	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	3480	* @{
Kojto	110:165afa46840b	3481	*/
Kojto	110:165afa46840b	3482	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3483	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3484	/**
Kojto	110:165afa46840b	3485	* @}
Kojto	110:165afa46840b	3486	*/
Kojto	110:165afa46840b	3487
Kojto	110:165afa46840b	3488	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3489	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3490	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3491	* power consumption.
Kojto	110:165afa46840b	3492	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3493	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	3494	* @{
Kojto	110:165afa46840b	3495	*/
Kojto	110:165afa46840b	3496	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
Kojto	110:165afa46840b	3497	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3498	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3499	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3500
Kojto	110:165afa46840b	3501	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
Kojto	110:165afa46840b	3502	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3503	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3504	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3505	/**
Kojto	110:165afa46840b	3506	* @}
Kojto	110:165afa46840b	3507	*/
Kojto	110:165afa46840b	3508
Kojto	110:165afa46840b	3509	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3510	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	3511	* @{
Kojto	122:f9eeca106725	3512	*/
Kojto	110:165afa46840b	3513	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	110:165afa46840b	3514	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
Kojto	110:165afa46840b	3515	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
Kojto	110:165afa46840b	3516	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	110:165afa46840b	3517	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	3518
Kojto	110:165afa46840b	3519	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	110:165afa46840b	3520	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
Kojto	110:165afa46840b	3521	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
Kojto	110:165afa46840b	3522	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	110:165afa46840b	3523	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	3524	/**
Kojto	110:165afa46840b	3525	* @}
Kojto	110:165afa46840b	3526	*/
Kojto	110:165afa46840b	3527
Kojto	110:165afa46840b	3528	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3529	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	3530	* @{
Kojto	122:f9eeca106725	3531	*/
Kojto	110:165afa46840b	3532	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3533	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
Kojto	110:165afa46840b	3534	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3535	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
Kojto	110:165afa46840b	3536	/**
Kojto	110:165afa46840b	3537	* @}
Kojto	110:165afa46840b	3538	*/
Kojto	110:165afa46840b	3539
Kojto	110:165afa46840b	3540	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	3541	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3542
Kojto	110:165afa46840b	3543	/-------------------------------- STM32F411xx -------------------------------/
Kojto	110:165afa46840b	3544	#if defined(STM32F411xE)
Kojto	110:165afa46840b	3545	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3546	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	3547	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3548	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3549	* using it.
Kojto	122:f9eeca106725	3550	* @{
Kojto	110:165afa46840b	3551	*/
Kojto	110:165afa46840b	3552	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3553	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3554	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3555	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3556	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3557	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3558	} while(0U)
Kojto	122:f9eeca106725	3559	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3560	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3561	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3562	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3563	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3564	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3565	} while(0U)
Kojto	122:f9eeca106725	3566	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3567	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3568	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3569	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3570	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3571	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3572	} while(0U)
Kojto	110:165afa46840b	3573	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3574	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3575	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3576	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3577	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3578	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3579	} while(0U)
Kojto	110:165afa46840b	3580	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	3581	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	110:165afa46840b	3582	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	3583	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	3584	/**
Kojto	110:165afa46840b	3585	* @}
Kojto	110:165afa46840b	3586	*/
Kojto	110:165afa46840b	3587
Kojto	122:f9eeca106725	3588	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3589	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	3590	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3591	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3592	* using it.
Kojto	122:f9eeca106725	3593	* @{
Kojto	122:f9eeca106725	3594	*/
Kojto	122:f9eeca106725	3595	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	3596	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	3597	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
Kojto	122:f9eeca106725	3598	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	3599
Kojto	122:f9eeca106725	3600	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	3601	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	3602	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	3603	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	3604	/**
Kojto	122:f9eeca106725	3605	* @}
Kojto	122:f9eeca106725	3606	*/
Kojto	122:f9eeca106725	3607
Kojto	110:165afa46840b	3608	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3609	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	99:dbbf35b96557	3610	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	3611	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	3612	* using it.
Kojto	110:165afa46840b	3613	* @{
Kojto	110:165afa46840b	3614	*/
Kojto	110:165afa46840b	3615	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	3616	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	145:64910690c574	3617	}while(0U)
Kojto	122:f9eeca106725	3618
Kojto	122:f9eeca106725	3619	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	122:f9eeca106725	3620	/**
Kojto	122:f9eeca106725	3621	* @}
Kojto	122:f9eeca106725	3622	*/
Kojto	122:f9eeca106725	3623
Kojto	122:f9eeca106725	3624	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3625	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	3626	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3627	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3628	* using it.
Kojto	122:f9eeca106725	3629	* @{
Kojto	122:f9eeca106725	3630	*/
Kojto	122:f9eeca106725	3631	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	3632	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	3633	/**
Kojto	122:f9eeca106725	3634	* @}
Kojto	122:f9eeca106725	3635	*/
Kojto	110:165afa46840b	3636
Kojto	110:165afa46840b	3637	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3638	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	110:165afa46840b	3639	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3640	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3641	* using it.
Kojto	122:f9eeca106725	3642	* @{
Kojto	110:165afa46840b	3643	*/
Kojto	110:165afa46840b	3644	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3645	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3646	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	3647	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3648	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	3649	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3650	} while(0U)
Kojto	110:165afa46840b	3651	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3652	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3653	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	3654	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3655	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	3656	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3657	} while(0U)
Kojto	110:165afa46840b	3658	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3659	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3660	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	3661	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3662	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	3663	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3664	} while(0U)
Kojto	110:165afa46840b	3665	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3666	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3667	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	3668	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3669	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	3670	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3671	} while(0U)
Kojto	110:165afa46840b	3672	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3673	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	3675	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	3677	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3678	} while(0U)
Kojto	110:165afa46840b	3679	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	3680	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	3681	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	3682	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	3683	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	110:165afa46840b	3684	/**
Kojto	110:165afa46840b	3685	* @}
Kojto	110:165afa46840b	3686	*/
Kojto	122:f9eeca106725	3687
Kojto	122:f9eeca106725	3688	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3689	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	3690	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3691	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3692	* using it.
Kojto	122:f9eeca106725	3693	* @{
Kojto	122:f9eeca106725	3694	*/
Kojto	122:f9eeca106725	3695	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	3696	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	3697	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	3698	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	3699	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	3700
Kojto	122:f9eeca106725	3701	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	3702	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	3703	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	3704	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	3705	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	3706	/**
Kojto	122:f9eeca106725	3707	* @}
Kojto	122:f9eeca106725	3708	*/
Kojto	122:f9eeca106725	3709
Kojto	110:165afa46840b	3710	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3711	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	122:f9eeca106725	3712	* @{
Kojto	110:165afa46840b	3713	*/
Kojto	110:165afa46840b	3714	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3715	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3716	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	110:165afa46840b	3717	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3718	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	110:165afa46840b	3719	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3720	} while(0U)
Kojto	110:165afa46840b	3721	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3722	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3723	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	3724	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3725	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	3726	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3727	} while(0U)
Kojto	110:165afa46840b	3728	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3729	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3730	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	3731	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3732	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	3733	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3734	} while(0U)
Kojto	110:165afa46840b	3735	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3736	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3737	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3738	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3739	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3740	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3741	} while(0U)
Kojto	110:165afa46840b	3742	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	3743	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	3744	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	3745	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	3746	/**
Kojto	110:165afa46840b	3747	* @}
Kojto	110:165afa46840b	3748	*/
Kojto	122:f9eeca106725	3749
Kojto	122:f9eeca106725	3750	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3751	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	3752	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3753	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3754	* using it.
Kojto	122:f9eeca106725	3755	* @{
Kojto	122:f9eeca106725	3756	*/
Kojto	122:f9eeca106725	3757	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	3758	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	3759	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto	122:f9eeca106725	3760	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto	122:f9eeca106725	3761
Kojto	122:f9eeca106725	3762	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	3763	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	3764	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	3765	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto	122:f9eeca106725	3766	/**
Kojto	122:f9eeca106725	3767	* @}
Kojto	122:f9eeca106725	3768	*/
Kojto	122:f9eeca106725	3769
Kojto	110:165afa46840b	3770	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	3771	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	3772	* @{
Kojto	122:f9eeca106725	3773	*/
Kojto	110:165afa46840b	3774	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3775	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	3776	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3777
Kojto	110:165afa46840b	3778	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3779	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	3780	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3781	/**
Kojto	110:165afa46840b	3782	* @}
Kojto	110:165afa46840b	3783	*/
Kojto	110:165afa46840b	3784
Kojto	110:165afa46840b	3785	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	3786	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	3787	* @{
Kojto	110:165afa46840b	3788	*/
Kojto	122:f9eeca106725	3789	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3790	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3791
Kojto	122:f9eeca106725	3792	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	3793	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3794	/**
Kojto	110:165afa46840b	3795	* @}
Kojto	110:165afa46840b	3796	*/
Kojto	110:165afa46840b	3797
Kojto	110:165afa46840b	3798	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	3799	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	3800	* @{
Kojto	110:165afa46840b	3801	*/
Kojto	122:f9eeca106725	3802	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	3803	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	110:165afa46840b	3804	/**
Kojto	110:165afa46840b	3805	* @}
Kojto	110:165afa46840b	3806	*/
Kojto	110:165afa46840b	3807
Kojto	110:165afa46840b	3808	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	3809	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	3810	* @{
Kojto	110:165afa46840b	3811	*/
Kojto	110:165afa46840b	3812	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3813	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3814	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3815	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3816	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3817
Kojto	110:165afa46840b	3818	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3819	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3820	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3821	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3822	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3823	/**
Kojto	110:165afa46840b	3824	* @}
Kojto	110:165afa46840b	3825	*/
Kojto	110:165afa46840b	3826
Kojto	110:165afa46840b	3827	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	3828	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	3829	* @{
Kojto	110:165afa46840b	3830	*/
Kojto	110:165afa46840b	3831	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3832	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3833	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3834	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3835
Kojto	110:165afa46840b	3836	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3837	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3838	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3839	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3840	/**
Kojto	110:165afa46840b	3841	* @}
Kojto	110:165afa46840b	3842	*/
Kojto	110:165afa46840b	3843
Kojto	110:165afa46840b	3844	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3845	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3846	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3847	* power consumption.
Kojto	110:165afa46840b	3848	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3849	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	3850	* @{
Kojto	110:165afa46840b	3851	*/
Kojto	110:165afa46840b	3852	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3853	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3854	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3855	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3856	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3857
Kojto	110:165afa46840b	3858	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3859	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3860	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3861	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3862	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3863	/**
Kojto	110:165afa46840b	3864	* @}
Kojto	110:165afa46840b	3865	*/
Kojto	110:165afa46840b	3866
Kojto	110:165afa46840b	3867	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3868	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3869	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3870	* power consumption.
Kojto	110:165afa46840b	3871	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3872	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3873	* @{
Kojto	110:165afa46840b	3874	*/
Kojto	110:165afa46840b	3875	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3876	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3877	/**
Kojto	110:165afa46840b	3878	* @}
Kojto	110:165afa46840b	3879	*/
Kojto	110:165afa46840b	3880
Kojto	110:165afa46840b	3881	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3882	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	3883	* @{
Kojto	122:f9eeca106725	3884	*/
Kojto	110:165afa46840b	3885	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3886	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3887	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3888	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3889	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3890
Kojto	110:165afa46840b	3891	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3892	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3893	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3894	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3895	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3896	/**
Kojto	110:165afa46840b	3897	* @}
Kojto	110:165afa46840b	3898	*/
Kojto	110:165afa46840b	3899
Kojto	110:165afa46840b	3900	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3901	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	3902	* @{
Kojto	122:f9eeca106725	3903	*/
Kojto	110:165afa46840b	3904	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3905	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3906	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3907	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3908
Kojto	110:165afa46840b	3909	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3910	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3911	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3912	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3913	/**
Kojto	110:165afa46840b	3914	* @}
Kojto	110:165afa46840b	3915	*/
Kojto	110:165afa46840b	3916	#endif /* STM32F411xE */
Kojto	110:165afa46840b	3917	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3918
Kojto	110:165afa46840b	3919	/---------------------------------- STM32F446xx -----------------------------/
Kojto	110:165afa46840b	3920	#if defined(STM32F446xx)
Kojto	110:165afa46840b	3921	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3922	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	3923	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3924	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3925	* using it.
Kojto	122:f9eeca106725	3926	* @{
Kojto	110:165afa46840b	3927	*/
Kojto	110:165afa46840b	3928	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3929	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3930	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	3931	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3932	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	3933	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3934	} while(0U)
Kojto	110:165afa46840b	3935	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3936	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3937	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3938	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3939	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3940	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3941	} while(0U)
Kojto	110:165afa46840b	3942	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3943	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3944	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3945	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3946	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3947	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3948	} while(0U)
Kojto	122:f9eeca106725	3949	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3950	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3951	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3952	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3953	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3954	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3955	} while(0U)
Kojto	122:f9eeca106725	3956	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3957	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3958	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3959	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3960	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3961	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3962	} while(0U)
Kojto	99:dbbf35b96557	3963	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3964	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3965	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	3966	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3967	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	3968	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3969	} while(0U)
Kojto	99:dbbf35b96557	3970	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3971	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3972	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	3973	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3974	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	3975	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3976	} while(0U)
Kojto	99:dbbf35b96557	3977	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3978	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3979	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	3980	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3981	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	3982	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3983	} while(0U)
Kojto	99:dbbf35b96557	3984	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3985	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3986	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	3987	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3988	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	3989	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	3990	} while(0U)
Kojto	110:165afa46840b	3991	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	3992	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	3993	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	3994	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	3995	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	3996	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	3997	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	3998	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	3999	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	4000	/**
Kojto	110:165afa46840b	4001	* @}
Kojto	110:165afa46840b	4002	*/
Kojto	110:165afa46840b	4003
Kojto	122:f9eeca106725	4004	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4005	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	4006	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4007	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4008	* using it.
Kojto	122:f9eeca106725	4009	* @{
Kojto	122:f9eeca106725	4010	*/
Kojto	122:f9eeca106725	4011	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	4012	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	4013	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	4014	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	122:f9eeca106725	4015	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto	122:f9eeca106725	4016	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto	122:f9eeca106725	4017	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	122:f9eeca106725	4018	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
Kojto	122:f9eeca106725	4019	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	4020
Kojto	122:f9eeca106725	4021	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	4022	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	4023	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	4024	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	122:f9eeca106725	4025	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto	122:f9eeca106725	4026	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
Kojto	122:f9eeca106725	4027	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	122:f9eeca106725	4028	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	4029	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	4030	/**
Kojto	122:f9eeca106725	4031	* @}
Kojto	122:f9eeca106725	4032	*/
Kojto	122:f9eeca106725	4033
Kojto	110:165afa46840b	4034	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	4035	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	99:dbbf35b96557	4036	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	4037	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	4038	* using it.
Kojto	122:f9eeca106725	4039	* @{
Kojto	99:dbbf35b96557	4040	*/
Kojto	99:dbbf35b96557	4041	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4042	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4043	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	4044	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4045	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	4046	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4047	} while(0U)
Kojto	99:dbbf35b96557	4048	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	110:165afa46840b	4049	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	4050	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	145:64910690c574	4051	}while(0U)
Kojto	110:165afa46840b	4052
Kojto	122:f9eeca106725	4053	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	110:165afa46840b	4054
Kojto	110:165afa46840b	4055	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4056	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4057	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	4058	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4059	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	4060	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4061	} while(0U)
Kojto	110:165afa46840b	4062	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	4063	/**
Kojto	110:165afa46840b	4064	* @}
Kojto	110:165afa46840b	4065	*/
Kojto	122:f9eeca106725	4066
Kojto	122:f9eeca106725	4067	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4068	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	4069	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4070	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4071	* using it.
Kojto	122:f9eeca106725	4072	* @{
Kojto	122:f9eeca106725	4073	*/
Kojto	122:f9eeca106725	4074	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto	122:f9eeca106725	4075	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto	122:f9eeca106725	4076
Kojto	122:f9eeca106725	4077	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	4078	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	4079
Kojto	122:f9eeca106725	4080	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	122:f9eeca106725	4081	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	4082	/**
Kojto	122:f9eeca106725	4083	* @}
Kojto	122:f9eeca106725	4084	*/
Kojto	122:f9eeca106725	4085
Kojto	110:165afa46840b	4086	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	4087	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	99:dbbf35b96557	4088	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	4089	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	4090	* using it.
Kojto	122:f9eeca106725	4091	* @{
Kojto	99:dbbf35b96557	4092	*/
Kojto	99:dbbf35b96557	4093	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4094	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4095	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	4096	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4097	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	4098	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4099	} while(0U)
Kojto	99:dbbf35b96557	4100	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4101	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4102	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	99:dbbf35b96557	4103	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4104	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	99:dbbf35b96557	4105	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4106	} while(0U)
Kojto	99:dbbf35b96557	4107
Kojto	99:dbbf35b96557	4108	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	99:dbbf35b96557	4109	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	110:165afa46840b	4110	/**
Kojto	110:165afa46840b	4111	* @}
Kojto	110:165afa46840b	4112	*/
Kojto	110:165afa46840b	4113
Kojto	122:f9eeca106725	4114	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4115	* @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	122:f9eeca106725	4116	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4117	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4118	* using it.
Kojto	122:f9eeca106725	4119	* @{
Kojto	122:f9eeca106725	4120	*/
Kojto	122:f9eeca106725	4121	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Kojto	122:f9eeca106725	4122	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto	122:f9eeca106725	4123
Kojto	122:f9eeca106725	4124	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Kojto	122:f9eeca106725	4125	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto	122:f9eeca106725	4126	/**
Kojto	122:f9eeca106725	4127	* @}
Kojto	122:f9eeca106725	4128	*/
Kojto	122:f9eeca106725	4129
Kojto	110:165afa46840b	4130	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	4131	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	99:dbbf35b96557	4132	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	4133	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	4134	* using it.
Kojto	122:f9eeca106725	4135	* @{
Kojto	99:dbbf35b96557	4136	*/
Kojto	99:dbbf35b96557	4137	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4138	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4139	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	4140	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4141	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	4142	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4143	} while(0U)
Kojto	99:dbbf35b96557	4144	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4145	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4146	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	4147	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4148	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	4149	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4150	} while(0U)
Kojto	99:dbbf35b96557	4151	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4152	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4153	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	4154	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4155	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	4156	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4157	} while(0U)
Kojto	99:dbbf35b96557	4158	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4159	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4160	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	4161	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4162	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	4163	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4164	} while(0U)
Kojto	99:dbbf35b96557	4165	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4166	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4167	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	4168	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4169	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	4170	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4171	} while(0U)
Kojto	99:dbbf35b96557	4172	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4173	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4174	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	99:dbbf35b96557	4175	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4176	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	99:dbbf35b96557	4177	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4178	} while(0U)
Kojto	99:dbbf35b96557	4179	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4180	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4181	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	4182	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4183	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	4184	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4185	} while(0U)
Kojto	99:dbbf35b96557	4186	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4187	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4188	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	4189	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4190	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	4191	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4192	} while(0U)
Kojto	99:dbbf35b96557	4193	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4194	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4195	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	4196	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4197	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	4198	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4199	} while(0U)
Kojto	99:dbbf35b96557	4200	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4201	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4202	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	99:dbbf35b96557	4203	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4204	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	99:dbbf35b96557	4205	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4206	} while(0U)
Kojto	99:dbbf35b96557	4207	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4208	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4209	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	4210	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4211	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	4212	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4213	} while(0U)
Kojto	99:dbbf35b96557	4214	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4215	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4216	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	4217	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4218	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	4219	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4220	} while(0U)
Kojto	99:dbbf35b96557	4221	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4222	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4223	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	99:dbbf35b96557	4224	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4225	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	99:dbbf35b96557	4226	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4227	} while(0U)
Kojto	99:dbbf35b96557	4228	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4229	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4230	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	4231	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4232	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	4233	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4234	} while(0U)
Kojto	110:165afa46840b	4235	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4236	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4237	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	4238	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4239	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	4240	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4241	} while(0U)
Kojto	110:165afa46840b	4242	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4243	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4244	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	4245	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4246	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	4247	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4248	} while(0U)
Kojto	110:165afa46840b	4249	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4250	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4251	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	4252	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4253	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	4254	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4255	} while(0U)
Kojto	110:165afa46840b	4256	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4257	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4258	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	4259	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4260	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	4261	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4262	} while(0U)
Kojto	110:165afa46840b	4263	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4264	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	4266	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	4268	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4269	} while(0U)
Kojto	110:165afa46840b	4270	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	4271	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	4272	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	4273	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	4274	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	4275	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	4276	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	4277	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	4278	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	4279	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	4280	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto	99:dbbf35b96557	4281	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	4282	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	4283	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	4284	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	99:dbbf35b96557	4285	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	4286	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	4287	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	99:dbbf35b96557	4288	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	4289	/**
Kojto	110:165afa46840b	4290	* @}
Kojto	110:165afa46840b	4291	*/
Kojto	110:165afa46840b	4292
Kojto	122:f9eeca106725	4293	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4294	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	4295	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4296	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4297	* using it.
Kojto	122:f9eeca106725	4298	* @{
Kojto	122:f9eeca106725	4299	*/
Kojto	122:f9eeca106725	4300	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	4301	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	4302	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	4303	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	4304	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	4305	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	4306	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	122:f9eeca106725	4307	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	122:f9eeca106725	4308	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto	122:f9eeca106725	4309	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	122:f9eeca106725	4310	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
Kojto	122:f9eeca106725	4311	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	122:f9eeca106725	4312	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto	122:f9eeca106725	4313	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto	122:f9eeca106725	4314	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
Kojto	122:f9eeca106725	4315	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	122:f9eeca106725	4316	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto	122:f9eeca106725	4317	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto	122:f9eeca106725	4318	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	122:f9eeca106725	4319
Kojto	122:f9eeca106725	4320	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	4321	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	4322	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	4323	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	4324	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	4325	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	4326	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	122:f9eeca106725	4327	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	122:f9eeca106725	4328	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	122:f9eeca106725	4329	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	122:f9eeca106725	4330	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
Kojto	122:f9eeca106725	4331	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	122:f9eeca106725	4332	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto	122:f9eeca106725	4333	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto	122:f9eeca106725	4334	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
Kojto	122:f9eeca106725	4335	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	122:f9eeca106725	4336	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto	122:f9eeca106725	4337	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto	122:f9eeca106725	4338	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	122:f9eeca106725	4339	/**
Kojto	122:f9eeca106725	4340	* @}
Kojto	122:f9eeca106725	4341	*/
Kojto	122:f9eeca106725	4342
Kojto	110:165afa46840b	4343	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	4344	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	99:dbbf35b96557	4345	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	4346	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	4347	* using it.
Kojto	122:f9eeca106725	4348	* @{
Kojto	99:dbbf35b96557	4349	*/
Kojto	99:dbbf35b96557	4350	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4351	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4352	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	4353	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4354	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	4355	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4356	} while(0U)
Kojto	99:dbbf35b96557	4357	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4358	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4359	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	4360	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4361	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	4362	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4363	} while(0U)
Kojto	99:dbbf35b96557	4364	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4365	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4366	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	4367	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4368	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	4369	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4370	} while(0U)
Kojto	99:dbbf35b96557	4371	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4372	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4373	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	4374	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4375	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	4376	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4377	} while(0U)
Kojto	99:dbbf35b96557	4378	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4379	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4380	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	99:dbbf35b96557	4381	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4382	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	99:dbbf35b96557	4383	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4384	} while(0U)
Kojto	110:165afa46840b	4385	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4386	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4387	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	4388	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4389	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	4390	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4391	} while(0U)
Kojto	110:165afa46840b	4392	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4393	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4394	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	4395	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4396	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	4397	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4398	} while(0U)
Kojto	110:165afa46840b	4399	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4400	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4401	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	4402	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4403	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	4404	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4405	} while(0U)
Kojto	110:165afa46840b	4406	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	4407	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	4408	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	4409	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	4410	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	4411	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	4412	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	110:165afa46840b	4413	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto	110:165afa46840b	4414	/**
Kojto	110:165afa46840b	4415	* @}
Kojto	110:165afa46840b	4416	*/
Kojto	110:165afa46840b	4417
Kojto	122:f9eeca106725	4418	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4419	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	4420	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4421	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4422	* using it.
Kojto	122:f9eeca106725	4423	* @{
Kojto	122:f9eeca106725	4424	*/
Kojto	122:f9eeca106725	4425	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	4426	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	4427	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto	122:f9eeca106725	4428	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto	122:f9eeca106725	4429	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto	122:f9eeca106725	4430	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto	122:f9eeca106725	4431	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
Kojto	122:f9eeca106725	4432	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
Kojto	122:f9eeca106725	4433
Kojto	122:f9eeca106725	4434	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	4435	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	4436	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	4437	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto	122:f9eeca106725	4438	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto	122:f9eeca106725	4439	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto	122:f9eeca106725	4440	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
Kojto	122:f9eeca106725	4441	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
Kojto	122:f9eeca106725	4442	/**
Kojto	122:f9eeca106725	4443	* @}
Kojto	122:f9eeca106725	4444	*/
Kojto	122:f9eeca106725	4445
Kojto	110:165afa46840b	4446	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	4447	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	4448	* @{
Kojto	110:165afa46840b	4449	*/
Kojto	110:165afa46840b	4450	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	4451	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	4452	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	4453	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	4454	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	4455	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	4456
Kojto	110:165afa46840b	4457	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	4458	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	4459	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	4460	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	4461	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	4462	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	4463	/**
Kojto	110:165afa46840b	4464	* @}
Kojto	110:165afa46840b	4465	*/
Kojto	110:165afa46840b	4466
Kojto	110:165afa46840b	4467	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	4468	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	4469	* @{
Kojto	110:165afa46840b	4470	*/
Kojto	122:f9eeca106725	4471	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	4472	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	4473	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	4474	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	4475
Kojto	122:f9eeca106725	4476	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	4477	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	4478	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	4479	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	4480	/**
Kojto	110:165afa46840b	4481	* @}
Kojto	110:165afa46840b	4482	*/
Kojto	110:165afa46840b	4483
Kojto	110:165afa46840b	4484	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	4485	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	4486	* @{
Kojto	99:dbbf35b96557	4487	*/
Kojto	122:f9eeca106725	4488	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	4489	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	110:165afa46840b	4490
Kojto	99:dbbf35b96557	4491	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	4492	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	99:dbbf35b96557	4493
Kojto	99:dbbf35b96557	4494	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	4495	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	4496	/**
Kojto	110:165afa46840b	4497	* @}
Kojto	110:165afa46840b	4498	*/
Kojto	110:165afa46840b	4499
Kojto	110:165afa46840b	4500	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	4501	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	4502	* @{
Kojto	122:f9eeca106725	4503	*/
Kojto	99:dbbf35b96557	4504	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	4505	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	4506	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	4507	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	4508	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	110:165afa46840b	4509	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
Kojto	99:dbbf35b96557	4510	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	4511	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	4512	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	4513	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	99:dbbf35b96557	4514	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	4515	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	4516	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	99:dbbf35b96557	4517	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	4518	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	4519	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	4520	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	4521	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	4522	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	4523
Kojto	110:165afa46840b	4524	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	4525	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	4526	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	4527	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	4528	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	4529	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	4530	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	4531	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	4532	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	4533	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	4534	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto	99:dbbf35b96557	4535	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	4536	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	4537	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	4538	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	99:dbbf35b96557	4539	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	4540	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	4541	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	99:dbbf35b96557	4542	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	4543	/**
Kojto	110:165afa46840b	4544	* @}
Kojto	110:165afa46840b	4545	*/
Kojto	110:165afa46840b	4546
Kojto	110:165afa46840b	4547	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	4548	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	4549	* @{
Kojto	110:165afa46840b	4550	*/
Kojto	110:165afa46840b	4551	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	4552	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	4553	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
Kojto	110:165afa46840b	4554	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	4555	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	4556	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	4557
Kojto	110:165afa46840b	4558	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	4559	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	4560	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	4561	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	4562	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	4563	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto	110:165afa46840b	4564	/**
Kojto	110:165afa46840b	4565	* @}
Kojto	110:165afa46840b	4566	*/
Kojto	110:165afa46840b	4567
Kojto	110:165afa46840b	4568	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4569	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	4570	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	4571	* power consumption.
Kojto	99:dbbf35b96557	4572	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	4573	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	4574	* @{
Kojto	110:165afa46840b	4575	*/
Kojto	110:165afa46840b	4576	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	4577	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	4578	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	4579	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	4580	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	4581	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	4582	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	4583	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	4584	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	4585	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	4586	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	4587
Kojto	110:165afa46840b	4588	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	4589	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	4590	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	4591	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	4592	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	4593	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	4594	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	4595	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	4596	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	4597	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	4598	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	4599	/**
Kojto	110:165afa46840b	4600	* @}
Kojto	110:165afa46840b	4601	*/
Kojto	110:165afa46840b	4602
Kojto	110:165afa46840b	4603	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4604	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	4605	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	4606	* power consumption.
Kojto	110:165afa46840b	4607	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	4608	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	4609	* @{
Kojto	110:165afa46840b	4610	*/
Kojto	110:165afa46840b	4611	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	4612	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	4613
Kojto	110:165afa46840b	4614	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	4615	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	4616
Kojto	99:dbbf35b96557	4617	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	4618	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	110:165afa46840b	4619	/**
Kojto	110:165afa46840b	4620	* @}
Kojto	110:165afa46840b	4621	*/
Kojto	110:165afa46840b	4622
Kojto	110:165afa46840b	4623	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4624	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	4625	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	4626	* power consumption.
Kojto	99:dbbf35b96557	4627	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	4628	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	4629	* @{
Kojto	99:dbbf35b96557	4630	*/
Kojto	99:dbbf35b96557	4631	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	4632	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	99:dbbf35b96557	4633
Kojto	99:dbbf35b96557	4634	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	4635	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	4636	/**
Kojto	110:165afa46840b	4637	* @}
Kojto	110:165afa46840b	4638	*/
Kojto	110:165afa46840b	4639
Kojto	110:165afa46840b	4640	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4641	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	4642	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	4643	* power consumption.
Kojto	99:dbbf35b96557	4644	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	4645	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	4646	* @{
Kojto	122:f9eeca106725	4647	*/
Kojto	99:dbbf35b96557	4648	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	4649	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	4650	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	4651	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	4652	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	110:165afa46840b	4653	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	99:dbbf35b96557	4654	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	4655	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	4656	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	4657	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	99:dbbf35b96557	4658	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	4659	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	4660	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
Kojto	99:dbbf35b96557	4661	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	4662	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	4663	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	4664	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	4665	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	4666	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	4667
Kojto	110:165afa46840b	4668	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	4669	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	4670	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	4671	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	4672	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	4673	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	4674	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	4675	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	4676	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	4677	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	110:165afa46840b	4678	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	99:dbbf35b96557	4679	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	4680	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	4681	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	110:165afa46840b	4682	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	99:dbbf35b96557	4683	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	4684	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	4685	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto	99:dbbf35b96557	4686	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	4687	/**
Kojto	110:165afa46840b	4688	* @}
Kojto	110:165afa46840b	4689	*/
Kojto	110:165afa46840b	4690
Kojto	110:165afa46840b	4691	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4692	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	4693	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	4694	* power consumption.
bogdanm	89:552587b429a1	4695	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	4696	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	4697	* @{
Kojto	122:f9eeca106725	4698	*/
Kojto	99:dbbf35b96557	4699	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	4700	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	4701	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	4702	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	99:dbbf35b96557	4703	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
Kojto	110:165afa46840b	4704	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	4705	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	4706	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	4707
Kojto	110:165afa46840b	4708	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	4709	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	4710	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	4711	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	4712	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	4713	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	4714	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	99:dbbf35b96557	4715	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto	110:165afa46840b	4716	/**
Kojto	110:165afa46840b	4717	* @}
Kojto	110:165afa46840b	4718	*/
Kojto	99:dbbf35b96557	4719
Kojto	99:dbbf35b96557	4720	#endif /* STM32F446xx */
Kojto	110:165afa46840b	4721	/----------------------------------------------------------------------------/
Kojto	122:f9eeca106725	4722
AnnaBridge	145:64910690c574	4723	/-------STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx-------/
AnnaBridge	145:64910690c574	4724	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	4725	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	4726	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	122:f9eeca106725	4727	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4728	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4729	* using it.
Kojto	122:f9eeca106725	4730	* @{
Kojto	122:f9eeca106725	4731	*/
Kojto	122:f9eeca106725	4732	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4733	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4734	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	122:f9eeca106725	4735	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4736	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	122:f9eeca106725	4737	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4738	} while(0U)
Kojto	122:f9eeca106725	4739	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4740	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4741	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	122:f9eeca106725	4742	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4743	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	122:f9eeca106725	4744	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4745	} while(0U)
Kojto	122:f9eeca106725	4746	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4747	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4748	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	122:f9eeca106725	4749	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4750	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	122:f9eeca106725	4751	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4752	} while(0U)
Kojto	122:f9eeca106725	4753	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4754	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4755	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	122:f9eeca106725	4756	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4757	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	122:f9eeca106725	4758	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4759	} while(0U)
Kojto	122:f9eeca106725	4760	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4761	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4762	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	122:f9eeca106725	4763	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4764	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	122:f9eeca106725	4765	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4766	} while(0U)
Kojto	122:f9eeca106725	4767
Kojto	122:f9eeca106725	4768	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	122:f9eeca106725	4769	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	122:f9eeca106725	4770	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	122:f9eeca106725	4771	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	122:f9eeca106725	4772	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	122:f9eeca106725	4773	/**
Kojto	122:f9eeca106725	4774	* @}
Kojto	122:f9eeca106725	4775	*/
Kojto	122:f9eeca106725	4776
Kojto	122:f9eeca106725	4777	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4778	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	4779	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4780	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4781	* using it.
Kojto	122:f9eeca106725	4782	* @{
Kojto	122:f9eeca106725	4783	*/
Kojto	122:f9eeca106725	4784	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	4785	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	4786	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	4787	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	122:f9eeca106725	4788	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	4789
Kojto	122:f9eeca106725	4790	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	4791	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	4792	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	4793	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	122:f9eeca106725	4794	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	4795	/**
Kojto	122:f9eeca106725	4796	* @}
Kojto	122:f9eeca106725	4797	*/
Kojto	122:f9eeca106725	4798
Kojto	122:f9eeca106725	4799	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	4800	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	122:f9eeca106725	4801	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4802	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4803	* using it.
Kojto	122:f9eeca106725	4804	* @{
Kojto	122:f9eeca106725	4805	*/
AnnaBridge	145:64910690c574	4806	#if defined(STM32F423xx)
AnnaBridge	145:64910690c574	4807	#define __HAL_RCC_AES_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	4808	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	4809	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
AnnaBridge	145:64910690c574	4810	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	4811	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
AnnaBridge	145:64910690c574	4812	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4813	} while(0U)
AnnaBridge	145:64910690c574	4814
AnnaBridge	145:64910690c574	4815	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
AnnaBridge	145:64910690c574	4816	#endif /* STM32F423xx */
Kojto	122:f9eeca106725	4817
Kojto	122:f9eeca106725	4818	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4819	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4820	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	122:f9eeca106725	4821	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4822	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	122:f9eeca106725	4823	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4824	} while(0U)
Kojto	122:f9eeca106725	4825	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	145:64910690c574	4826
AnnaBridge	145:64910690c574	4827	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	145:64910690c574	4828	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	145:64910690c574	4829	}while(0U)
AnnaBridge	145:64910690c574	4830
AnnaBridge	145:64910690c574	4831	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	122:f9eeca106725	4832	/**
Kojto	122:f9eeca106725	4833	* @}
Kojto	122:f9eeca106725	4834	*/
Kojto	122:f9eeca106725	4835
Kojto	122:f9eeca106725	4836	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4837	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	4838	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4839	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4840	* using it.
Kojto	122:f9eeca106725	4841	* @{
Kojto	122:f9eeca106725	4842	*/
AnnaBridge	145:64910690c574	4843	#if defined(STM32F423xx)
AnnaBridge	145:64910690c574	4844	#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
AnnaBridge	145:64910690c574	4845	#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
AnnaBridge	145:64910690c574	4846	#endif /* STM32F423xx */
AnnaBridge	145:64910690c574	4847
Kojto	122:f9eeca106725	4848	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	4849	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	4850
Kojto	122:f9eeca106725	4851	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	122:f9eeca106725	4852	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	4853	/**
Kojto	122:f9eeca106725	4854	* @}
Kojto	122:f9eeca106725	4855	*/
Kojto	122:f9eeca106725	4856
Kojto	122:f9eeca106725	4857	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	4858	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	122:f9eeca106725	4859	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4860	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4861	* using it.
Kojto	122:f9eeca106725	4862	* @{
Kojto	122:f9eeca106725	4863	*/
AnnaBridge	145:64910690c574	4864	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	4865	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4866	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4867	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	122:f9eeca106725	4868	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4869	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	122:f9eeca106725	4870	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4871	} while(0U)
Kojto	122:f9eeca106725	4872	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4873	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4874	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	122:f9eeca106725	4875	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4876	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	122:f9eeca106725	4877	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4878	} while(0U)
Kojto	122:f9eeca106725	4879
Kojto	122:f9eeca106725	4880	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto	122:f9eeca106725	4881	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge	145:64910690c574	4882	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	4883	/**
Kojto	122:f9eeca106725	4884	* @}
Kojto	122:f9eeca106725	4885	*/
Kojto	122:f9eeca106725	4886
Kojto	122:f9eeca106725	4887	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4888	* @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	122:f9eeca106725	4889	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4890	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4891	* using it.
Kojto	122:f9eeca106725	4892	* @{
Kojto	122:f9eeca106725	4893	*/
AnnaBridge	145:64910690c574	4894	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	4895	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
Kojto	122:f9eeca106725	4896	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto	122:f9eeca106725	4897
Kojto	122:f9eeca106725	4898	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
Kojto	122:f9eeca106725	4899	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge	145:64910690c574	4900	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	4901
Kojto	122:f9eeca106725	4902	/**
Kojto	122:f9eeca106725	4903	* @}
Kojto	122:f9eeca106725	4904	*/
Kojto	122:f9eeca106725	4905
Kojto	122:f9eeca106725	4906	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	4907	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	122:f9eeca106725	4908	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4909	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4910	* using it.
Kojto	122:f9eeca106725	4911	* @{
Kojto	122:f9eeca106725	4912	*/
Kojto	122:f9eeca106725	4913	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4914	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4915	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	122:f9eeca106725	4916	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4917	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	122:f9eeca106725	4918	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4919	} while(0U)
Kojto	122:f9eeca106725	4920	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4921	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4922	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	122:f9eeca106725	4923	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4924	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	122:f9eeca106725	4925	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4926	} while(0U)
Kojto	122:f9eeca106725	4927	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4928	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4929	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	122:f9eeca106725	4930	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4931	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	122:f9eeca106725	4932	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4933	} while(0U)
Kojto	122:f9eeca106725	4934	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4935	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4936	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	122:f9eeca106725	4937	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4938	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	122:f9eeca106725	4939	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4940	} while(0U)
Kojto	122:f9eeca106725	4941	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4942	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4943	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	122:f9eeca106725	4944	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4945	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	122:f9eeca106725	4946	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4947	} while(0U)
AnnaBridge	145:64910690c574	4948	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	4949	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	4950	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	4951	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	145:64910690c574	4952	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	4953	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	145:64910690c574	4954	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4955	} while(0U)
AnnaBridge	145:64910690c574	4956	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	4957	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4958	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4959	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	122:f9eeca106725	4960	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4961	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	122:f9eeca106725	4962	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4963	} while(0U)
AnnaBridge	145:64910690c574	4964	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	4965	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4966	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4967	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	122:f9eeca106725	4968	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4969	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	122:f9eeca106725	4970	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4971	} while(0U)
AnnaBridge	145:64910690c574	4972	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	4973
AnnaBridge	145:64910690c574	4974	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	4975	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	4976	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	4977	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	145:64910690c574	4978	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	4979	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	145:64910690c574	4980	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4981	} while(0U)
AnnaBridge	145:64910690c574	4982	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	4983	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	4984	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	145:64910690c574	4985	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	4986	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	145:64910690c574	4987	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4988	} while(0U)
AnnaBridge	145:64910690c574	4989	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	4990
Kojto	122:f9eeca106725	4991	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4992	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4993	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	122:f9eeca106725	4994	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4995	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	122:f9eeca106725	4996	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	4997	} while(0U)
Kojto	122:f9eeca106725	4998	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4999	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5000	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	122:f9eeca106725	5001	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5002	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	122:f9eeca106725	5003	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5004	} while(0U)
Kojto	122:f9eeca106725	5005	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5006	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5007	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	122:f9eeca106725	5008	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5009	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	122:f9eeca106725	5010	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5011	} while(0U)
AnnaBridge	145:64910690c574	5012	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5013	#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5014	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5015	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge	145:64910690c574	5016	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5017	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge	145:64910690c574	5018	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5019	} while(0U)
AnnaBridge	145:64910690c574	5020	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5021	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5022	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5023	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	122:f9eeca106725	5024	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5025	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	122:f9eeca106725	5026	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5027	} while(0U)
Kojto	122:f9eeca106725	5028	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5029	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5030	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	122:f9eeca106725	5031	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5032	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	122:f9eeca106725	5033	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5034	} while(0U)
Kojto	122:f9eeca106725	5035	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5036	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5037	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	122:f9eeca106725	5038	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5039	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	122:f9eeca106725	5040	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5041	} while(0U)
Kojto	122:f9eeca106725	5042	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5043	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5044	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	122:f9eeca106725	5045	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5046	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	122:f9eeca106725	5047	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5048	} while(0U)
Kojto	122:f9eeca106725	5049	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5050	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5051	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	122:f9eeca106725	5052	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5053	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	122:f9eeca106725	5054	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5055	} while(0U)
AnnaBridge	145:64910690c574	5056	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5057	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5058	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5059	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	145:64910690c574	5060	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5061	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	145:64910690c574	5062	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5063	} while(0U)
AnnaBridge	145:64910690c574	5064	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5065	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5066	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	145:64910690c574	5067	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5068	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	145:64910690c574	5069	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5070	} while(0U)
AnnaBridge	145:64910690c574	5071	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5072	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5073	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	145:64910690c574	5074	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5075	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	145:64910690c574	5076	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5077	} while(0U)
AnnaBridge	145:64910690c574	5078	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5079
Kojto	122:f9eeca106725	5080	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	122:f9eeca106725	5081	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	122:f9eeca106725	5082	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	122:f9eeca106725	5083	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	122:f9eeca106725	5084	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	122:f9eeca106725	5085	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	122:f9eeca106725	5086	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	145:64910690c574	5087	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	145:64910690c574	5088	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5089	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
AnnaBridge	145:64910690c574	5090	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5091	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
AnnaBridge	145:64910690c574	5092	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	145:64910690c574	5093	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5094	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	145:64910690c574	5095	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5096	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5097	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	145:64910690c574	5098	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	145:64910690c574	5099	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5100	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	122:f9eeca106725	5101	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	122:f9eeca106725	5102	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	122:f9eeca106725	5103	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	145:64910690c574	5104	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5105	#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
AnnaBridge	145:64910690c574	5106	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	145:64910690c574	5107	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
AnnaBridge	145:64910690c574	5108	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
AnnaBridge	145:64910690c574	5109	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5110
Kojto	122:f9eeca106725	5111	/**
Kojto	122:f9eeca106725	5112	* @}
Kojto	122:f9eeca106725	5113	*/
Kojto	122:f9eeca106725	5114
Kojto	122:f9eeca106725	5115	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	5116	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	5117	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	5118	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	5119	* using it.
Kojto	122:f9eeca106725	5120	* @{
Kojto	122:f9eeca106725	5121	*/
Kojto	122:f9eeca106725	5122	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	5123	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	5124	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	5125	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	5126	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	122:f9eeca106725	5127	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	122:f9eeca106725	5128	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	145:64910690c574	5129	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	145:64910690c574	5130	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5131	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
AnnaBridge	145:64910690c574	5132	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5133	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
AnnaBridge	145:64910690c574	5134	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	145:64910690c574	5135	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5136	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	145:64910690c574	5137	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	145:64910690c574	5138	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5139	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	145:64910690c574	5140	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	145:64910690c574	5141	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5142	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	5143	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
Kojto	122:f9eeca106725	5144	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
Kojto	122:f9eeca106725	5145	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	145:64910690c574	5146	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5147	#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
AnnaBridge	145:64910690c574	5148	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	145:64910690c574	5149	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
AnnaBridge	145:64910690c574	5150	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
AnnaBridge	145:64910690c574	5151	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5152
Kojto	122:f9eeca106725	5153	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	5154	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	5155	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	5156	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	5157	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	122:f9eeca106725	5158	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	122:f9eeca106725	5159	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	122:f9eeca106725	5160	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	145:64910690c574	5161	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5162	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
AnnaBridge	145:64910690c574	5163	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5164	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
AnnaBridge	145:64910690c574	5165	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	145:64910690c574	5166	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5167	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	145:64910690c574	5168	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	145:64910690c574	5169	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5170	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	145:64910690c574	5171	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	145:64910690c574	5172	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5173	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	5174	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
Kojto	122:f9eeca106725	5175	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	122:f9eeca106725	5176	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	145:64910690c574	5177	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5178	#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
AnnaBridge	145:64910690c574	5179	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	145:64910690c574	5180	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
AnnaBridge	145:64910690c574	5181	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
AnnaBridge	145:64910690c574	5182	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5183	/**
Kojto	122:f9eeca106725	5184	* @}
Kojto	122:f9eeca106725	5185	*/
Kojto	122:f9eeca106725	5186	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	5187	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	122:f9eeca106725	5188	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	5189	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	5190	* using it.
Kojto	122:f9eeca106725	5191	* @{
Kojto	122:f9eeca106725	5192	*/
Kojto	122:f9eeca106725	5193	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5194	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5195	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	122:f9eeca106725	5196	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5197	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	122:f9eeca106725	5198	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5199	} while(0U)
AnnaBridge	145:64910690c574	5200	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5201	#define __HAL_RCC_UART9_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5202	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5203	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
AnnaBridge	145:64910690c574	5204	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5205	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
AnnaBridge	145:64910690c574	5206	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5207	} while(0U)
AnnaBridge	145:64910690c574	5208	#define __HAL_RCC_UART10_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5209	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5210	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
AnnaBridge	145:64910690c574	5211	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5212	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
AnnaBridge	145:64910690c574	5213	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5214	} while(0U)
AnnaBridge	145:64910690c574	5215	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5216	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5217	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5218	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	145:64910690c574	5219	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5220	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	145:64910690c574	5221	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5222	} while(0U)
AnnaBridge	145:64910690c574	5223	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5224	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5225	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	145:64910690c574	5226	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5227	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	145:64910690c574	5228	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5229	} while(0U)
AnnaBridge	145:64910690c574	5230	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5231	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5232	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	145:64910690c574	5233	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5234	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	145:64910690c574	5235	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5236	} while(0U)
AnnaBridge	145:64910690c574	5237	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5238	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5239	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	145:64910690c574	5240	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5241	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	145:64910690c574	5242	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5243	} while(0U)
Kojto	122:f9eeca106725	5244	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5245	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5246	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	122:f9eeca106725	5247	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5248	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	122:f9eeca106725	5249	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5250	} while(0U)
AnnaBridge	145:64910690c574	5251	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5252	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5253	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5254	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	122:f9eeca106725	5255	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5256	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	122:f9eeca106725	5257	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5258	} while(0U)
AnnaBridge	145:64910690c574	5259	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5260	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5261	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5262	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
Kojto	122:f9eeca106725	5263	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5264	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
Kojto	122:f9eeca106725	5265	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5266	} while(0U)
AnnaBridge	145:64910690c574	5267	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5268	#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
AnnaBridge	145:64910690c574	5269	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	145:64910690c574	5270	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
AnnaBridge	145:64910690c574	5271	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	145:64910690c574	5272	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
AnnaBridge	145:64910690c574	5273	UNUSED(tmpreg); \
AnnaBridge	145:64910690c574	5274	} while(0U)
AnnaBridge	145:64910690c574	5275	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5276
AnnaBridge	145:64910690c574	5277	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	145:64910690c574	5278	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5279	#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
AnnaBridge	145:64910690c574	5280	#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
AnnaBridge	145:64910690c574	5281	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5282	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	122:f9eeca106725	5283	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	145:64910690c574	5284	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
Kojto	122:f9eeca106725	5285	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	122:f9eeca106725	5286	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	145:64910690c574	5287	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5288	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge	145:64910690c574	5289	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5290	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
AnnaBridge	145:64910690c574	5291	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5292	#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
AnnaBridge	145:64910690c574	5293	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5294	/**
Kojto	122:f9eeca106725	5295	* @}
Kojto	122:f9eeca106725	5296	*/
Kojto	122:f9eeca106725	5297
Kojto	122:f9eeca106725	5298	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	5299	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	5300	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	5301	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	5302	* using it.
Kojto	122:f9eeca106725	5303	* @{
Kojto	122:f9eeca106725	5304	*/
AnnaBridge	145:64910690c574	5305	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	145:64910690c574	5306	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5307	#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
AnnaBridge	145:64910690c574	5308	#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
AnnaBridge	145:64910690c574	5309	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5310	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	145:64910690c574	5311	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	145:64910690c574	5312	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
AnnaBridge	145:64910690c574	5313	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	145:64910690c574	5314	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	145:64910690c574	5315	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5316	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge	145:64910690c574	5317	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5318	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
AnnaBridge	145:64910690c574	5319	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5320	#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
AnnaBridge	145:64910690c574	5321	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5322
AnnaBridge	145:64910690c574	5323	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	145:64910690c574	5324	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5325	#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
AnnaBridge	145:64910690c574	5326	#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
AnnaBridge	145:64910690c574	5327	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5328	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	145:64910690c574	5329	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	145:64910690c574	5330	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
AnnaBridge	145:64910690c574	5331	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	145:64910690c574	5332	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	145:64910690c574	5333	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5334	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge	145:64910690c574	5335	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5336	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
AnnaBridge	145:64910690c574	5337	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5338	#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
AnnaBridge	145:64910690c574	5339	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5340	/**
Kojto	122:f9eeca106725	5341	* @}
Kojto	122:f9eeca106725	5342	*/
Kojto	122:f9eeca106725	5343
Kojto	122:f9eeca106725	5344	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	122:f9eeca106725	5345	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	5346	* @{
Kojto	122:f9eeca106725	5347	*/
Kojto	122:f9eeca106725	5348	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	122:f9eeca106725	5349	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	122:f9eeca106725	5350	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	122:f9eeca106725	5351	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	122:f9eeca106725	5352	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	122:f9eeca106725	5353
Kojto	122:f9eeca106725	5354	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	122:f9eeca106725	5355	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	122:f9eeca106725	5356	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	122:f9eeca106725	5357	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	122:f9eeca106725	5358	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	122:f9eeca106725	5359	/**
Kojto	122:f9eeca106725	5360	* @}
Kojto	122:f9eeca106725	5361	*/
Kojto	122:f9eeca106725	5362
Kojto	122:f9eeca106725	5363	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	122:f9eeca106725	5364	* @brief Force or release AHB2 peripheral reset.
Kojto	122:f9eeca106725	5365	* @{
Kojto	122:f9eeca106725	5366	*/
Kojto	122:f9eeca106725	5367	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	5368	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	122:f9eeca106725	5369
AnnaBridge	145:64910690c574	5370	#if defined(STM32F423xx)
AnnaBridge	145:64910690c574	5371	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_AESRST))
AnnaBridge	145:64910690c574	5372	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
AnnaBridge	145:64910690c574	5373	#endif /* STM32F423xx */
AnnaBridge	145:64910690c574	5374
Kojto	122:f9eeca106725	5375	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	122:f9eeca106725	5376	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	122:f9eeca106725	5377
Kojto	122:f9eeca106725	5378	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	122:f9eeca106725	5379	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	122:f9eeca106725	5380	/**
Kojto	122:f9eeca106725	5381	* @}
Kojto	122:f9eeca106725	5382	*/
Kojto	122:f9eeca106725	5383
Kojto	122:f9eeca106725	5384	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	122:f9eeca106725	5385	* @brief Force or release AHB3 peripheral reset.
Kojto	122:f9eeca106725	5386	* @{
Kojto	122:f9eeca106725	5387	*/
AnnaBridge	145:64910690c574	5388	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5389	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	5390	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	122:f9eeca106725	5391
Kojto	122:f9eeca106725	5392	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
Kojto	122:f9eeca106725	5393	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	122:f9eeca106725	5394
Kojto	122:f9eeca106725	5395	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto	122:f9eeca106725	5396	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge	145:64910690c574	5397	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5398	#if defined(STM32F412Cx)
Kojto	122:f9eeca106725	5399	#define __HAL_RCC_AHB3_FORCE_RESET()
Kojto	122:f9eeca106725	5400	#define __HAL_RCC_AHB3_RELEASE_RESET()
Kojto	122:f9eeca106725	5401
Kojto	122:f9eeca106725	5402	#define __HAL_RCC_FSMC_FORCE_RESET()
Kojto	122:f9eeca106725	5403	#define __HAL_RCC_QSPI_FORCE_RESET()
Kojto	122:f9eeca106725	5404
Kojto	122:f9eeca106725	5405	#define __HAL_RCC_FSMC_RELEASE_RESET()
Kojto	122:f9eeca106725	5406	#define __HAL_RCC_QSPI_RELEASE_RESET()
Kojto	122:f9eeca106725	5407	#endif /* STM32F412Cx */
Kojto	122:f9eeca106725	5408	/**
Kojto	122:f9eeca106725	5409	* @}
Kojto	122:f9eeca106725	5410	*/
Kojto	122:f9eeca106725	5411
Kojto	122:f9eeca106725	5412	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	122:f9eeca106725	5413	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	5414	* @{
Kojto	122:f9eeca106725	5415	*/
AnnaBridge	145:64910690c574	5416	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	145:64910690c574	5417	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	145:64910690c574	5418	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	122:f9eeca106725	5419	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	122:f9eeca106725	5420	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	122:f9eeca106725	5421	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	122:f9eeca106725	5422	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	145:64910690c574	5423	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	145:64910690c574	5424	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5425	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	145:64910690c574	5426	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5427	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	145:64910690c574	5428	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5429	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	145:64910690c574	5430	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5431	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5432	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	145:64910690c574	5433	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	145:64910690c574	5434	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5435	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	122:f9eeca106725	5436	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	122:f9eeca106725	5437	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	122:f9eeca106725	5438	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	145:64910690c574	5439	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5440	#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN3RST))
AnnaBridge	145:64910690c574	5441	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	145:64910690c574	5442	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
AnnaBridge	145:64910690c574	5443	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
AnnaBridge	145:64910690c574	5444	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5445
AnnaBridge	145:64910690c574	5446	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	145:64910690c574	5447	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	145:64910690c574	5448	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	145:64910690c574	5449	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	145:64910690c574	5450	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	145:64910690c574	5451	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	145:64910690c574	5452	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	145:64910690c574	5453	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	145:64910690c574	5454	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5455	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	145:64910690c574	5456	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5457	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	145:64910690c574	5458	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5459	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	145:64910690c574	5460	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5461	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5462	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	145:64910690c574	5463	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	145:64910690c574	5464	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5465	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	122:f9eeca106725	5466	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	145:64910690c574	5467	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	145:64910690c574	5468	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	145:64910690c574	5469	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5470	#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
AnnaBridge	145:64910690c574	5471	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	145:64910690c574	5472	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
AnnaBridge	145:64910690c574	5473	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
AnnaBridge	145:64910690c574	5474	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5475	/**
Kojto	122:f9eeca106725	5476	* @}
Kojto	122:f9eeca106725	5477	*/
Kojto	122:f9eeca106725	5478
Kojto	122:f9eeca106725	5479	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	122:f9eeca106725	5480	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	5481	* @{
Kojto	122:f9eeca106725	5482	*/
Kojto	122:f9eeca106725	5483	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	145:64910690c574	5484	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5485	#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART9RST))
AnnaBridge	145:64910690c574	5486	#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART10RST))
AnnaBridge	145:64910690c574	5487	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5488	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	122:f9eeca106725	5489	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	145:64910690c574	5490	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	145:64910690c574	5491	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	145:64910690c574	5492	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5493	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
AnnaBridge	145:64910690c574	5494	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5495	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
AnnaBridge	145:64910690c574	5496	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5497	#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM2RST))
AnnaBridge	145:64910690c574	5498	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5499
AnnaBridge	145:64910690c574	5500	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	145:64910690c574	5501	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5502	#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
AnnaBridge	145:64910690c574	5503	#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
AnnaBridge	145:64910690c574	5504	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5505	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	122:f9eeca106725	5506	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	122:f9eeca106725	5507	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	122:f9eeca106725	5508	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	145:64910690c574	5509	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5510	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge	145:64910690c574	5511	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5512	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
AnnaBridge	145:64910690c574	5513	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5514	#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
AnnaBridge	145:64910690c574	5515	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5516	/**
Kojto	122:f9eeca106725	5517	* @}
Kojto	122:f9eeca106725	5518	*/
Kojto	122:f9eeca106725	5519
Kojto	122:f9eeca106725	5520	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5521	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5522	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5523	* power consumption.
Kojto	122:f9eeca106725	5524	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5525	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5526	* @{
Kojto	122:f9eeca106725	5527	*/
Kojto	122:f9eeca106725	5528	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	122:f9eeca106725	5529	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	122:f9eeca106725	5530	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	122:f9eeca106725	5531	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	122:f9eeca106725	5532	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	122:f9eeca106725	5533	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	122:f9eeca106725	5534	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	145:64910690c574	5535	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5536	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	145:64910690c574	5537	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5538
Kojto	122:f9eeca106725	5539	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	122:f9eeca106725	5540	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	122:f9eeca106725	5541	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	122:f9eeca106725	5542	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	122:f9eeca106725	5543	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	122:f9eeca106725	5544	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	122:f9eeca106725	5545	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	145:64910690c574	5546	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5547	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	145:64910690c574	5548	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5549	/**
Kojto	122:f9eeca106725	5550	* @}
Kojto	122:f9eeca106725	5551	*/
Kojto	122:f9eeca106725	5552
Kojto	122:f9eeca106725	5553	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5554	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5555	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5556	* power consumption.
Kojto	122:f9eeca106725	5557	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5558	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5559	* @{
Kojto	122:f9eeca106725	5560	*/
AnnaBridge	145:64910690c574	5561	#if defined(STM32F423xx)
AnnaBridge	145:64910690c574	5562	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AESLPEN))
AnnaBridge	145:64910690c574	5563	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
AnnaBridge	145:64910690c574	5564	#endif /* STM32F423xx */
AnnaBridge	145:64910690c574	5565
Kojto	122:f9eeca106725	5566	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	122:f9eeca106725	5567	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	122:f9eeca106725	5568
Kojto	122:f9eeca106725	5569	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	122:f9eeca106725	5570	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	122:f9eeca106725	5571	/**
Kojto	122:f9eeca106725	5572	* @}
Kojto	122:f9eeca106725	5573	*/
Kojto	122:f9eeca106725	5574
Kojto	122:f9eeca106725	5575	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5576	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5577	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5578	* power consumption.
Kojto	122:f9eeca106725	5579	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5580	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5581	* @{
Kojto	122:f9eeca106725	5582	*/
AnnaBridge	145:64910690c574	5583	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5584	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
Kojto	122:f9eeca106725	5585	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	122:f9eeca106725	5586
Kojto	122:f9eeca106725	5587	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto	122:f9eeca106725	5588	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	145:64910690c574	5589	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5590
Kojto	122:f9eeca106725	5591	/**
Kojto	122:f9eeca106725	5592	* @}
Kojto	122:f9eeca106725	5593	*/
Kojto	122:f9eeca106725	5594
Kojto	122:f9eeca106725	5595	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5596	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5597	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5598	* power consumption.
Kojto	122:f9eeca106725	5599	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5600	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5601	* @{
Kojto	122:f9eeca106725	5602	*/
AnnaBridge	145:64910690c574	5603	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	145:64910690c574	5604	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	145:64910690c574	5605	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	122:f9eeca106725	5606	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	122:f9eeca106725	5607	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	122:f9eeca106725	5608	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	122:f9eeca106725	5609	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	122:f9eeca106725	5610	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	145:64910690c574	5611	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5612	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	145:64910690c574	5613	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5614	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	145:64910690c574	5615	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	145:64910690c574	5616	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5617	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	145:64910690c574	5618	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5619	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5620	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	145:64910690c574	5621	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	145:64910690c574	5622	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5623	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	122:f9eeca106725	5624	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	122:f9eeca106725	5625	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	122:f9eeca106725	5626	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	145:64910690c574	5627	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5628	#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN3LPEN))
AnnaBridge	145:64910690c574	5629	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	145:64910690c574	5630	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
AnnaBridge	145:64910690c574	5631	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
AnnaBridge	145:64910690c574	5632	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5633
Kojto	122:f9eeca106725	5634	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	122:f9eeca106725	5635	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	122:f9eeca106725	5636	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	122:f9eeca106725	5637	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	122:f9eeca106725	5638	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	122:f9eeca106725	5639	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	122:f9eeca106725	5640	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	122:f9eeca106725	5641	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	145:64910690c574	5642	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5643	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	145:64910690c574	5644	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5645	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	145:64910690c574	5646	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	145:64910690c574	5647	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5648	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	145:64910690c574	5649	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5650	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5651	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	145:64910690c574	5652	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	145:64910690c574	5653	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5654	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	122:f9eeca106725	5655	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	122:f9eeca106725	5656	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	122:f9eeca106725	5657	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	145:64910690c574	5658	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5659	#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
AnnaBridge	145:64910690c574	5660	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	145:64910690c574	5661	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
AnnaBridge	145:64910690c574	5662	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
AnnaBridge	145:64910690c574	5663	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5664	/**
Kojto	122:f9eeca106725	5665	* @}
Kojto	122:f9eeca106725	5666	*/
Kojto	122:f9eeca106725	5667
Kojto	122:f9eeca106725	5668	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5669	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5670	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5671	* power consumption.
Kojto	122:f9eeca106725	5672	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5673	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5674	* @{
Kojto	122:f9eeca106725	5675	*/
Kojto	122:f9eeca106725	5676	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	145:64910690c574	5677	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5678	#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART9LPEN))
AnnaBridge	145:64910690c574	5679	#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART10LPEN))
AnnaBridge	145:64910690c574	5680	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5681	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	145:64910690c574	5682	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	145:64910690c574	5683	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	145:64910690c574	5684	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	145:64910690c574	5685	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	145:64910690c574	5686	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5687	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	145:64910690c574	5688	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5689	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge	145:64910690c574	5690	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5691	#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM2LPEN))
AnnaBridge	145:64910690c574	5692	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5693
AnnaBridge	145:64910690c574	5694	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	145:64910690c574	5695	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5696	#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
AnnaBridge	145:64910690c574	5697	#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
AnnaBridge	145:64910690c574	5698	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5699	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	122:f9eeca106725	5700	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	145:64910690c574	5701	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	145:64910690c574	5702	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	122:f9eeca106725	5703	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	145:64910690c574	5704	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5705	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	145:64910690c574	5706	#endif /* STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5707	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge	145:64910690c574	5708	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	5709	#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
AnnaBridge	145:64910690c574	5710	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	5711	/**
AnnaBridge	145:64910690c574	5712	* @}
AnnaBridge	145:64910690c574	5713	*/
AnnaBridge	145:64910690c574	5714	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	5715	/----------------------------------------------------------------------------/
Kojto	122:f9eeca106725	5716
Kojto	110:165afa46840b	5717	/------------------------------- PLL Configuration --------------------------/
Kojto	110:165afa46840b	5718	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
Kojto	122:f9eeca106725	5719	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	145:64910690c574	5720	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	99:dbbf35b96557	5721	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	5722	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	5723	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	5724	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5725	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	5726	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	5727	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	99:dbbf35b96557	5728	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	99:dbbf35b96557	5729	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	5730	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5731	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5732	* of 2 MHz to limit PLL jitter.
Kojto	99:dbbf35b96557	5733	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	122:f9eeca106725	5734	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5735	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5736	* output frequency is between 100 and 432 MHz.
Kojto	99:dbbf35b96557	5737	*
Kojto	99:dbbf35b96557	5738	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	5739	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	5740	*
Kojto	99:dbbf35b96557	5741	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	110:165afa46840b	5742	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	5743	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	99:dbbf35b96557	5744	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	99:dbbf35b96557	5745	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	99:dbbf35b96557	5746	* correctly.
Kojto	99:dbbf35b96557	5747	*
Kojto	99:dbbf35b96557	5748	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	99:dbbf35b96557	5749	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	122:f9eeca106725	5750	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
AnnaBridge	145:64910690c574	5751	STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
Kojto	99:dbbf35b96557	5752	*
Kojto	99:dbbf35b96557	5753	*/
Kojto	99:dbbf35b96557	5754	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
Kojto	99:dbbf35b96557	5755	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
Kojto	99:dbbf35b96557	5756	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
AnnaBridge	145:64910690c574	5757	((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	99:dbbf35b96557	5758	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
Kojto	99:dbbf35b96557	5759	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
Kojto	99:dbbf35b96557	5760	#else
Kojto	99:dbbf35b96557	5761	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	5762	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	5763	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	5764	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5765	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	5766	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	5767	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	99:dbbf35b96557	5768	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	99:dbbf35b96557	5769	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	5770	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5771	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5772	* of 2 MHz to limit PLL jitter.
Kojto	99:dbbf35b96557	5773	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	122:f9eeca106725	5774	* This parameter must be a number between Min_Data = 50 and Max_Data = 432
Kojto	122:f9eeca106725	5775	* Except for STM32F411xE devices where Min_Data = 192.
Kojto	99:dbbf35b96557	5776	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5777	* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
Kojto	122:f9eeca106725	5778	* where frequency is between 192 and 432 MHz.
Kojto	99:dbbf35b96557	5779	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	5780	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	5781	*
Kojto	99:dbbf35b96557	5782	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	110:165afa46840b	5783	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	5784	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	99:dbbf35b96557	5785	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	99:dbbf35b96557	5786	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	99:dbbf35b96557	5787	* correctly.
Kojto	99:dbbf35b96557	5788	*
Kojto	99:dbbf35b96557	5789	*/
Kojto	99:dbbf35b96557	5790	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
Kojto	122:f9eeca106725	5791	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
Kojto	99:dbbf35b96557	5792	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
AnnaBridge	145:64910690c574	5793	((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	99:dbbf35b96557	5794	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto	122:f9eeca106725	5795	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	110:165afa46840b	5796	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	5797
Kojto	110:165afa46840b	5798	/----------------------------PLLI2S Configuration ---------------------------/
Kojto	110:165afa46840b	5799	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	5800	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	5801	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	5802	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	145:64910690c574	5803	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	110:165afa46840b	5804
Kojto	110:165afa46840b	5805	/** @brief Macros to enable or disable the PLLI2S.
Kojto	110:165afa46840b	5806	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto	110:165afa46840b	5807	*/
Kojto	110:165afa46840b	5808	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
Kojto	110:165afa46840b	5809	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
Kojto	110:165afa46840b	5810
Kojto	110:165afa46840b	5811	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	5812	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
Kojto	122:f9eeca106725	5813	STM32F412Rx \|\| STM32F412Cx */
Kojto	99:dbbf35b96557	5814	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	5815	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	5816	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5817	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	5818	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	5819	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	99:dbbf35b96557	5820	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	5821	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5822	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5823	* of 1 MHz to limit PLLI2S jitter.
Kojto	110:165afa46840b	5824	*
Kojto	99:dbbf35b96557	5825	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	122:f9eeca106725	5826	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5827	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5828	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5829	*
Kojto	99:dbbf35b96557	5830	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
Kojto	99:dbbf35b96557	5831	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	5832	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
Kojto	99:dbbf35b96557	5833	*
Kojto	99:dbbf35b96557	5834	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	5835	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5836	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	5837	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	5838	*
Kojto	99:dbbf35b96557	5839	* @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	5840	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	5841	*/
Kojto	110:165afa46840b	5842	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	110:165afa46840b	5843	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	110:165afa46840b	5844	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
AnnaBridge	145:64910690c574	5845	((((__PLLI2SP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
Kojto	110:165afa46840b	5846	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	110:165afa46840b	5847	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
AnnaBridge	145:64910690c574	5848	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	145:64910690c574	5849	defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	5850	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	122:f9eeca106725	5851	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	122:f9eeca106725	5852	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	122:f9eeca106725	5853	* HAL_RCC_ClockConfig() API).
Kojto	122:f9eeca106725	5854	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	122:f9eeca106725	5855	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	122:f9eeca106725	5856	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	122:f9eeca106725	5857	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	122:f9eeca106725	5858	* of 1 MHz to limit PLLI2S jitter.
Kojto	122:f9eeca106725	5859	*
Kojto	122:f9eeca106725	5860	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	122:f9eeca106725	5861	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	122:f9eeca106725	5862	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5863	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	122:f9eeca106725	5864	*
Kojto	122:f9eeca106725	5865	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	122:f9eeca106725	5866	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	122:f9eeca106725	5867	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	122:f9eeca106725	5868	* on the I2S clock frequency.
Kojto	122:f9eeca106725	5869	*
Kojto	122:f9eeca106725	5870	* @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto	122:f9eeca106725	5871	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	122:f9eeca106725	5872	*/
Kojto	122:f9eeca106725	5873	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	122:f9eeca106725	5874	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	122:f9eeca106725	5875	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	122:f9eeca106725	5876	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	122:f9eeca106725	5877	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	5878	#else
Kojto	99:dbbf35b96557	5879	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	5880	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5881	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	5882	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	5883	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	122:f9eeca106725	5884	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5885	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5886	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	110:165afa46840b	5887	*
Kojto	99:dbbf35b96557	5888	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	5889	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5890	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	5891	* on the I2S clock frequency.
Kojto	110:165afa46840b	5892	*
Kojto	110:165afa46840b	5893	*/
Kojto	110:165afa46840b	5894	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
Kojto	110:165afa46840b	5895	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	99:dbbf35b96557	5896	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	5897	#endif /* STM32F446xx */
bogdanm	89:552587b429a1	5898
bogdanm	92:4fc01daae5a5	5899	#if defined(STM32F411xE)
Kojto	99:dbbf35b96557	5900	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	5901	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5902	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5903	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	5904	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	5905	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	99:dbbf35b96557	5906	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	110:165afa46840b	5907	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
Kojto	99:dbbf35b96557	5908	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5909	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5910	* of 2 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	5911	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	99:dbbf35b96557	5912	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	5913	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	5914	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5915	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	5916	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5917	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	5918	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	5919	*/
Kojto	99:dbbf35b96557	5920	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	99:dbbf35b96557	5921	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	99:dbbf35b96557	5922	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	5923	#endif /* STM32F411xE */
Kojto	99:dbbf35b96557	5924
Kojto	110:165afa46840b	5925	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	5926	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto	99:dbbf35b96557	5927	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5928	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	5929	* HAL_RCC_ClockConfig() API)
Kojto	99:dbbf35b96557	5930	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	5931	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5932	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5933	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5934	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
Kojto	99:dbbf35b96557	5935	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	5936	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
Kojto	110:165afa46840b	5937	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
Kojto	99:dbbf35b96557	5938	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	5939	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5940	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	5941	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	5942	*/
AnnaBridge	145:64910690c574	5943	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) \|\
AnnaBridge	145:64910690c574	5944	((__PLLI2SQ__) << 24U) \|\
AnnaBridge	145:64910690c574	5945	((__PLLI2SR__) << 28U))
Kojto	110:165afa46840b	5946	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	5947	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	5948
Kojto	110:165afa46840b	5949	/------------------------------ PLLSAI Configuration ------------------------/
Kojto	110:165afa46840b	5950	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	5951	/** @brief Macros to Enable or Disable the PLLISAI.
Kojto	110:165afa46840b	5952	* @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto	99:dbbf35b96557	5953	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	5954	*/
Kojto	99:dbbf35b96557	5955	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
Kojto	99:dbbf35b96557	5956	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
Kojto	99:dbbf35b96557	5957
Kojto	99:dbbf35b96557	5958	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	5959	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	99:dbbf35b96557	5960	*
Kojto	99:dbbf35b96557	5961	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
Kojto	99:dbbf35b96557	5962	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	5963	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5964	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5965	* of 1 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	5966	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
Kojto	99:dbbf35b96557	5967	*
Kojto	99:dbbf35b96557	5968	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	122:f9eeca106725	5969	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5970	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5971	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5972	*
Kojto	99:dbbf35b96557	5973	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	5974	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	5975	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
Kojto	99:dbbf35b96557	5976	*
Kojto	99:dbbf35b96557	5977	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	5978	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	5979	*
Kojto	99:dbbf35b96557	5980	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	99:dbbf35b96557	5981	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5982	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	99:dbbf35b96557	5983	*/
Kojto	99:dbbf35b96557	5984	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	99:dbbf35b96557	5985	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
Kojto	99:dbbf35b96557	5986	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
AnnaBridge	145:64910690c574	5987	((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
Kojto	99:dbbf35b96557	5988	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
Kojto	99:dbbf35b96557	5989	#endif /* STM32F446xx */
Kojto	110:165afa46840b	5990
Kojto	110:165afa46840b	5991	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	5992	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	110:165afa46840b	5993	*
Kojto	110:165afa46840b	5994	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	122:f9eeca106725	5995	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	110:165afa46840b	5996	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5997	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	110:165afa46840b	5998	*
Kojto	110:165afa46840b	5999	* @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
Kojto	110:165afa46840b	6000	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	110:165afa46840b	6001	*
Kojto	110:165afa46840b	6002	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	110:165afa46840b	6003	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	6004	*
Kojto	110:165afa46840b	6005	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	110:165afa46840b	6006	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	110:165afa46840b	6007	*/
Kojto	110:165afa46840b	6008	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	110:165afa46840b	6009	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
AnnaBridge	145:64910690c574	6010	((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
Kojto	110:165afa46840b	6011	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
Kojto	110:165afa46840b	6012	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	110:165afa46840b	6013	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	6014
Kojto	99:dbbf35b96557	6015	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	6016	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	99:dbbf35b96557	6017	*
Kojto	99:dbbf35b96557	6018	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	122:f9eeca106725	6019	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	6020	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	6021	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	6022	*
Kojto	99:dbbf35b96557	6023	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	6024	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	6025	*
Kojto	99:dbbf35b96557	6026	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	99:dbbf35b96557	6027	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	6028	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
bogdanm	92:4fc01daae5a5	6029	*/
Kojto	99:dbbf35b96557	6030	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	99:dbbf35b96557	6031	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	99:dbbf35b96557	6032	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
Kojto	99:dbbf35b96557	6033	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	99:dbbf35b96557	6034	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	6035
Kojto	110:165afa46840b	6036	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6037	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	6038
Kojto	110:165afa46840b	6039	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
AnnaBridge	145:64910690c574	6040	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	6041	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
AnnaBridge	145:64910690c574	6042	* @note This function must be called before enabling the PLLI2S.
AnnaBridge	145:64910690c574	6043	* @param __PLLI2SDivR__: specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	145:64910690c574	6044	* This parameter must be a number between 1 and 32.
AnnaBridge	145:64910690c574	6045	* SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
AnnaBridge	145:64910690c574	6046	*/
AnnaBridge	145:64910690c574	6047	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
AnnaBridge	145:64910690c574	6048
AnnaBridge	145:64910690c574	6049	/** @brief Macro to configure the SAI clock Divider coming from PLL.
AnnaBridge	145:64910690c574	6050	* @param __PLLDivR__: specifies the PLL division factor for SAI1 clock.
AnnaBridge	145:64910690c574	6051	* This parameter must be a number between 1 and 32.
AnnaBridge	145:64910690c574	6052	* SAI1 clock frequency = f(PLLR) / __PLLDivR__
AnnaBridge	145:64910690c574	6053	*/
AnnaBridge	145:64910690c574	6054	#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
AnnaBridge	145:64910690c574	6055	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	6056
Kojto	110:165afa46840b	6057	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	6058	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	6059	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto	110:165afa46840b	6060	* @note This function must be called before enabling the PLLI2S.
Kojto	110:165afa46840b	6061	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	6062	* This parameter must be a number between 1 and 32.
Kojto	99:dbbf35b96557	6063	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto	99:dbbf35b96557	6064	*/
AnnaBridge	145:64910690c574	6065	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
Kojto	99:dbbf35b96557	6066
Kojto	99:dbbf35b96557	6067	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto	99:dbbf35b96557	6068	* @note This function must be called before enabling the PLLSAI.
Kojto	99:dbbf35b96557	6069	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto	99:dbbf35b96557	6070	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto	99:dbbf35b96557	6071	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto	99:dbbf35b96557	6072	*/
AnnaBridge	145:64910690c574	6073	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
Kojto	110:165afa46840b	6074	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6075
Kojto	110:165afa46840b	6076	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	6077	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto	99:dbbf35b96557	6078	*
Kojto	110:165afa46840b	6079	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	6080	* @note This function must be called before enabling the PLLSAI.
Kojto	99:dbbf35b96557	6081	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto	99:dbbf35b96557	6082	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto	99:dbbf35b96557	6083	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto	110:165afa46840b	6084	*/
Kojto	99:dbbf35b96557	6085	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
Kojto	110:165afa46840b	6086	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6087	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	6088
Kojto	110:165afa46840b	6089	/------------------------- Peripheral Clock selection -----------------------/
Kojto	99:dbbf35b96557	6090	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Kojto	99:dbbf35b96557	6091	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	6092	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
Kojto	110:165afa46840b	6093	defined(STM32F479xx)
Kojto	99:dbbf35b96557	6094	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	99:dbbf35b96557	6095	* @note This function must be called before enabling the I2S APB clock.
Kojto	99:dbbf35b96557	6096	* @param __SOURCE__: specifies the I2S clock source.
Kojto	99:dbbf35b96557	6097	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6098	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto	99:dbbf35b96557	6099	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	6100	* used as I2S clock source.
bogdanm	92:4fc01daae5a5	6101	*/
Kojto	99:dbbf35b96557	6102	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
AnnaBridge	145:64910690c574	6103
AnnaBridge	145:64910690c574	6104
AnnaBridge	145:64910690c574	6105	/** @brief Macro to get the I2S clock source (I2SCLK).
AnnaBridge	145:64910690c574	6106	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6107	* @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
AnnaBridge	145:64910690c574	6108	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge	145:64910690c574	6109	* used as I2S clock source
AnnaBridge	145:64910690c574	6110	*/
AnnaBridge	145:64910690c574	6111	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
Kojto	110:165afa46840b	6112	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	6113
Kojto	110:165afa46840b	6114	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	6115
Kojto	99:dbbf35b96557	6116	/** @brief Macro to configure SAI1BlockA clock source selection.
Kojto	110:165afa46840b	6117	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	6118	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	6119	* the SAI clock.
Kojto	99:dbbf35b96557	6120	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	99:dbbf35b96557	6121	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6122	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	99:dbbf35b96557	6123	* as SAI1 Block A clock.
Kojto	99:dbbf35b96557	6124	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	99:dbbf35b96557	6125	* as SAI1 Block A clock.
Kojto	99:dbbf35b96557	6126	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	6127	* used as SAI1 Block A clock.
Kojto	99:dbbf35b96557	6128	*/
Kojto	99:dbbf35b96557	6129	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	6130
Kojto	99:dbbf35b96557	6131	/** @brief Macro to configure SAI1BlockB clock source selection.
Kojto	110:165afa46840b	6132	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	6133	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	6134	* the SAI clock.
Kojto	99:dbbf35b96557	6135	* @param __SOURCE__: specifies the SAI Block B clock source.
Kojto	99:dbbf35b96557	6136	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6137	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	99:dbbf35b96557	6138	* as SAI1 Block B clock.
Kojto	99:dbbf35b96557	6139	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	99:dbbf35b96557	6140	* as SAI1 Block B clock.
Kojto	99:dbbf35b96557	6141	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	6142	* used as SAI1 Block B clock.
Kojto	99:dbbf35b96557	6143	*/
Kojto	99:dbbf35b96557	6144	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
Kojto	110:165afa46840b	6145	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	6146
Kojto	99:dbbf35b96557	6147	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	6148	/** @brief Macro to configure SAI1 clock source selection.
Kojto	110:165afa46840b	6149	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	6150	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	6151	* the SAI clock.
Kojto	99:dbbf35b96557	6152	* @param __SOURCE__: specifies the SAI1 clock source.
Kojto	99:dbbf35b96557	6153	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6154	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	6155	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	6156	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	6157	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	6158	*/
Kojto	99:dbbf35b96557	6159	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	6160
Kojto	99:dbbf35b96557	6161	/** @brief Macro to Get SAI1 clock source selection.
Kojto	99:dbbf35b96557	6162	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	6163	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	6164	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	6165	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	6166	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	6167	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	6168	*/
Kojto	99:dbbf35b96557	6169	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
Kojto	99:dbbf35b96557	6170
Kojto	99:dbbf35b96557	6171	/** @brief Macro to configure SAI2 clock source selection.
Kojto	99:dbbf35b96557	6172	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	6173	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	6174	* the SAI clock.
Kojto	99:dbbf35b96557	6175	* @param __SOURCE__: specifies the SAI2 clock source.
Kojto	99:dbbf35b96557	6176	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6177	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	6178	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	6179	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	99:dbbf35b96557	6180	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	99:dbbf35b96557	6181	*/
Kojto	99:dbbf35b96557	6182	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
bogdanm	92:4fc01daae5a5	6183
Kojto	99:dbbf35b96557	6184	/** @brief Macro to Get SAI2 clock source selection.
Kojto	99:dbbf35b96557	6185	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	6186	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	6187	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	6188	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	6189	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	99:dbbf35b96557	6190	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	99:dbbf35b96557	6191	*/
Kojto	99:dbbf35b96557	6192	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
Kojto	99:dbbf35b96557	6193
Kojto	99:dbbf35b96557	6194	/** @brief Macro to configure I2S APB1 clock source selection.
Kojto	99:dbbf35b96557	6195	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	99:dbbf35b96557	6196	* @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto	99:dbbf35b96557	6197	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6198	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	145:64910690c574	6199	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
AnnaBridge	145:64910690c574	6200	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
Kojto	99:dbbf35b96557	6201	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	6202	*/
Kojto	99:dbbf35b96557	6203	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	6204
Kojto	99:dbbf35b96557	6205	/** @brief Macro to Get I2S APB1 clock source selection.
Kojto	99:dbbf35b96557	6206	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	6207	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	145:64910690c574	6208	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
AnnaBridge	145:64910690c574	6209	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
Kojto	99:dbbf35b96557	6210	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	6211	*/
Kojto	99:dbbf35b96557	6212	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto	99:dbbf35b96557	6213
Kojto	99:dbbf35b96557	6214	/** @brief Macro to configure I2S APB2 clock source selection.
Kojto	99:dbbf35b96557	6215	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	99:dbbf35b96557	6216	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	99:dbbf35b96557	6217	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6218	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	145:64910690c574	6219	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
AnnaBridge	145:64910690c574	6220	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
Kojto	99:dbbf35b96557	6221	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	6222	*/
Kojto	99:dbbf35b96557	6223	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	6224
Kojto	99:dbbf35b96557	6225	/** @brief Macro to Get I2S APB2 clock source selection.
Kojto	99:dbbf35b96557	6226	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	6227	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	145:64910690c574	6228	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
AnnaBridge	145:64910690c574	6229	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
Kojto	99:dbbf35b96557	6230	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	6231	*/
Kojto	99:dbbf35b96557	6232	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto	99:dbbf35b96557	6233
Kojto	99:dbbf35b96557	6234	/** @brief Macro to configure the CEC clock.
Kojto	99:dbbf35b96557	6235	* @param __SOURCE__: specifies the CEC clock source.
Kojto	99:dbbf35b96557	6236	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6237	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	99:dbbf35b96557	6238	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	99:dbbf35b96557	6239	*/
Kojto	99:dbbf35b96557	6240	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
bogdanm	89:552587b429a1	6241
Kojto	99:dbbf35b96557	6242	/** @brief Macro to Get the CEC clock.
Kojto	99:dbbf35b96557	6243	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	6244	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
Kojto	99:dbbf35b96557	6245	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	99:dbbf35b96557	6246	*/
Kojto	99:dbbf35b96557	6247	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
Kojto	110:165afa46840b	6248
Kojto	99:dbbf35b96557	6249	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	99:dbbf35b96557	6250	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	99:dbbf35b96557	6251	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6252	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
Kojto	110:165afa46840b	6253	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	6254	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	99:dbbf35b96557	6255	*/
Kojto	99:dbbf35b96557	6256	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	6257
Kojto	99:dbbf35b96557	6258	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	99:dbbf35b96557	6259	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6260	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
Kojto	110:165afa46840b	6261	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	6262	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	99:dbbf35b96557	6263	*/
Kojto	99:dbbf35b96557	6264	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	99:dbbf35b96557	6265
Kojto	99:dbbf35b96557	6266	/** @brief Macro to configure the CLK48 clock.
Kojto	122:f9eeca106725	6267	* @param __SOURCE__: specifies the CLK48 clock source.
Kojto	99:dbbf35b96557	6268	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6269	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	6270	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
Kojto	99:dbbf35b96557	6271	*/
Kojto	99:dbbf35b96557	6272	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	6273
Kojto	99:dbbf35b96557	6274	/** @brief Macro to Get the CLK48 clock.
Kojto	99:dbbf35b96557	6275	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6276	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	6277	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
Kojto	99:dbbf35b96557	6278	*/
Kojto	99:dbbf35b96557	6279	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto	99:dbbf35b96557	6280
Kojto	99:dbbf35b96557	6281	/** @brief Macro to configure the SDIO clock.
Kojto	99:dbbf35b96557	6282	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	99:dbbf35b96557	6283	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6284	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	99:dbbf35b96557	6285	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	99:dbbf35b96557	6286	*/
Kojto	99:dbbf35b96557	6287	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	6288
Kojto	99:dbbf35b96557	6289	/** @brief Macro to Get the SDIO clock.
Kojto	99:dbbf35b96557	6290	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6291	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	99:dbbf35b96557	6292	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	99:dbbf35b96557	6293	*/
Kojto	99:dbbf35b96557	6294	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto	99:dbbf35b96557	6295
Kojto	99:dbbf35b96557	6296	/** @brief Macro to configure the SPDIFRX clock.
Kojto	99:dbbf35b96557	6297	* @param __SOURCE__: specifies the SPDIFRX clock source.
Kojto	99:dbbf35b96557	6298	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	6299	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	99:dbbf35b96557	6300	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	99:dbbf35b96557	6301	*/
Kojto	99:dbbf35b96557	6302	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	6303
Kojto	99:dbbf35b96557	6304	/** @brief Macro to Get the SPDIFRX clock.
Kojto	99:dbbf35b96557	6305	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	6306	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	99:dbbf35b96557	6307	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	99:dbbf35b96557	6308	*/
Kojto	99:dbbf35b96557	6309	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
Kojto	99:dbbf35b96557	6310	#endif /* STM32F446xx */
Kojto	110:165afa46840b	6311
Kojto	110:165afa46840b	6312	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	6313
Kojto	110:165afa46840b	6314	/** @brief Macro to configure the CLK48 clock.
Kojto	122:f9eeca106725	6315	* @param __SOURCE__: specifies the CLK48 clock source.
Kojto	110:165afa46840b	6316	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6317	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	6318	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
Kojto	110:165afa46840b	6319	*/
Kojto	110:165afa46840b	6320	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	6321
Kojto	110:165afa46840b	6322	/** @brief Macro to Get the CLK48 clock.
Kojto	110:165afa46840b	6323	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6324	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	6325	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
Kojto	110:165afa46840b	6326	*/
Kojto	110:165afa46840b	6327	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
Kojto	110:165afa46840b	6328
Kojto	110:165afa46840b	6329	/** @brief Macro to configure the SDIO clock.
Kojto	110:165afa46840b	6330	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	110:165afa46840b	6331	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6332	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	110:165afa46840b	6333	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	110:165afa46840b	6334	*/
Kojto	110:165afa46840b	6335	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	6336
Kojto	110:165afa46840b	6337	/** @brief Macro to Get the SDIO clock.
Kojto	110:165afa46840b	6338	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6339	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	110:165afa46840b	6340	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	110:165afa46840b	6341	*/
Kojto	110:165afa46840b	6342	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
Kojto	110:165afa46840b	6343
Kojto	110:165afa46840b	6344	/** @brief Macro to configure the DSI clock.
Kojto	110:165afa46840b	6345	* @param __SOURCE__: specifies the DSI clock source.
Kojto	110:165afa46840b	6346	* This parameter can be one of the following values:
Kojto	110:165afa46840b	6347	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto	110:165afa46840b	6348	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto	110:165afa46840b	6349	*/
Kojto	110:165afa46840b	6350	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	6351
Kojto	110:165afa46840b	6352	/** @brief Macro to Get the DSI clock.
Kojto	110:165afa46840b	6353	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	6354	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto	110:165afa46840b	6355	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto	110:165afa46840b	6356	*/
Kojto	110:165afa46840b	6357	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
Kojto	110:165afa46840b	6358
Kojto	110:165afa46840b	6359	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6360
AnnaBridge	145:64910690c574	6361	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	145:64910690c574	6362	defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	6363	/** @brief Macro to configure the DFSDM1 clock.
Kojto	122:f9eeca106725	6364	* @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
Kojto	122:f9eeca106725	6365	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6366	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
Kojto	122:f9eeca106725	6367	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
Kojto	122:f9eeca106725	6368	* @retval None
Kojto	122:f9eeca106725	6369	*/
Kojto	122:f9eeca106725	6370	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
Kojto	122:f9eeca106725	6371
Kojto	122:f9eeca106725	6372	/** @brief Macro to get the DFSDM1 clock source.
Kojto	122:f9eeca106725	6373	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6374	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
Kojto	122:f9eeca106725	6375	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
Kojto	122:f9eeca106725	6376	*/
Kojto	122:f9eeca106725	6377	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
Kojto	122:f9eeca106725	6378
Kojto	122:f9eeca106725	6379	/** @brief Macro to configure DFSDM1 Audio clock source selection.
AnnaBridge	145:64910690c574	6380	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
AnnaBridge	145:64910690c574	6381	STM32F413xx/STM32F423xx Devices.
Kojto	122:f9eeca106725	6382	* @param __SOURCE__: specifies the DFSDM1 Audio clock source.
Kojto	122:f9eeca106725	6383	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6384	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	145:64910690c574	6385	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
Kojto	122:f9eeca106725	6386	*/
Kojto	122:f9eeca106725	6387	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
Kojto	122:f9eeca106725	6388
Kojto	122:f9eeca106725	6389	/** @brief Macro to Get DFSDM1 Audio clock source selection.
AnnaBridge	145:64910690c574	6390	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
AnnaBridge	145:64910690c574	6391	STM32F413xx/STM32F423xx Devices.
Kojto	122:f9eeca106725	6392	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6393	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	145:64910690c574	6394	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
Kojto	122:f9eeca106725	6395	*/
Kojto	122:f9eeca106725	6396	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
Kojto	122:f9eeca106725	6397
AnnaBridge	145:64910690c574	6398	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	6399	/** @brief Macro to configure the DFSDM2 clock.
AnnaBridge	145:64910690c574	6400	* @param __DFSDM2_CLKSOURCE__: specifies the DFSDM1 clock source.
AnnaBridge	145:64910690c574	6401	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6402	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	145:64910690c574	6403	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	145:64910690c574	6404	* @retval None
AnnaBridge	145:64910690c574	6405	*/
AnnaBridge	145:64910690c574	6406	#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
AnnaBridge	145:64910690c574	6407
AnnaBridge	145:64910690c574	6408	/** @brief Macro to get the DFSDM2 clock source.
AnnaBridge	145:64910690c574	6409	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6410	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	145:64910690c574	6411	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	145:64910690c574	6412	*/
AnnaBridge	145:64910690c574	6413	#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
AnnaBridge	145:64910690c574	6414
AnnaBridge	145:64910690c574	6415	/** @brief Macro to configure DFSDM1 Audio clock source selection.
AnnaBridge	145:64910690c574	6416	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	145:64910690c574	6417	* @param __SOURCE__: specifies the DFSDM2 Audio clock source.
AnnaBridge	145:64910690c574	6418	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6419	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	145:64910690c574	6420	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	145:64910690c574	6421	*/
AnnaBridge	145:64910690c574	6422	#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
AnnaBridge	145:64910690c574	6423
AnnaBridge	145:64910690c574	6424	/** @brief Macro to Get DFSDM2 Audio clock source selection.
AnnaBridge	145:64910690c574	6425	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	145:64910690c574	6426	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6427	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	145:64910690c574	6428	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	145:64910690c574	6429	*/
AnnaBridge	145:64910690c574	6430	#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
AnnaBridge	145:64910690c574	6431
AnnaBridge	145:64910690c574	6432	/** @brief Macro to configure SAI1BlockA clock source selection.
AnnaBridge	145:64910690c574	6433	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	145:64910690c574	6434	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	145:64910690c574	6435	* the SAI clock.
AnnaBridge	145:64910690c574	6436	* @param __SOURCE__: specifies the SAI Block A clock source.
AnnaBridge	145:64910690c574	6437	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6438	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6439	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6440	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6441	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	145:64910690c574	6442	*/
AnnaBridge	145:64910690c574	6443	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
AnnaBridge	145:64910690c574	6444
AnnaBridge	145:64910690c574	6445	/** @brief Macro to Get SAI1 BlockA clock source selection.
AnnaBridge	145:64910690c574	6446	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	145:64910690c574	6447	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6448	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6449	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6450	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6451	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	145:64910690c574	6452	*/
AnnaBridge	145:64910690c574	6453	#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
AnnaBridge	145:64910690c574	6454
AnnaBridge	145:64910690c574	6455	/** @brief Macro to configure SAI1 BlockB clock source selection.
AnnaBridge	145:64910690c574	6456	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	145:64910690c574	6457	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	145:64910690c574	6458	* the SAI clock.
AnnaBridge	145:64910690c574	6459	* @param __SOURCE__: specifies the SAI Block B clock source.
AnnaBridge	145:64910690c574	6460	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6461	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6462	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6463	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6464	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	145:64910690c574	6465	*/
AnnaBridge	145:64910690c574	6466	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
AnnaBridge	145:64910690c574	6467
AnnaBridge	145:64910690c574	6468	/** @brief Macro to Get SAI1 BlockB clock source selection.
AnnaBridge	145:64910690c574	6469	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	145:64910690c574	6470	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6471	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6472	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6473	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	145:64910690c574	6474	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	145:64910690c574	6475	*/
AnnaBridge	145:64910690c574	6476	#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
AnnaBridge	145:64910690c574	6477
AnnaBridge	145:64910690c574	6478	/** @brief Macro to configure the LPTIM1 clock.
AnnaBridge	145:64910690c574	6479	* @param __SOURCE__: specifies the LPTIM1 clock source.
AnnaBridge	145:64910690c574	6480	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6481	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
AnnaBridge	145:64910690c574	6482	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	145:64910690c574	6483	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	145:64910690c574	6484	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	145:64910690c574	6485	*/
AnnaBridge	145:64910690c574	6486	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	145:64910690c574	6487
AnnaBridge	145:64910690c574	6488	/** @brief Macro to Get the LPTIM1 clock.
AnnaBridge	145:64910690c574	6489	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6490	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
AnnaBridge	145:64910690c574	6491	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	145:64910690c574	6492	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	145:64910690c574	6493	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	145:64910690c574	6494	*/
AnnaBridge	145:64910690c574	6495	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
AnnaBridge	145:64910690c574	6496	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	6497
Kojto	122:f9eeca106725	6498	/** @brief Macro to configure I2S APB1 clock source selection.
Kojto	122:f9eeca106725	6499	* @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto	122:f9eeca106725	6500	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6501	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
Kojto	122:f9eeca106725	6502	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	122:f9eeca106725	6503	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
Kojto	122:f9eeca106725	6504	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6505	*/
Kojto	122:f9eeca106725	6506	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto	122:f9eeca106725	6507
Kojto	122:f9eeca106725	6508	/** @brief Macro to Get I2S APB1 clock source selection.
Kojto	122:f9eeca106725	6509	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6510	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
Kojto	122:f9eeca106725	6511	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	122:f9eeca106725	6512	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
Kojto	122:f9eeca106725	6513	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6514	*/
Kojto	122:f9eeca106725	6515	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto	122:f9eeca106725	6516
Kojto	122:f9eeca106725	6517	/** @brief Macro to configure I2S APB2 clock source selection.
Kojto	122:f9eeca106725	6518	* @param __SOURCE__: specifies the I2S APB2 clock source.
Kojto	122:f9eeca106725	6519	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6520	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
Kojto	122:f9eeca106725	6521	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	122:f9eeca106725	6522	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
Kojto	122:f9eeca106725	6523	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6524	*/
Kojto	122:f9eeca106725	6525	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto	122:f9eeca106725	6526
Kojto	122:f9eeca106725	6527	/** @brief Macro to Get I2S APB2 clock source selection.
Kojto	122:f9eeca106725	6528	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6529	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
Kojto	122:f9eeca106725	6530	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	122:f9eeca106725	6531	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
Kojto	122:f9eeca106725	6532	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6533	*/
Kojto	122:f9eeca106725	6534	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto	122:f9eeca106725	6535
Kojto	122:f9eeca106725	6536	/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
Kojto	122:f9eeca106725	6537	* @note This macro must be called before enabling the I2S APB clock.
Kojto	122:f9eeca106725	6538	* @param __SOURCE__: specifies the I2S clock source.
Kojto	122:f9eeca106725	6539	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6540	* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6541	* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	122:f9eeca106725	6542	* used as I2S clock source.
Kojto	122:f9eeca106725	6543	*/
Kojto	122:f9eeca106725	6544	#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
Kojto	122:f9eeca106725	6545
Kojto	122:f9eeca106725	6546	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	122:f9eeca106725	6547	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	122:f9eeca106725	6548	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6549	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6550	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6551	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6552	*/
Kojto	122:f9eeca106725	6553	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	122:f9eeca106725	6554
Kojto	122:f9eeca106725	6555	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	122:f9eeca106725	6556	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6557	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6558	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6559	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6560	*/
Kojto	122:f9eeca106725	6561	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	122:f9eeca106725	6562
Kojto	122:f9eeca106725	6563	/** @brief Macro to configure the CLK48 clock.
Kojto	122:f9eeca106725	6564	* @param __SOURCE__: specifies the CLK48 clock source.
Kojto	122:f9eeca106725	6565	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6566	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	6567	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
Kojto	122:f9eeca106725	6568	*/
Kojto	122:f9eeca106725	6569	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	122:f9eeca106725	6570
Kojto	122:f9eeca106725	6571	/** @brief Macro to Get the CLK48 clock.
Kojto	122:f9eeca106725	6572	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6573	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	6574	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
Kojto	122:f9eeca106725	6575	*/
Kojto	122:f9eeca106725	6576	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto	122:f9eeca106725	6577
Kojto	122:f9eeca106725	6578	/** @brief Macro to configure the SDIO clock.
Kojto	122:f9eeca106725	6579	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	122:f9eeca106725	6580	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6581	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	122:f9eeca106725	6582	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	122:f9eeca106725	6583	*/
Kojto	122:f9eeca106725	6584	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	122:f9eeca106725	6585
Kojto	122:f9eeca106725	6586	/** @brief Macro to Get the SDIO clock.
Kojto	122:f9eeca106725	6587	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6588	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	122:f9eeca106725	6589	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	122:f9eeca106725	6590	*/
Kojto	122:f9eeca106725	6591	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto	122:f9eeca106725	6592
Kojto	122:f9eeca106725	6593	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	6594
Kojto	110:165afa46840b	6595	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	6596	/** @brief Macro to configure I2S clock source selection.
Kojto	110:165afa46840b	6597	* @param __SOURCE__: specifies the I2S clock source.
Kojto	110:165afa46840b	6598	* This parameter can be one of the following values:
Kojto	110:165afa46840b	6599	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
Kojto	110:165afa46840b	6600	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	110:165afa46840b	6601	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
Kojto	110:165afa46840b	6602	*/
Kojto	110:165afa46840b	6603	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
Kojto	110:165afa46840b	6604
Kojto	110:165afa46840b	6605	/** @brief Macro to Get I2S clock source selection.
Kojto	110:165afa46840b	6606	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	6607	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
Kojto	110:165afa46840b	6608	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	110:165afa46840b	6609	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
Kojto	110:165afa46840b	6610	*/
Kojto	110:165afa46840b	6611	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
Kojto	110:165afa46840b	6612
Kojto	110:165afa46840b	6613	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	110:165afa46840b	6614	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	110:165afa46840b	6615	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6616	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
Kojto	110:165afa46840b	6617	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	6618	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	110:165afa46840b	6619	*/
Kojto	110:165afa46840b	6620	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	6621
Kojto	110:165afa46840b	6622	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	110:165afa46840b	6623	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6624	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
Kojto	110:165afa46840b	6625	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	6626	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	110:165afa46840b	6627	*/
Kojto	110:165afa46840b	6628	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	110:165afa46840b	6629
Kojto	110:165afa46840b	6630	/** @brief Macro to configure the LPTIM1 clock.
Kojto	110:165afa46840b	6631	* @param __SOURCE__: specifies the LPTIM1 clock source.
Kojto	110:165afa46840b	6632	* This parameter can be one of the following values:
AnnaBridge	145:64910690c574	6633	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
Kojto	110:165afa46840b	6634	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
Kojto	110:165afa46840b	6635	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	110:165afa46840b	6636	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	110:165afa46840b	6637	*/
Kojto	110:165afa46840b	6638	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	6639
Kojto	110:165afa46840b	6640	/** @brief Macro to Get the LPTIM1 clock.
Kojto	110:165afa46840b	6641	* @retval The clock source can be one of the following values:
AnnaBridge	145:64910690c574	6642	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
Kojto	110:165afa46840b	6643	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
Kojto	110:165afa46840b	6644	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	110:165afa46840b	6645	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	110:165afa46840b	6646	*/
Kojto	110:165afa46840b	6647	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
Kojto	110:165afa46840b	6648	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	6649
Kojto	110:165afa46840b	6650	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	6651	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
Kojto	110:165afa46840b	6652	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	122:f9eeca106725	6653	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	145:64910690c574	6654	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
bogdanm	89:552587b429a1	6655	/** @brief Macro to configure the Timers clocks prescalers
bogdanm	89:552587b429a1	6656	* @note This feature is only available with STM32F429x/439x Devices.
bogdanm	89:552587b429a1	6657	* @param __PRESC__ : specifies the Timers clocks prescalers selection
bogdanm	89:552587b429a1	6658	* This parameter can be one of the following values:
bogdanm	89:552587b429a1	6659	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
bogdanm	89:552587b429a1	6660	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
bogdanm	89:552587b429a1	6661	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
bogdanm	89:552587b429a1	6662	* division by 4 or more.
bogdanm	89:552587b429a1	6663	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
bogdanm	89:552587b429a1	6664	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
bogdanm	89:552587b429a1	6665	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
bogdanm	89:552587b429a1	6666	* to division by 8 or more.
bogdanm	89:552587b429a1	6667	*/
Kojto	99:dbbf35b96557	6668	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
bogdanm	92:4fc01daae5a5	6669
Kojto	110:165afa46840b	6670	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
AnnaBridge	145:64910690c574	6671	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\|\
AnnaBridge	145:64910690c574	6672	STM32F423xx */
Kojto	110:165afa46840b	6673
Kojto	110:165afa46840b	6674	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	6675
Kojto	110:165afa46840b	6676	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	89:552587b429a1	6677	/** @brief Enable PLLSAI_RDY interrupt.
bogdanm	89:552587b429a1	6678	*/
bogdanm	89:552587b429a1	6679	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
bogdanm	89:552587b429a1	6680
bogdanm	89:552587b429a1	6681	/** @brief Disable PLLSAI_RDY interrupt.
bogdanm	89:552587b429a1	6682	*/
bogdanm	89:552587b429a1	6683	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
bogdanm	89:552587b429a1	6684
bogdanm	89:552587b429a1	6685	/** @brief Clear the PLLSAI RDY interrupt pending bits.
bogdanm	89:552587b429a1	6686	*/
bogdanm	89:552587b429a1	6687	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
bogdanm	89:552587b429a1	6688
bogdanm	89:552587b429a1	6689	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
bogdanm	89:552587b429a1	6690	* @retval The new state (TRUE or FALSE).
bogdanm	89:552587b429a1	6691	*/
bogdanm	89:552587b429a1	6692	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
bogdanm	89:552587b429a1	6693
bogdanm	89:552587b429a1	6694	/** @brief Check PLLSAI RDY flag is set or not.
bogdanm	89:552587b429a1	6695	* @retval The new state (TRUE or FALSE).
bogdanm	89:552587b429a1	6696	*/
bogdanm	89:552587b429a1	6697	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
bogdanm	89:552587b429a1	6698
Kojto	110:165afa46840b	6699	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6700
Kojto	110:165afa46840b	6701	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	122:f9eeca106725	6702	/** @brief Macros to enable or disable the RCC MCO1 feature.
Kojto	110:165afa46840b	6703	*/
Kojto	110:165afa46840b	6704	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
Kojto	110:165afa46840b	6705	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
Kojto	122:f9eeca106725	6706
Kojto	122:f9eeca106725	6707	/** @brief Macros to enable or disable the RCC MCO2 feature.
Kojto	110:165afa46840b	6708	*/
Kojto	110:165afa46840b	6709	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
Kojto	110:165afa46840b	6710	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
Kojto	122:f9eeca106725	6711
Kojto	110:165afa46840b	6712	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	6713
Kojto	99:dbbf35b96557	6714	/**
Kojto	99:dbbf35b96557	6715	* @}
Kojto	99:dbbf35b96557	6716	*/
bogdanm	89:552587b429a1	6717
bogdanm	89:552587b429a1	6718	/* Exported functions --------------------------------------------------------*/
Kojto	99:dbbf35b96557	6719	/** @addtogroup RCCEx_Exported_Functions
Kojto	99:dbbf35b96557	6720	* @{
Kojto	99:dbbf35b96557	6721	*/
Kojto	99:dbbf35b96557	6722
Kojto	99:dbbf35b96557	6723	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	99:dbbf35b96557	6724	* @{
Kojto	99:dbbf35b96557	6725	*/
bogdanm	89:552587b429a1	6726	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	89:552587b429a1	6727	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	89:552587b429a1	6728
Kojto	99:dbbf35b96557	6729	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto	99:dbbf35b96557	6730
Kojto	110:165afa46840b	6731	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
Kojto	122:f9eeca106725	6732	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
AnnaBridge	145:64910690c574	6733	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
AnnaBridge	145:64910690c574	6734	defined(STM32F423xx)
bogdanm	92:4fc01daae5a5	6735	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
AnnaBridge	145:64910690c574	6736	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
bogdanm	89:552587b429a1	6737	/**
bogdanm	89:552587b429a1	6738	* @}
bogdanm	89:552587b429a1	6739	*/
bogdanm	89:552587b429a1	6740
bogdanm	89:552587b429a1	6741	/**
bogdanm	89:552587b429a1	6742	* @}
bogdanm	89:552587b429a1	6743	*/
Kojto	99:dbbf35b96557	6744	/* Private types -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	6745	/* Private variables ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	6746	/* Private constants ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	6747	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
Kojto	99:dbbf35b96557	6748	* @{
Kojto	99:dbbf35b96557	6749	*/
Kojto	99:dbbf35b96557	6750
Kojto	99:dbbf35b96557	6751	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	99:dbbf35b96557	6752	* @brief RCC registers bit address in the alias region
Kojto	99:dbbf35b96557	6753	* @{
Kojto	99:dbbf35b96557	6754	*/
Kojto	99:dbbf35b96557	6755	/* --- CR Register ---*/
Kojto	110:165afa46840b	6756	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	6757	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	6758	/* Alias word address of PLLSAION bit */
AnnaBridge	145:64910690c574	6759	#define RCC_PLLSAION_BIT_NUMBER 0x1CU
AnnaBridge	145:64910690c574	6760	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
AnnaBridge	145:64910690c574	6761
AnnaBridge	145:64910690c574	6762	#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
Kojto	110:165afa46840b	6763	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6764
Kojto	110:165afa46840b	6765	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	6766	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	6767	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	6768	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	145:64910690c574	6769	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	110:165afa46840b	6770	/* Alias word address of PLLI2SON bit */
AnnaBridge	145:64910690c574	6771	#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
AnnaBridge	145:64910690c574	6772	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
Kojto	110:165afa46840b	6773	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	6774	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	145:64910690c574	6775	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	110:165afa46840b	6776
Kojto	99:dbbf35b96557	6777	/* --- DCKCFGR Register ---*/
Kojto	110:165afa46840b	6778	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	122:f9eeca106725	6779	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F401xC) \|\|\
Kojto	122:f9eeca106725	6780	defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	122:f9eeca106725	6781	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	145:64910690c574	6782	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	99:dbbf35b96557	6783	/* Alias word address of TIMPRE bit */
AnnaBridge	145:64910690c574	6784	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
AnnaBridge	145:64910690c574	6785	#define RCC_TIMPRE_BIT_NUMBER 0x18U
AnnaBridge	145:64910690c574	6786	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
Kojto	122:f9eeca106725	6787	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F401xC \|\|\
Kojto	122:f9eeca106725	6788	STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
AnnaBridge	145:64910690c574	6789	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	110:165afa46840b	6790
Kojto	110:165afa46840b	6791	/* --- CFGR Register ---*/
Kojto	122:f9eeca106725	6792	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
Kojto	110:165afa46840b	6793	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	6794	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	6795	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	6796	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	6797	/* Alias word address of I2SSRC bit */
AnnaBridge	145:64910690c574	6798	#define RCC_I2SSRC_BIT_NUMBER 0x17U
AnnaBridge	145:64910690c574	6799	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
Kojto	110:165afa46840b	6800
AnnaBridge	145:64910690c574	6801	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
Kojto	110:165afa46840b	6802	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	6803	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	6804
AnnaBridge	145:64910690c574	6805	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	145:64910690c574	6806	defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	122:f9eeca106725	6807	/* --- PLLI2SCFGR Register ---*/
AnnaBridge	145:64910690c574	6808	#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
Kojto	122:f9eeca106725	6809	/* Alias word address of PLLI2SSRC bit */
AnnaBridge	145:64910690c574	6810	#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
AnnaBridge	145:64910690c574	6811	#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
Kojto	122:f9eeca106725	6812
AnnaBridge	145:64910690c574	6813	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
AnnaBridge	145:64910690c574	6814	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \| STM32F423xx */
Kojto	110:165afa46840b	6815
Kojto	110:165afa46840b	6816	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	6817	/* Alias word address of MCO1EN bit */
AnnaBridge	145:64910690c574	6818	#define RCC_MCO1EN_BIT_NUMBER 0x8U
AnnaBridge	145:64910690c574	6819	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
Kojto	110:165afa46840b	6820
Kojto	110:165afa46840b	6821	/* Alias word address of MCO2EN bit */
AnnaBridge	145:64910690c574	6822	#define RCC_MCO2EN_BIT_NUMBER 0x9U
AnnaBridge	145:64910690c574	6823	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
Kojto	110:165afa46840b	6824	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	6825
AnnaBridge	145:64910690c574	6826	#define PLL_TIMEOUT_VALUE 2U /* 2 ms */
Kojto	99:dbbf35b96557	6827	/**
Kojto	99:dbbf35b96557	6828	* @}
Kojto	99:dbbf35b96557	6829	*/
Kojto	99:dbbf35b96557	6830
Kojto	99:dbbf35b96557	6831	/**
Kojto	99:dbbf35b96557	6832	* @}
Kojto	99:dbbf35b96557	6833	*/
Kojto	99:dbbf35b96557	6834
Kojto	99:dbbf35b96557	6835	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	6836	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	99:dbbf35b96557	6837	* @{
Kojto	99:dbbf35b96557	6838	*/
Kojto	99:dbbf35b96557	6839	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	99:dbbf35b96557	6840	* @{
Kojto	99:dbbf35b96557	6841	*/
Kojto	122:f9eeca106725	6842	#if defined(STM32F411xE)
Kojto	122:f9eeca106725	6843	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6844	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6845	#else /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|
Kojto	122:f9eeca106725	6846	STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410Tx \|\| STM32F410Cx \|\|
Kojto	122:f9eeca106725	6847	STM32F410Rx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Cx \|\| STM32F412Rx \|\|
AnnaBridge	145:64910690c574	6848	STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	6849	#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6850	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6851	#endif /* STM32F411xE */
Kojto	122:f9eeca106725	6852
Kojto	99:dbbf35b96557	6853	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
AnnaBridge	145:64910690c574	6854	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
Kojto	99:dbbf35b96557	6855	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	6856
Kojto	122:f9eeca106725	6857	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	145:64910690c574	6858	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
Kojto	122:f9eeca106725	6859	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
Kojto	122:f9eeca106725	6860
Kojto	122:f9eeca106725	6861	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	145:64910690c574	6862	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
Kojto	122:f9eeca106725	6863	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	6864
Kojto	110:165afa46840b	6865	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	145:64910690c574	6866	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
Kojto	110:165afa46840b	6867	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	6868
Kojto	99:dbbf35b96557	6869	#if defined(STM32F446xx)
AnnaBridge	145:64910690c574	6870	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
Kojto	99:dbbf35b96557	6871	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	6872
Kojto	122:f9eeca106725	6873	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	145:64910690c574	6874	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
Kojto	122:f9eeca106725	6875	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	6876
Kojto	122:f9eeca106725	6877	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
AnnaBridge	145:64910690c574	6878	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
Kojto	122:f9eeca106725	6879	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	145:64910690c574	6880
AnnaBridge	145:64910690c574	6881	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	6882	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
AnnaBridge	145:64910690c574	6883	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	6884
Kojto	122:f9eeca106725	6885	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	99:dbbf35b96557	6886
Kojto	110:165afa46840b	6887	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	6888	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	6889	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
Kojto	122:f9eeca106725	6890
Kojto	122:f9eeca106725	6891	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6892
Kojto	122:f9eeca106725	6893	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
Kojto	122:f9eeca106725	6894
Kojto	122:f9eeca106725	6895	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	122:f9eeca106725	6896
Kojto	122:f9eeca106725	6897	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
Kojto	122:f9eeca106725	6898
Kojto	122:f9eeca106725	6899	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
Kojto	99:dbbf35b96557	6900
Kojto	99:dbbf35b96557	6901	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
Kojto	99:dbbf35b96557	6902	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
Kojto	99:dbbf35b96557	6903	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
Kojto	99:dbbf35b96557	6904	((VALUE) == RCC_PLLSAIDIVR_16))
Kojto	110:165afa46840b	6905	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6906
Kojto	122:f9eeca106725	6907	#if defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	145:64910690c574	6908	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	6909	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
Kojto	99:dbbf35b96557	6910
Kojto	99:dbbf35b96557	6911	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	99:dbbf35b96557	6912	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
AnnaBridge	145:64910690c574	6913	#endif /* STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	110:165afa46840b	6914
Kojto	110:165afa46840b	6915	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	122:f9eeca106725	6916	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	110:165afa46840b	6917
Kojto	110:165afa46840b	6918	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	110:165afa46840b	6919	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	110:165afa46840b	6920
AnnaBridge	145:64910690c574	6921	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
Kojto	110:165afa46840b	6922	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	110:165afa46840b	6923	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	110:165afa46840b	6924
AnnaBridge	145:64910690c574	6925	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
Kojto	110:165afa46840b	6926	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
Kojto	110:165afa46840b	6927	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
Kojto	110:165afa46840b	6928	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto	110:165afa46840b	6929
Kojto	110:165afa46840b	6930	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
Kojto	110:165afa46840b	6931	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
Kojto	110:165afa46840b	6932	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
Kojto	110:165afa46840b	6933	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	6934
Kojto	99:dbbf35b96557	6935	#if defined(STM32F446xx)
Kojto	122:f9eeca106725	6936	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
bogdanm	89:552587b429a1	6937
Kojto	99:dbbf35b96557	6938	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
Kojto	99:dbbf35b96557	6939	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
Kojto	99:dbbf35b96557	6940	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
Kojto	99:dbbf35b96557	6941	((VALUE) == RCC_PLLI2SP_DIV8))
Kojto	99:dbbf35b96557	6942
Kojto	122:f9eeca106725	6943	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
Kojto	99:dbbf35b96557	6944
Kojto	99:dbbf35b96557	6945	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	99:dbbf35b96557	6946	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	99:dbbf35b96557	6947	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	99:dbbf35b96557	6948	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	99:dbbf35b96557	6949
Kojto	99:dbbf35b96557	6950	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
Kojto	99:dbbf35b96557	6951	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	6952	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6953	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
Kojto	99:dbbf35b96557	6954
Kojto	99:dbbf35b96557	6955	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
Kojto	99:dbbf35b96557	6956	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	6957	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6958	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	6959
Kojto	99:dbbf35b96557	6960	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	6961	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
Kojto	99:dbbf35b96557	6962	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6963	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	6964
Kojto	99:dbbf35b96557	6965	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	6966	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
Kojto	99:dbbf35b96557	6967	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6968	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	6969
AnnaBridge	145:64910690c574	6970	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
Kojto	99:dbbf35b96557	6971	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	99:dbbf35b96557	6972	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	99:dbbf35b96557	6973
Kojto	99:dbbf35b96557	6974	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
Kojto	99:dbbf35b96557	6975	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	99:dbbf35b96557	6976
Kojto	122:f9eeca106725	6977	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
Kojto	122:f9eeca106725	6978	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
Kojto	122:f9eeca106725	6979
Kojto	122:f9eeca106725	6980	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
Kojto	99:dbbf35b96557	6981	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	99:dbbf35b96557	6982
Kojto	110:165afa46840b	6983	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6984	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
Kojto	110:165afa46840b	6985	#endif /* STM32F446xx */
Kojto	110:165afa46840b	6986
Kojto	110:165afa46840b	6987	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	6988	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	110:165afa46840b	6989
Kojto	110:165afa46840b	6990	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	110:165afa46840b	6991	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	110:165afa46840b	6992	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	110:165afa46840b	6993	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	110:165afa46840b	6994
Kojto	122:f9eeca106725	6995	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
Kojto	122:f9eeca106725	6996	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
Kojto	122:f9eeca106725	6997
Kojto	122:f9eeca106725	6998	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
Kojto	110:165afa46840b	6999	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	110:165afa46840b	7000
Kojto	110:165afa46840b	7001	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
Kojto	110:165afa46840b	7002	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
Kojto	110:165afa46840b	7003
Kojto	110:165afa46840b	7004	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	110:165afa46840b	7005	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	110:165afa46840b	7006	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	7007
AnnaBridge	145:64910690c574	7008	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	145:64910690c574	7009	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	7010	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge	145:64910690c574	7011
Kojto	122:f9eeca106725	7012	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	122:f9eeca106725	7013
Kojto	122:f9eeca106725	7014	#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) \|\| \
Kojto	122:f9eeca106725	7015	((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
Kojto	122:f9eeca106725	7016
Kojto	122:f9eeca106725	7017	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
Kojto	122:f9eeca106725	7018	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
Kojto	122:f9eeca106725	7019	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
Kojto	122:f9eeca106725	7020	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto	122:f9eeca106725	7021
Kojto	122:f9eeca106725	7022	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
Kojto	122:f9eeca106725	7023	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
Kojto	122:f9eeca106725	7024	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
Kojto	122:f9eeca106725	7025	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto	122:f9eeca106725	7026
AnnaBridge	145:64910690c574	7027	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
Kojto	122:f9eeca106725	7028	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	122:f9eeca106725	7029	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	122:f9eeca106725	7030
Kojto	122:f9eeca106725	7031	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
Kojto	122:f9eeca106725	7032	((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
Kojto	122:f9eeca106725	7033
Kojto	122:f9eeca106725	7034	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
Kojto	122:f9eeca106725	7035	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	122:f9eeca106725	7036
AnnaBridge	145:64910690c574	7037	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) \|\| \
Kojto	122:f9eeca106725	7038	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
Kojto	122:f9eeca106725	7039
AnnaBridge	145:64910690c574	7040	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) \|\| \
AnnaBridge	145:64910690c574	7041	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
AnnaBridge	145:64910690c574	7042
AnnaBridge	145:64910690c574	7043	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	145:64910690c574	7044	#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) \|\| \
AnnaBridge	145:64910690c574	7045	((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
AnnaBridge	145:64910690c574	7046
AnnaBridge	145:64910690c574	7047	#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) \|\| \
AnnaBridge	145:64910690c574	7048	((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
AnnaBridge	145:64910690c574	7049
AnnaBridge	145:64910690c574	7050	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	145:64910690c574	7051	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
AnnaBridge	145:64910690c574	7052	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
AnnaBridge	145:64910690c574	7053	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge	145:64910690c574	7054
AnnaBridge	145:64910690c574	7055	#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) \|\|\
AnnaBridge	145:64910690c574	7056	((SOURCE) == RCC_SAIACLKSOURCE_EXT) \|\|\
AnnaBridge	145:64910690c574	7057	((SOURCE) == RCC_SAIACLKSOURCE_PLLR) \|\|\
AnnaBridge	145:64910690c574	7058	((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
AnnaBridge	145:64910690c574	7059
AnnaBridge	145:64910690c574	7060	#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) \|\|\
AnnaBridge	145:64910690c574	7061	((SOURCE) == RCC_SAIBCLKSOURCE_EXT) \|\|\
AnnaBridge	145:64910690c574	7062	((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) \|\|\
AnnaBridge	145:64910690c574	7063	((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
AnnaBridge	145:64910690c574	7064
AnnaBridge	145:64910690c574	7065	#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	145:64910690c574	7066
AnnaBridge	145:64910690c574	7067	#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	145:64910690c574	7068
AnnaBridge	145:64910690c574	7069	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	145:64910690c574	7070	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Kojto	122:f9eeca106725	7071
Kojto	110:165afa46840b	7072	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	7073	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	7074	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	7075	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	145:64910690c574	7076	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Kojto	110:165afa46840b	7077
Kojto	110:165afa46840b	7078	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
Kojto	110:165afa46840b	7079	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	110:165afa46840b	7080
Kojto	110:165afa46840b	7081	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	7082	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| \
Kojto	122:f9eeca106725	7083	STM32F412Rx */
Kojto	110:165afa46840b	7084
Kojto	110:165afa46840b	7085	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	7086	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
Kojto	110:165afa46840b	7087	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	110:165afa46840b	7088	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	7089	/**
Kojto	99:dbbf35b96557	7090	* @}
Kojto	99:dbbf35b96557	7091	*/
Kojto	99:dbbf35b96557	7092
Kojto	99:dbbf35b96557	7093	/**
Kojto	99:dbbf35b96557	7094	* @}
Kojto	99:dbbf35b96557	7095	*/
Kojto	99:dbbf35b96557	7096
Kojto	99:dbbf35b96557	7097	/**
Kojto	99:dbbf35b96557	7098	* @}
Kojto	99:dbbf35b96557	7099	*/
Kojto	99:dbbf35b96557	7100
Kojto	99:dbbf35b96557	7101	/**
Kojto	99:dbbf35b96557	7102	* @}
Kojto	99:dbbf35b96557	7103	*/
bogdanm	89:552587b429a1	7104	#ifdef __cplusplus
bogdanm	89:552587b429a1	7105	}
bogdanm	89:552587b429a1	7106	#endif
bogdanm	89:552587b429a1	7107
bogdanm	89:552587b429a1	7108	#endif /* __STM32F4xx_HAL_RCC_EX_H */
bogdanm	89:552587b429a1	7109
bogdanm	89:552587b429a1	7110	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/