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TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Parent:
128:9bcdf88f62b0 
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_sram.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 14-April-2017
bogdanm 89:552587b429a1 7 * @brief Header file of SRAM HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
AnnaBridge 145:64910690c574 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_SRAM_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_SRAM_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 145:64910690c574 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
AnnaBridge 145:64910690c574 48 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
bogdanm 89:552587b429a1 49 #include "stm32f4xx_ll_fsmc.h"
AnnaBridge 145:64910690c574 50 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
bogdanm 89:552587b429a1 51
Kojto 110:165afa46840b 52 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
Kojto 110:165afa46840b 53 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 89:552587b429a1 54 #include "stm32f4xx_ll_fmc.h"
Kojto 110:165afa46840b 55 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57
bogdanm 89:552587b429a1 58 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 59 * @{
bogdanm 89:552587b429a1 60 */
bogdanm 89:552587b429a1 61
Kojto 99:dbbf35b96557 62 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
Kojto 99:dbbf35b96557 63 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 122:f9eeca106725 64 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
AnnaBridge 145:64910690c574 65 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
Kojto 110:165afa46840b 66
bogdanm 89:552587b429a1 67 /** @addtogroup SRAM
bogdanm 89:552587b429a1 68 * @{
bogdanm 89:552587b429a1 69 */
bogdanm 89:552587b429a1 70
bogdanm 89:552587b429a1 71 /* Exported typedef ----------------------------------------------------------*/
bogdanm 89:552587b429a1 72
Kojto 99:dbbf35b96557 73 /** @defgroup SRAM_Exported_Types SRAM Exported Types
Kojto 99:dbbf35b96557 74 * @{
Kojto 99:dbbf35b96557 75 */
bogdanm 89:552587b429a1 76 /**
bogdanm 89:552587b429a1 77 * @brief HAL SRAM State structures definition
bogdanm 89:552587b429a1 78 */
bogdanm 89:552587b429a1 79 typedef enum
bogdanm 89:552587b429a1 80 {
Kojto 122:f9eeca106725 81 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
Kojto 122:f9eeca106725 82 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
Kojto 122:f9eeca106725 83 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
Kojto 122:f9eeca106725 84 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
Kojto 122:f9eeca106725 85 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
bogdanm 89:552587b429a1 86
bogdanm 89:552587b429a1 87 }HAL_SRAM_StateTypeDef;
bogdanm 89:552587b429a1 88
bogdanm 89:552587b429a1 89 /**
bogdanm 89:552587b429a1 90 * @brief SRAM handle Structure definition
bogdanm 89:552587b429a1 91 */
bogdanm 89:552587b429a1 92 typedef struct
bogdanm 89:552587b429a1 93 {
bogdanm 89:552587b429a1 94 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
bogdanm 89:552587b429a1 95
bogdanm 89:552587b429a1 96 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
bogdanm 89:552587b429a1 97
bogdanm 89:552587b429a1 98 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
bogdanm 89:552587b429a1 99
bogdanm 89:552587b429a1 100 HAL_LockTypeDef Lock; /*!< SRAM locking object */
bogdanm 89:552587b429a1 101
bogdanm 89:552587b429a1 102 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
bogdanm 89:552587b429a1 103
bogdanm 89:552587b429a1 104 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
bogdanm 89:552587b429a1 105
bogdanm 89:552587b429a1 106 }SRAM_HandleTypeDef;
bogdanm 89:552587b429a1 107
Kojto 99:dbbf35b96557 108 /**
Kojto 99:dbbf35b96557 109 * @}
Kojto 99:dbbf35b96557 110 */
Kojto 99:dbbf35b96557 111
bogdanm 89:552587b429a1 112 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 113 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 114
Kojto 99:dbbf35b96557 115 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
Kojto 99:dbbf35b96557 116 * @{
Kojto 99:dbbf35b96557 117 */
bogdanm 89:552587b429a1 118 /** @brief Reset SRAM handle state
bogdanm 89:552587b429a1 119 * @param __HANDLE__: SRAM handle
bogdanm 89:552587b429a1 120 * @retval None
bogdanm 89:552587b429a1 121 */
bogdanm 89:552587b429a1 122 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
bogdanm 89:552587b429a1 123
Kojto 99:dbbf35b96557 124 /**
Kojto 99:dbbf35b96557 125 * @}
Kojto 99:dbbf35b96557 126 */
bogdanm 89:552587b429a1 127 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 128
Kojto 99:dbbf35b96557 129 /** @addtogroup SRAM_Exported_Functions
Kojto 99:dbbf35b96557 130 * @{
Kojto 99:dbbf35b96557 131 */
Kojto 99:dbbf35b96557 132
Kojto 99:dbbf35b96557 133 /** @addtogroup SRAM_Exported_Functions_Group1
Kojto 99:dbbf35b96557 134 * @{
Kojto 99:dbbf35b96557 135 */
bogdanm 89:552587b429a1 136 /* Initialization/de-initialization functions **********************************/
bogdanm 89:552587b429a1 137 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
bogdanm 89:552587b429a1 138 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
Kojto 99:dbbf35b96557 139 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
Kojto 99:dbbf35b96557 140 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
bogdanm 89:552587b429a1 141
Kojto 99:dbbf35b96557 142 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 143 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 144 /**
Kojto 99:dbbf35b96557 145 * @}
Kojto 99:dbbf35b96557 146 */
Kojto 99:dbbf35b96557 147
Kojto 99:dbbf35b96557 148 /** @addtogroup SRAM_Exported_Functions_Group2
Kojto 99:dbbf35b96557 149 * @{
Kojto 99:dbbf35b96557 150 */
bogdanm 89:552587b429a1 151 /* I/O operation functions *****************************************************/
bogdanm 89:552587b429a1 152 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 153 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 154 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 155 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 156 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 157 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 158 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 159 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
Kojto 99:dbbf35b96557 160 /**
Kojto 99:dbbf35b96557 161 * @}
Kojto 99:dbbf35b96557 162 */
bogdanm 89:552587b429a1 163
Kojto 99:dbbf35b96557 164 /** @addtogroup SRAM_Exported_Functions_Group3
Kojto 99:dbbf35b96557 165 * @{
Kojto 99:dbbf35b96557 166 */
bogdanm 89:552587b429a1 167 /* SRAM Control functions ******************************************************/
bogdanm 89:552587b429a1 168 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
bogdanm 89:552587b429a1 169 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
bogdanm 89:552587b429a1 170 /**
bogdanm 89:552587b429a1 171 * @}
bogdanm 89:552587b429a1 172 */
bogdanm 89:552587b429a1 173
Kojto 99:dbbf35b96557 174 /** @addtogroup SRAM_Exported_Functions_Group4
Kojto 99:dbbf35b96557 175 * @{
Kojto 99:dbbf35b96557 176 */
Kojto 99:dbbf35b96557 177 /* SRAM State functions *********************************************************/
Kojto 99:dbbf35b96557 178 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
Kojto 99:dbbf35b96557 179 /**
Kojto 99:dbbf35b96557 180 * @}
Kojto 99:dbbf35b96557 181 */
Kojto 99:dbbf35b96557 182
bogdanm 89:552587b429a1 183 /**
bogdanm 89:552587b429a1 184 * @}
bogdanm 89:552587b429a1 185 */
Kojto 99:dbbf35b96557 186
Kojto 99:dbbf35b96557 187 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 188 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 189 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 190 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 191 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 192 /**
Kojto 99:dbbf35b96557 193 * @}
Kojto 99:dbbf35b96557 194 */
Kojto 99:dbbf35b96557 195
Kojto 110:165afa46840b 196 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
Kojto 122:f9eeca106725 197 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
AnnaBridge 145:64910690c574 198 STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
Kojto 99:dbbf35b96557 199 /**
Kojto 99:dbbf35b96557 200 * @}
Kojto 99:dbbf35b96557 201 */
bogdanm 89:552587b429a1 202 #ifdef __cplusplus
bogdanm 89:552587b429a1 203 }
bogdanm 89:552587b429a1 204 #endif
bogdanm 89:552587b429a1 205
bogdanm 89:552587b429a1 206 #endif /* __STM32F4xx_HAL_SRAM_H */
bogdanm 89:552587b429a1 207
bogdanm 89:552587b429a1 208 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/