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TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Child:: 161:aa5281ff4a02

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32l4xx_ll_dma.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.7.1
AnnaBridge	145:64910690c574	6	* @date 21-April-2017
AnnaBridge	145:64910690c574	7	* @brief Header file of DMA LL module.
AnnaBridge	145:64910690c574	8	******************************************************************************
AnnaBridge	145:64910690c574	9	* @attention
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	12	*
AnnaBridge	145:64910690c574	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	14	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	16	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	19	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	21	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	22	* without specific prior written permission.
AnnaBridge	145:64910690c574	23	*
AnnaBridge	145:64910690c574	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	34	*
AnnaBridge	145:64910690c574	35	******************************************************************************
AnnaBridge	145:64910690c574	36	*/
AnnaBridge	145:64910690c574	37
AnnaBridge	145:64910690c574	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	39	#ifndef __STM32L4xx_LL_DMA_H
AnnaBridge	145:64910690c574	40	#define __STM32L4xx_LL_DMA_H
AnnaBridge	145:64910690c574	41
AnnaBridge	145:64910690c574	42	#ifdef __cplusplus
AnnaBridge	145:64910690c574	43	extern "C" {
AnnaBridge	145:64910690c574	44	#endif
AnnaBridge	145:64910690c574	45
AnnaBridge	145:64910690c574	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	47	#include "stm32l4xx.h"
AnnaBridge	145:64910690c574	48
AnnaBridge	145:64910690c574	49	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	145:64910690c574	50	* @{
AnnaBridge	145:64910690c574	51	*/
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	145:64910690c574	54
AnnaBridge	145:64910690c574	55	/** @defgroup DMA_LL DMA
AnnaBridge	145:64910690c574	56	* @{
AnnaBridge	145:64910690c574	57	*/
AnnaBridge	145:64910690c574	58
AnnaBridge	145:64910690c574	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	145:64910690c574	62	* @{
AnnaBridge	145:64910690c574	63	*/
AnnaBridge	145:64910690c574	64	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge	145:64910690c574	65	static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge	145:64910690c574	66	{
AnnaBridge	145:64910690c574	67	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	68	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	69	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	70	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	71	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	72	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	73	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge	145:64910690c574	74	};
AnnaBridge	145:64910690c574	75	/**
AnnaBridge	145:64910690c574	76	* @}
AnnaBridge	145:64910690c574	77	*/
AnnaBridge	145:64910690c574	78
AnnaBridge	145:64910690c574	79	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	145:64910690c574	81	* @{
AnnaBridge	145:64910690c574	82	*/
AnnaBridge	145:64910690c574	83	/* Define used to get CSELR register offset */
AnnaBridge	145:64910690c574	84	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
AnnaBridge	145:64910690c574	85
AnnaBridge	145:64910690c574	86	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	145:64910690c574	87	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
AnnaBridge	145:64910690c574	88	/**
AnnaBridge	145:64910690c574	89	* @}
AnnaBridge	145:64910690c574	90	*/
AnnaBridge	145:64910690c574	91
AnnaBridge	145:64910690c574	92	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	93	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	94	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	145:64910690c574	95	* @{
AnnaBridge	145:64910690c574	96	*/
AnnaBridge	145:64910690c574	97	/**
AnnaBridge	145:64910690c574	98	* @}
AnnaBridge	145:64910690c574	99	*/
AnnaBridge	145:64910690c574	100	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	145:64910690c574	101
AnnaBridge	145:64910690c574	102	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	103	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	104	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	145:64910690c574	105	* @{
AnnaBridge	145:64910690c574	106	*/
AnnaBridge	145:64910690c574	107	typedef struct
AnnaBridge	145:64910690c574	108	{
AnnaBridge	145:64910690c574	109	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	145:64910690c574	110	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	145:64910690c574	111
AnnaBridge	145:64910690c574	112	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	145:64910690c574	113
AnnaBridge	145:64910690c574	114	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	145:64910690c574	115	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	145:64910690c574	116
AnnaBridge	145:64910690c574	117	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	145:64910690c574	118
AnnaBridge	145:64910690c574	119	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	145:64910690c574	120	from memory to memory or from peripheral to memory.
AnnaBridge	145:64910690c574	121	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	145:64910690c574	122
AnnaBridge	145:64910690c574	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	145:64910690c574	124
AnnaBridge	145:64910690c574	125	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	145:64910690c574	126	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	145:64910690c574	127	@note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge	145:64910690c574	128	data transfer direction is configured on the selected Channel
AnnaBridge	145:64910690c574	129
AnnaBridge	145:64910690c574	130	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	145:64910690c574	131
AnnaBridge	145:64910690c574	132	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	145:64910690c574	133	is incremented or not.
AnnaBridge	145:64910690c574	134	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	145:64910690c574	135
AnnaBridge	145:64910690c574	136	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	145:64910690c574	137
AnnaBridge	145:64910690c574	138	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	145:64910690c574	139	is incremented or not.
AnnaBridge	145:64910690c574	140	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	145:64910690c574	141
AnnaBridge	145:64910690c574	142	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	145:64910690c574	143
AnnaBridge	145:64910690c574	144	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	145:64910690c574	145	in case of memory to memory transfer direction.
AnnaBridge	145:64910690c574	146	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	145:64910690c574	147
AnnaBridge	145:64910690c574	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	145:64910690c574	149
AnnaBridge	145:64910690c574	150	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	145:64910690c574	151	in case of memory to memory transfer direction.
AnnaBridge	145:64910690c574	152	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	145:64910690c574	153
AnnaBridge	145:64910690c574	154	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	145:64910690c574	155
AnnaBridge	145:64910690c574	156	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	145:64910690c574	157	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	145:64910690c574	158	or MemorySize parameters depending in the transfer direction.
AnnaBridge	145:64910690c574	159	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	145:64910690c574	160
AnnaBridge	145:64910690c574	161	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	145:64910690c574	162
AnnaBridge	145:64910690c574	163	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	145:64910690c574	164	This parameter can be a value of @ref DMA_LL_EC_REQUEST
AnnaBridge	145:64910690c574	165
AnnaBridge	145:64910690c574	166	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	145:64910690c574	167
AnnaBridge	145:64910690c574	168	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	145:64910690c574	169	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	145:64910690c574	170
AnnaBridge	145:64910690c574	171	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge	145:64910690c574	172
AnnaBridge	145:64910690c574	173	} LL_DMA_InitTypeDef;
AnnaBridge	145:64910690c574	174	/**
AnnaBridge	145:64910690c574	175	* @}
AnnaBridge	145:64910690c574	176	*/
AnnaBridge	145:64910690c574	177	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	145:64910690c574	178
AnnaBridge	145:64910690c574	179	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	180	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	145:64910690c574	181	* @{
AnnaBridge	145:64910690c574	182	*/
AnnaBridge	145:64910690c574	183	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	145:64910690c574	184	* @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge	145:64910690c574	185	* @{
AnnaBridge	145:64910690c574	186	*/
AnnaBridge	145:64910690c574	187	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
AnnaBridge	145:64910690c574	188	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	145:64910690c574	189	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	145:64910690c574	190	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	145:64910690c574	191	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
AnnaBridge	145:64910690c574	192	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	145:64910690c574	193	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	145:64910690c574	194	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	145:64910690c574	195	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
AnnaBridge	145:64910690c574	196	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	145:64910690c574	197	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	145:64910690c574	198	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	145:64910690c574	199	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
AnnaBridge	145:64910690c574	200	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	145:64910690c574	201	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	145:64910690c574	202	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	145:64910690c574	203	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
AnnaBridge	145:64910690c574	204	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	145:64910690c574	205	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	145:64910690c574	206	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	145:64910690c574	207	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
AnnaBridge	145:64910690c574	208	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	145:64910690c574	209	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	145:64910690c574	210	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	145:64910690c574	211	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
AnnaBridge	145:64910690c574	212	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	145:64910690c574	213	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	145:64910690c574	214	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	145:64910690c574	215	/**
AnnaBridge	145:64910690c574	216	* @}
AnnaBridge	145:64910690c574	217	*/
AnnaBridge	145:64910690c574	218
AnnaBridge	145:64910690c574	219	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	145:64910690c574	220	* @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge	145:64910690c574	221	* @{
AnnaBridge	145:64910690c574	222	*/
AnnaBridge	145:64910690c574	223	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
AnnaBridge	145:64910690c574	224	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	145:64910690c574	225	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	145:64910690c574	226	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	145:64910690c574	227	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
AnnaBridge	145:64910690c574	228	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	145:64910690c574	229	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	145:64910690c574	230	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	145:64910690c574	231	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
AnnaBridge	145:64910690c574	232	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	145:64910690c574	233	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	145:64910690c574	234	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	145:64910690c574	235	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
AnnaBridge	145:64910690c574	236	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	145:64910690c574	237	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	145:64910690c574	238	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	145:64910690c574	239	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
AnnaBridge	145:64910690c574	240	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	145:64910690c574	241	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	145:64910690c574	242	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	145:64910690c574	243	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
AnnaBridge	145:64910690c574	244	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	145:64910690c574	245	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	145:64910690c574	246	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	145:64910690c574	247	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
AnnaBridge	145:64910690c574	248	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	145:64910690c574	249	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	145:64910690c574	250	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	145:64910690c574	251	/**
AnnaBridge	145:64910690c574	252	* @}
AnnaBridge	145:64910690c574	253	*/
AnnaBridge	145:64910690c574	254
AnnaBridge	145:64910690c574	255	/** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge	145:64910690c574	256	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge	145:64910690c574	257	* @{
AnnaBridge	145:64910690c574	258	*/
AnnaBridge	145:64910690c574	259	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
AnnaBridge	145:64910690c574	260	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
AnnaBridge	145:64910690c574	261	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
AnnaBridge	145:64910690c574	262	/**
AnnaBridge	145:64910690c574	263	* @}
AnnaBridge	145:64910690c574	264	*/
AnnaBridge	145:64910690c574	265
AnnaBridge	145:64910690c574	266	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	145:64910690c574	267	* @{
AnnaBridge	145:64910690c574	268	*/
AnnaBridge	145:64910690c574	269	#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /!< DMA Channel 1 /
AnnaBridge	145:64910690c574	270	#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /!< DMA Channel 2 /
AnnaBridge	145:64910690c574	271	#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /!< DMA Channel 3 /
AnnaBridge	145:64910690c574	272	#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /!< DMA Channel 4 /
AnnaBridge	145:64910690c574	273	#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /!< DMA Channel 5 /
AnnaBridge	145:64910690c574	274	#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /!< DMA Channel 6 /
AnnaBridge	145:64910690c574	275	#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /!< DMA Channel 7 /
AnnaBridge	145:64910690c574	276	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	277	#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
AnnaBridge	145:64910690c574	278	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	145:64910690c574	279	/**
AnnaBridge	145:64910690c574	280	* @}
AnnaBridge	145:64910690c574	281	*/
AnnaBridge	145:64910690c574	282
AnnaBridge	145:64910690c574	283	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge	145:64910690c574	284	* @{
AnnaBridge	145:64910690c574	285	*/
AnnaBridge	145:64910690c574	286	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
AnnaBridge	145:64910690c574	287	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
AnnaBridge	145:64910690c574	288	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
AnnaBridge	145:64910690c574	289	/**
AnnaBridge	145:64910690c574	290	* @}
AnnaBridge	145:64910690c574	291	*/
AnnaBridge	145:64910690c574	292
AnnaBridge	145:64910690c574	293	/** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge	145:64910690c574	294	* @{
AnnaBridge	145:64910690c574	295	*/
AnnaBridge	145:64910690c574	296	#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /!< Normal Mode /
AnnaBridge	145:64910690c574	297	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
AnnaBridge	145:64910690c574	298	/**
AnnaBridge	145:64910690c574	299	* @}
AnnaBridge	145:64910690c574	300	*/
AnnaBridge	145:64910690c574	301
AnnaBridge	145:64910690c574	302	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge	145:64910690c574	303	* @{
AnnaBridge	145:64910690c574	304	*/
AnnaBridge	145:64910690c574	305	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	145:64910690c574	306	#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /!< Peripheral increment mode Disable /
AnnaBridge	145:64910690c574	307	/**
AnnaBridge	145:64910690c574	308	* @}
AnnaBridge	145:64910690c574	309	*/
AnnaBridge	145:64910690c574	310
AnnaBridge	145:64910690c574	311	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge	145:64910690c574	312	* @{
AnnaBridge	145:64910690c574	313	*/
AnnaBridge	145:64910690c574	314	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	145:64910690c574	315	#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /!< Memory increment mode Disable /
AnnaBridge	145:64910690c574	316	/**
AnnaBridge	145:64910690c574	317	* @}
AnnaBridge	145:64910690c574	318	*/
AnnaBridge	145:64910690c574	319
AnnaBridge	145:64910690c574	320	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge	145:64910690c574	321	* @{
AnnaBridge	145:64910690c574	322	*/
AnnaBridge	145:64910690c574	323	#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment : Byte /
AnnaBridge	145:64910690c574	324	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	145:64910690c574	325	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	145:64910690c574	326	/**
AnnaBridge	145:64910690c574	327	* @}
AnnaBridge	145:64910690c574	328	*/
AnnaBridge	145:64910690c574	329
AnnaBridge	145:64910690c574	330	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge	145:64910690c574	331	* @{
AnnaBridge	145:64910690c574	332	*/
AnnaBridge	145:64910690c574	333	#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment : Byte /
AnnaBridge	145:64910690c574	334	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	145:64910690c574	335	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	145:64910690c574	336	/**
AnnaBridge	145:64910690c574	337	* @}
AnnaBridge	145:64910690c574	338	*/
AnnaBridge	145:64910690c574	339
AnnaBridge	145:64910690c574	340	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge	145:64910690c574	341	* @{
AnnaBridge	145:64910690c574	342	*/
AnnaBridge	145:64910690c574	343	#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level : Low /
AnnaBridge	145:64910690c574	344	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
AnnaBridge	145:64910690c574	345	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
AnnaBridge	145:64910690c574	346	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
AnnaBridge	145:64910690c574	347	/**
AnnaBridge	145:64910690c574	348	* @}
AnnaBridge	145:64910690c574	349	*/
AnnaBridge	145:64910690c574	350
AnnaBridge	145:64910690c574	351	/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
AnnaBridge	145:64910690c574	352	* @{
AnnaBridge	145:64910690c574	353	*/
AnnaBridge	145:64910690c574	354	#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /!< DMA peripheral request 0 /
AnnaBridge	145:64910690c574	355	#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /!< DMA peripheral request 1 /
AnnaBridge	145:64910690c574	356	#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /!< DMA peripheral request 2 /
AnnaBridge	145:64910690c574	357	#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /!< DMA peripheral request 3 /
AnnaBridge	145:64910690c574	358	#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /!< DMA peripheral request 4 /
AnnaBridge	145:64910690c574	359	#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /!< DMA peripheral request 5 /
AnnaBridge	145:64910690c574	360	#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /!< DMA peripheral request 6 /
AnnaBridge	145:64910690c574	361	#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /!< DMA peripheral request 7 /
AnnaBridge	145:64910690c574	362	/**
AnnaBridge	145:64910690c574	363	* @}
AnnaBridge	145:64910690c574	364	*/
AnnaBridge	145:64910690c574	365
AnnaBridge	145:64910690c574	366	/**
AnnaBridge	145:64910690c574	367	* @}
AnnaBridge	145:64910690c574	368	*/
AnnaBridge	145:64910690c574	369
AnnaBridge	145:64910690c574	370	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	371	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	145:64910690c574	372	* @{
AnnaBridge	145:64910690c574	373	*/
AnnaBridge	145:64910690c574	374
AnnaBridge	145:64910690c574	375	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	145:64910690c574	376	* @{
AnnaBridge	145:64910690c574	377	*/
AnnaBridge	145:64910690c574	378	/**
AnnaBridge	145:64910690c574	379	* @brief Write a value in DMA register
AnnaBridge	145:64910690c574	380	* @param __INSTANCE__ DMA Instance
AnnaBridge	145:64910690c574	381	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	382	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	383	* @retval None
AnnaBridge	145:64910690c574	384	*/
AnnaBridge	145:64910690c574	385	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	386
AnnaBridge	145:64910690c574	387	/**
AnnaBridge	145:64910690c574	388	* @brief Read a value in DMA register
AnnaBridge	145:64910690c574	389	* @param __INSTANCE__ DMA Instance
AnnaBridge	145:64910690c574	390	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	391	* @retval Register value
AnnaBridge	145:64910690c574	392	*/
AnnaBridge	145:64910690c574	393	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	145:64910690c574	394	/**
AnnaBridge	145:64910690c574	395	* @}
AnnaBridge	145:64910690c574	396	*/
AnnaBridge	145:64910690c574	397
AnnaBridge	145:64910690c574	398	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge	145:64910690c574	399	* @{
AnnaBridge	145:64910690c574	400	*/
AnnaBridge	145:64910690c574	401	/**
AnnaBridge	145:64910690c574	402	* @brief Convert DMAx_Channely into DMAx
AnnaBridge	145:64910690c574	403	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	145:64910690c574	404	* @retval DMAx
AnnaBridge	145:64910690c574	405	*/
AnnaBridge	145:64910690c574	406	#if defined(DMA2)
AnnaBridge	145:64910690c574	407	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge	145:64910690c574	408	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge	145:64910690c574	409	#else
AnnaBridge	145:64910690c574	410	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge	145:64910690c574	411	#endif
AnnaBridge	145:64910690c574	412
AnnaBridge	145:64910690c574	413	/**
AnnaBridge	145:64910690c574	414	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge	145:64910690c574	415	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	145:64910690c574	416	* @retval LL_DMA_CHANNEL_y
AnnaBridge	145:64910690c574	417	*/
AnnaBridge	145:64910690c574	418	#if defined (DMA2)
AnnaBridge	145:64910690c574	419	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	145:64910690c574	420	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	145:64910690c574	421	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	145:64910690c574	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	145:64910690c574	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	145:64910690c574	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	145:64910690c574	425	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	145:64910690c574	426	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	145:64910690c574	427	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	145:64910690c574	428	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	145:64910690c574	429	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	145:64910690c574	430	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	145:64910690c574	431	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	145:64910690c574	432	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	145:64910690c574	433	LL_DMA_CHANNEL_7)
AnnaBridge	145:64910690c574	434	#else
AnnaBridge	145:64910690c574	435	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	145:64910690c574	436	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	145:64910690c574	437	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	145:64910690c574	438	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	145:64910690c574	439	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	145:64910690c574	440	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	145:64910690c574	441	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	145:64910690c574	442	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	145:64910690c574	443	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	145:64910690c574	444	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	145:64910690c574	445	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	145:64910690c574	446	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	145:64910690c574	447	LL_DMA_CHANNEL_7)
AnnaBridge	145:64910690c574	448	#endif
AnnaBridge	145:64910690c574	449	#else
AnnaBridge	145:64910690c574	450	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	145:64910690c574	451	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	145:64910690c574	452	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	145:64910690c574	453	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	145:64910690c574	454	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	145:64910690c574	455	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	145:64910690c574	456	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	145:64910690c574	457	LL_DMA_CHANNEL_7)
AnnaBridge	145:64910690c574	458	#endif
AnnaBridge	145:64910690c574	459
AnnaBridge	145:64910690c574	460	/**
AnnaBridge	145:64910690c574	461	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge	145:64910690c574	462	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	145:64910690c574	463	* @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge	145:64910690c574	464	* @retval DMAx_Channely
AnnaBridge	145:64910690c574	465	*/
AnnaBridge	145:64910690c574	466	#if defined (DMA2)
AnnaBridge	145:64910690c574	467	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	145:64910690c574	468	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	145:64910690c574	469	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	145:64910690c574	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	145:64910690c574	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	145:64910690c574	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	145:64910690c574	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	145:64910690c574	474	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	145:64910690c574	475	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	145:64910690c574	476	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	145:64910690c574	477	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	145:64910690c574	478	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	145:64910690c574	479	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	145:64910690c574	480	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
AnnaBridge	145:64910690c574	481	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
AnnaBridge	145:64910690c574	482	DMA2_Channel7)
AnnaBridge	145:64910690c574	483	#else
AnnaBridge	145:64910690c574	484	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	145:64910690c574	485	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	145:64910690c574	486	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	145:64910690c574	487	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	145:64910690c574	488	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	145:64910690c574	489	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	145:64910690c574	490	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	145:64910690c574	491	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	145:64910690c574	492	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	145:64910690c574	493	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	145:64910690c574	494	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	145:64910690c574	495	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	145:64910690c574	496	DMA1_Channel7)
AnnaBridge	145:64910690c574	497	#endif
AnnaBridge	145:64910690c574	498	#else
AnnaBridge	145:64910690c574	499	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	145:64910690c574	500	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	145:64910690c574	501	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	145:64910690c574	502	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	145:64910690c574	503	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	145:64910690c574	504	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	145:64910690c574	505	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	145:64910690c574	506	DMA1_Channel7)
AnnaBridge	145:64910690c574	507	#endif
AnnaBridge	145:64910690c574	508
AnnaBridge	145:64910690c574	509	/**
AnnaBridge	145:64910690c574	510	* @}
AnnaBridge	145:64910690c574	511	*/
AnnaBridge	145:64910690c574	512
AnnaBridge	145:64910690c574	513	/**
AnnaBridge	145:64910690c574	514	* @}
AnnaBridge	145:64910690c574	515	*/
AnnaBridge	145:64910690c574	516
AnnaBridge	145:64910690c574	517	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	518	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	145:64910690c574	519	* @{
AnnaBridge	145:64910690c574	520	*/
AnnaBridge	145:64910690c574	521
AnnaBridge	145:64910690c574	522	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	145:64910690c574	523	* @{
AnnaBridge	145:64910690c574	524	*/
AnnaBridge	145:64910690c574	525	/**
AnnaBridge	145:64910690c574	526	* @brief Enable DMA channel.
AnnaBridge	145:64910690c574	527	* @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge	145:64910690c574	528	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	529	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	530	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	531	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	532	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	533	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	534	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	535	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	536	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	537	* @retval None
AnnaBridge	145:64910690c574	538	*/
AnnaBridge	145:64910690c574	539	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	540	{
AnnaBridge	145:64910690c574	541	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	145:64910690c574	542	}
AnnaBridge	145:64910690c574	543
AnnaBridge	145:64910690c574	544	/**
AnnaBridge	145:64910690c574	545	* @brief Disable DMA channel.
AnnaBridge	145:64910690c574	546	* @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge	145:64910690c574	547	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	548	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	549	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	550	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	551	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	552	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	553	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	554	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	555	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	556	* @retval None
AnnaBridge	145:64910690c574	557	*/
AnnaBridge	145:64910690c574	558	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	559	{
AnnaBridge	145:64910690c574	560	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	145:64910690c574	561	}
AnnaBridge	145:64910690c574	562
AnnaBridge	145:64910690c574	563	/**
AnnaBridge	145:64910690c574	564	* @brief Check if DMA channel is enabled or disabled.
AnnaBridge	145:64910690c574	565	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge	145:64910690c574	566	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	567	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	568	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	569	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	570	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	571	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	572	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	573	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	574	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	575	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	576	*/
AnnaBridge	145:64910690c574	577	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	578	{
AnnaBridge	145:64910690c574	579	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	580	DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge	145:64910690c574	581	}
AnnaBridge	145:64910690c574	582
AnnaBridge	145:64910690c574	583	/**
AnnaBridge	145:64910690c574	584	* @brief Configure all parameters link to DMA transfer.
AnnaBridge	145:64910690c574	585	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	586	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	587	* CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	588	* CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	589	* CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	590	* CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	591	* CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	592	* CCR PL LL_DMA_ConfigTransfer
AnnaBridge	145:64910690c574	593	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	594	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	595	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	596	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	597	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	598	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	599	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	600	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	601	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	602	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	145:64910690c574	603	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	145:64910690c574	604	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	145:64910690c574	605	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	145:64910690c574	606	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	145:64910690c574	607	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	145:64910690c574	608	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	145:64910690c574	609	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	145:64910690c574	610	* @retval None
AnnaBridge	145:64910690c574	611	*/
AnnaBridge	145:64910690c574	612	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	145:64910690c574	613	{
AnnaBridge	145:64910690c574	614	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	615	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
AnnaBridge	145:64910690c574	616	Configuration);
AnnaBridge	145:64910690c574	617	}
AnnaBridge	145:64910690c574	618
AnnaBridge	145:64910690c574	619	/**
AnnaBridge	145:64910690c574	620	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	145:64910690c574	621	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge	145:64910690c574	622	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge	145:64910690c574	623	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	624	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	625	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	626	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	627	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	628	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	629	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	630	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	631	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	632	* @param Direction This parameter can be one of the following values:
AnnaBridge	145:64910690c574	633	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	145:64910690c574	634	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	145:64910690c574	635	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	145:64910690c574	636	* @retval None
AnnaBridge	145:64910690c574	637	*/
AnnaBridge	145:64910690c574	638	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge	145:64910690c574	639	{
AnnaBridge	145:64910690c574	640	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	641	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
AnnaBridge	145:64910690c574	642	}
AnnaBridge	145:64910690c574	643
AnnaBridge	145:64910690c574	644	/**
AnnaBridge	145:64910690c574	645	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	145:64910690c574	646	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge	145:64910690c574	647	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge	145:64910690c574	648	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	649	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	650	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	651	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	652	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	653	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	654	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	655	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	656	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	657	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	658	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	145:64910690c574	659	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	145:64910690c574	660	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	145:64910690c574	661	*/
AnnaBridge	145:64910690c574	662	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	663	{
AnnaBridge	145:64910690c574	664	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	665	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
AnnaBridge	145:64910690c574	666	}
AnnaBridge	145:64910690c574	667
AnnaBridge	145:64910690c574	668	/**
AnnaBridge	145:64910690c574	669	* @brief Set DMA mode circular or normal.
AnnaBridge	145:64910690c574	670	* @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge	145:64910690c574	671	* data transfer is configured on the selected Channel.
AnnaBridge	145:64910690c574	672	* @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge	145:64910690c574	673	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	674	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	675	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	676	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	677	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	678	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	679	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	680	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	681	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	682	* @param Mode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	683	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	145:64910690c574	684	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	145:64910690c574	685	* @retval None
AnnaBridge	145:64910690c574	686	*/
AnnaBridge	145:64910690c574	687	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge	145:64910690c574	688	{
AnnaBridge	145:64910690c574	689	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge	145:64910690c574	690	Mode);
AnnaBridge	145:64910690c574	691	}
AnnaBridge	145:64910690c574	692
AnnaBridge	145:64910690c574	693	/**
AnnaBridge	145:64910690c574	694	* @brief Get DMA mode circular or normal.
AnnaBridge	145:64910690c574	695	* @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge	145:64910690c574	696	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	697	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	698	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	699	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	700	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	701	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	702	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	703	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	704	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	705	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	706	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	145:64910690c574	707	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	145:64910690c574	708	*/
AnnaBridge	145:64910690c574	709	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	710	{
AnnaBridge	145:64910690c574	711	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	712	DMA_CCR_CIRC));
AnnaBridge	145:64910690c574	713	}
AnnaBridge	145:64910690c574	714
AnnaBridge	145:64910690c574	715	/**
AnnaBridge	145:64910690c574	716	* @brief Set Peripheral increment mode.
AnnaBridge	145:64910690c574	717	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	145:64910690c574	718	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	719	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	720	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	721	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	722	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	723	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	724	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	725	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	726	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	727	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	728	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	145:64910690c574	729	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	145:64910690c574	730	* @retval None
AnnaBridge	145:64910690c574	731	*/
AnnaBridge	145:64910690c574	732	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge	145:64910690c574	733	{
AnnaBridge	145:64910690c574	734	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge	145:64910690c574	735	PeriphOrM2MSrcIncMode);
AnnaBridge	145:64910690c574	736	}
AnnaBridge	145:64910690c574	737
AnnaBridge	145:64910690c574	738	/**
AnnaBridge	145:64910690c574	739	* @brief Get Peripheral increment mode.
AnnaBridge	145:64910690c574	740	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	145:64910690c574	741	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	742	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	743	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	744	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	745	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	746	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	747	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	748	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	749	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	750	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	751	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	145:64910690c574	752	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	145:64910690c574	753	*/
AnnaBridge	145:64910690c574	754	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	755	{
AnnaBridge	145:64910690c574	756	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	757	DMA_CCR_PINC));
AnnaBridge	145:64910690c574	758	}
AnnaBridge	145:64910690c574	759
AnnaBridge	145:64910690c574	760	/**
AnnaBridge	145:64910690c574	761	* @brief Set Memory increment mode.
AnnaBridge	145:64910690c574	762	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	145:64910690c574	763	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	764	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	765	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	766	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	767	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	768	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	769	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	770	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	771	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	772	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	773	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	145:64910690c574	774	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	145:64910690c574	775	* @retval None
AnnaBridge	145:64910690c574	776	*/
AnnaBridge	145:64910690c574	777	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge	145:64910690c574	778	{
AnnaBridge	145:64910690c574	779	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge	145:64910690c574	780	MemoryOrM2MDstIncMode);
AnnaBridge	145:64910690c574	781	}
AnnaBridge	145:64910690c574	782
AnnaBridge	145:64910690c574	783	/**
AnnaBridge	145:64910690c574	784	* @brief Get Memory increment mode.
AnnaBridge	145:64910690c574	785	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	145:64910690c574	786	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	787	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	788	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	789	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	790	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	791	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	792	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	793	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	794	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	795	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	796	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	145:64910690c574	797	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	145:64910690c574	798	*/
AnnaBridge	145:64910690c574	799	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	800	{
AnnaBridge	145:64910690c574	801	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	802	DMA_CCR_MINC));
AnnaBridge	145:64910690c574	803	}
AnnaBridge	145:64910690c574	804
AnnaBridge	145:64910690c574	805	/**
AnnaBridge	145:64910690c574	806	* @brief Set Peripheral size.
AnnaBridge	145:64910690c574	807	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	145:64910690c574	808	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	809	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	810	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	811	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	812	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	813	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	814	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	815	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	816	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	817	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge	145:64910690c574	818	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	145:64910690c574	819	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	145:64910690c574	820	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	145:64910690c574	821	* @retval None
AnnaBridge	145:64910690c574	822	*/
AnnaBridge	145:64910690c574	823	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge	145:64910690c574	824	{
AnnaBridge	145:64910690c574	825	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge	145:64910690c574	826	PeriphOrM2MSrcDataSize);
AnnaBridge	145:64910690c574	827	}
AnnaBridge	145:64910690c574	828
AnnaBridge	145:64910690c574	829	/**
AnnaBridge	145:64910690c574	830	* @brief Get Peripheral size.
AnnaBridge	145:64910690c574	831	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	145:64910690c574	832	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	833	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	834	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	835	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	836	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	837	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	838	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	839	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	840	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	841	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	842	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	145:64910690c574	843	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	145:64910690c574	844	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	145:64910690c574	845	*/
AnnaBridge	145:64910690c574	846	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	847	{
AnnaBridge	145:64910690c574	848	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	849	DMA_CCR_PSIZE));
AnnaBridge	145:64910690c574	850	}
AnnaBridge	145:64910690c574	851
AnnaBridge	145:64910690c574	852	/**
AnnaBridge	145:64910690c574	853	* @brief Set Memory size.
AnnaBridge	145:64910690c574	854	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge	145:64910690c574	855	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	856	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	857	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	858	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	859	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	860	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	861	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	862	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	863	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	864	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge	145:64910690c574	865	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	145:64910690c574	866	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	145:64910690c574	867	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	145:64910690c574	868	* @retval None
AnnaBridge	145:64910690c574	869	*/
AnnaBridge	145:64910690c574	870	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge	145:64910690c574	871	{
AnnaBridge	145:64910690c574	872	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge	145:64910690c574	873	MemoryOrM2MDstDataSize);
AnnaBridge	145:64910690c574	874	}
AnnaBridge	145:64910690c574	875
AnnaBridge	145:64910690c574	876	/**
AnnaBridge	145:64910690c574	877	* @brief Get Memory size.
AnnaBridge	145:64910690c574	878	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge	145:64910690c574	879	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	880	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	881	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	882	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	883	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	884	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	885	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	886	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	887	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	888	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	889	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	145:64910690c574	890	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	145:64910690c574	891	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	145:64910690c574	892	*/
AnnaBridge	145:64910690c574	893	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	894	{
AnnaBridge	145:64910690c574	895	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	896	DMA_CCR_MSIZE));
AnnaBridge	145:64910690c574	897	}
AnnaBridge	145:64910690c574	898
AnnaBridge	145:64910690c574	899	/**
AnnaBridge	145:64910690c574	900	* @brief Set Channel priority level.
AnnaBridge	145:64910690c574	901	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge	145:64910690c574	902	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	903	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	904	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	905	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	906	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	907	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	908	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	909	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	910	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	911	* @param Priority This parameter can be one of the following values:
AnnaBridge	145:64910690c574	912	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	145:64910690c574	913	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	145:64910690c574	914	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	145:64910690c574	915	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	145:64910690c574	916	* @retval None
AnnaBridge	145:64910690c574	917	*/
AnnaBridge	145:64910690c574	918	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge	145:64910690c574	919	{
AnnaBridge	145:64910690c574	920	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge	145:64910690c574	921	Priority);
AnnaBridge	145:64910690c574	922	}
AnnaBridge	145:64910690c574	923
AnnaBridge	145:64910690c574	924	/**
AnnaBridge	145:64910690c574	925	* @brief Get Channel priority level.
AnnaBridge	145:64910690c574	926	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge	145:64910690c574	927	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	928	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	929	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	930	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	931	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	932	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	933	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	934	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	935	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	936	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	937	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	145:64910690c574	938	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	145:64910690c574	939	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	145:64910690c574	940	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	145:64910690c574	941	*/
AnnaBridge	145:64910690c574	942	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	943	{
AnnaBridge	145:64910690c574	944	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	945	DMA_CCR_PL));
AnnaBridge	145:64910690c574	946	}
AnnaBridge	145:64910690c574	947
AnnaBridge	145:64910690c574	948	/**
AnnaBridge	145:64910690c574	949	* @brief Set Number of data to transfer.
AnnaBridge	145:64910690c574	950	* @note This action has no effect if
AnnaBridge	145:64910690c574	951	* channel is enabled.
AnnaBridge	145:64910690c574	952	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge	145:64910690c574	953	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	954	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	955	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	956	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	957	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	958	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	959	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	960	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	961	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	962	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	145:64910690c574	963	* @retval None
AnnaBridge	145:64910690c574	964	*/
AnnaBridge	145:64910690c574	965	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge	145:64910690c574	966	{
AnnaBridge	145:64910690c574	967	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	145:64910690c574	968	DMA_CNDTR_NDT, NbData);
AnnaBridge	145:64910690c574	969	}
AnnaBridge	145:64910690c574	970
AnnaBridge	145:64910690c574	971	/**
AnnaBridge	145:64910690c574	972	* @brief Get Number of data to transfer.
AnnaBridge	145:64910690c574	973	* @note Once the channel is enabled, the return value indicate the
AnnaBridge	145:64910690c574	974	* remaining bytes to be transmitted.
AnnaBridge	145:64910690c574	975	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge	145:64910690c574	976	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	977	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	978	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	979	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	980	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	981	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	982	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	983	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	984	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	985	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	986	*/
AnnaBridge	145:64910690c574	987	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	988	{
AnnaBridge	145:64910690c574	989	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	145:64910690c574	990	DMA_CNDTR_NDT));
AnnaBridge	145:64910690c574	991	}
AnnaBridge	145:64910690c574	992
AnnaBridge	145:64910690c574	993	/**
AnnaBridge	145:64910690c574	994	* @brief Configure the Source and Destination addresses.
AnnaBridge	145:64910690c574	995	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	996	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge	145:64910690c574	997	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge	145:64910690c574	998	* CMAR MA LL_DMA_ConfigAddresses
AnnaBridge	145:64910690c574	999	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1000	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1001	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1002	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1003	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1004	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1005	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1006	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1007	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1008	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1009	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1010	* @param Direction This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1011	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	145:64910690c574	1012	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	145:64910690c574	1013	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	145:64910690c574	1014	* @retval None
AnnaBridge	145:64910690c574	1015	*/
AnnaBridge	145:64910690c574	1016	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge	145:64910690c574	1017	uint32_t DstAddress, uint32_t Direction)
AnnaBridge	145:64910690c574	1018	{
AnnaBridge	145:64910690c574	1019	/* Direction Memory to Periph */
AnnaBridge	145:64910690c574	1020	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	145:64910690c574	1021	{
AnnaBridge	145:64910690c574	1022	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge	145:64910690c574	1023	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge	145:64910690c574	1024	}
AnnaBridge	145:64910690c574	1025	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	145:64910690c574	1026	else
AnnaBridge	145:64910690c574	1027	{
AnnaBridge	145:64910690c574	1028	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge	145:64910690c574	1029	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge	145:64910690c574	1030	}
AnnaBridge	145:64910690c574	1031	}
AnnaBridge	145:64910690c574	1032
AnnaBridge	145:64910690c574	1033	/**
AnnaBridge	145:64910690c574	1034	* @brief Set the Memory address.
AnnaBridge	145:64910690c574	1035	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	145:64910690c574	1036	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	1037	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge	145:64910690c574	1038	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1039	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1040	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1041	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1042	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1043	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1044	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1045	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1046	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1047	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1048	* @retval None
AnnaBridge	145:64910690c574	1049	*/
AnnaBridge	145:64910690c574	1050	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	145:64910690c574	1051	{
AnnaBridge	145:64910690c574	1052	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	145:64910690c574	1053	}
AnnaBridge	145:64910690c574	1054
AnnaBridge	145:64910690c574	1055	/**
AnnaBridge	145:64910690c574	1056	* @brief Set the Peripheral address.
AnnaBridge	145:64910690c574	1057	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	145:64910690c574	1058	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	1059	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge	145:64910690c574	1060	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1061	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1062	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1063	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1064	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1065	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1066	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1067	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1068	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1069	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1070	* @retval None
AnnaBridge	145:64910690c574	1071	*/
AnnaBridge	145:64910690c574	1072	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge	145:64910690c574	1073	{
AnnaBridge	145:64910690c574	1074	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge	145:64910690c574	1075	}
AnnaBridge	145:64910690c574	1076
AnnaBridge	145:64910690c574	1077	/**
AnnaBridge	145:64910690c574	1078	* @brief Get Memory address.
AnnaBridge	145:64910690c574	1079	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	145:64910690c574	1080	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge	145:64910690c574	1081	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1082	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1083	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1084	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1085	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1086	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1087	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1088	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1089	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1090	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1091	*/
AnnaBridge	145:64910690c574	1092	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1093	{
AnnaBridge	145:64910690c574	1094	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	145:64910690c574	1095	}
AnnaBridge	145:64910690c574	1096
AnnaBridge	145:64910690c574	1097	/**
AnnaBridge	145:64910690c574	1098	* @brief Get Peripheral address.
AnnaBridge	145:64910690c574	1099	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	145:64910690c574	1100	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge	145:64910690c574	1101	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1102	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1103	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1104	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1105	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1106	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1107	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1108	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1109	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1110	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1111	*/
AnnaBridge	145:64910690c574	1112	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1113	{
AnnaBridge	145:64910690c574	1114	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	145:64910690c574	1115	}
AnnaBridge	145:64910690c574	1116
AnnaBridge	145:64910690c574	1117	/**
AnnaBridge	145:64910690c574	1118	* @brief Set the Memory to Memory Source address.
AnnaBridge	145:64910690c574	1119	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	145:64910690c574	1120	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	1121	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	145:64910690c574	1122	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1123	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1124	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1125	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1126	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1127	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1128	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1129	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1130	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1131	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1132	* @retval None
AnnaBridge	145:64910690c574	1133	*/
AnnaBridge	145:64910690c574	1134	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	145:64910690c574	1135	{
AnnaBridge	145:64910690c574	1136	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge	145:64910690c574	1137	}
AnnaBridge	145:64910690c574	1138
AnnaBridge	145:64910690c574	1139	/**
AnnaBridge	145:64910690c574	1140	* @brief Set the Memory to Memory Destination address.
AnnaBridge	145:64910690c574	1141	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	145:64910690c574	1142	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	1143	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge	145:64910690c574	1144	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1145	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1146	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1147	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1148	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1149	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1150	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1151	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1152	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1153	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1154	* @retval None
AnnaBridge	145:64910690c574	1155	*/
AnnaBridge	145:64910690c574	1156	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	145:64910690c574	1157	{
AnnaBridge	145:64910690c574	1158	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	145:64910690c574	1159	}
AnnaBridge	145:64910690c574	1160
AnnaBridge	145:64910690c574	1161	/**
AnnaBridge	145:64910690c574	1162	* @brief Get the Memory to Memory Source address.
AnnaBridge	145:64910690c574	1163	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	145:64910690c574	1164	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	145:64910690c574	1165	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1166	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1167	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1168	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1169	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1170	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1171	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1172	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1173	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1174	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1175	*/
AnnaBridge	145:64910690c574	1176	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1177	{
AnnaBridge	145:64910690c574	1178	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	145:64910690c574	1179	}
AnnaBridge	145:64910690c574	1180
AnnaBridge	145:64910690c574	1181	/**
AnnaBridge	145:64910690c574	1182	* @brief Get the Memory to Memory Destination address.
AnnaBridge	145:64910690c574	1183	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	145:64910690c574	1184	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge	145:64910690c574	1185	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1186	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1187	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1188	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1189	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1190	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1191	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1192	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1193	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1194	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	145:64910690c574	1195	*/
AnnaBridge	145:64910690c574	1196	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1197	{
AnnaBridge	145:64910690c574	1198	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	145:64910690c574	1199	}
AnnaBridge	145:64910690c574	1200
AnnaBridge	145:64910690c574	1201	/**
AnnaBridge	145:64910690c574	1202	* @brief Set DMA request for DMA instance on Channel x.
AnnaBridge	145:64910690c574	1203	* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
AnnaBridge	145:64910690c574	1204	* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
AnnaBridge	145:64910690c574	1205	* CSELR C2S LL_DMA_SetPeriphRequest\n
AnnaBridge	145:64910690c574	1206	* CSELR C3S LL_DMA_SetPeriphRequest\n
AnnaBridge	145:64910690c574	1207	* CSELR C4S LL_DMA_SetPeriphRequest\n
AnnaBridge	145:64910690c574	1208	* CSELR C5S LL_DMA_SetPeriphRequest\n
AnnaBridge	145:64910690c574	1209	* CSELR C6S LL_DMA_SetPeriphRequest\n
AnnaBridge	145:64910690c574	1210	* CSELR C7S LL_DMA_SetPeriphRequest
AnnaBridge	145:64910690c574	1211	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1212	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1213	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1214	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1215	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1216	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1217	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1218	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1219	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1220	* @param PeriphRequest This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1221	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	145:64910690c574	1222	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	145:64910690c574	1223	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	145:64910690c574	1224	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	145:64910690c574	1225	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	145:64910690c574	1226	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	145:64910690c574	1227	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	145:64910690c574	1228	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	145:64910690c574	1229	* @retval None
AnnaBridge	145:64910690c574	1230	*/
AnnaBridge	145:64910690c574	1231	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
AnnaBridge	145:64910690c574	1232	{
AnnaBridge	145:64910690c574	1233	MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	145:64910690c574	1234	DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
AnnaBridge	145:64910690c574	1235	}
AnnaBridge	145:64910690c574	1236
AnnaBridge	145:64910690c574	1237	/**
AnnaBridge	145:64910690c574	1238	* @brief Get DMA request for DMA instance on Channel x.
AnnaBridge	145:64910690c574	1239	* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
AnnaBridge	145:64910690c574	1240	* CSELR C2S LL_DMA_GetPeriphRequest\n
AnnaBridge	145:64910690c574	1241	* CSELR C3S LL_DMA_GetPeriphRequest\n
AnnaBridge	145:64910690c574	1242	* CSELR C4S LL_DMA_GetPeriphRequest\n
AnnaBridge	145:64910690c574	1243	* CSELR C5S LL_DMA_GetPeriphRequest\n
AnnaBridge	145:64910690c574	1244	* CSELR C6S LL_DMA_GetPeriphRequest\n
AnnaBridge	145:64910690c574	1245	* CSELR C7S LL_DMA_GetPeriphRequest
AnnaBridge	145:64910690c574	1246	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1247	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1248	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1249	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1250	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1251	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1252	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1253	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1254	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1255	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1256	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	145:64910690c574	1257	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	145:64910690c574	1258	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	145:64910690c574	1259	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	145:64910690c574	1260	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	145:64910690c574	1261	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	145:64910690c574	1262	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	145:64910690c574	1263	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	145:64910690c574	1264	*/
AnnaBridge	145:64910690c574	1265	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1266	{
AnnaBridge	145:64910690c574	1267	return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	145:64910690c574	1268	DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
AnnaBridge	145:64910690c574	1269	}
AnnaBridge	145:64910690c574	1270
AnnaBridge	145:64910690c574	1271	/**
AnnaBridge	145:64910690c574	1272	* @}
AnnaBridge	145:64910690c574	1273	*/
AnnaBridge	145:64910690c574	1274
AnnaBridge	145:64910690c574	1275	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	145:64910690c574	1276	* @{
AnnaBridge	145:64910690c574	1277	*/
AnnaBridge	145:64910690c574	1278
AnnaBridge	145:64910690c574	1279	/**
AnnaBridge	145:64910690c574	1280	* @brief Get Channel 1 global interrupt flag.
AnnaBridge	145:64910690c574	1281	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge	145:64910690c574	1282	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1283	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1284	*/
AnnaBridge	145:64910690c574	1285	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1286	{
AnnaBridge	145:64910690c574	1287	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge	145:64910690c574	1288	}
AnnaBridge	145:64910690c574	1289
AnnaBridge	145:64910690c574	1290	/**
AnnaBridge	145:64910690c574	1291	* @brief Get Channel 2 global interrupt flag.
AnnaBridge	145:64910690c574	1292	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge	145:64910690c574	1293	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1294	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1295	*/
AnnaBridge	145:64910690c574	1296	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1297	{
AnnaBridge	145:64910690c574	1298	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge	145:64910690c574	1299	}
AnnaBridge	145:64910690c574	1300
AnnaBridge	145:64910690c574	1301	/**
AnnaBridge	145:64910690c574	1302	* @brief Get Channel 3 global interrupt flag.
AnnaBridge	145:64910690c574	1303	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge	145:64910690c574	1304	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1305	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1306	*/
AnnaBridge	145:64910690c574	1307	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1308	{
AnnaBridge	145:64910690c574	1309	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge	145:64910690c574	1310	}
AnnaBridge	145:64910690c574	1311
AnnaBridge	145:64910690c574	1312	/**
AnnaBridge	145:64910690c574	1313	* @brief Get Channel 4 global interrupt flag.
AnnaBridge	145:64910690c574	1314	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge	145:64910690c574	1315	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1316	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1317	*/
AnnaBridge	145:64910690c574	1318	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1319	{
AnnaBridge	145:64910690c574	1320	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge	145:64910690c574	1321	}
AnnaBridge	145:64910690c574	1322
AnnaBridge	145:64910690c574	1323	/**
AnnaBridge	145:64910690c574	1324	* @brief Get Channel 5 global interrupt flag.
AnnaBridge	145:64910690c574	1325	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge	145:64910690c574	1326	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1327	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1328	*/
AnnaBridge	145:64910690c574	1329	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1330	{
AnnaBridge	145:64910690c574	1331	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge	145:64910690c574	1332	}
AnnaBridge	145:64910690c574	1333
AnnaBridge	145:64910690c574	1334	/**
AnnaBridge	145:64910690c574	1335	* @brief Get Channel 6 global interrupt flag.
AnnaBridge	145:64910690c574	1336	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge	145:64910690c574	1337	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1338	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1339	*/
AnnaBridge	145:64910690c574	1340	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1341	{
AnnaBridge	145:64910690c574	1342	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge	145:64910690c574	1343	}
AnnaBridge	145:64910690c574	1344
AnnaBridge	145:64910690c574	1345	/**
AnnaBridge	145:64910690c574	1346	* @brief Get Channel 7 global interrupt flag.
AnnaBridge	145:64910690c574	1347	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge	145:64910690c574	1348	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1349	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1350	*/
AnnaBridge	145:64910690c574	1351	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1352	{
AnnaBridge	145:64910690c574	1353	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge	145:64910690c574	1354	}
AnnaBridge	145:64910690c574	1355
AnnaBridge	145:64910690c574	1356	/**
AnnaBridge	145:64910690c574	1357	* @brief Get Channel 1 transfer complete flag.
AnnaBridge	145:64910690c574	1358	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	145:64910690c574	1359	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1360	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1361	*/
AnnaBridge	145:64910690c574	1362	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1363	{
AnnaBridge	145:64910690c574	1364	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge	145:64910690c574	1365	}
AnnaBridge	145:64910690c574	1366
AnnaBridge	145:64910690c574	1367	/**
AnnaBridge	145:64910690c574	1368	* @brief Get Channel 2 transfer complete flag.
AnnaBridge	145:64910690c574	1369	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	145:64910690c574	1370	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1371	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1372	*/
AnnaBridge	145:64910690c574	1373	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1374	{
AnnaBridge	145:64910690c574	1375	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge	145:64910690c574	1376	}
AnnaBridge	145:64910690c574	1377
AnnaBridge	145:64910690c574	1378	/**
AnnaBridge	145:64910690c574	1379	* @brief Get Channel 3 transfer complete flag.
AnnaBridge	145:64910690c574	1380	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	145:64910690c574	1381	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1382	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1383	*/
AnnaBridge	145:64910690c574	1384	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1385	{
AnnaBridge	145:64910690c574	1386	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge	145:64910690c574	1387	}
AnnaBridge	145:64910690c574	1388
AnnaBridge	145:64910690c574	1389	/**
AnnaBridge	145:64910690c574	1390	* @brief Get Channel 4 transfer complete flag.
AnnaBridge	145:64910690c574	1391	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	145:64910690c574	1392	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1393	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1394	*/
AnnaBridge	145:64910690c574	1395	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1396	{
AnnaBridge	145:64910690c574	1397	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge	145:64910690c574	1398	}
AnnaBridge	145:64910690c574	1399
AnnaBridge	145:64910690c574	1400	/**
AnnaBridge	145:64910690c574	1401	* @brief Get Channel 5 transfer complete flag.
AnnaBridge	145:64910690c574	1402	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge	145:64910690c574	1403	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1404	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1405	*/
AnnaBridge	145:64910690c574	1406	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1407	{
AnnaBridge	145:64910690c574	1408	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge	145:64910690c574	1409	}
AnnaBridge	145:64910690c574	1410
AnnaBridge	145:64910690c574	1411	/**
AnnaBridge	145:64910690c574	1412	* @brief Get Channel 6 transfer complete flag.
AnnaBridge	145:64910690c574	1413	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	145:64910690c574	1414	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1415	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1416	*/
AnnaBridge	145:64910690c574	1417	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1418	{
AnnaBridge	145:64910690c574	1419	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge	145:64910690c574	1420	}
AnnaBridge	145:64910690c574	1421
AnnaBridge	145:64910690c574	1422	/**
AnnaBridge	145:64910690c574	1423	* @brief Get Channel 7 transfer complete flag.
AnnaBridge	145:64910690c574	1424	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	145:64910690c574	1425	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1426	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1427	*/
AnnaBridge	145:64910690c574	1428	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1429	{
AnnaBridge	145:64910690c574	1430	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge	145:64910690c574	1431	}
AnnaBridge	145:64910690c574	1432
AnnaBridge	145:64910690c574	1433	/**
AnnaBridge	145:64910690c574	1434	* @brief Get Channel 1 half transfer flag.
AnnaBridge	145:64910690c574	1435	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	145:64910690c574	1436	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1437	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1438	*/
AnnaBridge	145:64910690c574	1439	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1440	{
AnnaBridge	145:64910690c574	1441	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge	145:64910690c574	1442	}
AnnaBridge	145:64910690c574	1443
AnnaBridge	145:64910690c574	1444	/**
AnnaBridge	145:64910690c574	1445	* @brief Get Channel 2 half transfer flag.
AnnaBridge	145:64910690c574	1446	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	145:64910690c574	1447	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1448	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1449	*/
AnnaBridge	145:64910690c574	1450	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1451	{
AnnaBridge	145:64910690c574	1452	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge	145:64910690c574	1453	}
AnnaBridge	145:64910690c574	1454
AnnaBridge	145:64910690c574	1455	/**
AnnaBridge	145:64910690c574	1456	* @brief Get Channel 3 half transfer flag.
AnnaBridge	145:64910690c574	1457	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	145:64910690c574	1458	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1459	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1460	*/
AnnaBridge	145:64910690c574	1461	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1462	{
AnnaBridge	145:64910690c574	1463	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge	145:64910690c574	1464	}
AnnaBridge	145:64910690c574	1465
AnnaBridge	145:64910690c574	1466	/**
AnnaBridge	145:64910690c574	1467	* @brief Get Channel 4 half transfer flag.
AnnaBridge	145:64910690c574	1468	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	145:64910690c574	1469	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1470	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1471	*/
AnnaBridge	145:64910690c574	1472	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1473	{
AnnaBridge	145:64910690c574	1474	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge	145:64910690c574	1475	}
AnnaBridge	145:64910690c574	1476
AnnaBridge	145:64910690c574	1477	/**
AnnaBridge	145:64910690c574	1478	* @brief Get Channel 5 half transfer flag.
AnnaBridge	145:64910690c574	1479	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge	145:64910690c574	1480	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1481	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1482	*/
AnnaBridge	145:64910690c574	1483	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1484	{
AnnaBridge	145:64910690c574	1485	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge	145:64910690c574	1486	}
AnnaBridge	145:64910690c574	1487
AnnaBridge	145:64910690c574	1488	/**
AnnaBridge	145:64910690c574	1489	* @brief Get Channel 6 half transfer flag.
AnnaBridge	145:64910690c574	1490	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	145:64910690c574	1491	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1492	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1493	*/
AnnaBridge	145:64910690c574	1494	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1495	{
AnnaBridge	145:64910690c574	1496	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge	145:64910690c574	1497	}
AnnaBridge	145:64910690c574	1498
AnnaBridge	145:64910690c574	1499	/**
AnnaBridge	145:64910690c574	1500	* @brief Get Channel 7 half transfer flag.
AnnaBridge	145:64910690c574	1501	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	145:64910690c574	1502	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1503	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1504	*/
AnnaBridge	145:64910690c574	1505	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1506	{
AnnaBridge	145:64910690c574	1507	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge	145:64910690c574	1508	}
AnnaBridge	145:64910690c574	1509
AnnaBridge	145:64910690c574	1510	/**
AnnaBridge	145:64910690c574	1511	* @brief Get Channel 1 transfer error flag.
AnnaBridge	145:64910690c574	1512	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	145:64910690c574	1513	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1514	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1515	*/
AnnaBridge	145:64910690c574	1516	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1517	{
AnnaBridge	145:64910690c574	1518	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge	145:64910690c574	1519	}
AnnaBridge	145:64910690c574	1520
AnnaBridge	145:64910690c574	1521	/**
AnnaBridge	145:64910690c574	1522	* @brief Get Channel 2 transfer error flag.
AnnaBridge	145:64910690c574	1523	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	145:64910690c574	1524	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1525	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1526	*/
AnnaBridge	145:64910690c574	1527	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1528	{
AnnaBridge	145:64910690c574	1529	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge	145:64910690c574	1530	}
AnnaBridge	145:64910690c574	1531
AnnaBridge	145:64910690c574	1532	/**
AnnaBridge	145:64910690c574	1533	* @brief Get Channel 3 transfer error flag.
AnnaBridge	145:64910690c574	1534	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	145:64910690c574	1535	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1536	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1537	*/
AnnaBridge	145:64910690c574	1538	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1539	{
AnnaBridge	145:64910690c574	1540	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge	145:64910690c574	1541	}
AnnaBridge	145:64910690c574	1542
AnnaBridge	145:64910690c574	1543	/**
AnnaBridge	145:64910690c574	1544	* @brief Get Channel 4 transfer error flag.
AnnaBridge	145:64910690c574	1545	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	145:64910690c574	1546	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1547	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1548	*/
AnnaBridge	145:64910690c574	1549	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1550	{
AnnaBridge	145:64910690c574	1551	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge	145:64910690c574	1552	}
AnnaBridge	145:64910690c574	1553
AnnaBridge	145:64910690c574	1554	/**
AnnaBridge	145:64910690c574	1555	* @brief Get Channel 5 transfer error flag.
AnnaBridge	145:64910690c574	1556	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge	145:64910690c574	1557	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1558	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1559	*/
AnnaBridge	145:64910690c574	1560	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1561	{
AnnaBridge	145:64910690c574	1562	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge	145:64910690c574	1563	}
AnnaBridge	145:64910690c574	1564
AnnaBridge	145:64910690c574	1565	/**
AnnaBridge	145:64910690c574	1566	* @brief Get Channel 6 transfer error flag.
AnnaBridge	145:64910690c574	1567	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	145:64910690c574	1568	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1569	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1570	*/
AnnaBridge	145:64910690c574	1571	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1572	{
AnnaBridge	145:64910690c574	1573	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge	145:64910690c574	1574	}
AnnaBridge	145:64910690c574	1575
AnnaBridge	145:64910690c574	1576	/**
AnnaBridge	145:64910690c574	1577	* @brief Get Channel 7 transfer error flag.
AnnaBridge	145:64910690c574	1578	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	145:64910690c574	1579	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1580	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1581	*/
AnnaBridge	145:64910690c574	1582	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1583	{
AnnaBridge	145:64910690c574	1584	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge	145:64910690c574	1585	}
AnnaBridge	145:64910690c574	1586
AnnaBridge	145:64910690c574	1587	/**
AnnaBridge	145:64910690c574	1588	* @brief Clear Channel 1 global interrupt flag.
AnnaBridge	145:64910690c574	1589	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge	145:64910690c574	1590	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1591	* @retval None
AnnaBridge	145:64910690c574	1592	*/
AnnaBridge	145:64910690c574	1593	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1594	{
AnnaBridge	145:64910690c574	1595	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge	145:64910690c574	1596	}
AnnaBridge	145:64910690c574	1597
AnnaBridge	145:64910690c574	1598	/**
AnnaBridge	145:64910690c574	1599	* @brief Clear Channel 2 global interrupt flag.
AnnaBridge	145:64910690c574	1600	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge	145:64910690c574	1601	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1602	* @retval None
AnnaBridge	145:64910690c574	1603	*/
AnnaBridge	145:64910690c574	1604	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1605	{
AnnaBridge	145:64910690c574	1606	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge	145:64910690c574	1607	}
AnnaBridge	145:64910690c574	1608
AnnaBridge	145:64910690c574	1609	/**
AnnaBridge	145:64910690c574	1610	* @brief Clear Channel 3 global interrupt flag.
AnnaBridge	145:64910690c574	1611	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge	145:64910690c574	1612	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1613	* @retval None
AnnaBridge	145:64910690c574	1614	*/
AnnaBridge	145:64910690c574	1615	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1616	{
AnnaBridge	145:64910690c574	1617	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge	145:64910690c574	1618	}
AnnaBridge	145:64910690c574	1619
AnnaBridge	145:64910690c574	1620	/**
AnnaBridge	145:64910690c574	1621	* @brief Clear Channel 4 global interrupt flag.
AnnaBridge	145:64910690c574	1622	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge	145:64910690c574	1623	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1624	* @retval None
AnnaBridge	145:64910690c574	1625	*/
AnnaBridge	145:64910690c574	1626	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1627	{
AnnaBridge	145:64910690c574	1628	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge	145:64910690c574	1629	}
AnnaBridge	145:64910690c574	1630
AnnaBridge	145:64910690c574	1631	/**
AnnaBridge	145:64910690c574	1632	* @brief Clear Channel 5 global interrupt flag.
AnnaBridge	145:64910690c574	1633	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge	145:64910690c574	1634	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1635	* @retval None
AnnaBridge	145:64910690c574	1636	*/
AnnaBridge	145:64910690c574	1637	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1638	{
AnnaBridge	145:64910690c574	1639	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge	145:64910690c574	1640	}
AnnaBridge	145:64910690c574	1641
AnnaBridge	145:64910690c574	1642	/**
AnnaBridge	145:64910690c574	1643	* @brief Clear Channel 6 global interrupt flag.
AnnaBridge	145:64910690c574	1644	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge	145:64910690c574	1645	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1646	* @retval None
AnnaBridge	145:64910690c574	1647	*/
AnnaBridge	145:64910690c574	1648	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1649	{
AnnaBridge	145:64910690c574	1650	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge	145:64910690c574	1651	}
AnnaBridge	145:64910690c574	1652
AnnaBridge	145:64910690c574	1653	/**
AnnaBridge	145:64910690c574	1654	* @brief Clear Channel 7 global interrupt flag.
AnnaBridge	145:64910690c574	1655	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge	145:64910690c574	1656	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1657	* @retval None
AnnaBridge	145:64910690c574	1658	*/
AnnaBridge	145:64910690c574	1659	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1660	{
AnnaBridge	145:64910690c574	1661	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge	145:64910690c574	1662	}
AnnaBridge	145:64910690c574	1663
AnnaBridge	145:64910690c574	1664	/**
AnnaBridge	145:64910690c574	1665	* @brief Clear Channel 1 transfer complete flag.
AnnaBridge	145:64910690c574	1666	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	145:64910690c574	1667	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1668	* @retval None
AnnaBridge	145:64910690c574	1669	*/
AnnaBridge	145:64910690c574	1670	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1671	{
AnnaBridge	145:64910690c574	1672	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge	145:64910690c574	1673	}
AnnaBridge	145:64910690c574	1674
AnnaBridge	145:64910690c574	1675	/**
AnnaBridge	145:64910690c574	1676	* @brief Clear Channel 2 transfer complete flag.
AnnaBridge	145:64910690c574	1677	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	145:64910690c574	1678	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1679	* @retval None
AnnaBridge	145:64910690c574	1680	*/
AnnaBridge	145:64910690c574	1681	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1682	{
AnnaBridge	145:64910690c574	1683	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge	145:64910690c574	1684	}
AnnaBridge	145:64910690c574	1685
AnnaBridge	145:64910690c574	1686	/**
AnnaBridge	145:64910690c574	1687	* @brief Clear Channel 3 transfer complete flag.
AnnaBridge	145:64910690c574	1688	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	145:64910690c574	1689	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1690	* @retval None
AnnaBridge	145:64910690c574	1691	*/
AnnaBridge	145:64910690c574	1692	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1693	{
AnnaBridge	145:64910690c574	1694	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge	145:64910690c574	1695	}
AnnaBridge	145:64910690c574	1696
AnnaBridge	145:64910690c574	1697	/**
AnnaBridge	145:64910690c574	1698	* @brief Clear Channel 4 transfer complete flag.
AnnaBridge	145:64910690c574	1699	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	145:64910690c574	1700	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1701	* @retval None
AnnaBridge	145:64910690c574	1702	*/
AnnaBridge	145:64910690c574	1703	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1704	{
AnnaBridge	145:64910690c574	1705	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge	145:64910690c574	1706	}
AnnaBridge	145:64910690c574	1707
AnnaBridge	145:64910690c574	1708	/**
AnnaBridge	145:64910690c574	1709	* @brief Clear Channel 5 transfer complete flag.
AnnaBridge	145:64910690c574	1710	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	145:64910690c574	1711	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1712	* @retval None
AnnaBridge	145:64910690c574	1713	*/
AnnaBridge	145:64910690c574	1714	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1715	{
AnnaBridge	145:64910690c574	1716	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge	145:64910690c574	1717	}
AnnaBridge	145:64910690c574	1718
AnnaBridge	145:64910690c574	1719	/**
AnnaBridge	145:64910690c574	1720	* @brief Clear Channel 6 transfer complete flag.
AnnaBridge	145:64910690c574	1721	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	145:64910690c574	1722	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1723	* @retval None
AnnaBridge	145:64910690c574	1724	*/
AnnaBridge	145:64910690c574	1725	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1726	{
AnnaBridge	145:64910690c574	1727	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge	145:64910690c574	1728	}
AnnaBridge	145:64910690c574	1729
AnnaBridge	145:64910690c574	1730	/**
AnnaBridge	145:64910690c574	1731	* @brief Clear Channel 7 transfer complete flag.
AnnaBridge	145:64910690c574	1732	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	145:64910690c574	1733	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1734	* @retval None
AnnaBridge	145:64910690c574	1735	*/
AnnaBridge	145:64910690c574	1736	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1737	{
AnnaBridge	145:64910690c574	1738	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge	145:64910690c574	1739	}
AnnaBridge	145:64910690c574	1740
AnnaBridge	145:64910690c574	1741	/**
AnnaBridge	145:64910690c574	1742	* @brief Clear Channel 1 half transfer flag.
AnnaBridge	145:64910690c574	1743	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	145:64910690c574	1744	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1745	* @retval None
AnnaBridge	145:64910690c574	1746	*/
AnnaBridge	145:64910690c574	1747	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1748	{
AnnaBridge	145:64910690c574	1749	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge	145:64910690c574	1750	}
AnnaBridge	145:64910690c574	1751
AnnaBridge	145:64910690c574	1752	/**
AnnaBridge	145:64910690c574	1753	* @brief Clear Channel 2 half transfer flag.
AnnaBridge	145:64910690c574	1754	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	145:64910690c574	1755	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1756	* @retval None
AnnaBridge	145:64910690c574	1757	*/
AnnaBridge	145:64910690c574	1758	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1759	{
AnnaBridge	145:64910690c574	1760	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge	145:64910690c574	1761	}
AnnaBridge	145:64910690c574	1762
AnnaBridge	145:64910690c574	1763	/**
AnnaBridge	145:64910690c574	1764	* @brief Clear Channel 3 half transfer flag.
AnnaBridge	145:64910690c574	1765	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	145:64910690c574	1766	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1767	* @retval None
AnnaBridge	145:64910690c574	1768	*/
AnnaBridge	145:64910690c574	1769	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1770	{
AnnaBridge	145:64910690c574	1771	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge	145:64910690c574	1772	}
AnnaBridge	145:64910690c574	1773
AnnaBridge	145:64910690c574	1774	/**
AnnaBridge	145:64910690c574	1775	* @brief Clear Channel 4 half transfer flag.
AnnaBridge	145:64910690c574	1776	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	145:64910690c574	1777	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1778	* @retval None
AnnaBridge	145:64910690c574	1779	*/
AnnaBridge	145:64910690c574	1780	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1781	{
AnnaBridge	145:64910690c574	1782	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge	145:64910690c574	1783	}
AnnaBridge	145:64910690c574	1784
AnnaBridge	145:64910690c574	1785	/**
AnnaBridge	145:64910690c574	1786	* @brief Clear Channel 5 half transfer flag.
AnnaBridge	145:64910690c574	1787	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	145:64910690c574	1788	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1789	* @retval None
AnnaBridge	145:64910690c574	1790	*/
AnnaBridge	145:64910690c574	1791	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1792	{
AnnaBridge	145:64910690c574	1793	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge	145:64910690c574	1794	}
AnnaBridge	145:64910690c574	1795
AnnaBridge	145:64910690c574	1796	/**
AnnaBridge	145:64910690c574	1797	* @brief Clear Channel 6 half transfer flag.
AnnaBridge	145:64910690c574	1798	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	145:64910690c574	1799	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1800	* @retval None
AnnaBridge	145:64910690c574	1801	*/
AnnaBridge	145:64910690c574	1802	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1803	{
AnnaBridge	145:64910690c574	1804	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge	145:64910690c574	1805	}
AnnaBridge	145:64910690c574	1806
AnnaBridge	145:64910690c574	1807	/**
AnnaBridge	145:64910690c574	1808	* @brief Clear Channel 7 half transfer flag.
AnnaBridge	145:64910690c574	1809	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	145:64910690c574	1810	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1811	* @retval None
AnnaBridge	145:64910690c574	1812	*/
AnnaBridge	145:64910690c574	1813	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1814	{
AnnaBridge	145:64910690c574	1815	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge	145:64910690c574	1816	}
AnnaBridge	145:64910690c574	1817
AnnaBridge	145:64910690c574	1818	/**
AnnaBridge	145:64910690c574	1819	* @brief Clear Channel 1 transfer error flag.
AnnaBridge	145:64910690c574	1820	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	145:64910690c574	1821	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1822	* @retval None
AnnaBridge	145:64910690c574	1823	*/
AnnaBridge	145:64910690c574	1824	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1825	{
AnnaBridge	145:64910690c574	1826	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge	145:64910690c574	1827	}
AnnaBridge	145:64910690c574	1828
AnnaBridge	145:64910690c574	1829	/**
AnnaBridge	145:64910690c574	1830	* @brief Clear Channel 2 transfer error flag.
AnnaBridge	145:64910690c574	1831	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	145:64910690c574	1832	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1833	* @retval None
AnnaBridge	145:64910690c574	1834	*/
AnnaBridge	145:64910690c574	1835	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1836	{
AnnaBridge	145:64910690c574	1837	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge	145:64910690c574	1838	}
AnnaBridge	145:64910690c574	1839
AnnaBridge	145:64910690c574	1840	/**
AnnaBridge	145:64910690c574	1841	* @brief Clear Channel 3 transfer error flag.
AnnaBridge	145:64910690c574	1842	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	145:64910690c574	1843	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1844	* @retval None
AnnaBridge	145:64910690c574	1845	*/
AnnaBridge	145:64910690c574	1846	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1847	{
AnnaBridge	145:64910690c574	1848	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge	145:64910690c574	1849	}
AnnaBridge	145:64910690c574	1850
AnnaBridge	145:64910690c574	1851	/**
AnnaBridge	145:64910690c574	1852	* @brief Clear Channel 4 transfer error flag.
AnnaBridge	145:64910690c574	1853	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	145:64910690c574	1854	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1855	* @retval None
AnnaBridge	145:64910690c574	1856	*/
AnnaBridge	145:64910690c574	1857	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1858	{
AnnaBridge	145:64910690c574	1859	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge	145:64910690c574	1860	}
AnnaBridge	145:64910690c574	1861
AnnaBridge	145:64910690c574	1862	/**
AnnaBridge	145:64910690c574	1863	* @brief Clear Channel 5 transfer error flag.
AnnaBridge	145:64910690c574	1864	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	145:64910690c574	1865	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1866	* @retval None
AnnaBridge	145:64910690c574	1867	*/
AnnaBridge	145:64910690c574	1868	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1869	{
AnnaBridge	145:64910690c574	1870	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge	145:64910690c574	1871	}
AnnaBridge	145:64910690c574	1872
AnnaBridge	145:64910690c574	1873	/**
AnnaBridge	145:64910690c574	1874	* @brief Clear Channel 6 transfer error flag.
AnnaBridge	145:64910690c574	1875	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	145:64910690c574	1876	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1877	* @retval None
AnnaBridge	145:64910690c574	1878	*/
AnnaBridge	145:64910690c574	1879	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1880	{
AnnaBridge	145:64910690c574	1881	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge	145:64910690c574	1882	}
AnnaBridge	145:64910690c574	1883
AnnaBridge	145:64910690c574	1884	/**
AnnaBridge	145:64910690c574	1885	* @brief Clear Channel 7 transfer error flag.
AnnaBridge	145:64910690c574	1886	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	145:64910690c574	1887	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1888	* @retval None
AnnaBridge	145:64910690c574	1889	*/
AnnaBridge	145:64910690c574	1890	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1891	{
AnnaBridge	145:64910690c574	1892	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge	145:64910690c574	1893	}
AnnaBridge	145:64910690c574	1894
AnnaBridge	145:64910690c574	1895	/**
AnnaBridge	145:64910690c574	1896	* @}
AnnaBridge	145:64910690c574	1897	*/
AnnaBridge	145:64910690c574	1898
AnnaBridge	145:64910690c574	1899	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	145:64910690c574	1900	* @{
AnnaBridge	145:64910690c574	1901	*/
AnnaBridge	145:64910690c574	1902	/**
AnnaBridge	145:64910690c574	1903	* @brief Enable Transfer complete interrupt.
AnnaBridge	145:64910690c574	1904	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge	145:64910690c574	1905	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1906	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1907	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1908	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1909	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1910	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1911	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1912	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1913	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1914	* @retval None
AnnaBridge	145:64910690c574	1915	*/
AnnaBridge	145:64910690c574	1916	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1917	{
AnnaBridge	145:64910690c574	1918	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	145:64910690c574	1919	}
AnnaBridge	145:64910690c574	1920
AnnaBridge	145:64910690c574	1921	/**
AnnaBridge	145:64910690c574	1922	* @brief Enable Half transfer interrupt.
AnnaBridge	145:64910690c574	1923	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge	145:64910690c574	1924	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1925	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1926	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1927	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1928	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1929	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1930	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1931	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1932	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1933	* @retval None
AnnaBridge	145:64910690c574	1934	*/
AnnaBridge	145:64910690c574	1935	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1936	{
AnnaBridge	145:64910690c574	1937	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	145:64910690c574	1938	}
AnnaBridge	145:64910690c574	1939
AnnaBridge	145:64910690c574	1940	/**
AnnaBridge	145:64910690c574	1941	* @brief Enable Transfer error interrupt.
AnnaBridge	145:64910690c574	1942	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge	145:64910690c574	1943	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1944	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1945	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1946	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1947	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1948	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1949	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1950	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1951	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1952	* @retval None
AnnaBridge	145:64910690c574	1953	*/
AnnaBridge	145:64910690c574	1954	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1955	{
AnnaBridge	145:64910690c574	1956	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	145:64910690c574	1957	}
AnnaBridge	145:64910690c574	1958
AnnaBridge	145:64910690c574	1959	/**
AnnaBridge	145:64910690c574	1960	* @brief Disable Transfer complete interrupt.
AnnaBridge	145:64910690c574	1961	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge	145:64910690c574	1962	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1963	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1964	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1965	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1966	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1967	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1968	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1969	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1970	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1971	* @retval None
AnnaBridge	145:64910690c574	1972	*/
AnnaBridge	145:64910690c574	1973	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1974	{
AnnaBridge	145:64910690c574	1975	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	145:64910690c574	1976	}
AnnaBridge	145:64910690c574	1977
AnnaBridge	145:64910690c574	1978	/**
AnnaBridge	145:64910690c574	1979	* @brief Disable Half transfer interrupt.
AnnaBridge	145:64910690c574	1980	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge	145:64910690c574	1981	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1982	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1983	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1984	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1985	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1986	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1987	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1988	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1989	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1990	* @retval None
AnnaBridge	145:64910690c574	1991	*/
AnnaBridge	145:64910690c574	1992	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	1993	{
AnnaBridge	145:64910690c574	1994	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	145:64910690c574	1995	}
AnnaBridge	145:64910690c574	1996
AnnaBridge	145:64910690c574	1997	/**
AnnaBridge	145:64910690c574	1998	* @brief Disable Transfer error interrupt.
AnnaBridge	145:64910690c574	1999	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge	145:64910690c574	2000	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2001	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2002	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	2003	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	2004	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	2005	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	2006	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	2007	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	2008	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	2009	* @retval None
AnnaBridge	145:64910690c574	2010	*/
AnnaBridge	145:64910690c574	2011	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	2012	{
AnnaBridge	145:64910690c574	2013	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	145:64910690c574	2014	}
AnnaBridge	145:64910690c574	2015
AnnaBridge	145:64910690c574	2016	/**
AnnaBridge	145:64910690c574	2017	* @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge	145:64910690c574	2018	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	145:64910690c574	2019	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2020	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2021	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	2022	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	2023	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	2024	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	2025	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	2026	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	2027	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	2028	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2029	*/
AnnaBridge	145:64910690c574	2030	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	2031	{
AnnaBridge	145:64910690c574	2032	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	2033	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge	145:64910690c574	2034	}
AnnaBridge	145:64910690c574	2035
AnnaBridge	145:64910690c574	2036	/**
AnnaBridge	145:64910690c574	2037	* @brief Check if Half transfer Interrupt is enabled.
AnnaBridge	145:64910690c574	2038	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	145:64910690c574	2039	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2040	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2041	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	2042	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	2043	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	2044	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	2045	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	2046	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	2047	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	2048	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2049	*/
AnnaBridge	145:64910690c574	2050	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	2051	{
AnnaBridge	145:64910690c574	2052	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	2053	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge	145:64910690c574	2054	}
AnnaBridge	145:64910690c574	2055
AnnaBridge	145:64910690c574	2056	/**
AnnaBridge	145:64910690c574	2057	* @brief Check if Transfer error Interrupt is enabled.
AnnaBridge	145:64910690c574	2058	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	145:64910690c574	2059	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2060	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2061	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	2062	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	2063	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	2064	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	2065	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	2066	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	2067	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	2068	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2069	*/
AnnaBridge	145:64910690c574	2070	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	145:64910690c574	2071	{
AnnaBridge	145:64910690c574	2072	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	145:64910690c574	2073	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge	145:64910690c574	2074	}
AnnaBridge	145:64910690c574	2075
AnnaBridge	145:64910690c574	2076	/**
AnnaBridge	145:64910690c574	2077	* @}
AnnaBridge	145:64910690c574	2078	*/
AnnaBridge	145:64910690c574	2079
AnnaBridge	145:64910690c574	2080	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	2081	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	145:64910690c574	2082	* @{
AnnaBridge	145:64910690c574	2083	*/
AnnaBridge	145:64910690c574	2084
AnnaBridge	145:64910690c574	2085	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	145:64910690c574	2086	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge	145:64910690c574	2087	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	145:64910690c574	2088
AnnaBridge	145:64910690c574	2089	/**
AnnaBridge	145:64910690c574	2090	* @}
AnnaBridge	145:64910690c574	2091	*/
AnnaBridge	145:64910690c574	2092	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	2093
AnnaBridge	145:64910690c574	2094	/**
AnnaBridge	145:64910690c574	2095	* @}
AnnaBridge	145:64910690c574	2096	*/
AnnaBridge	145:64910690c574	2097
AnnaBridge	145:64910690c574	2098	/**
AnnaBridge	145:64910690c574	2099	* @}
AnnaBridge	145:64910690c574	2100	*/
AnnaBridge	145:64910690c574	2101
AnnaBridge	145:64910690c574	2102	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	145:64910690c574	2103
AnnaBridge	145:64910690c574	2104	/**
AnnaBridge	145:64910690c574	2105	* @}
AnnaBridge	145:64910690c574	2106	*/
AnnaBridge	145:64910690c574	2107
AnnaBridge	145:64910690c574	2108	#ifdef __cplusplus
AnnaBridge	145:64910690c574	2109	}
AnnaBridge	145:64910690c574	2110	#endif
AnnaBridge	145:64910690c574	2111
AnnaBridge	145:64910690c574	2112	#endif /* __STM32L4xx_LL_DMA_H */
AnnaBridge	145:64910690c574	2113
AnnaBridge	145:64910690c574	2114	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/