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mbed 2

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TARGET_VK_RZ_A1H/core_ca.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
165:d1b4690b3f8b
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /**************************************************************************//**
AnnaBridge 165:d1b4690b3f8b 2 * @file core_ca.h
AnnaBridge 165:d1b4690b3f8b 3 * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
AnnaBridge 165:d1b4690b3f8b 4 * @version V1.00
AnnaBridge 165:d1b4690b3f8b 5 * @date 22. Feb 2017
AnnaBridge 165:d1b4690b3f8b 6 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 7 /*
AnnaBridge 165:d1b4690b3f8b 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 165:d1b4690b3f8b 9 *
AnnaBridge 165:d1b4690b3f8b 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 165:d1b4690b3f8b 11 *
AnnaBridge 165:d1b4690b3f8b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 165:d1b4690b3f8b 13 * not use this file except in compliance with the License.
AnnaBridge 165:d1b4690b3f8b 14 * You may obtain a copy of the License at
AnnaBridge 165:d1b4690b3f8b 15 *
AnnaBridge 165:d1b4690b3f8b 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 165:d1b4690b3f8b 17 *
AnnaBridge 165:d1b4690b3f8b 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 165:d1b4690b3f8b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 165:d1b4690b3f8b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 165:d1b4690b3f8b 21 * See the License for the specific language governing permissions and
AnnaBridge 165:d1b4690b3f8b 22 * limitations under the License.
AnnaBridge 165:d1b4690b3f8b 23 */
AnnaBridge 165:d1b4690b3f8b 24
AnnaBridge 165:d1b4690b3f8b 25 #if defined ( __ICCARM__ )
AnnaBridge 165:d1b4690b3f8b 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 165:d1b4690b3f8b 27 #elif defined (__clang__)
AnnaBridge 165:d1b4690b3f8b 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 165:d1b4690b3f8b 29 #endif
AnnaBridge 165:d1b4690b3f8b 30
AnnaBridge 165:d1b4690b3f8b 31 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 32 extern "C" {
AnnaBridge 165:d1b4690b3f8b 33 #endif
AnnaBridge 165:d1b4690b3f8b 34
AnnaBridge 165:d1b4690b3f8b 35 #ifndef __CORE_CA_H_GENERIC
AnnaBridge 165:d1b4690b3f8b 36 #define __CORE_CA_H_GENERIC
AnnaBridge 165:d1b4690b3f8b 37
AnnaBridge 165:d1b4690b3f8b 38
AnnaBridge 165:d1b4690b3f8b 39 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 40 * CMSIS definitions
AnnaBridge 165:d1b4690b3f8b 41 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 42
AnnaBridge 165:d1b4690b3f8b 43 /* CMSIS CA definitions */
AnnaBridge 165:d1b4690b3f8b 44 #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */
AnnaBridge 165:d1b4690b3f8b 45 #define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
AnnaBridge 165:d1b4690b3f8b 46 #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 165:d1b4690b3f8b 47 __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
AnnaBridge 165:d1b4690b3f8b 48
AnnaBridge 165:d1b4690b3f8b 49 #if defined ( __CC_ARM )
AnnaBridge 165:d1b4690b3f8b 50 #if defined __TARGET_FPU_VFP
AnnaBridge 165:d1b4690b3f8b 51 #if (__FPU_PRESENT == 1)
AnnaBridge 165:d1b4690b3f8b 52 #define __FPU_USED 1U
AnnaBridge 165:d1b4690b3f8b 53 #else
AnnaBridge 165:d1b4690b3f8b 54 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 55 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 56 #endif
AnnaBridge 165:d1b4690b3f8b 57 #else
AnnaBridge 165:d1b4690b3f8b 58 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 59 #endif
AnnaBridge 165:d1b4690b3f8b 60
AnnaBridge 165:d1b4690b3f8b 61 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 165:d1b4690b3f8b 62 #if defined __ARM_PCS_VFP
AnnaBridge 165:d1b4690b3f8b 63 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 64 #define __FPU_USED 1U
AnnaBridge 165:d1b4690b3f8b 65 #else
AnnaBridge 165:d1b4690b3f8b 66 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 67 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 68 #endif
AnnaBridge 165:d1b4690b3f8b 69 #else
AnnaBridge 165:d1b4690b3f8b 70 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 71 #endif
AnnaBridge 165:d1b4690b3f8b 72
AnnaBridge 165:d1b4690b3f8b 73 #elif defined ( __ICCARM__ )
AnnaBridge 165:d1b4690b3f8b 74 #if defined __ARMVFP__
AnnaBridge 165:d1b4690b3f8b 75 #if (__FPU_PRESENT == 1)
AnnaBridge 165:d1b4690b3f8b 76 #define __FPU_USED 1U
AnnaBridge 165:d1b4690b3f8b 77 #else
AnnaBridge 165:d1b4690b3f8b 78 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 79 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 80 #endif
AnnaBridge 165:d1b4690b3f8b 81 #else
AnnaBridge 165:d1b4690b3f8b 82 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 83 #endif
AnnaBridge 165:d1b4690b3f8b 84
AnnaBridge 165:d1b4690b3f8b 85 #elif defined ( __TMS470__ )
AnnaBridge 165:d1b4690b3f8b 86 #if defined __TI_VFP_SUPPORT__
AnnaBridge 165:d1b4690b3f8b 87 #if (__FPU_PRESENT == 1)
AnnaBridge 165:d1b4690b3f8b 88 #define __FPU_USED 1U
AnnaBridge 165:d1b4690b3f8b 89 #else
AnnaBridge 165:d1b4690b3f8b 90 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 91 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 92 #endif
AnnaBridge 165:d1b4690b3f8b 93 #else
AnnaBridge 165:d1b4690b3f8b 94 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 95 #endif
AnnaBridge 165:d1b4690b3f8b 96
AnnaBridge 165:d1b4690b3f8b 97 #elif defined ( __GNUC__ )
AnnaBridge 165:d1b4690b3f8b 98 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 165:d1b4690b3f8b 99 #if (__FPU_PRESENT == 1)
AnnaBridge 165:d1b4690b3f8b 100 #define __FPU_USED 1U
AnnaBridge 165:d1b4690b3f8b 101 #else
AnnaBridge 165:d1b4690b3f8b 102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 103 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 104 #endif
AnnaBridge 165:d1b4690b3f8b 105 #else
AnnaBridge 165:d1b4690b3f8b 106 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 107 #endif
AnnaBridge 165:d1b4690b3f8b 108
AnnaBridge 165:d1b4690b3f8b 109 #elif defined ( __TASKING__ )
AnnaBridge 165:d1b4690b3f8b 110 #if defined __FPU_VFP__
AnnaBridge 165:d1b4690b3f8b 111 #if (__FPU_PRESENT == 1)
AnnaBridge 165:d1b4690b3f8b 112 #define __FPU_USED 1U
AnnaBridge 165:d1b4690b3f8b 113 #else
AnnaBridge 165:d1b4690b3f8b 114 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 115 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 116 #endif
AnnaBridge 165:d1b4690b3f8b 117 #else
AnnaBridge 165:d1b4690b3f8b 118 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 119 #endif
AnnaBridge 165:d1b4690b3f8b 120 #endif
AnnaBridge 165:d1b4690b3f8b 121
AnnaBridge 165:d1b4690b3f8b 122 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 165:d1b4690b3f8b 123
AnnaBridge 165:d1b4690b3f8b 124 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 125 }
AnnaBridge 165:d1b4690b3f8b 126 #endif
AnnaBridge 165:d1b4690b3f8b 127
AnnaBridge 165:d1b4690b3f8b 128 #endif /* __CORE_CA_H_GENERIC */
AnnaBridge 165:d1b4690b3f8b 129
AnnaBridge 165:d1b4690b3f8b 130 #ifndef __CMSIS_GENERIC
AnnaBridge 165:d1b4690b3f8b 131
AnnaBridge 165:d1b4690b3f8b 132 #ifndef __CORE_CA_H_DEPENDANT
AnnaBridge 165:d1b4690b3f8b 133 #define __CORE_CA_H_DEPENDANT
AnnaBridge 165:d1b4690b3f8b 134
AnnaBridge 165:d1b4690b3f8b 135 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 136 extern "C" {
AnnaBridge 165:d1b4690b3f8b 137 #endif
AnnaBridge 165:d1b4690b3f8b 138
AnnaBridge 165:d1b4690b3f8b 139 /* check device defines and use defaults */
AnnaBridge 165:d1b4690b3f8b 140 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 165:d1b4690b3f8b 141 #ifndef __CA_REV
AnnaBridge 165:d1b4690b3f8b 142 #define __CA_REV 0x0000U
AnnaBridge 165:d1b4690b3f8b 143 #warning "__CA_REV not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 144 #endif
AnnaBridge 165:d1b4690b3f8b 145
AnnaBridge 165:d1b4690b3f8b 146 #ifndef __FPU_PRESENT
AnnaBridge 165:d1b4690b3f8b 147 #define __FPU_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 148 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 149 #endif
AnnaBridge 165:d1b4690b3f8b 150
AnnaBridge 165:d1b4690b3f8b 151 #ifndef __GIC_PRESENT
AnnaBridge 165:d1b4690b3f8b 152 #define __GIC_PRESENT 1U
AnnaBridge 165:d1b4690b3f8b 153 #warning "__GIC_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 154 #endif
AnnaBridge 165:d1b4690b3f8b 155
AnnaBridge 165:d1b4690b3f8b 156 #ifndef __TIM_PRESENT
AnnaBridge 165:d1b4690b3f8b 157 #define __TIM_PRESENT 1U
AnnaBridge 165:d1b4690b3f8b 158 #warning "__TIM_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 159 #endif
AnnaBridge 165:d1b4690b3f8b 160
AnnaBridge 165:d1b4690b3f8b 161 #ifndef __L2C_PRESENT
AnnaBridge 165:d1b4690b3f8b 162 #define __L2C_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 163 #warning "__L2C_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 164 #endif
AnnaBridge 165:d1b4690b3f8b 165 #endif
AnnaBridge 165:d1b4690b3f8b 166
AnnaBridge 165:d1b4690b3f8b 167 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 165:d1b4690b3f8b 168 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 169 #define __I volatile /*!< \brief Defines 'read only' permissions */
AnnaBridge 165:d1b4690b3f8b 170 #else
AnnaBridge 165:d1b4690b3f8b 171 #define __I volatile const /*!< \brief Defines 'read only' permissions */
AnnaBridge 165:d1b4690b3f8b 172 #endif
AnnaBridge 165:d1b4690b3f8b 173 #define __O volatile /*!< \brief Defines 'write only' permissions */
AnnaBridge 165:d1b4690b3f8b 174 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
AnnaBridge 165:d1b4690b3f8b 175
AnnaBridge 165:d1b4690b3f8b 176 /* following defines should be used for structure members */
AnnaBridge 165:d1b4690b3f8b 177 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 178 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 179 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 180 #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
AnnaBridge 165:d1b4690b3f8b 181
AnnaBridge 165:d1b4690b3f8b 182 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 183 * Register Abstraction
AnnaBridge 165:d1b4690b3f8b 184 Core Register contain:
AnnaBridge 165:d1b4690b3f8b 185 - CPSR
AnnaBridge 165:d1b4690b3f8b 186 - CP15 Registers
AnnaBridge 165:d1b4690b3f8b 187 - L2C-310 Cache Controller
AnnaBridge 165:d1b4690b3f8b 188 - Generic Interrupt Controller Distributor
AnnaBridge 165:d1b4690b3f8b 189 - Generic Interrupt Controller Interface
AnnaBridge 165:d1b4690b3f8b 190 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 191
AnnaBridge 165:d1b4690b3f8b 192 /* Core Register CPSR */
AnnaBridge 165:d1b4690b3f8b 193 typedef union
AnnaBridge 165:d1b4690b3f8b 194 {
AnnaBridge 165:d1b4690b3f8b 195 struct
AnnaBridge 165:d1b4690b3f8b 196 {
AnnaBridge 165:d1b4690b3f8b 197 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
AnnaBridge 165:d1b4690b3f8b 198 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
AnnaBridge 165:d1b4690b3f8b 199 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
AnnaBridge 165:d1b4690b3f8b 200 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
AnnaBridge 165:d1b4690b3f8b 201 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
AnnaBridge 165:d1b4690b3f8b 202 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
AnnaBridge 165:d1b4690b3f8b 203 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
AnnaBridge 165:d1b4690b3f8b 204 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
AnnaBridge 165:d1b4690b3f8b 205 RESERVED(0:4, uint32_t)
AnnaBridge 165:d1b4690b3f8b 206 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
AnnaBridge 165:d1b4690b3f8b 207 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
AnnaBridge 165:d1b4690b3f8b 208 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
AnnaBridge 165:d1b4690b3f8b 209 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
AnnaBridge 165:d1b4690b3f8b 210 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
AnnaBridge 165:d1b4690b3f8b 211 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
AnnaBridge 165:d1b4690b3f8b 212 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
AnnaBridge 165:d1b4690b3f8b 213 } b; /*!< \brief Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 214 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 165:d1b4690b3f8b 215 } CPSR_Type;
AnnaBridge 165:d1b4690b3f8b 216
AnnaBridge 165:d1b4690b3f8b 217
AnnaBridge 165:d1b4690b3f8b 218
AnnaBridge 165:d1b4690b3f8b 219 /* CPSR Register Definitions */
AnnaBridge 165:d1b4690b3f8b 220 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
AnnaBridge 165:d1b4690b3f8b 221 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
AnnaBridge 165:d1b4690b3f8b 222
AnnaBridge 165:d1b4690b3f8b 223 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
AnnaBridge 165:d1b4690b3f8b 224 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
AnnaBridge 165:d1b4690b3f8b 225
AnnaBridge 165:d1b4690b3f8b 226 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
AnnaBridge 165:d1b4690b3f8b 227 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
AnnaBridge 165:d1b4690b3f8b 228
AnnaBridge 165:d1b4690b3f8b 229 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
AnnaBridge 165:d1b4690b3f8b 230 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
AnnaBridge 165:d1b4690b3f8b 231
AnnaBridge 165:d1b4690b3f8b 232 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
AnnaBridge 165:d1b4690b3f8b 233 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
AnnaBridge 165:d1b4690b3f8b 234
AnnaBridge 165:d1b4690b3f8b 235 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
AnnaBridge 165:d1b4690b3f8b 236 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
AnnaBridge 165:d1b4690b3f8b 237
AnnaBridge 165:d1b4690b3f8b 238 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
AnnaBridge 165:d1b4690b3f8b 239 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
AnnaBridge 165:d1b4690b3f8b 240
AnnaBridge 165:d1b4690b3f8b 241 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
AnnaBridge 165:d1b4690b3f8b 242 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
AnnaBridge 165:d1b4690b3f8b 243
AnnaBridge 165:d1b4690b3f8b 244 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
AnnaBridge 165:d1b4690b3f8b 245 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
AnnaBridge 165:d1b4690b3f8b 246
AnnaBridge 165:d1b4690b3f8b 247 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
AnnaBridge 165:d1b4690b3f8b 248 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
AnnaBridge 165:d1b4690b3f8b 249
AnnaBridge 165:d1b4690b3f8b 250 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
AnnaBridge 165:d1b4690b3f8b 251 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
AnnaBridge 165:d1b4690b3f8b 252
AnnaBridge 165:d1b4690b3f8b 253 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
AnnaBridge 165:d1b4690b3f8b 254 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
AnnaBridge 165:d1b4690b3f8b 255
AnnaBridge 165:d1b4690b3f8b 256 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
AnnaBridge 165:d1b4690b3f8b 257 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
AnnaBridge 165:d1b4690b3f8b 258
AnnaBridge 165:d1b4690b3f8b 259 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
AnnaBridge 165:d1b4690b3f8b 260 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
AnnaBridge 165:d1b4690b3f8b 261
AnnaBridge 165:d1b4690b3f8b 262 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
AnnaBridge 165:d1b4690b3f8b 263 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
AnnaBridge 165:d1b4690b3f8b 264
AnnaBridge 165:d1b4690b3f8b 265 #define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */
AnnaBridge 165:d1b4690b3f8b 266 #define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
AnnaBridge 165:d1b4690b3f8b 267 #define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */
AnnaBridge 165:d1b4690b3f8b 268 #define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */
AnnaBridge 165:d1b4690b3f8b 269 #define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */
AnnaBridge 165:d1b4690b3f8b 270 #define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */
AnnaBridge 165:d1b4690b3f8b 271 #define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */
AnnaBridge 165:d1b4690b3f8b 272 #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */
AnnaBridge 165:d1b4690b3f8b 273 #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */
AnnaBridge 165:d1b4690b3f8b 274
AnnaBridge 165:d1b4690b3f8b 275 /* CP15 Register SCTLR */
AnnaBridge 165:d1b4690b3f8b 276 typedef union
AnnaBridge 165:d1b4690b3f8b 277 {
AnnaBridge 165:d1b4690b3f8b 278 struct
AnnaBridge 165:d1b4690b3f8b 279 {
AnnaBridge 165:d1b4690b3f8b 280 uint32_t M:1; /*!< \brief bit: 0 MMU enable */
AnnaBridge 165:d1b4690b3f8b 281 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
AnnaBridge 165:d1b4690b3f8b 282 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
AnnaBridge 165:d1b4690b3f8b 283 RESERVED(0:2, uint32_t)
AnnaBridge 165:d1b4690b3f8b 284 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
AnnaBridge 165:d1b4690b3f8b 285 RESERVED(1:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 286 uint32_t B:1; /*!< \brief bit: 7 Endianness model */
AnnaBridge 165:d1b4690b3f8b 287 RESERVED(2:2, uint32_t)
AnnaBridge 165:d1b4690b3f8b 288 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
AnnaBridge 165:d1b4690b3f8b 289 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
AnnaBridge 165:d1b4690b3f8b 290 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
AnnaBridge 165:d1b4690b3f8b 291 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
AnnaBridge 165:d1b4690b3f8b 292 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
AnnaBridge 165:d1b4690b3f8b 293 RESERVED(3:2, uint32_t)
AnnaBridge 165:d1b4690b3f8b 294 uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
AnnaBridge 165:d1b4690b3f8b 295 RESERVED(4:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 296 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
AnnaBridge 165:d1b4690b3f8b 297 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
AnnaBridge 165:d1b4690b3f8b 298 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
AnnaBridge 165:d1b4690b3f8b 299 uint32_t U:1; /*!< \brief bit: 22 Alignment model */
AnnaBridge 165:d1b4690b3f8b 300 RESERVED(5:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 301 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
AnnaBridge 165:d1b4690b3f8b 302 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
AnnaBridge 165:d1b4690b3f8b 303 RESERVED(6:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 304 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
AnnaBridge 165:d1b4690b3f8b 305 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
AnnaBridge 165:d1b4690b3f8b 306 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
AnnaBridge 165:d1b4690b3f8b 307 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
AnnaBridge 165:d1b4690b3f8b 308 RESERVED(7:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 309 } b; /*!< \brief Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 310 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 165:d1b4690b3f8b 311 } SCTLR_Type;
AnnaBridge 165:d1b4690b3f8b 312
AnnaBridge 165:d1b4690b3f8b 313 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
AnnaBridge 165:d1b4690b3f8b 314 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
AnnaBridge 165:d1b4690b3f8b 315
AnnaBridge 165:d1b4690b3f8b 316 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
AnnaBridge 165:d1b4690b3f8b 317 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
AnnaBridge 165:d1b4690b3f8b 318
AnnaBridge 165:d1b4690b3f8b 319 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
AnnaBridge 165:d1b4690b3f8b 320 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
AnnaBridge 165:d1b4690b3f8b 321
AnnaBridge 165:d1b4690b3f8b 322 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
AnnaBridge 165:d1b4690b3f8b 323 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
AnnaBridge 165:d1b4690b3f8b 324
AnnaBridge 165:d1b4690b3f8b 325 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
AnnaBridge 165:d1b4690b3f8b 326 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
AnnaBridge 165:d1b4690b3f8b 327
AnnaBridge 165:d1b4690b3f8b 328 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
AnnaBridge 165:d1b4690b3f8b 329 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
AnnaBridge 165:d1b4690b3f8b 330
AnnaBridge 165:d1b4690b3f8b 331 #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
AnnaBridge 165:d1b4690b3f8b 332 #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
AnnaBridge 165:d1b4690b3f8b 333
AnnaBridge 165:d1b4690b3f8b 334 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
AnnaBridge 165:d1b4690b3f8b 335 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
AnnaBridge 165:d1b4690b3f8b 336
AnnaBridge 165:d1b4690b3f8b 337 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
AnnaBridge 165:d1b4690b3f8b 338 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
AnnaBridge 165:d1b4690b3f8b 339
AnnaBridge 165:d1b4690b3f8b 340 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
AnnaBridge 165:d1b4690b3f8b 341 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
AnnaBridge 165:d1b4690b3f8b 342
AnnaBridge 165:d1b4690b3f8b 343 #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
AnnaBridge 165:d1b4690b3f8b 344 #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
AnnaBridge 165:d1b4690b3f8b 345
AnnaBridge 165:d1b4690b3f8b 346 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
AnnaBridge 165:d1b4690b3f8b 347 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
AnnaBridge 165:d1b4690b3f8b 348
AnnaBridge 165:d1b4690b3f8b 349 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
AnnaBridge 165:d1b4690b3f8b 350 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
AnnaBridge 165:d1b4690b3f8b 351
AnnaBridge 165:d1b4690b3f8b 352 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
AnnaBridge 165:d1b4690b3f8b 353 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
AnnaBridge 165:d1b4690b3f8b 354
AnnaBridge 165:d1b4690b3f8b 355 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
AnnaBridge 165:d1b4690b3f8b 356 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
AnnaBridge 165:d1b4690b3f8b 357
AnnaBridge 165:d1b4690b3f8b 358 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
AnnaBridge 165:d1b4690b3f8b 359 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
AnnaBridge 165:d1b4690b3f8b 360
AnnaBridge 165:d1b4690b3f8b 361 #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
AnnaBridge 165:d1b4690b3f8b 362 #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
AnnaBridge 165:d1b4690b3f8b 363
AnnaBridge 165:d1b4690b3f8b 364 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
AnnaBridge 165:d1b4690b3f8b 365 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
AnnaBridge 165:d1b4690b3f8b 366
AnnaBridge 165:d1b4690b3f8b 367 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
AnnaBridge 165:d1b4690b3f8b 368 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
AnnaBridge 165:d1b4690b3f8b 369
AnnaBridge 165:d1b4690b3f8b 370 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
AnnaBridge 165:d1b4690b3f8b 371 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
AnnaBridge 165:d1b4690b3f8b 372
AnnaBridge 165:d1b4690b3f8b 373 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
AnnaBridge 165:d1b4690b3f8b 374 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
AnnaBridge 165:d1b4690b3f8b 375
AnnaBridge 165:d1b4690b3f8b 376 /* CP15 Register ACTLR */
AnnaBridge 165:d1b4690b3f8b 377 typedef union
AnnaBridge 165:d1b4690b3f8b 378 {
AnnaBridge 165:d1b4690b3f8b 379 #if __CORTEX_A == 5 || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 380 /** \brief Structure used for bit access on Cortex-A5 */
AnnaBridge 165:d1b4690b3f8b 381 struct
AnnaBridge 165:d1b4690b3f8b 382 {
AnnaBridge 165:d1b4690b3f8b 383 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
AnnaBridge 165:d1b4690b3f8b 384 RESERVED(0:5, uint32_t)
AnnaBridge 165:d1b4690b3f8b 385 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
AnnaBridge 165:d1b4690b3f8b 386 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
AnnaBridge 165:d1b4690b3f8b 387 RESERVED(1:2, uint32_t)
AnnaBridge 165:d1b4690b3f8b 388 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
AnnaBridge 165:d1b4690b3f8b 389 uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */
AnnaBridge 165:d1b4690b3f8b 390 uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
AnnaBridge 165:d1b4690b3f8b 391 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
AnnaBridge 165:d1b4690b3f8b 392 uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */
AnnaBridge 165:d1b4690b3f8b 393 uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */
AnnaBridge 165:d1b4690b3f8b 394 uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */
AnnaBridge 165:d1b4690b3f8b 395 RESERVED(3:9, uint32_t)
AnnaBridge 165:d1b4690b3f8b 396 uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */
AnnaBridge 165:d1b4690b3f8b 397 RESERVED(7:3, uint32_t)
AnnaBridge 165:d1b4690b3f8b 398 } b;
AnnaBridge 165:d1b4690b3f8b 399 #endif
AnnaBridge 165:d1b4690b3f8b 400 #if __CORTEX_A == 7 || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 401 /** \brief Structure used for bit access on Cortex-A7 */
AnnaBridge 165:d1b4690b3f8b 402 struct
AnnaBridge 165:d1b4690b3f8b 403 {
AnnaBridge 165:d1b4690b3f8b 404 RESERVED(0:6, uint32_t)
AnnaBridge 165:d1b4690b3f8b 405 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
AnnaBridge 165:d1b4690b3f8b 406 RESERVED(1:3, uint32_t)
AnnaBridge 165:d1b4690b3f8b 407 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
AnnaBridge 165:d1b4690b3f8b 408 uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */
AnnaBridge 165:d1b4690b3f8b 409 uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
AnnaBridge 165:d1b4690b3f8b 410 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
AnnaBridge 165:d1b4690b3f8b 411 uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */
AnnaBridge 165:d1b4690b3f8b 412 RESERVED(3:12, uint32_t)
AnnaBridge 165:d1b4690b3f8b 413 uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */
AnnaBridge 165:d1b4690b3f8b 414 RESERVED(7:3, uint32_t)
AnnaBridge 165:d1b4690b3f8b 415 } b;
AnnaBridge 165:d1b4690b3f8b 416 #endif
AnnaBridge 165:d1b4690b3f8b 417 #if __CORTEX_A == 9 || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 418 /** \brief Structure used for bit access on Cortex-A9 */
AnnaBridge 165:d1b4690b3f8b 419 struct
AnnaBridge 165:d1b4690b3f8b 420 {
AnnaBridge 165:d1b4690b3f8b 421 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
AnnaBridge 165:d1b4690b3f8b 422 RESERVED(0:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 423 uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */
AnnaBridge 165:d1b4690b3f8b 424 uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */
AnnaBridge 165:d1b4690b3f8b 425 RESERVED(1:2, uint32_t)
AnnaBridge 165:d1b4690b3f8b 426 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
AnnaBridge 165:d1b4690b3f8b 427 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
AnnaBridge 165:d1b4690b3f8b 428 uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */
AnnaBridge 165:d1b4690b3f8b 429 uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */
AnnaBridge 165:d1b4690b3f8b 430 RESERVED(7:22, uint32_t)
AnnaBridge 165:d1b4690b3f8b 431 } b;
AnnaBridge 165:d1b4690b3f8b 432 #endif
AnnaBridge 165:d1b4690b3f8b 433 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 165:d1b4690b3f8b 434 } ACTLR_Type;
AnnaBridge 165:d1b4690b3f8b 435
AnnaBridge 165:d1b4690b3f8b 436 #define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */
AnnaBridge 165:d1b4690b3f8b 437 #define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */
AnnaBridge 165:d1b4690b3f8b 438
AnnaBridge 165:d1b4690b3f8b 439 #define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */
AnnaBridge 165:d1b4690b3f8b 440 #define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */
AnnaBridge 165:d1b4690b3f8b 441
AnnaBridge 165:d1b4690b3f8b 442 #define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */
AnnaBridge 165:d1b4690b3f8b 443 #define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */
AnnaBridge 165:d1b4690b3f8b 444
AnnaBridge 165:d1b4690b3f8b 445 #define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */
AnnaBridge 165:d1b4690b3f8b 446 #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */
AnnaBridge 165:d1b4690b3f8b 447
AnnaBridge 165:d1b4690b3f8b 448 #define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */
AnnaBridge 165:d1b4690b3f8b 449 #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */
AnnaBridge 165:d1b4690b3f8b 450
AnnaBridge 165:d1b4690b3f8b 451 #define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */
AnnaBridge 165:d1b4690b3f8b 452 #define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */
AnnaBridge 165:d1b4690b3f8b 453
AnnaBridge 165:d1b4690b3f8b 454 #define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */
AnnaBridge 165:d1b4690b3f8b 455 #define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */
AnnaBridge 165:d1b4690b3f8b 456
AnnaBridge 165:d1b4690b3f8b 457 #define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */
AnnaBridge 165:d1b4690b3f8b 458 #define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */
AnnaBridge 165:d1b4690b3f8b 459
AnnaBridge 165:d1b4690b3f8b 460 #define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */
AnnaBridge 165:d1b4690b3f8b 461 #define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */
AnnaBridge 165:d1b4690b3f8b 462
AnnaBridge 165:d1b4690b3f8b 463 #define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */
AnnaBridge 165:d1b4690b3f8b 464 #define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */
AnnaBridge 165:d1b4690b3f8b 465
AnnaBridge 165:d1b4690b3f8b 466 #define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */
AnnaBridge 165:d1b4690b3f8b 467 #define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */
AnnaBridge 165:d1b4690b3f8b 468
AnnaBridge 165:d1b4690b3f8b 469 #define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */
AnnaBridge 165:d1b4690b3f8b 470 #define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */
AnnaBridge 165:d1b4690b3f8b 471
AnnaBridge 165:d1b4690b3f8b 472 #define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */
AnnaBridge 165:d1b4690b3f8b 473 #define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */
AnnaBridge 165:d1b4690b3f8b 474
AnnaBridge 165:d1b4690b3f8b 475 #define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */
AnnaBridge 165:d1b4690b3f8b 476 #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */
AnnaBridge 165:d1b4690b3f8b 477
AnnaBridge 165:d1b4690b3f8b 478 #define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */
AnnaBridge 165:d1b4690b3f8b 479 #define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */
AnnaBridge 165:d1b4690b3f8b 480
AnnaBridge 165:d1b4690b3f8b 481 #define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */
AnnaBridge 165:d1b4690b3f8b 482 #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */
AnnaBridge 165:d1b4690b3f8b 483
AnnaBridge 165:d1b4690b3f8b 484 #define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */
AnnaBridge 165:d1b4690b3f8b 485 #define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */
AnnaBridge 165:d1b4690b3f8b 486
AnnaBridge 165:d1b4690b3f8b 487 #define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */
AnnaBridge 165:d1b4690b3f8b 488 #define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */
AnnaBridge 165:d1b4690b3f8b 489
AnnaBridge 165:d1b4690b3f8b 490 #define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */
AnnaBridge 165:d1b4690b3f8b 491 #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */
AnnaBridge 165:d1b4690b3f8b 492
AnnaBridge 165:d1b4690b3f8b 493 /* CP15 Register CPACR */
AnnaBridge 165:d1b4690b3f8b 494 typedef union
AnnaBridge 165:d1b4690b3f8b 495 {
AnnaBridge 165:d1b4690b3f8b 496 struct
AnnaBridge 165:d1b4690b3f8b 497 {
AnnaBridge 165:d1b4690b3f8b 498 uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */
AnnaBridge 165:d1b4690b3f8b 499 uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */
AnnaBridge 165:d1b4690b3f8b 500 uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */
AnnaBridge 165:d1b4690b3f8b 501 uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */
AnnaBridge 165:d1b4690b3f8b 502 uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */
AnnaBridge 165:d1b4690b3f8b 503 uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */
AnnaBridge 165:d1b4690b3f8b 504 uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */
AnnaBridge 165:d1b4690b3f8b 505 uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */
AnnaBridge 165:d1b4690b3f8b 506 uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */
AnnaBridge 165:d1b4690b3f8b 507 uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */
AnnaBridge 165:d1b4690b3f8b 508 uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
AnnaBridge 165:d1b4690b3f8b 509 uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
AnnaBridge 165:d1b4690b3f8b 510 uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */
AnnaBridge 165:d1b4690b3f8b 511 uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */
AnnaBridge 165:d1b4690b3f8b 512 uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */
AnnaBridge 165:d1b4690b3f8b 513 RESERVED(0:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 514 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
AnnaBridge 165:d1b4690b3f8b 515 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
AnnaBridge 165:d1b4690b3f8b 516 } b; /*!< \brief Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 517 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 165:d1b4690b3f8b 518 } CPACR_Type;
AnnaBridge 165:d1b4690b3f8b 519
AnnaBridge 165:d1b4690b3f8b 520 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
AnnaBridge 165:d1b4690b3f8b 521 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
AnnaBridge 165:d1b4690b3f8b 522
AnnaBridge 165:d1b4690b3f8b 523 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
AnnaBridge 165:d1b4690b3f8b 524 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
AnnaBridge 165:d1b4690b3f8b 525
AnnaBridge 165:d1b4690b3f8b 526 #define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */
AnnaBridge 165:d1b4690b3f8b 527 #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
AnnaBridge 165:d1b4690b3f8b 528
AnnaBridge 165:d1b4690b3f8b 529 #define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */
AnnaBridge 165:d1b4690b3f8b 530 #define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */
AnnaBridge 165:d1b4690b3f8b 531
AnnaBridge 165:d1b4690b3f8b 532 #define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */
AnnaBridge 165:d1b4690b3f8b 533 #define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */
AnnaBridge 165:d1b4690b3f8b 534 #define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */
AnnaBridge 165:d1b4690b3f8b 535
AnnaBridge 165:d1b4690b3f8b 536 /* CP15 Register DFSR */
AnnaBridge 165:d1b4690b3f8b 537 typedef union
AnnaBridge 165:d1b4690b3f8b 538 {
AnnaBridge 165:d1b4690b3f8b 539 struct
AnnaBridge 165:d1b4690b3f8b 540 {
AnnaBridge 165:d1b4690b3f8b 541 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
AnnaBridge 165:d1b4690b3f8b 542 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
AnnaBridge 165:d1b4690b3f8b 543 RESERVED(0:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 544 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
AnnaBridge 165:d1b4690b3f8b 545 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
AnnaBridge 165:d1b4690b3f8b 546 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
AnnaBridge 165:d1b4690b3f8b 547 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
AnnaBridge 165:d1b4690b3f8b 548 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
AnnaBridge 165:d1b4690b3f8b 549 RESERVED(1:18, uint32_t)
AnnaBridge 165:d1b4690b3f8b 550 } s; /*!< \brief Structure used for bit access in short format */
AnnaBridge 165:d1b4690b3f8b 551 struct
AnnaBridge 165:d1b4690b3f8b 552 {
AnnaBridge 165:d1b4690b3f8b 553 uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */
AnnaBridge 165:d1b4690b3f8b 554 RESERVED(0:3, uint32_t)
AnnaBridge 165:d1b4690b3f8b 555 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
AnnaBridge 165:d1b4690b3f8b 556 RESERVED(1:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 557 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
AnnaBridge 165:d1b4690b3f8b 558 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
AnnaBridge 165:d1b4690b3f8b 559 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
AnnaBridge 165:d1b4690b3f8b 560 RESERVED(2:18, uint32_t)
AnnaBridge 165:d1b4690b3f8b 561 } l; /*!< \brief Structure used for bit access in long format */
AnnaBridge 165:d1b4690b3f8b 562 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 165:d1b4690b3f8b 563 } DFSR_Type;
AnnaBridge 165:d1b4690b3f8b 564
AnnaBridge 165:d1b4690b3f8b 565 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
AnnaBridge 165:d1b4690b3f8b 566 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
AnnaBridge 165:d1b4690b3f8b 567
AnnaBridge 165:d1b4690b3f8b 568 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
AnnaBridge 165:d1b4690b3f8b 569 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
AnnaBridge 165:d1b4690b3f8b 570
AnnaBridge 165:d1b4690b3f8b 571 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
AnnaBridge 165:d1b4690b3f8b 572 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
AnnaBridge 165:d1b4690b3f8b 573
AnnaBridge 165:d1b4690b3f8b 574 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
AnnaBridge 165:d1b4690b3f8b 575 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
AnnaBridge 165:d1b4690b3f8b 576
AnnaBridge 165:d1b4690b3f8b 577 #define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */
AnnaBridge 165:d1b4690b3f8b 578 #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */
AnnaBridge 165:d1b4690b3f8b 579
AnnaBridge 165:d1b4690b3f8b 580 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
AnnaBridge 165:d1b4690b3f8b 581 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
AnnaBridge 165:d1b4690b3f8b 582
AnnaBridge 165:d1b4690b3f8b 583 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
AnnaBridge 165:d1b4690b3f8b 584 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
AnnaBridge 165:d1b4690b3f8b 585
AnnaBridge 165:d1b4690b3f8b 586 #define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */
AnnaBridge 165:d1b4690b3f8b 587 #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */
AnnaBridge 165:d1b4690b3f8b 588
AnnaBridge 165:d1b4690b3f8b 589 /* CP15 Register IFSR */
AnnaBridge 165:d1b4690b3f8b 590 typedef union
AnnaBridge 165:d1b4690b3f8b 591 {
AnnaBridge 165:d1b4690b3f8b 592 struct
AnnaBridge 165:d1b4690b3f8b 593 {
AnnaBridge 165:d1b4690b3f8b 594 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
AnnaBridge 165:d1b4690b3f8b 595 RESERVED(0:5, uint32_t)
AnnaBridge 165:d1b4690b3f8b 596 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
AnnaBridge 165:d1b4690b3f8b 597 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
AnnaBridge 165:d1b4690b3f8b 598 RESERVED(1:1, uint32_t)
AnnaBridge 165:d1b4690b3f8b 599 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
AnnaBridge 165:d1b4690b3f8b 600 RESERVED(2:19, uint32_t)
AnnaBridge 165:d1b4690b3f8b 601 } s; /*!< \brief Structure used for bit access in short format */
AnnaBridge 165:d1b4690b3f8b 602 struct
AnnaBridge 165:d1b4690b3f8b 603 {
AnnaBridge 165:d1b4690b3f8b 604 uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */
AnnaBridge 165:d1b4690b3f8b 605 RESERVED(0:3, uint32_t)
AnnaBridge 165:d1b4690b3f8b 606 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
AnnaBridge 165:d1b4690b3f8b 607 RESERVED(1:2, uint32_t)
AnnaBridge 165:d1b4690b3f8b 608 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
AnnaBridge 165:d1b4690b3f8b 609 RESERVED(2:19, uint32_t)
AnnaBridge 165:d1b4690b3f8b 610 } l; /*!< \brief Structure used for bit access in long format */
AnnaBridge 165:d1b4690b3f8b 611 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 165:d1b4690b3f8b 612 } IFSR_Type;
AnnaBridge 165:d1b4690b3f8b 613
AnnaBridge 165:d1b4690b3f8b 614 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
AnnaBridge 165:d1b4690b3f8b 615 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
AnnaBridge 165:d1b4690b3f8b 616
AnnaBridge 165:d1b4690b3f8b 617 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
AnnaBridge 165:d1b4690b3f8b 618 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
AnnaBridge 165:d1b4690b3f8b 619
AnnaBridge 165:d1b4690b3f8b 620 #define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */
AnnaBridge 165:d1b4690b3f8b 621 #define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */
AnnaBridge 165:d1b4690b3f8b 622
AnnaBridge 165:d1b4690b3f8b 623 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
AnnaBridge 165:d1b4690b3f8b 624 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
AnnaBridge 165:d1b4690b3f8b 625
AnnaBridge 165:d1b4690b3f8b 626 #define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */
AnnaBridge 165:d1b4690b3f8b 627 #define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */
AnnaBridge 165:d1b4690b3f8b 628
AnnaBridge 165:d1b4690b3f8b 629 /* CP15 Register ISR */
AnnaBridge 165:d1b4690b3f8b 630 typedef union
AnnaBridge 165:d1b4690b3f8b 631 {
AnnaBridge 165:d1b4690b3f8b 632 struct
AnnaBridge 165:d1b4690b3f8b 633 {
AnnaBridge 165:d1b4690b3f8b 634 RESERVED(0:6, uint32_t)
AnnaBridge 165:d1b4690b3f8b 635 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
AnnaBridge 165:d1b4690b3f8b 636 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
AnnaBridge 165:d1b4690b3f8b 637 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
AnnaBridge 165:d1b4690b3f8b 638 RESERVED(1:23, uint32_t)
AnnaBridge 165:d1b4690b3f8b 639 } b; /*!< \brief Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 640 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 165:d1b4690b3f8b 641 } ISR_Type;
AnnaBridge 165:d1b4690b3f8b 642
AnnaBridge 165:d1b4690b3f8b 643 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
AnnaBridge 165:d1b4690b3f8b 644 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
AnnaBridge 165:d1b4690b3f8b 645
AnnaBridge 165:d1b4690b3f8b 646 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
AnnaBridge 165:d1b4690b3f8b 647 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
AnnaBridge 165:d1b4690b3f8b 648
AnnaBridge 165:d1b4690b3f8b 649 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
AnnaBridge 165:d1b4690b3f8b 650 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
AnnaBridge 165:d1b4690b3f8b 651
AnnaBridge 165:d1b4690b3f8b 652 /* DACR Register */
AnnaBridge 165:d1b4690b3f8b 653 #define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */
AnnaBridge 165:d1b4690b3f8b 654 #define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */
AnnaBridge 165:d1b4690b3f8b 655 #define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */
AnnaBridge 165:d1b4690b3f8b 656 #define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */
AnnaBridge 165:d1b4690b3f8b 657 #define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */
AnnaBridge 165:d1b4690b3f8b 658
AnnaBridge 165:d1b4690b3f8b 659 /**
AnnaBridge 165:d1b4690b3f8b 660 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 165:d1b4690b3f8b 661 \param [in] field Name of the register bit field.
AnnaBridge 165:d1b4690b3f8b 662 \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 165:d1b4690b3f8b 663 \return Masked and shifted value.
AnnaBridge 165:d1b4690b3f8b 664 */
AnnaBridge 165:d1b4690b3f8b 665 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 165:d1b4690b3f8b 666
AnnaBridge 165:d1b4690b3f8b 667 /**
AnnaBridge 165:d1b4690b3f8b 668 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 165:d1b4690b3f8b 669 \param [in] field Name of the register bit field.
AnnaBridge 165:d1b4690b3f8b 670 \param [in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 165:d1b4690b3f8b 671 \return Masked and shifted bit field value.
AnnaBridge 165:d1b4690b3f8b 672 */
AnnaBridge 165:d1b4690b3f8b 673 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 165:d1b4690b3f8b 674
AnnaBridge 165:d1b4690b3f8b 675
AnnaBridge 165:d1b4690b3f8b 676 /**
AnnaBridge 165:d1b4690b3f8b 677 \brief Union type to access the L2C_310 Cache Controller.
AnnaBridge 165:d1b4690b3f8b 678 */
AnnaBridge 165:d1b4690b3f8b 679 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 680 typedef struct
AnnaBridge 165:d1b4690b3f8b 681 {
AnnaBridge 165:d1b4690b3f8b 682 __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */
AnnaBridge 165:d1b4690b3f8b 683 __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */
AnnaBridge 165:d1b4690b3f8b 684 RESERVED(0[0x3e], uint32_t)
AnnaBridge 165:d1b4690b3f8b 685 __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */
AnnaBridge 165:d1b4690b3f8b 686 __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */
AnnaBridge 165:d1b4690b3f8b 687 RESERVED(1[0x3e], uint32_t)
AnnaBridge 165:d1b4690b3f8b 688 __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */
AnnaBridge 165:d1b4690b3f8b 689 __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */
AnnaBridge 165:d1b4690b3f8b 690 __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */
AnnaBridge 165:d1b4690b3f8b 691 RESERVED(2[0x2], uint32_t)
AnnaBridge 165:d1b4690b3f8b 692 __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */
AnnaBridge 165:d1b4690b3f8b 693 __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */
AnnaBridge 165:d1b4690b3f8b 694 __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */
AnnaBridge 165:d1b4690b3f8b 695 __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */
AnnaBridge 165:d1b4690b3f8b 696 RESERVED(3[0x143], uint32_t)
AnnaBridge 165:d1b4690b3f8b 697 __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */
AnnaBridge 165:d1b4690b3f8b 698 RESERVED(4[0xf], uint32_t)
AnnaBridge 165:d1b4690b3f8b 699 __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */
AnnaBridge 165:d1b4690b3f8b 700 RESERVED(6[2], uint32_t)
AnnaBridge 165:d1b4690b3f8b 701 __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */
AnnaBridge 165:d1b4690b3f8b 702 RESERVED(5[0xc], uint32_t)
AnnaBridge 165:d1b4690b3f8b 703 __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */
AnnaBridge 165:d1b4690b3f8b 704 RESERVED(7[1], uint32_t)
AnnaBridge 165:d1b4690b3f8b 705 __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */
AnnaBridge 165:d1b4690b3f8b 706 __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */
AnnaBridge 165:d1b4690b3f8b 707 RESERVED(8[0xc], uint32_t)
AnnaBridge 165:d1b4690b3f8b 708 __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */
AnnaBridge 165:d1b4690b3f8b 709 RESERVED(9[1], uint32_t)
AnnaBridge 165:d1b4690b3f8b 710 __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */
AnnaBridge 165:d1b4690b3f8b 711 __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */
AnnaBridge 165:d1b4690b3f8b 712 RESERVED(10[0x40], uint32_t)
AnnaBridge 165:d1b4690b3f8b 713 __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */
AnnaBridge 165:d1b4690b3f8b 714 __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */
AnnaBridge 165:d1b4690b3f8b 715 __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */
AnnaBridge 165:d1b4690b3f8b 716 __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */
AnnaBridge 165:d1b4690b3f8b 717 __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */
AnnaBridge 165:d1b4690b3f8b 718 __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */
AnnaBridge 165:d1b4690b3f8b 719 __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */
AnnaBridge 165:d1b4690b3f8b 720 __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */
AnnaBridge 165:d1b4690b3f8b 721 __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */
AnnaBridge 165:d1b4690b3f8b 722 __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */
AnnaBridge 165:d1b4690b3f8b 723 __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */
AnnaBridge 165:d1b4690b3f8b 724 __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */
AnnaBridge 165:d1b4690b3f8b 725 __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */
AnnaBridge 165:d1b4690b3f8b 726 __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */
AnnaBridge 165:d1b4690b3f8b 727 __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */
AnnaBridge 165:d1b4690b3f8b 728 __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */
AnnaBridge 165:d1b4690b3f8b 729 RESERVED(11[0x4], uint32_t)
AnnaBridge 165:d1b4690b3f8b 730 __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */
AnnaBridge 165:d1b4690b3f8b 731 __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */
AnnaBridge 165:d1b4690b3f8b 732 RESERVED(12[0xaa], uint32_t)
AnnaBridge 165:d1b4690b3f8b 733 __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */
AnnaBridge 165:d1b4690b3f8b 734 __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */
AnnaBridge 165:d1b4690b3f8b 735 RESERVED(13[0xce], uint32_t)
AnnaBridge 165:d1b4690b3f8b 736 __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */
AnnaBridge 165:d1b4690b3f8b 737 } L2C_310_TypeDef;
AnnaBridge 165:d1b4690b3f8b 738
AnnaBridge 165:d1b4690b3f8b 739 #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
AnnaBridge 165:d1b4690b3f8b 740 #endif
AnnaBridge 165:d1b4690b3f8b 741
AnnaBridge 165:d1b4690b3f8b 742 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 743
AnnaBridge 165:d1b4690b3f8b 744 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
AnnaBridge 165:d1b4690b3f8b 745 */
AnnaBridge 165:d1b4690b3f8b 746 typedef struct
AnnaBridge 165:d1b4690b3f8b 747 {
AnnaBridge 165:d1b4690b3f8b 748 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */
AnnaBridge 165:d1b4690b3f8b 749 __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 165:d1b4690b3f8b 750 __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
AnnaBridge 165:d1b4690b3f8b 751 RESERVED(0, uint32_t)
AnnaBridge 165:d1b4690b3f8b 752 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */
AnnaBridge 165:d1b4690b3f8b 753 RESERVED(1[11], uint32_t)
AnnaBridge 165:d1b4690b3f8b 754 __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */
AnnaBridge 165:d1b4690b3f8b 755 RESERVED(2, uint32_t)
AnnaBridge 165:d1b4690b3f8b 756 __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */
AnnaBridge 165:d1b4690b3f8b 757 RESERVED(3, uint32_t)
AnnaBridge 165:d1b4690b3f8b 758 __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */
AnnaBridge 165:d1b4690b3f8b 759 RESERVED(4, uint32_t)
AnnaBridge 165:d1b4690b3f8b 760 __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */
AnnaBridge 165:d1b4690b3f8b 761 RESERVED(5[9], uint32_t)
AnnaBridge 165:d1b4690b3f8b 762 __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
AnnaBridge 165:d1b4690b3f8b 763 __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
AnnaBridge 165:d1b4690b3f8b 764 __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
AnnaBridge 165:d1b4690b3f8b 765 __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
AnnaBridge 165:d1b4690b3f8b 766 __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
AnnaBridge 165:d1b4690b3f8b 767 __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */
AnnaBridge 165:d1b4690b3f8b 768 __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
AnnaBridge 165:d1b4690b3f8b 769 __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */
AnnaBridge 165:d1b4690b3f8b 770 RESERVED(6, uint32_t)
AnnaBridge 165:d1b4690b3f8b 771 __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */
AnnaBridge 165:d1b4690b3f8b 772 RESERVED(7, uint32_t)
AnnaBridge 165:d1b4690b3f8b 773 __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */
AnnaBridge 165:d1b4690b3f8b 774 __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
AnnaBridge 165:d1b4690b3f8b 775 RESERVED(8[32], uint32_t)
AnnaBridge 165:d1b4690b3f8b 776 __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */
AnnaBridge 165:d1b4690b3f8b 777 __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */
AnnaBridge 165:d1b4690b3f8b 778 RESERVED(9[3], uint32_t)
AnnaBridge 165:d1b4690b3f8b 779 __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
AnnaBridge 165:d1b4690b3f8b 780 __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */
AnnaBridge 165:d1b4690b3f8b 781 RESERVED(10[5236], uint32_t)
AnnaBridge 165:d1b4690b3f8b 782 __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */
AnnaBridge 165:d1b4690b3f8b 783 } GICDistributor_Type;
AnnaBridge 165:d1b4690b3f8b 784
AnnaBridge 165:d1b4690b3f8b 785 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
AnnaBridge 165:d1b4690b3f8b 786
AnnaBridge 165:d1b4690b3f8b 787 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
AnnaBridge 165:d1b4690b3f8b 788 */
AnnaBridge 165:d1b4690b3f8b 789 typedef struct
AnnaBridge 165:d1b4690b3f8b 790 {
AnnaBridge 165:d1b4690b3f8b 791 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */
AnnaBridge 165:d1b4690b3f8b 792 __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */
AnnaBridge 165:d1b4690b3f8b 793 __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */
AnnaBridge 165:d1b4690b3f8b 794 __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
AnnaBridge 165:d1b4690b3f8b 795 __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */
AnnaBridge 165:d1b4690b3f8b 796 __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
AnnaBridge 165:d1b4690b3f8b 797 __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
AnnaBridge 165:d1b4690b3f8b 798 __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */
AnnaBridge 165:d1b4690b3f8b 799 __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
AnnaBridge 165:d1b4690b3f8b 800 __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
AnnaBridge 165:d1b4690b3f8b 801 __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
AnnaBridge 165:d1b4690b3f8b 802 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */
AnnaBridge 165:d1b4690b3f8b 803 RESERVED(1[40], uint32_t)
AnnaBridge 165:d1b4690b3f8b 804 __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */
AnnaBridge 165:d1b4690b3f8b 805 __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
AnnaBridge 165:d1b4690b3f8b 806 RESERVED(2[3], uint32_t)
AnnaBridge 165:d1b4690b3f8b 807 __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */
AnnaBridge 165:d1b4690b3f8b 808 RESERVED(3[960], uint32_t)
AnnaBridge 165:d1b4690b3f8b 809 __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */
AnnaBridge 165:d1b4690b3f8b 810 } GICInterface_Type;
AnnaBridge 165:d1b4690b3f8b 811
AnnaBridge 165:d1b4690b3f8b 812 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */
AnnaBridge 165:d1b4690b3f8b 813 #endif
AnnaBridge 165:d1b4690b3f8b 814
AnnaBridge 165:d1b4690b3f8b 815 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 816 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 817 /** \brief Structure type to access the Private Timer
AnnaBridge 165:d1b4690b3f8b 818 */
AnnaBridge 165:d1b4690b3f8b 819 typedef struct
AnnaBridge 165:d1b4690b3f8b 820 {
AnnaBridge 165:d1b4690b3f8b 821 __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
AnnaBridge 165:d1b4690b3f8b 822 __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
AnnaBridge 165:d1b4690b3f8b 823 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
AnnaBridge 165:d1b4690b3f8b 824 __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
AnnaBridge 165:d1b4690b3f8b 825 RESERVED(0[4], uint32_t)
AnnaBridge 165:d1b4690b3f8b 826 __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
AnnaBridge 165:d1b4690b3f8b 827 __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
AnnaBridge 165:d1b4690b3f8b 828 __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
AnnaBridge 165:d1b4690b3f8b 829 __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
AnnaBridge 165:d1b4690b3f8b 830 __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
AnnaBridge 165:d1b4690b3f8b 831 __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
AnnaBridge 165:d1b4690b3f8b 832 } Timer_Type;
AnnaBridge 165:d1b4690b3f8b 833 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */
AnnaBridge 165:d1b4690b3f8b 834 #endif
AnnaBridge 165:d1b4690b3f8b 835 #endif
AnnaBridge 165:d1b4690b3f8b 836
AnnaBridge 165:d1b4690b3f8b 837 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 838 * Hardware Abstraction Layer
AnnaBridge 165:d1b4690b3f8b 839 Core Function Interface contains:
AnnaBridge 165:d1b4690b3f8b 840 - L1 Cache Functions
AnnaBridge 165:d1b4690b3f8b 841 - L2C-310 Cache Controller Functions
AnnaBridge 165:d1b4690b3f8b 842 - PL1 Timer Functions
AnnaBridge 165:d1b4690b3f8b 843 - GIC Functions
AnnaBridge 165:d1b4690b3f8b 844 - MMU Functions
AnnaBridge 165:d1b4690b3f8b 845 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 846
AnnaBridge 165:d1b4690b3f8b 847 /* ########################## L1 Cache functions ################################# */
AnnaBridge 165:d1b4690b3f8b 848
AnnaBridge 165:d1b4690b3f8b 849 /** \brief Enable Caches by setting I and C bits in SCTLR register.
AnnaBridge 165:d1b4690b3f8b 850 */
AnnaBridge 165:d1b4690b3f8b 851 __STATIC_FORCEINLINE void L1C_EnableCaches(void) {
AnnaBridge 165:d1b4690b3f8b 852 __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
AnnaBridge 165:d1b4690b3f8b 853 __ISB();
AnnaBridge 165:d1b4690b3f8b 854 }
AnnaBridge 165:d1b4690b3f8b 855
AnnaBridge 165:d1b4690b3f8b 856 /** \brief Disable Caches by clearing I and C bits in SCTLR register.
AnnaBridge 165:d1b4690b3f8b 857 */
AnnaBridge 165:d1b4690b3f8b 858 __STATIC_FORCEINLINE void L1C_DisableCaches(void) {
AnnaBridge 165:d1b4690b3f8b 859 __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
AnnaBridge 165:d1b4690b3f8b 860 __ISB();
AnnaBridge 165:d1b4690b3f8b 861 }
AnnaBridge 165:d1b4690b3f8b 862
AnnaBridge 165:d1b4690b3f8b 863 /** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
AnnaBridge 165:d1b4690b3f8b 864 */
AnnaBridge 165:d1b4690b3f8b 865 __STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
AnnaBridge 165:d1b4690b3f8b 866 __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
AnnaBridge 165:d1b4690b3f8b 867 __ISB();
AnnaBridge 165:d1b4690b3f8b 868 }
AnnaBridge 165:d1b4690b3f8b 869
AnnaBridge 165:d1b4690b3f8b 870 /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
AnnaBridge 165:d1b4690b3f8b 871 */
AnnaBridge 165:d1b4690b3f8b 872 __STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
AnnaBridge 165:d1b4690b3f8b 873 __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
AnnaBridge 165:d1b4690b3f8b 874 __ISB();
AnnaBridge 165:d1b4690b3f8b 875 }
AnnaBridge 165:d1b4690b3f8b 876
AnnaBridge 165:d1b4690b3f8b 877 /** \brief Invalidate entire branch predictor array
AnnaBridge 165:d1b4690b3f8b 878 */
AnnaBridge 165:d1b4690b3f8b 879 __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
AnnaBridge 165:d1b4690b3f8b 880 __set_BPIALL(0);
AnnaBridge 165:d1b4690b3f8b 881 __DSB(); //ensure completion of the invalidation
AnnaBridge 165:d1b4690b3f8b 882 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 165:d1b4690b3f8b 883 }
AnnaBridge 165:d1b4690b3f8b 884
AnnaBridge 165:d1b4690b3f8b 885 /** \brief Invalidate the whole instruction cache
AnnaBridge 165:d1b4690b3f8b 886 */
AnnaBridge 165:d1b4690b3f8b 887 __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
AnnaBridge 165:d1b4690b3f8b 888 __set_ICIALLU(0);
AnnaBridge 165:d1b4690b3f8b 889 __DSB(); //ensure completion of the invalidation
AnnaBridge 165:d1b4690b3f8b 890 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 165:d1b4690b3f8b 891 }
AnnaBridge 165:d1b4690b3f8b 892
AnnaBridge 165:d1b4690b3f8b 893 /** \brief Clean data cache line by address.
AnnaBridge 165:d1b4690b3f8b 894 * \param [in] va Pointer to data to clear the cache for.
AnnaBridge 165:d1b4690b3f8b 895 */
AnnaBridge 165:d1b4690b3f8b 896 __STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
AnnaBridge 165:d1b4690b3f8b 897 __set_DCCMVAC((uint32_t)va);
AnnaBridge 165:d1b4690b3f8b 898 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 165:d1b4690b3f8b 899 }
AnnaBridge 165:d1b4690b3f8b 900
AnnaBridge 165:d1b4690b3f8b 901 /** \brief Invalidate data cache line by address.
AnnaBridge 165:d1b4690b3f8b 902 * \param [in] va Pointer to data to invalidate the cache for.
AnnaBridge 165:d1b4690b3f8b 903 */
AnnaBridge 165:d1b4690b3f8b 904 __STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
AnnaBridge 165:d1b4690b3f8b 905 __set_DCIMVAC((uint32_t)va);
AnnaBridge 165:d1b4690b3f8b 906 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 165:d1b4690b3f8b 907 }
AnnaBridge 165:d1b4690b3f8b 908
AnnaBridge 165:d1b4690b3f8b 909 /** \brief Clean and Invalidate data cache by address.
AnnaBridge 165:d1b4690b3f8b 910 * \param [in] va Pointer to data to invalidate the cache for.
AnnaBridge 165:d1b4690b3f8b 911 */
AnnaBridge 165:d1b4690b3f8b 912 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
AnnaBridge 165:d1b4690b3f8b 913 __set_DCCIMVAC((uint32_t)va);
AnnaBridge 165:d1b4690b3f8b 914 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 165:d1b4690b3f8b 915 }
AnnaBridge 165:d1b4690b3f8b 916
AnnaBridge 165:d1b4690b3f8b 917 /** \brief Calculate log2 rounded up
AnnaBridge 165:d1b4690b3f8b 918 * - log(0) => 0
AnnaBridge 165:d1b4690b3f8b 919 * - log(1) => 0
AnnaBridge 165:d1b4690b3f8b 920 * - log(2) => 1
AnnaBridge 165:d1b4690b3f8b 921 * - log(3) => 2
AnnaBridge 165:d1b4690b3f8b 922 * - log(4) => 2
AnnaBridge 165:d1b4690b3f8b 923 * - log(5) => 3
AnnaBridge 165:d1b4690b3f8b 924 * : :
AnnaBridge 165:d1b4690b3f8b 925 * - log(16) => 4
AnnaBridge 165:d1b4690b3f8b 926 * - log(32) => 5
AnnaBridge 165:d1b4690b3f8b 927 * : :
AnnaBridge 165:d1b4690b3f8b 928 * \param [in] n input value parameter
AnnaBridge 165:d1b4690b3f8b 929 * \return log2(n)
AnnaBridge 165:d1b4690b3f8b 930 */
AnnaBridge 165:d1b4690b3f8b 931 __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
AnnaBridge 165:d1b4690b3f8b 932 {
AnnaBridge 165:d1b4690b3f8b 933 if (n < 2U) {
AnnaBridge 165:d1b4690b3f8b 934 return 0U;
AnnaBridge 165:d1b4690b3f8b 935 }
AnnaBridge 165:d1b4690b3f8b 936 uint8_t log = 0U;
AnnaBridge 165:d1b4690b3f8b 937 uint32_t t = n;
AnnaBridge 165:d1b4690b3f8b 938 while(t > 1U)
AnnaBridge 165:d1b4690b3f8b 939 {
AnnaBridge 165:d1b4690b3f8b 940 log++;
AnnaBridge 165:d1b4690b3f8b 941 t >>= 1U;
AnnaBridge 165:d1b4690b3f8b 942 }
AnnaBridge 165:d1b4690b3f8b 943 if (n & 1U) { log++; }
AnnaBridge 165:d1b4690b3f8b 944 return log;
AnnaBridge 165:d1b4690b3f8b 945 }
AnnaBridge 165:d1b4690b3f8b 946
AnnaBridge 165:d1b4690b3f8b 947 /** \brief Apply cache maintenance to given cache level.
AnnaBridge 165:d1b4690b3f8b 948 * \param [in] level cache level to be maintained
AnnaBridge 165:d1b4690b3f8b 949 * \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
AnnaBridge 165:d1b4690b3f8b 950 */
AnnaBridge 165:d1b4690b3f8b 951 __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
AnnaBridge 165:d1b4690b3f8b 952 {
AnnaBridge 165:d1b4690b3f8b 953 register volatile uint32_t Dummy;
AnnaBridge 165:d1b4690b3f8b 954 register volatile uint32_t ccsidr;
AnnaBridge 165:d1b4690b3f8b 955 uint32_t num_sets;
AnnaBridge 165:d1b4690b3f8b 956 uint32_t num_ways;
AnnaBridge 165:d1b4690b3f8b 957 uint32_t shift_way;
AnnaBridge 165:d1b4690b3f8b 958 uint32_t log2_linesize;
AnnaBridge 165:d1b4690b3f8b 959 int32_t log2_num_ways;
AnnaBridge 165:d1b4690b3f8b 960
AnnaBridge 165:d1b4690b3f8b 961 Dummy = level << 1U;
AnnaBridge 165:d1b4690b3f8b 962 /* set csselr, select ccsidr register */
AnnaBridge 165:d1b4690b3f8b 963 __set_CCSIDR(Dummy);
AnnaBridge 165:d1b4690b3f8b 964 /* get current ccsidr register */
AnnaBridge 165:d1b4690b3f8b 965 ccsidr = __get_CCSIDR();
AnnaBridge 165:d1b4690b3f8b 966 num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
AnnaBridge 165:d1b4690b3f8b 967 num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
AnnaBridge 165:d1b4690b3f8b 968 log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
AnnaBridge 165:d1b4690b3f8b 969 log2_num_ways = __log2_up(num_ways);
AnnaBridge 165:d1b4690b3f8b 970 if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
AnnaBridge 165:d1b4690b3f8b 971 return; // FATAL ERROR
AnnaBridge 165:d1b4690b3f8b 972 }
AnnaBridge 165:d1b4690b3f8b 973 shift_way = 32U - (uint32_t)log2_num_ways;
AnnaBridge 165:d1b4690b3f8b 974 for(int32_t way = num_ways-1; way >= 0; way--)
AnnaBridge 165:d1b4690b3f8b 975 {
AnnaBridge 165:d1b4690b3f8b 976 for(int32_t set = num_sets-1; set >= 0; set--)
AnnaBridge 165:d1b4690b3f8b 977 {
AnnaBridge 165:d1b4690b3f8b 978 Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
AnnaBridge 165:d1b4690b3f8b 979 switch (maint)
AnnaBridge 165:d1b4690b3f8b 980 {
AnnaBridge 165:d1b4690b3f8b 981 case 0U: __set_DCISW(Dummy); break;
AnnaBridge 165:d1b4690b3f8b 982 case 1U: __set_DCCSW(Dummy); break;
AnnaBridge 165:d1b4690b3f8b 983 default: __set_DCCISW(Dummy); break;
AnnaBridge 165:d1b4690b3f8b 984 }
AnnaBridge 165:d1b4690b3f8b 985 }
AnnaBridge 165:d1b4690b3f8b 986 }
AnnaBridge 165:d1b4690b3f8b 987 __DMB();
AnnaBridge 165:d1b4690b3f8b 988 }
AnnaBridge 165:d1b4690b3f8b 989
AnnaBridge 165:d1b4690b3f8b 990 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 165:d1b4690b3f8b 991 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
AnnaBridge 165:d1b4690b3f8b 992 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
AnnaBridge 165:d1b4690b3f8b 993 */
AnnaBridge 165:d1b4690b3f8b 994 __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge 165:d1b4690b3f8b 995 register volatile uint32_t clidr;
AnnaBridge 165:d1b4690b3f8b 996 uint32_t cache_type;
AnnaBridge 165:d1b4690b3f8b 997 clidr = __get_CLIDR();
AnnaBridge 165:d1b4690b3f8b 998 for(uint32_t i = 0U; i<7U; i++)
AnnaBridge 165:d1b4690b3f8b 999 {
AnnaBridge 165:d1b4690b3f8b 1000 cache_type = (clidr >> i*3U) & 0x7UL;
AnnaBridge 165:d1b4690b3f8b 1001 if ((cache_type >= 2U) && (cache_type <= 4U))
AnnaBridge 165:d1b4690b3f8b 1002 {
AnnaBridge 165:d1b4690b3f8b 1003 __L1C_MaintainDCacheSetWay(i, op);
AnnaBridge 165:d1b4690b3f8b 1004 }
AnnaBridge 165:d1b4690b3f8b 1005 }
AnnaBridge 165:d1b4690b3f8b 1006 }
AnnaBridge 165:d1b4690b3f8b 1007
AnnaBridge 165:d1b4690b3f8b 1008 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 165:d1b4690b3f8b 1009 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
AnnaBridge 165:d1b4690b3f8b 1010 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
AnnaBridge 165:d1b4690b3f8b 1011 * \deprecated Use generic L1C_CleanInvalidateCache instead.
AnnaBridge 165:d1b4690b3f8b 1012 */
AnnaBridge 165:d1b4690b3f8b 1013 CMSIS_DEPRECATED
AnnaBridge 165:d1b4690b3f8b 1014 __STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge 165:d1b4690b3f8b 1015 L1C_CleanInvalidateCache(op);
AnnaBridge 165:d1b4690b3f8b 1016 }
AnnaBridge 165:d1b4690b3f8b 1017
AnnaBridge 165:d1b4690b3f8b 1018 /** \brief Invalidate the whole data cache.
AnnaBridge 165:d1b4690b3f8b 1019 */
AnnaBridge 165:d1b4690b3f8b 1020 __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
AnnaBridge 165:d1b4690b3f8b 1021 L1C_CleanInvalidateCache(0);
AnnaBridge 165:d1b4690b3f8b 1022 }
AnnaBridge 165:d1b4690b3f8b 1023
AnnaBridge 165:d1b4690b3f8b 1024 /** \brief Clean the whole data cache.
AnnaBridge 165:d1b4690b3f8b 1025 */
AnnaBridge 165:d1b4690b3f8b 1026 __STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
AnnaBridge 165:d1b4690b3f8b 1027 L1C_CleanInvalidateCache(1);
AnnaBridge 165:d1b4690b3f8b 1028 }
AnnaBridge 165:d1b4690b3f8b 1029
AnnaBridge 165:d1b4690b3f8b 1030 /** \brief Clean and invalidate the whole data cache.
AnnaBridge 165:d1b4690b3f8b 1031 */
AnnaBridge 165:d1b4690b3f8b 1032 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
AnnaBridge 165:d1b4690b3f8b 1033 L1C_CleanInvalidateCache(2);
AnnaBridge 165:d1b4690b3f8b 1034 }
AnnaBridge 165:d1b4690b3f8b 1035
AnnaBridge 165:d1b4690b3f8b 1036 /* ########################## L2 Cache functions ################################# */
AnnaBridge 165:d1b4690b3f8b 1037 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 1038 /** \brief Cache Sync operation by writing CACHE_SYNC register.
AnnaBridge 165:d1b4690b3f8b 1039 */
AnnaBridge 165:d1b4690b3f8b 1040 __STATIC_INLINE void L2C_Sync(void)
AnnaBridge 165:d1b4690b3f8b 1041 {
AnnaBridge 165:d1b4690b3f8b 1042 L2C_310->CACHE_SYNC = 0x0;
AnnaBridge 165:d1b4690b3f8b 1043 }
AnnaBridge 165:d1b4690b3f8b 1044
AnnaBridge 165:d1b4690b3f8b 1045 /** \brief Read cache controller cache ID from CACHE_ID register.
AnnaBridge 165:d1b4690b3f8b 1046 * \return L2C_310_TypeDef::CACHE_ID
AnnaBridge 165:d1b4690b3f8b 1047 */
AnnaBridge 165:d1b4690b3f8b 1048 __STATIC_INLINE int L2C_GetID (void)
AnnaBridge 165:d1b4690b3f8b 1049 {
AnnaBridge 165:d1b4690b3f8b 1050 return L2C_310->CACHE_ID;
AnnaBridge 165:d1b4690b3f8b 1051 }
AnnaBridge 165:d1b4690b3f8b 1052
AnnaBridge 165:d1b4690b3f8b 1053 /** \brief Read cache controller cache type from CACHE_TYPE register.
AnnaBridge 165:d1b4690b3f8b 1054 * \return L2C_310_TypeDef::CACHE_TYPE
AnnaBridge 165:d1b4690b3f8b 1055 */
AnnaBridge 165:d1b4690b3f8b 1056 __STATIC_INLINE int L2C_GetType (void)
AnnaBridge 165:d1b4690b3f8b 1057 {
AnnaBridge 165:d1b4690b3f8b 1058 return L2C_310->CACHE_TYPE;
AnnaBridge 165:d1b4690b3f8b 1059 }
AnnaBridge 165:d1b4690b3f8b 1060
AnnaBridge 165:d1b4690b3f8b 1061 /** \brief Invalidate all cache by way
AnnaBridge 165:d1b4690b3f8b 1062 */
AnnaBridge 165:d1b4690b3f8b 1063 __STATIC_INLINE void L2C_InvAllByWay (void)
AnnaBridge 165:d1b4690b3f8b 1064 {
AnnaBridge 165:d1b4690b3f8b 1065 unsigned int assoc;
AnnaBridge 165:d1b4690b3f8b 1066
AnnaBridge 165:d1b4690b3f8b 1067 if (L2C_310->AUX_CNT & (1U << 16U)) {
AnnaBridge 165:d1b4690b3f8b 1068 assoc = 16U;
AnnaBridge 165:d1b4690b3f8b 1069 } else {
AnnaBridge 165:d1b4690b3f8b 1070 assoc = 8U;
AnnaBridge 165:d1b4690b3f8b 1071 }
AnnaBridge 165:d1b4690b3f8b 1072
AnnaBridge 165:d1b4690b3f8b 1073 L2C_310->INV_WAY = (1U << assoc) - 1U;
AnnaBridge 165:d1b4690b3f8b 1074 while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
AnnaBridge 165:d1b4690b3f8b 1075
AnnaBridge 165:d1b4690b3f8b 1076 L2C_Sync();
AnnaBridge 165:d1b4690b3f8b 1077 }
AnnaBridge 165:d1b4690b3f8b 1078
AnnaBridge 165:d1b4690b3f8b 1079 /** \brief Clean and Invalidate all cache by way
AnnaBridge 165:d1b4690b3f8b 1080 */
AnnaBridge 165:d1b4690b3f8b 1081 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
AnnaBridge 165:d1b4690b3f8b 1082 {
AnnaBridge 165:d1b4690b3f8b 1083 unsigned int assoc;
AnnaBridge 165:d1b4690b3f8b 1084
AnnaBridge 165:d1b4690b3f8b 1085 if (L2C_310->AUX_CNT & (1U << 16U)) {
AnnaBridge 165:d1b4690b3f8b 1086 assoc = 16U;
AnnaBridge 165:d1b4690b3f8b 1087 } else {
AnnaBridge 165:d1b4690b3f8b 1088 assoc = 8U;
AnnaBridge 165:d1b4690b3f8b 1089 }
AnnaBridge 165:d1b4690b3f8b 1090
AnnaBridge 165:d1b4690b3f8b 1091 L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
AnnaBridge 165:d1b4690b3f8b 1092 while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
AnnaBridge 165:d1b4690b3f8b 1093
AnnaBridge 165:d1b4690b3f8b 1094 L2C_Sync();
AnnaBridge 165:d1b4690b3f8b 1095 }
AnnaBridge 165:d1b4690b3f8b 1096
AnnaBridge 165:d1b4690b3f8b 1097 /** \brief Enable Level 2 Cache
AnnaBridge 165:d1b4690b3f8b 1098 */
AnnaBridge 165:d1b4690b3f8b 1099 __STATIC_INLINE void L2C_Enable(void)
AnnaBridge 165:d1b4690b3f8b 1100 {
AnnaBridge 165:d1b4690b3f8b 1101 L2C_310->CONTROL = 0;
AnnaBridge 165:d1b4690b3f8b 1102 L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
AnnaBridge 165:d1b4690b3f8b 1103 L2C_310->DEBUG_CONTROL = 0;
AnnaBridge 165:d1b4690b3f8b 1104 L2C_310->DATA_LOCK_0_WAY = 0;
AnnaBridge 165:d1b4690b3f8b 1105 L2C_310->CACHE_SYNC = 0;
AnnaBridge 165:d1b4690b3f8b 1106 L2C_310->CONTROL = 0x01;
AnnaBridge 165:d1b4690b3f8b 1107 L2C_Sync();
AnnaBridge 165:d1b4690b3f8b 1108 }
AnnaBridge 165:d1b4690b3f8b 1109
AnnaBridge 165:d1b4690b3f8b 1110 /** \brief Disable Level 2 Cache
AnnaBridge 165:d1b4690b3f8b 1111 */
AnnaBridge 165:d1b4690b3f8b 1112 __STATIC_INLINE void L2C_Disable(void)
AnnaBridge 165:d1b4690b3f8b 1113 {
AnnaBridge 165:d1b4690b3f8b 1114 L2C_310->CONTROL = 0x00;
AnnaBridge 165:d1b4690b3f8b 1115 L2C_Sync();
AnnaBridge 165:d1b4690b3f8b 1116 }
AnnaBridge 165:d1b4690b3f8b 1117
AnnaBridge 165:d1b4690b3f8b 1118 /** \brief Invalidate cache by physical address
AnnaBridge 165:d1b4690b3f8b 1119 * \param [in] pa Pointer to data to invalidate cache for.
AnnaBridge 165:d1b4690b3f8b 1120 */
AnnaBridge 165:d1b4690b3f8b 1121 __STATIC_INLINE void L2C_InvPa (void *pa)
AnnaBridge 165:d1b4690b3f8b 1122 {
AnnaBridge 165:d1b4690b3f8b 1123 L2C_310->INV_LINE_PA = (unsigned int)pa;
AnnaBridge 165:d1b4690b3f8b 1124 L2C_Sync();
AnnaBridge 165:d1b4690b3f8b 1125 }
AnnaBridge 165:d1b4690b3f8b 1126
AnnaBridge 165:d1b4690b3f8b 1127 /** \brief Clean cache by physical address
AnnaBridge 165:d1b4690b3f8b 1128 * \param [in] pa Pointer to data to invalidate cache for.
AnnaBridge 165:d1b4690b3f8b 1129 */
AnnaBridge 165:d1b4690b3f8b 1130 __STATIC_INLINE void L2C_CleanPa (void *pa)
AnnaBridge 165:d1b4690b3f8b 1131 {
AnnaBridge 165:d1b4690b3f8b 1132 L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
AnnaBridge 165:d1b4690b3f8b 1133 L2C_Sync();
AnnaBridge 165:d1b4690b3f8b 1134 }
AnnaBridge 165:d1b4690b3f8b 1135
AnnaBridge 165:d1b4690b3f8b 1136 /** \brief Clean and invalidate cache by physical address
AnnaBridge 165:d1b4690b3f8b 1137 * \param [in] pa Pointer to data to invalidate cache for.
AnnaBridge 165:d1b4690b3f8b 1138 */
AnnaBridge 165:d1b4690b3f8b 1139 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
AnnaBridge 165:d1b4690b3f8b 1140 {
AnnaBridge 165:d1b4690b3f8b 1141 L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
AnnaBridge 165:d1b4690b3f8b 1142 L2C_Sync();
AnnaBridge 165:d1b4690b3f8b 1143 }
AnnaBridge 165:d1b4690b3f8b 1144 #endif
AnnaBridge 165:d1b4690b3f8b 1145
AnnaBridge 165:d1b4690b3f8b 1146 /* ########################## GIC functions ###################################### */
AnnaBridge 165:d1b4690b3f8b 1147 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 1148
AnnaBridge 165:d1b4690b3f8b 1149 /** \brief Enable the interrupt distributor using the GIC's CTLR register.
AnnaBridge 165:d1b4690b3f8b 1150 */
AnnaBridge 165:d1b4690b3f8b 1151 __STATIC_INLINE void GIC_EnableDistributor(void)
AnnaBridge 165:d1b4690b3f8b 1152 {
AnnaBridge 165:d1b4690b3f8b 1153 GICDistributor->CTLR |= 1U;
AnnaBridge 165:d1b4690b3f8b 1154 }
AnnaBridge 165:d1b4690b3f8b 1155
AnnaBridge 165:d1b4690b3f8b 1156 /** \brief Disable the interrupt distributor using the GIC's CTLR register.
AnnaBridge 165:d1b4690b3f8b 1157 */
AnnaBridge 165:d1b4690b3f8b 1158 __STATIC_INLINE void GIC_DisableDistributor(void)
AnnaBridge 165:d1b4690b3f8b 1159 {
AnnaBridge 165:d1b4690b3f8b 1160 GICDistributor->CTLR &=~1U;
AnnaBridge 165:d1b4690b3f8b 1161 }
AnnaBridge 165:d1b4690b3f8b 1162
AnnaBridge 165:d1b4690b3f8b 1163 /** \brief Read the GIC's TYPER register.
AnnaBridge 165:d1b4690b3f8b 1164 * \return GICDistributor_Type::TYPER
AnnaBridge 165:d1b4690b3f8b 1165 */
AnnaBridge 165:d1b4690b3f8b 1166 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
AnnaBridge 165:d1b4690b3f8b 1167 {
AnnaBridge 165:d1b4690b3f8b 1168 return (GICDistributor->TYPER);
AnnaBridge 165:d1b4690b3f8b 1169 }
AnnaBridge 165:d1b4690b3f8b 1170
AnnaBridge 165:d1b4690b3f8b 1171 /** \brief Reads the GIC's IIDR register.
AnnaBridge 165:d1b4690b3f8b 1172 * \return GICDistributor_Type::IIDR
AnnaBridge 165:d1b4690b3f8b 1173 */
AnnaBridge 165:d1b4690b3f8b 1174 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
AnnaBridge 165:d1b4690b3f8b 1175 {
AnnaBridge 165:d1b4690b3f8b 1176 return (GICDistributor->IIDR);
AnnaBridge 165:d1b4690b3f8b 1177 }
AnnaBridge 165:d1b4690b3f8b 1178
AnnaBridge 165:d1b4690b3f8b 1179 /** \brief Sets the GIC's ITARGETSR register for the given interrupt.
AnnaBridge 165:d1b4690b3f8b 1180 * \param [in] IRQn Interrupt to be configured.
AnnaBridge 165:d1b4690b3f8b 1181 * \param [in] cpu_target CPU interfaces to assign this interrupt to.
AnnaBridge 165:d1b4690b3f8b 1182 */
AnnaBridge 165:d1b4690b3f8b 1183 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
AnnaBridge 165:d1b4690b3f8b 1184 {
AnnaBridge 165:d1b4690b3f8b 1185 uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
AnnaBridge 165:d1b4690b3f8b 1186 GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
AnnaBridge 165:d1b4690b3f8b 1187 }
AnnaBridge 165:d1b4690b3f8b 1188
AnnaBridge 165:d1b4690b3f8b 1189 /** \brief Read the GIC's ITARGETSR register.
AnnaBridge 165:d1b4690b3f8b 1190 * \param [in] IRQn Interrupt to acquire the configuration for.
AnnaBridge 165:d1b4690b3f8b 1191 * \return GICDistributor_Type::ITARGETSR
AnnaBridge 165:d1b4690b3f8b 1192 */
AnnaBridge 165:d1b4690b3f8b 1193 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1194 {
AnnaBridge 165:d1b4690b3f8b 1195 return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
AnnaBridge 165:d1b4690b3f8b 1196 }
AnnaBridge 165:d1b4690b3f8b 1197
AnnaBridge 165:d1b4690b3f8b 1198 /** \brief Enable the CPU's interrupt interface.
AnnaBridge 165:d1b4690b3f8b 1199 */
AnnaBridge 165:d1b4690b3f8b 1200 __STATIC_INLINE void GIC_EnableInterface(void)
AnnaBridge 165:d1b4690b3f8b 1201 {
AnnaBridge 165:d1b4690b3f8b 1202 GICInterface->CTLR |= 1U; //enable interface
AnnaBridge 165:d1b4690b3f8b 1203 }
AnnaBridge 165:d1b4690b3f8b 1204
AnnaBridge 165:d1b4690b3f8b 1205 /** \brief Disable the CPU's interrupt interface.
AnnaBridge 165:d1b4690b3f8b 1206 */
AnnaBridge 165:d1b4690b3f8b 1207 __STATIC_INLINE void GIC_DisableInterface(void)
AnnaBridge 165:d1b4690b3f8b 1208 {
AnnaBridge 165:d1b4690b3f8b 1209 GICInterface->CTLR &=~1U; //disable distributor
AnnaBridge 165:d1b4690b3f8b 1210 }
AnnaBridge 165:d1b4690b3f8b 1211
AnnaBridge 165:d1b4690b3f8b 1212 /** \brief Read the CPU's IAR register.
AnnaBridge 165:d1b4690b3f8b 1213 * \return GICInterface_Type::IAR
AnnaBridge 165:d1b4690b3f8b 1214 */
AnnaBridge 165:d1b4690b3f8b 1215 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
AnnaBridge 165:d1b4690b3f8b 1216 {
AnnaBridge 165:d1b4690b3f8b 1217 return (IRQn_Type)(GICInterface->IAR);
AnnaBridge 165:d1b4690b3f8b 1218 }
AnnaBridge 165:d1b4690b3f8b 1219
AnnaBridge 165:d1b4690b3f8b 1220 /** \brief Writes the given interrupt number to the CPU's EOIR register.
AnnaBridge 165:d1b4690b3f8b 1221 * \param [in] IRQn The interrupt to be signaled as finished.
AnnaBridge 165:d1b4690b3f8b 1222 */
AnnaBridge 165:d1b4690b3f8b 1223 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1224 {
AnnaBridge 165:d1b4690b3f8b 1225 GICInterface->EOIR = IRQn;
AnnaBridge 165:d1b4690b3f8b 1226 }
AnnaBridge 165:d1b4690b3f8b 1227
AnnaBridge 165:d1b4690b3f8b 1228 /** \brief Enables the given interrupt using GIC's ISENABLER register.
AnnaBridge 165:d1b4690b3f8b 1229 * \param [in] IRQn The interrupt to be enabled.
AnnaBridge 165:d1b4690b3f8b 1230 */
AnnaBridge 165:d1b4690b3f8b 1231 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1232 {
AnnaBridge 165:d1b4690b3f8b 1233 GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
AnnaBridge 165:d1b4690b3f8b 1234 }
AnnaBridge 165:d1b4690b3f8b 1235
AnnaBridge 165:d1b4690b3f8b 1236 /** \brief Get interrupt enable status using GIC's ISENABLER register.
AnnaBridge 165:d1b4690b3f8b 1237 * \param [in] IRQn The interrupt to be queried.
AnnaBridge 165:d1b4690b3f8b 1238 * \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
AnnaBridge 165:d1b4690b3f8b 1239 */
AnnaBridge 165:d1b4690b3f8b 1240 __STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1241 {
AnnaBridge 165:d1b4690b3f8b 1242 return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
AnnaBridge 165:d1b4690b3f8b 1243 }
AnnaBridge 165:d1b4690b3f8b 1244
AnnaBridge 165:d1b4690b3f8b 1245 /** \brief Disables the given interrupt using GIC's ICENABLER register.
AnnaBridge 165:d1b4690b3f8b 1246 * \param [in] IRQn The interrupt to be disabled.
AnnaBridge 165:d1b4690b3f8b 1247 */
AnnaBridge 165:d1b4690b3f8b 1248 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1249 {
AnnaBridge 165:d1b4690b3f8b 1250 GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
AnnaBridge 165:d1b4690b3f8b 1251 }
AnnaBridge 165:d1b4690b3f8b 1252
AnnaBridge 165:d1b4690b3f8b 1253 /** \brief Get interrupt pending status from GIC's ISPENDR register.
AnnaBridge 165:d1b4690b3f8b 1254 * \param [in] IRQn The interrupt to be queried.
AnnaBridge 165:d1b4690b3f8b 1255 * \return 0 - interrupt is not pending, 1 - interrupt is pendig.
AnnaBridge 165:d1b4690b3f8b 1256 */
AnnaBridge 165:d1b4690b3f8b 1257 __STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1258 {
AnnaBridge 165:d1b4690b3f8b 1259 uint32_t pend;
AnnaBridge 165:d1b4690b3f8b 1260
AnnaBridge 165:d1b4690b3f8b 1261 if (IRQn >= 16U) {
AnnaBridge 165:d1b4690b3f8b 1262 pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
AnnaBridge 165:d1b4690b3f8b 1263 } else {
AnnaBridge 165:d1b4690b3f8b 1264 // INTID 0-15 Software Generated Interrupt
AnnaBridge 165:d1b4690b3f8b 1265 pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
AnnaBridge 165:d1b4690b3f8b 1266 // No CPU identification offered
AnnaBridge 165:d1b4690b3f8b 1267 if (pend != 0U) {
AnnaBridge 165:d1b4690b3f8b 1268 pend = 1U;
AnnaBridge 165:d1b4690b3f8b 1269 } else {
AnnaBridge 165:d1b4690b3f8b 1270 pend = 0U;
AnnaBridge 165:d1b4690b3f8b 1271 }
AnnaBridge 165:d1b4690b3f8b 1272 }
AnnaBridge 165:d1b4690b3f8b 1273
AnnaBridge 165:d1b4690b3f8b 1274 return (pend);
AnnaBridge 165:d1b4690b3f8b 1275 }
AnnaBridge 165:d1b4690b3f8b 1276
AnnaBridge 165:d1b4690b3f8b 1277 /** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
AnnaBridge 165:d1b4690b3f8b 1278 * \param [in] IRQn The interrupt to be enabled.
AnnaBridge 165:d1b4690b3f8b 1279 */
AnnaBridge 165:d1b4690b3f8b 1280 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1281 {
AnnaBridge 165:d1b4690b3f8b 1282 if (IRQn >= 16U) {
AnnaBridge 165:d1b4690b3f8b 1283 GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
AnnaBridge 165:d1b4690b3f8b 1284 } else {
AnnaBridge 165:d1b4690b3f8b 1285 // INTID 0-15 Software Generated Interrupt
AnnaBridge 165:d1b4690b3f8b 1286 GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
AnnaBridge 165:d1b4690b3f8b 1287 // Forward the interrupt to the CPU interface that requested it
AnnaBridge 165:d1b4690b3f8b 1288 GICDistributor->SGIR = (IRQn | 0x02000000U);
AnnaBridge 165:d1b4690b3f8b 1289 }
AnnaBridge 165:d1b4690b3f8b 1290 }
AnnaBridge 165:d1b4690b3f8b 1291
AnnaBridge 165:d1b4690b3f8b 1292 /** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
AnnaBridge 165:d1b4690b3f8b 1293 * \param [in] IRQn The interrupt to be enabled.
AnnaBridge 165:d1b4690b3f8b 1294 */
AnnaBridge 165:d1b4690b3f8b 1295 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1296 {
AnnaBridge 165:d1b4690b3f8b 1297 if (IRQn >= 16U) {
AnnaBridge 165:d1b4690b3f8b 1298 GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
AnnaBridge 165:d1b4690b3f8b 1299 } else {
AnnaBridge 165:d1b4690b3f8b 1300 // INTID 0-15 Software Generated Interrupt
AnnaBridge 165:d1b4690b3f8b 1301 GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
AnnaBridge 165:d1b4690b3f8b 1302 }
AnnaBridge 165:d1b4690b3f8b 1303 }
AnnaBridge 165:d1b4690b3f8b 1304
AnnaBridge 165:d1b4690b3f8b 1305 /** \brief Sets the interrupt configuration using GIC's ICFGR register.
AnnaBridge 165:d1b4690b3f8b 1306 * \param [in] IRQn The interrupt to be configured.
AnnaBridge 165:d1b4690b3f8b 1307 * \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
AnnaBridge 165:d1b4690b3f8b 1308 * Bit 1: 0 - level sensitive, 1 - edge triggered
AnnaBridge 165:d1b4690b3f8b 1309 */
AnnaBridge 165:d1b4690b3f8b 1310 __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
AnnaBridge 165:d1b4690b3f8b 1311 {
AnnaBridge 165:d1b4690b3f8b 1312 uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
AnnaBridge 165:d1b4690b3f8b 1313 uint32_t shift = (IRQn % 16U) << 1U;
AnnaBridge 165:d1b4690b3f8b 1314
AnnaBridge 165:d1b4690b3f8b 1315 icfgr &= (~(3U << shift));
AnnaBridge 165:d1b4690b3f8b 1316 icfgr |= ( int_config << shift);
AnnaBridge 165:d1b4690b3f8b 1317
AnnaBridge 165:d1b4690b3f8b 1318 GICDistributor->ICFGR[IRQn / 16U] = icfgr;
AnnaBridge 165:d1b4690b3f8b 1319 }
AnnaBridge 165:d1b4690b3f8b 1320
AnnaBridge 165:d1b4690b3f8b 1321 /** \brief Get the interrupt configuration from the GIC's ICFGR register.
AnnaBridge 165:d1b4690b3f8b 1322 * \param [in] IRQn Interrupt to acquire the configuration for.
AnnaBridge 165:d1b4690b3f8b 1323 * \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
AnnaBridge 165:d1b4690b3f8b 1324 * Bit 1: 0 - level sensitive, 1 - edge triggered
AnnaBridge 165:d1b4690b3f8b 1325 */
AnnaBridge 165:d1b4690b3f8b 1326 __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1327 {
AnnaBridge 165:d1b4690b3f8b 1328 return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
AnnaBridge 165:d1b4690b3f8b 1329 }
AnnaBridge 165:d1b4690b3f8b 1330
AnnaBridge 165:d1b4690b3f8b 1331 /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
AnnaBridge 165:d1b4690b3f8b 1332 * \param [in] IRQn The interrupt to be configured.
AnnaBridge 165:d1b4690b3f8b 1333 * \param [in] priority The priority for the interrupt, lower values denote higher priorities.
AnnaBridge 165:d1b4690b3f8b 1334 */
AnnaBridge 165:d1b4690b3f8b 1335 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 165:d1b4690b3f8b 1336 {
AnnaBridge 165:d1b4690b3f8b 1337 uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
AnnaBridge 165:d1b4690b3f8b 1338 GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
AnnaBridge 165:d1b4690b3f8b 1339 }
AnnaBridge 165:d1b4690b3f8b 1340
AnnaBridge 165:d1b4690b3f8b 1341 /** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
AnnaBridge 165:d1b4690b3f8b 1342 * \param [in] IRQn The interrupt to be queried.
AnnaBridge 165:d1b4690b3f8b 1343 */
AnnaBridge 165:d1b4690b3f8b 1344 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1345 {
AnnaBridge 165:d1b4690b3f8b 1346 return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
AnnaBridge 165:d1b4690b3f8b 1347 }
AnnaBridge 165:d1b4690b3f8b 1348
AnnaBridge 165:d1b4690b3f8b 1349 /** \brief Set the interrupt priority mask using CPU's PMR register.
AnnaBridge 165:d1b4690b3f8b 1350 * \param [in] priority Priority mask to be set.
AnnaBridge 165:d1b4690b3f8b 1351 */
AnnaBridge 165:d1b4690b3f8b 1352 __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
AnnaBridge 165:d1b4690b3f8b 1353 {
AnnaBridge 165:d1b4690b3f8b 1354 GICInterface->PMR = priority & 0xFFUL; //set priority mask
AnnaBridge 165:d1b4690b3f8b 1355 }
AnnaBridge 165:d1b4690b3f8b 1356
AnnaBridge 165:d1b4690b3f8b 1357 /** \brief Read the current interrupt priority mask from CPU's PMR register.
AnnaBridge 165:d1b4690b3f8b 1358 * \result GICInterface_Type::PMR
AnnaBridge 165:d1b4690b3f8b 1359 */
AnnaBridge 165:d1b4690b3f8b 1360 __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
AnnaBridge 165:d1b4690b3f8b 1361 {
AnnaBridge 165:d1b4690b3f8b 1362 return GICInterface->PMR;
AnnaBridge 165:d1b4690b3f8b 1363 }
AnnaBridge 165:d1b4690b3f8b 1364
AnnaBridge 165:d1b4690b3f8b 1365 /** \brief Configures the group priority and subpriority split point using CPU's BPR register.
AnnaBridge 165:d1b4690b3f8b 1366 * \param [in] binary_point Amount of bits used as subpriority.
AnnaBridge 165:d1b4690b3f8b 1367 */
AnnaBridge 165:d1b4690b3f8b 1368 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
AnnaBridge 165:d1b4690b3f8b 1369 {
AnnaBridge 165:d1b4690b3f8b 1370 GICInterface->BPR = binary_point & 7U; //set binary point
AnnaBridge 165:d1b4690b3f8b 1371 }
AnnaBridge 165:d1b4690b3f8b 1372
AnnaBridge 165:d1b4690b3f8b 1373 /** \brief Read the current group priority and subpriority split point from CPU's BPR register.
AnnaBridge 165:d1b4690b3f8b 1374 * \return GICInterface_Type::BPR
AnnaBridge 165:d1b4690b3f8b 1375 */
AnnaBridge 165:d1b4690b3f8b 1376 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
AnnaBridge 165:d1b4690b3f8b 1377 {
AnnaBridge 165:d1b4690b3f8b 1378 return GICInterface->BPR;
AnnaBridge 165:d1b4690b3f8b 1379 }
AnnaBridge 165:d1b4690b3f8b 1380
AnnaBridge 165:d1b4690b3f8b 1381 /** \brief Get the status for a given interrupt.
AnnaBridge 165:d1b4690b3f8b 1382 * \param [in] IRQn The interrupt to get status for.
AnnaBridge 165:d1b4690b3f8b 1383 * \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
AnnaBridge 165:d1b4690b3f8b 1384 */
AnnaBridge 165:d1b4690b3f8b 1385 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1386 {
AnnaBridge 165:d1b4690b3f8b 1387 uint32_t pending, active;
AnnaBridge 165:d1b4690b3f8b 1388
AnnaBridge 165:d1b4690b3f8b 1389 active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
AnnaBridge 165:d1b4690b3f8b 1390 pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
AnnaBridge 165:d1b4690b3f8b 1391
AnnaBridge 165:d1b4690b3f8b 1392 return ((active<<1U) | pending);
AnnaBridge 165:d1b4690b3f8b 1393 }
AnnaBridge 165:d1b4690b3f8b 1394
AnnaBridge 165:d1b4690b3f8b 1395 /** \brief Generate a software interrupt using GIC's SGIR register.
AnnaBridge 165:d1b4690b3f8b 1396 * \param [in] IRQn Software interrupt to be generated.
AnnaBridge 165:d1b4690b3f8b 1397 * \param [in] target_list List of CPUs the software interrupt should be forwarded to.
AnnaBridge 165:d1b4690b3f8b 1398 * \param [in] filter_list Filter to be applied to determine interrupt receivers.
AnnaBridge 165:d1b4690b3f8b 1399 */
AnnaBridge 165:d1b4690b3f8b 1400 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
AnnaBridge 165:d1b4690b3f8b 1401 {
AnnaBridge 165:d1b4690b3f8b 1402 GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
AnnaBridge 165:d1b4690b3f8b 1403 }
AnnaBridge 165:d1b4690b3f8b 1404
AnnaBridge 165:d1b4690b3f8b 1405 /** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
AnnaBridge 165:d1b4690b3f8b 1406 * \return GICInterface_Type::HPPIR
AnnaBridge 165:d1b4690b3f8b 1407 */
AnnaBridge 165:d1b4690b3f8b 1408 __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
AnnaBridge 165:d1b4690b3f8b 1409 {
AnnaBridge 165:d1b4690b3f8b 1410 return GICInterface->HPPIR;
AnnaBridge 165:d1b4690b3f8b 1411 }
AnnaBridge 165:d1b4690b3f8b 1412
AnnaBridge 165:d1b4690b3f8b 1413 /** \brief Provides information about the implementer and revision of the CPU interface.
AnnaBridge 165:d1b4690b3f8b 1414 * \return GICInterface_Type::IIDR
AnnaBridge 165:d1b4690b3f8b 1415 */
AnnaBridge 165:d1b4690b3f8b 1416 __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
AnnaBridge 165:d1b4690b3f8b 1417 {
AnnaBridge 165:d1b4690b3f8b 1418 return GICInterface->IIDR;
AnnaBridge 165:d1b4690b3f8b 1419 }
AnnaBridge 165:d1b4690b3f8b 1420
AnnaBridge 165:d1b4690b3f8b 1421 /** \brief Set the interrupt group from the GIC's IGROUPR register.
AnnaBridge 165:d1b4690b3f8b 1422 * \param [in] IRQn The interrupt to be queried.
AnnaBridge 165:d1b4690b3f8b 1423 * \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
AnnaBridge 165:d1b4690b3f8b 1424 */
AnnaBridge 165:d1b4690b3f8b 1425 __STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
AnnaBridge 165:d1b4690b3f8b 1426 {
AnnaBridge 165:d1b4690b3f8b 1427 uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
AnnaBridge 165:d1b4690b3f8b 1428 uint32_t shift = (IRQn % 32U);
AnnaBridge 165:d1b4690b3f8b 1429
AnnaBridge 165:d1b4690b3f8b 1430 igroupr &= (~(1U << shift));
AnnaBridge 165:d1b4690b3f8b 1431 igroupr |= ( (group & 1U) << shift);
AnnaBridge 165:d1b4690b3f8b 1432
AnnaBridge 165:d1b4690b3f8b 1433 GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
AnnaBridge 165:d1b4690b3f8b 1434 }
AnnaBridge 165:d1b4690b3f8b 1435 #define GIC_SetSecurity GIC_SetGroup
AnnaBridge 165:d1b4690b3f8b 1436
AnnaBridge 165:d1b4690b3f8b 1437 /** \brief Get the interrupt group from the GIC's IGROUPR register.
AnnaBridge 165:d1b4690b3f8b 1438 * \param [in] IRQn The interrupt to be queried.
AnnaBridge 165:d1b4690b3f8b 1439 * \return 0 - Group 0, 1 - Group 1
AnnaBridge 165:d1b4690b3f8b 1440 */
AnnaBridge 165:d1b4690b3f8b 1441 __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1442 {
AnnaBridge 165:d1b4690b3f8b 1443 return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
AnnaBridge 165:d1b4690b3f8b 1444 }
AnnaBridge 165:d1b4690b3f8b 1445 #define GIC_GetSecurity GIC_GetGroup
AnnaBridge 165:d1b4690b3f8b 1446
AnnaBridge 165:d1b4690b3f8b 1447 /** \brief Initialize the interrupt distributor.
AnnaBridge 165:d1b4690b3f8b 1448 */
AnnaBridge 165:d1b4690b3f8b 1449 __STATIC_INLINE void GIC_DistInit(void)
AnnaBridge 165:d1b4690b3f8b 1450 {
AnnaBridge 165:d1b4690b3f8b 1451 uint32_t i;
AnnaBridge 165:d1b4690b3f8b 1452 uint32_t num_irq = 0U;
AnnaBridge 165:d1b4690b3f8b 1453 uint32_t priority_field;
AnnaBridge 165:d1b4690b3f8b 1454
AnnaBridge 165:d1b4690b3f8b 1455 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
AnnaBridge 165:d1b4690b3f8b 1456 //configuring all of the interrupts as Secure.
AnnaBridge 165:d1b4690b3f8b 1457
AnnaBridge 165:d1b4690b3f8b 1458 //Disable interrupt forwarding
AnnaBridge 165:d1b4690b3f8b 1459 GIC_DisableDistributor();
AnnaBridge 165:d1b4690b3f8b 1460 //Get the maximum number of interrupts that the GIC supports
AnnaBridge 165:d1b4690b3f8b 1461 num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
AnnaBridge 165:d1b4690b3f8b 1462
AnnaBridge 165:d1b4690b3f8b 1463 /* Priority level is implementation defined.
AnnaBridge 165:d1b4690b3f8b 1464 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
AnnaBridge 165:d1b4690b3f8b 1465 priority field and read back the value stored.*/
AnnaBridge 165:d1b4690b3f8b 1466 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
AnnaBridge 165:d1b4690b3f8b 1467 priority_field = GIC_GetPriority((IRQn_Type)0U);
AnnaBridge 165:d1b4690b3f8b 1468
AnnaBridge 165:d1b4690b3f8b 1469 for (i = 32U; i < num_irq; i++)
AnnaBridge 165:d1b4690b3f8b 1470 {
AnnaBridge 165:d1b4690b3f8b 1471 //Disable the SPI interrupt
AnnaBridge 165:d1b4690b3f8b 1472 GIC_DisableIRQ((IRQn_Type)i);
AnnaBridge 165:d1b4690b3f8b 1473 //Set level-sensitive (and N-N model)
AnnaBridge 165:d1b4690b3f8b 1474 GIC_SetConfiguration((IRQn_Type)i, 0U);
AnnaBridge 165:d1b4690b3f8b 1475 //Set priority
AnnaBridge 165:d1b4690b3f8b 1476 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
AnnaBridge 165:d1b4690b3f8b 1477 //Set target list to CPU0
AnnaBridge 165:d1b4690b3f8b 1478 GIC_SetTarget((IRQn_Type)i, 1U);
AnnaBridge 165:d1b4690b3f8b 1479 }
AnnaBridge 165:d1b4690b3f8b 1480 //Enable distributor
AnnaBridge 165:d1b4690b3f8b 1481 GIC_EnableDistributor();
AnnaBridge 165:d1b4690b3f8b 1482 }
AnnaBridge 165:d1b4690b3f8b 1483
AnnaBridge 165:d1b4690b3f8b 1484 /** \brief Initialize the CPU's interrupt interface
AnnaBridge 165:d1b4690b3f8b 1485 */
AnnaBridge 165:d1b4690b3f8b 1486 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
AnnaBridge 165:d1b4690b3f8b 1487 {
AnnaBridge 165:d1b4690b3f8b 1488 uint32_t i;
AnnaBridge 165:d1b4690b3f8b 1489 uint32_t priority_field;
AnnaBridge 165:d1b4690b3f8b 1490
AnnaBridge 165:d1b4690b3f8b 1491 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
AnnaBridge 165:d1b4690b3f8b 1492 //configuring all of the interrupts as Secure.
AnnaBridge 165:d1b4690b3f8b 1493
AnnaBridge 165:d1b4690b3f8b 1494 //Disable interrupt forwarding
AnnaBridge 165:d1b4690b3f8b 1495 GIC_DisableInterface();
AnnaBridge 165:d1b4690b3f8b 1496
AnnaBridge 165:d1b4690b3f8b 1497 /* Priority level is implementation defined.
AnnaBridge 165:d1b4690b3f8b 1498 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
AnnaBridge 165:d1b4690b3f8b 1499 priority field and read back the value stored.*/
AnnaBridge 165:d1b4690b3f8b 1500 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
AnnaBridge 165:d1b4690b3f8b 1501 priority_field = GIC_GetPriority((IRQn_Type)0U);
AnnaBridge 165:d1b4690b3f8b 1502
AnnaBridge 165:d1b4690b3f8b 1503 //SGI and PPI
AnnaBridge 165:d1b4690b3f8b 1504 for (i = 0U; i < 32U; i++)
AnnaBridge 165:d1b4690b3f8b 1505 {
AnnaBridge 165:d1b4690b3f8b 1506 if(i > 15U) {
AnnaBridge 165:d1b4690b3f8b 1507 //Set level-sensitive (and N-N model) for PPI
AnnaBridge 165:d1b4690b3f8b 1508 GIC_SetConfiguration((IRQn_Type)i, 0U);
AnnaBridge 165:d1b4690b3f8b 1509 }
AnnaBridge 165:d1b4690b3f8b 1510 //Disable SGI and PPI interrupts
AnnaBridge 165:d1b4690b3f8b 1511 GIC_DisableIRQ((IRQn_Type)i);
AnnaBridge 165:d1b4690b3f8b 1512 //Set priority
AnnaBridge 165:d1b4690b3f8b 1513 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
AnnaBridge 165:d1b4690b3f8b 1514 }
AnnaBridge 165:d1b4690b3f8b 1515 //Enable interface
AnnaBridge 165:d1b4690b3f8b 1516 GIC_EnableInterface();
AnnaBridge 165:d1b4690b3f8b 1517 //Set binary point to 0
AnnaBridge 165:d1b4690b3f8b 1518 GIC_SetBinaryPoint(0U);
AnnaBridge 165:d1b4690b3f8b 1519 //Set priority mask
AnnaBridge 165:d1b4690b3f8b 1520 GIC_SetInterfacePriorityMask(0xFFU);
AnnaBridge 165:d1b4690b3f8b 1521 }
AnnaBridge 165:d1b4690b3f8b 1522
AnnaBridge 165:d1b4690b3f8b 1523 /** \brief Initialize and enable the GIC
AnnaBridge 165:d1b4690b3f8b 1524 */
AnnaBridge 165:d1b4690b3f8b 1525 __STATIC_INLINE void GIC_Enable(void)
AnnaBridge 165:d1b4690b3f8b 1526 {
AnnaBridge 165:d1b4690b3f8b 1527 GIC_DistInit();
AnnaBridge 165:d1b4690b3f8b 1528 GIC_CPUInterfaceInit(); //per CPU
AnnaBridge 165:d1b4690b3f8b 1529 }
AnnaBridge 165:d1b4690b3f8b 1530 #endif
AnnaBridge 165:d1b4690b3f8b 1531
AnnaBridge 165:d1b4690b3f8b 1532 /* ########################## Generic Timer functions ############################ */
AnnaBridge 165:d1b4690b3f8b 1533 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 1534
AnnaBridge 165:d1b4690b3f8b 1535 /* PL1 Physical Timer */
AnnaBridge 165:d1b4690b3f8b 1536 #if (__CORTEX_A == 7U) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 1537
AnnaBridge 165:d1b4690b3f8b 1538 /** \brief Physical Timer Control register */
AnnaBridge 165:d1b4690b3f8b 1539 typedef union
AnnaBridge 165:d1b4690b3f8b 1540 {
AnnaBridge 165:d1b4690b3f8b 1541 struct
AnnaBridge 165:d1b4690b3f8b 1542 {
AnnaBridge 165:d1b4690b3f8b 1543 uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
AnnaBridge 165:d1b4690b3f8b 1544 uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
AnnaBridge 165:d1b4690b3f8b 1545 uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
AnnaBridge 165:d1b4690b3f8b 1546 RESERVED(0:29, uint32_t)
AnnaBridge 165:d1b4690b3f8b 1547 } b; /*!< \brief Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 1548 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 165:d1b4690b3f8b 1549 } CNTP_CTL_Type;
AnnaBridge 165:d1b4690b3f8b 1550
AnnaBridge 165:d1b4690b3f8b 1551 /** \brief Configures the frequency the timer shall run at.
AnnaBridge 165:d1b4690b3f8b 1552 * \param [in] value The timer frequency in Hz.
AnnaBridge 165:d1b4690b3f8b 1553 */
AnnaBridge 165:d1b4690b3f8b 1554 __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 1555 {
AnnaBridge 165:d1b4690b3f8b 1556 __set_CNTFRQ(value);
AnnaBridge 165:d1b4690b3f8b 1557 __ISB();
AnnaBridge 165:d1b4690b3f8b 1558 }
AnnaBridge 165:d1b4690b3f8b 1559
AnnaBridge 165:d1b4690b3f8b 1560 /** \brief Sets the reset value of the timer.
AnnaBridge 165:d1b4690b3f8b 1561 * \param [in] value The value the timer is loaded with.
AnnaBridge 165:d1b4690b3f8b 1562 */
AnnaBridge 165:d1b4690b3f8b 1563 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 1564 {
AnnaBridge 165:d1b4690b3f8b 1565 __set_CNTP_TVAL(value);
AnnaBridge 165:d1b4690b3f8b 1566 __ISB();
AnnaBridge 165:d1b4690b3f8b 1567 }
AnnaBridge 165:d1b4690b3f8b 1568
AnnaBridge 165:d1b4690b3f8b 1569 /** \brief Get the current counter value.
AnnaBridge 165:d1b4690b3f8b 1570 * \return Current counter value.
AnnaBridge 165:d1b4690b3f8b 1571 */
AnnaBridge 165:d1b4690b3f8b 1572 __STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
AnnaBridge 165:d1b4690b3f8b 1573 {
AnnaBridge 165:d1b4690b3f8b 1574 return(__get_CNTP_TVAL());
AnnaBridge 165:d1b4690b3f8b 1575 }
AnnaBridge 165:d1b4690b3f8b 1576
AnnaBridge 165:d1b4690b3f8b 1577 /** \brief Get the current physical counter value.
AnnaBridge 165:d1b4690b3f8b 1578 * \return Current physical counter value.
AnnaBridge 165:d1b4690b3f8b 1579 */
AnnaBridge 165:d1b4690b3f8b 1580 __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
AnnaBridge 165:d1b4690b3f8b 1581 {
AnnaBridge 165:d1b4690b3f8b 1582 return(__get_CNTPCT());
AnnaBridge 165:d1b4690b3f8b 1583 }
AnnaBridge 165:d1b4690b3f8b 1584
AnnaBridge 165:d1b4690b3f8b 1585 /** \brief Set the physical compare value.
AnnaBridge 165:d1b4690b3f8b 1586 * \param [in] value New physical timer compare value.
AnnaBridge 165:d1b4690b3f8b 1587 */
AnnaBridge 165:d1b4690b3f8b 1588 __STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
AnnaBridge 165:d1b4690b3f8b 1589 {
AnnaBridge 165:d1b4690b3f8b 1590 __set_CNTP_CVAL(value);
AnnaBridge 165:d1b4690b3f8b 1591 __ISB();
AnnaBridge 165:d1b4690b3f8b 1592 }
AnnaBridge 165:d1b4690b3f8b 1593
AnnaBridge 165:d1b4690b3f8b 1594 /** \brief Get the physical compare value.
AnnaBridge 165:d1b4690b3f8b 1595 * \return Physical compare value.
AnnaBridge 165:d1b4690b3f8b 1596 */
AnnaBridge 165:d1b4690b3f8b 1597 __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
AnnaBridge 165:d1b4690b3f8b 1598 {
AnnaBridge 165:d1b4690b3f8b 1599 return(__get_CNTP_CVAL());
AnnaBridge 165:d1b4690b3f8b 1600 }
AnnaBridge 165:d1b4690b3f8b 1601
AnnaBridge 165:d1b4690b3f8b 1602 /** \brief Configure the timer by setting the control value.
AnnaBridge 165:d1b4690b3f8b 1603 * \param [in] value New timer control value.
AnnaBridge 165:d1b4690b3f8b 1604 */
AnnaBridge 165:d1b4690b3f8b 1605 __STATIC_INLINE void PL1_SetControl(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 1606 {
AnnaBridge 165:d1b4690b3f8b 1607 __set_CNTP_CTL(value);
AnnaBridge 165:d1b4690b3f8b 1608 __ISB();
AnnaBridge 165:d1b4690b3f8b 1609 }
AnnaBridge 165:d1b4690b3f8b 1610
AnnaBridge 165:d1b4690b3f8b 1611 /** \brief Get the control value.
AnnaBridge 165:d1b4690b3f8b 1612 * \return Control value.
AnnaBridge 165:d1b4690b3f8b 1613 */
AnnaBridge 165:d1b4690b3f8b 1614 __STATIC_INLINE uint32_t PL1_GetControl(void)
AnnaBridge 165:d1b4690b3f8b 1615 {
AnnaBridge 165:d1b4690b3f8b 1616 return(__get_CNTP_CTL());
AnnaBridge 165:d1b4690b3f8b 1617 }
AnnaBridge 165:d1b4690b3f8b 1618 #endif
AnnaBridge 165:d1b4690b3f8b 1619
AnnaBridge 165:d1b4690b3f8b 1620 /* Private Timer */
AnnaBridge 165:d1b4690b3f8b 1621 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
AnnaBridge 165:d1b4690b3f8b 1622 /** \brief Set the load value to timers LOAD register.
AnnaBridge 165:d1b4690b3f8b 1623 * \param [in] value The load value to be set.
AnnaBridge 165:d1b4690b3f8b 1624 */
AnnaBridge 165:d1b4690b3f8b 1625 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 1626 {
AnnaBridge 165:d1b4690b3f8b 1627 PTIM->LOAD = value;
AnnaBridge 165:d1b4690b3f8b 1628 }
AnnaBridge 165:d1b4690b3f8b 1629
AnnaBridge 165:d1b4690b3f8b 1630 /** \brief Get the load value from timers LOAD register.
AnnaBridge 165:d1b4690b3f8b 1631 * \return Timer_Type::LOAD
AnnaBridge 165:d1b4690b3f8b 1632 */
AnnaBridge 165:d1b4690b3f8b 1633 __STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
AnnaBridge 165:d1b4690b3f8b 1634 {
AnnaBridge 165:d1b4690b3f8b 1635 return(PTIM->LOAD);
AnnaBridge 165:d1b4690b3f8b 1636 }
AnnaBridge 165:d1b4690b3f8b 1637
AnnaBridge 165:d1b4690b3f8b 1638 /** \brief Set current counter value from its COUNTER register.
AnnaBridge 165:d1b4690b3f8b 1639 */
AnnaBridge 165:d1b4690b3f8b 1640 __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 1641 {
AnnaBridge 165:d1b4690b3f8b 1642 PTIM->COUNTER = value;
AnnaBridge 165:d1b4690b3f8b 1643 }
AnnaBridge 165:d1b4690b3f8b 1644
AnnaBridge 165:d1b4690b3f8b 1645 /** \brief Get current counter value from timers COUNTER register.
AnnaBridge 165:d1b4690b3f8b 1646 * \result Timer_Type::COUNTER
AnnaBridge 165:d1b4690b3f8b 1647 */
AnnaBridge 165:d1b4690b3f8b 1648 __STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
AnnaBridge 165:d1b4690b3f8b 1649 {
AnnaBridge 165:d1b4690b3f8b 1650 return(PTIM->COUNTER);
AnnaBridge 165:d1b4690b3f8b 1651 }
AnnaBridge 165:d1b4690b3f8b 1652
AnnaBridge 165:d1b4690b3f8b 1653 /** \brief Configure the timer using its CONTROL register.
AnnaBridge 165:d1b4690b3f8b 1654 * \param [in] value The new configuration value to be set.
AnnaBridge 165:d1b4690b3f8b 1655 */
AnnaBridge 165:d1b4690b3f8b 1656 __STATIC_INLINE void PTIM_SetControl(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 1657 {
AnnaBridge 165:d1b4690b3f8b 1658 PTIM->CONTROL = value;
AnnaBridge 165:d1b4690b3f8b 1659 }
AnnaBridge 165:d1b4690b3f8b 1660
AnnaBridge 165:d1b4690b3f8b 1661 /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
AnnaBridge 165:d1b4690b3f8b 1662 * \return Timer_Type::CONTROL
AnnaBridge 165:d1b4690b3f8b 1663 */
AnnaBridge 165:d1b4690b3f8b 1664 __STATIC_INLINE uint32_t PTIM_GetControl(void)
AnnaBridge 165:d1b4690b3f8b 1665 {
AnnaBridge 165:d1b4690b3f8b 1666 return(PTIM->CONTROL);
AnnaBridge 165:d1b4690b3f8b 1667 }
AnnaBridge 165:d1b4690b3f8b 1668
AnnaBridge 165:d1b4690b3f8b 1669 /** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
AnnaBridge 165:d1b4690b3f8b 1670 * \return 0 - flag is not set, 1- flag is set
AnnaBridge 165:d1b4690b3f8b 1671 */
AnnaBridge 165:d1b4690b3f8b 1672 __STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
AnnaBridge 165:d1b4690b3f8b 1673 {
AnnaBridge 165:d1b4690b3f8b 1674 return (PTIM->ISR & 1UL);
AnnaBridge 165:d1b4690b3f8b 1675 }
AnnaBridge 165:d1b4690b3f8b 1676
AnnaBridge 165:d1b4690b3f8b 1677 /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
AnnaBridge 165:d1b4690b3f8b 1678 */
AnnaBridge 165:d1b4690b3f8b 1679 __STATIC_INLINE void PTIM_ClearEventFlag(void)
AnnaBridge 165:d1b4690b3f8b 1680 {
AnnaBridge 165:d1b4690b3f8b 1681 PTIM->ISR = 1;
AnnaBridge 165:d1b4690b3f8b 1682 }
AnnaBridge 165:d1b4690b3f8b 1683 #endif
AnnaBridge 165:d1b4690b3f8b 1684 #endif
AnnaBridge 165:d1b4690b3f8b 1685
AnnaBridge 165:d1b4690b3f8b 1686 /* ########################## MMU functions ###################################### */
AnnaBridge 165:d1b4690b3f8b 1687
AnnaBridge 165:d1b4690b3f8b 1688 #define SECTION_DESCRIPTOR (0x2)
AnnaBridge 165:d1b4690b3f8b 1689 #define SECTION_MASK (0xFFFFFFFC)
AnnaBridge 165:d1b4690b3f8b 1690
AnnaBridge 165:d1b4690b3f8b 1691 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 165:d1b4690b3f8b 1692 #define SECTION_B_SHIFT (2)
AnnaBridge 165:d1b4690b3f8b 1693 #define SECTION_C_SHIFT (3)
AnnaBridge 165:d1b4690b3f8b 1694 #define SECTION_TEX0_SHIFT (12)
AnnaBridge 165:d1b4690b3f8b 1695 #define SECTION_TEX1_SHIFT (13)
AnnaBridge 165:d1b4690b3f8b 1696 #define SECTION_TEX2_SHIFT (14)
AnnaBridge 165:d1b4690b3f8b 1697
AnnaBridge 165:d1b4690b3f8b 1698 #define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge 165:d1b4690b3f8b 1699 #define SECTION_XN_SHIFT (4)
AnnaBridge 165:d1b4690b3f8b 1700
AnnaBridge 165:d1b4690b3f8b 1701 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 165:d1b4690b3f8b 1702 #define SECTION_DOMAIN_SHIFT (5)
AnnaBridge 165:d1b4690b3f8b 1703
AnnaBridge 165:d1b4690b3f8b 1704 #define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge 165:d1b4690b3f8b 1705 #define SECTION_P_SHIFT (9)
AnnaBridge 165:d1b4690b3f8b 1706
AnnaBridge 165:d1b4690b3f8b 1707 #define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge 165:d1b4690b3f8b 1708 #define SECTION_AP_SHIFT (10)
AnnaBridge 165:d1b4690b3f8b 1709 #define SECTION_AP2_SHIFT (15)
AnnaBridge 165:d1b4690b3f8b 1710
AnnaBridge 165:d1b4690b3f8b 1711 #define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge 165:d1b4690b3f8b 1712 #define SECTION_S_SHIFT (16)
AnnaBridge 165:d1b4690b3f8b 1713
AnnaBridge 165:d1b4690b3f8b 1714 #define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge 165:d1b4690b3f8b 1715 #define SECTION_NG_SHIFT (17)
AnnaBridge 165:d1b4690b3f8b 1716
AnnaBridge 165:d1b4690b3f8b 1717 #define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge 165:d1b4690b3f8b 1718 #define SECTION_NS_SHIFT (19)
AnnaBridge 165:d1b4690b3f8b 1719
AnnaBridge 165:d1b4690b3f8b 1720 #define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge 165:d1b4690b3f8b 1721 #define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge 165:d1b4690b3f8b 1722
AnnaBridge 165:d1b4690b3f8b 1723 #define PAGE_L2_4K_DESC (0x2)
AnnaBridge 165:d1b4690b3f8b 1724 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge 165:d1b4690b3f8b 1725
AnnaBridge 165:d1b4690b3f8b 1726 #define PAGE_L2_64K_DESC (0x1)
AnnaBridge 165:d1b4690b3f8b 1727 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge 165:d1b4690b3f8b 1728
AnnaBridge 165:d1b4690b3f8b 1729 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge 165:d1b4690b3f8b 1730 #define PAGE_4K_B_SHIFT (2)
AnnaBridge 165:d1b4690b3f8b 1731 #define PAGE_4K_C_SHIFT (3)
AnnaBridge 165:d1b4690b3f8b 1732 #define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge 165:d1b4690b3f8b 1733 #define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge 165:d1b4690b3f8b 1734 #define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge 165:d1b4690b3f8b 1735
AnnaBridge 165:d1b4690b3f8b 1736 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 165:d1b4690b3f8b 1737 #define PAGE_64K_B_SHIFT (2)
AnnaBridge 165:d1b4690b3f8b 1738 #define PAGE_64K_C_SHIFT (3)
AnnaBridge 165:d1b4690b3f8b 1739 #define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge 165:d1b4690b3f8b 1740 #define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge 165:d1b4690b3f8b 1741 #define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge 165:d1b4690b3f8b 1742
AnnaBridge 165:d1b4690b3f8b 1743 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 165:d1b4690b3f8b 1744 #define PAGE_B_SHIFT (2)
AnnaBridge 165:d1b4690b3f8b 1745 #define PAGE_C_SHIFT (3)
AnnaBridge 165:d1b4690b3f8b 1746 #define PAGE_TEX_SHIFT (12)
AnnaBridge 165:d1b4690b3f8b 1747
AnnaBridge 165:d1b4690b3f8b 1748 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge 165:d1b4690b3f8b 1749 #define PAGE_XN_4K_SHIFT (0)
AnnaBridge 165:d1b4690b3f8b 1750 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge 165:d1b4690b3f8b 1751 #define PAGE_XN_64K_SHIFT (15)
AnnaBridge 165:d1b4690b3f8b 1752
AnnaBridge 165:d1b4690b3f8b 1753 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 165:d1b4690b3f8b 1754 #define PAGE_DOMAIN_SHIFT (5)
AnnaBridge 165:d1b4690b3f8b 1755
AnnaBridge 165:d1b4690b3f8b 1756 #define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge 165:d1b4690b3f8b 1757 #define PAGE_P_SHIFT (9)
AnnaBridge 165:d1b4690b3f8b 1758
AnnaBridge 165:d1b4690b3f8b 1759 #define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge 165:d1b4690b3f8b 1760 #define PAGE_AP_SHIFT (4)
AnnaBridge 165:d1b4690b3f8b 1761 #define PAGE_AP2_SHIFT (9)
AnnaBridge 165:d1b4690b3f8b 1762
AnnaBridge 165:d1b4690b3f8b 1763 #define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge 165:d1b4690b3f8b 1764 #define PAGE_S_SHIFT (10)
AnnaBridge 165:d1b4690b3f8b 1765
AnnaBridge 165:d1b4690b3f8b 1766 #define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge 165:d1b4690b3f8b 1767 #define PAGE_NG_SHIFT (11)
AnnaBridge 165:d1b4690b3f8b 1768
AnnaBridge 165:d1b4690b3f8b 1769 #define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge 165:d1b4690b3f8b 1770 #define PAGE_NS_SHIFT (3)
AnnaBridge 165:d1b4690b3f8b 1771
AnnaBridge 165:d1b4690b3f8b 1772 #define OFFSET_1M (0x00100000)
AnnaBridge 165:d1b4690b3f8b 1773 #define OFFSET_64K (0x00010000)
AnnaBridge 165:d1b4690b3f8b 1774 #define OFFSET_4K (0x00001000)
AnnaBridge 165:d1b4690b3f8b 1775
AnnaBridge 165:d1b4690b3f8b 1776 #define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge 165:d1b4690b3f8b 1777
AnnaBridge 165:d1b4690b3f8b 1778 /* Attributes enumerations */
AnnaBridge 165:d1b4690b3f8b 1779
AnnaBridge 165:d1b4690b3f8b 1780 /* Region size attributes */
AnnaBridge 165:d1b4690b3f8b 1781 typedef enum
AnnaBridge 165:d1b4690b3f8b 1782 {
AnnaBridge 165:d1b4690b3f8b 1783 SECTION,
AnnaBridge 165:d1b4690b3f8b 1784 PAGE_4k,
AnnaBridge 165:d1b4690b3f8b 1785 PAGE_64k,
AnnaBridge 165:d1b4690b3f8b 1786 } mmu_region_size_Type;
AnnaBridge 165:d1b4690b3f8b 1787
AnnaBridge 165:d1b4690b3f8b 1788 /* Region type attributes */
AnnaBridge 165:d1b4690b3f8b 1789 typedef enum
AnnaBridge 165:d1b4690b3f8b 1790 {
AnnaBridge 165:d1b4690b3f8b 1791 NORMAL,
AnnaBridge 165:d1b4690b3f8b 1792 DEVICE,
AnnaBridge 165:d1b4690b3f8b 1793 SHARED_DEVICE,
AnnaBridge 165:d1b4690b3f8b 1794 NON_SHARED_DEVICE,
AnnaBridge 165:d1b4690b3f8b 1795 STRONGLY_ORDERED
AnnaBridge 165:d1b4690b3f8b 1796 } mmu_memory_Type;
AnnaBridge 165:d1b4690b3f8b 1797
AnnaBridge 165:d1b4690b3f8b 1798 /* Region cacheability attributes */
AnnaBridge 165:d1b4690b3f8b 1799 typedef enum
AnnaBridge 165:d1b4690b3f8b 1800 {
AnnaBridge 165:d1b4690b3f8b 1801 NON_CACHEABLE,
AnnaBridge 165:d1b4690b3f8b 1802 WB_WA,
AnnaBridge 165:d1b4690b3f8b 1803 WT,
AnnaBridge 165:d1b4690b3f8b 1804 WB_NO_WA,
AnnaBridge 165:d1b4690b3f8b 1805 } mmu_cacheability_Type;
AnnaBridge 165:d1b4690b3f8b 1806
AnnaBridge 165:d1b4690b3f8b 1807 /* Region parity check attributes */
AnnaBridge 165:d1b4690b3f8b 1808 typedef enum
AnnaBridge 165:d1b4690b3f8b 1809 {
AnnaBridge 165:d1b4690b3f8b 1810 ECC_DISABLED,
AnnaBridge 165:d1b4690b3f8b 1811 ECC_ENABLED,
AnnaBridge 165:d1b4690b3f8b 1812 } mmu_ecc_check_Type;
AnnaBridge 165:d1b4690b3f8b 1813
AnnaBridge 165:d1b4690b3f8b 1814 /* Region execution attributes */
AnnaBridge 165:d1b4690b3f8b 1815 typedef enum
AnnaBridge 165:d1b4690b3f8b 1816 {
AnnaBridge 165:d1b4690b3f8b 1817 EXECUTE,
AnnaBridge 165:d1b4690b3f8b 1818 NON_EXECUTE,
AnnaBridge 165:d1b4690b3f8b 1819 } mmu_execute_Type;
AnnaBridge 165:d1b4690b3f8b 1820
AnnaBridge 165:d1b4690b3f8b 1821 /* Region global attributes */
AnnaBridge 165:d1b4690b3f8b 1822 typedef enum
AnnaBridge 165:d1b4690b3f8b 1823 {
AnnaBridge 165:d1b4690b3f8b 1824 GLOBAL,
AnnaBridge 165:d1b4690b3f8b 1825 NON_GLOBAL,
AnnaBridge 165:d1b4690b3f8b 1826 } mmu_global_Type;
AnnaBridge 165:d1b4690b3f8b 1827
AnnaBridge 165:d1b4690b3f8b 1828 /* Region shareability attributes */
AnnaBridge 165:d1b4690b3f8b 1829 typedef enum
AnnaBridge 165:d1b4690b3f8b 1830 {
AnnaBridge 165:d1b4690b3f8b 1831 NON_SHARED,
AnnaBridge 165:d1b4690b3f8b 1832 SHARED,
AnnaBridge 165:d1b4690b3f8b 1833 } mmu_shared_Type;
AnnaBridge 165:d1b4690b3f8b 1834
AnnaBridge 165:d1b4690b3f8b 1835 /* Region security attributes */
AnnaBridge 165:d1b4690b3f8b 1836 typedef enum
AnnaBridge 165:d1b4690b3f8b 1837 {
AnnaBridge 165:d1b4690b3f8b 1838 SECURE,
AnnaBridge 165:d1b4690b3f8b 1839 NON_SECURE,
AnnaBridge 165:d1b4690b3f8b 1840 } mmu_secure_Type;
AnnaBridge 165:d1b4690b3f8b 1841
AnnaBridge 165:d1b4690b3f8b 1842 /* Region access attributes */
AnnaBridge 165:d1b4690b3f8b 1843 typedef enum
AnnaBridge 165:d1b4690b3f8b 1844 {
AnnaBridge 165:d1b4690b3f8b 1845 NO_ACCESS,
AnnaBridge 165:d1b4690b3f8b 1846 RW,
AnnaBridge 165:d1b4690b3f8b 1847 READ,
AnnaBridge 165:d1b4690b3f8b 1848 } mmu_access_Type;
AnnaBridge 165:d1b4690b3f8b 1849
AnnaBridge 165:d1b4690b3f8b 1850 /* Memory Region definition */
AnnaBridge 165:d1b4690b3f8b 1851 typedef struct RegionStruct {
AnnaBridge 165:d1b4690b3f8b 1852 mmu_region_size_Type rg_t;
AnnaBridge 165:d1b4690b3f8b 1853 mmu_memory_Type mem_t;
AnnaBridge 165:d1b4690b3f8b 1854 uint8_t domain;
AnnaBridge 165:d1b4690b3f8b 1855 mmu_cacheability_Type inner_norm_t;
AnnaBridge 165:d1b4690b3f8b 1856 mmu_cacheability_Type outer_norm_t;
AnnaBridge 165:d1b4690b3f8b 1857 mmu_ecc_check_Type e_t;
AnnaBridge 165:d1b4690b3f8b 1858 mmu_execute_Type xn_t;
AnnaBridge 165:d1b4690b3f8b 1859 mmu_global_Type g_t;
AnnaBridge 165:d1b4690b3f8b 1860 mmu_secure_Type sec_t;
AnnaBridge 165:d1b4690b3f8b 1861 mmu_access_Type priv_t;
AnnaBridge 165:d1b4690b3f8b 1862 mmu_access_Type user_t;
AnnaBridge 165:d1b4690b3f8b 1863 mmu_shared_Type sh_t;
AnnaBridge 165:d1b4690b3f8b 1864
AnnaBridge 165:d1b4690b3f8b 1865 } mmu_region_attributes_Type;
AnnaBridge 165:d1b4690b3f8b 1866
AnnaBridge 165:d1b4690b3f8b 1867 //Following macros define the descriptors and attributes
AnnaBridge 165:d1b4690b3f8b 1868 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
AnnaBridge 165:d1b4690b3f8b 1869 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 165:d1b4690b3f8b 1870 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1871 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1872 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1873 region.inner_norm_t = WB_WA; \
AnnaBridge 165:d1b4690b3f8b 1874 region.outer_norm_t = WB_WA; \
AnnaBridge 165:d1b4690b3f8b 1875 region.mem_t = NORMAL; \
AnnaBridge 165:d1b4690b3f8b 1876 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1877 region.xn_t = EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1878 region.priv_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1879 region.user_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1880 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1881 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 165:d1b4690b3f8b 1882
AnnaBridge 165:d1b4690b3f8b 1883 //Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
AnnaBridge 165:d1b4690b3f8b 1884 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 165:d1b4690b3f8b 1885 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1886 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1887 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1888 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1889 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1890 region.mem_t = NORMAL; \
AnnaBridge 165:d1b4690b3f8b 1891 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1892 region.xn_t = EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1893 region.priv_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1894 region.user_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1895 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1896 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 165:d1b4690b3f8b 1897
AnnaBridge 165:d1b4690b3f8b 1898 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
AnnaBridge 165:d1b4690b3f8b 1899 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 165:d1b4690b3f8b 1900 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1901 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1902 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1903 region.inner_norm_t = WB_WA; \
AnnaBridge 165:d1b4690b3f8b 1904 region.outer_norm_t = WB_WA; \
AnnaBridge 165:d1b4690b3f8b 1905 region.mem_t = NORMAL; \
AnnaBridge 165:d1b4690b3f8b 1906 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1907 region.xn_t = EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1908 region.priv_t = READ; \
AnnaBridge 165:d1b4690b3f8b 1909 region.user_t = READ; \
AnnaBridge 165:d1b4690b3f8b 1910 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1911 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 165:d1b4690b3f8b 1912
AnnaBridge 165:d1b4690b3f8b 1913 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
AnnaBridge 165:d1b4690b3f8b 1914 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 165:d1b4690b3f8b 1915 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1916 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1917 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1918 region.inner_norm_t = WB_WA; \
AnnaBridge 165:d1b4690b3f8b 1919 region.outer_norm_t = WB_WA; \
AnnaBridge 165:d1b4690b3f8b 1920 region.mem_t = NORMAL; \
AnnaBridge 165:d1b4690b3f8b 1921 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1922 region.xn_t = NON_EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1923 region.priv_t = READ; \
AnnaBridge 165:d1b4690b3f8b 1924 region.user_t = READ; \
AnnaBridge 165:d1b4690b3f8b 1925 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1926 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 165:d1b4690b3f8b 1927
AnnaBridge 165:d1b4690b3f8b 1928 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
AnnaBridge 165:d1b4690b3f8b 1929 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 165:d1b4690b3f8b 1930 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1931 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1932 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1933 region.inner_norm_t = WB_WA; \
AnnaBridge 165:d1b4690b3f8b 1934 region.outer_norm_t = WB_WA; \
AnnaBridge 165:d1b4690b3f8b 1935 region.mem_t = NORMAL; \
AnnaBridge 165:d1b4690b3f8b 1936 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1937 region.xn_t = NON_EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1938 region.priv_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1939 region.user_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1940 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1941 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 165:d1b4690b3f8b 1942 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
AnnaBridge 165:d1b4690b3f8b 1943 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 165:d1b4690b3f8b 1944 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1945 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1946 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1947 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1948 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1949 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 165:d1b4690b3f8b 1950 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1951 region.xn_t = NON_EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1952 region.priv_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1953 region.user_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1954 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1955 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 165:d1b4690b3f8b 1956
AnnaBridge 165:d1b4690b3f8b 1957 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
AnnaBridge 165:d1b4690b3f8b 1958 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 165:d1b4690b3f8b 1959 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1960 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1961 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1962 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1963 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1964 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 165:d1b4690b3f8b 1965 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1966 region.xn_t = NON_EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1967 region.priv_t = READ; \
AnnaBridge 165:d1b4690b3f8b 1968 region.user_t = READ; \
AnnaBridge 165:d1b4690b3f8b 1969 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1970 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 165:d1b4690b3f8b 1971
AnnaBridge 165:d1b4690b3f8b 1972 //Sect_Device_RW. Sect_Device_RO, but writeable
AnnaBridge 165:d1b4690b3f8b 1973 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 165:d1b4690b3f8b 1974 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1975 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1976 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1977 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1978 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1979 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 165:d1b4690b3f8b 1980 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1981 region.xn_t = NON_EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1982 region.priv_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1983 region.user_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1984 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1985 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 165:d1b4690b3f8b 1986 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge 165:d1b4690b3f8b 1987 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
AnnaBridge 165:d1b4690b3f8b 1988 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 1989 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 1990 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 1991 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1992 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 1993 region.mem_t = SHARED_DEVICE; \
AnnaBridge 165:d1b4690b3f8b 1994 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 1995 region.xn_t = NON_EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 1996 region.priv_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1997 region.user_t = RW; \
AnnaBridge 165:d1b4690b3f8b 1998 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 1999 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge 165:d1b4690b3f8b 2000
AnnaBridge 165:d1b4690b3f8b 2001 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge 165:d1b4690b3f8b 2002 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
AnnaBridge 165:d1b4690b3f8b 2003 region.domain = 0x0; \
AnnaBridge 165:d1b4690b3f8b 2004 region.e_t = ECC_DISABLED; \
AnnaBridge 165:d1b4690b3f8b 2005 region.g_t = GLOBAL; \
AnnaBridge 165:d1b4690b3f8b 2006 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 2007 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 165:d1b4690b3f8b 2008 region.mem_t = SHARED_DEVICE; \
AnnaBridge 165:d1b4690b3f8b 2009 region.sec_t = SECURE; \
AnnaBridge 165:d1b4690b3f8b 2010 region.xn_t = NON_EXECUTE; \
AnnaBridge 165:d1b4690b3f8b 2011 region.priv_t = RW; \
AnnaBridge 165:d1b4690b3f8b 2012 region.user_t = RW; \
AnnaBridge 165:d1b4690b3f8b 2013 region.sh_t = NON_SHARED; \
AnnaBridge 165:d1b4690b3f8b 2014 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge 165:d1b4690b3f8b 2015
AnnaBridge 165:d1b4690b3f8b 2016 /** \brief Set section execution-never attribute
AnnaBridge 165:d1b4690b3f8b 2017
AnnaBridge 165:d1b4690b3f8b 2018 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2019 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 165:d1b4690b3f8b 2020
AnnaBridge 165:d1b4690b3f8b 2021 \return 0
AnnaBridge 165:d1b4690b3f8b 2022 */
AnnaBridge 165:d1b4690b3f8b 2023 __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge 165:d1b4690b3f8b 2024 {
AnnaBridge 165:d1b4690b3f8b 2025 *descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge 165:d1b4690b3f8b 2026 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2027 return 0;
AnnaBridge 165:d1b4690b3f8b 2028 }
AnnaBridge 165:d1b4690b3f8b 2029
AnnaBridge 165:d1b4690b3f8b 2030 /** \brief Set section domain
AnnaBridge 165:d1b4690b3f8b 2031
AnnaBridge 165:d1b4690b3f8b 2032 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2033 \param [in] domain Section domain
AnnaBridge 165:d1b4690b3f8b 2034
AnnaBridge 165:d1b4690b3f8b 2035 \return 0
AnnaBridge 165:d1b4690b3f8b 2036 */
AnnaBridge 165:d1b4690b3f8b 2037 __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 165:d1b4690b3f8b 2038 {
AnnaBridge 165:d1b4690b3f8b 2039 *descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge 165:d1b4690b3f8b 2040 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2041 return 0;
AnnaBridge 165:d1b4690b3f8b 2042 }
AnnaBridge 165:d1b4690b3f8b 2043
AnnaBridge 165:d1b4690b3f8b 2044 /** \brief Set section parity check
AnnaBridge 165:d1b4690b3f8b 2045
AnnaBridge 165:d1b4690b3f8b 2046 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2047 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 165:d1b4690b3f8b 2048
AnnaBridge 165:d1b4690b3f8b 2049 \return 0
AnnaBridge 165:d1b4690b3f8b 2050 */
AnnaBridge 165:d1b4690b3f8b 2051 __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 165:d1b4690b3f8b 2052 {
AnnaBridge 165:d1b4690b3f8b 2053 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 165:d1b4690b3f8b 2054 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2055 return 0;
AnnaBridge 165:d1b4690b3f8b 2056 }
AnnaBridge 165:d1b4690b3f8b 2057
AnnaBridge 165:d1b4690b3f8b 2058 /** \brief Set section access privileges
AnnaBridge 165:d1b4690b3f8b 2059
AnnaBridge 165:d1b4690b3f8b 2060 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2061 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 165:d1b4690b3f8b 2062 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 165:d1b4690b3f8b 2063 \param [in] afe Access flag enable
AnnaBridge 165:d1b4690b3f8b 2064
AnnaBridge 165:d1b4690b3f8b 2065 \return 0
AnnaBridge 165:d1b4690b3f8b 2066 */
AnnaBridge 165:d1b4690b3f8b 2067 __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 165:d1b4690b3f8b 2068 {
AnnaBridge 165:d1b4690b3f8b 2069 uint32_t ap = 0;
AnnaBridge 165:d1b4690b3f8b 2070
AnnaBridge 165:d1b4690b3f8b 2071 if (afe == 0) { //full access
AnnaBridge 165:d1b4690b3f8b 2072 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 165:d1b4690b3f8b 2073 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 165:d1b4690b3f8b 2074 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 165:d1b4690b3f8b 2075 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 165:d1b4690b3f8b 2076 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 165:d1b4690b3f8b 2077 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 165:d1b4690b3f8b 2078 }
AnnaBridge 165:d1b4690b3f8b 2079
AnnaBridge 165:d1b4690b3f8b 2080 else { //Simplified access
AnnaBridge 165:d1b4690b3f8b 2081 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 165:d1b4690b3f8b 2082 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 165:d1b4690b3f8b 2083 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 165:d1b4690b3f8b 2084 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 165:d1b4690b3f8b 2085 }
AnnaBridge 165:d1b4690b3f8b 2086
AnnaBridge 165:d1b4690b3f8b 2087 *descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge 165:d1b4690b3f8b 2088 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2089 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2090
AnnaBridge 165:d1b4690b3f8b 2091 return 0;
AnnaBridge 165:d1b4690b3f8b 2092 }
AnnaBridge 165:d1b4690b3f8b 2093
AnnaBridge 165:d1b4690b3f8b 2094 /** \brief Set section shareability
AnnaBridge 165:d1b4690b3f8b 2095
AnnaBridge 165:d1b4690b3f8b 2096 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2097 \param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge 165:d1b4690b3f8b 2098
AnnaBridge 165:d1b4690b3f8b 2099 \return 0
AnnaBridge 165:d1b4690b3f8b 2100 */
AnnaBridge 165:d1b4690b3f8b 2101 __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge 165:d1b4690b3f8b 2102 {
AnnaBridge 165:d1b4690b3f8b 2103 *descriptor_l1 &= SECTION_S_MASK;
AnnaBridge 165:d1b4690b3f8b 2104 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2105 return 0;
AnnaBridge 165:d1b4690b3f8b 2106 }
AnnaBridge 165:d1b4690b3f8b 2107
AnnaBridge 165:d1b4690b3f8b 2108 /** \brief Set section Global attribute
AnnaBridge 165:d1b4690b3f8b 2109
AnnaBridge 165:d1b4690b3f8b 2110 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2111 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge 165:d1b4690b3f8b 2112
AnnaBridge 165:d1b4690b3f8b 2113 \return 0
AnnaBridge 165:d1b4690b3f8b 2114 */
AnnaBridge 165:d1b4690b3f8b 2115 __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge 165:d1b4690b3f8b 2116 {
AnnaBridge 165:d1b4690b3f8b 2117 *descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge 165:d1b4690b3f8b 2118 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2119 return 0;
AnnaBridge 165:d1b4690b3f8b 2120 }
AnnaBridge 165:d1b4690b3f8b 2121
AnnaBridge 165:d1b4690b3f8b 2122 /** \brief Set section Security attribute
AnnaBridge 165:d1b4690b3f8b 2123
AnnaBridge 165:d1b4690b3f8b 2124 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2125 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge 165:d1b4690b3f8b 2126
AnnaBridge 165:d1b4690b3f8b 2127 \return 0
AnnaBridge 165:d1b4690b3f8b 2128 */
AnnaBridge 165:d1b4690b3f8b 2129 __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 165:d1b4690b3f8b 2130 {
AnnaBridge 165:d1b4690b3f8b 2131 *descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge 165:d1b4690b3f8b 2132 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2133 return 0;
AnnaBridge 165:d1b4690b3f8b 2134 }
AnnaBridge 165:d1b4690b3f8b 2135
AnnaBridge 165:d1b4690b3f8b 2136 /* Page 4k or 64k */
AnnaBridge 165:d1b4690b3f8b 2137 /** \brief Set 4k/64k page execution-never attribute
AnnaBridge 165:d1b4690b3f8b 2138
AnnaBridge 165:d1b4690b3f8b 2139 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 165:d1b4690b3f8b 2140 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 165:d1b4690b3f8b 2141 \param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge 165:d1b4690b3f8b 2142
AnnaBridge 165:d1b4690b3f8b 2143 \return 0
AnnaBridge 165:d1b4690b3f8b 2144 */
AnnaBridge 165:d1b4690b3f8b 2145 __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge 165:d1b4690b3f8b 2146 {
AnnaBridge 165:d1b4690b3f8b 2147 if (page == PAGE_4k)
AnnaBridge 165:d1b4690b3f8b 2148 {
AnnaBridge 165:d1b4690b3f8b 2149 *descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge 165:d1b4690b3f8b 2150 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2151 }
AnnaBridge 165:d1b4690b3f8b 2152 else
AnnaBridge 165:d1b4690b3f8b 2153 {
AnnaBridge 165:d1b4690b3f8b 2154 *descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge 165:d1b4690b3f8b 2155 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2156 }
AnnaBridge 165:d1b4690b3f8b 2157 return 0;
AnnaBridge 165:d1b4690b3f8b 2158 }
AnnaBridge 165:d1b4690b3f8b 2159
AnnaBridge 165:d1b4690b3f8b 2160 /** \brief Set 4k/64k page domain
AnnaBridge 165:d1b4690b3f8b 2161
AnnaBridge 165:d1b4690b3f8b 2162 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2163 \param [in] domain Page domain
AnnaBridge 165:d1b4690b3f8b 2164
AnnaBridge 165:d1b4690b3f8b 2165 \return 0
AnnaBridge 165:d1b4690b3f8b 2166 */
AnnaBridge 165:d1b4690b3f8b 2167 __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 165:d1b4690b3f8b 2168 {
AnnaBridge 165:d1b4690b3f8b 2169 *descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge 165:d1b4690b3f8b 2170 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2171 return 0;
AnnaBridge 165:d1b4690b3f8b 2172 }
AnnaBridge 165:d1b4690b3f8b 2173
AnnaBridge 165:d1b4690b3f8b 2174 /** \brief Set 4k/64k page parity check
AnnaBridge 165:d1b4690b3f8b 2175
AnnaBridge 165:d1b4690b3f8b 2176 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2177 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 165:d1b4690b3f8b 2178
AnnaBridge 165:d1b4690b3f8b 2179 \return 0
AnnaBridge 165:d1b4690b3f8b 2180 */
AnnaBridge 165:d1b4690b3f8b 2181 __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 165:d1b4690b3f8b 2182 {
AnnaBridge 165:d1b4690b3f8b 2183 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 165:d1b4690b3f8b 2184 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2185 return 0;
AnnaBridge 165:d1b4690b3f8b 2186 }
AnnaBridge 165:d1b4690b3f8b 2187
AnnaBridge 165:d1b4690b3f8b 2188 /** \brief Set 4k/64k page access privileges
AnnaBridge 165:d1b4690b3f8b 2189
AnnaBridge 165:d1b4690b3f8b 2190 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 165:d1b4690b3f8b 2191 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 165:d1b4690b3f8b 2192 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 165:d1b4690b3f8b 2193 \param [in] afe Access flag enable
AnnaBridge 165:d1b4690b3f8b 2194
AnnaBridge 165:d1b4690b3f8b 2195 \return 0
AnnaBridge 165:d1b4690b3f8b 2196 */
AnnaBridge 165:d1b4690b3f8b 2197 __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 165:d1b4690b3f8b 2198 {
AnnaBridge 165:d1b4690b3f8b 2199 uint32_t ap = 0;
AnnaBridge 165:d1b4690b3f8b 2200
AnnaBridge 165:d1b4690b3f8b 2201 if (afe == 0) { //full access
AnnaBridge 165:d1b4690b3f8b 2202 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 165:d1b4690b3f8b 2203 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 165:d1b4690b3f8b 2204 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 165:d1b4690b3f8b 2205 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 165:d1b4690b3f8b 2206 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 165:d1b4690b3f8b 2207 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge 165:d1b4690b3f8b 2208 }
AnnaBridge 165:d1b4690b3f8b 2209
AnnaBridge 165:d1b4690b3f8b 2210 else { //Simplified access
AnnaBridge 165:d1b4690b3f8b 2211 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 165:d1b4690b3f8b 2212 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 165:d1b4690b3f8b 2213 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 165:d1b4690b3f8b 2214 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 165:d1b4690b3f8b 2215 }
AnnaBridge 165:d1b4690b3f8b 2216
AnnaBridge 165:d1b4690b3f8b 2217 *descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge 165:d1b4690b3f8b 2218 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2219 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2220
AnnaBridge 165:d1b4690b3f8b 2221 return 0;
AnnaBridge 165:d1b4690b3f8b 2222 }
AnnaBridge 165:d1b4690b3f8b 2223
AnnaBridge 165:d1b4690b3f8b 2224 /** \brief Set 4k/64k page shareability
AnnaBridge 165:d1b4690b3f8b 2225
AnnaBridge 165:d1b4690b3f8b 2226 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 165:d1b4690b3f8b 2227 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge 165:d1b4690b3f8b 2228
AnnaBridge 165:d1b4690b3f8b 2229 \return 0
AnnaBridge 165:d1b4690b3f8b 2230 */
AnnaBridge 165:d1b4690b3f8b 2231 __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge 165:d1b4690b3f8b 2232 {
AnnaBridge 165:d1b4690b3f8b 2233 *descriptor_l2 &= PAGE_S_MASK;
AnnaBridge 165:d1b4690b3f8b 2234 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2235 return 0;
AnnaBridge 165:d1b4690b3f8b 2236 }
AnnaBridge 165:d1b4690b3f8b 2237
AnnaBridge 165:d1b4690b3f8b 2238 /** \brief Set 4k/64k page Global attribute
AnnaBridge 165:d1b4690b3f8b 2239
AnnaBridge 165:d1b4690b3f8b 2240 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 165:d1b4690b3f8b 2241 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge 165:d1b4690b3f8b 2242
AnnaBridge 165:d1b4690b3f8b 2243 \return 0
AnnaBridge 165:d1b4690b3f8b 2244 */
AnnaBridge 165:d1b4690b3f8b 2245 __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge 165:d1b4690b3f8b 2246 {
AnnaBridge 165:d1b4690b3f8b 2247 *descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge 165:d1b4690b3f8b 2248 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2249 return 0;
AnnaBridge 165:d1b4690b3f8b 2250 }
AnnaBridge 165:d1b4690b3f8b 2251
AnnaBridge 165:d1b4690b3f8b 2252 /** \brief Set 4k/64k page Security attribute
AnnaBridge 165:d1b4690b3f8b 2253
AnnaBridge 165:d1b4690b3f8b 2254 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2255 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge 165:d1b4690b3f8b 2256
AnnaBridge 165:d1b4690b3f8b 2257 \return 0
AnnaBridge 165:d1b4690b3f8b 2258 */
AnnaBridge 165:d1b4690b3f8b 2259 __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 165:d1b4690b3f8b 2260 {
AnnaBridge 165:d1b4690b3f8b 2261 *descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge 165:d1b4690b3f8b 2262 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2263 return 0;
AnnaBridge 165:d1b4690b3f8b 2264 }
AnnaBridge 165:d1b4690b3f8b 2265
AnnaBridge 165:d1b4690b3f8b 2266 /** \brief Set Section memory attributes
AnnaBridge 165:d1b4690b3f8b 2267
AnnaBridge 165:d1b4690b3f8b 2268 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 165:d1b4690b3f8b 2269 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 165:d1b4690b3f8b 2270 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 165:d1b4690b3f8b 2271 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 165:d1b4690b3f8b 2272
AnnaBridge 165:d1b4690b3f8b 2273 \return 0
AnnaBridge 165:d1b4690b3f8b 2274 */
AnnaBridge 165:d1b4690b3f8b 2275 __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge 165:d1b4690b3f8b 2276 {
AnnaBridge 165:d1b4690b3f8b 2277 *descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge 165:d1b4690b3f8b 2278
AnnaBridge 165:d1b4690b3f8b 2279 if (STRONGLY_ORDERED == mem)
AnnaBridge 165:d1b4690b3f8b 2280 {
AnnaBridge 165:d1b4690b3f8b 2281 return 0;
AnnaBridge 165:d1b4690b3f8b 2282 }
AnnaBridge 165:d1b4690b3f8b 2283 else if (SHARED_DEVICE == mem)
AnnaBridge 165:d1b4690b3f8b 2284 {
AnnaBridge 165:d1b4690b3f8b 2285 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2286 }
AnnaBridge 165:d1b4690b3f8b 2287 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 165:d1b4690b3f8b 2288 {
AnnaBridge 165:d1b4690b3f8b 2289 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2290 }
AnnaBridge 165:d1b4690b3f8b 2291 else if (NORMAL == mem)
AnnaBridge 165:d1b4690b3f8b 2292 {
AnnaBridge 165:d1b4690b3f8b 2293 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2294 switch(inner)
AnnaBridge 165:d1b4690b3f8b 2295 {
AnnaBridge 165:d1b4690b3f8b 2296 case NON_CACHEABLE:
AnnaBridge 165:d1b4690b3f8b 2297 break;
AnnaBridge 165:d1b4690b3f8b 2298 case WB_WA:
AnnaBridge 165:d1b4690b3f8b 2299 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2300 break;
AnnaBridge 165:d1b4690b3f8b 2301 case WT:
AnnaBridge 165:d1b4690b3f8b 2302 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2303 break;
AnnaBridge 165:d1b4690b3f8b 2304 case WB_NO_WA:
AnnaBridge 165:d1b4690b3f8b 2305 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2306 break;
AnnaBridge 165:d1b4690b3f8b 2307 }
AnnaBridge 165:d1b4690b3f8b 2308 switch(outer)
AnnaBridge 165:d1b4690b3f8b 2309 {
AnnaBridge 165:d1b4690b3f8b 2310 case NON_CACHEABLE:
AnnaBridge 165:d1b4690b3f8b 2311 break;
AnnaBridge 165:d1b4690b3f8b 2312 case WB_WA:
AnnaBridge 165:d1b4690b3f8b 2313 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2314 break;
AnnaBridge 165:d1b4690b3f8b 2315 case WT:
AnnaBridge 165:d1b4690b3f8b 2316 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2317 break;
AnnaBridge 165:d1b4690b3f8b 2318 case WB_NO_WA:
AnnaBridge 165:d1b4690b3f8b 2319 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2320 break;
AnnaBridge 165:d1b4690b3f8b 2321 }
AnnaBridge 165:d1b4690b3f8b 2322 }
AnnaBridge 165:d1b4690b3f8b 2323 return 0;
AnnaBridge 165:d1b4690b3f8b 2324 }
AnnaBridge 165:d1b4690b3f8b 2325
AnnaBridge 165:d1b4690b3f8b 2326 /** \brief Set 4k/64k page memory attributes
AnnaBridge 165:d1b4690b3f8b 2327
AnnaBridge 165:d1b4690b3f8b 2328 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 165:d1b4690b3f8b 2329 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 165:d1b4690b3f8b 2330 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 165:d1b4690b3f8b 2331 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 165:d1b4690b3f8b 2332 \param [in] page Page size
AnnaBridge 165:d1b4690b3f8b 2333
AnnaBridge 165:d1b4690b3f8b 2334 \return 0
AnnaBridge 165:d1b4690b3f8b 2335 */
AnnaBridge 165:d1b4690b3f8b 2336 __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge 165:d1b4690b3f8b 2337 {
AnnaBridge 165:d1b4690b3f8b 2338 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge 165:d1b4690b3f8b 2339
AnnaBridge 165:d1b4690b3f8b 2340 if (page == PAGE_64k)
AnnaBridge 165:d1b4690b3f8b 2341 {
AnnaBridge 165:d1b4690b3f8b 2342 //same as section
AnnaBridge 165:d1b4690b3f8b 2343 MMU_MemorySection(descriptor_l2, mem, outer, inner);
AnnaBridge 165:d1b4690b3f8b 2344 }
AnnaBridge 165:d1b4690b3f8b 2345 else
AnnaBridge 165:d1b4690b3f8b 2346 {
AnnaBridge 165:d1b4690b3f8b 2347 if (STRONGLY_ORDERED == mem)
AnnaBridge 165:d1b4690b3f8b 2348 {
AnnaBridge 165:d1b4690b3f8b 2349 return 0;
AnnaBridge 165:d1b4690b3f8b 2350 }
AnnaBridge 165:d1b4690b3f8b 2351 else if (SHARED_DEVICE == mem)
AnnaBridge 165:d1b4690b3f8b 2352 {
AnnaBridge 165:d1b4690b3f8b 2353 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2354 }
AnnaBridge 165:d1b4690b3f8b 2355 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 165:d1b4690b3f8b 2356 {
AnnaBridge 165:d1b4690b3f8b 2357 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2358 }
AnnaBridge 165:d1b4690b3f8b 2359 else if (NORMAL == mem)
AnnaBridge 165:d1b4690b3f8b 2360 {
AnnaBridge 165:d1b4690b3f8b 2361 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2362 switch(inner)
AnnaBridge 165:d1b4690b3f8b 2363 {
AnnaBridge 165:d1b4690b3f8b 2364 case NON_CACHEABLE:
AnnaBridge 165:d1b4690b3f8b 2365 break;
AnnaBridge 165:d1b4690b3f8b 2366 case WB_WA:
AnnaBridge 165:d1b4690b3f8b 2367 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2368 break;
AnnaBridge 165:d1b4690b3f8b 2369 case WT:
AnnaBridge 165:d1b4690b3f8b 2370 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2371 break;
AnnaBridge 165:d1b4690b3f8b 2372 case WB_NO_WA:
AnnaBridge 165:d1b4690b3f8b 2373 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2374 break;
AnnaBridge 165:d1b4690b3f8b 2375 }
AnnaBridge 165:d1b4690b3f8b 2376 switch(outer)
AnnaBridge 165:d1b4690b3f8b 2377 {
AnnaBridge 165:d1b4690b3f8b 2378 case NON_CACHEABLE:
AnnaBridge 165:d1b4690b3f8b 2379 break;
AnnaBridge 165:d1b4690b3f8b 2380 case WB_WA:
AnnaBridge 165:d1b4690b3f8b 2381 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2382 break;
AnnaBridge 165:d1b4690b3f8b 2383 case WT:
AnnaBridge 165:d1b4690b3f8b 2384 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge 165:d1b4690b3f8b 2385 break;
AnnaBridge 165:d1b4690b3f8b 2386 case WB_NO_WA:
AnnaBridge 165:d1b4690b3f8b 2387 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 165:d1b4690b3f8b 2388 break;
AnnaBridge 165:d1b4690b3f8b 2389 }
AnnaBridge 165:d1b4690b3f8b 2390 }
AnnaBridge 165:d1b4690b3f8b 2391 }
AnnaBridge 165:d1b4690b3f8b 2392
AnnaBridge 165:d1b4690b3f8b 2393 return 0;
AnnaBridge 165:d1b4690b3f8b 2394 }
AnnaBridge 165:d1b4690b3f8b 2395
AnnaBridge 165:d1b4690b3f8b 2396 /** \brief Create a L1 section descriptor
AnnaBridge 165:d1b4690b3f8b 2397
AnnaBridge 165:d1b4690b3f8b 2398 \param [out] descriptor L1 descriptor
AnnaBridge 165:d1b4690b3f8b 2399 \param [in] reg Section attributes
AnnaBridge 165:d1b4690b3f8b 2400
AnnaBridge 165:d1b4690b3f8b 2401 \return 0
AnnaBridge 165:d1b4690b3f8b 2402 */
AnnaBridge 165:d1b4690b3f8b 2403 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge 165:d1b4690b3f8b 2404 {
AnnaBridge 165:d1b4690b3f8b 2405 *descriptor = 0;
AnnaBridge 165:d1b4690b3f8b 2406
AnnaBridge 165:d1b4690b3f8b 2407 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge 165:d1b4690b3f8b 2408 MMU_XNSection(descriptor,reg.xn_t);
AnnaBridge 165:d1b4690b3f8b 2409 MMU_DomainSection(descriptor, reg.domain);
AnnaBridge 165:d1b4690b3f8b 2410 MMU_PSection(descriptor, reg.e_t);
AnnaBridge 165:d1b4690b3f8b 2411 MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge 165:d1b4690b3f8b 2412 MMU_SharedSection(descriptor,reg.sh_t);
AnnaBridge 165:d1b4690b3f8b 2413 MMU_GlobalSection(descriptor,reg.g_t);
AnnaBridge 165:d1b4690b3f8b 2414 MMU_SecureSection(descriptor,reg.sec_t);
AnnaBridge 165:d1b4690b3f8b 2415 *descriptor &= SECTION_MASK;
AnnaBridge 165:d1b4690b3f8b 2416 *descriptor |= SECTION_DESCRIPTOR;
AnnaBridge 165:d1b4690b3f8b 2417
AnnaBridge 165:d1b4690b3f8b 2418 return 0;
AnnaBridge 165:d1b4690b3f8b 2419 }
AnnaBridge 165:d1b4690b3f8b 2420
AnnaBridge 165:d1b4690b3f8b 2421
AnnaBridge 165:d1b4690b3f8b 2422 /** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge 165:d1b4690b3f8b 2423
AnnaBridge 165:d1b4690b3f8b 2424 \param [out] descriptor L1 descriptor
AnnaBridge 165:d1b4690b3f8b 2425 \param [out] descriptor2 L2 descriptor
AnnaBridge 165:d1b4690b3f8b 2426 \param [in] reg 4k/64k page attributes
AnnaBridge 165:d1b4690b3f8b 2427
AnnaBridge 165:d1b4690b3f8b 2428 \return 0
AnnaBridge 165:d1b4690b3f8b 2429 */
AnnaBridge 165:d1b4690b3f8b 2430 __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
AnnaBridge 165:d1b4690b3f8b 2431 {
AnnaBridge 165:d1b4690b3f8b 2432 *descriptor = 0;
AnnaBridge 165:d1b4690b3f8b 2433 *descriptor2 = 0;
AnnaBridge 165:d1b4690b3f8b 2434
AnnaBridge 165:d1b4690b3f8b 2435 switch (reg.rg_t)
AnnaBridge 165:d1b4690b3f8b 2436 {
AnnaBridge 165:d1b4690b3f8b 2437 case PAGE_4k:
AnnaBridge 165:d1b4690b3f8b 2438 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge 165:d1b4690b3f8b 2439 MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge 165:d1b4690b3f8b 2440 MMU_DomainPage(descriptor, reg.domain);
AnnaBridge 165:d1b4690b3f8b 2441 MMU_PPage(descriptor, reg.e_t);
AnnaBridge 165:d1b4690b3f8b 2442 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 165:d1b4690b3f8b 2443 MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge 165:d1b4690b3f8b 2444 MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge 165:d1b4690b3f8b 2445 MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge 165:d1b4690b3f8b 2446 *descriptor &= PAGE_L1_MASK;
AnnaBridge 165:d1b4690b3f8b 2447 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 165:d1b4690b3f8b 2448 *descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge 165:d1b4690b3f8b 2449 *descriptor2 |= PAGE_L2_4K_DESC;
AnnaBridge 165:d1b4690b3f8b 2450 break;
AnnaBridge 165:d1b4690b3f8b 2451
AnnaBridge 165:d1b4690b3f8b 2452 case PAGE_64k:
AnnaBridge 165:d1b4690b3f8b 2453 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge 165:d1b4690b3f8b 2454 MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge 165:d1b4690b3f8b 2455 MMU_DomainPage(descriptor, reg.domain);
AnnaBridge 165:d1b4690b3f8b 2456 MMU_PPage(descriptor, reg.e_t);
AnnaBridge 165:d1b4690b3f8b 2457 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 165:d1b4690b3f8b 2458 MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge 165:d1b4690b3f8b 2459 MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge 165:d1b4690b3f8b 2460 MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge 165:d1b4690b3f8b 2461 *descriptor &= PAGE_L1_MASK;
AnnaBridge 165:d1b4690b3f8b 2462 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 165:d1b4690b3f8b 2463 *descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge 165:d1b4690b3f8b 2464 *descriptor2 |= PAGE_L2_64K_DESC;
AnnaBridge 165:d1b4690b3f8b 2465 break;
AnnaBridge 165:d1b4690b3f8b 2466
AnnaBridge 165:d1b4690b3f8b 2467 case SECTION:
AnnaBridge 165:d1b4690b3f8b 2468 //error
AnnaBridge 165:d1b4690b3f8b 2469 break;
AnnaBridge 165:d1b4690b3f8b 2470 }
AnnaBridge 165:d1b4690b3f8b 2471
AnnaBridge 165:d1b4690b3f8b 2472 return 0;
AnnaBridge 165:d1b4690b3f8b 2473 }
AnnaBridge 165:d1b4690b3f8b 2474
AnnaBridge 165:d1b4690b3f8b 2475 /** \brief Create a 1MB Section
AnnaBridge 165:d1b4690b3f8b 2476
AnnaBridge 165:d1b4690b3f8b 2477 \param [in] ttb Translation table base address
AnnaBridge 165:d1b4690b3f8b 2478 \param [in] base_address Section base address
AnnaBridge 165:d1b4690b3f8b 2479 \param [in] count Number of sections to create
AnnaBridge 165:d1b4690b3f8b 2480 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 165:d1b4690b3f8b 2481
AnnaBridge 165:d1b4690b3f8b 2482 */
AnnaBridge 165:d1b4690b3f8b 2483 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge 165:d1b4690b3f8b 2484 {
AnnaBridge 165:d1b4690b3f8b 2485 uint32_t offset;
AnnaBridge 165:d1b4690b3f8b 2486 uint32_t entry;
AnnaBridge 165:d1b4690b3f8b 2487 uint32_t i;
AnnaBridge 165:d1b4690b3f8b 2488
AnnaBridge 165:d1b4690b3f8b 2489 offset = base_address >> 20;
AnnaBridge 165:d1b4690b3f8b 2490 entry = (base_address & 0xFFF00000) | descriptor_l1;
AnnaBridge 165:d1b4690b3f8b 2491
AnnaBridge 165:d1b4690b3f8b 2492 //4 bytes aligned
AnnaBridge 165:d1b4690b3f8b 2493 ttb = ttb + offset;
AnnaBridge 165:d1b4690b3f8b 2494
AnnaBridge 165:d1b4690b3f8b 2495 for (i = 0; i < count; i++ )
AnnaBridge 165:d1b4690b3f8b 2496 {
AnnaBridge 165:d1b4690b3f8b 2497 //4 bytes aligned
AnnaBridge 165:d1b4690b3f8b 2498 *ttb++ = entry;
AnnaBridge 165:d1b4690b3f8b 2499 entry += OFFSET_1M;
AnnaBridge 165:d1b4690b3f8b 2500 }
AnnaBridge 165:d1b4690b3f8b 2501 }
AnnaBridge 165:d1b4690b3f8b 2502
AnnaBridge 165:d1b4690b3f8b 2503 /** \brief Create a 4k page entry
AnnaBridge 165:d1b4690b3f8b 2504
AnnaBridge 165:d1b4690b3f8b 2505 \param [in] ttb L1 table base address
AnnaBridge 165:d1b4690b3f8b 2506 \param [in] base_address 4k base address
AnnaBridge 165:d1b4690b3f8b 2507 \param [in] count Number of 4k pages to create
AnnaBridge 165:d1b4690b3f8b 2508 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 165:d1b4690b3f8b 2509 \param [in] ttb_l2 L2 table base address
AnnaBridge 165:d1b4690b3f8b 2510 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 165:d1b4690b3f8b 2511
AnnaBridge 165:d1b4690b3f8b 2512 */
AnnaBridge 165:d1b4690b3f8b 2513 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 165:d1b4690b3f8b 2514 {
AnnaBridge 165:d1b4690b3f8b 2515
AnnaBridge 165:d1b4690b3f8b 2516 uint32_t offset, offset2;
AnnaBridge 165:d1b4690b3f8b 2517 uint32_t entry, entry2;
AnnaBridge 165:d1b4690b3f8b 2518 uint32_t i;
AnnaBridge 165:d1b4690b3f8b 2519
AnnaBridge 165:d1b4690b3f8b 2520 offset = base_address >> 20;
AnnaBridge 165:d1b4690b3f8b 2521 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 165:d1b4690b3f8b 2522
AnnaBridge 165:d1b4690b3f8b 2523 //4 bytes aligned
AnnaBridge 165:d1b4690b3f8b 2524 ttb += offset;
AnnaBridge 165:d1b4690b3f8b 2525 //create l1_entry
AnnaBridge 165:d1b4690b3f8b 2526 *ttb = entry;
AnnaBridge 165:d1b4690b3f8b 2527
AnnaBridge 165:d1b4690b3f8b 2528 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 165:d1b4690b3f8b 2529 ttb_l2 += offset2;
AnnaBridge 165:d1b4690b3f8b 2530 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
AnnaBridge 165:d1b4690b3f8b 2531 for (i = 0; i < count; i++ )
AnnaBridge 165:d1b4690b3f8b 2532 {
AnnaBridge 165:d1b4690b3f8b 2533 //4 bytes aligned
AnnaBridge 165:d1b4690b3f8b 2534 *ttb_l2++ = entry2;
AnnaBridge 165:d1b4690b3f8b 2535 entry2 += OFFSET_4K;
AnnaBridge 165:d1b4690b3f8b 2536 }
AnnaBridge 165:d1b4690b3f8b 2537 }
AnnaBridge 165:d1b4690b3f8b 2538
AnnaBridge 165:d1b4690b3f8b 2539 /** \brief Create a 64k page entry
AnnaBridge 165:d1b4690b3f8b 2540
AnnaBridge 165:d1b4690b3f8b 2541 \param [in] ttb L1 table base address
AnnaBridge 165:d1b4690b3f8b 2542 \param [in] base_address 64k base address
AnnaBridge 165:d1b4690b3f8b 2543 \param [in] count Number of 64k pages to create
AnnaBridge 165:d1b4690b3f8b 2544 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 165:d1b4690b3f8b 2545 \param [in] ttb_l2 L2 table base address
AnnaBridge 165:d1b4690b3f8b 2546 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 165:d1b4690b3f8b 2547
AnnaBridge 165:d1b4690b3f8b 2548 */
AnnaBridge 165:d1b4690b3f8b 2549 __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 165:d1b4690b3f8b 2550 {
AnnaBridge 165:d1b4690b3f8b 2551 uint32_t offset, offset2;
AnnaBridge 165:d1b4690b3f8b 2552 uint32_t entry, entry2;
AnnaBridge 165:d1b4690b3f8b 2553 uint32_t i,j;
AnnaBridge 165:d1b4690b3f8b 2554
AnnaBridge 165:d1b4690b3f8b 2555
AnnaBridge 165:d1b4690b3f8b 2556 offset = base_address >> 20;
AnnaBridge 165:d1b4690b3f8b 2557 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 165:d1b4690b3f8b 2558
AnnaBridge 165:d1b4690b3f8b 2559 //4 bytes aligned
AnnaBridge 165:d1b4690b3f8b 2560 ttb += offset;
AnnaBridge 165:d1b4690b3f8b 2561 //create l1_entry
AnnaBridge 165:d1b4690b3f8b 2562 *ttb = entry;
AnnaBridge 165:d1b4690b3f8b 2563
AnnaBridge 165:d1b4690b3f8b 2564 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 165:d1b4690b3f8b 2565 ttb_l2 += offset2;
AnnaBridge 165:d1b4690b3f8b 2566 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
AnnaBridge 165:d1b4690b3f8b 2567 for (i = 0; i < count; i++ )
AnnaBridge 165:d1b4690b3f8b 2568 {
AnnaBridge 165:d1b4690b3f8b 2569 //create 16 entries
AnnaBridge 165:d1b4690b3f8b 2570 for (j = 0; j < 16; j++)
AnnaBridge 165:d1b4690b3f8b 2571 {
AnnaBridge 165:d1b4690b3f8b 2572 //4 bytes aligned
AnnaBridge 165:d1b4690b3f8b 2573 *ttb_l2++ = entry2;
AnnaBridge 165:d1b4690b3f8b 2574 }
AnnaBridge 165:d1b4690b3f8b 2575 entry2 += OFFSET_64K;
AnnaBridge 165:d1b4690b3f8b 2576 }
AnnaBridge 165:d1b4690b3f8b 2577 }
AnnaBridge 165:d1b4690b3f8b 2578
AnnaBridge 165:d1b4690b3f8b 2579 /** \brief Enable MMU
AnnaBridge 165:d1b4690b3f8b 2580 */
AnnaBridge 165:d1b4690b3f8b 2581 __STATIC_INLINE void MMU_Enable(void)
AnnaBridge 165:d1b4690b3f8b 2582 {
AnnaBridge 165:d1b4690b3f8b 2583 // Set M bit 0 to enable the MMU
AnnaBridge 165:d1b4690b3f8b 2584 // Set AFE bit to enable simplified access permissions model
AnnaBridge 165:d1b4690b3f8b 2585 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 165:d1b4690b3f8b 2586 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 165:d1b4690b3f8b 2587 __ISB();
AnnaBridge 165:d1b4690b3f8b 2588 }
AnnaBridge 165:d1b4690b3f8b 2589
AnnaBridge 165:d1b4690b3f8b 2590 /** \brief Disable MMU
AnnaBridge 165:d1b4690b3f8b 2591 */
AnnaBridge 165:d1b4690b3f8b 2592 __STATIC_INLINE void MMU_Disable(void)
AnnaBridge 165:d1b4690b3f8b 2593 {
AnnaBridge 165:d1b4690b3f8b 2594 // Clear M bit 0 to disable the MMU
AnnaBridge 165:d1b4690b3f8b 2595 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 165:d1b4690b3f8b 2596 __ISB();
AnnaBridge 165:d1b4690b3f8b 2597 }
AnnaBridge 165:d1b4690b3f8b 2598
AnnaBridge 165:d1b4690b3f8b 2599 /** \brief Invalidate entire unified TLB
AnnaBridge 165:d1b4690b3f8b 2600 */
AnnaBridge 165:d1b4690b3f8b 2601
AnnaBridge 165:d1b4690b3f8b 2602 __STATIC_INLINE void MMU_InvalidateTLB(void)
AnnaBridge 165:d1b4690b3f8b 2603 {
AnnaBridge 165:d1b4690b3f8b 2604 __set_TLBIALL(0);
AnnaBridge 165:d1b4690b3f8b 2605 __DSB(); //ensure completion of the invalidation
AnnaBridge 165:d1b4690b3f8b 2606 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 165:d1b4690b3f8b 2607 }
AnnaBridge 165:d1b4690b3f8b 2608
AnnaBridge 165:d1b4690b3f8b 2609
AnnaBridge 165:d1b4690b3f8b 2610 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 2611 }
AnnaBridge 165:d1b4690b3f8b 2612 #endif
AnnaBridge 165:d1b4690b3f8b 2613
AnnaBridge 165:d1b4690b3f8b 2614 #endif /* __CORE_CA_H_DEPENDANT */
AnnaBridge 165:d1b4690b3f8b 2615
AnnaBridge 165:d1b4690b3f8b 2616 #endif /* __CMSIS_GENERIC */