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TARGET_VK_RZ_A1H/cmsis_gcc.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
165:d1b4690b3f8b
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /**************************************************************************//**
AnnaBridge 165:d1b4690b3f8b 2 * @file cmsis_gcc.h
AnnaBridge 165:d1b4690b3f8b 3 * @brief CMSIS compiler specific macros, functions, instructions
AnnaBridge 165:d1b4690b3f8b 4 * @version V1.0.1
AnnaBridge 165:d1b4690b3f8b 5 * @date 07. Sep 2017
AnnaBridge 165:d1b4690b3f8b 6 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 7 /*
AnnaBridge 165:d1b4690b3f8b 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 165:d1b4690b3f8b 9 *
AnnaBridge 165:d1b4690b3f8b 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 165:d1b4690b3f8b 11 *
AnnaBridge 165:d1b4690b3f8b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 165:d1b4690b3f8b 13 * not use this file except in compliance with the License.
AnnaBridge 165:d1b4690b3f8b 14 * You may obtain a copy of the License at
AnnaBridge 165:d1b4690b3f8b 15 *
AnnaBridge 165:d1b4690b3f8b 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 165:d1b4690b3f8b 17 *
AnnaBridge 165:d1b4690b3f8b 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 165:d1b4690b3f8b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 165:d1b4690b3f8b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 165:d1b4690b3f8b 21 * See the License for the specific language governing permissions and
AnnaBridge 165:d1b4690b3f8b 22 * limitations under the License.
AnnaBridge 165:d1b4690b3f8b 23 */
AnnaBridge 165:d1b4690b3f8b 24
AnnaBridge 165:d1b4690b3f8b 25 #ifndef __CMSIS_GCC_H
AnnaBridge 165:d1b4690b3f8b 26 #define __CMSIS_GCC_H
AnnaBridge 165:d1b4690b3f8b 27
AnnaBridge 165:d1b4690b3f8b 28 /* ignore some GCC warnings */
AnnaBridge 165:d1b4690b3f8b 29 #pragma GCC diagnostic push
AnnaBridge 165:d1b4690b3f8b 30 #pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge 165:d1b4690b3f8b 31 #pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge 165:d1b4690b3f8b 32 #pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge 165:d1b4690b3f8b 33
AnnaBridge 165:d1b4690b3f8b 34 /* Fallback for __has_builtin */
AnnaBridge 165:d1b4690b3f8b 35 #ifndef __has_builtin
AnnaBridge 165:d1b4690b3f8b 36 #define __has_builtin(x) (0)
AnnaBridge 165:d1b4690b3f8b 37 #endif
AnnaBridge 165:d1b4690b3f8b 38
AnnaBridge 165:d1b4690b3f8b 39 /* CMSIS compiler specific defines */
AnnaBridge 165:d1b4690b3f8b 40 #ifndef __ASM
AnnaBridge 165:d1b4690b3f8b 41 #define __ASM asm
AnnaBridge 165:d1b4690b3f8b 42 #endif
AnnaBridge 165:d1b4690b3f8b 43 #ifndef __INLINE
AnnaBridge 165:d1b4690b3f8b 44 #define __INLINE inline
AnnaBridge 165:d1b4690b3f8b 45 #endif
AnnaBridge 165:d1b4690b3f8b 46 #ifndef __FORCEINLINE
AnnaBridge 165:d1b4690b3f8b 47 #define __FORCEINLINE __attribute__((always_inline))
AnnaBridge 165:d1b4690b3f8b 48 #endif
AnnaBridge 165:d1b4690b3f8b 49 #ifndef __STATIC_INLINE
AnnaBridge 165:d1b4690b3f8b 50 #define __STATIC_INLINE static inline
AnnaBridge 165:d1b4690b3f8b 51 #endif
AnnaBridge 165:d1b4690b3f8b 52 #ifndef __STATIC_FORCEINLINE
AnnaBridge 165:d1b4690b3f8b 53 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
AnnaBridge 165:d1b4690b3f8b 54 #endif
AnnaBridge 165:d1b4690b3f8b 55 #ifndef __NO_RETURN
AnnaBridge 165:d1b4690b3f8b 56 #define __NO_RETURN __attribute__((__noreturn__))
AnnaBridge 165:d1b4690b3f8b 57 #endif
AnnaBridge 165:d1b4690b3f8b 58 #ifndef CMSIS_DEPRECATED
AnnaBridge 165:d1b4690b3f8b 59 #define CMSIS_DEPRECATED __attribute__((deprecated))
AnnaBridge 165:d1b4690b3f8b 60 #endif
AnnaBridge 165:d1b4690b3f8b 61 #ifndef __USED
AnnaBridge 165:d1b4690b3f8b 62 #define __USED __attribute__((used))
AnnaBridge 165:d1b4690b3f8b 63 #endif
AnnaBridge 165:d1b4690b3f8b 64 #ifndef __WEAK
AnnaBridge 165:d1b4690b3f8b 65 #define __WEAK __attribute__((weak))
AnnaBridge 165:d1b4690b3f8b 66 #endif
AnnaBridge 165:d1b4690b3f8b 67 #ifndef __PACKED
AnnaBridge 165:d1b4690b3f8b 68 #define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge 165:d1b4690b3f8b 69 #endif
AnnaBridge 165:d1b4690b3f8b 70 #ifndef __PACKED_STRUCT
AnnaBridge 165:d1b4690b3f8b 71 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge 165:d1b4690b3f8b 72 #endif
AnnaBridge 165:d1b4690b3f8b 73 #ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge 165:d1b4690b3f8b 74 #pragma GCC diagnostic push
AnnaBridge 165:d1b4690b3f8b 75 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 165:d1b4690b3f8b 76 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
AnnaBridge 165:d1b4690b3f8b 77 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge 165:d1b4690b3f8b 78 #pragma GCC diagnostic pop
AnnaBridge 165:d1b4690b3f8b 79 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 165:d1b4690b3f8b 80 #endif
AnnaBridge 165:d1b4690b3f8b 81 #ifndef __UNALIGNED_UINT16_READ
AnnaBridge 165:d1b4690b3f8b 82 #pragma GCC diagnostic push
AnnaBridge 165:d1b4690b3f8b 83 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 165:d1b4690b3f8b 84 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
AnnaBridge 165:d1b4690b3f8b 85 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge 165:d1b4690b3f8b 86 #pragma GCC diagnostic pop
AnnaBridge 165:d1b4690b3f8b 87 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
AnnaBridge 165:d1b4690b3f8b 88 #endif
AnnaBridge 165:d1b4690b3f8b 89 #ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge 165:d1b4690b3f8b 90 #pragma GCC diagnostic push
AnnaBridge 165:d1b4690b3f8b 91 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 165:d1b4690b3f8b 92 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
AnnaBridge 165:d1b4690b3f8b 93 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge 165:d1b4690b3f8b 94 #pragma GCC diagnostic pop
AnnaBridge 165:d1b4690b3f8b 95 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 165:d1b4690b3f8b 96 #endif
AnnaBridge 165:d1b4690b3f8b 97 #ifndef __UNALIGNED_UINT32_READ
AnnaBridge 165:d1b4690b3f8b 98 #pragma GCC diagnostic push
AnnaBridge 165:d1b4690b3f8b 99 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 165:d1b4690b3f8b 100 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge 165:d1b4690b3f8b 101 #pragma GCC diagnostic pop
AnnaBridge 165:d1b4690b3f8b 102 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
AnnaBridge 165:d1b4690b3f8b 103 #endif
AnnaBridge 165:d1b4690b3f8b 104 #ifndef __ALIGNED
AnnaBridge 165:d1b4690b3f8b 105 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 165:d1b4690b3f8b 106 #endif
AnnaBridge 165:d1b4690b3f8b 107
AnnaBridge 165:d1b4690b3f8b 108 /* ########################## Core Instruction Access ######################### */
AnnaBridge 165:d1b4690b3f8b 109 /**
AnnaBridge 165:d1b4690b3f8b 110 \brief No Operation
AnnaBridge 165:d1b4690b3f8b 111 */
AnnaBridge 165:d1b4690b3f8b 112 #define __NOP() __ASM volatile ("nop")
AnnaBridge 165:d1b4690b3f8b 113
AnnaBridge 165:d1b4690b3f8b 114 /**
AnnaBridge 165:d1b4690b3f8b 115 \brief Wait For Interrupt
AnnaBridge 165:d1b4690b3f8b 116 */
AnnaBridge 165:d1b4690b3f8b 117 #define __WFI() __ASM volatile ("wfi")
AnnaBridge 165:d1b4690b3f8b 118
AnnaBridge 165:d1b4690b3f8b 119 /**
AnnaBridge 165:d1b4690b3f8b 120 \brief Wait For Event
AnnaBridge 165:d1b4690b3f8b 121 */
AnnaBridge 165:d1b4690b3f8b 122 #define __WFE() __ASM volatile ("wfe")
AnnaBridge 165:d1b4690b3f8b 123
AnnaBridge 165:d1b4690b3f8b 124 /**
AnnaBridge 165:d1b4690b3f8b 125 \brief Send Event
AnnaBridge 165:d1b4690b3f8b 126 */
AnnaBridge 165:d1b4690b3f8b 127 #define __SEV() __ASM volatile ("sev")
AnnaBridge 165:d1b4690b3f8b 128
AnnaBridge 165:d1b4690b3f8b 129 /**
AnnaBridge 165:d1b4690b3f8b 130 \brief Instruction Synchronization Barrier
AnnaBridge 165:d1b4690b3f8b 131 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge 165:d1b4690b3f8b 132 so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge 165:d1b4690b3f8b 133 after the instruction has been completed.
AnnaBridge 165:d1b4690b3f8b 134 */
AnnaBridge 165:d1b4690b3f8b 135 __STATIC_FORCEINLINE void __ISB(void)
AnnaBridge 165:d1b4690b3f8b 136 {
AnnaBridge 165:d1b4690b3f8b 137 __ASM volatile ("isb 0xF":::"memory");
AnnaBridge 165:d1b4690b3f8b 138 }
AnnaBridge 165:d1b4690b3f8b 139
AnnaBridge 165:d1b4690b3f8b 140
AnnaBridge 165:d1b4690b3f8b 141 /**
AnnaBridge 165:d1b4690b3f8b 142 \brief Data Synchronization Barrier
AnnaBridge 165:d1b4690b3f8b 143 \details Acts as a special kind of Data Memory Barrier.
AnnaBridge 165:d1b4690b3f8b 144 It completes when all explicit memory accesses before this instruction complete.
AnnaBridge 165:d1b4690b3f8b 145 */
AnnaBridge 165:d1b4690b3f8b 146 __STATIC_FORCEINLINE void __DSB(void)
AnnaBridge 165:d1b4690b3f8b 147 {
AnnaBridge 165:d1b4690b3f8b 148 __ASM volatile ("dsb 0xF":::"memory");
AnnaBridge 165:d1b4690b3f8b 149 }
AnnaBridge 165:d1b4690b3f8b 150
AnnaBridge 165:d1b4690b3f8b 151 /**
AnnaBridge 165:d1b4690b3f8b 152 \brief Data Memory Barrier
AnnaBridge 165:d1b4690b3f8b 153 \details Ensures the apparent order of the explicit memory operations before
AnnaBridge 165:d1b4690b3f8b 154 and after the instruction, without ensuring their completion.
AnnaBridge 165:d1b4690b3f8b 155 */
AnnaBridge 165:d1b4690b3f8b 156 __STATIC_FORCEINLINE void __DMB(void)
AnnaBridge 165:d1b4690b3f8b 157 {
AnnaBridge 165:d1b4690b3f8b 158 __ASM volatile ("dmb 0xF":::"memory");
AnnaBridge 165:d1b4690b3f8b 159 }
AnnaBridge 165:d1b4690b3f8b 160
AnnaBridge 165:d1b4690b3f8b 161 /**
AnnaBridge 165:d1b4690b3f8b 162 \brief Reverse byte order (32 bit)
AnnaBridge 165:d1b4690b3f8b 163 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
AnnaBridge 165:d1b4690b3f8b 164 \param [in] value Value to reverse
AnnaBridge 165:d1b4690b3f8b 165 \return Reversed value
AnnaBridge 165:d1b4690b3f8b 166 */
AnnaBridge 165:d1b4690b3f8b 167 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 168 {
AnnaBridge 165:d1b4690b3f8b 169 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge 165:d1b4690b3f8b 170 return __builtin_bswap32(value);
AnnaBridge 165:d1b4690b3f8b 171 #else
AnnaBridge 165:d1b4690b3f8b 172 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 173
AnnaBridge 165:d1b4690b3f8b 174 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 165:d1b4690b3f8b 175 return result;
AnnaBridge 165:d1b4690b3f8b 176 #endif
AnnaBridge 165:d1b4690b3f8b 177 }
AnnaBridge 165:d1b4690b3f8b 178
AnnaBridge 165:d1b4690b3f8b 179 /**
AnnaBridge 165:d1b4690b3f8b 180 \brief Reverse byte order (16 bit)
AnnaBridge 165:d1b4690b3f8b 181 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
AnnaBridge 165:d1b4690b3f8b 182 \param [in] value Value to reverse
AnnaBridge 165:d1b4690b3f8b 183 \return Reversed value
AnnaBridge 165:d1b4690b3f8b 184 */
AnnaBridge 165:d1b4690b3f8b 185 #ifndef __NO_EMBEDDED_ASM
AnnaBridge 165:d1b4690b3f8b 186 __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 187 {
AnnaBridge 165:d1b4690b3f8b 188 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 189 __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
AnnaBridge 165:d1b4690b3f8b 190 return result;
AnnaBridge 165:d1b4690b3f8b 191 }
AnnaBridge 165:d1b4690b3f8b 192 #endif
AnnaBridge 165:d1b4690b3f8b 193
AnnaBridge 165:d1b4690b3f8b 194 /**
AnnaBridge 165:d1b4690b3f8b 195 \brief Reverse byte order (16 bit)
AnnaBridge 165:d1b4690b3f8b 196 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
AnnaBridge 165:d1b4690b3f8b 197 \param [in] value Value to reverse
AnnaBridge 165:d1b4690b3f8b 198 \return Reversed value
AnnaBridge 165:d1b4690b3f8b 199 */
AnnaBridge 165:d1b4690b3f8b 200 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
AnnaBridge 165:d1b4690b3f8b 201 {
AnnaBridge 165:d1b4690b3f8b 202 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 165:d1b4690b3f8b 203 return (int16_t)__builtin_bswap16(value);
AnnaBridge 165:d1b4690b3f8b 204 #else
AnnaBridge 165:d1b4690b3f8b 205 int16_t result;
AnnaBridge 165:d1b4690b3f8b 206
AnnaBridge 165:d1b4690b3f8b 207 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 165:d1b4690b3f8b 208 return result;
AnnaBridge 165:d1b4690b3f8b 209 #endif
AnnaBridge 165:d1b4690b3f8b 210 }
AnnaBridge 165:d1b4690b3f8b 211
AnnaBridge 165:d1b4690b3f8b 212 /**
AnnaBridge 165:d1b4690b3f8b 213 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 165:d1b4690b3f8b 214 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 165:d1b4690b3f8b 215 \param [in] op1 Value to rotate
AnnaBridge 165:d1b4690b3f8b 216 \param [in] op2 Number of Bits to rotate
AnnaBridge 165:d1b4690b3f8b 217 \return Rotated value
AnnaBridge 165:d1b4690b3f8b 218 */
AnnaBridge 165:d1b4690b3f8b 219 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 165:d1b4690b3f8b 220 {
AnnaBridge 165:d1b4690b3f8b 221 op2 %= 32U;
AnnaBridge 165:d1b4690b3f8b 222 if (op2 == 0U) {
AnnaBridge 165:d1b4690b3f8b 223 return op1;
AnnaBridge 165:d1b4690b3f8b 224 }
AnnaBridge 165:d1b4690b3f8b 225 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 165:d1b4690b3f8b 226 }
AnnaBridge 165:d1b4690b3f8b 227
AnnaBridge 165:d1b4690b3f8b 228
AnnaBridge 165:d1b4690b3f8b 229 /**
AnnaBridge 165:d1b4690b3f8b 230 \brief Breakpoint
AnnaBridge 165:d1b4690b3f8b 231 \param [in] value is ignored by the processor.
AnnaBridge 165:d1b4690b3f8b 232 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 165:d1b4690b3f8b 233 */
AnnaBridge 165:d1b4690b3f8b 234 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 165:d1b4690b3f8b 235
AnnaBridge 165:d1b4690b3f8b 236 /**
AnnaBridge 165:d1b4690b3f8b 237 \brief Reverse bit order of value
AnnaBridge 165:d1b4690b3f8b 238 \details Reverses the bit order of the given value.
AnnaBridge 165:d1b4690b3f8b 239 \param [in] value Value to reverse
AnnaBridge 165:d1b4690b3f8b 240 \return Reversed value
AnnaBridge 165:d1b4690b3f8b 241 */
AnnaBridge 165:d1b4690b3f8b 242 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
AnnaBridge 165:d1b4690b3f8b 243 {
AnnaBridge 165:d1b4690b3f8b 244 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 245
AnnaBridge 165:d1b4690b3f8b 246 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 165:d1b4690b3f8b 247 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 165:d1b4690b3f8b 248 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 165:d1b4690b3f8b 249 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge 165:d1b4690b3f8b 250 #else
AnnaBridge 165:d1b4690b3f8b 251 int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
AnnaBridge 165:d1b4690b3f8b 252
AnnaBridge 165:d1b4690b3f8b 253 result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge 165:d1b4690b3f8b 254 for (value >>= 1U; value; value >>= 1U)
AnnaBridge 165:d1b4690b3f8b 255 {
AnnaBridge 165:d1b4690b3f8b 256 result <<= 1U;
AnnaBridge 165:d1b4690b3f8b 257 result |= value & 1U;
AnnaBridge 165:d1b4690b3f8b 258 s--;
AnnaBridge 165:d1b4690b3f8b 259 }
AnnaBridge 165:d1b4690b3f8b 260 result <<= s; /* shift when v's highest bits are zero */
AnnaBridge 165:d1b4690b3f8b 261 #endif
AnnaBridge 165:d1b4690b3f8b 262 return result;
AnnaBridge 165:d1b4690b3f8b 263 }
AnnaBridge 165:d1b4690b3f8b 264
AnnaBridge 165:d1b4690b3f8b 265 /**
AnnaBridge 165:d1b4690b3f8b 266 \brief Count leading zeros
AnnaBridge 165:d1b4690b3f8b 267 \param [in] value Value to count the leading zeros
AnnaBridge 165:d1b4690b3f8b 268 \return number of leading zeros in value
AnnaBridge 165:d1b4690b3f8b 269 */
AnnaBridge 165:d1b4690b3f8b 270 #define __CLZ (uint8_t)__builtin_clz
AnnaBridge 165:d1b4690b3f8b 271
AnnaBridge 165:d1b4690b3f8b 272 /**
AnnaBridge 165:d1b4690b3f8b 273 \brief LDR Exclusive (8 bit)
AnnaBridge 165:d1b4690b3f8b 274 \details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge 165:d1b4690b3f8b 275 \param [in] ptr Pointer to data
AnnaBridge 165:d1b4690b3f8b 276 \return value of type uint8_t at (*ptr)
AnnaBridge 165:d1b4690b3f8b 277 */
AnnaBridge 165:d1b4690b3f8b 278 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge 165:d1b4690b3f8b 279 {
AnnaBridge 165:d1b4690b3f8b 280 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 281
AnnaBridge 165:d1b4690b3f8b 282 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 165:d1b4690b3f8b 283 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 165:d1b4690b3f8b 284 #else
AnnaBridge 165:d1b4690b3f8b 285 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 165:d1b4690b3f8b 286 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 165:d1b4690b3f8b 287 */
AnnaBridge 165:d1b4690b3f8b 288 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge 165:d1b4690b3f8b 289 #endif
AnnaBridge 165:d1b4690b3f8b 290 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 165:d1b4690b3f8b 291 }
AnnaBridge 165:d1b4690b3f8b 292
AnnaBridge 165:d1b4690b3f8b 293
AnnaBridge 165:d1b4690b3f8b 294 /**
AnnaBridge 165:d1b4690b3f8b 295 \brief LDR Exclusive (16 bit)
AnnaBridge 165:d1b4690b3f8b 296 \details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge 165:d1b4690b3f8b 297 \param [in] ptr Pointer to data
AnnaBridge 165:d1b4690b3f8b 298 \return value of type uint16_t at (*ptr)
AnnaBridge 165:d1b4690b3f8b 299 */
AnnaBridge 165:d1b4690b3f8b 300 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge 165:d1b4690b3f8b 301 {
AnnaBridge 165:d1b4690b3f8b 302 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 303
AnnaBridge 165:d1b4690b3f8b 304 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 165:d1b4690b3f8b 305 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 165:d1b4690b3f8b 306 #else
AnnaBridge 165:d1b4690b3f8b 307 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 165:d1b4690b3f8b 308 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 165:d1b4690b3f8b 309 */
AnnaBridge 165:d1b4690b3f8b 310 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge 165:d1b4690b3f8b 311 #endif
AnnaBridge 165:d1b4690b3f8b 312 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 165:d1b4690b3f8b 313 }
AnnaBridge 165:d1b4690b3f8b 314
AnnaBridge 165:d1b4690b3f8b 315
AnnaBridge 165:d1b4690b3f8b 316 /**
AnnaBridge 165:d1b4690b3f8b 317 \brief LDR Exclusive (32 bit)
AnnaBridge 165:d1b4690b3f8b 318 \details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge 165:d1b4690b3f8b 319 \param [in] ptr Pointer to data
AnnaBridge 165:d1b4690b3f8b 320 \return value of type uint32_t at (*ptr)
AnnaBridge 165:d1b4690b3f8b 321 */
AnnaBridge 165:d1b4690b3f8b 322 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge 165:d1b4690b3f8b 323 {
AnnaBridge 165:d1b4690b3f8b 324 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 325
AnnaBridge 165:d1b4690b3f8b 326 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 165:d1b4690b3f8b 327 return(result);
AnnaBridge 165:d1b4690b3f8b 328 }
AnnaBridge 165:d1b4690b3f8b 329
AnnaBridge 165:d1b4690b3f8b 330
AnnaBridge 165:d1b4690b3f8b 331 /**
AnnaBridge 165:d1b4690b3f8b 332 \brief STR Exclusive (8 bit)
AnnaBridge 165:d1b4690b3f8b 333 \details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge 165:d1b4690b3f8b 334 \param [in] value Value to store
AnnaBridge 165:d1b4690b3f8b 335 \param [in] ptr Pointer to location
AnnaBridge 165:d1b4690b3f8b 336 \return 0 Function succeeded
AnnaBridge 165:d1b4690b3f8b 337 \return 1 Function failed
AnnaBridge 165:d1b4690b3f8b 338 */
AnnaBridge 165:d1b4690b3f8b 339 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge 165:d1b4690b3f8b 340 {
AnnaBridge 165:d1b4690b3f8b 341 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 342
AnnaBridge 165:d1b4690b3f8b 343 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge 165:d1b4690b3f8b 344 return(result);
AnnaBridge 165:d1b4690b3f8b 345 }
AnnaBridge 165:d1b4690b3f8b 346
AnnaBridge 165:d1b4690b3f8b 347
AnnaBridge 165:d1b4690b3f8b 348 /**
AnnaBridge 165:d1b4690b3f8b 349 \brief STR Exclusive (16 bit)
AnnaBridge 165:d1b4690b3f8b 350 \details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge 165:d1b4690b3f8b 351 \param [in] value Value to store
AnnaBridge 165:d1b4690b3f8b 352 \param [in] ptr Pointer to location
AnnaBridge 165:d1b4690b3f8b 353 \return 0 Function succeeded
AnnaBridge 165:d1b4690b3f8b 354 \return 1 Function failed
AnnaBridge 165:d1b4690b3f8b 355 */
AnnaBridge 165:d1b4690b3f8b 356 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge 165:d1b4690b3f8b 357 {
AnnaBridge 165:d1b4690b3f8b 358 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 359
AnnaBridge 165:d1b4690b3f8b 360 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge 165:d1b4690b3f8b 361 return(result);
AnnaBridge 165:d1b4690b3f8b 362 }
AnnaBridge 165:d1b4690b3f8b 363
AnnaBridge 165:d1b4690b3f8b 364
AnnaBridge 165:d1b4690b3f8b 365 /**
AnnaBridge 165:d1b4690b3f8b 366 \brief STR Exclusive (32 bit)
AnnaBridge 165:d1b4690b3f8b 367 \details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge 165:d1b4690b3f8b 368 \param [in] value Value to store
AnnaBridge 165:d1b4690b3f8b 369 \param [in] ptr Pointer to location
AnnaBridge 165:d1b4690b3f8b 370 \return 0 Function succeeded
AnnaBridge 165:d1b4690b3f8b 371 \return 1 Function failed
AnnaBridge 165:d1b4690b3f8b 372 */
AnnaBridge 165:d1b4690b3f8b 373 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge 165:d1b4690b3f8b 374 {
AnnaBridge 165:d1b4690b3f8b 375 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 376
AnnaBridge 165:d1b4690b3f8b 377 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge 165:d1b4690b3f8b 378 return(result);
AnnaBridge 165:d1b4690b3f8b 379 }
AnnaBridge 165:d1b4690b3f8b 380
AnnaBridge 165:d1b4690b3f8b 381
AnnaBridge 165:d1b4690b3f8b 382 /**
AnnaBridge 165:d1b4690b3f8b 383 \brief Remove the exclusive lock
AnnaBridge 165:d1b4690b3f8b 384 \details Removes the exclusive lock which is created by LDREX.
AnnaBridge 165:d1b4690b3f8b 385 */
AnnaBridge 165:d1b4690b3f8b 386 __STATIC_FORCEINLINE void __CLREX(void)
AnnaBridge 165:d1b4690b3f8b 387 {
AnnaBridge 165:d1b4690b3f8b 388 __ASM volatile ("clrex" ::: "memory");
AnnaBridge 165:d1b4690b3f8b 389 }
AnnaBridge 165:d1b4690b3f8b 390
AnnaBridge 165:d1b4690b3f8b 391 /**
AnnaBridge 165:d1b4690b3f8b 392 \brief Signed Saturate
AnnaBridge 165:d1b4690b3f8b 393 \details Saturates a signed value.
AnnaBridge 165:d1b4690b3f8b 394 \param [in] value Value to be saturated
AnnaBridge 165:d1b4690b3f8b 395 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 165:d1b4690b3f8b 396 \return Saturated value
AnnaBridge 165:d1b4690b3f8b 397 */
AnnaBridge 165:d1b4690b3f8b 398 #define __SSAT(ARG1,ARG2) \
AnnaBridge 165:d1b4690b3f8b 399 __extension__ \
AnnaBridge 165:d1b4690b3f8b 400 ({ \
AnnaBridge 165:d1b4690b3f8b 401 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 165:d1b4690b3f8b 402 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 165:d1b4690b3f8b 403 __RES; \
AnnaBridge 165:d1b4690b3f8b 404 })
AnnaBridge 165:d1b4690b3f8b 405
AnnaBridge 165:d1b4690b3f8b 406
AnnaBridge 165:d1b4690b3f8b 407 /**
AnnaBridge 165:d1b4690b3f8b 408 \brief Unsigned Saturate
AnnaBridge 165:d1b4690b3f8b 409 \details Saturates an unsigned value.
AnnaBridge 165:d1b4690b3f8b 410 \param [in] value Value to be saturated
AnnaBridge 165:d1b4690b3f8b 411 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 165:d1b4690b3f8b 412 \return Saturated value
AnnaBridge 165:d1b4690b3f8b 413 */
AnnaBridge 165:d1b4690b3f8b 414 #define __USAT(ARG1,ARG2) \
AnnaBridge 165:d1b4690b3f8b 415 __extension__ \
AnnaBridge 165:d1b4690b3f8b 416 ({ \
AnnaBridge 165:d1b4690b3f8b 417 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 165:d1b4690b3f8b 418 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 165:d1b4690b3f8b 419 __RES; \
AnnaBridge 165:d1b4690b3f8b 420 })
AnnaBridge 165:d1b4690b3f8b 421
AnnaBridge 165:d1b4690b3f8b 422 /* ########################### Core Function Access ########################### */
AnnaBridge 165:d1b4690b3f8b 423
AnnaBridge 165:d1b4690b3f8b 424 /**
AnnaBridge 165:d1b4690b3f8b 425 \brief Enable IRQ Interrupts
AnnaBridge 165:d1b4690b3f8b 426 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge 165:d1b4690b3f8b 427 Can only be executed in Privileged modes.
AnnaBridge 165:d1b4690b3f8b 428 */
AnnaBridge 165:d1b4690b3f8b 429 __STATIC_FORCEINLINE void __enable_irq(void)
AnnaBridge 165:d1b4690b3f8b 430 {
AnnaBridge 165:d1b4690b3f8b 431 __ASM volatile ("cpsie i" : : : "memory");
AnnaBridge 165:d1b4690b3f8b 432 }
AnnaBridge 165:d1b4690b3f8b 433
AnnaBridge 165:d1b4690b3f8b 434 /**
AnnaBridge 165:d1b4690b3f8b 435 \brief Disable IRQ Interrupts
AnnaBridge 165:d1b4690b3f8b 436 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 165:d1b4690b3f8b 437 Can only be executed in Privileged modes.
AnnaBridge 165:d1b4690b3f8b 438 */
AnnaBridge 165:d1b4690b3f8b 439 __STATIC_FORCEINLINE void __disable_irq(void)
AnnaBridge 165:d1b4690b3f8b 440 {
AnnaBridge 165:d1b4690b3f8b 441 __ASM volatile ("cpsid i" : : : "memory");
AnnaBridge 165:d1b4690b3f8b 442 }
AnnaBridge 165:d1b4690b3f8b 443
AnnaBridge 165:d1b4690b3f8b 444 /**
AnnaBridge 165:d1b4690b3f8b 445 \brief Get FPSCR
AnnaBridge 165:d1b4690b3f8b 446 \details Returns the current value of the Floating Point Status/Control register.
AnnaBridge 165:d1b4690b3f8b 447 \return Floating Point Status/Control register value
AnnaBridge 165:d1b4690b3f8b 448 */
AnnaBridge 165:d1b4690b3f8b 449 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
AnnaBridge 165:d1b4690b3f8b 450 {
AnnaBridge 165:d1b4690b3f8b 451 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 165:d1b4690b3f8b 452 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 165:d1b4690b3f8b 453 #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge 165:d1b4690b3f8b 454 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge 165:d1b4690b3f8b 455 return __builtin_arm_get_fpscr();
AnnaBridge 165:d1b4690b3f8b 456 #else
AnnaBridge 165:d1b4690b3f8b 457 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 458
AnnaBridge 165:d1b4690b3f8b 459 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge 165:d1b4690b3f8b 460 return(result);
AnnaBridge 165:d1b4690b3f8b 461 #endif
AnnaBridge 165:d1b4690b3f8b 462 #else
AnnaBridge 165:d1b4690b3f8b 463 return(0U);
AnnaBridge 165:d1b4690b3f8b 464 #endif
AnnaBridge 165:d1b4690b3f8b 465 }
AnnaBridge 165:d1b4690b3f8b 466
AnnaBridge 165:d1b4690b3f8b 467 /**
AnnaBridge 165:d1b4690b3f8b 468 \brief Set FPSCR
AnnaBridge 165:d1b4690b3f8b 469 \details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge 165:d1b4690b3f8b 470 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 165:d1b4690b3f8b 471 */
AnnaBridge 165:d1b4690b3f8b 472 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 165:d1b4690b3f8b 473 {
AnnaBridge 165:d1b4690b3f8b 474 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 165:d1b4690b3f8b 475 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 165:d1b4690b3f8b 476 #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge 165:d1b4690b3f8b 477 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge 165:d1b4690b3f8b 478 __builtin_arm_set_fpscr(fpscr);
AnnaBridge 165:d1b4690b3f8b 479 #else
AnnaBridge 165:d1b4690b3f8b 480 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
AnnaBridge 165:d1b4690b3f8b 481 #endif
AnnaBridge 165:d1b4690b3f8b 482 #else
AnnaBridge 165:d1b4690b3f8b 483 (void)fpscr;
AnnaBridge 165:d1b4690b3f8b 484 #endif
AnnaBridge 165:d1b4690b3f8b 485 }
AnnaBridge 165:d1b4690b3f8b 486
AnnaBridge 165:d1b4690b3f8b 487 /** \brief Get CPSR Register
AnnaBridge 165:d1b4690b3f8b 488 \return CPSR Register value
AnnaBridge 165:d1b4690b3f8b 489 */
AnnaBridge 165:d1b4690b3f8b 490 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
AnnaBridge 165:d1b4690b3f8b 491 {
AnnaBridge 165:d1b4690b3f8b 492 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 493 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
AnnaBridge 165:d1b4690b3f8b 494 return(result);
AnnaBridge 165:d1b4690b3f8b 495 }
AnnaBridge 165:d1b4690b3f8b 496
AnnaBridge 165:d1b4690b3f8b 497 /** \brief Set CPSR Register
AnnaBridge 165:d1b4690b3f8b 498 \param [in] cpsr CPSR value to set
AnnaBridge 165:d1b4690b3f8b 499 */
AnnaBridge 165:d1b4690b3f8b 500 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
AnnaBridge 165:d1b4690b3f8b 501 {
AnnaBridge 165:d1b4690b3f8b 502 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
AnnaBridge 165:d1b4690b3f8b 503 }
AnnaBridge 165:d1b4690b3f8b 504
AnnaBridge 165:d1b4690b3f8b 505 /** \brief Get Mode
AnnaBridge 165:d1b4690b3f8b 506 \return Processor Mode
AnnaBridge 165:d1b4690b3f8b 507 */
AnnaBridge 165:d1b4690b3f8b 508 __STATIC_FORCEINLINE uint32_t __get_mode(void)
AnnaBridge 165:d1b4690b3f8b 509 {
AnnaBridge 165:d1b4690b3f8b 510 return (__get_CPSR() & 0x1FU);
AnnaBridge 165:d1b4690b3f8b 511 }
AnnaBridge 165:d1b4690b3f8b 512
AnnaBridge 165:d1b4690b3f8b 513 /** \brief Set Mode
AnnaBridge 165:d1b4690b3f8b 514 \param [in] mode Mode value to set
AnnaBridge 165:d1b4690b3f8b 515 */
AnnaBridge 165:d1b4690b3f8b 516 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
AnnaBridge 165:d1b4690b3f8b 517 {
AnnaBridge 165:d1b4690b3f8b 518 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
AnnaBridge 165:d1b4690b3f8b 519 }
AnnaBridge 165:d1b4690b3f8b 520
AnnaBridge 165:d1b4690b3f8b 521 /** \brief Get Stack Pointer
AnnaBridge 165:d1b4690b3f8b 522 \return Stack Pointer value
AnnaBridge 165:d1b4690b3f8b 523 */
AnnaBridge 165:d1b4690b3f8b 524 __STATIC_FORCEINLINE uint32_t __get_SP(void)
AnnaBridge 165:d1b4690b3f8b 525 {
AnnaBridge 165:d1b4690b3f8b 526 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 527 __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
AnnaBridge 165:d1b4690b3f8b 528 return result;
AnnaBridge 165:d1b4690b3f8b 529 }
AnnaBridge 165:d1b4690b3f8b 530
AnnaBridge 165:d1b4690b3f8b 531 /** \brief Set Stack Pointer
AnnaBridge 165:d1b4690b3f8b 532 \param [in] stack Stack Pointer value to set
AnnaBridge 165:d1b4690b3f8b 533 */
AnnaBridge 165:d1b4690b3f8b 534 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
AnnaBridge 165:d1b4690b3f8b 535 {
AnnaBridge 165:d1b4690b3f8b 536 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
AnnaBridge 165:d1b4690b3f8b 537 }
AnnaBridge 165:d1b4690b3f8b 538
AnnaBridge 165:d1b4690b3f8b 539 /** \brief Get USR/SYS Stack Pointer
AnnaBridge 165:d1b4690b3f8b 540 \return USR/SYS Stack Pointer value
AnnaBridge 165:d1b4690b3f8b 541 */
AnnaBridge 165:d1b4690b3f8b 542 __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
AnnaBridge 165:d1b4690b3f8b 543 {
AnnaBridge 165:d1b4690b3f8b 544 uint32_t cpsr = __get_CPSR();
AnnaBridge 165:d1b4690b3f8b 545 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 546 __ASM volatile(
AnnaBridge 165:d1b4690b3f8b 547 "CPS #0x1F \n"
AnnaBridge 165:d1b4690b3f8b 548 "MOV %0, sp " : "=r"(result) : : "memory"
AnnaBridge 165:d1b4690b3f8b 549 );
AnnaBridge 165:d1b4690b3f8b 550 __set_CPSR(cpsr);
AnnaBridge 165:d1b4690b3f8b 551 __ISB();
AnnaBridge 165:d1b4690b3f8b 552 return result;
AnnaBridge 165:d1b4690b3f8b 553 }
AnnaBridge 165:d1b4690b3f8b 554
AnnaBridge 165:d1b4690b3f8b 555 /** \brief Set USR/SYS Stack Pointer
AnnaBridge 165:d1b4690b3f8b 556 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 165:d1b4690b3f8b 557 */
AnnaBridge 165:d1b4690b3f8b 558 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
AnnaBridge 165:d1b4690b3f8b 559 {
AnnaBridge 165:d1b4690b3f8b 560 uint32_t cpsr = __get_CPSR();
AnnaBridge 165:d1b4690b3f8b 561 __ASM volatile(
AnnaBridge 165:d1b4690b3f8b 562 "CPS #0x1F \n"
AnnaBridge 165:d1b4690b3f8b 563 "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
AnnaBridge 165:d1b4690b3f8b 564 );
AnnaBridge 165:d1b4690b3f8b 565 __set_CPSR(cpsr);
AnnaBridge 165:d1b4690b3f8b 566 __ISB();
AnnaBridge 165:d1b4690b3f8b 567 }
AnnaBridge 165:d1b4690b3f8b 568
AnnaBridge 165:d1b4690b3f8b 569 /** \brief Get FPEXC
AnnaBridge 165:d1b4690b3f8b 570 \return Floating Point Exception Control register value
AnnaBridge 165:d1b4690b3f8b 571 */
AnnaBridge 165:d1b4690b3f8b 572 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
AnnaBridge 165:d1b4690b3f8b 573 {
AnnaBridge 165:d1b4690b3f8b 574 #if (__FPU_PRESENT == 1)
AnnaBridge 165:d1b4690b3f8b 575 uint32_t result;
AnnaBridge 165:d1b4690b3f8b 576 __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
AnnaBridge 165:d1b4690b3f8b 577 return(result);
AnnaBridge 165:d1b4690b3f8b 578 #else
AnnaBridge 165:d1b4690b3f8b 579 return(0);
AnnaBridge 165:d1b4690b3f8b 580 #endif
AnnaBridge 165:d1b4690b3f8b 581 }
AnnaBridge 165:d1b4690b3f8b 582
AnnaBridge 165:d1b4690b3f8b 583 /** \brief Set FPEXC
AnnaBridge 165:d1b4690b3f8b 584 \param [in] fpexc Floating Point Exception Control value to set
AnnaBridge 165:d1b4690b3f8b 585 */
AnnaBridge 165:d1b4690b3f8b 586 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 165:d1b4690b3f8b 587 {
AnnaBridge 165:d1b4690b3f8b 588 #if (__FPU_PRESENT == 1)
AnnaBridge 165:d1b4690b3f8b 589 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
AnnaBridge 165:d1b4690b3f8b 590 #endif
AnnaBridge 165:d1b4690b3f8b 591 }
AnnaBridge 165:d1b4690b3f8b 592
AnnaBridge 165:d1b4690b3f8b 593 /*
AnnaBridge 165:d1b4690b3f8b 594 * Include common core functions to access Coprocessor 15 registers
AnnaBridge 165:d1b4690b3f8b 595 */
AnnaBridge 165:d1b4690b3f8b 596
AnnaBridge 165:d1b4690b3f8b 597 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
AnnaBridge 165:d1b4690b3f8b 598 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
AnnaBridge 165:d1b4690b3f8b 599 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
AnnaBridge 165:d1b4690b3f8b 600 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
AnnaBridge 165:d1b4690b3f8b 601
AnnaBridge 165:d1b4690b3f8b 602 #include "cmsis_cp15.h"
AnnaBridge 165:d1b4690b3f8b 603
AnnaBridge 165:d1b4690b3f8b 604 /** \brief Enable Floating Point Unit
AnnaBridge 165:d1b4690b3f8b 605
AnnaBridge 165:d1b4690b3f8b 606 Critical section, called from undef handler, so systick is disabled
AnnaBridge 165:d1b4690b3f8b 607 */
AnnaBridge 165:d1b4690b3f8b 608 __STATIC_INLINE void __FPU_Enable(void)
AnnaBridge 165:d1b4690b3f8b 609 {
AnnaBridge 165:d1b4690b3f8b 610 __ASM volatile(
AnnaBridge 165:d1b4690b3f8b 611 //Permit access to VFP/NEON, registers by modifying CPACR
AnnaBridge 165:d1b4690b3f8b 612 " MRC p15,0,R1,c1,c0,2 \n"
AnnaBridge 165:d1b4690b3f8b 613 " ORR R1,R1,#0x00F00000 \n"
AnnaBridge 165:d1b4690b3f8b 614 " MCR p15,0,R1,c1,c0,2 \n"
AnnaBridge 165:d1b4690b3f8b 615
AnnaBridge 165:d1b4690b3f8b 616 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
AnnaBridge 165:d1b4690b3f8b 617 " ISB \n"
AnnaBridge 165:d1b4690b3f8b 618
AnnaBridge 165:d1b4690b3f8b 619 //Enable VFP/NEON
AnnaBridge 165:d1b4690b3f8b 620 " VMRS R1,FPEXC \n"
AnnaBridge 165:d1b4690b3f8b 621 " ORR R1,R1,#0x40000000 \n"
AnnaBridge 165:d1b4690b3f8b 622 " VMSR FPEXC,R1 \n"
AnnaBridge 165:d1b4690b3f8b 623
AnnaBridge 165:d1b4690b3f8b 624 //Initialise VFP/NEON registers to 0
AnnaBridge 165:d1b4690b3f8b 625 " MOV R2,#0 \n"
AnnaBridge 165:d1b4690b3f8b 626
AnnaBridge 165:d1b4690b3f8b 627 //Initialise D16 registers to 0
AnnaBridge 165:d1b4690b3f8b 628 " VMOV D0, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 629 " VMOV D1, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 630 " VMOV D2, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 631 " VMOV D3, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 632 " VMOV D4, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 633 " VMOV D5, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 634 " VMOV D6, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 635 " VMOV D7, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 636 " VMOV D8, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 637 " VMOV D9, R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 638 " VMOV D10,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 639 " VMOV D11,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 640 " VMOV D12,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 641 " VMOV D13,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 642 " VMOV D14,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 643 " VMOV D15,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 644
AnnaBridge 165:d1b4690b3f8b 645 #if __ARM_NEON == 1
AnnaBridge 165:d1b4690b3f8b 646 //Initialise D32 registers to 0
AnnaBridge 165:d1b4690b3f8b 647 " VMOV D16,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 648 " VMOV D17,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 649 " VMOV D18,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 650 " VMOV D19,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 651 " VMOV D20,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 652 " VMOV D21,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 653 " VMOV D22,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 654 " VMOV D23,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 655 " VMOV D24,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 656 " VMOV D25,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 657 " VMOV D26,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 658 " VMOV D27,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 659 " VMOV D28,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 660 " VMOV D29,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 661 " VMOV D30,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 662 " VMOV D31,R2,R2 \n"
AnnaBridge 165:d1b4690b3f8b 663 #endif
AnnaBridge 165:d1b4690b3f8b 664
AnnaBridge 165:d1b4690b3f8b 665 //Initialise FPSCR to a known state
AnnaBridge 165:d1b4690b3f8b 666 " VMRS R2,FPSCR \n"
AnnaBridge 165:d1b4690b3f8b 667 " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AnnaBridge 165:d1b4690b3f8b 668 " AND R2,R2,R3 \n"
AnnaBridge 165:d1b4690b3f8b 669 " VMSR FPSCR,R2 "
AnnaBridge 165:d1b4690b3f8b 670 );
AnnaBridge 165:d1b4690b3f8b 671 }
AnnaBridge 165:d1b4690b3f8b 672
AnnaBridge 165:d1b4690b3f8b 673 #pragma GCC diagnostic pop
AnnaBridge 165:d1b4690b3f8b 674
AnnaBridge 165:d1b4690b3f8b 675 #endif /* __CMSIS_GCC_H */