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TARGET_MIMXRT1050_EVK/mpu_armv8.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
161:aa5281ff4a02
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /******************************************************************************
AnnaBridge 161:aa5281ff4a02 2 * @file mpu_armv8.h
AnnaBridge 161:aa5281ff4a02 3 * @brief CMSIS MPU API for ARMv8 MPU
AnnaBridge 161:aa5281ff4a02 4 * @version V5.0.3
AnnaBridge 161:aa5281ff4a02 5 * @date 09. August 2017
AnnaBridge 161:aa5281ff4a02 6 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 7 /*
AnnaBridge 161:aa5281ff4a02 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
AnnaBridge 161:aa5281ff4a02 9 *
AnnaBridge 161:aa5281ff4a02 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 161:aa5281ff4a02 11 *
AnnaBridge 161:aa5281ff4a02 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 161:aa5281ff4a02 13 * not use this file except in compliance with the License.
AnnaBridge 161:aa5281ff4a02 14 * You may obtain a copy of the License at
AnnaBridge 161:aa5281ff4a02 15 *
AnnaBridge 161:aa5281ff4a02 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 161:aa5281ff4a02 17 *
AnnaBridge 161:aa5281ff4a02 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 161:aa5281ff4a02 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 161:aa5281ff4a02 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 161:aa5281ff4a02 21 * See the License for the specific language governing permissions and
AnnaBridge 161:aa5281ff4a02 22 * limitations under the License.
AnnaBridge 161:aa5281ff4a02 23 */
AnnaBridge 161:aa5281ff4a02 24
AnnaBridge 161:aa5281ff4a02 25 #ifndef ARM_MPU_ARMV8_H
AnnaBridge 161:aa5281ff4a02 26 #define ARM_MPU_ARMV8_H
AnnaBridge 161:aa5281ff4a02 27
AnnaBridge 161:aa5281ff4a02 28 /** \brief Attribute for device memory (outer only) */
AnnaBridge 161:aa5281ff4a02 29 #define ARM_MPU_ATTR_DEVICE ( 0U )
AnnaBridge 161:aa5281ff4a02 30
AnnaBridge 161:aa5281ff4a02 31 /** \brief Attribute for non-cacheable, normal memory */
AnnaBridge 161:aa5281ff4a02 32 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
AnnaBridge 161:aa5281ff4a02 33
AnnaBridge 161:aa5281ff4a02 34 /** \brief Attribute for normal memory (outer and inner)
AnnaBridge 161:aa5281ff4a02 35 * \param NT Non-Transient: Set to 1 for non-transient data.
AnnaBridge 161:aa5281ff4a02 36 * \param WB Write-Back: Set to 1 to use write-back update policy.
AnnaBridge 161:aa5281ff4a02 37 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
AnnaBridge 161:aa5281ff4a02 38 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
AnnaBridge 161:aa5281ff4a02 39 */
AnnaBridge 161:aa5281ff4a02 40 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
AnnaBridge 161:aa5281ff4a02 41 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
AnnaBridge 161:aa5281ff4a02 42
AnnaBridge 161:aa5281ff4a02 43 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
AnnaBridge 161:aa5281ff4a02 44 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
AnnaBridge 161:aa5281ff4a02 45
AnnaBridge 161:aa5281ff4a02 46 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
AnnaBridge 161:aa5281ff4a02 47 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
AnnaBridge 161:aa5281ff4a02 48
AnnaBridge 161:aa5281ff4a02 49 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 161:aa5281ff4a02 50 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
AnnaBridge 161:aa5281ff4a02 51
AnnaBridge 161:aa5281ff4a02 52 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 161:aa5281ff4a02 53 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
AnnaBridge 161:aa5281ff4a02 54
AnnaBridge 161:aa5281ff4a02 55 /** \brief Memory Attribute
AnnaBridge 161:aa5281ff4a02 56 * \param O Outer memory attributes
AnnaBridge 161:aa5281ff4a02 57 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
AnnaBridge 161:aa5281ff4a02 58 */
AnnaBridge 161:aa5281ff4a02 59 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
AnnaBridge 161:aa5281ff4a02 60
AnnaBridge 161:aa5281ff4a02 61 /** \brief Normal memory non-shareable */
AnnaBridge 161:aa5281ff4a02 62 #define ARM_MPU_SH_NON (0U)
AnnaBridge 161:aa5281ff4a02 63
AnnaBridge 161:aa5281ff4a02 64 /** \brief Normal memory outer shareable */
AnnaBridge 161:aa5281ff4a02 65 #define ARM_MPU_SH_OUTER (2U)
AnnaBridge 161:aa5281ff4a02 66
AnnaBridge 161:aa5281ff4a02 67 /** \brief Normal memory inner shareable */
AnnaBridge 161:aa5281ff4a02 68 #define ARM_MPU_SH_INNER (3U)
AnnaBridge 161:aa5281ff4a02 69
AnnaBridge 161:aa5281ff4a02 70 /** \brief Memory access permissions
AnnaBridge 161:aa5281ff4a02 71 * \param RO Read-Only: Set to 1 for read-only memory.
AnnaBridge 161:aa5281ff4a02 72 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
AnnaBridge 161:aa5281ff4a02 73 */
AnnaBridge 161:aa5281ff4a02 74 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
AnnaBridge 161:aa5281ff4a02 75
AnnaBridge 161:aa5281ff4a02 76 /** \brief Region Base Address Register value
AnnaBridge 161:aa5281ff4a02 77 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
AnnaBridge 161:aa5281ff4a02 78 * \param SH Defines the Shareability domain for this memory region.
AnnaBridge 161:aa5281ff4a02 79 * \param RO Read-Only: Set to 1 for a read-only memory region.
AnnaBridge 161:aa5281ff4a02 80 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
AnnaBridge 161:aa5281ff4a02 81 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
AnnaBridge 161:aa5281ff4a02 82 */
AnnaBridge 161:aa5281ff4a02 83 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
AnnaBridge 161:aa5281ff4a02 84 ((BASE & MPU_RBAR_BASE_Pos) | \
AnnaBridge 161:aa5281ff4a02 85 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
AnnaBridge 161:aa5281ff4a02 86 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
AnnaBridge 161:aa5281ff4a02 87 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
AnnaBridge 161:aa5281ff4a02 88
AnnaBridge 161:aa5281ff4a02 89 /** \brief Region Limit Address Register value
AnnaBridge 161:aa5281ff4a02 90 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
AnnaBridge 161:aa5281ff4a02 91 * \param IDX The attribute index to be associated with this memory region.
AnnaBridge 161:aa5281ff4a02 92 */
AnnaBridge 161:aa5281ff4a02 93 #define ARM_MPU_RLAR(LIMIT, IDX) \
AnnaBridge 161:aa5281ff4a02 94 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
AnnaBridge 161:aa5281ff4a02 95 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
AnnaBridge 161:aa5281ff4a02 96 (MPU_RLAR_EN_Msk))
AnnaBridge 161:aa5281ff4a02 97
AnnaBridge 161:aa5281ff4a02 98 /**
AnnaBridge 161:aa5281ff4a02 99 * Struct for a single MPU Region
AnnaBridge 161:aa5281ff4a02 100 */
AnnaBridge 161:aa5281ff4a02 101 typedef struct _ARM_MPU_Region_t {
AnnaBridge 161:aa5281ff4a02 102 uint32_t RBAR; /*!< Region Base Address Register value */
AnnaBridge 161:aa5281ff4a02 103 uint32_t RLAR; /*!< Region Limit Address Register value */
AnnaBridge 161:aa5281ff4a02 104 } ARM_MPU_Region_t;
AnnaBridge 161:aa5281ff4a02 105
AnnaBridge 161:aa5281ff4a02 106 /** Enable the MPU.
AnnaBridge 161:aa5281ff4a02 107 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 161:aa5281ff4a02 108 */
AnnaBridge 161:aa5281ff4a02 109 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 161:aa5281ff4a02 110 {
AnnaBridge 161:aa5281ff4a02 111 __DSB();
AnnaBridge 161:aa5281ff4a02 112 __ISB();
AnnaBridge 161:aa5281ff4a02 113 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 161:aa5281ff4a02 114 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 161:aa5281ff4a02 115 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 161:aa5281ff4a02 116 #endif
AnnaBridge 161:aa5281ff4a02 117 }
AnnaBridge 161:aa5281ff4a02 118
AnnaBridge 161:aa5281ff4a02 119 /** Disable the MPU.
AnnaBridge 161:aa5281ff4a02 120 */
AnnaBridge 161:aa5281ff4a02 121 __STATIC_INLINE void ARM_MPU_Disable(void)
AnnaBridge 161:aa5281ff4a02 122 {
AnnaBridge 161:aa5281ff4a02 123 __DSB();
AnnaBridge 161:aa5281ff4a02 124 __ISB();
AnnaBridge 161:aa5281ff4a02 125 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 161:aa5281ff4a02 126 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 161:aa5281ff4a02 127 #endif
AnnaBridge 161:aa5281ff4a02 128 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 161:aa5281ff4a02 129 }
AnnaBridge 161:aa5281ff4a02 130
AnnaBridge 161:aa5281ff4a02 131 #ifdef MPU_NS
AnnaBridge 161:aa5281ff4a02 132 /** Enable the Non-secure MPU.
AnnaBridge 161:aa5281ff4a02 133 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 161:aa5281ff4a02 134 */
AnnaBridge 161:aa5281ff4a02 135 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
AnnaBridge 161:aa5281ff4a02 136 {
AnnaBridge 161:aa5281ff4a02 137 __DSB();
AnnaBridge 161:aa5281ff4a02 138 __ISB();
AnnaBridge 161:aa5281ff4a02 139 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 161:aa5281ff4a02 140 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 161:aa5281ff4a02 141 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 161:aa5281ff4a02 142 #endif
AnnaBridge 161:aa5281ff4a02 143 }
AnnaBridge 161:aa5281ff4a02 144
AnnaBridge 161:aa5281ff4a02 145 /** Disable the Non-secure MPU.
AnnaBridge 161:aa5281ff4a02 146 */
AnnaBridge 161:aa5281ff4a02 147 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
AnnaBridge 161:aa5281ff4a02 148 {
AnnaBridge 161:aa5281ff4a02 149 __DSB();
AnnaBridge 161:aa5281ff4a02 150 __ISB();
AnnaBridge 161:aa5281ff4a02 151 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 161:aa5281ff4a02 152 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 161:aa5281ff4a02 153 #endif
AnnaBridge 161:aa5281ff4a02 154 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 161:aa5281ff4a02 155 }
AnnaBridge 161:aa5281ff4a02 156 #endif
AnnaBridge 161:aa5281ff4a02 157
AnnaBridge 161:aa5281ff4a02 158 /** Set the memory attribute encoding to the given MPU.
AnnaBridge 161:aa5281ff4a02 159 * \param mpu Pointer to the MPU to be configured.
AnnaBridge 161:aa5281ff4a02 160 * \param idx The attribute index to be set [0-7]
AnnaBridge 161:aa5281ff4a02 161 * \param attr The attribute value to be set.
AnnaBridge 161:aa5281ff4a02 162 */
AnnaBridge 161:aa5281ff4a02 163 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
AnnaBridge 161:aa5281ff4a02 164 {
AnnaBridge 161:aa5281ff4a02 165 const uint8_t reg = idx / 4U;
AnnaBridge 161:aa5281ff4a02 166 const uint32_t pos = ((idx % 4U) * 8U);
AnnaBridge 161:aa5281ff4a02 167 const uint32_t mask = 0xFFU << pos;
AnnaBridge 161:aa5281ff4a02 168
AnnaBridge 161:aa5281ff4a02 169 if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) {
AnnaBridge 161:aa5281ff4a02 170 return; // invalid index
AnnaBridge 161:aa5281ff4a02 171 }
AnnaBridge 161:aa5281ff4a02 172
AnnaBridge 161:aa5281ff4a02 173 MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask));
AnnaBridge 161:aa5281ff4a02 174 }
AnnaBridge 161:aa5281ff4a02 175
AnnaBridge 161:aa5281ff4a02 176 /** Set the memory attribute encoding.
AnnaBridge 161:aa5281ff4a02 177 * \param idx The attribute index to be set [0-7]
AnnaBridge 161:aa5281ff4a02 178 * \param attr The attribute value to be set.
AnnaBridge 161:aa5281ff4a02 179 */
AnnaBridge 161:aa5281ff4a02 180 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
AnnaBridge 161:aa5281ff4a02 181 {
AnnaBridge 161:aa5281ff4a02 182 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
AnnaBridge 161:aa5281ff4a02 183 }
AnnaBridge 161:aa5281ff4a02 184
AnnaBridge 161:aa5281ff4a02 185 #ifdef MPU_NS
AnnaBridge 161:aa5281ff4a02 186 /** Set the memory attribute encoding to the Non-secure MPU.
AnnaBridge 161:aa5281ff4a02 187 * \param idx The attribute index to be set [0-7]
AnnaBridge 161:aa5281ff4a02 188 * \param attr The attribute value to be set.
AnnaBridge 161:aa5281ff4a02 189 */
AnnaBridge 161:aa5281ff4a02 190 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
AnnaBridge 161:aa5281ff4a02 191 {
AnnaBridge 161:aa5281ff4a02 192 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
AnnaBridge 161:aa5281ff4a02 193 }
AnnaBridge 161:aa5281ff4a02 194 #endif
AnnaBridge 161:aa5281ff4a02 195
AnnaBridge 161:aa5281ff4a02 196 /** Clear and disable the given MPU region of the given MPU.
AnnaBridge 161:aa5281ff4a02 197 * \param mpu Pointer to MPU to be used.
AnnaBridge 161:aa5281ff4a02 198 * \param rnr Region number to be cleared.
AnnaBridge 161:aa5281ff4a02 199 */
AnnaBridge 161:aa5281ff4a02 200 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
AnnaBridge 161:aa5281ff4a02 201 {
AnnaBridge 161:aa5281ff4a02 202 MPU->RNR = rnr;
AnnaBridge 161:aa5281ff4a02 203 MPU->RLAR = 0U;
AnnaBridge 161:aa5281ff4a02 204 }
AnnaBridge 161:aa5281ff4a02 205
AnnaBridge 161:aa5281ff4a02 206 /** Clear and disable the given MPU region.
AnnaBridge 161:aa5281ff4a02 207 * \param rnr Region number to be cleared.
AnnaBridge 161:aa5281ff4a02 208 */
AnnaBridge 161:aa5281ff4a02 209 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
AnnaBridge 161:aa5281ff4a02 210 {
AnnaBridge 161:aa5281ff4a02 211 ARM_MPU_ClrRegionEx(MPU, rnr);
AnnaBridge 161:aa5281ff4a02 212 }
AnnaBridge 161:aa5281ff4a02 213
AnnaBridge 161:aa5281ff4a02 214 #ifdef MPU_NS
AnnaBridge 161:aa5281ff4a02 215 /** Clear and disable the given Non-secure MPU region.
AnnaBridge 161:aa5281ff4a02 216 * \param rnr Region number to be cleared.
AnnaBridge 161:aa5281ff4a02 217 */
AnnaBridge 161:aa5281ff4a02 218 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
AnnaBridge 161:aa5281ff4a02 219 {
AnnaBridge 161:aa5281ff4a02 220 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
AnnaBridge 161:aa5281ff4a02 221 }
AnnaBridge 161:aa5281ff4a02 222 #endif
AnnaBridge 161:aa5281ff4a02 223
AnnaBridge 161:aa5281ff4a02 224 /** Configure the given MPU region of the given MPU.
AnnaBridge 161:aa5281ff4a02 225 * \param mpu Pointer to MPU to be used.
AnnaBridge 161:aa5281ff4a02 226 * \param rnr Region number to be configured.
AnnaBridge 161:aa5281ff4a02 227 * \param rbar Value for RBAR register.
AnnaBridge 161:aa5281ff4a02 228 * \param rlar Value for RLAR register.
AnnaBridge 161:aa5281ff4a02 229 */
AnnaBridge 161:aa5281ff4a02 230 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 161:aa5281ff4a02 231 {
AnnaBridge 161:aa5281ff4a02 232 MPU->RNR = rnr;
AnnaBridge 161:aa5281ff4a02 233 MPU->RBAR = rbar;
AnnaBridge 161:aa5281ff4a02 234 MPU->RLAR = rlar;
AnnaBridge 161:aa5281ff4a02 235 }
AnnaBridge 161:aa5281ff4a02 236
AnnaBridge 161:aa5281ff4a02 237 /** Configure the given MPU region.
AnnaBridge 161:aa5281ff4a02 238 * \param rnr Region number to be configured.
AnnaBridge 161:aa5281ff4a02 239 * \param rbar Value for RBAR register.
AnnaBridge 161:aa5281ff4a02 240 * \param rlar Value for RLAR register.
AnnaBridge 161:aa5281ff4a02 241 */
AnnaBridge 161:aa5281ff4a02 242 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 161:aa5281ff4a02 243 {
AnnaBridge 161:aa5281ff4a02 244 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
AnnaBridge 161:aa5281ff4a02 245 }
AnnaBridge 161:aa5281ff4a02 246
AnnaBridge 161:aa5281ff4a02 247 #ifdef MPU_NS
AnnaBridge 161:aa5281ff4a02 248 /** Configure the given Non-secure MPU region.
AnnaBridge 161:aa5281ff4a02 249 * \param rnr Region number to be configured.
AnnaBridge 161:aa5281ff4a02 250 * \param rbar Value for RBAR register.
AnnaBridge 161:aa5281ff4a02 251 * \param rlar Value for RLAR register.
AnnaBridge 161:aa5281ff4a02 252 */
AnnaBridge 161:aa5281ff4a02 253 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 161:aa5281ff4a02 254 {
AnnaBridge 161:aa5281ff4a02 255 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
AnnaBridge 161:aa5281ff4a02 256 }
AnnaBridge 161:aa5281ff4a02 257 #endif
AnnaBridge 161:aa5281ff4a02 258
AnnaBridge 161:aa5281ff4a02 259 /** Memcopy with strictly ordered memory access, e.g. for register targets.
AnnaBridge 161:aa5281ff4a02 260 * \param dst Destination data is copied to.
AnnaBridge 161:aa5281ff4a02 261 * \param src Source data is copied from.
AnnaBridge 161:aa5281ff4a02 262 * \param len Amount of data words to be copied.
AnnaBridge 161:aa5281ff4a02 263 */
AnnaBridge 161:aa5281ff4a02 264 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
AnnaBridge 161:aa5281ff4a02 265 {
AnnaBridge 161:aa5281ff4a02 266 uint32_t i;
AnnaBridge 161:aa5281ff4a02 267 for (i = 0U; i < len; ++i)
AnnaBridge 161:aa5281ff4a02 268 {
AnnaBridge 161:aa5281ff4a02 269 dst[i] = src[i];
AnnaBridge 161:aa5281ff4a02 270 }
AnnaBridge 161:aa5281ff4a02 271 }
AnnaBridge 161:aa5281ff4a02 272
AnnaBridge 161:aa5281ff4a02 273 /** Load the given number of MPU regions from a table to the given MPU.
AnnaBridge 161:aa5281ff4a02 274 * \param mpu Pointer to the MPU registers to be used.
AnnaBridge 161:aa5281ff4a02 275 * \param rnr First region number to be configured.
AnnaBridge 161:aa5281ff4a02 276 * \param table Pointer to the MPU configuration table.
AnnaBridge 161:aa5281ff4a02 277 * \param cnt Amount of regions to be configured.
AnnaBridge 161:aa5281ff4a02 278 */
AnnaBridge 161:aa5281ff4a02 279 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 161:aa5281ff4a02 280 {
AnnaBridge 161:aa5281ff4a02 281 static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
AnnaBridge 161:aa5281ff4a02 282 if (cnt == 1U) {
AnnaBridge 161:aa5281ff4a02 283 mpu->RNR = rnr;
AnnaBridge 161:aa5281ff4a02 284 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
AnnaBridge 161:aa5281ff4a02 285 } else {
AnnaBridge 161:aa5281ff4a02 286 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
AnnaBridge 161:aa5281ff4a02 287 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
AnnaBridge 161:aa5281ff4a02 288
AnnaBridge 161:aa5281ff4a02 289 mpu->RNR = rnrBase;
AnnaBridge 161:aa5281ff4a02 290 if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
AnnaBridge 161:aa5281ff4a02 291 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
AnnaBridge 161:aa5281ff4a02 292 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
AnnaBridge 161:aa5281ff4a02 293 ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c);
AnnaBridge 161:aa5281ff4a02 294 } else {
AnnaBridge 161:aa5281ff4a02 295 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
AnnaBridge 161:aa5281ff4a02 296 }
AnnaBridge 161:aa5281ff4a02 297 }
AnnaBridge 161:aa5281ff4a02 298 }
AnnaBridge 161:aa5281ff4a02 299
AnnaBridge 161:aa5281ff4a02 300 /** Load the given number of MPU regions from a table.
AnnaBridge 161:aa5281ff4a02 301 * \param rnr First region number to be configured.
AnnaBridge 161:aa5281ff4a02 302 * \param table Pointer to the MPU configuration table.
AnnaBridge 161:aa5281ff4a02 303 * \param cnt Amount of regions to be configured.
AnnaBridge 161:aa5281ff4a02 304 */
AnnaBridge 161:aa5281ff4a02 305 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 161:aa5281ff4a02 306 {
AnnaBridge 161:aa5281ff4a02 307 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
AnnaBridge 161:aa5281ff4a02 308 }
AnnaBridge 161:aa5281ff4a02 309
AnnaBridge 161:aa5281ff4a02 310 #ifdef MPU_NS
AnnaBridge 161:aa5281ff4a02 311 /** Load the given number of MPU regions from a table to the Non-secure MPU.
AnnaBridge 161:aa5281ff4a02 312 * \param rnr First region number to be configured.
AnnaBridge 161:aa5281ff4a02 313 * \param table Pointer to the MPU configuration table.
AnnaBridge 161:aa5281ff4a02 314 * \param cnt Amount of regions to be configured.
AnnaBridge 161:aa5281ff4a02 315 */
AnnaBridge 161:aa5281ff4a02 316 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 161:aa5281ff4a02 317 {
AnnaBridge 161:aa5281ff4a02 318 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
AnnaBridge 161:aa5281ff4a02 319 }
AnnaBridge 161:aa5281ff4a02 320 #endif
AnnaBridge 161:aa5281ff4a02 321
AnnaBridge 161:aa5281ff4a02 322 #endif
AnnaBridge 161:aa5281ff4a02 323