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TARGET_GR_LYCHEE/irq_ctrl.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
161:aa5281ff4a02
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /**************************************************************************//**
AnnaBridge 161:aa5281ff4a02 2 * @file irq_ctrl.h
AnnaBridge 161:aa5281ff4a02 3 * @brief Interrupt Controller API header file
AnnaBridge 161:aa5281ff4a02 4 * @version V1.0.0
AnnaBridge 161:aa5281ff4a02 5 * @date 23. June 2017
AnnaBridge 161:aa5281ff4a02 6 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 7 /*
AnnaBridge 161:aa5281ff4a02 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
AnnaBridge 161:aa5281ff4a02 9 *
AnnaBridge 161:aa5281ff4a02 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 161:aa5281ff4a02 11 *
AnnaBridge 161:aa5281ff4a02 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 161:aa5281ff4a02 13 * not use this file except in compliance with the License.
AnnaBridge 161:aa5281ff4a02 14 * You may obtain a copy of the License at
AnnaBridge 161:aa5281ff4a02 15 *
AnnaBridge 161:aa5281ff4a02 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 161:aa5281ff4a02 17 *
AnnaBridge 161:aa5281ff4a02 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 161:aa5281ff4a02 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 161:aa5281ff4a02 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 161:aa5281ff4a02 21 * See the License for the specific language governing permissions and
AnnaBridge 161:aa5281ff4a02 22 * limitations under the License.
AnnaBridge 161:aa5281ff4a02 23 */
AnnaBridge 161:aa5281ff4a02 24
AnnaBridge 161:aa5281ff4a02 25 #ifndef IRQ_CTRL_H_
AnnaBridge 161:aa5281ff4a02 26 #define IRQ_CTRL_H_
AnnaBridge 161:aa5281ff4a02 27
AnnaBridge 161:aa5281ff4a02 28 #include <stdint.h>
AnnaBridge 161:aa5281ff4a02 29
AnnaBridge 161:aa5281ff4a02 30 #ifndef IRQHANDLER_T
AnnaBridge 161:aa5281ff4a02 31 #define IRQHANDLER_T
AnnaBridge 161:aa5281ff4a02 32 /// Interrupt handler data type
AnnaBridge 161:aa5281ff4a02 33 typedef void (*IRQHandler_t) (void);
AnnaBridge 161:aa5281ff4a02 34 #endif
AnnaBridge 161:aa5281ff4a02 35
AnnaBridge 161:aa5281ff4a02 36 #ifndef IRQN_ID_T
AnnaBridge 161:aa5281ff4a02 37 #define IRQN_ID_T
AnnaBridge 161:aa5281ff4a02 38 /// Interrupt ID number data type
AnnaBridge 161:aa5281ff4a02 39 typedef int32_t IRQn_ID_t;
AnnaBridge 161:aa5281ff4a02 40 #endif
AnnaBridge 161:aa5281ff4a02 41
AnnaBridge 161:aa5281ff4a02 42 /* Interrupt mode bit-masks */
AnnaBridge 161:aa5281ff4a02 43 #define IRQ_MODE_TRIG_Pos (0U)
AnnaBridge 161:aa5281ff4a02 44 #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
AnnaBridge 161:aa5281ff4a02 45 #define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
AnnaBridge 161:aa5281ff4a02 46 #define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
AnnaBridge 161:aa5281ff4a02 47 #define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
AnnaBridge 161:aa5281ff4a02 48 #define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
AnnaBridge 161:aa5281ff4a02 49 #define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
AnnaBridge 161:aa5281ff4a02 50 #define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
AnnaBridge 161:aa5281ff4a02 51 #define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
AnnaBridge 161:aa5281ff4a02 52
AnnaBridge 161:aa5281ff4a02 53 #define IRQ_MODE_TYPE_Pos (3U)
AnnaBridge 161:aa5281ff4a02 54 #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
AnnaBridge 161:aa5281ff4a02 55 #define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
AnnaBridge 161:aa5281ff4a02 56 #define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
AnnaBridge 161:aa5281ff4a02 57
AnnaBridge 161:aa5281ff4a02 58 #define IRQ_MODE_DOMAIN_Pos (4U)
AnnaBridge 161:aa5281ff4a02 59 #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
AnnaBridge 161:aa5281ff4a02 60 #define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
AnnaBridge 161:aa5281ff4a02 61 #define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
AnnaBridge 161:aa5281ff4a02 62
AnnaBridge 161:aa5281ff4a02 63 #define IRQ_MODE_CPU_Pos (5U)
AnnaBridge 161:aa5281ff4a02 64 #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
AnnaBridge 161:aa5281ff4a02 65 #define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
AnnaBridge 161:aa5281ff4a02 66 #define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
AnnaBridge 161:aa5281ff4a02 67 #define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
AnnaBridge 161:aa5281ff4a02 68 #define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
AnnaBridge 161:aa5281ff4a02 69 #define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
AnnaBridge 161:aa5281ff4a02 70 #define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
AnnaBridge 161:aa5281ff4a02 71 #define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
AnnaBridge 161:aa5281ff4a02 72 #define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
AnnaBridge 161:aa5281ff4a02 73 #define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
AnnaBridge 161:aa5281ff4a02 74
AnnaBridge 161:aa5281ff4a02 75 #define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
AnnaBridge 161:aa5281ff4a02 76
AnnaBridge 161:aa5281ff4a02 77 /* Interrupt priority bit-masks */
AnnaBridge 161:aa5281ff4a02 78 #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
AnnaBridge 161:aa5281ff4a02 79 #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
AnnaBridge 161:aa5281ff4a02 80
AnnaBridge 161:aa5281ff4a02 81 /// Initialize interrupt controller.
AnnaBridge 161:aa5281ff4a02 82 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 83 int32_t IRQ_Initialize (void);
AnnaBridge 161:aa5281ff4a02 84
AnnaBridge 161:aa5281ff4a02 85 /// Register interrupt handler.
AnnaBridge 161:aa5281ff4a02 86 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 87 /// \param[in] handler interrupt handler function address
AnnaBridge 161:aa5281ff4a02 88 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 89 int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
AnnaBridge 161:aa5281ff4a02 90
AnnaBridge 161:aa5281ff4a02 91 /// Get the registered interrupt handler.
AnnaBridge 161:aa5281ff4a02 92 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 93 /// \return registered interrupt handler function address.
AnnaBridge 161:aa5281ff4a02 94 IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 95
AnnaBridge 161:aa5281ff4a02 96 /// Enable interrupt.
AnnaBridge 161:aa5281ff4a02 97 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 98 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 99 int32_t IRQ_Enable (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 100
AnnaBridge 161:aa5281ff4a02 101 /// Disable interrupt.
AnnaBridge 161:aa5281ff4a02 102 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 103 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 104 int32_t IRQ_Disable (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 105
AnnaBridge 161:aa5281ff4a02 106 /// Get interrupt enable state.
AnnaBridge 161:aa5281ff4a02 107 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 108 /// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
AnnaBridge 161:aa5281ff4a02 109 uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 110
AnnaBridge 161:aa5281ff4a02 111 /// Configure interrupt request mode.
AnnaBridge 161:aa5281ff4a02 112 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 113 /// \param[in] mode mode configuration
AnnaBridge 161:aa5281ff4a02 114 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 115 int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
AnnaBridge 161:aa5281ff4a02 116
AnnaBridge 161:aa5281ff4a02 117 /// Get interrupt mode configuration.
AnnaBridge 161:aa5281ff4a02 118 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 119 /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
AnnaBridge 161:aa5281ff4a02 120 uint32_t IRQ_GetMode (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 121
AnnaBridge 161:aa5281ff4a02 122 /// Get ID number of current interrupt request (IRQ).
AnnaBridge 161:aa5281ff4a02 123 /// \return interrupt ID number.
AnnaBridge 161:aa5281ff4a02 124 IRQn_ID_t IRQ_GetActiveIRQ (void);
AnnaBridge 161:aa5281ff4a02 125
AnnaBridge 161:aa5281ff4a02 126 /// Get ID number of current fast interrupt request (FIQ).
AnnaBridge 161:aa5281ff4a02 127 /// \return interrupt ID number.
AnnaBridge 161:aa5281ff4a02 128 IRQn_ID_t IRQ_GetActiveFIQ (void);
AnnaBridge 161:aa5281ff4a02 129
AnnaBridge 161:aa5281ff4a02 130 /// Signal end of interrupt processing.
AnnaBridge 161:aa5281ff4a02 131 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 132 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 133 int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 134
AnnaBridge 161:aa5281ff4a02 135 /// Set interrupt pending flag.
AnnaBridge 161:aa5281ff4a02 136 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 137 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 138 int32_t IRQ_SetPending (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 139
AnnaBridge 161:aa5281ff4a02 140 /// Get interrupt pending flag.
AnnaBridge 161:aa5281ff4a02 141 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 142 /// \return 0 - interrupt is not pending, 1 - interrupt is pending.
AnnaBridge 161:aa5281ff4a02 143 uint32_t IRQ_GetPending (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 144
AnnaBridge 161:aa5281ff4a02 145 /// Clear interrupt pending flag.
AnnaBridge 161:aa5281ff4a02 146 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 147 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 148 int32_t IRQ_ClearPending (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 149
AnnaBridge 161:aa5281ff4a02 150 /// Set interrupt priority value.
AnnaBridge 161:aa5281ff4a02 151 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 152 /// \param[in] priority interrupt priority value
AnnaBridge 161:aa5281ff4a02 153 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 154 int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
AnnaBridge 161:aa5281ff4a02 155
AnnaBridge 161:aa5281ff4a02 156 /// Get interrupt priority.
AnnaBridge 161:aa5281ff4a02 157 /// \param[in] irqn interrupt ID number
AnnaBridge 161:aa5281ff4a02 158 /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
AnnaBridge 161:aa5281ff4a02 159 uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
AnnaBridge 161:aa5281ff4a02 160
AnnaBridge 161:aa5281ff4a02 161 /// Set priority masking threshold.
AnnaBridge 161:aa5281ff4a02 162 /// \param[in] priority priority masking threshold value
AnnaBridge 161:aa5281ff4a02 163 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 164 int32_t IRQ_SetPriorityMask (uint32_t priority);
AnnaBridge 161:aa5281ff4a02 165
AnnaBridge 161:aa5281ff4a02 166 /// Get priority masking threshold
AnnaBridge 161:aa5281ff4a02 167 /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
AnnaBridge 161:aa5281ff4a02 168 uint32_t IRQ_GetPriorityMask (void);
AnnaBridge 161:aa5281ff4a02 169
AnnaBridge 161:aa5281ff4a02 170 /// Set priority grouping field split point
AnnaBridge 161:aa5281ff4a02 171 /// \param[in] bits number of MSB bits included in the group priority field comparison
AnnaBridge 161:aa5281ff4a02 172 /// \return 0 on success, -1 on error.
AnnaBridge 161:aa5281ff4a02 173 int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
AnnaBridge 161:aa5281ff4a02 174
AnnaBridge 161:aa5281ff4a02 175 /// Get priority grouping field split point
AnnaBridge 161:aa5281ff4a02 176 /// \return current number of MSB bits included in the group priority field comparison with
AnnaBridge 161:aa5281ff4a02 177 /// optional IRQ_PRIORITY_ERROR bit set.
AnnaBridge 161:aa5281ff4a02 178 uint32_t IRQ_GetPriorityGroupBits (void);
AnnaBridge 161:aa5281ff4a02 179
AnnaBridge 161:aa5281ff4a02 180 #endif // IRQ_CTRL_H_