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TARGET_DISCO_L496AG/mpu_armv8.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
165:d1b4690b3f8b
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /******************************************************************************
AnnaBridge 165:d1b4690b3f8b 2 * @file mpu_armv8.h
AnnaBridge 165:d1b4690b3f8b 3 * @brief CMSIS MPU API for ARMv8 MPU
AnnaBridge 165:d1b4690b3f8b 4 * @version V5.0.3
AnnaBridge 165:d1b4690b3f8b 5 * @date 09. August 2017
AnnaBridge 165:d1b4690b3f8b 6 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 7 /*
AnnaBridge 165:d1b4690b3f8b 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
AnnaBridge 165:d1b4690b3f8b 9 *
AnnaBridge 165:d1b4690b3f8b 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 165:d1b4690b3f8b 11 *
AnnaBridge 165:d1b4690b3f8b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 165:d1b4690b3f8b 13 * not use this file except in compliance with the License.
AnnaBridge 165:d1b4690b3f8b 14 * You may obtain a copy of the License at
AnnaBridge 165:d1b4690b3f8b 15 *
AnnaBridge 165:d1b4690b3f8b 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 165:d1b4690b3f8b 17 *
AnnaBridge 165:d1b4690b3f8b 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 165:d1b4690b3f8b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 165:d1b4690b3f8b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 165:d1b4690b3f8b 21 * See the License for the specific language governing permissions and
AnnaBridge 165:d1b4690b3f8b 22 * limitations under the License.
AnnaBridge 165:d1b4690b3f8b 23 */
AnnaBridge 165:d1b4690b3f8b 24
AnnaBridge 165:d1b4690b3f8b 25 #ifndef ARM_MPU_ARMV8_H
AnnaBridge 165:d1b4690b3f8b 26 #define ARM_MPU_ARMV8_H
AnnaBridge 165:d1b4690b3f8b 27
AnnaBridge 165:d1b4690b3f8b 28 /** \brief Attribute for device memory (outer only) */
AnnaBridge 165:d1b4690b3f8b 29 #define ARM_MPU_ATTR_DEVICE ( 0U )
AnnaBridge 165:d1b4690b3f8b 30
AnnaBridge 165:d1b4690b3f8b 31 /** \brief Attribute for non-cacheable, normal memory */
AnnaBridge 165:d1b4690b3f8b 32 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
AnnaBridge 165:d1b4690b3f8b 33
AnnaBridge 165:d1b4690b3f8b 34 /** \brief Attribute for normal memory (outer and inner)
AnnaBridge 165:d1b4690b3f8b 35 * \param NT Non-Transient: Set to 1 for non-transient data.
AnnaBridge 165:d1b4690b3f8b 36 * \param WB Write-Back: Set to 1 to use write-back update policy.
AnnaBridge 165:d1b4690b3f8b 37 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
AnnaBridge 165:d1b4690b3f8b 38 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
AnnaBridge 165:d1b4690b3f8b 39 */
AnnaBridge 165:d1b4690b3f8b 40 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
AnnaBridge 165:d1b4690b3f8b 41 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
AnnaBridge 165:d1b4690b3f8b 42
AnnaBridge 165:d1b4690b3f8b 43 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
AnnaBridge 165:d1b4690b3f8b 44 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
AnnaBridge 165:d1b4690b3f8b 45
AnnaBridge 165:d1b4690b3f8b 46 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
AnnaBridge 165:d1b4690b3f8b 47 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
AnnaBridge 165:d1b4690b3f8b 48
AnnaBridge 165:d1b4690b3f8b 49 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 165:d1b4690b3f8b 50 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
AnnaBridge 165:d1b4690b3f8b 51
AnnaBridge 165:d1b4690b3f8b 52 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 165:d1b4690b3f8b 53 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
AnnaBridge 165:d1b4690b3f8b 54
AnnaBridge 165:d1b4690b3f8b 55 /** \brief Memory Attribute
AnnaBridge 165:d1b4690b3f8b 56 * \param O Outer memory attributes
AnnaBridge 165:d1b4690b3f8b 57 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
AnnaBridge 165:d1b4690b3f8b 58 */
AnnaBridge 165:d1b4690b3f8b 59 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
AnnaBridge 165:d1b4690b3f8b 60
AnnaBridge 165:d1b4690b3f8b 61 /** \brief Normal memory non-shareable */
AnnaBridge 165:d1b4690b3f8b 62 #define ARM_MPU_SH_NON (0U)
AnnaBridge 165:d1b4690b3f8b 63
AnnaBridge 165:d1b4690b3f8b 64 /** \brief Normal memory outer shareable */
AnnaBridge 165:d1b4690b3f8b 65 #define ARM_MPU_SH_OUTER (2U)
AnnaBridge 165:d1b4690b3f8b 66
AnnaBridge 165:d1b4690b3f8b 67 /** \brief Normal memory inner shareable */
AnnaBridge 165:d1b4690b3f8b 68 #define ARM_MPU_SH_INNER (3U)
AnnaBridge 165:d1b4690b3f8b 69
AnnaBridge 165:d1b4690b3f8b 70 /** \brief Memory access permissions
AnnaBridge 165:d1b4690b3f8b 71 * \param RO Read-Only: Set to 1 for read-only memory.
AnnaBridge 165:d1b4690b3f8b 72 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
AnnaBridge 165:d1b4690b3f8b 73 */
AnnaBridge 165:d1b4690b3f8b 74 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
AnnaBridge 165:d1b4690b3f8b 75
AnnaBridge 165:d1b4690b3f8b 76 /** \brief Region Base Address Register value
AnnaBridge 165:d1b4690b3f8b 77 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
AnnaBridge 165:d1b4690b3f8b 78 * \param SH Defines the Shareability domain for this memory region.
AnnaBridge 165:d1b4690b3f8b 79 * \param RO Read-Only: Set to 1 for a read-only memory region.
AnnaBridge 165:d1b4690b3f8b 80 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
AnnaBridge 165:d1b4690b3f8b 81 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
AnnaBridge 165:d1b4690b3f8b 82 */
AnnaBridge 165:d1b4690b3f8b 83 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
AnnaBridge 165:d1b4690b3f8b 84 ((BASE & MPU_RBAR_BASE_Pos) | \
AnnaBridge 165:d1b4690b3f8b 85 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
AnnaBridge 165:d1b4690b3f8b 86 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
AnnaBridge 165:d1b4690b3f8b 87 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
AnnaBridge 165:d1b4690b3f8b 88
AnnaBridge 165:d1b4690b3f8b 89 /** \brief Region Limit Address Register value
AnnaBridge 165:d1b4690b3f8b 90 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
AnnaBridge 165:d1b4690b3f8b 91 * \param IDX The attribute index to be associated with this memory region.
AnnaBridge 165:d1b4690b3f8b 92 */
AnnaBridge 165:d1b4690b3f8b 93 #define ARM_MPU_RLAR(LIMIT, IDX) \
AnnaBridge 165:d1b4690b3f8b 94 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
AnnaBridge 165:d1b4690b3f8b 95 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
AnnaBridge 165:d1b4690b3f8b 96 (MPU_RLAR_EN_Msk))
AnnaBridge 165:d1b4690b3f8b 97
AnnaBridge 165:d1b4690b3f8b 98 /**
AnnaBridge 165:d1b4690b3f8b 99 * Struct for a single MPU Region
AnnaBridge 165:d1b4690b3f8b 100 */
AnnaBridge 165:d1b4690b3f8b 101 typedef struct _ARM_MPU_Region_t {
AnnaBridge 165:d1b4690b3f8b 102 uint32_t RBAR; /*!< Region Base Address Register value */
AnnaBridge 165:d1b4690b3f8b 103 uint32_t RLAR; /*!< Region Limit Address Register value */
AnnaBridge 165:d1b4690b3f8b 104 } ARM_MPU_Region_t;
AnnaBridge 165:d1b4690b3f8b 105
AnnaBridge 165:d1b4690b3f8b 106 /** Enable the MPU.
AnnaBridge 165:d1b4690b3f8b 107 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 165:d1b4690b3f8b 108 */
AnnaBridge 165:d1b4690b3f8b 109 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 165:d1b4690b3f8b 110 {
AnnaBridge 165:d1b4690b3f8b 111 __DSB();
AnnaBridge 165:d1b4690b3f8b 112 __ISB();
AnnaBridge 165:d1b4690b3f8b 113 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 114 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 115 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 116 #endif
AnnaBridge 165:d1b4690b3f8b 117 }
AnnaBridge 165:d1b4690b3f8b 118
AnnaBridge 165:d1b4690b3f8b 119 /** Disable the MPU.
AnnaBridge 165:d1b4690b3f8b 120 */
AnnaBridge 165:d1b4690b3f8b 121 __STATIC_INLINE void ARM_MPU_Disable(void)
AnnaBridge 165:d1b4690b3f8b 122 {
AnnaBridge 165:d1b4690b3f8b 123 __DSB();
AnnaBridge 165:d1b4690b3f8b 124 __ISB();
AnnaBridge 165:d1b4690b3f8b 125 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 126 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 127 #endif
AnnaBridge 165:d1b4690b3f8b 128 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 129 }
AnnaBridge 165:d1b4690b3f8b 130
AnnaBridge 165:d1b4690b3f8b 131 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 132 /** Enable the Non-secure MPU.
AnnaBridge 165:d1b4690b3f8b 133 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 165:d1b4690b3f8b 134 */
AnnaBridge 165:d1b4690b3f8b 135 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
AnnaBridge 165:d1b4690b3f8b 136 {
AnnaBridge 165:d1b4690b3f8b 137 __DSB();
AnnaBridge 165:d1b4690b3f8b 138 __ISB();
AnnaBridge 165:d1b4690b3f8b 139 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 140 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 141 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 142 #endif
AnnaBridge 165:d1b4690b3f8b 143 }
AnnaBridge 165:d1b4690b3f8b 144
AnnaBridge 165:d1b4690b3f8b 145 /** Disable the Non-secure MPU.
AnnaBridge 165:d1b4690b3f8b 146 */
AnnaBridge 165:d1b4690b3f8b 147 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
AnnaBridge 165:d1b4690b3f8b 148 {
AnnaBridge 165:d1b4690b3f8b 149 __DSB();
AnnaBridge 165:d1b4690b3f8b 150 __ISB();
AnnaBridge 165:d1b4690b3f8b 151 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 152 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 153 #endif
AnnaBridge 165:d1b4690b3f8b 154 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 155 }
AnnaBridge 165:d1b4690b3f8b 156 #endif
AnnaBridge 165:d1b4690b3f8b 157
AnnaBridge 165:d1b4690b3f8b 158 /** Set the memory attribute encoding to the given MPU.
AnnaBridge 165:d1b4690b3f8b 159 * \param mpu Pointer to the MPU to be configured.
AnnaBridge 165:d1b4690b3f8b 160 * \param idx The attribute index to be set [0-7]
AnnaBridge 165:d1b4690b3f8b 161 * \param attr The attribute value to be set.
AnnaBridge 165:d1b4690b3f8b 162 */
AnnaBridge 165:d1b4690b3f8b 163 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
AnnaBridge 165:d1b4690b3f8b 164 {
AnnaBridge 165:d1b4690b3f8b 165 const uint8_t reg = idx / 4U;
AnnaBridge 165:d1b4690b3f8b 166 const uint32_t pos = ((idx % 4U) * 8U);
AnnaBridge 165:d1b4690b3f8b 167 const uint32_t mask = 0xFFU << pos;
AnnaBridge 165:d1b4690b3f8b 168
AnnaBridge 165:d1b4690b3f8b 169 if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) {
AnnaBridge 165:d1b4690b3f8b 170 return; // invalid index
AnnaBridge 165:d1b4690b3f8b 171 }
AnnaBridge 165:d1b4690b3f8b 172
AnnaBridge 165:d1b4690b3f8b 173 MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask));
AnnaBridge 165:d1b4690b3f8b 174 }
AnnaBridge 165:d1b4690b3f8b 175
AnnaBridge 165:d1b4690b3f8b 176 /** Set the memory attribute encoding.
AnnaBridge 165:d1b4690b3f8b 177 * \param idx The attribute index to be set [0-7]
AnnaBridge 165:d1b4690b3f8b 178 * \param attr The attribute value to be set.
AnnaBridge 165:d1b4690b3f8b 179 */
AnnaBridge 165:d1b4690b3f8b 180 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
AnnaBridge 165:d1b4690b3f8b 181 {
AnnaBridge 165:d1b4690b3f8b 182 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
AnnaBridge 165:d1b4690b3f8b 183 }
AnnaBridge 165:d1b4690b3f8b 184
AnnaBridge 165:d1b4690b3f8b 185 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 186 /** Set the memory attribute encoding to the Non-secure MPU.
AnnaBridge 165:d1b4690b3f8b 187 * \param idx The attribute index to be set [0-7]
AnnaBridge 165:d1b4690b3f8b 188 * \param attr The attribute value to be set.
AnnaBridge 165:d1b4690b3f8b 189 */
AnnaBridge 165:d1b4690b3f8b 190 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
AnnaBridge 165:d1b4690b3f8b 191 {
AnnaBridge 165:d1b4690b3f8b 192 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
AnnaBridge 165:d1b4690b3f8b 193 }
AnnaBridge 165:d1b4690b3f8b 194 #endif
AnnaBridge 165:d1b4690b3f8b 195
AnnaBridge 165:d1b4690b3f8b 196 /** Clear and disable the given MPU region of the given MPU.
AnnaBridge 165:d1b4690b3f8b 197 * \param mpu Pointer to MPU to be used.
AnnaBridge 165:d1b4690b3f8b 198 * \param rnr Region number to be cleared.
AnnaBridge 165:d1b4690b3f8b 199 */
AnnaBridge 165:d1b4690b3f8b 200 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
AnnaBridge 165:d1b4690b3f8b 201 {
AnnaBridge 165:d1b4690b3f8b 202 MPU->RNR = rnr;
AnnaBridge 165:d1b4690b3f8b 203 MPU->RLAR = 0U;
AnnaBridge 165:d1b4690b3f8b 204 }
AnnaBridge 165:d1b4690b3f8b 205
AnnaBridge 165:d1b4690b3f8b 206 /** Clear and disable the given MPU region.
AnnaBridge 165:d1b4690b3f8b 207 * \param rnr Region number to be cleared.
AnnaBridge 165:d1b4690b3f8b 208 */
AnnaBridge 165:d1b4690b3f8b 209 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
AnnaBridge 165:d1b4690b3f8b 210 {
AnnaBridge 165:d1b4690b3f8b 211 ARM_MPU_ClrRegionEx(MPU, rnr);
AnnaBridge 165:d1b4690b3f8b 212 }
AnnaBridge 165:d1b4690b3f8b 213
AnnaBridge 165:d1b4690b3f8b 214 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 215 /** Clear and disable the given Non-secure MPU region.
AnnaBridge 165:d1b4690b3f8b 216 * \param rnr Region number to be cleared.
AnnaBridge 165:d1b4690b3f8b 217 */
AnnaBridge 165:d1b4690b3f8b 218 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
AnnaBridge 165:d1b4690b3f8b 219 {
AnnaBridge 165:d1b4690b3f8b 220 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
AnnaBridge 165:d1b4690b3f8b 221 }
AnnaBridge 165:d1b4690b3f8b 222 #endif
AnnaBridge 165:d1b4690b3f8b 223
AnnaBridge 165:d1b4690b3f8b 224 /** Configure the given MPU region of the given MPU.
AnnaBridge 165:d1b4690b3f8b 225 * \param mpu Pointer to MPU to be used.
AnnaBridge 165:d1b4690b3f8b 226 * \param rnr Region number to be configured.
AnnaBridge 165:d1b4690b3f8b 227 * \param rbar Value for RBAR register.
AnnaBridge 165:d1b4690b3f8b 228 * \param rlar Value for RLAR register.
AnnaBridge 165:d1b4690b3f8b 229 */
AnnaBridge 165:d1b4690b3f8b 230 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 165:d1b4690b3f8b 231 {
AnnaBridge 165:d1b4690b3f8b 232 MPU->RNR = rnr;
AnnaBridge 165:d1b4690b3f8b 233 MPU->RBAR = rbar;
AnnaBridge 165:d1b4690b3f8b 234 MPU->RLAR = rlar;
AnnaBridge 165:d1b4690b3f8b 235 }
AnnaBridge 165:d1b4690b3f8b 236
AnnaBridge 165:d1b4690b3f8b 237 /** Configure the given MPU region.
AnnaBridge 165:d1b4690b3f8b 238 * \param rnr Region number to be configured.
AnnaBridge 165:d1b4690b3f8b 239 * \param rbar Value for RBAR register.
AnnaBridge 165:d1b4690b3f8b 240 * \param rlar Value for RLAR register.
AnnaBridge 165:d1b4690b3f8b 241 */
AnnaBridge 165:d1b4690b3f8b 242 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 165:d1b4690b3f8b 243 {
AnnaBridge 165:d1b4690b3f8b 244 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
AnnaBridge 165:d1b4690b3f8b 245 }
AnnaBridge 165:d1b4690b3f8b 246
AnnaBridge 165:d1b4690b3f8b 247 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 248 /** Configure the given Non-secure MPU region.
AnnaBridge 165:d1b4690b3f8b 249 * \param rnr Region number to be configured.
AnnaBridge 165:d1b4690b3f8b 250 * \param rbar Value for RBAR register.
AnnaBridge 165:d1b4690b3f8b 251 * \param rlar Value for RLAR register.
AnnaBridge 165:d1b4690b3f8b 252 */
AnnaBridge 165:d1b4690b3f8b 253 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 165:d1b4690b3f8b 254 {
AnnaBridge 165:d1b4690b3f8b 255 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
AnnaBridge 165:d1b4690b3f8b 256 }
AnnaBridge 165:d1b4690b3f8b 257 #endif
AnnaBridge 165:d1b4690b3f8b 258
AnnaBridge 165:d1b4690b3f8b 259 /** Memcopy with strictly ordered memory access, e.g. for register targets.
AnnaBridge 165:d1b4690b3f8b 260 * \param dst Destination data is copied to.
AnnaBridge 165:d1b4690b3f8b 261 * \param src Source data is copied from.
AnnaBridge 165:d1b4690b3f8b 262 * \param len Amount of data words to be copied.
AnnaBridge 165:d1b4690b3f8b 263 */
AnnaBridge 165:d1b4690b3f8b 264 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
AnnaBridge 165:d1b4690b3f8b 265 {
AnnaBridge 165:d1b4690b3f8b 266 uint32_t i;
AnnaBridge 165:d1b4690b3f8b 267 for (i = 0U; i < len; ++i)
AnnaBridge 165:d1b4690b3f8b 268 {
AnnaBridge 165:d1b4690b3f8b 269 dst[i] = src[i];
AnnaBridge 165:d1b4690b3f8b 270 }
AnnaBridge 165:d1b4690b3f8b 271 }
AnnaBridge 165:d1b4690b3f8b 272
AnnaBridge 165:d1b4690b3f8b 273 /** Load the given number of MPU regions from a table to the given MPU.
AnnaBridge 165:d1b4690b3f8b 274 * \param mpu Pointer to the MPU registers to be used.
AnnaBridge 165:d1b4690b3f8b 275 * \param rnr First region number to be configured.
AnnaBridge 165:d1b4690b3f8b 276 * \param table Pointer to the MPU configuration table.
AnnaBridge 165:d1b4690b3f8b 277 * \param cnt Amount of regions to be configured.
AnnaBridge 165:d1b4690b3f8b 278 */
AnnaBridge 165:d1b4690b3f8b 279 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 165:d1b4690b3f8b 280 {
AnnaBridge 165:d1b4690b3f8b 281 static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
AnnaBridge 165:d1b4690b3f8b 282 if (cnt == 1U) {
AnnaBridge 165:d1b4690b3f8b 283 mpu->RNR = rnr;
AnnaBridge 165:d1b4690b3f8b 284 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
AnnaBridge 165:d1b4690b3f8b 285 } else {
AnnaBridge 165:d1b4690b3f8b 286 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
AnnaBridge 165:d1b4690b3f8b 287 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
AnnaBridge 165:d1b4690b3f8b 288
AnnaBridge 165:d1b4690b3f8b 289 mpu->RNR = rnrBase;
AnnaBridge 165:d1b4690b3f8b 290 if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
AnnaBridge 165:d1b4690b3f8b 291 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
AnnaBridge 165:d1b4690b3f8b 292 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
AnnaBridge 165:d1b4690b3f8b 293 ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c);
AnnaBridge 165:d1b4690b3f8b 294 } else {
AnnaBridge 165:d1b4690b3f8b 295 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
AnnaBridge 165:d1b4690b3f8b 296 }
AnnaBridge 165:d1b4690b3f8b 297 }
AnnaBridge 165:d1b4690b3f8b 298 }
AnnaBridge 165:d1b4690b3f8b 299
AnnaBridge 165:d1b4690b3f8b 300 /** Load the given number of MPU regions from a table.
AnnaBridge 165:d1b4690b3f8b 301 * \param rnr First region number to be configured.
AnnaBridge 165:d1b4690b3f8b 302 * \param table Pointer to the MPU configuration table.
AnnaBridge 165:d1b4690b3f8b 303 * \param cnt Amount of regions to be configured.
AnnaBridge 165:d1b4690b3f8b 304 */
AnnaBridge 165:d1b4690b3f8b 305 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 165:d1b4690b3f8b 306 {
AnnaBridge 165:d1b4690b3f8b 307 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
AnnaBridge 165:d1b4690b3f8b 308 }
AnnaBridge 165:d1b4690b3f8b 309
AnnaBridge 165:d1b4690b3f8b 310 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 311 /** Load the given number of MPU regions from a table to the Non-secure MPU.
AnnaBridge 165:d1b4690b3f8b 312 * \param rnr First region number to be configured.
AnnaBridge 165:d1b4690b3f8b 313 * \param table Pointer to the MPU configuration table.
AnnaBridge 165:d1b4690b3f8b 314 * \param cnt Amount of regions to be configured.
AnnaBridge 165:d1b4690b3f8b 315 */
AnnaBridge 165:d1b4690b3f8b 316 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 165:d1b4690b3f8b 317 {
AnnaBridge 165:d1b4690b3f8b 318 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
AnnaBridge 165:d1b4690b3f8b 319 }
AnnaBridge 165:d1b4690b3f8b 320 #endif
AnnaBridge 165:d1b4690b3f8b 321
AnnaBridge 165:d1b4690b3f8b 322 #endif
AnnaBridge 165:d1b4690b3f8b 323