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TARGET_DISCO_L496AG/mpu_armv7.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
165:d1b4690b3f8b
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /******************************************************************************
AnnaBridge 165:d1b4690b3f8b 2 * @file mpu_armv7.h
AnnaBridge 165:d1b4690b3f8b 3 * @brief CMSIS MPU API for ARMv7 MPU
AnnaBridge 165:d1b4690b3f8b 4 * @version V5.0.3
AnnaBridge 165:d1b4690b3f8b 5 * @date 09. August 2017
AnnaBridge 165:d1b4690b3f8b 6 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 7 /*
AnnaBridge 165:d1b4690b3f8b 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
AnnaBridge 165:d1b4690b3f8b 9 *
AnnaBridge 165:d1b4690b3f8b 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 165:d1b4690b3f8b 11 *
AnnaBridge 165:d1b4690b3f8b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 165:d1b4690b3f8b 13 * not use this file except in compliance with the License.
AnnaBridge 165:d1b4690b3f8b 14 * You may obtain a copy of the License at
AnnaBridge 165:d1b4690b3f8b 15 *
AnnaBridge 165:d1b4690b3f8b 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 165:d1b4690b3f8b 17 *
AnnaBridge 165:d1b4690b3f8b 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 165:d1b4690b3f8b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 165:d1b4690b3f8b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 165:d1b4690b3f8b 21 * See the License for the specific language governing permissions and
AnnaBridge 165:d1b4690b3f8b 22 * limitations under the License.
AnnaBridge 165:d1b4690b3f8b 23 */
AnnaBridge 165:d1b4690b3f8b 24
AnnaBridge 165:d1b4690b3f8b 25 #ifndef ARM_MPU_ARMV7_H
AnnaBridge 165:d1b4690b3f8b 26 #define ARM_MPU_ARMV7_H
AnnaBridge 165:d1b4690b3f8b 27
AnnaBridge 165:d1b4690b3f8b 28 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
AnnaBridge 165:d1b4690b3f8b 29 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
AnnaBridge 165:d1b4690b3f8b 30 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
AnnaBridge 165:d1b4690b3f8b 31 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
AnnaBridge 165:d1b4690b3f8b 32 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
AnnaBridge 165:d1b4690b3f8b 33 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
AnnaBridge 165:d1b4690b3f8b 34 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
AnnaBridge 165:d1b4690b3f8b 35 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
AnnaBridge 165:d1b4690b3f8b 36 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
AnnaBridge 165:d1b4690b3f8b 37 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
AnnaBridge 165:d1b4690b3f8b 38 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
AnnaBridge 165:d1b4690b3f8b 39 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
AnnaBridge 165:d1b4690b3f8b 40 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
AnnaBridge 165:d1b4690b3f8b 41 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
AnnaBridge 165:d1b4690b3f8b 42 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
AnnaBridge 165:d1b4690b3f8b 43 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
AnnaBridge 165:d1b4690b3f8b 44 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
AnnaBridge 165:d1b4690b3f8b 45 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
AnnaBridge 165:d1b4690b3f8b 46 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
AnnaBridge 165:d1b4690b3f8b 47 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
AnnaBridge 165:d1b4690b3f8b 48 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
AnnaBridge 165:d1b4690b3f8b 49 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
AnnaBridge 165:d1b4690b3f8b 50 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
AnnaBridge 165:d1b4690b3f8b 51 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
AnnaBridge 165:d1b4690b3f8b 52 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
AnnaBridge 165:d1b4690b3f8b 53 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
AnnaBridge 165:d1b4690b3f8b 54 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
AnnaBridge 165:d1b4690b3f8b 55 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
AnnaBridge 165:d1b4690b3f8b 56
AnnaBridge 165:d1b4690b3f8b 57 #define ARM_MPU_AP_NONE 0U
AnnaBridge 165:d1b4690b3f8b 58 #define ARM_MPU_AP_PRIV 1U
AnnaBridge 165:d1b4690b3f8b 59 #define ARM_MPU_AP_URO 2U
AnnaBridge 165:d1b4690b3f8b 60 #define ARM_MPU_AP_FULL 3U
AnnaBridge 165:d1b4690b3f8b 61 #define ARM_MPU_AP_PRO 5U
AnnaBridge 165:d1b4690b3f8b 62 #define ARM_MPU_AP_RO 6U
AnnaBridge 165:d1b4690b3f8b 63
AnnaBridge 165:d1b4690b3f8b 64 /** MPU Region Base Address Register Value
AnnaBridge 165:d1b4690b3f8b 65 *
AnnaBridge 165:d1b4690b3f8b 66 * \param Region The region to be configured, number 0 to 15.
AnnaBridge 165:d1b4690b3f8b 67 * \param BaseAddress The base address for the region.
AnnaBridge 165:d1b4690b3f8b 68 */
AnnaBridge 165:d1b4690b3f8b 69 #define ARM_MPU_RBAR(Region, BaseAddress) \
AnnaBridge 165:d1b4690b3f8b 70 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
AnnaBridge 165:d1b4690b3f8b 71 ((Region) & MPU_RBAR_REGION_Msk) | \
AnnaBridge 165:d1b4690b3f8b 72 (MPU_RBAR_VALID_Msk))
AnnaBridge 165:d1b4690b3f8b 73
AnnaBridge 165:d1b4690b3f8b 74 /**
AnnaBridge 165:d1b4690b3f8b 75 * MPU Region Attribut and Size Register Value
AnnaBridge 165:d1b4690b3f8b 76 *
AnnaBridge 165:d1b4690b3f8b 77 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
AnnaBridge 165:d1b4690b3f8b 78 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
AnnaBridge 165:d1b4690b3f8b 79 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
AnnaBridge 165:d1b4690b3f8b 80 * \param IsShareable Region is shareable between multiple bus masters.
AnnaBridge 165:d1b4690b3f8b 81 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
AnnaBridge 165:d1b4690b3f8b 82 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
AnnaBridge 165:d1b4690b3f8b 83 * \param SubRegionDisable Sub-region disable field.
AnnaBridge 165:d1b4690b3f8b 84 * \param Size Region size of the region to be configured, for example 4K, 8K.
AnnaBridge 165:d1b4690b3f8b 85 */
AnnaBridge 165:d1b4690b3f8b 86 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
AnnaBridge 165:d1b4690b3f8b 87 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
AnnaBridge 165:d1b4690b3f8b 88 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
AnnaBridge 165:d1b4690b3f8b 89 (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
AnnaBridge 165:d1b4690b3f8b 90 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
AnnaBridge 165:d1b4690b3f8b 91 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
AnnaBridge 165:d1b4690b3f8b 92 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
AnnaBridge 165:d1b4690b3f8b 93 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
AnnaBridge 165:d1b4690b3f8b 94 (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
AnnaBridge 165:d1b4690b3f8b 95 (MPU_RASR_ENABLE_Msk))
AnnaBridge 165:d1b4690b3f8b 96
AnnaBridge 165:d1b4690b3f8b 97
AnnaBridge 165:d1b4690b3f8b 98 /**
AnnaBridge 165:d1b4690b3f8b 99 * Struct for a single MPU Region
AnnaBridge 165:d1b4690b3f8b 100 */
AnnaBridge 165:d1b4690b3f8b 101 typedef struct _ARM_MPU_Region_t {
AnnaBridge 165:d1b4690b3f8b 102 uint32_t RBAR; //!< The region base address register value (RBAR)
AnnaBridge 165:d1b4690b3f8b 103 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
AnnaBridge 165:d1b4690b3f8b 104 } ARM_MPU_Region_t;
AnnaBridge 165:d1b4690b3f8b 105
AnnaBridge 165:d1b4690b3f8b 106 /** Enable the MPU.
AnnaBridge 165:d1b4690b3f8b 107 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 165:d1b4690b3f8b 108 */
AnnaBridge 165:d1b4690b3f8b 109 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 165:d1b4690b3f8b 110 {
AnnaBridge 165:d1b4690b3f8b 111 __DSB();
AnnaBridge 165:d1b4690b3f8b 112 __ISB();
AnnaBridge 165:d1b4690b3f8b 113 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 114 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 115 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 116 #endif
AnnaBridge 165:d1b4690b3f8b 117 }
AnnaBridge 165:d1b4690b3f8b 118
AnnaBridge 165:d1b4690b3f8b 119 /** Disable the MPU.
AnnaBridge 165:d1b4690b3f8b 120 */
AnnaBridge 165:d1b4690b3f8b 121 __STATIC_INLINE void ARM_MPU_Disable(void)
AnnaBridge 165:d1b4690b3f8b 122 {
AnnaBridge 165:d1b4690b3f8b 123 __DSB();
AnnaBridge 165:d1b4690b3f8b 124 __ISB();
AnnaBridge 165:d1b4690b3f8b 125 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 126 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 127 #endif
AnnaBridge 165:d1b4690b3f8b 128 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 129 }
AnnaBridge 165:d1b4690b3f8b 130
AnnaBridge 165:d1b4690b3f8b 131 /** Clear and disable the given MPU region.
AnnaBridge 165:d1b4690b3f8b 132 * \param rnr Region number to be cleared.
AnnaBridge 165:d1b4690b3f8b 133 */
AnnaBridge 165:d1b4690b3f8b 134 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
AnnaBridge 165:d1b4690b3f8b 135 {
AnnaBridge 165:d1b4690b3f8b 136 MPU->RNR = rnr;
AnnaBridge 165:d1b4690b3f8b 137 MPU->RASR = 0U;
AnnaBridge 165:d1b4690b3f8b 138 }
AnnaBridge 165:d1b4690b3f8b 139
AnnaBridge 165:d1b4690b3f8b 140 /** Configure an MPU region.
AnnaBridge 165:d1b4690b3f8b 141 * \param rbar Value for RBAR register.
AnnaBridge 165:d1b4690b3f8b 142 * \param rsar Value for RSAR register.
AnnaBridge 165:d1b4690b3f8b 143 */
AnnaBridge 165:d1b4690b3f8b 144 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
AnnaBridge 165:d1b4690b3f8b 145 {
AnnaBridge 165:d1b4690b3f8b 146 MPU->RBAR = rbar;
AnnaBridge 165:d1b4690b3f8b 147 MPU->RASR = rasr;
AnnaBridge 165:d1b4690b3f8b 148 }
AnnaBridge 165:d1b4690b3f8b 149
AnnaBridge 165:d1b4690b3f8b 150 /** Configure the given MPU region.
AnnaBridge 165:d1b4690b3f8b 151 * \param rnr Region number to be configured.
AnnaBridge 165:d1b4690b3f8b 152 * \param rbar Value for RBAR register.
AnnaBridge 165:d1b4690b3f8b 153 * \param rsar Value for RSAR register.
AnnaBridge 165:d1b4690b3f8b 154 */
AnnaBridge 165:d1b4690b3f8b 155 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
AnnaBridge 165:d1b4690b3f8b 156 {
AnnaBridge 165:d1b4690b3f8b 157 MPU->RNR = rnr;
AnnaBridge 165:d1b4690b3f8b 158 MPU->RBAR = rbar;
AnnaBridge 165:d1b4690b3f8b 159 MPU->RASR = rasr;
AnnaBridge 165:d1b4690b3f8b 160 }
AnnaBridge 165:d1b4690b3f8b 161
AnnaBridge 165:d1b4690b3f8b 162 /** Memcopy with strictly ordered memory access, e.g. for register targets.
AnnaBridge 165:d1b4690b3f8b 163 * \param dst Destination data is copied to.
AnnaBridge 165:d1b4690b3f8b 164 * \param src Source data is copied from.
AnnaBridge 165:d1b4690b3f8b 165 * \param len Amount of data words to be copied.
AnnaBridge 165:d1b4690b3f8b 166 */
AnnaBridge 165:d1b4690b3f8b 167 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
AnnaBridge 165:d1b4690b3f8b 168 {
AnnaBridge 165:d1b4690b3f8b 169 uint32_t i;
AnnaBridge 165:d1b4690b3f8b 170 for (i = 0U; i < len; ++i)
AnnaBridge 165:d1b4690b3f8b 171 {
AnnaBridge 165:d1b4690b3f8b 172 dst[i] = src[i];
AnnaBridge 165:d1b4690b3f8b 173 }
AnnaBridge 165:d1b4690b3f8b 174 }
AnnaBridge 165:d1b4690b3f8b 175
AnnaBridge 165:d1b4690b3f8b 176 /** Load the given number of MPU regions from a table.
AnnaBridge 165:d1b4690b3f8b 177 * \param table Pointer to the MPU configuration table.
AnnaBridge 165:d1b4690b3f8b 178 * \param cnt Amount of regions to be configured.
AnnaBridge 165:d1b4690b3f8b 179 */
AnnaBridge 165:d1b4690b3f8b 180 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 165:d1b4690b3f8b 181 {
AnnaBridge 165:d1b4690b3f8b 182 static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
AnnaBridge 165:d1b4690b3f8b 183 if (cnt > MPU_TYPE_RALIASES) {
AnnaBridge 165:d1b4690b3f8b 184 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
AnnaBridge 165:d1b4690b3f8b 185 ARM_MPU_Load(table+MPU_TYPE_RALIASES, cnt-MPU_TYPE_RALIASES);
AnnaBridge 165:d1b4690b3f8b 186 } else {
AnnaBridge 165:d1b4690b3f8b 187 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
AnnaBridge 165:d1b4690b3f8b 188 }
AnnaBridge 165:d1b4690b3f8b 189 }
AnnaBridge 165:d1b4690b3f8b 190
AnnaBridge 165:d1b4690b3f8b 191 #endif