mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_L496AG/core_cm4.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:: Anna Bridge
Date:: Fri Apr 20 11:08:29 2018 +0100
Revision:: 166:5aab5a7997ee
Parent:: 165:d1b4690b3f8b
Child:: 169:a7c7b631e539

Updating mbed 2 version number

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:d1b4690b3f8b	1	/************************************************************************//
AnnaBridge	165:d1b4690b3f8b	2	* @file core_cm4.h
AnnaBridge	165:d1b4690b3f8b	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
AnnaBridge	165:d1b4690b3f8b	4	* @version V5.0.3
AnnaBridge	165:d1b4690b3f8b	5	* @date 09. August 2017
AnnaBridge	165:d1b4690b3f8b	6	******************************************************************************/
AnnaBridge	165:d1b4690b3f8b	7	/*
AnnaBridge	165:d1b4690b3f8b	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	165:d1b4690b3f8b	9	*
AnnaBridge	165:d1b4690b3f8b	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	165:d1b4690b3f8b	11	*
AnnaBridge	165:d1b4690b3f8b	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	165:d1b4690b3f8b	13	* not use this file except in compliance with the License.
AnnaBridge	165:d1b4690b3f8b	14	* You may obtain a copy of the License at
AnnaBridge	165:d1b4690b3f8b	15	*
AnnaBridge	165:d1b4690b3f8b	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	165:d1b4690b3f8b	17	*
AnnaBridge	165:d1b4690b3f8b	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	165:d1b4690b3f8b	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	165:d1b4690b3f8b	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	165:d1b4690b3f8b	21	* See the License for the specific language governing permissions and
AnnaBridge	165:d1b4690b3f8b	22	* limitations under the License.
AnnaBridge	165:d1b4690b3f8b	23	*/
AnnaBridge	165:d1b4690b3f8b	24
AnnaBridge	165:d1b4690b3f8b	25	#if defined ( __ICCARM__ )
AnnaBridge	165:d1b4690b3f8b	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	165:d1b4690b3f8b	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	165:d1b4690b3f8b	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	165:d1b4690b3f8b	29	#endif
AnnaBridge	165:d1b4690b3f8b	30
AnnaBridge	165:d1b4690b3f8b	31	#ifndef __CORE_CM4_H_GENERIC
AnnaBridge	165:d1b4690b3f8b	32	#define __CORE_CM4_H_GENERIC
AnnaBridge	165:d1b4690b3f8b	33
AnnaBridge	165:d1b4690b3f8b	34	#include <stdint.h>
AnnaBridge	165:d1b4690b3f8b	35
AnnaBridge	165:d1b4690b3f8b	36	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	37	extern "C" {
AnnaBridge	165:d1b4690b3f8b	38	#endif
AnnaBridge	165:d1b4690b3f8b	39
AnnaBridge	165:d1b4690b3f8b	40	/**
AnnaBridge	165:d1b4690b3f8b	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	165:d1b4690b3f8b	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	165:d1b4690b3f8b	43
AnnaBridge	165:d1b4690b3f8b	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	165:d1b4690b3f8b	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	165:d1b4690b3f8b	46
AnnaBridge	165:d1b4690b3f8b	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	165:d1b4690b3f8b	48	Unions are used for effective representation of core registers.
AnnaBridge	165:d1b4690b3f8b	49
AnnaBridge	165:d1b4690b3f8b	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	165:d1b4690b3f8b	51	Function-like macros are used to allow more efficient code.
AnnaBridge	165:d1b4690b3f8b	52	*/
AnnaBridge	165:d1b4690b3f8b	53
AnnaBridge	165:d1b4690b3f8b	54
AnnaBridge	165:d1b4690b3f8b	55	/*******************************************************************************
AnnaBridge	165:d1b4690b3f8b	56	* CMSIS definitions
AnnaBridge	165:d1b4690b3f8b	57	******************************************************************************/
AnnaBridge	165:d1b4690b3f8b	58	/**
AnnaBridge	165:d1b4690b3f8b	59	\ingroup Cortex_M4
AnnaBridge	165:d1b4690b3f8b	60	@{
AnnaBridge	165:d1b4690b3f8b	61	*/
AnnaBridge	165:d1b4690b3f8b	62
AnnaBridge	165:d1b4690b3f8b	63	#include "cmsis_version.h"
AnnaBridge	165:d1b4690b3f8b	64
AnnaBridge	165:d1b4690b3f8b	65	/* CMSIS CM4 definitions */
AnnaBridge	165:d1b4690b3f8b	66	#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
AnnaBridge	165:d1b4690b3f8b	67	#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	165:d1b4690b3f8b	68	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	165:d1b4690b3f8b	69	__CM4_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	165:d1b4690b3f8b	70
AnnaBridge	165:d1b4690b3f8b	71	#define __CORTEX_M (4U) /!< Cortex-M Core /
AnnaBridge	165:d1b4690b3f8b	72
AnnaBridge	165:d1b4690b3f8b	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	165:d1b4690b3f8b	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	165:d1b4690b3f8b	75	*/
AnnaBridge	165:d1b4690b3f8b	76	#if defined ( __CC_ARM )
AnnaBridge	165:d1b4690b3f8b	77	#if defined __TARGET_FPU_VFP
AnnaBridge	165:d1b4690b3f8b	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	79	#define __FPU_USED 1U
AnnaBridge	165:d1b4690b3f8b	80	#else
AnnaBridge	165:d1b4690b3f8b	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	165:d1b4690b3f8b	82	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	83	#endif
AnnaBridge	165:d1b4690b3f8b	84	#else
AnnaBridge	165:d1b4690b3f8b	85	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	86	#endif
AnnaBridge	165:d1b4690b3f8b	87
AnnaBridge	165:d1b4690b3f8b	88	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	165:d1b4690b3f8b	89	#if defined __ARM_PCS_VFP
AnnaBridge	165:d1b4690b3f8b	90	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	91	#define __FPU_USED 1U
AnnaBridge	165:d1b4690b3f8b	92	#else
AnnaBridge	165:d1b4690b3f8b	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	165:d1b4690b3f8b	94	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	95	#endif
AnnaBridge	165:d1b4690b3f8b	96	#else
AnnaBridge	165:d1b4690b3f8b	97	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	98	#endif
AnnaBridge	165:d1b4690b3f8b	99
AnnaBridge	165:d1b4690b3f8b	100	#elif defined ( __GNUC__ )
AnnaBridge	165:d1b4690b3f8b	101	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	165:d1b4690b3f8b	102	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	103	#define __FPU_USED 1U
AnnaBridge	165:d1b4690b3f8b	104	#else
AnnaBridge	165:d1b4690b3f8b	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	165:d1b4690b3f8b	106	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	107	#endif
AnnaBridge	165:d1b4690b3f8b	108	#else
AnnaBridge	165:d1b4690b3f8b	109	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	110	#endif
AnnaBridge	165:d1b4690b3f8b	111
AnnaBridge	165:d1b4690b3f8b	112	#elif defined ( __ICCARM__ )
AnnaBridge	165:d1b4690b3f8b	113	#if defined __ARMVFP__
AnnaBridge	165:d1b4690b3f8b	114	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	115	#define __FPU_USED 1U
AnnaBridge	165:d1b4690b3f8b	116	#else
AnnaBridge	165:d1b4690b3f8b	117	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	165:d1b4690b3f8b	118	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	119	#endif
AnnaBridge	165:d1b4690b3f8b	120	#else
AnnaBridge	165:d1b4690b3f8b	121	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	122	#endif
AnnaBridge	165:d1b4690b3f8b	123
AnnaBridge	165:d1b4690b3f8b	124	#elif defined ( __TI_ARM__ )
AnnaBridge	165:d1b4690b3f8b	125	#if defined __TI_VFP_SUPPORT__
AnnaBridge	165:d1b4690b3f8b	126	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	127	#define __FPU_USED 1U
AnnaBridge	165:d1b4690b3f8b	128	#else
AnnaBridge	165:d1b4690b3f8b	129	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	165:d1b4690b3f8b	130	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	131	#endif
AnnaBridge	165:d1b4690b3f8b	132	#else
AnnaBridge	165:d1b4690b3f8b	133	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	134	#endif
AnnaBridge	165:d1b4690b3f8b	135
AnnaBridge	165:d1b4690b3f8b	136	#elif defined ( __TASKING__ )
AnnaBridge	165:d1b4690b3f8b	137	#if defined __FPU_VFP__
AnnaBridge	165:d1b4690b3f8b	138	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	139	#define __FPU_USED 1U
AnnaBridge	165:d1b4690b3f8b	140	#else
AnnaBridge	165:d1b4690b3f8b	141	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	165:d1b4690b3f8b	142	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	143	#endif
AnnaBridge	165:d1b4690b3f8b	144	#else
AnnaBridge	165:d1b4690b3f8b	145	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	146	#endif
AnnaBridge	165:d1b4690b3f8b	147
AnnaBridge	165:d1b4690b3f8b	148	#elif defined ( __CSMC__ )
AnnaBridge	165:d1b4690b3f8b	149	#if ( __CSMC__ & 0x400U)
AnnaBridge	165:d1b4690b3f8b	150	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	151	#define __FPU_USED 1U
AnnaBridge	165:d1b4690b3f8b	152	#else
AnnaBridge	165:d1b4690b3f8b	153	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	165:d1b4690b3f8b	154	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	155	#endif
AnnaBridge	165:d1b4690b3f8b	156	#else
AnnaBridge	165:d1b4690b3f8b	157	#define __FPU_USED 0U
AnnaBridge	165:d1b4690b3f8b	158	#endif
AnnaBridge	165:d1b4690b3f8b	159
AnnaBridge	165:d1b4690b3f8b	160	#endif
AnnaBridge	165:d1b4690b3f8b	161
AnnaBridge	165:d1b4690b3f8b	162	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	165:d1b4690b3f8b	163
AnnaBridge	165:d1b4690b3f8b	164
AnnaBridge	165:d1b4690b3f8b	165	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	166	}
AnnaBridge	165:d1b4690b3f8b	167	#endif
AnnaBridge	165:d1b4690b3f8b	168
AnnaBridge	165:d1b4690b3f8b	169	#endif /* __CORE_CM4_H_GENERIC */
AnnaBridge	165:d1b4690b3f8b	170
AnnaBridge	165:d1b4690b3f8b	171	#ifndef __CMSIS_GENERIC
AnnaBridge	165:d1b4690b3f8b	172
AnnaBridge	165:d1b4690b3f8b	173	#ifndef __CORE_CM4_H_DEPENDANT
AnnaBridge	165:d1b4690b3f8b	174	#define __CORE_CM4_H_DEPENDANT
AnnaBridge	165:d1b4690b3f8b	175
AnnaBridge	165:d1b4690b3f8b	176	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	177	extern "C" {
AnnaBridge	165:d1b4690b3f8b	178	#endif
AnnaBridge	165:d1b4690b3f8b	179
AnnaBridge	165:d1b4690b3f8b	180	/* check device defines and use defaults */
AnnaBridge	165:d1b4690b3f8b	181	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	165:d1b4690b3f8b	182	#ifndef __CM4_REV
AnnaBridge	165:d1b4690b3f8b	183	#define __CM4_REV 0x0000U
AnnaBridge	165:d1b4690b3f8b	184	#warning "__CM4_REV not defined in device header file; using default!"
AnnaBridge	165:d1b4690b3f8b	185	#endif
AnnaBridge	165:d1b4690b3f8b	186
AnnaBridge	165:d1b4690b3f8b	187	#ifndef __FPU_PRESENT
AnnaBridge	165:d1b4690b3f8b	188	#define __FPU_PRESENT 0U
AnnaBridge	165:d1b4690b3f8b	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	165:d1b4690b3f8b	190	#endif
AnnaBridge	165:d1b4690b3f8b	191
AnnaBridge	165:d1b4690b3f8b	192	#ifndef __MPU_PRESENT
AnnaBridge	165:d1b4690b3f8b	193	#define __MPU_PRESENT 0U
AnnaBridge	165:d1b4690b3f8b	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	165:d1b4690b3f8b	195	#endif
AnnaBridge	165:d1b4690b3f8b	196
AnnaBridge	165:d1b4690b3f8b	197	#ifndef __NVIC_PRIO_BITS
AnnaBridge	165:d1b4690b3f8b	198	#define __NVIC_PRIO_BITS 3U
AnnaBridge	165:d1b4690b3f8b	199	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	165:d1b4690b3f8b	200	#endif
AnnaBridge	165:d1b4690b3f8b	201
AnnaBridge	165:d1b4690b3f8b	202	#ifndef __Vendor_SysTickConfig
AnnaBridge	165:d1b4690b3f8b	203	#define __Vendor_SysTickConfig 0U
AnnaBridge	165:d1b4690b3f8b	204	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	165:d1b4690b3f8b	205	#endif
AnnaBridge	165:d1b4690b3f8b	206	#endif
AnnaBridge	165:d1b4690b3f8b	207
AnnaBridge	165:d1b4690b3f8b	208	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	165:d1b4690b3f8b	209	/**
AnnaBridge	165:d1b4690b3f8b	210	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	165:d1b4690b3f8b	211
AnnaBridge	165:d1b4690b3f8b	212	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	165:d1b4690b3f8b	213	\li to specify the access to peripheral variables.
AnnaBridge	165:d1b4690b3f8b	214	\li for automatic generation of peripheral register debug information.
AnnaBridge	165:d1b4690b3f8b	215	*/
AnnaBridge	165:d1b4690b3f8b	216	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	217	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	165:d1b4690b3f8b	218	#else
AnnaBridge	165:d1b4690b3f8b	219	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	165:d1b4690b3f8b	220	#endif
AnnaBridge	165:d1b4690b3f8b	221	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	165:d1b4690b3f8b	222	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	165:d1b4690b3f8b	223
AnnaBridge	165:d1b4690b3f8b	224	/* following defines should be used for structure members */
AnnaBridge	165:d1b4690b3f8b	225	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	165:d1b4690b3f8b	226	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	165:d1b4690b3f8b	227	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	165:d1b4690b3f8b	228
AnnaBridge	165:d1b4690b3f8b	229	/@} end of group Cortex_M4 /
AnnaBridge	165:d1b4690b3f8b	230
AnnaBridge	165:d1b4690b3f8b	231
AnnaBridge	165:d1b4690b3f8b	232
AnnaBridge	165:d1b4690b3f8b	233	/*******************************************************************************
AnnaBridge	165:d1b4690b3f8b	234	* Register Abstraction
AnnaBridge	165:d1b4690b3f8b	235	Core Register contain:
AnnaBridge	165:d1b4690b3f8b	236	- Core Register
AnnaBridge	165:d1b4690b3f8b	237	- Core NVIC Register
AnnaBridge	165:d1b4690b3f8b	238	- Core SCB Register
AnnaBridge	165:d1b4690b3f8b	239	- Core SysTick Register
AnnaBridge	165:d1b4690b3f8b	240	- Core Debug Register
AnnaBridge	165:d1b4690b3f8b	241	- Core MPU Register
AnnaBridge	165:d1b4690b3f8b	242	- Core FPU Register
AnnaBridge	165:d1b4690b3f8b	243	******************************************************************************/
AnnaBridge	165:d1b4690b3f8b	244	/**
AnnaBridge	165:d1b4690b3f8b	245	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	165:d1b4690b3f8b	246	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	165:d1b4690b3f8b	247	*/
AnnaBridge	165:d1b4690b3f8b	248
AnnaBridge	165:d1b4690b3f8b	249	/**
AnnaBridge	165:d1b4690b3f8b	250	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	251	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	165:d1b4690b3f8b	252	\brief Core Register type definitions.
AnnaBridge	165:d1b4690b3f8b	253	@{
AnnaBridge	165:d1b4690b3f8b	254	*/
AnnaBridge	165:d1b4690b3f8b	255
AnnaBridge	165:d1b4690b3f8b	256	/**
AnnaBridge	165:d1b4690b3f8b	257	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	165:d1b4690b3f8b	258	*/
AnnaBridge	165:d1b4690b3f8b	259	typedef union
AnnaBridge	165:d1b4690b3f8b	260	{
AnnaBridge	165:d1b4690b3f8b	261	struct
AnnaBridge	165:d1b4690b3f8b	262	{
AnnaBridge	165:d1b4690b3f8b	263	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	165:d1b4690b3f8b	264	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	165:d1b4690b3f8b	265	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	165:d1b4690b3f8b	266	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	165:d1b4690b3f8b	267	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	165:d1b4690b3f8b	268	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	165:d1b4690b3f8b	269	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	165:d1b4690b3f8b	270	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	165:d1b4690b3f8b	271	} b; /!< Structure used for bit access /
AnnaBridge	165:d1b4690b3f8b	272	uint32_t w; /!< Type used for word access /
AnnaBridge	165:d1b4690b3f8b	273	} APSR_Type;
AnnaBridge	165:d1b4690b3f8b	274
AnnaBridge	165:d1b4690b3f8b	275	/* APSR Register Definitions */
AnnaBridge	165:d1b4690b3f8b	276	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	165:d1b4690b3f8b	277	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	165:d1b4690b3f8b	278
AnnaBridge	165:d1b4690b3f8b	279	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	165:d1b4690b3f8b	280	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	165:d1b4690b3f8b	281
AnnaBridge	165:d1b4690b3f8b	282	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	165:d1b4690b3f8b	283	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	165:d1b4690b3f8b	284
AnnaBridge	165:d1b4690b3f8b	285	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	165:d1b4690b3f8b	286	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	165:d1b4690b3f8b	287
AnnaBridge	165:d1b4690b3f8b	288	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	165:d1b4690b3f8b	289	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	165:d1b4690b3f8b	290
AnnaBridge	165:d1b4690b3f8b	291	#define APSR_GE_Pos 16U /!< APSR: GE Position /
AnnaBridge	165:d1b4690b3f8b	292	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	165:d1b4690b3f8b	293
AnnaBridge	165:d1b4690b3f8b	294
AnnaBridge	165:d1b4690b3f8b	295	/**
AnnaBridge	165:d1b4690b3f8b	296	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	165:d1b4690b3f8b	297	*/
AnnaBridge	165:d1b4690b3f8b	298	typedef union
AnnaBridge	165:d1b4690b3f8b	299	{
AnnaBridge	165:d1b4690b3f8b	300	struct
AnnaBridge	165:d1b4690b3f8b	301	{
AnnaBridge	165:d1b4690b3f8b	302	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	165:d1b4690b3f8b	303	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	165:d1b4690b3f8b	304	} b; /!< Structure used for bit access /
AnnaBridge	165:d1b4690b3f8b	305	uint32_t w; /!< Type used for word access /
AnnaBridge	165:d1b4690b3f8b	306	} IPSR_Type;
AnnaBridge	165:d1b4690b3f8b	307
AnnaBridge	165:d1b4690b3f8b	308	/* IPSR Register Definitions */
AnnaBridge	165:d1b4690b3f8b	309	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	165:d1b4690b3f8b	310	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	165:d1b4690b3f8b	311
AnnaBridge	165:d1b4690b3f8b	312
AnnaBridge	165:d1b4690b3f8b	313	/**
AnnaBridge	165:d1b4690b3f8b	314	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	165:d1b4690b3f8b	315	*/
AnnaBridge	165:d1b4690b3f8b	316	typedef union
AnnaBridge	165:d1b4690b3f8b	317	{
AnnaBridge	165:d1b4690b3f8b	318	struct
AnnaBridge	165:d1b4690b3f8b	319	{
AnnaBridge	165:d1b4690b3f8b	320	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	165:d1b4690b3f8b	321	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	165:d1b4690b3f8b	322	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	165:d1b4690b3f8b	323	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	165:d1b4690b3f8b	324	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	165:d1b4690b3f8b	325	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	165:d1b4690b3f8b	326	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	165:d1b4690b3f8b	327	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	165:d1b4690b3f8b	328	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	165:d1b4690b3f8b	329	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	165:d1b4690b3f8b	330	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	165:d1b4690b3f8b	331	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	165:d1b4690b3f8b	332	} b; /!< Structure used for bit access /
AnnaBridge	165:d1b4690b3f8b	333	uint32_t w; /!< Type used for word access /
AnnaBridge	165:d1b4690b3f8b	334	} xPSR_Type;
AnnaBridge	165:d1b4690b3f8b	335
AnnaBridge	165:d1b4690b3f8b	336	/* xPSR Register Definitions */
AnnaBridge	165:d1b4690b3f8b	337	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	165:d1b4690b3f8b	338	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	165:d1b4690b3f8b	339
AnnaBridge	165:d1b4690b3f8b	340	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	165:d1b4690b3f8b	341	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	165:d1b4690b3f8b	342
AnnaBridge	165:d1b4690b3f8b	343	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	165:d1b4690b3f8b	344	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	165:d1b4690b3f8b	345
AnnaBridge	165:d1b4690b3f8b	346	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	165:d1b4690b3f8b	347	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	165:d1b4690b3f8b	348
AnnaBridge	165:d1b4690b3f8b	349	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	165:d1b4690b3f8b	350	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	165:d1b4690b3f8b	351
AnnaBridge	165:d1b4690b3f8b	352	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	165:d1b4690b3f8b	353	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
AnnaBridge	165:d1b4690b3f8b	354
AnnaBridge	165:d1b4690b3f8b	355	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	165:d1b4690b3f8b	356	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	165:d1b4690b3f8b	357
AnnaBridge	165:d1b4690b3f8b	358	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
AnnaBridge	165:d1b4690b3f8b	359	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	165:d1b4690b3f8b	360
AnnaBridge	165:d1b4690b3f8b	361	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	165:d1b4690b3f8b	362	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	165:d1b4690b3f8b	363
AnnaBridge	165:d1b4690b3f8b	364	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	165:d1b4690b3f8b	365	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	165:d1b4690b3f8b	366
AnnaBridge	165:d1b4690b3f8b	367
AnnaBridge	165:d1b4690b3f8b	368	/**
AnnaBridge	165:d1b4690b3f8b	369	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	165:d1b4690b3f8b	370	*/
AnnaBridge	165:d1b4690b3f8b	371	typedef union
AnnaBridge	165:d1b4690b3f8b	372	{
AnnaBridge	165:d1b4690b3f8b	373	struct
AnnaBridge	165:d1b4690b3f8b	374	{
AnnaBridge	165:d1b4690b3f8b	375	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	165:d1b4690b3f8b	376	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	165:d1b4690b3f8b	377	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
AnnaBridge	165:d1b4690b3f8b	378	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
AnnaBridge	165:d1b4690b3f8b	379	} b; /!< Structure used for bit access /
AnnaBridge	165:d1b4690b3f8b	380	uint32_t w; /!< Type used for word access /
AnnaBridge	165:d1b4690b3f8b	381	} CONTROL_Type;
AnnaBridge	165:d1b4690b3f8b	382
AnnaBridge	165:d1b4690b3f8b	383	/* CONTROL Register Definitions */
AnnaBridge	165:d1b4690b3f8b	384	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
AnnaBridge	165:d1b4690b3f8b	385	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	165:d1b4690b3f8b	386
AnnaBridge	165:d1b4690b3f8b	387	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	165:d1b4690b3f8b	388	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	165:d1b4690b3f8b	389
AnnaBridge	165:d1b4690b3f8b	390	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	165:d1b4690b3f8b	391	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	165:d1b4690b3f8b	392
AnnaBridge	165:d1b4690b3f8b	393	/@} end of group CMSIS_CORE /
AnnaBridge	165:d1b4690b3f8b	394
AnnaBridge	165:d1b4690b3f8b	395
AnnaBridge	165:d1b4690b3f8b	396	/**
AnnaBridge	165:d1b4690b3f8b	397	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	398	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	165:d1b4690b3f8b	399	\brief Type definitions for the NVIC Registers
AnnaBridge	165:d1b4690b3f8b	400	@{
AnnaBridge	165:d1b4690b3f8b	401	*/
AnnaBridge	165:d1b4690b3f8b	402
AnnaBridge	165:d1b4690b3f8b	403	/**
AnnaBridge	165:d1b4690b3f8b	404	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	165:d1b4690b3f8b	405	*/
AnnaBridge	165:d1b4690b3f8b	406	typedef struct
AnnaBridge	165:d1b4690b3f8b	407	{
AnnaBridge	165:d1b4690b3f8b	408	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	165:d1b4690b3f8b	409	uint32_t RESERVED0[24U];
AnnaBridge	165:d1b4690b3f8b	410	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	165:d1b4690b3f8b	411	uint32_t RSERVED1[24U];
AnnaBridge	165:d1b4690b3f8b	412	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	165:d1b4690b3f8b	413	uint32_t RESERVED2[24U];
AnnaBridge	165:d1b4690b3f8b	414	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	165:d1b4690b3f8b	415	uint32_t RESERVED3[24U];
AnnaBridge	165:d1b4690b3f8b	416	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	165:d1b4690b3f8b	417	uint32_t RESERVED4[56U];
AnnaBridge	165:d1b4690b3f8b	418	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	165:d1b4690b3f8b	419	uint32_t RESERVED5[644U];
AnnaBridge	165:d1b4690b3f8b	420	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	165:d1b4690b3f8b	421	} NVIC_Type;
AnnaBridge	165:d1b4690b3f8b	422
AnnaBridge	165:d1b4690b3f8b	423	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	165:d1b4690b3f8b	424	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	165:d1b4690b3f8b	425	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	165:d1b4690b3f8b	426
AnnaBridge	165:d1b4690b3f8b	427	/@} end of group CMSIS_NVIC /
AnnaBridge	165:d1b4690b3f8b	428
AnnaBridge	165:d1b4690b3f8b	429
AnnaBridge	165:d1b4690b3f8b	430	/**
AnnaBridge	165:d1b4690b3f8b	431	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	432	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	165:d1b4690b3f8b	433	\brief Type definitions for the System Control Block Registers
AnnaBridge	165:d1b4690b3f8b	434	@{
AnnaBridge	165:d1b4690b3f8b	435	*/
AnnaBridge	165:d1b4690b3f8b	436
AnnaBridge	165:d1b4690b3f8b	437	/**
AnnaBridge	165:d1b4690b3f8b	438	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	165:d1b4690b3f8b	439	*/
AnnaBridge	165:d1b4690b3f8b	440	typedef struct
AnnaBridge	165:d1b4690b3f8b	441	{
AnnaBridge	165:d1b4690b3f8b	442	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	165:d1b4690b3f8b	443	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	165:d1b4690b3f8b	444	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	165:d1b4690b3f8b	445	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	165:d1b4690b3f8b	446	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	165:d1b4690b3f8b	447	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	165:d1b4690b3f8b	448	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	165:d1b4690b3f8b	449	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	165:d1b4690b3f8b	450	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	165:d1b4690b3f8b	451	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	165:d1b4690b3f8b	452	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	165:d1b4690b3f8b	453	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	165:d1b4690b3f8b	454	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	165:d1b4690b3f8b	455	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	165:d1b4690b3f8b	456	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	165:d1b4690b3f8b	457	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	165:d1b4690b3f8b	458	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	165:d1b4690b3f8b	459	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	165:d1b4690b3f8b	460	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	165:d1b4690b3f8b	461	uint32_t RESERVED0[5U];
AnnaBridge	165:d1b4690b3f8b	462	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	165:d1b4690b3f8b	463	} SCB_Type;
AnnaBridge	165:d1b4690b3f8b	464
AnnaBridge	165:d1b4690b3f8b	465	/* SCB CPUID Register Definitions */
AnnaBridge	165:d1b4690b3f8b	466	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	165:d1b4690b3f8b	467	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	165:d1b4690b3f8b	468
AnnaBridge	165:d1b4690b3f8b	469	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	165:d1b4690b3f8b	470	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	165:d1b4690b3f8b	471
AnnaBridge	165:d1b4690b3f8b	472	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	165:d1b4690b3f8b	473	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	165:d1b4690b3f8b	474
AnnaBridge	165:d1b4690b3f8b	475	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	165:d1b4690b3f8b	476	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	165:d1b4690b3f8b	477
AnnaBridge	165:d1b4690b3f8b	478	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	165:d1b4690b3f8b	479	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	165:d1b4690b3f8b	480
AnnaBridge	165:d1b4690b3f8b	481	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	165:d1b4690b3f8b	482	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
AnnaBridge	165:d1b4690b3f8b	483	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
AnnaBridge	165:d1b4690b3f8b	484
AnnaBridge	165:d1b4690b3f8b	485	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	165:d1b4690b3f8b	486	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	165:d1b4690b3f8b	487
AnnaBridge	165:d1b4690b3f8b	488	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	165:d1b4690b3f8b	489	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	165:d1b4690b3f8b	490
AnnaBridge	165:d1b4690b3f8b	491	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	165:d1b4690b3f8b	492	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	165:d1b4690b3f8b	493
AnnaBridge	165:d1b4690b3f8b	494	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	165:d1b4690b3f8b	495	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	165:d1b4690b3f8b	496
AnnaBridge	165:d1b4690b3f8b	497	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	165:d1b4690b3f8b	498	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	165:d1b4690b3f8b	499
AnnaBridge	165:d1b4690b3f8b	500	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	165:d1b4690b3f8b	501	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	165:d1b4690b3f8b	502
AnnaBridge	165:d1b4690b3f8b	503	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	165:d1b4690b3f8b	504	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	165:d1b4690b3f8b	505
AnnaBridge	165:d1b4690b3f8b	506	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	165:d1b4690b3f8b	507	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	165:d1b4690b3f8b	508
AnnaBridge	165:d1b4690b3f8b	509	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	165:d1b4690b3f8b	510	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	165:d1b4690b3f8b	511
AnnaBridge	165:d1b4690b3f8b	512	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	165:d1b4690b3f8b	513	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	165:d1b4690b3f8b	514	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	165:d1b4690b3f8b	515
AnnaBridge	165:d1b4690b3f8b	516	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	517	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	165:d1b4690b3f8b	518	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	165:d1b4690b3f8b	519
AnnaBridge	165:d1b4690b3f8b	520	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	165:d1b4690b3f8b	521	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	165:d1b4690b3f8b	522
AnnaBridge	165:d1b4690b3f8b	523	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	165:d1b4690b3f8b	524	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	165:d1b4690b3f8b	525
AnnaBridge	165:d1b4690b3f8b	526	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	165:d1b4690b3f8b	527	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	165:d1b4690b3f8b	528
AnnaBridge	165:d1b4690b3f8b	529	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	165:d1b4690b3f8b	530	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	165:d1b4690b3f8b	531
AnnaBridge	165:d1b4690b3f8b	532	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	165:d1b4690b3f8b	533	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	165:d1b4690b3f8b	534
AnnaBridge	165:d1b4690b3f8b	535	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
AnnaBridge	165:d1b4690b3f8b	536	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
AnnaBridge	165:d1b4690b3f8b	537
AnnaBridge	165:d1b4690b3f8b	538	/* SCB System Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	539	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	165:d1b4690b3f8b	540	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	165:d1b4690b3f8b	541
AnnaBridge	165:d1b4690b3f8b	542	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	165:d1b4690b3f8b	543	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	165:d1b4690b3f8b	544
AnnaBridge	165:d1b4690b3f8b	545	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	165:d1b4690b3f8b	546	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	165:d1b4690b3f8b	547
AnnaBridge	165:d1b4690b3f8b	548	/* SCB Configuration Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	549	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
AnnaBridge	165:d1b4690b3f8b	550	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
AnnaBridge	165:d1b4690b3f8b	551
AnnaBridge	165:d1b4690b3f8b	552	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	165:d1b4690b3f8b	553	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	165:d1b4690b3f8b	554
AnnaBridge	165:d1b4690b3f8b	555	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	165:d1b4690b3f8b	556	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	165:d1b4690b3f8b	557
AnnaBridge	165:d1b4690b3f8b	558	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	165:d1b4690b3f8b	559	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	165:d1b4690b3f8b	560
AnnaBridge	165:d1b4690b3f8b	561	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	165:d1b4690b3f8b	562	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	165:d1b4690b3f8b	563
AnnaBridge	165:d1b4690b3f8b	564	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
AnnaBridge	165:d1b4690b3f8b	565	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
AnnaBridge	165:d1b4690b3f8b	566
AnnaBridge	165:d1b4690b3f8b	567	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	165:d1b4690b3f8b	568	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	165:d1b4690b3f8b	569	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	165:d1b4690b3f8b	570
AnnaBridge	165:d1b4690b3f8b	571	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	165:d1b4690b3f8b	572	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	165:d1b4690b3f8b	573
AnnaBridge	165:d1b4690b3f8b	574	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	165:d1b4690b3f8b	575	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	165:d1b4690b3f8b	576
AnnaBridge	165:d1b4690b3f8b	577	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	165:d1b4690b3f8b	578	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	165:d1b4690b3f8b	579
AnnaBridge	165:d1b4690b3f8b	580	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	165:d1b4690b3f8b	581	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	165:d1b4690b3f8b	582
AnnaBridge	165:d1b4690b3f8b	583	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	165:d1b4690b3f8b	584	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	165:d1b4690b3f8b	585
AnnaBridge	165:d1b4690b3f8b	586	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	165:d1b4690b3f8b	587	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	165:d1b4690b3f8b	588
AnnaBridge	165:d1b4690b3f8b	589	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	165:d1b4690b3f8b	590	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	165:d1b4690b3f8b	591
AnnaBridge	165:d1b4690b3f8b	592	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	165:d1b4690b3f8b	593	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	165:d1b4690b3f8b	594
AnnaBridge	165:d1b4690b3f8b	595	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	165:d1b4690b3f8b	596	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	165:d1b4690b3f8b	597
AnnaBridge	165:d1b4690b3f8b	598	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	165:d1b4690b3f8b	599	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	165:d1b4690b3f8b	600
AnnaBridge	165:d1b4690b3f8b	601	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	165:d1b4690b3f8b	602	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	165:d1b4690b3f8b	603
AnnaBridge	165:d1b4690b3f8b	604	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	165:d1b4690b3f8b	605	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	165:d1b4690b3f8b	606
AnnaBridge	165:d1b4690b3f8b	607	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	165:d1b4690b3f8b	608	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	165:d1b4690b3f8b	609
AnnaBridge	165:d1b4690b3f8b	610	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	165:d1b4690b3f8b	611	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	165:d1b4690b3f8b	612	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	165:d1b4690b3f8b	613
AnnaBridge	165:d1b4690b3f8b	614	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	165:d1b4690b3f8b	615	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	165:d1b4690b3f8b	616
AnnaBridge	165:d1b4690b3f8b	617	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	165:d1b4690b3f8b	618	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	165:d1b4690b3f8b	619
AnnaBridge	165:d1b4690b3f8b	620	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	165:d1b4690b3f8b	621	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	165:d1b4690b3f8b	622	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	165:d1b4690b3f8b	623
AnnaBridge	165:d1b4690b3f8b	624	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	165:d1b4690b3f8b	625	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	165:d1b4690b3f8b	626
AnnaBridge	165:d1b4690b3f8b	627	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	165:d1b4690b3f8b	628	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	165:d1b4690b3f8b	629
AnnaBridge	165:d1b4690b3f8b	630	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	165:d1b4690b3f8b	631	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	165:d1b4690b3f8b	632
AnnaBridge	165:d1b4690b3f8b	633	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	165:d1b4690b3f8b	634	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	165:d1b4690b3f8b	635
AnnaBridge	165:d1b4690b3f8b	636	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	165:d1b4690b3f8b	637	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	165:d1b4690b3f8b	638
AnnaBridge	165:d1b4690b3f8b	639	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	165:d1b4690b3f8b	640	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	165:d1b4690b3f8b	641	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	165:d1b4690b3f8b	642
AnnaBridge	165:d1b4690b3f8b	643	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	165:d1b4690b3f8b	644	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	165:d1b4690b3f8b	645
AnnaBridge	165:d1b4690b3f8b	646	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	165:d1b4690b3f8b	647	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	165:d1b4690b3f8b	648
AnnaBridge	165:d1b4690b3f8b	649	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	165:d1b4690b3f8b	650	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	165:d1b4690b3f8b	651
AnnaBridge	165:d1b4690b3f8b	652	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	165:d1b4690b3f8b	653	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	165:d1b4690b3f8b	654
AnnaBridge	165:d1b4690b3f8b	655	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	165:d1b4690b3f8b	656	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	165:d1b4690b3f8b	657
AnnaBridge	165:d1b4690b3f8b	658	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	165:d1b4690b3f8b	659	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	165:d1b4690b3f8b	660
AnnaBridge	165:d1b4690b3f8b	661	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	165:d1b4690b3f8b	662	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	165:d1b4690b3f8b	663	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	165:d1b4690b3f8b	664
AnnaBridge	165:d1b4690b3f8b	665	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	165:d1b4690b3f8b	666	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	165:d1b4690b3f8b	667
AnnaBridge	165:d1b4690b3f8b	668	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	165:d1b4690b3f8b	669	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	165:d1b4690b3f8b	670
AnnaBridge	165:d1b4690b3f8b	671	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	165:d1b4690b3f8b	672	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	165:d1b4690b3f8b	673
AnnaBridge	165:d1b4690b3f8b	674	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	165:d1b4690b3f8b	675	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	165:d1b4690b3f8b	676
AnnaBridge	165:d1b4690b3f8b	677	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	165:d1b4690b3f8b	678	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	165:d1b4690b3f8b	679
AnnaBridge	165:d1b4690b3f8b	680	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	165:d1b4690b3f8b	681	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	165:d1b4690b3f8b	682	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	165:d1b4690b3f8b	683
AnnaBridge	165:d1b4690b3f8b	684	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	165:d1b4690b3f8b	685	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	165:d1b4690b3f8b	686
AnnaBridge	165:d1b4690b3f8b	687	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	165:d1b4690b3f8b	688	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	165:d1b4690b3f8b	689
AnnaBridge	165:d1b4690b3f8b	690	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	165:d1b4690b3f8b	691	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	165:d1b4690b3f8b	692	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	165:d1b4690b3f8b	693
AnnaBridge	165:d1b4690b3f8b	694	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	165:d1b4690b3f8b	695	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	165:d1b4690b3f8b	696
AnnaBridge	165:d1b4690b3f8b	697	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	165:d1b4690b3f8b	698	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	165:d1b4690b3f8b	699
AnnaBridge	165:d1b4690b3f8b	700	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	165:d1b4690b3f8b	701	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	165:d1b4690b3f8b	702
AnnaBridge	165:d1b4690b3f8b	703	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	165:d1b4690b3f8b	704	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	165:d1b4690b3f8b	705
AnnaBridge	165:d1b4690b3f8b	706	/@} end of group CMSIS_SCB /
AnnaBridge	165:d1b4690b3f8b	707
AnnaBridge	165:d1b4690b3f8b	708
AnnaBridge	165:d1b4690b3f8b	709	/**
AnnaBridge	165:d1b4690b3f8b	710	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	711	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	165:d1b4690b3f8b	712	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	165:d1b4690b3f8b	713	@{
AnnaBridge	165:d1b4690b3f8b	714	*/
AnnaBridge	165:d1b4690b3f8b	715
AnnaBridge	165:d1b4690b3f8b	716	/**
AnnaBridge	165:d1b4690b3f8b	717	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	165:d1b4690b3f8b	718	*/
AnnaBridge	165:d1b4690b3f8b	719	typedef struct
AnnaBridge	165:d1b4690b3f8b	720	{
AnnaBridge	165:d1b4690b3f8b	721	uint32_t RESERVED0[1U];
AnnaBridge	165:d1b4690b3f8b	722	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	165:d1b4690b3f8b	723	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	165:d1b4690b3f8b	724	} SCnSCB_Type;
AnnaBridge	165:d1b4690b3f8b	725
AnnaBridge	165:d1b4690b3f8b	726	/* Interrupt Controller Type Register Definitions */
AnnaBridge	165:d1b4690b3f8b	727	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	165:d1b4690b3f8b	728	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	165:d1b4690b3f8b	729
AnnaBridge	165:d1b4690b3f8b	730	/* Auxiliary Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	731	#define SCnSCB_ACTLR_DISOOFP_Pos 9U /!< ACTLR: DISOOFP Position /
AnnaBridge	165:d1b4690b3f8b	732	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
AnnaBridge	165:d1b4690b3f8b	733
AnnaBridge	165:d1b4690b3f8b	734	#define SCnSCB_ACTLR_DISFPCA_Pos 8U /!< ACTLR: DISFPCA Position /
AnnaBridge	165:d1b4690b3f8b	735	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
AnnaBridge	165:d1b4690b3f8b	736
AnnaBridge	165:d1b4690b3f8b	737	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
AnnaBridge	165:d1b4690b3f8b	738	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
AnnaBridge	165:d1b4690b3f8b	739
AnnaBridge	165:d1b4690b3f8b	740	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
AnnaBridge	165:d1b4690b3f8b	741	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
AnnaBridge	165:d1b4690b3f8b	742
AnnaBridge	165:d1b4690b3f8b	743	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
AnnaBridge	165:d1b4690b3f8b	744	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	165:d1b4690b3f8b	745
AnnaBridge	165:d1b4690b3f8b	746	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	165:d1b4690b3f8b	747
AnnaBridge	165:d1b4690b3f8b	748
AnnaBridge	165:d1b4690b3f8b	749	/**
AnnaBridge	165:d1b4690b3f8b	750	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	751	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	165:d1b4690b3f8b	752	\brief Type definitions for the System Timer Registers.
AnnaBridge	165:d1b4690b3f8b	753	@{
AnnaBridge	165:d1b4690b3f8b	754	*/
AnnaBridge	165:d1b4690b3f8b	755
AnnaBridge	165:d1b4690b3f8b	756	/**
AnnaBridge	165:d1b4690b3f8b	757	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	165:d1b4690b3f8b	758	*/
AnnaBridge	165:d1b4690b3f8b	759	typedef struct
AnnaBridge	165:d1b4690b3f8b	760	{
AnnaBridge	165:d1b4690b3f8b	761	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	165:d1b4690b3f8b	762	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	165:d1b4690b3f8b	763	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	165:d1b4690b3f8b	764	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	165:d1b4690b3f8b	765	} SysTick_Type;
AnnaBridge	165:d1b4690b3f8b	766
AnnaBridge	165:d1b4690b3f8b	767	/* SysTick Control / Status Register Definitions */
AnnaBridge	165:d1b4690b3f8b	768	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	165:d1b4690b3f8b	769	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	165:d1b4690b3f8b	770
AnnaBridge	165:d1b4690b3f8b	771	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	165:d1b4690b3f8b	772	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	165:d1b4690b3f8b	773
AnnaBridge	165:d1b4690b3f8b	774	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	165:d1b4690b3f8b	775	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	165:d1b4690b3f8b	776
AnnaBridge	165:d1b4690b3f8b	777	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	165:d1b4690b3f8b	778	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	165:d1b4690b3f8b	779
AnnaBridge	165:d1b4690b3f8b	780	/* SysTick Reload Register Definitions */
AnnaBridge	165:d1b4690b3f8b	781	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	165:d1b4690b3f8b	782	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	165:d1b4690b3f8b	783
AnnaBridge	165:d1b4690b3f8b	784	/* SysTick Current Register Definitions */
AnnaBridge	165:d1b4690b3f8b	785	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	165:d1b4690b3f8b	786	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	165:d1b4690b3f8b	787
AnnaBridge	165:d1b4690b3f8b	788	/* SysTick Calibration Register Definitions */
AnnaBridge	165:d1b4690b3f8b	789	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	165:d1b4690b3f8b	790	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	165:d1b4690b3f8b	791
AnnaBridge	165:d1b4690b3f8b	792	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	165:d1b4690b3f8b	793	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	165:d1b4690b3f8b	794
AnnaBridge	165:d1b4690b3f8b	795	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	165:d1b4690b3f8b	796	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	165:d1b4690b3f8b	797
AnnaBridge	165:d1b4690b3f8b	798	/@} end of group CMSIS_SysTick /
AnnaBridge	165:d1b4690b3f8b	799
AnnaBridge	165:d1b4690b3f8b	800
AnnaBridge	165:d1b4690b3f8b	801	/**
AnnaBridge	165:d1b4690b3f8b	802	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	803	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	165:d1b4690b3f8b	804	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	165:d1b4690b3f8b	805	@{
AnnaBridge	165:d1b4690b3f8b	806	*/
AnnaBridge	165:d1b4690b3f8b	807
AnnaBridge	165:d1b4690b3f8b	808	/**
AnnaBridge	165:d1b4690b3f8b	809	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	165:d1b4690b3f8b	810	*/
AnnaBridge	165:d1b4690b3f8b	811	typedef struct
AnnaBridge	165:d1b4690b3f8b	812	{
AnnaBridge	165:d1b4690b3f8b	813	__OM union
AnnaBridge	165:d1b4690b3f8b	814	{
AnnaBridge	165:d1b4690b3f8b	815	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	165:d1b4690b3f8b	816	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	165:d1b4690b3f8b	817	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	165:d1b4690b3f8b	818	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	165:d1b4690b3f8b	819	uint32_t RESERVED0[864U];
AnnaBridge	165:d1b4690b3f8b	820	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	165:d1b4690b3f8b	821	uint32_t RESERVED1[15U];
AnnaBridge	165:d1b4690b3f8b	822	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	165:d1b4690b3f8b	823	uint32_t RESERVED2[15U];
AnnaBridge	165:d1b4690b3f8b	824	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	165:d1b4690b3f8b	825	uint32_t RESERVED3[29U];
AnnaBridge	165:d1b4690b3f8b	826	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	165:d1b4690b3f8b	827	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	165:d1b4690b3f8b	828	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	165:d1b4690b3f8b	829	uint32_t RESERVED4[43U];
AnnaBridge	165:d1b4690b3f8b	830	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	165:d1b4690b3f8b	831	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	165:d1b4690b3f8b	832	uint32_t RESERVED5[6U];
AnnaBridge	165:d1b4690b3f8b	833	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	165:d1b4690b3f8b	834	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	165:d1b4690b3f8b	835	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	165:d1b4690b3f8b	836	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	165:d1b4690b3f8b	837	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	165:d1b4690b3f8b	838	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	165:d1b4690b3f8b	839	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	165:d1b4690b3f8b	840	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	165:d1b4690b3f8b	841	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	165:d1b4690b3f8b	842	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	165:d1b4690b3f8b	843	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	165:d1b4690b3f8b	844	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	165:d1b4690b3f8b	845	} ITM_Type;
AnnaBridge	165:d1b4690b3f8b	846
AnnaBridge	165:d1b4690b3f8b	847	/* ITM Trace Privilege Register Definitions */
AnnaBridge	165:d1b4690b3f8b	848	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
AnnaBridge	165:d1b4690b3f8b	849	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	165:d1b4690b3f8b	850
AnnaBridge	165:d1b4690b3f8b	851	/* ITM Trace Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	852	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	165:d1b4690b3f8b	853	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	165:d1b4690b3f8b	854
AnnaBridge	165:d1b4690b3f8b	855	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	165:d1b4690b3f8b	856	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	165:d1b4690b3f8b	857
AnnaBridge	165:d1b4690b3f8b	858	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	165:d1b4690b3f8b	859	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	165:d1b4690b3f8b	860
AnnaBridge	165:d1b4690b3f8b	861	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
AnnaBridge	165:d1b4690b3f8b	862	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
AnnaBridge	165:d1b4690b3f8b	863
AnnaBridge	165:d1b4690b3f8b	864	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	165:d1b4690b3f8b	865	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	165:d1b4690b3f8b	866
AnnaBridge	165:d1b4690b3f8b	867	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	165:d1b4690b3f8b	868	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	165:d1b4690b3f8b	869
AnnaBridge	165:d1b4690b3f8b	870	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	165:d1b4690b3f8b	871	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	165:d1b4690b3f8b	872
AnnaBridge	165:d1b4690b3f8b	873	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	165:d1b4690b3f8b	874	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	165:d1b4690b3f8b	875
AnnaBridge	165:d1b4690b3f8b	876	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	165:d1b4690b3f8b	877	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	165:d1b4690b3f8b	878
AnnaBridge	165:d1b4690b3f8b	879	/* ITM Integration Write Register Definitions */
AnnaBridge	165:d1b4690b3f8b	880	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	165:d1b4690b3f8b	881	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	165:d1b4690b3f8b	882
AnnaBridge	165:d1b4690b3f8b	883	/* ITM Integration Read Register Definitions */
AnnaBridge	165:d1b4690b3f8b	884	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	165:d1b4690b3f8b	885	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	165:d1b4690b3f8b	886
AnnaBridge	165:d1b4690b3f8b	887	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	888	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	165:d1b4690b3f8b	889	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	165:d1b4690b3f8b	890
AnnaBridge	165:d1b4690b3f8b	891	/* ITM Lock Status Register Definitions */
AnnaBridge	165:d1b4690b3f8b	892	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	165:d1b4690b3f8b	893	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	165:d1b4690b3f8b	894
AnnaBridge	165:d1b4690b3f8b	895	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	165:d1b4690b3f8b	896	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	165:d1b4690b3f8b	897
AnnaBridge	165:d1b4690b3f8b	898	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	165:d1b4690b3f8b	899	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	165:d1b4690b3f8b	900
AnnaBridge	165:d1b4690b3f8b	901	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	165:d1b4690b3f8b	902
AnnaBridge	165:d1b4690b3f8b	903
AnnaBridge	165:d1b4690b3f8b	904	/**
AnnaBridge	165:d1b4690b3f8b	905	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	906	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	165:d1b4690b3f8b	907	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	165:d1b4690b3f8b	908	@{
AnnaBridge	165:d1b4690b3f8b	909	*/
AnnaBridge	165:d1b4690b3f8b	910
AnnaBridge	165:d1b4690b3f8b	911	/**
AnnaBridge	165:d1b4690b3f8b	912	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	165:d1b4690b3f8b	913	*/
AnnaBridge	165:d1b4690b3f8b	914	typedef struct
AnnaBridge	165:d1b4690b3f8b	915	{
AnnaBridge	165:d1b4690b3f8b	916	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	165:d1b4690b3f8b	917	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	165:d1b4690b3f8b	918	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	165:d1b4690b3f8b	919	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	165:d1b4690b3f8b	920	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	165:d1b4690b3f8b	921	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	165:d1b4690b3f8b	922	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	165:d1b4690b3f8b	923	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	165:d1b4690b3f8b	924	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	165:d1b4690b3f8b	925	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	165:d1b4690b3f8b	926	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	165:d1b4690b3f8b	927	uint32_t RESERVED0[1U];
AnnaBridge	165:d1b4690b3f8b	928	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	165:d1b4690b3f8b	929	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	165:d1b4690b3f8b	930	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	165:d1b4690b3f8b	931	uint32_t RESERVED1[1U];
AnnaBridge	165:d1b4690b3f8b	932	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	165:d1b4690b3f8b	933	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	165:d1b4690b3f8b	934	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	165:d1b4690b3f8b	935	uint32_t RESERVED2[1U];
AnnaBridge	165:d1b4690b3f8b	936	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	165:d1b4690b3f8b	937	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	165:d1b4690b3f8b	938	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	165:d1b4690b3f8b	939	} DWT_Type;
AnnaBridge	165:d1b4690b3f8b	940
AnnaBridge	165:d1b4690b3f8b	941	/* DWT Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	942	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	165:d1b4690b3f8b	943	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	165:d1b4690b3f8b	944
AnnaBridge	165:d1b4690b3f8b	945	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	165:d1b4690b3f8b	946	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	165:d1b4690b3f8b	947
AnnaBridge	165:d1b4690b3f8b	948	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	165:d1b4690b3f8b	949	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	165:d1b4690b3f8b	950
AnnaBridge	165:d1b4690b3f8b	951	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	165:d1b4690b3f8b	952	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	165:d1b4690b3f8b	953
AnnaBridge	165:d1b4690b3f8b	954	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	165:d1b4690b3f8b	955	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	165:d1b4690b3f8b	956
AnnaBridge	165:d1b4690b3f8b	957	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	165:d1b4690b3f8b	958	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	165:d1b4690b3f8b	959
AnnaBridge	165:d1b4690b3f8b	960	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	165:d1b4690b3f8b	961	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	165:d1b4690b3f8b	962
AnnaBridge	165:d1b4690b3f8b	963	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	165:d1b4690b3f8b	964	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	165:d1b4690b3f8b	965
AnnaBridge	165:d1b4690b3f8b	966	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	165:d1b4690b3f8b	967	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	165:d1b4690b3f8b	968
AnnaBridge	165:d1b4690b3f8b	969	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	165:d1b4690b3f8b	970	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	165:d1b4690b3f8b	971
AnnaBridge	165:d1b4690b3f8b	972	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	165:d1b4690b3f8b	973	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	165:d1b4690b3f8b	974
AnnaBridge	165:d1b4690b3f8b	975	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	165:d1b4690b3f8b	976	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	165:d1b4690b3f8b	977
AnnaBridge	165:d1b4690b3f8b	978	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	165:d1b4690b3f8b	979	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	165:d1b4690b3f8b	980
AnnaBridge	165:d1b4690b3f8b	981	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	165:d1b4690b3f8b	982	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	165:d1b4690b3f8b	983
AnnaBridge	165:d1b4690b3f8b	984	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	165:d1b4690b3f8b	985	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	165:d1b4690b3f8b	986
AnnaBridge	165:d1b4690b3f8b	987	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	165:d1b4690b3f8b	988	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	165:d1b4690b3f8b	989
AnnaBridge	165:d1b4690b3f8b	990	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	165:d1b4690b3f8b	991	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	165:d1b4690b3f8b	992
AnnaBridge	165:d1b4690b3f8b	993	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	165:d1b4690b3f8b	994	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	165:d1b4690b3f8b	995
AnnaBridge	165:d1b4690b3f8b	996	/* DWT CPI Count Register Definitions */
AnnaBridge	165:d1b4690b3f8b	997	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	165:d1b4690b3f8b	998	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	165:d1b4690b3f8b	999
AnnaBridge	165:d1b4690b3f8b	1000	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1001	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	165:d1b4690b3f8b	1002	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	165:d1b4690b3f8b	1003
AnnaBridge	165:d1b4690b3f8b	1004	/* DWT Sleep Count Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1005	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	165:d1b4690b3f8b	1006	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	165:d1b4690b3f8b	1007
AnnaBridge	165:d1b4690b3f8b	1008	/* DWT LSU Count Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1009	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	165:d1b4690b3f8b	1010	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	165:d1b4690b3f8b	1011
AnnaBridge	165:d1b4690b3f8b	1012	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1013	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	165:d1b4690b3f8b	1014	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	165:d1b4690b3f8b	1015
AnnaBridge	165:d1b4690b3f8b	1016	/* DWT Comparator Mask Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1017	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
AnnaBridge	165:d1b4690b3f8b	1018	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
AnnaBridge	165:d1b4690b3f8b	1019
AnnaBridge	165:d1b4690b3f8b	1020	/* DWT Comparator Function Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1021	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	165:d1b4690b3f8b	1022	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	165:d1b4690b3f8b	1023
AnnaBridge	165:d1b4690b3f8b	1024	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
AnnaBridge	165:d1b4690b3f8b	1025	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
AnnaBridge	165:d1b4690b3f8b	1026
AnnaBridge	165:d1b4690b3f8b	1027	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
AnnaBridge	165:d1b4690b3f8b	1028	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
AnnaBridge	165:d1b4690b3f8b	1029
AnnaBridge	165:d1b4690b3f8b	1030	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	165:d1b4690b3f8b	1031	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	165:d1b4690b3f8b	1032
AnnaBridge	165:d1b4690b3f8b	1033	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
AnnaBridge	165:d1b4690b3f8b	1034	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
AnnaBridge	165:d1b4690b3f8b	1035
AnnaBridge	165:d1b4690b3f8b	1036	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
AnnaBridge	165:d1b4690b3f8b	1037	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
AnnaBridge	165:d1b4690b3f8b	1038
AnnaBridge	165:d1b4690b3f8b	1039	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
AnnaBridge	165:d1b4690b3f8b	1040	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
AnnaBridge	165:d1b4690b3f8b	1041
AnnaBridge	165:d1b4690b3f8b	1042	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
AnnaBridge	165:d1b4690b3f8b	1043	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
AnnaBridge	165:d1b4690b3f8b	1044
AnnaBridge	165:d1b4690b3f8b	1045	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
AnnaBridge	165:d1b4690b3f8b	1046	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
AnnaBridge	165:d1b4690b3f8b	1047
AnnaBridge	165:d1b4690b3f8b	1048	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	165:d1b4690b3f8b	1049
AnnaBridge	165:d1b4690b3f8b	1050
AnnaBridge	165:d1b4690b3f8b	1051	/**
AnnaBridge	165:d1b4690b3f8b	1052	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	1053	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	165:d1b4690b3f8b	1054	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	165:d1b4690b3f8b	1055	@{
AnnaBridge	165:d1b4690b3f8b	1056	*/
AnnaBridge	165:d1b4690b3f8b	1057
AnnaBridge	165:d1b4690b3f8b	1058	/**
AnnaBridge	165:d1b4690b3f8b	1059	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	165:d1b4690b3f8b	1060	*/
AnnaBridge	165:d1b4690b3f8b	1061	typedef struct
AnnaBridge	165:d1b4690b3f8b	1062	{
AnnaBridge	165:d1b4690b3f8b	1063	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	165:d1b4690b3f8b	1064	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	165:d1b4690b3f8b	1065	uint32_t RESERVED0[2U];
AnnaBridge	165:d1b4690b3f8b	1066	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	165:d1b4690b3f8b	1067	uint32_t RESERVED1[55U];
AnnaBridge	165:d1b4690b3f8b	1068	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	165:d1b4690b3f8b	1069	uint32_t RESERVED2[131U];
AnnaBridge	165:d1b4690b3f8b	1070	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	165:d1b4690b3f8b	1071	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	165:d1b4690b3f8b	1072	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	165:d1b4690b3f8b	1073	uint32_t RESERVED3[759U];
AnnaBridge	165:d1b4690b3f8b	1074	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	165:d1b4690b3f8b	1075	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	165:d1b4690b3f8b	1076	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	165:d1b4690b3f8b	1077	uint32_t RESERVED4[1U];
AnnaBridge	165:d1b4690b3f8b	1078	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	165:d1b4690b3f8b	1079	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	165:d1b4690b3f8b	1080	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	165:d1b4690b3f8b	1081	uint32_t RESERVED5[39U];
AnnaBridge	165:d1b4690b3f8b	1082	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	165:d1b4690b3f8b	1083	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	165:d1b4690b3f8b	1084	uint32_t RESERVED7[8U];
AnnaBridge	165:d1b4690b3f8b	1085	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	165:d1b4690b3f8b	1086	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	165:d1b4690b3f8b	1087	} TPI_Type;
AnnaBridge	165:d1b4690b3f8b	1088
AnnaBridge	165:d1b4690b3f8b	1089	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1090	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	165:d1b4690b3f8b	1091	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	165:d1b4690b3f8b	1092
AnnaBridge	165:d1b4690b3f8b	1093	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1094	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	165:d1b4690b3f8b	1095	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	165:d1b4690b3f8b	1096
AnnaBridge	165:d1b4690b3f8b	1097	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1098	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	165:d1b4690b3f8b	1099	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	165:d1b4690b3f8b	1100
AnnaBridge	165:d1b4690b3f8b	1101	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	165:d1b4690b3f8b	1102	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	165:d1b4690b3f8b	1103
AnnaBridge	165:d1b4690b3f8b	1104	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	165:d1b4690b3f8b	1105	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	165:d1b4690b3f8b	1106
AnnaBridge	165:d1b4690b3f8b	1107	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	165:d1b4690b3f8b	1108	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	165:d1b4690b3f8b	1109
AnnaBridge	165:d1b4690b3f8b	1110	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1111	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	165:d1b4690b3f8b	1112	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	165:d1b4690b3f8b	1113
AnnaBridge	165:d1b4690b3f8b	1114	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	165:d1b4690b3f8b	1115	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	165:d1b4690b3f8b	1116
AnnaBridge	165:d1b4690b3f8b	1117	/* TPI TRIGGER Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1118	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	165:d1b4690b3f8b	1119	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	165:d1b4690b3f8b	1120
AnnaBridge	165:d1b4690b3f8b	1121	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	165:d1b4690b3f8b	1122	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	165:d1b4690b3f8b	1123	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	165:d1b4690b3f8b	1124
AnnaBridge	165:d1b4690b3f8b	1125	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	165:d1b4690b3f8b	1126	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	165:d1b4690b3f8b	1127
AnnaBridge	165:d1b4690b3f8b	1128	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	165:d1b4690b3f8b	1129	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	165:d1b4690b3f8b	1130
AnnaBridge	165:d1b4690b3f8b	1131	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	165:d1b4690b3f8b	1132	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	165:d1b4690b3f8b	1133
AnnaBridge	165:d1b4690b3f8b	1134	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	165:d1b4690b3f8b	1135	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	165:d1b4690b3f8b	1136
AnnaBridge	165:d1b4690b3f8b	1137	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	165:d1b4690b3f8b	1138	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	165:d1b4690b3f8b	1139
AnnaBridge	165:d1b4690b3f8b	1140	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	165:d1b4690b3f8b	1141	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	165:d1b4690b3f8b	1142
AnnaBridge	165:d1b4690b3f8b	1143	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1144	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	165:d1b4690b3f8b	1145	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	165:d1b4690b3f8b	1146
AnnaBridge	165:d1b4690b3f8b	1147	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	165:d1b4690b3f8b	1148	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	165:d1b4690b3f8b	1149	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	165:d1b4690b3f8b	1150
AnnaBridge	165:d1b4690b3f8b	1151	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	165:d1b4690b3f8b	1152	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	165:d1b4690b3f8b	1153
AnnaBridge	165:d1b4690b3f8b	1154	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	165:d1b4690b3f8b	1155	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	165:d1b4690b3f8b	1156
AnnaBridge	165:d1b4690b3f8b	1157	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	165:d1b4690b3f8b	1158	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	165:d1b4690b3f8b	1159
AnnaBridge	165:d1b4690b3f8b	1160	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	165:d1b4690b3f8b	1161	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	165:d1b4690b3f8b	1162
AnnaBridge	165:d1b4690b3f8b	1163	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	165:d1b4690b3f8b	1164	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	165:d1b4690b3f8b	1165
AnnaBridge	165:d1b4690b3f8b	1166	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	165:d1b4690b3f8b	1167	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	165:d1b4690b3f8b	1168
AnnaBridge	165:d1b4690b3f8b	1169	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1170	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	165:d1b4690b3f8b	1171	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	165:d1b4690b3f8b	1172
AnnaBridge	165:d1b4690b3f8b	1173	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1174	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	165:d1b4690b3f8b	1175	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	165:d1b4690b3f8b	1176
AnnaBridge	165:d1b4690b3f8b	1177	/* TPI DEVID Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1178	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	165:d1b4690b3f8b	1179	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	165:d1b4690b3f8b	1180
AnnaBridge	165:d1b4690b3f8b	1181	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	165:d1b4690b3f8b	1182	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	165:d1b4690b3f8b	1183
AnnaBridge	165:d1b4690b3f8b	1184	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	165:d1b4690b3f8b	1185	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	165:d1b4690b3f8b	1186
AnnaBridge	165:d1b4690b3f8b	1187	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	165:d1b4690b3f8b	1188	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	165:d1b4690b3f8b	1189
AnnaBridge	165:d1b4690b3f8b	1190	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	165:d1b4690b3f8b	1191	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	165:d1b4690b3f8b	1192
AnnaBridge	165:d1b4690b3f8b	1193	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	165:d1b4690b3f8b	1194	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	165:d1b4690b3f8b	1195
AnnaBridge	165:d1b4690b3f8b	1196	/* TPI DEVTYPE Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1197	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	165:d1b4690b3f8b	1198	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	165:d1b4690b3f8b	1199
AnnaBridge	165:d1b4690b3f8b	1200	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	165:d1b4690b3f8b	1201	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	165:d1b4690b3f8b	1202
AnnaBridge	165:d1b4690b3f8b	1203	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	165:d1b4690b3f8b	1204
AnnaBridge	165:d1b4690b3f8b	1205
AnnaBridge	165:d1b4690b3f8b	1206	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	1207	/**
AnnaBridge	165:d1b4690b3f8b	1208	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	1209	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	165:d1b4690b3f8b	1210	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	165:d1b4690b3f8b	1211	@{
AnnaBridge	165:d1b4690b3f8b	1212	*/
AnnaBridge	165:d1b4690b3f8b	1213
AnnaBridge	165:d1b4690b3f8b	1214	/**
AnnaBridge	165:d1b4690b3f8b	1215	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	165:d1b4690b3f8b	1216	*/
AnnaBridge	165:d1b4690b3f8b	1217	typedef struct
AnnaBridge	165:d1b4690b3f8b	1218	{
AnnaBridge	165:d1b4690b3f8b	1219	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	165:d1b4690b3f8b	1220	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	165:d1b4690b3f8b	1221	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	165:d1b4690b3f8b	1222	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	165:d1b4690b3f8b	1223	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	165:d1b4690b3f8b	1224	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	165:d1b4690b3f8b	1225	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	165:d1b4690b3f8b	1226	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	165:d1b4690b3f8b	1227	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	165:d1b4690b3f8b	1228	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	165:d1b4690b3f8b	1229	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
AnnaBridge	165:d1b4690b3f8b	1230	} MPU_Type;
AnnaBridge	165:d1b4690b3f8b	1231
AnnaBridge	165:d1b4690b3f8b	1232	#define MPU_TYPE_RALIASES 4U
AnnaBridge	165:d1b4690b3f8b	1233
AnnaBridge	165:d1b4690b3f8b	1234	/* MPU Type Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1235	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	165:d1b4690b3f8b	1236	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	165:d1b4690b3f8b	1237
AnnaBridge	165:d1b4690b3f8b	1238	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	165:d1b4690b3f8b	1239	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	165:d1b4690b3f8b	1240
AnnaBridge	165:d1b4690b3f8b	1241	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	165:d1b4690b3f8b	1242	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	165:d1b4690b3f8b	1243
AnnaBridge	165:d1b4690b3f8b	1244	/* MPU Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1245	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	165:d1b4690b3f8b	1246	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	165:d1b4690b3f8b	1247
AnnaBridge	165:d1b4690b3f8b	1248	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	165:d1b4690b3f8b	1249	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	165:d1b4690b3f8b	1250
AnnaBridge	165:d1b4690b3f8b	1251	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	165:d1b4690b3f8b	1252	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	165:d1b4690b3f8b	1253
AnnaBridge	165:d1b4690b3f8b	1254	/* MPU Region Number Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1255	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	165:d1b4690b3f8b	1256	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	165:d1b4690b3f8b	1257
AnnaBridge	165:d1b4690b3f8b	1258	/* MPU Region Base Address Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1259	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	165:d1b4690b3f8b	1260	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	165:d1b4690b3f8b	1261
AnnaBridge	165:d1b4690b3f8b	1262	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
AnnaBridge	165:d1b4690b3f8b	1263	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
AnnaBridge	165:d1b4690b3f8b	1264
AnnaBridge	165:d1b4690b3f8b	1265	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
AnnaBridge	165:d1b4690b3f8b	1266	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
AnnaBridge	165:d1b4690b3f8b	1267
AnnaBridge	165:d1b4690b3f8b	1268	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1269	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
AnnaBridge	165:d1b4690b3f8b	1270	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
AnnaBridge	165:d1b4690b3f8b	1271
AnnaBridge	165:d1b4690b3f8b	1272	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
AnnaBridge	165:d1b4690b3f8b	1273	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
AnnaBridge	165:d1b4690b3f8b	1274
AnnaBridge	165:d1b4690b3f8b	1275	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
AnnaBridge	165:d1b4690b3f8b	1276	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
AnnaBridge	165:d1b4690b3f8b	1277
AnnaBridge	165:d1b4690b3f8b	1278	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
AnnaBridge	165:d1b4690b3f8b	1279	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
AnnaBridge	165:d1b4690b3f8b	1280
AnnaBridge	165:d1b4690b3f8b	1281	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
AnnaBridge	165:d1b4690b3f8b	1282	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
AnnaBridge	165:d1b4690b3f8b	1283
AnnaBridge	165:d1b4690b3f8b	1284	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
AnnaBridge	165:d1b4690b3f8b	1285	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
AnnaBridge	165:d1b4690b3f8b	1286
AnnaBridge	165:d1b4690b3f8b	1287	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
AnnaBridge	165:d1b4690b3f8b	1288	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
AnnaBridge	165:d1b4690b3f8b	1289
AnnaBridge	165:d1b4690b3f8b	1290	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
AnnaBridge	165:d1b4690b3f8b	1291	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
AnnaBridge	165:d1b4690b3f8b	1292
AnnaBridge	165:d1b4690b3f8b	1293	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
AnnaBridge	165:d1b4690b3f8b	1294	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
AnnaBridge	165:d1b4690b3f8b	1295
AnnaBridge	165:d1b4690b3f8b	1296	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
AnnaBridge	165:d1b4690b3f8b	1297	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
AnnaBridge	165:d1b4690b3f8b	1298
AnnaBridge	165:d1b4690b3f8b	1299	/@} end of group CMSIS_MPU /
AnnaBridge	165:d1b4690b3f8b	1300	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
AnnaBridge	165:d1b4690b3f8b	1301
AnnaBridge	165:d1b4690b3f8b	1302
AnnaBridge	165:d1b4690b3f8b	1303	/**
AnnaBridge	165:d1b4690b3f8b	1304	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	1305	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	165:d1b4690b3f8b	1306	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	165:d1b4690b3f8b	1307	@{
AnnaBridge	165:d1b4690b3f8b	1308	*/
AnnaBridge	165:d1b4690b3f8b	1309
AnnaBridge	165:d1b4690b3f8b	1310	/**
AnnaBridge	165:d1b4690b3f8b	1311	\brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	165:d1b4690b3f8b	1312	*/
AnnaBridge	165:d1b4690b3f8b	1313	typedef struct
AnnaBridge	165:d1b4690b3f8b	1314	{
AnnaBridge	165:d1b4690b3f8b	1315	uint32_t RESERVED0[1U];
AnnaBridge	165:d1b4690b3f8b	1316	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	165:d1b4690b3f8b	1317	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	165:d1b4690b3f8b	1318	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	165:d1b4690b3f8b	1319	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	165:d1b4690b3f8b	1320	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	165:d1b4690b3f8b	1321	} FPU_Type;
AnnaBridge	165:d1b4690b3f8b	1322
AnnaBridge	165:d1b4690b3f8b	1323	/* Floating-Point Context Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1324	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
AnnaBridge	165:d1b4690b3f8b	1325	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	165:d1b4690b3f8b	1326
AnnaBridge	165:d1b4690b3f8b	1327	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
AnnaBridge	165:d1b4690b3f8b	1328	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	165:d1b4690b3f8b	1329
AnnaBridge	165:d1b4690b3f8b	1330	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
AnnaBridge	165:d1b4690b3f8b	1331	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	165:d1b4690b3f8b	1332
AnnaBridge	165:d1b4690b3f8b	1333	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
AnnaBridge	165:d1b4690b3f8b	1334	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	165:d1b4690b3f8b	1335
AnnaBridge	165:d1b4690b3f8b	1336	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
AnnaBridge	165:d1b4690b3f8b	1337	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	165:d1b4690b3f8b	1338
AnnaBridge	165:d1b4690b3f8b	1339	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
AnnaBridge	165:d1b4690b3f8b	1340	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	165:d1b4690b3f8b	1341
AnnaBridge	165:d1b4690b3f8b	1342	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
AnnaBridge	165:d1b4690b3f8b	1343	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	165:d1b4690b3f8b	1344
AnnaBridge	165:d1b4690b3f8b	1345	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
AnnaBridge	165:d1b4690b3f8b	1346	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	165:d1b4690b3f8b	1347
AnnaBridge	165:d1b4690b3f8b	1348	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	165:d1b4690b3f8b	1349	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	165:d1b4690b3f8b	1350
AnnaBridge	165:d1b4690b3f8b	1351	/* Floating-Point Context Address Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1352	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
AnnaBridge	165:d1b4690b3f8b	1353	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	165:d1b4690b3f8b	1354
AnnaBridge	165:d1b4690b3f8b	1355	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1356	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
AnnaBridge	165:d1b4690b3f8b	1357	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	165:d1b4690b3f8b	1358
AnnaBridge	165:d1b4690b3f8b	1359	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
AnnaBridge	165:d1b4690b3f8b	1360	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	165:d1b4690b3f8b	1361
AnnaBridge	165:d1b4690b3f8b	1362	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
AnnaBridge	165:d1b4690b3f8b	1363	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	165:d1b4690b3f8b	1364
AnnaBridge	165:d1b4690b3f8b	1365	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
AnnaBridge	165:d1b4690b3f8b	1366	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	165:d1b4690b3f8b	1367
AnnaBridge	165:d1b4690b3f8b	1368	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	165:d1b4690b3f8b	1369	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	165:d1b4690b3f8b	1370	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	165:d1b4690b3f8b	1371
AnnaBridge	165:d1b4690b3f8b	1372	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
AnnaBridge	165:d1b4690b3f8b	1373	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	165:d1b4690b3f8b	1374
AnnaBridge	165:d1b4690b3f8b	1375	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
AnnaBridge	165:d1b4690b3f8b	1376	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	165:d1b4690b3f8b	1377
AnnaBridge	165:d1b4690b3f8b	1378	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
AnnaBridge	165:d1b4690b3f8b	1379	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	165:d1b4690b3f8b	1380
AnnaBridge	165:d1b4690b3f8b	1381	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	165:d1b4690b3f8b	1382	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	165:d1b4690b3f8b	1383
AnnaBridge	165:d1b4690b3f8b	1384	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
AnnaBridge	165:d1b4690b3f8b	1385	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	165:d1b4690b3f8b	1386
AnnaBridge	165:d1b4690b3f8b	1387	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
AnnaBridge	165:d1b4690b3f8b	1388	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	165:d1b4690b3f8b	1389
AnnaBridge	165:d1b4690b3f8b	1390	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	165:d1b4690b3f8b	1391	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	165:d1b4690b3f8b	1392
AnnaBridge	165:d1b4690b3f8b	1393	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	165:d1b4690b3f8b	1394	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	165:d1b4690b3f8b	1395	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	165:d1b4690b3f8b	1396
AnnaBridge	165:d1b4690b3f8b	1397	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
AnnaBridge	165:d1b4690b3f8b	1398	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	165:d1b4690b3f8b	1399
AnnaBridge	165:d1b4690b3f8b	1400	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	165:d1b4690b3f8b	1401	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	165:d1b4690b3f8b	1402
AnnaBridge	165:d1b4690b3f8b	1403	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
AnnaBridge	165:d1b4690b3f8b	1404	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	165:d1b4690b3f8b	1405
AnnaBridge	165:d1b4690b3f8b	1406	/@} end of group CMSIS_FPU /
AnnaBridge	165:d1b4690b3f8b	1407
AnnaBridge	165:d1b4690b3f8b	1408
AnnaBridge	165:d1b4690b3f8b	1409	/**
AnnaBridge	165:d1b4690b3f8b	1410	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	1411	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	165:d1b4690b3f8b	1412	\brief Type definitions for the Core Debug Registers
AnnaBridge	165:d1b4690b3f8b	1413	@{
AnnaBridge	165:d1b4690b3f8b	1414	*/
AnnaBridge	165:d1b4690b3f8b	1415
AnnaBridge	165:d1b4690b3f8b	1416	/**
AnnaBridge	165:d1b4690b3f8b	1417	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	165:d1b4690b3f8b	1418	*/
AnnaBridge	165:d1b4690b3f8b	1419	typedef struct
AnnaBridge	165:d1b4690b3f8b	1420	{
AnnaBridge	165:d1b4690b3f8b	1421	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	165:d1b4690b3f8b	1422	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	165:d1b4690b3f8b	1423	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	165:d1b4690b3f8b	1424	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	165:d1b4690b3f8b	1425	} CoreDebug_Type;
AnnaBridge	165:d1b4690b3f8b	1426
AnnaBridge	165:d1b4690b3f8b	1427	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1428	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	165:d1b4690b3f8b	1429	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	165:d1b4690b3f8b	1430
AnnaBridge	165:d1b4690b3f8b	1431	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	165:d1b4690b3f8b	1432	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	165:d1b4690b3f8b	1433
AnnaBridge	165:d1b4690b3f8b	1434	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	165:d1b4690b3f8b	1435	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	165:d1b4690b3f8b	1436
AnnaBridge	165:d1b4690b3f8b	1437	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	165:d1b4690b3f8b	1438	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	165:d1b4690b3f8b	1439
AnnaBridge	165:d1b4690b3f8b	1440	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	165:d1b4690b3f8b	1441	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	165:d1b4690b3f8b	1442
AnnaBridge	165:d1b4690b3f8b	1443	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	165:d1b4690b3f8b	1444	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	165:d1b4690b3f8b	1445
AnnaBridge	165:d1b4690b3f8b	1446	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	165:d1b4690b3f8b	1447	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	165:d1b4690b3f8b	1448
AnnaBridge	165:d1b4690b3f8b	1449	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	165:d1b4690b3f8b	1450	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	165:d1b4690b3f8b	1451
AnnaBridge	165:d1b4690b3f8b	1452	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	165:d1b4690b3f8b	1453	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	165:d1b4690b3f8b	1454
AnnaBridge	165:d1b4690b3f8b	1455	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	165:d1b4690b3f8b	1456	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	165:d1b4690b3f8b	1457
AnnaBridge	165:d1b4690b3f8b	1458	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	165:d1b4690b3f8b	1459	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	165:d1b4690b3f8b	1460
AnnaBridge	165:d1b4690b3f8b	1461	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	165:d1b4690b3f8b	1462	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	165:d1b4690b3f8b	1463
AnnaBridge	165:d1b4690b3f8b	1464	/* Debug Core Register Selector Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1465	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	165:d1b4690b3f8b	1466	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	165:d1b4690b3f8b	1467
AnnaBridge	165:d1b4690b3f8b	1468	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	165:d1b4690b3f8b	1469	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	165:d1b4690b3f8b	1470
AnnaBridge	165:d1b4690b3f8b	1471	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	165:d1b4690b3f8b	1472	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	165:d1b4690b3f8b	1473	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	165:d1b4690b3f8b	1474
AnnaBridge	165:d1b4690b3f8b	1475	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	165:d1b4690b3f8b	1476	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	165:d1b4690b3f8b	1477
AnnaBridge	165:d1b4690b3f8b	1478	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	165:d1b4690b3f8b	1479	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	165:d1b4690b3f8b	1480
AnnaBridge	165:d1b4690b3f8b	1481	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	165:d1b4690b3f8b	1482	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	165:d1b4690b3f8b	1483
AnnaBridge	165:d1b4690b3f8b	1484	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	165:d1b4690b3f8b	1485	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	165:d1b4690b3f8b	1486
AnnaBridge	165:d1b4690b3f8b	1487	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	165:d1b4690b3f8b	1488	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	165:d1b4690b3f8b	1489
AnnaBridge	165:d1b4690b3f8b	1490	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	165:d1b4690b3f8b	1491	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	165:d1b4690b3f8b	1492
AnnaBridge	165:d1b4690b3f8b	1493	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	165:d1b4690b3f8b	1494	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	165:d1b4690b3f8b	1495
AnnaBridge	165:d1b4690b3f8b	1496	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	165:d1b4690b3f8b	1497	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	165:d1b4690b3f8b	1498
AnnaBridge	165:d1b4690b3f8b	1499	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	165:d1b4690b3f8b	1500	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	165:d1b4690b3f8b	1501
AnnaBridge	165:d1b4690b3f8b	1502	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	165:d1b4690b3f8b	1503	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	165:d1b4690b3f8b	1504
AnnaBridge	165:d1b4690b3f8b	1505	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	165:d1b4690b3f8b	1506	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	165:d1b4690b3f8b	1507
AnnaBridge	165:d1b4690b3f8b	1508	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	165:d1b4690b3f8b	1509	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	165:d1b4690b3f8b	1510
AnnaBridge	165:d1b4690b3f8b	1511	/@} end of group CMSIS_CoreDebug /
AnnaBridge	165:d1b4690b3f8b	1512
AnnaBridge	165:d1b4690b3f8b	1513
AnnaBridge	165:d1b4690b3f8b	1514	/**
AnnaBridge	165:d1b4690b3f8b	1515	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	1516	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	165:d1b4690b3f8b	1517	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	165:d1b4690b3f8b	1518	@{
AnnaBridge	165:d1b4690b3f8b	1519	*/
AnnaBridge	165:d1b4690b3f8b	1520
AnnaBridge	165:d1b4690b3f8b	1521	/**
AnnaBridge	165:d1b4690b3f8b	1522	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	165:d1b4690b3f8b	1523	\param[in] field Name of the register bit field.
AnnaBridge	165:d1b4690b3f8b	1524	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	165:d1b4690b3f8b	1525	\return Masked and shifted value.
AnnaBridge	165:d1b4690b3f8b	1526	*/
AnnaBridge	165:d1b4690b3f8b	1527	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	165:d1b4690b3f8b	1528
AnnaBridge	165:d1b4690b3f8b	1529	/**
AnnaBridge	165:d1b4690b3f8b	1530	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	165:d1b4690b3f8b	1531	\param[in] field Name of the register bit field.
AnnaBridge	165:d1b4690b3f8b	1532	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	165:d1b4690b3f8b	1533	\return Masked and shifted bit field value.
AnnaBridge	165:d1b4690b3f8b	1534	*/
AnnaBridge	165:d1b4690b3f8b	1535	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	165:d1b4690b3f8b	1536
AnnaBridge	165:d1b4690b3f8b	1537	/@} end of group CMSIS_core_bitfield /
AnnaBridge	165:d1b4690b3f8b	1538
AnnaBridge	165:d1b4690b3f8b	1539
AnnaBridge	165:d1b4690b3f8b	1540	/**
AnnaBridge	165:d1b4690b3f8b	1541	\ingroup CMSIS_core_register
AnnaBridge	165:d1b4690b3f8b	1542	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	165:d1b4690b3f8b	1543	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	165:d1b4690b3f8b	1544	@{
AnnaBridge	165:d1b4690b3f8b	1545	*/
AnnaBridge	165:d1b4690b3f8b	1546
AnnaBridge	165:d1b4690b3f8b	1547	/* Memory mapping of Core Hardware */
AnnaBridge	165:d1b4690b3f8b	1548	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	165:d1b4690b3f8b	1549	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	165:d1b4690b3f8b	1550	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	165:d1b4690b3f8b	1551	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	165:d1b4690b3f8b	1552	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	165:d1b4690b3f8b	1553	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	165:d1b4690b3f8b	1554	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	165:d1b4690b3f8b	1555	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	165:d1b4690b3f8b	1556
AnnaBridge	165:d1b4690b3f8b	1557	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	165:d1b4690b3f8b	1558	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	165:d1b4690b3f8b	1559	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	165:d1b4690b3f8b	1560	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	165:d1b4690b3f8b	1561	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	165:d1b4690b3f8b	1562	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	165:d1b4690b3f8b	1563	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	165:d1b4690b3f8b	1564	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	165:d1b4690b3f8b	1565
AnnaBridge	165:d1b4690b3f8b	1566	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	1567	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	165:d1b4690b3f8b	1568	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	165:d1b4690b3f8b	1569	#endif
AnnaBridge	165:d1b4690b3f8b	1570
AnnaBridge	165:d1b4690b3f8b	1571	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	165:d1b4690b3f8b	1572	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	165:d1b4690b3f8b	1573
AnnaBridge	165:d1b4690b3f8b	1574	/@} /
AnnaBridge	165:d1b4690b3f8b	1575
AnnaBridge	165:d1b4690b3f8b	1576
AnnaBridge	165:d1b4690b3f8b	1577
AnnaBridge	165:d1b4690b3f8b	1578	/*******************************************************************************
AnnaBridge	165:d1b4690b3f8b	1579	* Hardware Abstraction Layer
AnnaBridge	165:d1b4690b3f8b	1580	Core Function Interface contains:
AnnaBridge	165:d1b4690b3f8b	1581	- Core NVIC Functions
AnnaBridge	165:d1b4690b3f8b	1582	- Core SysTick Functions
AnnaBridge	165:d1b4690b3f8b	1583	- Core Debug Functions
AnnaBridge	165:d1b4690b3f8b	1584	- Core Register Access Functions
AnnaBridge	165:d1b4690b3f8b	1585	******************************************************************************/
AnnaBridge	165:d1b4690b3f8b	1586	/**
AnnaBridge	165:d1b4690b3f8b	1587	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	165:d1b4690b3f8b	1588	*/
AnnaBridge	165:d1b4690b3f8b	1589
AnnaBridge	165:d1b4690b3f8b	1590
AnnaBridge	165:d1b4690b3f8b	1591
AnnaBridge	165:d1b4690b3f8b	1592	/* ########################## NVIC functions #################################### */
AnnaBridge	165:d1b4690b3f8b	1593	/**
AnnaBridge	165:d1b4690b3f8b	1594	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	165:d1b4690b3f8b	1595	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	165:d1b4690b3f8b	1596	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	165:d1b4690b3f8b	1597	@{
AnnaBridge	165:d1b4690b3f8b	1598	*/
AnnaBridge	165:d1b4690b3f8b	1599
AnnaBridge	165:d1b4690b3f8b	1600	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	165:d1b4690b3f8b	1601	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	165:d1b4690b3f8b	1602	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	165:d1b4690b3f8b	1603	#endif
AnnaBridge	165:d1b4690b3f8b	1604	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	165:d1b4690b3f8b	1605	#else
AnnaBridge	165:d1b4690b3f8b	1606	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	165:d1b4690b3f8b	1607	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	165:d1b4690b3f8b	1608	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	165:d1b4690b3f8b	1609	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	165:d1b4690b3f8b	1610	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	165:d1b4690b3f8b	1611	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	165:d1b4690b3f8b	1612	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	165:d1b4690b3f8b	1613	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	165:d1b4690b3f8b	1614	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	165:d1b4690b3f8b	1615	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	165:d1b4690b3f8b	1616	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	165:d1b4690b3f8b	1617	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	165:d1b4690b3f8b	1618	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	165:d1b4690b3f8b	1619
AnnaBridge	165:d1b4690b3f8b	1620	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	165:d1b4690b3f8b	1621	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	165:d1b4690b3f8b	1622	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	165:d1b4690b3f8b	1623	#endif
AnnaBridge	165:d1b4690b3f8b	1624	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	165:d1b4690b3f8b	1625	#else
AnnaBridge	165:d1b4690b3f8b	1626	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	165:d1b4690b3f8b	1627	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	165:d1b4690b3f8b	1628	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	165:d1b4690b3f8b	1629
AnnaBridge	165:d1b4690b3f8b	1630	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	165:d1b4690b3f8b	1631
AnnaBridge	165:d1b4690b3f8b	1632
AnnaBridge	165:d1b4690b3f8b	1633
AnnaBridge	165:d1b4690b3f8b	1634	/**
AnnaBridge	165:d1b4690b3f8b	1635	\brief Set Priority Grouping
AnnaBridge	165:d1b4690b3f8b	1636	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	165:d1b4690b3f8b	1637	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	165:d1b4690b3f8b	1638	Only values from 0..7 are used.
AnnaBridge	165:d1b4690b3f8b	1639	In case of a conflict between priority grouping and available
AnnaBridge	165:d1b4690b3f8b	1640	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	165:d1b4690b3f8b	1641	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	165:d1b4690b3f8b	1642	*/
AnnaBridge	165:d1b4690b3f8b	1643	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	165:d1b4690b3f8b	1644	{
AnnaBridge	165:d1b4690b3f8b	1645	uint32_t reg_value;
AnnaBridge	165:d1b4690b3f8b	1646	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	165:d1b4690b3f8b	1647
AnnaBridge	165:d1b4690b3f8b	1648	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	165:d1b4690b3f8b	1649	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	165:d1b4690b3f8b	1650	reg_value = (reg_value \|
AnnaBridge	165:d1b4690b3f8b	1651	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	165:d1b4690b3f8b	1652	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge	165:d1b4690b3f8b	1653	SCB->AIRCR = reg_value;
AnnaBridge	165:d1b4690b3f8b	1654	}
AnnaBridge	165:d1b4690b3f8b	1655
AnnaBridge	165:d1b4690b3f8b	1656
AnnaBridge	165:d1b4690b3f8b	1657	/**
AnnaBridge	165:d1b4690b3f8b	1658	\brief Get Priority Grouping
AnnaBridge	165:d1b4690b3f8b	1659	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	165:d1b4690b3f8b	1660	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	165:d1b4690b3f8b	1661	*/
AnnaBridge	165:d1b4690b3f8b	1662	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	165:d1b4690b3f8b	1663	{
AnnaBridge	165:d1b4690b3f8b	1664	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	165:d1b4690b3f8b	1665	}
AnnaBridge	165:d1b4690b3f8b	1666
AnnaBridge	165:d1b4690b3f8b	1667
AnnaBridge	165:d1b4690b3f8b	1668	/**
AnnaBridge	165:d1b4690b3f8b	1669	\brief Enable Interrupt
AnnaBridge	165:d1b4690b3f8b	1670	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	165:d1b4690b3f8b	1671	\param [in] IRQn Device specific interrupt number.
AnnaBridge	165:d1b4690b3f8b	1672	\note IRQn must not be negative.
AnnaBridge	165:d1b4690b3f8b	1673	*/
AnnaBridge	165:d1b4690b3f8b	1674	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1675	{
AnnaBridge	165:d1b4690b3f8b	1676	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1677	{
AnnaBridge	165:d1b4690b3f8b	1678	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	165:d1b4690b3f8b	1679	}
AnnaBridge	165:d1b4690b3f8b	1680	}
AnnaBridge	165:d1b4690b3f8b	1681
AnnaBridge	165:d1b4690b3f8b	1682
AnnaBridge	165:d1b4690b3f8b	1683	/**
AnnaBridge	165:d1b4690b3f8b	1684	\brief Get Interrupt Enable status
AnnaBridge	165:d1b4690b3f8b	1685	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	165:d1b4690b3f8b	1686	\param [in] IRQn Device specific interrupt number.
AnnaBridge	165:d1b4690b3f8b	1687	\return 0 Interrupt is not enabled.
AnnaBridge	165:d1b4690b3f8b	1688	\return 1 Interrupt is enabled.
AnnaBridge	165:d1b4690b3f8b	1689	\note IRQn must not be negative.
AnnaBridge	165:d1b4690b3f8b	1690	*/
AnnaBridge	165:d1b4690b3f8b	1691	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1692	{
AnnaBridge	165:d1b4690b3f8b	1693	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1694	{
AnnaBridge	165:d1b4690b3f8b	1695	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	165:d1b4690b3f8b	1696	}
AnnaBridge	165:d1b4690b3f8b	1697	else
AnnaBridge	165:d1b4690b3f8b	1698	{
AnnaBridge	165:d1b4690b3f8b	1699	return(0U);
AnnaBridge	165:d1b4690b3f8b	1700	}
AnnaBridge	165:d1b4690b3f8b	1701	}
AnnaBridge	165:d1b4690b3f8b	1702
AnnaBridge	165:d1b4690b3f8b	1703
AnnaBridge	165:d1b4690b3f8b	1704	/**
AnnaBridge	165:d1b4690b3f8b	1705	\brief Disable Interrupt
AnnaBridge	165:d1b4690b3f8b	1706	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	165:d1b4690b3f8b	1707	\param [in] IRQn Device specific interrupt number.
AnnaBridge	165:d1b4690b3f8b	1708	\note IRQn must not be negative.
AnnaBridge	165:d1b4690b3f8b	1709	*/
AnnaBridge	165:d1b4690b3f8b	1710	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1711	{
AnnaBridge	165:d1b4690b3f8b	1712	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1713	{
AnnaBridge	165:d1b4690b3f8b	1714	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	165:d1b4690b3f8b	1715	__DSB();
AnnaBridge	165:d1b4690b3f8b	1716	__ISB();
AnnaBridge	165:d1b4690b3f8b	1717	}
AnnaBridge	165:d1b4690b3f8b	1718	}
AnnaBridge	165:d1b4690b3f8b	1719
AnnaBridge	165:d1b4690b3f8b	1720
AnnaBridge	165:d1b4690b3f8b	1721	/**
AnnaBridge	165:d1b4690b3f8b	1722	\brief Get Pending Interrupt
AnnaBridge	165:d1b4690b3f8b	1723	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	165:d1b4690b3f8b	1724	\param [in] IRQn Device specific interrupt number.
AnnaBridge	165:d1b4690b3f8b	1725	\return 0 Interrupt status is not pending.
AnnaBridge	165:d1b4690b3f8b	1726	\return 1 Interrupt status is pending.
AnnaBridge	165:d1b4690b3f8b	1727	\note IRQn must not be negative.
AnnaBridge	165:d1b4690b3f8b	1728	*/
AnnaBridge	165:d1b4690b3f8b	1729	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1730	{
AnnaBridge	165:d1b4690b3f8b	1731	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1732	{
AnnaBridge	165:d1b4690b3f8b	1733	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	165:d1b4690b3f8b	1734	}
AnnaBridge	165:d1b4690b3f8b	1735	else
AnnaBridge	165:d1b4690b3f8b	1736	{
AnnaBridge	165:d1b4690b3f8b	1737	return(0U);
AnnaBridge	165:d1b4690b3f8b	1738	}
AnnaBridge	165:d1b4690b3f8b	1739	}
AnnaBridge	165:d1b4690b3f8b	1740
AnnaBridge	165:d1b4690b3f8b	1741
AnnaBridge	165:d1b4690b3f8b	1742	/**
AnnaBridge	165:d1b4690b3f8b	1743	\brief Set Pending Interrupt
AnnaBridge	165:d1b4690b3f8b	1744	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	165:d1b4690b3f8b	1745	\param [in] IRQn Device specific interrupt number.
AnnaBridge	165:d1b4690b3f8b	1746	\note IRQn must not be negative.
AnnaBridge	165:d1b4690b3f8b	1747	*/
AnnaBridge	165:d1b4690b3f8b	1748	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1749	{
AnnaBridge	165:d1b4690b3f8b	1750	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1751	{
AnnaBridge	165:d1b4690b3f8b	1752	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	165:d1b4690b3f8b	1753	}
AnnaBridge	165:d1b4690b3f8b	1754	}
AnnaBridge	165:d1b4690b3f8b	1755
AnnaBridge	165:d1b4690b3f8b	1756
AnnaBridge	165:d1b4690b3f8b	1757	/**
AnnaBridge	165:d1b4690b3f8b	1758	\brief Clear Pending Interrupt
AnnaBridge	165:d1b4690b3f8b	1759	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	165:d1b4690b3f8b	1760	\param [in] IRQn Device specific interrupt number.
AnnaBridge	165:d1b4690b3f8b	1761	\note IRQn must not be negative.
AnnaBridge	165:d1b4690b3f8b	1762	*/
AnnaBridge	165:d1b4690b3f8b	1763	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1764	{
AnnaBridge	165:d1b4690b3f8b	1765	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1766	{
AnnaBridge	165:d1b4690b3f8b	1767	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	165:d1b4690b3f8b	1768	}
AnnaBridge	165:d1b4690b3f8b	1769	}
AnnaBridge	165:d1b4690b3f8b	1770
AnnaBridge	165:d1b4690b3f8b	1771
AnnaBridge	165:d1b4690b3f8b	1772	/**
AnnaBridge	165:d1b4690b3f8b	1773	\brief Get Active Interrupt
AnnaBridge	165:d1b4690b3f8b	1774	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	165:d1b4690b3f8b	1775	\param [in] IRQn Device specific interrupt number.
AnnaBridge	165:d1b4690b3f8b	1776	\return 0 Interrupt status is not active.
AnnaBridge	165:d1b4690b3f8b	1777	\return 1 Interrupt status is active.
AnnaBridge	165:d1b4690b3f8b	1778	\note IRQn must not be negative.
AnnaBridge	165:d1b4690b3f8b	1779	*/
AnnaBridge	165:d1b4690b3f8b	1780	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1781	{
AnnaBridge	165:d1b4690b3f8b	1782	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1783	{
AnnaBridge	165:d1b4690b3f8b	1784	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	165:d1b4690b3f8b	1785	}
AnnaBridge	165:d1b4690b3f8b	1786	else
AnnaBridge	165:d1b4690b3f8b	1787	{
AnnaBridge	165:d1b4690b3f8b	1788	return(0U);
AnnaBridge	165:d1b4690b3f8b	1789	}
AnnaBridge	165:d1b4690b3f8b	1790	}
AnnaBridge	165:d1b4690b3f8b	1791
AnnaBridge	165:d1b4690b3f8b	1792
AnnaBridge	165:d1b4690b3f8b	1793	/**
AnnaBridge	165:d1b4690b3f8b	1794	\brief Set Interrupt Priority
AnnaBridge	165:d1b4690b3f8b	1795	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	165:d1b4690b3f8b	1796	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	165:d1b4690b3f8b	1797	or negative to specify a processor exception.
AnnaBridge	165:d1b4690b3f8b	1798	\param [in] IRQn Interrupt number.
AnnaBridge	165:d1b4690b3f8b	1799	\param [in] priority Priority to set.
AnnaBridge	165:d1b4690b3f8b	1800	\note The priority cannot be set for every processor exception.
AnnaBridge	165:d1b4690b3f8b	1801	*/
AnnaBridge	165:d1b4690b3f8b	1802	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	165:d1b4690b3f8b	1803	{
AnnaBridge	165:d1b4690b3f8b	1804	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1805	{
AnnaBridge	165:d1b4690b3f8b	1806	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	165:d1b4690b3f8b	1807	}
AnnaBridge	165:d1b4690b3f8b	1808	else
AnnaBridge	165:d1b4690b3f8b	1809	{
AnnaBridge	165:d1b4690b3f8b	1810	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	165:d1b4690b3f8b	1811	}
AnnaBridge	165:d1b4690b3f8b	1812	}
AnnaBridge	165:d1b4690b3f8b	1813
AnnaBridge	165:d1b4690b3f8b	1814
AnnaBridge	165:d1b4690b3f8b	1815	/**
AnnaBridge	165:d1b4690b3f8b	1816	\brief Get Interrupt Priority
AnnaBridge	165:d1b4690b3f8b	1817	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	165:d1b4690b3f8b	1818	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	165:d1b4690b3f8b	1819	or negative to specify a processor exception.
AnnaBridge	165:d1b4690b3f8b	1820	\param [in] IRQn Interrupt number.
AnnaBridge	165:d1b4690b3f8b	1821	\return Interrupt Priority.
AnnaBridge	165:d1b4690b3f8b	1822	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	165:d1b4690b3f8b	1823	*/
AnnaBridge	165:d1b4690b3f8b	1824	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1825	{
AnnaBridge	165:d1b4690b3f8b	1826
AnnaBridge	165:d1b4690b3f8b	1827	if ((int32_t)(IRQn) >= 0)
AnnaBridge	165:d1b4690b3f8b	1828	{
AnnaBridge	165:d1b4690b3f8b	1829	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	165:d1b4690b3f8b	1830	}
AnnaBridge	165:d1b4690b3f8b	1831	else
AnnaBridge	165:d1b4690b3f8b	1832	{
AnnaBridge	165:d1b4690b3f8b	1833	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	165:d1b4690b3f8b	1834	}
AnnaBridge	165:d1b4690b3f8b	1835	}
AnnaBridge	165:d1b4690b3f8b	1836
AnnaBridge	165:d1b4690b3f8b	1837
AnnaBridge	165:d1b4690b3f8b	1838	/**
AnnaBridge	165:d1b4690b3f8b	1839	\brief Encode Priority
AnnaBridge	165:d1b4690b3f8b	1840	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	165:d1b4690b3f8b	1841	preemptive priority value, and subpriority value.
AnnaBridge	165:d1b4690b3f8b	1842	In case of a conflict between priority grouping and available
AnnaBridge	165:d1b4690b3f8b	1843	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	165:d1b4690b3f8b	1844	\param [in] PriorityGroup Used priority group.
AnnaBridge	165:d1b4690b3f8b	1845	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	165:d1b4690b3f8b	1846	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	165:d1b4690b3f8b	1847	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	165:d1b4690b3f8b	1848	*/
AnnaBridge	165:d1b4690b3f8b	1849	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	165:d1b4690b3f8b	1850	{
AnnaBridge	165:d1b4690b3f8b	1851	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	165:d1b4690b3f8b	1852	uint32_t PreemptPriorityBits;
AnnaBridge	165:d1b4690b3f8b	1853	uint32_t SubPriorityBits;
AnnaBridge	165:d1b4690b3f8b	1854
AnnaBridge	165:d1b4690b3f8b	1855	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	165:d1b4690b3f8b	1856	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	165:d1b4690b3f8b	1857
AnnaBridge	165:d1b4690b3f8b	1858	return (
AnnaBridge	165:d1b4690b3f8b	1859	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	165:d1b4690b3f8b	1860	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	165:d1b4690b3f8b	1861	);
AnnaBridge	165:d1b4690b3f8b	1862	}
AnnaBridge	165:d1b4690b3f8b	1863
AnnaBridge	165:d1b4690b3f8b	1864
AnnaBridge	165:d1b4690b3f8b	1865	/**
AnnaBridge	165:d1b4690b3f8b	1866	\brief Decode Priority
AnnaBridge	165:d1b4690b3f8b	1867	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	165:d1b4690b3f8b	1868	preemptive priority value and subpriority value.
AnnaBridge	165:d1b4690b3f8b	1869	In case of a conflict between priority grouping and available
AnnaBridge	165:d1b4690b3f8b	1870	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	165:d1b4690b3f8b	1871	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	165:d1b4690b3f8b	1872	\param [in] PriorityGroup Used priority group.
AnnaBridge	165:d1b4690b3f8b	1873	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	165:d1b4690b3f8b	1874	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	165:d1b4690b3f8b	1875	*/
AnnaBridge	165:d1b4690b3f8b	1876	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	165:d1b4690b3f8b	1877	{
AnnaBridge	165:d1b4690b3f8b	1878	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	165:d1b4690b3f8b	1879	uint32_t PreemptPriorityBits;
AnnaBridge	165:d1b4690b3f8b	1880	uint32_t SubPriorityBits;
AnnaBridge	165:d1b4690b3f8b	1881
AnnaBridge	165:d1b4690b3f8b	1882	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	165:d1b4690b3f8b	1883	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	165:d1b4690b3f8b	1884
AnnaBridge	165:d1b4690b3f8b	1885	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	165:d1b4690b3f8b	1886	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	165:d1b4690b3f8b	1887	}
AnnaBridge	165:d1b4690b3f8b	1888
AnnaBridge	165:d1b4690b3f8b	1889
AnnaBridge	165:d1b4690b3f8b	1890	/**
AnnaBridge	165:d1b4690b3f8b	1891	\brief Set Interrupt Vector
AnnaBridge	165:d1b4690b3f8b	1892	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	165:d1b4690b3f8b	1893	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	165:d1b4690b3f8b	1894	or negative to specify a processor exception.
AnnaBridge	165:d1b4690b3f8b	1895	VTOR must been relocated to SRAM before.
AnnaBridge	165:d1b4690b3f8b	1896	\param [in] IRQn Interrupt number
AnnaBridge	165:d1b4690b3f8b	1897	\param [in] vector Address of interrupt handler function
AnnaBridge	165:d1b4690b3f8b	1898	*/
AnnaBridge	165:d1b4690b3f8b	1899	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	165:d1b4690b3f8b	1900	{
AnnaBridge	165:d1b4690b3f8b	1901	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	165:d1b4690b3f8b	1902	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	165:d1b4690b3f8b	1903	}
AnnaBridge	165:d1b4690b3f8b	1904
AnnaBridge	165:d1b4690b3f8b	1905
AnnaBridge	165:d1b4690b3f8b	1906	/**
AnnaBridge	165:d1b4690b3f8b	1907	\brief Get Interrupt Vector
AnnaBridge	165:d1b4690b3f8b	1908	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	165:d1b4690b3f8b	1909	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	165:d1b4690b3f8b	1910	or negative to specify a processor exception.
AnnaBridge	165:d1b4690b3f8b	1911	\param [in] IRQn Interrupt number.
AnnaBridge	165:d1b4690b3f8b	1912	\return Address of interrupt handler function
AnnaBridge	165:d1b4690b3f8b	1913	*/
AnnaBridge	165:d1b4690b3f8b	1914	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	165:d1b4690b3f8b	1915	{
AnnaBridge	165:d1b4690b3f8b	1916	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	165:d1b4690b3f8b	1917	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	165:d1b4690b3f8b	1918	}
AnnaBridge	165:d1b4690b3f8b	1919
AnnaBridge	165:d1b4690b3f8b	1920
AnnaBridge	165:d1b4690b3f8b	1921	/**
AnnaBridge	165:d1b4690b3f8b	1922	\brief System Reset
AnnaBridge	165:d1b4690b3f8b	1923	\details Initiates a system reset request to reset the MCU.
AnnaBridge	165:d1b4690b3f8b	1924	*/
AnnaBridge	165:d1b4690b3f8b	1925	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	165:d1b4690b3f8b	1926	{
AnnaBridge	165:d1b4690b3f8b	1927	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	165:d1b4690b3f8b	1928	buffered write are completed before reset */
AnnaBridge	165:d1b4690b3f8b	1929	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	165:d1b4690b3f8b	1930	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	165:d1b4690b3f8b	1931	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	165:d1b4690b3f8b	1932	__DSB(); /* Ensure completion of memory access */
AnnaBridge	165:d1b4690b3f8b	1933
AnnaBridge	165:d1b4690b3f8b	1934	for(;;) /* wait until reset */
AnnaBridge	165:d1b4690b3f8b	1935	{
AnnaBridge	165:d1b4690b3f8b	1936	__NOP();
AnnaBridge	165:d1b4690b3f8b	1937	}
AnnaBridge	165:d1b4690b3f8b	1938	}
AnnaBridge	165:d1b4690b3f8b	1939
AnnaBridge	165:d1b4690b3f8b	1940	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	165:d1b4690b3f8b	1941
AnnaBridge	165:d1b4690b3f8b	1942	/* ########################## MPU functions #################################### */
AnnaBridge	165:d1b4690b3f8b	1943
AnnaBridge	165:d1b4690b3f8b	1944	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	165:d1b4690b3f8b	1945
AnnaBridge	165:d1b4690b3f8b	1946	#include "mpu_armv7.h"
AnnaBridge	165:d1b4690b3f8b	1947
AnnaBridge	165:d1b4690b3f8b	1948	#endif
AnnaBridge	165:d1b4690b3f8b	1949
AnnaBridge	165:d1b4690b3f8b	1950
AnnaBridge	165:d1b4690b3f8b	1951	/* ########################## FPU functions #################################### */
AnnaBridge	165:d1b4690b3f8b	1952	/**
AnnaBridge	165:d1b4690b3f8b	1953	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	165:d1b4690b3f8b	1954	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	165:d1b4690b3f8b	1955	\brief Function that provides FPU type.
AnnaBridge	165:d1b4690b3f8b	1956	@{
AnnaBridge	165:d1b4690b3f8b	1957	*/
AnnaBridge	165:d1b4690b3f8b	1958
AnnaBridge	165:d1b4690b3f8b	1959	/**
AnnaBridge	165:d1b4690b3f8b	1960	\brief get FPU type
AnnaBridge	165:d1b4690b3f8b	1961	\details returns the FPU type
AnnaBridge	165:d1b4690b3f8b	1962	\returns
AnnaBridge	165:d1b4690b3f8b	1963	- \b 0: No FPU
AnnaBridge	165:d1b4690b3f8b	1964	- \b 1: Single precision FPU
AnnaBridge	165:d1b4690b3f8b	1965	- \b 2: Double + Single precision FPU
AnnaBridge	165:d1b4690b3f8b	1966	*/
AnnaBridge	165:d1b4690b3f8b	1967	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	165:d1b4690b3f8b	1968	{
AnnaBridge	165:d1b4690b3f8b	1969	uint32_t mvfr0;
AnnaBridge	165:d1b4690b3f8b	1970
AnnaBridge	165:d1b4690b3f8b	1971	mvfr0 = FPU->MVFR0;
AnnaBridge	165:d1b4690b3f8b	1972	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	165:d1b4690b3f8b	1973	{
AnnaBridge	165:d1b4690b3f8b	1974	return 1U; /* Single precision FPU */
AnnaBridge	165:d1b4690b3f8b	1975	}
AnnaBridge	165:d1b4690b3f8b	1976	else
AnnaBridge	165:d1b4690b3f8b	1977	{
AnnaBridge	165:d1b4690b3f8b	1978	return 0U; /* No FPU */
AnnaBridge	165:d1b4690b3f8b	1979	}
AnnaBridge	165:d1b4690b3f8b	1980	}
AnnaBridge	165:d1b4690b3f8b	1981
AnnaBridge	165:d1b4690b3f8b	1982
AnnaBridge	165:d1b4690b3f8b	1983	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	165:d1b4690b3f8b	1984
AnnaBridge	165:d1b4690b3f8b	1985
AnnaBridge	165:d1b4690b3f8b	1986
AnnaBridge	165:d1b4690b3f8b	1987	/* ################################## SysTick function ############################################ */
AnnaBridge	165:d1b4690b3f8b	1988	/**
AnnaBridge	165:d1b4690b3f8b	1989	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	165:d1b4690b3f8b	1990	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	165:d1b4690b3f8b	1991	\brief Functions that configure the System.
AnnaBridge	165:d1b4690b3f8b	1992	@{
AnnaBridge	165:d1b4690b3f8b	1993	*/
AnnaBridge	165:d1b4690b3f8b	1994
AnnaBridge	165:d1b4690b3f8b	1995	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	165:d1b4690b3f8b	1996
AnnaBridge	165:d1b4690b3f8b	1997	/**
AnnaBridge	165:d1b4690b3f8b	1998	\brief System Tick Configuration
AnnaBridge	165:d1b4690b3f8b	1999	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	165:d1b4690b3f8b	2000	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	165:d1b4690b3f8b	2001	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	165:d1b4690b3f8b	2002	\return 0 Function succeeded.
AnnaBridge	165:d1b4690b3f8b	2003	\return 1 Function failed.
AnnaBridge	165:d1b4690b3f8b	2004	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	165:d1b4690b3f8b	2005	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	165:d1b4690b3f8b	2006	must contain a vendor-specific implementation of this function.
AnnaBridge	165:d1b4690b3f8b	2007	*/
AnnaBridge	165:d1b4690b3f8b	2008	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	165:d1b4690b3f8b	2009	{
AnnaBridge	165:d1b4690b3f8b	2010	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	165:d1b4690b3f8b	2011	{
AnnaBridge	165:d1b4690b3f8b	2012	return (1UL); /* Reload value impossible */
AnnaBridge	165:d1b4690b3f8b	2013	}
AnnaBridge	165:d1b4690b3f8b	2014
AnnaBridge	165:d1b4690b3f8b	2015	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	165:d1b4690b3f8b	2016	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	165:d1b4690b3f8b	2017	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	165:d1b4690b3f8b	2018	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	165:d1b4690b3f8b	2019	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	165:d1b4690b3f8b	2020	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	165:d1b4690b3f8b	2021	return (0UL); /* Function successful */
AnnaBridge	165:d1b4690b3f8b	2022	}
AnnaBridge	165:d1b4690b3f8b	2023
AnnaBridge	165:d1b4690b3f8b	2024	#endif
AnnaBridge	165:d1b4690b3f8b	2025
AnnaBridge	165:d1b4690b3f8b	2026	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	165:d1b4690b3f8b	2027
AnnaBridge	165:d1b4690b3f8b	2028
AnnaBridge	165:d1b4690b3f8b	2029
AnnaBridge	165:d1b4690b3f8b	2030	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	165:d1b4690b3f8b	2031	/**
AnnaBridge	165:d1b4690b3f8b	2032	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	165:d1b4690b3f8b	2033	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	165:d1b4690b3f8b	2034	\brief Functions that access the ITM debug interface.
AnnaBridge	165:d1b4690b3f8b	2035	@{
AnnaBridge	165:d1b4690b3f8b	2036	*/
AnnaBridge	165:d1b4690b3f8b	2037
AnnaBridge	165:d1b4690b3f8b	2038	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	165:d1b4690b3f8b	2039	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	165:d1b4690b3f8b	2040
AnnaBridge	165:d1b4690b3f8b	2041
AnnaBridge	165:d1b4690b3f8b	2042	/**
AnnaBridge	165:d1b4690b3f8b	2043	\brief ITM Send Character
AnnaBridge	165:d1b4690b3f8b	2044	\details Transmits a character via the ITM channel 0, and
AnnaBridge	165:d1b4690b3f8b	2045	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	165:d1b4690b3f8b	2046	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	165:d1b4690b3f8b	2047	\param [in] ch Character to transmit.
AnnaBridge	165:d1b4690b3f8b	2048	\returns Character to transmit.
AnnaBridge	165:d1b4690b3f8b	2049	*/
AnnaBridge	165:d1b4690b3f8b	2050	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	165:d1b4690b3f8b	2051	{
AnnaBridge	165:d1b4690b3f8b	2052	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	165:d1b4690b3f8b	2053	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	165:d1b4690b3f8b	2054	{
AnnaBridge	165:d1b4690b3f8b	2055	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	165:d1b4690b3f8b	2056	{
AnnaBridge	165:d1b4690b3f8b	2057	__NOP();
AnnaBridge	165:d1b4690b3f8b	2058	}
AnnaBridge	165:d1b4690b3f8b	2059	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	165:d1b4690b3f8b	2060	}
AnnaBridge	165:d1b4690b3f8b	2061	return (ch);
AnnaBridge	165:d1b4690b3f8b	2062	}
AnnaBridge	165:d1b4690b3f8b	2063
AnnaBridge	165:d1b4690b3f8b	2064
AnnaBridge	165:d1b4690b3f8b	2065	/**
AnnaBridge	165:d1b4690b3f8b	2066	\brief ITM Receive Character
AnnaBridge	165:d1b4690b3f8b	2067	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	165:d1b4690b3f8b	2068	\return Received character.
AnnaBridge	165:d1b4690b3f8b	2069	\return -1 No character pending.
AnnaBridge	165:d1b4690b3f8b	2070	*/
AnnaBridge	165:d1b4690b3f8b	2071	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	165:d1b4690b3f8b	2072	{
AnnaBridge	165:d1b4690b3f8b	2073	int32_t ch = -1; /* no character available */
AnnaBridge	165:d1b4690b3f8b	2074
AnnaBridge	165:d1b4690b3f8b	2075	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	165:d1b4690b3f8b	2076	{
AnnaBridge	165:d1b4690b3f8b	2077	ch = ITM_RxBuffer;
AnnaBridge	165:d1b4690b3f8b	2078	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	165:d1b4690b3f8b	2079	}
AnnaBridge	165:d1b4690b3f8b	2080
AnnaBridge	165:d1b4690b3f8b	2081	return (ch);
AnnaBridge	165:d1b4690b3f8b	2082	}
AnnaBridge	165:d1b4690b3f8b	2083
AnnaBridge	165:d1b4690b3f8b	2084
AnnaBridge	165:d1b4690b3f8b	2085	/**
AnnaBridge	165:d1b4690b3f8b	2086	\brief ITM Check Character
AnnaBridge	165:d1b4690b3f8b	2087	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	165:d1b4690b3f8b	2088	\return 0 No character available.
AnnaBridge	165:d1b4690b3f8b	2089	\return 1 Character available.
AnnaBridge	165:d1b4690b3f8b	2090	*/
AnnaBridge	165:d1b4690b3f8b	2091	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	165:d1b4690b3f8b	2092	{
AnnaBridge	165:d1b4690b3f8b	2093
AnnaBridge	165:d1b4690b3f8b	2094	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	165:d1b4690b3f8b	2095	{
AnnaBridge	165:d1b4690b3f8b	2096	return (0); /* no character available */
AnnaBridge	165:d1b4690b3f8b	2097	}
AnnaBridge	165:d1b4690b3f8b	2098	else
AnnaBridge	165:d1b4690b3f8b	2099	{
AnnaBridge	165:d1b4690b3f8b	2100	return (1); /* character available */
AnnaBridge	165:d1b4690b3f8b	2101	}
AnnaBridge	165:d1b4690b3f8b	2102	}
AnnaBridge	165:d1b4690b3f8b	2103
AnnaBridge	165:d1b4690b3f8b	2104	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	165:d1b4690b3f8b	2105
AnnaBridge	165:d1b4690b3f8b	2106
AnnaBridge	165:d1b4690b3f8b	2107
AnnaBridge	165:d1b4690b3f8b	2108
AnnaBridge	165:d1b4690b3f8b	2109	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	2110	}
AnnaBridge	165:d1b4690b3f8b	2111	#endif
AnnaBridge	165:d1b4690b3f8b	2112
AnnaBridge	165:d1b4690b3f8b	2113	#endif /* __CORE_CM4_H_DEPENDANT */
AnnaBridge	165:d1b4690b3f8b	2114
AnnaBridge	165:d1b4690b3f8b	2115	#endif /* __CMSIS_GENERIC */