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TARGET_DISCO_L496AG/core_cm0plus.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
165:d1b4690b3f8b
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /**************************************************************************//**
AnnaBridge 165:d1b4690b3f8b 2 * @file core_cm0plus.h
AnnaBridge 165:d1b4690b3f8b 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
AnnaBridge 165:d1b4690b3f8b 4 * @version V5.0.3
AnnaBridge 165:d1b4690b3f8b 5 * @date 09. August 2017
AnnaBridge 165:d1b4690b3f8b 6 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 7 /*
AnnaBridge 165:d1b4690b3f8b 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 165:d1b4690b3f8b 9 *
AnnaBridge 165:d1b4690b3f8b 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 165:d1b4690b3f8b 11 *
AnnaBridge 165:d1b4690b3f8b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 165:d1b4690b3f8b 13 * not use this file except in compliance with the License.
AnnaBridge 165:d1b4690b3f8b 14 * You may obtain a copy of the License at
AnnaBridge 165:d1b4690b3f8b 15 *
AnnaBridge 165:d1b4690b3f8b 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 165:d1b4690b3f8b 17 *
AnnaBridge 165:d1b4690b3f8b 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 165:d1b4690b3f8b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 165:d1b4690b3f8b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 165:d1b4690b3f8b 21 * See the License for the specific language governing permissions and
AnnaBridge 165:d1b4690b3f8b 22 * limitations under the License.
AnnaBridge 165:d1b4690b3f8b 23 */
AnnaBridge 165:d1b4690b3f8b 24
AnnaBridge 165:d1b4690b3f8b 25 #if defined ( __ICCARM__ )
AnnaBridge 165:d1b4690b3f8b 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 165:d1b4690b3f8b 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 165:d1b4690b3f8b 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 165:d1b4690b3f8b 29 #endif
AnnaBridge 165:d1b4690b3f8b 30
AnnaBridge 165:d1b4690b3f8b 31 #ifndef __CORE_CM0PLUS_H_GENERIC
AnnaBridge 165:d1b4690b3f8b 32 #define __CORE_CM0PLUS_H_GENERIC
AnnaBridge 165:d1b4690b3f8b 33
AnnaBridge 165:d1b4690b3f8b 34 #include <stdint.h>
AnnaBridge 165:d1b4690b3f8b 35
AnnaBridge 165:d1b4690b3f8b 36 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 37 extern "C" {
AnnaBridge 165:d1b4690b3f8b 38 #endif
AnnaBridge 165:d1b4690b3f8b 39
AnnaBridge 165:d1b4690b3f8b 40 /**
AnnaBridge 165:d1b4690b3f8b 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 165:d1b4690b3f8b 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 165:d1b4690b3f8b 43
AnnaBridge 165:d1b4690b3f8b 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 165:d1b4690b3f8b 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 165:d1b4690b3f8b 46
AnnaBridge 165:d1b4690b3f8b 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 165:d1b4690b3f8b 48 Unions are used for effective representation of core registers.
AnnaBridge 165:d1b4690b3f8b 49
AnnaBridge 165:d1b4690b3f8b 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 165:d1b4690b3f8b 51 Function-like macros are used to allow more efficient code.
AnnaBridge 165:d1b4690b3f8b 52 */
AnnaBridge 165:d1b4690b3f8b 53
AnnaBridge 165:d1b4690b3f8b 54
AnnaBridge 165:d1b4690b3f8b 55 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 56 * CMSIS definitions
AnnaBridge 165:d1b4690b3f8b 57 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 58 /**
AnnaBridge 165:d1b4690b3f8b 59 \ingroup Cortex-M0+
AnnaBridge 165:d1b4690b3f8b 60 @{
AnnaBridge 165:d1b4690b3f8b 61 */
AnnaBridge 165:d1b4690b3f8b 62
AnnaBridge 165:d1b4690b3f8b 63 #include "cmsis_version.h"
AnnaBridge 165:d1b4690b3f8b 64
AnnaBridge 165:d1b4690b3f8b 65 /* CMSIS CM0+ definitions */
AnnaBridge 165:d1b4690b3f8b 66 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 165:d1b4690b3f8b 67 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 165:d1b4690b3f8b 68 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 165:d1b4690b3f8b 69 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 165:d1b4690b3f8b 70
AnnaBridge 165:d1b4690b3f8b 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 165:d1b4690b3f8b 72
AnnaBridge 165:d1b4690b3f8b 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 165:d1b4690b3f8b 74 This core does not support an FPU at all
AnnaBridge 165:d1b4690b3f8b 75 */
AnnaBridge 165:d1b4690b3f8b 76 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 77
AnnaBridge 165:d1b4690b3f8b 78 #if defined ( __CC_ARM )
AnnaBridge 165:d1b4690b3f8b 79 #if defined __TARGET_FPU_VFP
AnnaBridge 165:d1b4690b3f8b 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 81 #endif
AnnaBridge 165:d1b4690b3f8b 82
AnnaBridge 165:d1b4690b3f8b 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 165:d1b4690b3f8b 84 #if defined __ARM_PCS_VFP
AnnaBridge 165:d1b4690b3f8b 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 86 #endif
AnnaBridge 165:d1b4690b3f8b 87
AnnaBridge 165:d1b4690b3f8b 88 #elif defined ( __GNUC__ )
AnnaBridge 165:d1b4690b3f8b 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 165:d1b4690b3f8b 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 91 #endif
AnnaBridge 165:d1b4690b3f8b 92
AnnaBridge 165:d1b4690b3f8b 93 #elif defined ( __ICCARM__ )
AnnaBridge 165:d1b4690b3f8b 94 #if defined __ARMVFP__
AnnaBridge 165:d1b4690b3f8b 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 96 #endif
AnnaBridge 165:d1b4690b3f8b 97
AnnaBridge 165:d1b4690b3f8b 98 #elif defined ( __TI_ARM__ )
AnnaBridge 165:d1b4690b3f8b 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 165:d1b4690b3f8b 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 101 #endif
AnnaBridge 165:d1b4690b3f8b 102
AnnaBridge 165:d1b4690b3f8b 103 #elif defined ( __TASKING__ )
AnnaBridge 165:d1b4690b3f8b 104 #if defined __FPU_VFP__
AnnaBridge 165:d1b4690b3f8b 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 106 #endif
AnnaBridge 165:d1b4690b3f8b 107
AnnaBridge 165:d1b4690b3f8b 108 #elif defined ( __CSMC__ )
AnnaBridge 165:d1b4690b3f8b 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 165:d1b4690b3f8b 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 111 #endif
AnnaBridge 165:d1b4690b3f8b 112
AnnaBridge 165:d1b4690b3f8b 113 #endif
AnnaBridge 165:d1b4690b3f8b 114
AnnaBridge 165:d1b4690b3f8b 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 165:d1b4690b3f8b 116
AnnaBridge 165:d1b4690b3f8b 117
AnnaBridge 165:d1b4690b3f8b 118 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 119 }
AnnaBridge 165:d1b4690b3f8b 120 #endif
AnnaBridge 165:d1b4690b3f8b 121
AnnaBridge 165:d1b4690b3f8b 122 #endif /* __CORE_CM0PLUS_H_GENERIC */
AnnaBridge 165:d1b4690b3f8b 123
AnnaBridge 165:d1b4690b3f8b 124 #ifndef __CMSIS_GENERIC
AnnaBridge 165:d1b4690b3f8b 125
AnnaBridge 165:d1b4690b3f8b 126 #ifndef __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 165:d1b4690b3f8b 127 #define __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 165:d1b4690b3f8b 128
AnnaBridge 165:d1b4690b3f8b 129 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 130 extern "C" {
AnnaBridge 165:d1b4690b3f8b 131 #endif
AnnaBridge 165:d1b4690b3f8b 132
AnnaBridge 165:d1b4690b3f8b 133 /* check device defines and use defaults */
AnnaBridge 165:d1b4690b3f8b 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 165:d1b4690b3f8b 135 #ifndef __CM0PLUS_REV
AnnaBridge 165:d1b4690b3f8b 136 #define __CM0PLUS_REV 0x0000U
AnnaBridge 165:d1b4690b3f8b 137 #warning "__CM0PLUS_REV not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 138 #endif
AnnaBridge 165:d1b4690b3f8b 139
AnnaBridge 165:d1b4690b3f8b 140 #ifndef __MPU_PRESENT
AnnaBridge 165:d1b4690b3f8b 141 #define __MPU_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 143 #endif
AnnaBridge 165:d1b4690b3f8b 144
AnnaBridge 165:d1b4690b3f8b 145 #ifndef __VTOR_PRESENT
AnnaBridge 165:d1b4690b3f8b 146 #define __VTOR_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 148 #endif
AnnaBridge 165:d1b4690b3f8b 149
AnnaBridge 165:d1b4690b3f8b 150 #ifndef __NVIC_PRIO_BITS
AnnaBridge 165:d1b4690b3f8b 151 #define __NVIC_PRIO_BITS 2U
AnnaBridge 165:d1b4690b3f8b 152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 153 #endif
AnnaBridge 165:d1b4690b3f8b 154
AnnaBridge 165:d1b4690b3f8b 155 #ifndef __Vendor_SysTickConfig
AnnaBridge 165:d1b4690b3f8b 156 #define __Vendor_SysTickConfig 0U
AnnaBridge 165:d1b4690b3f8b 157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 158 #endif
AnnaBridge 165:d1b4690b3f8b 159 #endif
AnnaBridge 165:d1b4690b3f8b 160
AnnaBridge 165:d1b4690b3f8b 161 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 165:d1b4690b3f8b 162 /**
AnnaBridge 165:d1b4690b3f8b 163 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 165:d1b4690b3f8b 164
AnnaBridge 165:d1b4690b3f8b 165 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 165:d1b4690b3f8b 166 \li to specify the access to peripheral variables.
AnnaBridge 165:d1b4690b3f8b 167 \li for automatic generation of peripheral register debug information.
AnnaBridge 165:d1b4690b3f8b 168 */
AnnaBridge 165:d1b4690b3f8b 169 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 170 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 165:d1b4690b3f8b 171 #else
AnnaBridge 165:d1b4690b3f8b 172 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 165:d1b4690b3f8b 173 #endif
AnnaBridge 165:d1b4690b3f8b 174 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 165:d1b4690b3f8b 175 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 165:d1b4690b3f8b 176
AnnaBridge 165:d1b4690b3f8b 177 /* following defines should be used for structure members */
AnnaBridge 165:d1b4690b3f8b 178 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 179 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 181
AnnaBridge 165:d1b4690b3f8b 182 /*@} end of group Cortex-M0+ */
AnnaBridge 165:d1b4690b3f8b 183
AnnaBridge 165:d1b4690b3f8b 184
AnnaBridge 165:d1b4690b3f8b 185
AnnaBridge 165:d1b4690b3f8b 186 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 187 * Register Abstraction
AnnaBridge 165:d1b4690b3f8b 188 Core Register contain:
AnnaBridge 165:d1b4690b3f8b 189 - Core Register
AnnaBridge 165:d1b4690b3f8b 190 - Core NVIC Register
AnnaBridge 165:d1b4690b3f8b 191 - Core SCB Register
AnnaBridge 165:d1b4690b3f8b 192 - Core SysTick Register
AnnaBridge 165:d1b4690b3f8b 193 - Core MPU Register
AnnaBridge 165:d1b4690b3f8b 194 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 195 /**
AnnaBridge 165:d1b4690b3f8b 196 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 165:d1b4690b3f8b 197 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 165:d1b4690b3f8b 198 */
AnnaBridge 165:d1b4690b3f8b 199
AnnaBridge 165:d1b4690b3f8b 200 /**
AnnaBridge 165:d1b4690b3f8b 201 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 202 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 165:d1b4690b3f8b 203 \brief Core Register type definitions.
AnnaBridge 165:d1b4690b3f8b 204 @{
AnnaBridge 165:d1b4690b3f8b 205 */
AnnaBridge 165:d1b4690b3f8b 206
AnnaBridge 165:d1b4690b3f8b 207 /**
AnnaBridge 165:d1b4690b3f8b 208 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 165:d1b4690b3f8b 209 */
AnnaBridge 165:d1b4690b3f8b 210 typedef union
AnnaBridge 165:d1b4690b3f8b 211 {
AnnaBridge 165:d1b4690b3f8b 212 struct
AnnaBridge 165:d1b4690b3f8b 213 {
AnnaBridge 165:d1b4690b3f8b 214 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 165:d1b4690b3f8b 215 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 165:d1b4690b3f8b 216 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 165:d1b4690b3f8b 217 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 165:d1b4690b3f8b 218 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 165:d1b4690b3f8b 219 } b; /*!< Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 220 uint32_t w; /*!< Type used for word access */
AnnaBridge 165:d1b4690b3f8b 221 } APSR_Type;
AnnaBridge 165:d1b4690b3f8b 222
AnnaBridge 165:d1b4690b3f8b 223 /* APSR Register Definitions */
AnnaBridge 165:d1b4690b3f8b 224 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 165:d1b4690b3f8b 225 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 165:d1b4690b3f8b 226
AnnaBridge 165:d1b4690b3f8b 227 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 165:d1b4690b3f8b 228 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 165:d1b4690b3f8b 229
AnnaBridge 165:d1b4690b3f8b 230 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 165:d1b4690b3f8b 231 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 165:d1b4690b3f8b 232
AnnaBridge 165:d1b4690b3f8b 233 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 165:d1b4690b3f8b 234 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 165:d1b4690b3f8b 235
AnnaBridge 165:d1b4690b3f8b 236
AnnaBridge 165:d1b4690b3f8b 237 /**
AnnaBridge 165:d1b4690b3f8b 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 165:d1b4690b3f8b 239 */
AnnaBridge 165:d1b4690b3f8b 240 typedef union
AnnaBridge 165:d1b4690b3f8b 241 {
AnnaBridge 165:d1b4690b3f8b 242 struct
AnnaBridge 165:d1b4690b3f8b 243 {
AnnaBridge 165:d1b4690b3f8b 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 165:d1b4690b3f8b 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 165:d1b4690b3f8b 246 } b; /*!< Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 247 uint32_t w; /*!< Type used for word access */
AnnaBridge 165:d1b4690b3f8b 248 } IPSR_Type;
AnnaBridge 165:d1b4690b3f8b 249
AnnaBridge 165:d1b4690b3f8b 250 /* IPSR Register Definitions */
AnnaBridge 165:d1b4690b3f8b 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 165:d1b4690b3f8b 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 165:d1b4690b3f8b 253
AnnaBridge 165:d1b4690b3f8b 254
AnnaBridge 165:d1b4690b3f8b 255 /**
AnnaBridge 165:d1b4690b3f8b 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 165:d1b4690b3f8b 257 */
AnnaBridge 165:d1b4690b3f8b 258 typedef union
AnnaBridge 165:d1b4690b3f8b 259 {
AnnaBridge 165:d1b4690b3f8b 260 struct
AnnaBridge 165:d1b4690b3f8b 261 {
AnnaBridge 165:d1b4690b3f8b 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 165:d1b4690b3f8b 263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 165:d1b4690b3f8b 264 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 165:d1b4690b3f8b 265 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 165:d1b4690b3f8b 266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 165:d1b4690b3f8b 267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 165:d1b4690b3f8b 268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 165:d1b4690b3f8b 269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 165:d1b4690b3f8b 270 } b; /*!< Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 271 uint32_t w; /*!< Type used for word access */
AnnaBridge 165:d1b4690b3f8b 272 } xPSR_Type;
AnnaBridge 165:d1b4690b3f8b 273
AnnaBridge 165:d1b4690b3f8b 274 /* xPSR Register Definitions */
AnnaBridge 165:d1b4690b3f8b 275 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 165:d1b4690b3f8b 276 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 165:d1b4690b3f8b 277
AnnaBridge 165:d1b4690b3f8b 278 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 165:d1b4690b3f8b 279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 165:d1b4690b3f8b 280
AnnaBridge 165:d1b4690b3f8b 281 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 165:d1b4690b3f8b 282 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 165:d1b4690b3f8b 283
AnnaBridge 165:d1b4690b3f8b 284 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 165:d1b4690b3f8b 285 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 165:d1b4690b3f8b 286
AnnaBridge 165:d1b4690b3f8b 287 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 165:d1b4690b3f8b 288 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 165:d1b4690b3f8b 289
AnnaBridge 165:d1b4690b3f8b 290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 165:d1b4690b3f8b 291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 165:d1b4690b3f8b 292
AnnaBridge 165:d1b4690b3f8b 293
AnnaBridge 165:d1b4690b3f8b 294 /**
AnnaBridge 165:d1b4690b3f8b 295 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 165:d1b4690b3f8b 296 */
AnnaBridge 165:d1b4690b3f8b 297 typedef union
AnnaBridge 165:d1b4690b3f8b 298 {
AnnaBridge 165:d1b4690b3f8b 299 struct
AnnaBridge 165:d1b4690b3f8b 300 {
AnnaBridge 165:d1b4690b3f8b 301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 165:d1b4690b3f8b 302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 165:d1b4690b3f8b 303 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 165:d1b4690b3f8b 304 } b; /*!< Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 305 uint32_t w; /*!< Type used for word access */
AnnaBridge 165:d1b4690b3f8b 306 } CONTROL_Type;
AnnaBridge 165:d1b4690b3f8b 307
AnnaBridge 165:d1b4690b3f8b 308 /* CONTROL Register Definitions */
AnnaBridge 165:d1b4690b3f8b 309 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 165:d1b4690b3f8b 310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 165:d1b4690b3f8b 311
AnnaBridge 165:d1b4690b3f8b 312 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 165:d1b4690b3f8b 313 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 165:d1b4690b3f8b 314
AnnaBridge 165:d1b4690b3f8b 315 /*@} end of group CMSIS_CORE */
AnnaBridge 165:d1b4690b3f8b 316
AnnaBridge 165:d1b4690b3f8b 317
AnnaBridge 165:d1b4690b3f8b 318 /**
AnnaBridge 165:d1b4690b3f8b 319 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 320 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 165:d1b4690b3f8b 321 \brief Type definitions for the NVIC Registers
AnnaBridge 165:d1b4690b3f8b 322 @{
AnnaBridge 165:d1b4690b3f8b 323 */
AnnaBridge 165:d1b4690b3f8b 324
AnnaBridge 165:d1b4690b3f8b 325 /**
AnnaBridge 165:d1b4690b3f8b 326 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 165:d1b4690b3f8b 327 */
AnnaBridge 165:d1b4690b3f8b 328 typedef struct
AnnaBridge 165:d1b4690b3f8b 329 {
AnnaBridge 165:d1b4690b3f8b 330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 165:d1b4690b3f8b 331 uint32_t RESERVED0[31U];
AnnaBridge 165:d1b4690b3f8b 332 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 165:d1b4690b3f8b 333 uint32_t RSERVED1[31U];
AnnaBridge 165:d1b4690b3f8b 334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 165:d1b4690b3f8b 335 uint32_t RESERVED2[31U];
AnnaBridge 165:d1b4690b3f8b 336 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 165:d1b4690b3f8b 337 uint32_t RESERVED3[31U];
AnnaBridge 165:d1b4690b3f8b 338 uint32_t RESERVED4[64U];
AnnaBridge 165:d1b4690b3f8b 339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 165:d1b4690b3f8b 340 } NVIC_Type;
AnnaBridge 165:d1b4690b3f8b 341
AnnaBridge 165:d1b4690b3f8b 342 /*@} end of group CMSIS_NVIC */
AnnaBridge 165:d1b4690b3f8b 343
AnnaBridge 165:d1b4690b3f8b 344
AnnaBridge 165:d1b4690b3f8b 345 /**
AnnaBridge 165:d1b4690b3f8b 346 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 347 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 165:d1b4690b3f8b 348 \brief Type definitions for the System Control Block Registers
AnnaBridge 165:d1b4690b3f8b 349 @{
AnnaBridge 165:d1b4690b3f8b 350 */
AnnaBridge 165:d1b4690b3f8b 351
AnnaBridge 165:d1b4690b3f8b 352 /**
AnnaBridge 165:d1b4690b3f8b 353 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 165:d1b4690b3f8b 354 */
AnnaBridge 165:d1b4690b3f8b 355 typedef struct
AnnaBridge 165:d1b4690b3f8b 356 {
AnnaBridge 165:d1b4690b3f8b 357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 165:d1b4690b3f8b 358 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 165:d1b4690b3f8b 359 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 165:d1b4690b3f8b 361 #else
AnnaBridge 165:d1b4690b3f8b 362 uint32_t RESERVED0;
AnnaBridge 165:d1b4690b3f8b 363 #endif
AnnaBridge 165:d1b4690b3f8b 364 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 165:d1b4690b3f8b 365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 165:d1b4690b3f8b 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 165:d1b4690b3f8b 367 uint32_t RESERVED1;
AnnaBridge 165:d1b4690b3f8b 368 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 165:d1b4690b3f8b 369 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 165:d1b4690b3f8b 370 } SCB_Type;
AnnaBridge 165:d1b4690b3f8b 371
AnnaBridge 165:d1b4690b3f8b 372 /* SCB CPUID Register Definitions */
AnnaBridge 165:d1b4690b3f8b 373 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 165:d1b4690b3f8b 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 165:d1b4690b3f8b 375
AnnaBridge 165:d1b4690b3f8b 376 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 165:d1b4690b3f8b 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 165:d1b4690b3f8b 378
AnnaBridge 165:d1b4690b3f8b 379 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 165:d1b4690b3f8b 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 165:d1b4690b3f8b 381
AnnaBridge 165:d1b4690b3f8b 382 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 165:d1b4690b3f8b 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 165:d1b4690b3f8b 384
AnnaBridge 165:d1b4690b3f8b 385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 165:d1b4690b3f8b 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 165:d1b4690b3f8b 387
AnnaBridge 165:d1b4690b3f8b 388 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 165:d1b4690b3f8b 389 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 165:d1b4690b3f8b 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 165:d1b4690b3f8b 391
AnnaBridge 165:d1b4690b3f8b 392 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 165:d1b4690b3f8b 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 165:d1b4690b3f8b 394
AnnaBridge 165:d1b4690b3f8b 395 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 165:d1b4690b3f8b 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 165:d1b4690b3f8b 397
AnnaBridge 165:d1b4690b3f8b 398 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 165:d1b4690b3f8b 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 165:d1b4690b3f8b 400
AnnaBridge 165:d1b4690b3f8b 401 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 165:d1b4690b3f8b 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 165:d1b4690b3f8b 403
AnnaBridge 165:d1b4690b3f8b 404 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 165:d1b4690b3f8b 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 165:d1b4690b3f8b 406
AnnaBridge 165:d1b4690b3f8b 407 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 165:d1b4690b3f8b 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 165:d1b4690b3f8b 409
AnnaBridge 165:d1b4690b3f8b 410 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 165:d1b4690b3f8b 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 165:d1b4690b3f8b 412
AnnaBridge 165:d1b4690b3f8b 413 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 165:d1b4690b3f8b 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 165:d1b4690b3f8b 415
AnnaBridge 165:d1b4690b3f8b 416 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 417 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 165:d1b4690b3f8b 418 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 165:d1b4690b3f8b 419 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 165:d1b4690b3f8b 420 #endif
AnnaBridge 165:d1b4690b3f8b 421
AnnaBridge 165:d1b4690b3f8b 422 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 423 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 165:d1b4690b3f8b 424 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 165:d1b4690b3f8b 425
AnnaBridge 165:d1b4690b3f8b 426 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 165:d1b4690b3f8b 427 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 165:d1b4690b3f8b 428
AnnaBridge 165:d1b4690b3f8b 429 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 165:d1b4690b3f8b 430 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 165:d1b4690b3f8b 431
AnnaBridge 165:d1b4690b3f8b 432 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 165:d1b4690b3f8b 433 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 165:d1b4690b3f8b 434
AnnaBridge 165:d1b4690b3f8b 435 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 165:d1b4690b3f8b 436 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 165:d1b4690b3f8b 437
AnnaBridge 165:d1b4690b3f8b 438 /* SCB System Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 439 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 165:d1b4690b3f8b 440 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 165:d1b4690b3f8b 441
AnnaBridge 165:d1b4690b3f8b 442 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 165:d1b4690b3f8b 443 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 165:d1b4690b3f8b 444
AnnaBridge 165:d1b4690b3f8b 445 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 165:d1b4690b3f8b 446 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 165:d1b4690b3f8b 447
AnnaBridge 165:d1b4690b3f8b 448 /* SCB Configuration Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 449 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 165:d1b4690b3f8b 450 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 165:d1b4690b3f8b 451
AnnaBridge 165:d1b4690b3f8b 452 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 165:d1b4690b3f8b 453 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 165:d1b4690b3f8b 454
AnnaBridge 165:d1b4690b3f8b 455 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 165:d1b4690b3f8b 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 165:d1b4690b3f8b 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 165:d1b4690b3f8b 458
AnnaBridge 165:d1b4690b3f8b 459 /*@} end of group CMSIS_SCB */
AnnaBridge 165:d1b4690b3f8b 460
AnnaBridge 165:d1b4690b3f8b 461
AnnaBridge 165:d1b4690b3f8b 462 /**
AnnaBridge 165:d1b4690b3f8b 463 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 464 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 165:d1b4690b3f8b 465 \brief Type definitions for the System Timer Registers.
AnnaBridge 165:d1b4690b3f8b 466 @{
AnnaBridge 165:d1b4690b3f8b 467 */
AnnaBridge 165:d1b4690b3f8b 468
AnnaBridge 165:d1b4690b3f8b 469 /**
AnnaBridge 165:d1b4690b3f8b 470 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 165:d1b4690b3f8b 471 */
AnnaBridge 165:d1b4690b3f8b 472 typedef struct
AnnaBridge 165:d1b4690b3f8b 473 {
AnnaBridge 165:d1b4690b3f8b 474 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 165:d1b4690b3f8b 475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 165:d1b4690b3f8b 476 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 165:d1b4690b3f8b 477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 165:d1b4690b3f8b 478 } SysTick_Type;
AnnaBridge 165:d1b4690b3f8b 479
AnnaBridge 165:d1b4690b3f8b 480 /* SysTick Control / Status Register Definitions */
AnnaBridge 165:d1b4690b3f8b 481 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 165:d1b4690b3f8b 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 165:d1b4690b3f8b 483
AnnaBridge 165:d1b4690b3f8b 484 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 165:d1b4690b3f8b 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 165:d1b4690b3f8b 486
AnnaBridge 165:d1b4690b3f8b 487 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 165:d1b4690b3f8b 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 165:d1b4690b3f8b 489
AnnaBridge 165:d1b4690b3f8b 490 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 165:d1b4690b3f8b 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 165:d1b4690b3f8b 492
AnnaBridge 165:d1b4690b3f8b 493 /* SysTick Reload Register Definitions */
AnnaBridge 165:d1b4690b3f8b 494 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 165:d1b4690b3f8b 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 165:d1b4690b3f8b 496
AnnaBridge 165:d1b4690b3f8b 497 /* SysTick Current Register Definitions */
AnnaBridge 165:d1b4690b3f8b 498 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 165:d1b4690b3f8b 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 165:d1b4690b3f8b 500
AnnaBridge 165:d1b4690b3f8b 501 /* SysTick Calibration Register Definitions */
AnnaBridge 165:d1b4690b3f8b 502 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 165:d1b4690b3f8b 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 165:d1b4690b3f8b 504
AnnaBridge 165:d1b4690b3f8b 505 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 165:d1b4690b3f8b 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 165:d1b4690b3f8b 507
AnnaBridge 165:d1b4690b3f8b 508 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 165:d1b4690b3f8b 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 165:d1b4690b3f8b 510
AnnaBridge 165:d1b4690b3f8b 511 /*@} end of group CMSIS_SysTick */
AnnaBridge 165:d1b4690b3f8b 512
AnnaBridge 165:d1b4690b3f8b 513 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 514 /**
AnnaBridge 165:d1b4690b3f8b 515 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 516 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 165:d1b4690b3f8b 517 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 165:d1b4690b3f8b 518 @{
AnnaBridge 165:d1b4690b3f8b 519 */
AnnaBridge 165:d1b4690b3f8b 520
AnnaBridge 165:d1b4690b3f8b 521 /**
AnnaBridge 165:d1b4690b3f8b 522 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 165:d1b4690b3f8b 523 */
AnnaBridge 165:d1b4690b3f8b 524 typedef struct
AnnaBridge 165:d1b4690b3f8b 525 {
AnnaBridge 165:d1b4690b3f8b 526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 165:d1b4690b3f8b 527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 165:d1b4690b3f8b 528 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 165:d1b4690b3f8b 529 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 165:d1b4690b3f8b 530 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 165:d1b4690b3f8b 531 } MPU_Type;
AnnaBridge 165:d1b4690b3f8b 532
AnnaBridge 165:d1b4690b3f8b 533 #define MPU_TYPE_RALIASES 1U
AnnaBridge 165:d1b4690b3f8b 534
AnnaBridge 165:d1b4690b3f8b 535 /* MPU Type Register Definitions */
AnnaBridge 165:d1b4690b3f8b 536 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 165:d1b4690b3f8b 537 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 165:d1b4690b3f8b 538
AnnaBridge 165:d1b4690b3f8b 539 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 165:d1b4690b3f8b 540 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 165:d1b4690b3f8b 541
AnnaBridge 165:d1b4690b3f8b 542 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 165:d1b4690b3f8b 543 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 165:d1b4690b3f8b 544
AnnaBridge 165:d1b4690b3f8b 545 /* MPU Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 546 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 165:d1b4690b3f8b 547 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 165:d1b4690b3f8b 548
AnnaBridge 165:d1b4690b3f8b 549 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 165:d1b4690b3f8b 550 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 165:d1b4690b3f8b 551
AnnaBridge 165:d1b4690b3f8b 552 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 165:d1b4690b3f8b 553 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 165:d1b4690b3f8b 554
AnnaBridge 165:d1b4690b3f8b 555 /* MPU Region Number Register Definitions */
AnnaBridge 165:d1b4690b3f8b 556 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 165:d1b4690b3f8b 557 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 165:d1b4690b3f8b 558
AnnaBridge 165:d1b4690b3f8b 559 /* MPU Region Base Address Register Definitions */
AnnaBridge 165:d1b4690b3f8b 560 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
AnnaBridge 165:d1b4690b3f8b 561 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 165:d1b4690b3f8b 562
AnnaBridge 165:d1b4690b3f8b 563 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 165:d1b4690b3f8b 564 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 165:d1b4690b3f8b 565
AnnaBridge 165:d1b4690b3f8b 566 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 165:d1b4690b3f8b 567 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 165:d1b4690b3f8b 568
AnnaBridge 165:d1b4690b3f8b 569 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 165:d1b4690b3f8b 570 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 165:d1b4690b3f8b 571 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 165:d1b4690b3f8b 572
AnnaBridge 165:d1b4690b3f8b 573 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 165:d1b4690b3f8b 574 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 165:d1b4690b3f8b 575
AnnaBridge 165:d1b4690b3f8b 576 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 165:d1b4690b3f8b 577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 165:d1b4690b3f8b 578
AnnaBridge 165:d1b4690b3f8b 579 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 165:d1b4690b3f8b 580 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 165:d1b4690b3f8b 581
AnnaBridge 165:d1b4690b3f8b 582 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 165:d1b4690b3f8b 583 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 165:d1b4690b3f8b 584
AnnaBridge 165:d1b4690b3f8b 585 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 165:d1b4690b3f8b 586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 165:d1b4690b3f8b 587
AnnaBridge 165:d1b4690b3f8b 588 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 165:d1b4690b3f8b 589 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 165:d1b4690b3f8b 590
AnnaBridge 165:d1b4690b3f8b 591 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 165:d1b4690b3f8b 592 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 165:d1b4690b3f8b 593
AnnaBridge 165:d1b4690b3f8b 594 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 165:d1b4690b3f8b 595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 165:d1b4690b3f8b 596
AnnaBridge 165:d1b4690b3f8b 597 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 165:d1b4690b3f8b 598 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 165:d1b4690b3f8b 599
AnnaBridge 165:d1b4690b3f8b 600 /*@} end of group CMSIS_MPU */
AnnaBridge 165:d1b4690b3f8b 601 #endif
AnnaBridge 165:d1b4690b3f8b 602
AnnaBridge 165:d1b4690b3f8b 603
AnnaBridge 165:d1b4690b3f8b 604 /**
AnnaBridge 165:d1b4690b3f8b 605 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 606 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 165:d1b4690b3f8b 607 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 165:d1b4690b3f8b 608 Therefore they are not covered by the Cortex-M0+ header file.
AnnaBridge 165:d1b4690b3f8b 609 @{
AnnaBridge 165:d1b4690b3f8b 610 */
AnnaBridge 165:d1b4690b3f8b 611 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 165:d1b4690b3f8b 612
AnnaBridge 165:d1b4690b3f8b 613
AnnaBridge 165:d1b4690b3f8b 614 /**
AnnaBridge 165:d1b4690b3f8b 615 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 616 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 165:d1b4690b3f8b 617 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 165:d1b4690b3f8b 618 @{
AnnaBridge 165:d1b4690b3f8b 619 */
AnnaBridge 165:d1b4690b3f8b 620
AnnaBridge 165:d1b4690b3f8b 621 /**
AnnaBridge 165:d1b4690b3f8b 622 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 165:d1b4690b3f8b 623 \param[in] field Name of the register bit field.
AnnaBridge 165:d1b4690b3f8b 624 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 165:d1b4690b3f8b 625 \return Masked and shifted value.
AnnaBridge 165:d1b4690b3f8b 626 */
AnnaBridge 165:d1b4690b3f8b 627 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 165:d1b4690b3f8b 628
AnnaBridge 165:d1b4690b3f8b 629 /**
AnnaBridge 165:d1b4690b3f8b 630 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 165:d1b4690b3f8b 631 \param[in] field Name of the register bit field.
AnnaBridge 165:d1b4690b3f8b 632 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 165:d1b4690b3f8b 633 \return Masked and shifted bit field value.
AnnaBridge 165:d1b4690b3f8b 634 */
AnnaBridge 165:d1b4690b3f8b 635 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 165:d1b4690b3f8b 636
AnnaBridge 165:d1b4690b3f8b 637 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 165:d1b4690b3f8b 638
AnnaBridge 165:d1b4690b3f8b 639
AnnaBridge 165:d1b4690b3f8b 640 /**
AnnaBridge 165:d1b4690b3f8b 641 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 642 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 165:d1b4690b3f8b 643 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 165:d1b4690b3f8b 644 @{
AnnaBridge 165:d1b4690b3f8b 645 */
AnnaBridge 165:d1b4690b3f8b 646
AnnaBridge 165:d1b4690b3f8b 647 /* Memory mapping of Core Hardware */
AnnaBridge 165:d1b4690b3f8b 648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 165:d1b4690b3f8b 649 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 165:d1b4690b3f8b 650 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 165:d1b4690b3f8b 651 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 165:d1b4690b3f8b 652
AnnaBridge 165:d1b4690b3f8b 653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 165:d1b4690b3f8b 654 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 165:d1b4690b3f8b 655 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 165:d1b4690b3f8b 656
AnnaBridge 165:d1b4690b3f8b 657 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 658 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 165:d1b4690b3f8b 659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 165:d1b4690b3f8b 660 #endif
AnnaBridge 165:d1b4690b3f8b 661
AnnaBridge 165:d1b4690b3f8b 662 /*@} */
AnnaBridge 165:d1b4690b3f8b 663
AnnaBridge 165:d1b4690b3f8b 664
AnnaBridge 165:d1b4690b3f8b 665
AnnaBridge 165:d1b4690b3f8b 666 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 667 * Hardware Abstraction Layer
AnnaBridge 165:d1b4690b3f8b 668 Core Function Interface contains:
AnnaBridge 165:d1b4690b3f8b 669 - Core NVIC Functions
AnnaBridge 165:d1b4690b3f8b 670 - Core SysTick Functions
AnnaBridge 165:d1b4690b3f8b 671 - Core Register Access Functions
AnnaBridge 165:d1b4690b3f8b 672 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 673 /**
AnnaBridge 165:d1b4690b3f8b 674 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 165:d1b4690b3f8b 675 */
AnnaBridge 165:d1b4690b3f8b 676
AnnaBridge 165:d1b4690b3f8b 677
AnnaBridge 165:d1b4690b3f8b 678
AnnaBridge 165:d1b4690b3f8b 679 /* ########################## NVIC functions #################################### */
AnnaBridge 165:d1b4690b3f8b 680 /**
AnnaBridge 165:d1b4690b3f8b 681 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 165:d1b4690b3f8b 682 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 165:d1b4690b3f8b 683 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 165:d1b4690b3f8b 684 @{
AnnaBridge 165:d1b4690b3f8b 685 */
AnnaBridge 165:d1b4690b3f8b 686
AnnaBridge 165:d1b4690b3f8b 687 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 165:d1b4690b3f8b 688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 165:d1b4690b3f8b 689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 165:d1b4690b3f8b 690 #endif
AnnaBridge 165:d1b4690b3f8b 691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 165:d1b4690b3f8b 692 #else
AnnaBridge 165:d1b4690b3f8b 693 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
AnnaBridge 165:d1b4690b3f8b 694 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
AnnaBridge 165:d1b4690b3f8b 695 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 165:d1b4690b3f8b 696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 165:d1b4690b3f8b 697 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 165:d1b4690b3f8b 698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 165:d1b4690b3f8b 699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 165:d1b4690b3f8b 700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 165:d1b4690b3f8b 701 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
AnnaBridge 165:d1b4690b3f8b 702 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 165:d1b4690b3f8b 703 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 165:d1b4690b3f8b 704 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 165:d1b4690b3f8b 705 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 165:d1b4690b3f8b 706
AnnaBridge 165:d1b4690b3f8b 707 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 165:d1b4690b3f8b 708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 165:d1b4690b3f8b 709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 165:d1b4690b3f8b 710 #endif
AnnaBridge 165:d1b4690b3f8b 711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 165:d1b4690b3f8b 712 #else
AnnaBridge 165:d1b4690b3f8b 713 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 165:d1b4690b3f8b 714 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 165:d1b4690b3f8b 715 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 165:d1b4690b3f8b 716
AnnaBridge 165:d1b4690b3f8b 717 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 165:d1b4690b3f8b 718
AnnaBridge 165:d1b4690b3f8b 719
AnnaBridge 165:d1b4690b3f8b 720 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 165:d1b4690b3f8b 721 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 165:d1b4690b3f8b 722 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 165:d1b4690b3f8b 723 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 165:d1b4690b3f8b 724 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 165:d1b4690b3f8b 725
AnnaBridge 165:d1b4690b3f8b 726
AnnaBridge 165:d1b4690b3f8b 727 /**
AnnaBridge 165:d1b4690b3f8b 728 \brief Enable Interrupt
AnnaBridge 165:d1b4690b3f8b 729 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 165:d1b4690b3f8b 730 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 731 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 732 */
AnnaBridge 165:d1b4690b3f8b 733 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 734 {
AnnaBridge 165:d1b4690b3f8b 735 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 736 {
AnnaBridge 165:d1b4690b3f8b 737 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 738 }
AnnaBridge 165:d1b4690b3f8b 739 }
AnnaBridge 165:d1b4690b3f8b 740
AnnaBridge 165:d1b4690b3f8b 741
AnnaBridge 165:d1b4690b3f8b 742 /**
AnnaBridge 165:d1b4690b3f8b 743 \brief Get Interrupt Enable status
AnnaBridge 165:d1b4690b3f8b 744 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 165:d1b4690b3f8b 745 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 746 \return 0 Interrupt is not enabled.
AnnaBridge 165:d1b4690b3f8b 747 \return 1 Interrupt is enabled.
AnnaBridge 165:d1b4690b3f8b 748 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 749 */
AnnaBridge 165:d1b4690b3f8b 750 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 751 {
AnnaBridge 165:d1b4690b3f8b 752 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 753 {
AnnaBridge 165:d1b4690b3f8b 754 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 755 }
AnnaBridge 165:d1b4690b3f8b 756 else
AnnaBridge 165:d1b4690b3f8b 757 {
AnnaBridge 165:d1b4690b3f8b 758 return(0U);
AnnaBridge 165:d1b4690b3f8b 759 }
AnnaBridge 165:d1b4690b3f8b 760 }
AnnaBridge 165:d1b4690b3f8b 761
AnnaBridge 165:d1b4690b3f8b 762
AnnaBridge 165:d1b4690b3f8b 763 /**
AnnaBridge 165:d1b4690b3f8b 764 \brief Disable Interrupt
AnnaBridge 165:d1b4690b3f8b 765 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 165:d1b4690b3f8b 766 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 767 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 768 */
AnnaBridge 165:d1b4690b3f8b 769 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 770 {
AnnaBridge 165:d1b4690b3f8b 771 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 772 {
AnnaBridge 165:d1b4690b3f8b 773 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 774 __DSB();
AnnaBridge 165:d1b4690b3f8b 775 __ISB();
AnnaBridge 165:d1b4690b3f8b 776 }
AnnaBridge 165:d1b4690b3f8b 777 }
AnnaBridge 165:d1b4690b3f8b 778
AnnaBridge 165:d1b4690b3f8b 779
AnnaBridge 165:d1b4690b3f8b 780 /**
AnnaBridge 165:d1b4690b3f8b 781 \brief Get Pending Interrupt
AnnaBridge 165:d1b4690b3f8b 782 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 165:d1b4690b3f8b 783 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 784 \return 0 Interrupt status is not pending.
AnnaBridge 165:d1b4690b3f8b 785 \return 1 Interrupt status is pending.
AnnaBridge 165:d1b4690b3f8b 786 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 787 */
AnnaBridge 165:d1b4690b3f8b 788 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 789 {
AnnaBridge 165:d1b4690b3f8b 790 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 791 {
AnnaBridge 165:d1b4690b3f8b 792 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 793 }
AnnaBridge 165:d1b4690b3f8b 794 else
AnnaBridge 165:d1b4690b3f8b 795 {
AnnaBridge 165:d1b4690b3f8b 796 return(0U);
AnnaBridge 165:d1b4690b3f8b 797 }
AnnaBridge 165:d1b4690b3f8b 798 }
AnnaBridge 165:d1b4690b3f8b 799
AnnaBridge 165:d1b4690b3f8b 800
AnnaBridge 165:d1b4690b3f8b 801 /**
AnnaBridge 165:d1b4690b3f8b 802 \brief Set Pending Interrupt
AnnaBridge 165:d1b4690b3f8b 803 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 165:d1b4690b3f8b 804 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 805 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 806 */
AnnaBridge 165:d1b4690b3f8b 807 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 808 {
AnnaBridge 165:d1b4690b3f8b 809 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 810 {
AnnaBridge 165:d1b4690b3f8b 811 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 812 }
AnnaBridge 165:d1b4690b3f8b 813 }
AnnaBridge 165:d1b4690b3f8b 814
AnnaBridge 165:d1b4690b3f8b 815
AnnaBridge 165:d1b4690b3f8b 816 /**
AnnaBridge 165:d1b4690b3f8b 817 \brief Clear Pending Interrupt
AnnaBridge 165:d1b4690b3f8b 818 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 165:d1b4690b3f8b 819 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 820 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 821 */
AnnaBridge 165:d1b4690b3f8b 822 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 823 {
AnnaBridge 165:d1b4690b3f8b 824 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 825 {
AnnaBridge 165:d1b4690b3f8b 826 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 827 }
AnnaBridge 165:d1b4690b3f8b 828 }
AnnaBridge 165:d1b4690b3f8b 829
AnnaBridge 165:d1b4690b3f8b 830
AnnaBridge 165:d1b4690b3f8b 831 /**
AnnaBridge 165:d1b4690b3f8b 832 \brief Set Interrupt Priority
AnnaBridge 165:d1b4690b3f8b 833 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 165:d1b4690b3f8b 834 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 835 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 836 \param [in] IRQn Interrupt number.
AnnaBridge 165:d1b4690b3f8b 837 \param [in] priority Priority to set.
AnnaBridge 165:d1b4690b3f8b 838 \note The priority cannot be set for every processor exception.
AnnaBridge 165:d1b4690b3f8b 839 */
AnnaBridge 165:d1b4690b3f8b 840 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 165:d1b4690b3f8b 841 {
AnnaBridge 165:d1b4690b3f8b 842 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 843 {
AnnaBridge 165:d1b4690b3f8b 844 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 165:d1b4690b3f8b 845 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 165:d1b4690b3f8b 846 }
AnnaBridge 165:d1b4690b3f8b 847 else
AnnaBridge 165:d1b4690b3f8b 848 {
AnnaBridge 165:d1b4690b3f8b 849 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 165:d1b4690b3f8b 850 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 165:d1b4690b3f8b 851 }
AnnaBridge 165:d1b4690b3f8b 852 }
AnnaBridge 165:d1b4690b3f8b 853
AnnaBridge 165:d1b4690b3f8b 854
AnnaBridge 165:d1b4690b3f8b 855 /**
AnnaBridge 165:d1b4690b3f8b 856 \brief Get Interrupt Priority
AnnaBridge 165:d1b4690b3f8b 857 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 165:d1b4690b3f8b 858 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 859 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 860 \param [in] IRQn Interrupt number.
AnnaBridge 165:d1b4690b3f8b 861 \return Interrupt Priority.
AnnaBridge 165:d1b4690b3f8b 862 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 165:d1b4690b3f8b 863 */
AnnaBridge 165:d1b4690b3f8b 864 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 865 {
AnnaBridge 165:d1b4690b3f8b 866
AnnaBridge 165:d1b4690b3f8b 867 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 868 {
AnnaBridge 165:d1b4690b3f8b 869 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 165:d1b4690b3f8b 870 }
AnnaBridge 165:d1b4690b3f8b 871 else
AnnaBridge 165:d1b4690b3f8b 872 {
AnnaBridge 165:d1b4690b3f8b 873 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 165:d1b4690b3f8b 874 }
AnnaBridge 165:d1b4690b3f8b 875 }
AnnaBridge 165:d1b4690b3f8b 876
AnnaBridge 165:d1b4690b3f8b 877
AnnaBridge 165:d1b4690b3f8b 878 /**
AnnaBridge 165:d1b4690b3f8b 879 \brief Set Interrupt Vector
AnnaBridge 165:d1b4690b3f8b 880 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 165:d1b4690b3f8b 881 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 882 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 883 VTOR must been relocated to SRAM before.
AnnaBridge 165:d1b4690b3f8b 884 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 165:d1b4690b3f8b 885 \param [in] IRQn Interrupt number
AnnaBridge 165:d1b4690b3f8b 886 \param [in] vector Address of interrupt handler function
AnnaBridge 165:d1b4690b3f8b 887 */
AnnaBridge 165:d1b4690b3f8b 888 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 165:d1b4690b3f8b 889 {
AnnaBridge 165:d1b4690b3f8b 890 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 891 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 165:d1b4690b3f8b 892 #else
AnnaBridge 165:d1b4690b3f8b 893 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 165:d1b4690b3f8b 894 #endif
AnnaBridge 165:d1b4690b3f8b 895 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 165:d1b4690b3f8b 896 }
AnnaBridge 165:d1b4690b3f8b 897
AnnaBridge 165:d1b4690b3f8b 898
AnnaBridge 165:d1b4690b3f8b 899 /**
AnnaBridge 165:d1b4690b3f8b 900 \brief Get Interrupt Vector
AnnaBridge 165:d1b4690b3f8b 901 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 165:d1b4690b3f8b 902 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 903 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 904 \param [in] IRQn Interrupt number.
AnnaBridge 165:d1b4690b3f8b 905 \return Address of interrupt handler function
AnnaBridge 165:d1b4690b3f8b 906 */
AnnaBridge 165:d1b4690b3f8b 907 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 908 {
AnnaBridge 165:d1b4690b3f8b 909 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 910 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 165:d1b4690b3f8b 911 #else
AnnaBridge 165:d1b4690b3f8b 912 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 165:d1b4690b3f8b 913 #endif
AnnaBridge 165:d1b4690b3f8b 914 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 165:d1b4690b3f8b 915
AnnaBridge 165:d1b4690b3f8b 916 }
AnnaBridge 165:d1b4690b3f8b 917
AnnaBridge 165:d1b4690b3f8b 918
AnnaBridge 165:d1b4690b3f8b 919 /**
AnnaBridge 165:d1b4690b3f8b 920 \brief System Reset
AnnaBridge 165:d1b4690b3f8b 921 \details Initiates a system reset request to reset the MCU.
AnnaBridge 165:d1b4690b3f8b 922 */
AnnaBridge 165:d1b4690b3f8b 923 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 165:d1b4690b3f8b 924 {
AnnaBridge 165:d1b4690b3f8b 925 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 165:d1b4690b3f8b 926 buffered write are completed before reset */
AnnaBridge 165:d1b4690b3f8b 927 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 165:d1b4690b3f8b 928 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 165:d1b4690b3f8b 929 __DSB(); /* Ensure completion of memory access */
AnnaBridge 165:d1b4690b3f8b 930
AnnaBridge 165:d1b4690b3f8b 931 for(;;) /* wait until reset */
AnnaBridge 165:d1b4690b3f8b 932 {
AnnaBridge 165:d1b4690b3f8b 933 __NOP();
AnnaBridge 165:d1b4690b3f8b 934 }
AnnaBridge 165:d1b4690b3f8b 935 }
AnnaBridge 165:d1b4690b3f8b 936
AnnaBridge 165:d1b4690b3f8b 937 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 165:d1b4690b3f8b 938
AnnaBridge 165:d1b4690b3f8b 939 /* ########################## MPU functions #################################### */
AnnaBridge 165:d1b4690b3f8b 940
AnnaBridge 165:d1b4690b3f8b 941 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 942
AnnaBridge 165:d1b4690b3f8b 943 #include "mpu_armv7.h"
AnnaBridge 165:d1b4690b3f8b 944
AnnaBridge 165:d1b4690b3f8b 945 #endif
AnnaBridge 165:d1b4690b3f8b 946
AnnaBridge 165:d1b4690b3f8b 947 /* ########################## FPU functions #################################### */
AnnaBridge 165:d1b4690b3f8b 948 /**
AnnaBridge 165:d1b4690b3f8b 949 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 165:d1b4690b3f8b 950 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 165:d1b4690b3f8b 951 \brief Function that provides FPU type.
AnnaBridge 165:d1b4690b3f8b 952 @{
AnnaBridge 165:d1b4690b3f8b 953 */
AnnaBridge 165:d1b4690b3f8b 954
AnnaBridge 165:d1b4690b3f8b 955 /**
AnnaBridge 165:d1b4690b3f8b 956 \brief get FPU type
AnnaBridge 165:d1b4690b3f8b 957 \details returns the FPU type
AnnaBridge 165:d1b4690b3f8b 958 \returns
AnnaBridge 165:d1b4690b3f8b 959 - \b 0: No FPU
AnnaBridge 165:d1b4690b3f8b 960 - \b 1: Single precision FPU
AnnaBridge 165:d1b4690b3f8b 961 - \b 2: Double + Single precision FPU
AnnaBridge 165:d1b4690b3f8b 962 */
AnnaBridge 165:d1b4690b3f8b 963 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 165:d1b4690b3f8b 964 {
AnnaBridge 165:d1b4690b3f8b 965 return 0U; /* No FPU */
AnnaBridge 165:d1b4690b3f8b 966 }
AnnaBridge 165:d1b4690b3f8b 967
AnnaBridge 165:d1b4690b3f8b 968
AnnaBridge 165:d1b4690b3f8b 969 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 165:d1b4690b3f8b 970
AnnaBridge 165:d1b4690b3f8b 971
AnnaBridge 165:d1b4690b3f8b 972
AnnaBridge 165:d1b4690b3f8b 973 /* ################################## SysTick function ############################################ */
AnnaBridge 165:d1b4690b3f8b 974 /**
AnnaBridge 165:d1b4690b3f8b 975 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 165:d1b4690b3f8b 976 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 165:d1b4690b3f8b 977 \brief Functions that configure the System.
AnnaBridge 165:d1b4690b3f8b 978 @{
AnnaBridge 165:d1b4690b3f8b 979 */
AnnaBridge 165:d1b4690b3f8b 980
AnnaBridge 165:d1b4690b3f8b 981 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 165:d1b4690b3f8b 982
AnnaBridge 165:d1b4690b3f8b 983 /**
AnnaBridge 165:d1b4690b3f8b 984 \brief System Tick Configuration
AnnaBridge 165:d1b4690b3f8b 985 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 165:d1b4690b3f8b 986 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 165:d1b4690b3f8b 987 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 165:d1b4690b3f8b 988 \return 0 Function succeeded.
AnnaBridge 165:d1b4690b3f8b 989 \return 1 Function failed.
AnnaBridge 165:d1b4690b3f8b 990 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 165:d1b4690b3f8b 991 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 165:d1b4690b3f8b 992 must contain a vendor-specific implementation of this function.
AnnaBridge 165:d1b4690b3f8b 993 */
AnnaBridge 165:d1b4690b3f8b 994 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 165:d1b4690b3f8b 995 {
AnnaBridge 165:d1b4690b3f8b 996 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 165:d1b4690b3f8b 997 {
AnnaBridge 165:d1b4690b3f8b 998 return (1UL); /* Reload value impossible */
AnnaBridge 165:d1b4690b3f8b 999 }
AnnaBridge 165:d1b4690b3f8b 1000
AnnaBridge 165:d1b4690b3f8b 1001 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 165:d1b4690b3f8b 1002 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 165:d1b4690b3f8b 1003 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 165:d1b4690b3f8b 1004 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 165:d1b4690b3f8b 1005 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 165:d1b4690b3f8b 1006 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 165:d1b4690b3f8b 1007 return (0UL); /* Function successful */
AnnaBridge 165:d1b4690b3f8b 1008 }
AnnaBridge 165:d1b4690b3f8b 1009
AnnaBridge 165:d1b4690b3f8b 1010 #endif
AnnaBridge 165:d1b4690b3f8b 1011
AnnaBridge 165:d1b4690b3f8b 1012 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 165:d1b4690b3f8b 1013
AnnaBridge 165:d1b4690b3f8b 1014
AnnaBridge 165:d1b4690b3f8b 1015
AnnaBridge 165:d1b4690b3f8b 1016
AnnaBridge 165:d1b4690b3f8b 1017 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 1018 }
AnnaBridge 165:d1b4690b3f8b 1019 #endif
AnnaBridge 165:d1b4690b3f8b 1020
AnnaBridge 165:d1b4690b3f8b 1021 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
AnnaBridge 165:d1b4690b3f8b 1022
AnnaBridge 165:d1b4690b3f8b 1023 #endif /* __CMSIS_GENERIC */