mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_L496AG/core_armv8mbl.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
165:d1b4690b3f8b
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /**************************************************************************//**
AnnaBridge 165:d1b4690b3f8b 2 * @file core_armv8mbl.h
AnnaBridge 165:d1b4690b3f8b 3 * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File
AnnaBridge 165:d1b4690b3f8b 4 * @version V5.0.3
AnnaBridge 165:d1b4690b3f8b 5 * @date 09. August 2017
AnnaBridge 165:d1b4690b3f8b 6 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 7 /*
AnnaBridge 165:d1b4690b3f8b 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 165:d1b4690b3f8b 9 *
AnnaBridge 165:d1b4690b3f8b 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 165:d1b4690b3f8b 11 *
AnnaBridge 165:d1b4690b3f8b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 165:d1b4690b3f8b 13 * not use this file except in compliance with the License.
AnnaBridge 165:d1b4690b3f8b 14 * You may obtain a copy of the License at
AnnaBridge 165:d1b4690b3f8b 15 *
AnnaBridge 165:d1b4690b3f8b 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 165:d1b4690b3f8b 17 *
AnnaBridge 165:d1b4690b3f8b 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 165:d1b4690b3f8b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 165:d1b4690b3f8b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 165:d1b4690b3f8b 21 * See the License for the specific language governing permissions and
AnnaBridge 165:d1b4690b3f8b 22 * limitations under the License.
AnnaBridge 165:d1b4690b3f8b 23 */
AnnaBridge 165:d1b4690b3f8b 24
AnnaBridge 165:d1b4690b3f8b 25 #if defined ( __ICCARM__ )
AnnaBridge 165:d1b4690b3f8b 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 165:d1b4690b3f8b 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 165:d1b4690b3f8b 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 165:d1b4690b3f8b 29 #endif
AnnaBridge 165:d1b4690b3f8b 30
AnnaBridge 165:d1b4690b3f8b 31 #ifndef __CORE_ARMV8MBL_H_GENERIC
AnnaBridge 165:d1b4690b3f8b 32 #define __CORE_ARMV8MBL_H_GENERIC
AnnaBridge 165:d1b4690b3f8b 33
AnnaBridge 165:d1b4690b3f8b 34 #include <stdint.h>
AnnaBridge 165:d1b4690b3f8b 35
AnnaBridge 165:d1b4690b3f8b 36 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 37 extern "C" {
AnnaBridge 165:d1b4690b3f8b 38 #endif
AnnaBridge 165:d1b4690b3f8b 39
AnnaBridge 165:d1b4690b3f8b 40 /**
AnnaBridge 165:d1b4690b3f8b 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 165:d1b4690b3f8b 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 165:d1b4690b3f8b 43
AnnaBridge 165:d1b4690b3f8b 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 165:d1b4690b3f8b 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 165:d1b4690b3f8b 46
AnnaBridge 165:d1b4690b3f8b 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 165:d1b4690b3f8b 48 Unions are used for effective representation of core registers.
AnnaBridge 165:d1b4690b3f8b 49
AnnaBridge 165:d1b4690b3f8b 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 165:d1b4690b3f8b 51 Function-like macros are used to allow more efficient code.
AnnaBridge 165:d1b4690b3f8b 52 */
AnnaBridge 165:d1b4690b3f8b 53
AnnaBridge 165:d1b4690b3f8b 54
AnnaBridge 165:d1b4690b3f8b 55 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 56 * CMSIS definitions
AnnaBridge 165:d1b4690b3f8b 57 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 58 /**
AnnaBridge 165:d1b4690b3f8b 59 \ingroup Cortex_ARMv8MBL
AnnaBridge 165:d1b4690b3f8b 60 @{
AnnaBridge 165:d1b4690b3f8b 61 */
AnnaBridge 165:d1b4690b3f8b 62
AnnaBridge 165:d1b4690b3f8b 63 #include "cmsis_version.h"
AnnaBridge 165:d1b4690b3f8b 64
AnnaBridge 165:d1b4690b3f8b 65 /* CMSIS definitions */
AnnaBridge 165:d1b4690b3f8b 66 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 165:d1b4690b3f8b 67 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 165:d1b4690b3f8b 68 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 165:d1b4690b3f8b 69 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 165:d1b4690b3f8b 70
AnnaBridge 165:d1b4690b3f8b 71 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */
AnnaBridge 165:d1b4690b3f8b 72
AnnaBridge 165:d1b4690b3f8b 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 165:d1b4690b3f8b 74 This core does not support an FPU at all
AnnaBridge 165:d1b4690b3f8b 75 */
AnnaBridge 165:d1b4690b3f8b 76 #define __FPU_USED 0U
AnnaBridge 165:d1b4690b3f8b 77
AnnaBridge 165:d1b4690b3f8b 78 #if defined ( __CC_ARM )
AnnaBridge 165:d1b4690b3f8b 79 #if defined __TARGET_FPU_VFP
AnnaBridge 165:d1b4690b3f8b 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 81 #endif
AnnaBridge 165:d1b4690b3f8b 82
AnnaBridge 165:d1b4690b3f8b 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 165:d1b4690b3f8b 84 #if defined __ARM_PCS_VFP
AnnaBridge 165:d1b4690b3f8b 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 86 #endif
AnnaBridge 165:d1b4690b3f8b 87
AnnaBridge 165:d1b4690b3f8b 88 #elif defined ( __GNUC__ )
AnnaBridge 165:d1b4690b3f8b 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 165:d1b4690b3f8b 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 91 #endif
AnnaBridge 165:d1b4690b3f8b 92
AnnaBridge 165:d1b4690b3f8b 93 #elif defined ( __ICCARM__ )
AnnaBridge 165:d1b4690b3f8b 94 #if defined __ARMVFP__
AnnaBridge 165:d1b4690b3f8b 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 96 #endif
AnnaBridge 165:d1b4690b3f8b 97
AnnaBridge 165:d1b4690b3f8b 98 #elif defined ( __TI_ARM__ )
AnnaBridge 165:d1b4690b3f8b 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 165:d1b4690b3f8b 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 101 #endif
AnnaBridge 165:d1b4690b3f8b 102
AnnaBridge 165:d1b4690b3f8b 103 #elif defined ( __TASKING__ )
AnnaBridge 165:d1b4690b3f8b 104 #if defined __FPU_VFP__
AnnaBridge 165:d1b4690b3f8b 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 106 #endif
AnnaBridge 165:d1b4690b3f8b 107
AnnaBridge 165:d1b4690b3f8b 108 #elif defined ( __CSMC__ )
AnnaBridge 165:d1b4690b3f8b 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 165:d1b4690b3f8b 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 165:d1b4690b3f8b 111 #endif
AnnaBridge 165:d1b4690b3f8b 112
AnnaBridge 165:d1b4690b3f8b 113 #endif
AnnaBridge 165:d1b4690b3f8b 114
AnnaBridge 165:d1b4690b3f8b 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 165:d1b4690b3f8b 116
AnnaBridge 165:d1b4690b3f8b 117
AnnaBridge 165:d1b4690b3f8b 118 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 119 }
AnnaBridge 165:d1b4690b3f8b 120 #endif
AnnaBridge 165:d1b4690b3f8b 121
AnnaBridge 165:d1b4690b3f8b 122 #endif /* __CORE_ARMV8MBL_H_GENERIC */
AnnaBridge 165:d1b4690b3f8b 123
AnnaBridge 165:d1b4690b3f8b 124 #ifndef __CMSIS_GENERIC
AnnaBridge 165:d1b4690b3f8b 125
AnnaBridge 165:d1b4690b3f8b 126 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
AnnaBridge 165:d1b4690b3f8b 127 #define __CORE_ARMV8MBL_H_DEPENDANT
AnnaBridge 165:d1b4690b3f8b 128
AnnaBridge 165:d1b4690b3f8b 129 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 130 extern "C" {
AnnaBridge 165:d1b4690b3f8b 131 #endif
AnnaBridge 165:d1b4690b3f8b 132
AnnaBridge 165:d1b4690b3f8b 133 /* check device defines and use defaults */
AnnaBridge 165:d1b4690b3f8b 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 165:d1b4690b3f8b 135 #ifndef __ARMv8MBL_REV
AnnaBridge 165:d1b4690b3f8b 136 #define __ARMv8MBL_REV 0x0000U
AnnaBridge 165:d1b4690b3f8b 137 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 138 #endif
AnnaBridge 165:d1b4690b3f8b 139
AnnaBridge 165:d1b4690b3f8b 140 #ifndef __FPU_PRESENT
AnnaBridge 165:d1b4690b3f8b 141 #define __FPU_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 142 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 143 #endif
AnnaBridge 165:d1b4690b3f8b 144
AnnaBridge 165:d1b4690b3f8b 145 #ifndef __MPU_PRESENT
AnnaBridge 165:d1b4690b3f8b 146 #define __MPU_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 147 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 148 #endif
AnnaBridge 165:d1b4690b3f8b 149
AnnaBridge 165:d1b4690b3f8b 150 #ifndef __SAUREGION_PRESENT
AnnaBridge 165:d1b4690b3f8b 151 #define __SAUREGION_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 153 #endif
AnnaBridge 165:d1b4690b3f8b 154
AnnaBridge 165:d1b4690b3f8b 155 #ifndef __VTOR_PRESENT
AnnaBridge 165:d1b4690b3f8b 156 #define __VTOR_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 158 #endif
AnnaBridge 165:d1b4690b3f8b 159
AnnaBridge 165:d1b4690b3f8b 160 #ifndef __NVIC_PRIO_BITS
AnnaBridge 165:d1b4690b3f8b 161 #define __NVIC_PRIO_BITS 2U
AnnaBridge 165:d1b4690b3f8b 162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 163 #endif
AnnaBridge 165:d1b4690b3f8b 164
AnnaBridge 165:d1b4690b3f8b 165 #ifndef __Vendor_SysTickConfig
AnnaBridge 165:d1b4690b3f8b 166 #define __Vendor_SysTickConfig 0U
AnnaBridge 165:d1b4690b3f8b 167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 168 #endif
AnnaBridge 165:d1b4690b3f8b 169
AnnaBridge 165:d1b4690b3f8b 170 #ifndef __ETM_PRESENT
AnnaBridge 165:d1b4690b3f8b 171 #define __ETM_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 172 #warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 173 #endif
AnnaBridge 165:d1b4690b3f8b 174
AnnaBridge 165:d1b4690b3f8b 175 #ifndef __MTB_PRESENT
AnnaBridge 165:d1b4690b3f8b 176 #define __MTB_PRESENT 0U
AnnaBridge 165:d1b4690b3f8b 177 #warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge 165:d1b4690b3f8b 178 #endif
AnnaBridge 165:d1b4690b3f8b 179
AnnaBridge 165:d1b4690b3f8b 180 #endif
AnnaBridge 165:d1b4690b3f8b 181
AnnaBridge 165:d1b4690b3f8b 182 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 165:d1b4690b3f8b 183 /**
AnnaBridge 165:d1b4690b3f8b 184 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 165:d1b4690b3f8b 185
AnnaBridge 165:d1b4690b3f8b 186 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 165:d1b4690b3f8b 187 \li to specify the access to peripheral variables.
AnnaBridge 165:d1b4690b3f8b 188 \li for automatic generation of peripheral register debug information.
AnnaBridge 165:d1b4690b3f8b 189 */
AnnaBridge 165:d1b4690b3f8b 190 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 191 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 165:d1b4690b3f8b 192 #else
AnnaBridge 165:d1b4690b3f8b 193 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 165:d1b4690b3f8b 194 #endif
AnnaBridge 165:d1b4690b3f8b 195 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 165:d1b4690b3f8b 196 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 165:d1b4690b3f8b 197
AnnaBridge 165:d1b4690b3f8b 198 /* following defines should be used for structure members */
AnnaBridge 165:d1b4690b3f8b 199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 200 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 165:d1b4690b3f8b 202
AnnaBridge 165:d1b4690b3f8b 203 /*@} end of group ARMv8MBL */
AnnaBridge 165:d1b4690b3f8b 204
AnnaBridge 165:d1b4690b3f8b 205
AnnaBridge 165:d1b4690b3f8b 206
AnnaBridge 165:d1b4690b3f8b 207 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 208 * Register Abstraction
AnnaBridge 165:d1b4690b3f8b 209 Core Register contain:
AnnaBridge 165:d1b4690b3f8b 210 - Core Register
AnnaBridge 165:d1b4690b3f8b 211 - Core NVIC Register
AnnaBridge 165:d1b4690b3f8b 212 - Core SCB Register
AnnaBridge 165:d1b4690b3f8b 213 - Core SysTick Register
AnnaBridge 165:d1b4690b3f8b 214 - Core Debug Register
AnnaBridge 165:d1b4690b3f8b 215 - Core MPU Register
AnnaBridge 165:d1b4690b3f8b 216 - Core SAU Register
AnnaBridge 165:d1b4690b3f8b 217 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 218 /**
AnnaBridge 165:d1b4690b3f8b 219 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 165:d1b4690b3f8b 220 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 165:d1b4690b3f8b 221 */
AnnaBridge 165:d1b4690b3f8b 222
AnnaBridge 165:d1b4690b3f8b 223 /**
AnnaBridge 165:d1b4690b3f8b 224 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 225 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 165:d1b4690b3f8b 226 \brief Core Register type definitions.
AnnaBridge 165:d1b4690b3f8b 227 @{
AnnaBridge 165:d1b4690b3f8b 228 */
AnnaBridge 165:d1b4690b3f8b 229
AnnaBridge 165:d1b4690b3f8b 230 /**
AnnaBridge 165:d1b4690b3f8b 231 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 165:d1b4690b3f8b 232 */
AnnaBridge 165:d1b4690b3f8b 233 typedef union
AnnaBridge 165:d1b4690b3f8b 234 {
AnnaBridge 165:d1b4690b3f8b 235 struct
AnnaBridge 165:d1b4690b3f8b 236 {
AnnaBridge 165:d1b4690b3f8b 237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 165:d1b4690b3f8b 238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 165:d1b4690b3f8b 239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 165:d1b4690b3f8b 240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 165:d1b4690b3f8b 241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 165:d1b4690b3f8b 242 } b; /*!< Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 243 uint32_t w; /*!< Type used for word access */
AnnaBridge 165:d1b4690b3f8b 244 } APSR_Type;
AnnaBridge 165:d1b4690b3f8b 245
AnnaBridge 165:d1b4690b3f8b 246 /* APSR Register Definitions */
AnnaBridge 165:d1b4690b3f8b 247 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 165:d1b4690b3f8b 248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 165:d1b4690b3f8b 249
AnnaBridge 165:d1b4690b3f8b 250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 165:d1b4690b3f8b 251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 165:d1b4690b3f8b 252
AnnaBridge 165:d1b4690b3f8b 253 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 165:d1b4690b3f8b 254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 165:d1b4690b3f8b 255
AnnaBridge 165:d1b4690b3f8b 256 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 165:d1b4690b3f8b 257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 165:d1b4690b3f8b 258
AnnaBridge 165:d1b4690b3f8b 259
AnnaBridge 165:d1b4690b3f8b 260 /**
AnnaBridge 165:d1b4690b3f8b 261 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 165:d1b4690b3f8b 262 */
AnnaBridge 165:d1b4690b3f8b 263 typedef union
AnnaBridge 165:d1b4690b3f8b 264 {
AnnaBridge 165:d1b4690b3f8b 265 struct
AnnaBridge 165:d1b4690b3f8b 266 {
AnnaBridge 165:d1b4690b3f8b 267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 165:d1b4690b3f8b 268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 165:d1b4690b3f8b 269 } b; /*!< Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 270 uint32_t w; /*!< Type used for word access */
AnnaBridge 165:d1b4690b3f8b 271 } IPSR_Type;
AnnaBridge 165:d1b4690b3f8b 272
AnnaBridge 165:d1b4690b3f8b 273 /* IPSR Register Definitions */
AnnaBridge 165:d1b4690b3f8b 274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 165:d1b4690b3f8b 275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 165:d1b4690b3f8b 276
AnnaBridge 165:d1b4690b3f8b 277
AnnaBridge 165:d1b4690b3f8b 278 /**
AnnaBridge 165:d1b4690b3f8b 279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 165:d1b4690b3f8b 280 */
AnnaBridge 165:d1b4690b3f8b 281 typedef union
AnnaBridge 165:d1b4690b3f8b 282 {
AnnaBridge 165:d1b4690b3f8b 283 struct
AnnaBridge 165:d1b4690b3f8b 284 {
AnnaBridge 165:d1b4690b3f8b 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 165:d1b4690b3f8b 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 165:d1b4690b3f8b 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 165:d1b4690b3f8b 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 165:d1b4690b3f8b 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 165:d1b4690b3f8b 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 165:d1b4690b3f8b 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 165:d1b4690b3f8b 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 165:d1b4690b3f8b 293 } b; /*!< Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 294 uint32_t w; /*!< Type used for word access */
AnnaBridge 165:d1b4690b3f8b 295 } xPSR_Type;
AnnaBridge 165:d1b4690b3f8b 296
AnnaBridge 165:d1b4690b3f8b 297 /* xPSR Register Definitions */
AnnaBridge 165:d1b4690b3f8b 298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 165:d1b4690b3f8b 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 165:d1b4690b3f8b 300
AnnaBridge 165:d1b4690b3f8b 301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 165:d1b4690b3f8b 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 165:d1b4690b3f8b 303
AnnaBridge 165:d1b4690b3f8b 304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 165:d1b4690b3f8b 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 165:d1b4690b3f8b 306
AnnaBridge 165:d1b4690b3f8b 307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 165:d1b4690b3f8b 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 165:d1b4690b3f8b 309
AnnaBridge 165:d1b4690b3f8b 310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 165:d1b4690b3f8b 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 165:d1b4690b3f8b 312
AnnaBridge 165:d1b4690b3f8b 313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 165:d1b4690b3f8b 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 165:d1b4690b3f8b 315
AnnaBridge 165:d1b4690b3f8b 316
AnnaBridge 165:d1b4690b3f8b 317 /**
AnnaBridge 165:d1b4690b3f8b 318 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 165:d1b4690b3f8b 319 */
AnnaBridge 165:d1b4690b3f8b 320 typedef union
AnnaBridge 165:d1b4690b3f8b 321 {
AnnaBridge 165:d1b4690b3f8b 322 struct
AnnaBridge 165:d1b4690b3f8b 323 {
AnnaBridge 165:d1b4690b3f8b 324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 165:d1b4690b3f8b 325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
AnnaBridge 165:d1b4690b3f8b 326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 165:d1b4690b3f8b 327 } b; /*!< Structure used for bit access */
AnnaBridge 165:d1b4690b3f8b 328 uint32_t w; /*!< Type used for word access */
AnnaBridge 165:d1b4690b3f8b 329 } CONTROL_Type;
AnnaBridge 165:d1b4690b3f8b 330
AnnaBridge 165:d1b4690b3f8b 331 /* CONTROL Register Definitions */
AnnaBridge 165:d1b4690b3f8b 332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 165:d1b4690b3f8b 333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 165:d1b4690b3f8b 334
AnnaBridge 165:d1b4690b3f8b 335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 165:d1b4690b3f8b 336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 165:d1b4690b3f8b 337
AnnaBridge 165:d1b4690b3f8b 338 /*@} end of group CMSIS_CORE */
AnnaBridge 165:d1b4690b3f8b 339
AnnaBridge 165:d1b4690b3f8b 340
AnnaBridge 165:d1b4690b3f8b 341 /**
AnnaBridge 165:d1b4690b3f8b 342 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 165:d1b4690b3f8b 344 \brief Type definitions for the NVIC Registers
AnnaBridge 165:d1b4690b3f8b 345 @{
AnnaBridge 165:d1b4690b3f8b 346 */
AnnaBridge 165:d1b4690b3f8b 347
AnnaBridge 165:d1b4690b3f8b 348 /**
AnnaBridge 165:d1b4690b3f8b 349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 165:d1b4690b3f8b 350 */
AnnaBridge 165:d1b4690b3f8b 351 typedef struct
AnnaBridge 165:d1b4690b3f8b 352 {
AnnaBridge 165:d1b4690b3f8b 353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 165:d1b4690b3f8b 354 uint32_t RESERVED0[16U];
AnnaBridge 165:d1b4690b3f8b 355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 165:d1b4690b3f8b 356 uint32_t RSERVED1[16U];
AnnaBridge 165:d1b4690b3f8b 357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 165:d1b4690b3f8b 358 uint32_t RESERVED2[16U];
AnnaBridge 165:d1b4690b3f8b 359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 165:d1b4690b3f8b 360 uint32_t RESERVED3[16U];
AnnaBridge 165:d1b4690b3f8b 361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 165:d1b4690b3f8b 362 uint32_t RESERVED4[16U];
AnnaBridge 165:d1b4690b3f8b 363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
AnnaBridge 165:d1b4690b3f8b 364 uint32_t RESERVED5[16U];
AnnaBridge 165:d1b4690b3f8b 365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 165:d1b4690b3f8b 366 } NVIC_Type;
AnnaBridge 165:d1b4690b3f8b 367
AnnaBridge 165:d1b4690b3f8b 368 /*@} end of group CMSIS_NVIC */
AnnaBridge 165:d1b4690b3f8b 369
AnnaBridge 165:d1b4690b3f8b 370
AnnaBridge 165:d1b4690b3f8b 371 /**
AnnaBridge 165:d1b4690b3f8b 372 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 373 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 165:d1b4690b3f8b 374 \brief Type definitions for the System Control Block Registers
AnnaBridge 165:d1b4690b3f8b 375 @{
AnnaBridge 165:d1b4690b3f8b 376 */
AnnaBridge 165:d1b4690b3f8b 377
AnnaBridge 165:d1b4690b3f8b 378 /**
AnnaBridge 165:d1b4690b3f8b 379 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 165:d1b4690b3f8b 380 */
AnnaBridge 165:d1b4690b3f8b 381 typedef struct
AnnaBridge 165:d1b4690b3f8b 382 {
AnnaBridge 165:d1b4690b3f8b 383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 165:d1b4690b3f8b 384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 165:d1b4690b3f8b 385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 165:d1b4690b3f8b 387 #else
AnnaBridge 165:d1b4690b3f8b 388 uint32_t RESERVED0;
AnnaBridge 165:d1b4690b3f8b 389 #endif
AnnaBridge 165:d1b4690b3f8b 390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 165:d1b4690b3f8b 391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 165:d1b4690b3f8b 392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 165:d1b4690b3f8b 393 uint32_t RESERVED1;
AnnaBridge 165:d1b4690b3f8b 394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 165:d1b4690b3f8b 395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 165:d1b4690b3f8b 396 } SCB_Type;
AnnaBridge 165:d1b4690b3f8b 397
AnnaBridge 165:d1b4690b3f8b 398 /* SCB CPUID Register Definitions */
AnnaBridge 165:d1b4690b3f8b 399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 165:d1b4690b3f8b 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 165:d1b4690b3f8b 401
AnnaBridge 165:d1b4690b3f8b 402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 165:d1b4690b3f8b 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 165:d1b4690b3f8b 404
AnnaBridge 165:d1b4690b3f8b 405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 165:d1b4690b3f8b 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 165:d1b4690b3f8b 407
AnnaBridge 165:d1b4690b3f8b 408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 165:d1b4690b3f8b 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 165:d1b4690b3f8b 410
AnnaBridge 165:d1b4690b3f8b 411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 165:d1b4690b3f8b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 165:d1b4690b3f8b 413
AnnaBridge 165:d1b4690b3f8b 414 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 165:d1b4690b3f8b 415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
AnnaBridge 165:d1b4690b3f8b 416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
AnnaBridge 165:d1b4690b3f8b 417
AnnaBridge 165:d1b4690b3f8b 418 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
AnnaBridge 165:d1b4690b3f8b 419 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
AnnaBridge 165:d1b4690b3f8b 420
AnnaBridge 165:d1b4690b3f8b 421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 165:d1b4690b3f8b 422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 165:d1b4690b3f8b 423
AnnaBridge 165:d1b4690b3f8b 424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 165:d1b4690b3f8b 425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 165:d1b4690b3f8b 426
AnnaBridge 165:d1b4690b3f8b 427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 165:d1b4690b3f8b 428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 165:d1b4690b3f8b 429
AnnaBridge 165:d1b4690b3f8b 430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 165:d1b4690b3f8b 431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 165:d1b4690b3f8b 432
AnnaBridge 165:d1b4690b3f8b 433 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
AnnaBridge 165:d1b4690b3f8b 434 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
AnnaBridge 165:d1b4690b3f8b 435
AnnaBridge 165:d1b4690b3f8b 436 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 165:d1b4690b3f8b 437 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 165:d1b4690b3f8b 438
AnnaBridge 165:d1b4690b3f8b 439 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 165:d1b4690b3f8b 440 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 165:d1b4690b3f8b 441
AnnaBridge 165:d1b4690b3f8b 442 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 165:d1b4690b3f8b 443 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 165:d1b4690b3f8b 444
AnnaBridge 165:d1b4690b3f8b 445 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 165:d1b4690b3f8b 446 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 165:d1b4690b3f8b 447
AnnaBridge 165:d1b4690b3f8b 448 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 165:d1b4690b3f8b 449 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 165:d1b4690b3f8b 450
AnnaBridge 165:d1b4690b3f8b 451 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 452 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 165:d1b4690b3f8b 453 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 165:d1b4690b3f8b 454 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 165:d1b4690b3f8b 455 #endif
AnnaBridge 165:d1b4690b3f8b 456
AnnaBridge 165:d1b4690b3f8b 457 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 458 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 165:d1b4690b3f8b 459 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 165:d1b4690b3f8b 460
AnnaBridge 165:d1b4690b3f8b 461 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 165:d1b4690b3f8b 462 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 165:d1b4690b3f8b 463
AnnaBridge 165:d1b4690b3f8b 464 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 165:d1b4690b3f8b 465 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 165:d1b4690b3f8b 466
AnnaBridge 165:d1b4690b3f8b 467 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
AnnaBridge 165:d1b4690b3f8b 468 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
AnnaBridge 165:d1b4690b3f8b 469
AnnaBridge 165:d1b4690b3f8b 470 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
AnnaBridge 165:d1b4690b3f8b 471 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
AnnaBridge 165:d1b4690b3f8b 472
AnnaBridge 165:d1b4690b3f8b 473 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
AnnaBridge 165:d1b4690b3f8b 474 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
AnnaBridge 165:d1b4690b3f8b 475
AnnaBridge 165:d1b4690b3f8b 476 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 165:d1b4690b3f8b 477 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 165:d1b4690b3f8b 478
AnnaBridge 165:d1b4690b3f8b 479 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 165:d1b4690b3f8b 480 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 165:d1b4690b3f8b 481
AnnaBridge 165:d1b4690b3f8b 482 /* SCB System Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 483 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 165:d1b4690b3f8b 484 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 165:d1b4690b3f8b 485
AnnaBridge 165:d1b4690b3f8b 486 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
AnnaBridge 165:d1b4690b3f8b 487 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
AnnaBridge 165:d1b4690b3f8b 488
AnnaBridge 165:d1b4690b3f8b 489 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 165:d1b4690b3f8b 490 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 165:d1b4690b3f8b 491
AnnaBridge 165:d1b4690b3f8b 492 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 165:d1b4690b3f8b 493 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 165:d1b4690b3f8b 494
AnnaBridge 165:d1b4690b3f8b 495 /* SCB Configuration Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 496 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
AnnaBridge 165:d1b4690b3f8b 497 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
AnnaBridge 165:d1b4690b3f8b 498
AnnaBridge 165:d1b4690b3f8b 499 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
AnnaBridge 165:d1b4690b3f8b 500 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
AnnaBridge 165:d1b4690b3f8b 501
AnnaBridge 165:d1b4690b3f8b 502 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
AnnaBridge 165:d1b4690b3f8b 503 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
AnnaBridge 165:d1b4690b3f8b 504
AnnaBridge 165:d1b4690b3f8b 505 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
AnnaBridge 165:d1b4690b3f8b 506 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
AnnaBridge 165:d1b4690b3f8b 507
AnnaBridge 165:d1b4690b3f8b 508 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 165:d1b4690b3f8b 509 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 165:d1b4690b3f8b 510
AnnaBridge 165:d1b4690b3f8b 511 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 165:d1b4690b3f8b 512 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 165:d1b4690b3f8b 513
AnnaBridge 165:d1b4690b3f8b 514 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 165:d1b4690b3f8b 515 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 165:d1b4690b3f8b 516
AnnaBridge 165:d1b4690b3f8b 517 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 165:d1b4690b3f8b 518 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 165:d1b4690b3f8b 519
AnnaBridge 165:d1b4690b3f8b 520 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 165:d1b4690b3f8b 521 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
AnnaBridge 165:d1b4690b3f8b 522 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
AnnaBridge 165:d1b4690b3f8b 523
AnnaBridge 165:d1b4690b3f8b 524 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 165:d1b4690b3f8b 525 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 165:d1b4690b3f8b 526
AnnaBridge 165:d1b4690b3f8b 527 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 165:d1b4690b3f8b 528 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 165:d1b4690b3f8b 529
AnnaBridge 165:d1b4690b3f8b 530 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 165:d1b4690b3f8b 531 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 165:d1b4690b3f8b 532
AnnaBridge 165:d1b4690b3f8b 533 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 165:d1b4690b3f8b 534 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 165:d1b4690b3f8b 535
AnnaBridge 165:d1b4690b3f8b 536 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
AnnaBridge 165:d1b4690b3f8b 537 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
AnnaBridge 165:d1b4690b3f8b 538
AnnaBridge 165:d1b4690b3f8b 539 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
AnnaBridge 165:d1b4690b3f8b 540 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
AnnaBridge 165:d1b4690b3f8b 541
AnnaBridge 165:d1b4690b3f8b 542 /*@} end of group CMSIS_SCB */
AnnaBridge 165:d1b4690b3f8b 543
AnnaBridge 165:d1b4690b3f8b 544
AnnaBridge 165:d1b4690b3f8b 545 /**
AnnaBridge 165:d1b4690b3f8b 546 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 547 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 165:d1b4690b3f8b 548 \brief Type definitions for the System Timer Registers.
AnnaBridge 165:d1b4690b3f8b 549 @{
AnnaBridge 165:d1b4690b3f8b 550 */
AnnaBridge 165:d1b4690b3f8b 551
AnnaBridge 165:d1b4690b3f8b 552 /**
AnnaBridge 165:d1b4690b3f8b 553 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 165:d1b4690b3f8b 554 */
AnnaBridge 165:d1b4690b3f8b 555 typedef struct
AnnaBridge 165:d1b4690b3f8b 556 {
AnnaBridge 165:d1b4690b3f8b 557 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 165:d1b4690b3f8b 558 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 165:d1b4690b3f8b 559 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 165:d1b4690b3f8b 560 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 165:d1b4690b3f8b 561 } SysTick_Type;
AnnaBridge 165:d1b4690b3f8b 562
AnnaBridge 165:d1b4690b3f8b 563 /* SysTick Control / Status Register Definitions */
AnnaBridge 165:d1b4690b3f8b 564 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 165:d1b4690b3f8b 565 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 165:d1b4690b3f8b 566
AnnaBridge 165:d1b4690b3f8b 567 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 165:d1b4690b3f8b 568 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 165:d1b4690b3f8b 569
AnnaBridge 165:d1b4690b3f8b 570 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 165:d1b4690b3f8b 571 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 165:d1b4690b3f8b 572
AnnaBridge 165:d1b4690b3f8b 573 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 165:d1b4690b3f8b 574 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 165:d1b4690b3f8b 575
AnnaBridge 165:d1b4690b3f8b 576 /* SysTick Reload Register Definitions */
AnnaBridge 165:d1b4690b3f8b 577 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 165:d1b4690b3f8b 578 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 165:d1b4690b3f8b 579
AnnaBridge 165:d1b4690b3f8b 580 /* SysTick Current Register Definitions */
AnnaBridge 165:d1b4690b3f8b 581 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 165:d1b4690b3f8b 582 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 165:d1b4690b3f8b 583
AnnaBridge 165:d1b4690b3f8b 584 /* SysTick Calibration Register Definitions */
AnnaBridge 165:d1b4690b3f8b 585 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 165:d1b4690b3f8b 586 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 165:d1b4690b3f8b 587
AnnaBridge 165:d1b4690b3f8b 588 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 165:d1b4690b3f8b 589 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 165:d1b4690b3f8b 590
AnnaBridge 165:d1b4690b3f8b 591 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 165:d1b4690b3f8b 592 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 165:d1b4690b3f8b 593
AnnaBridge 165:d1b4690b3f8b 594 /*@} end of group CMSIS_SysTick */
AnnaBridge 165:d1b4690b3f8b 595
AnnaBridge 165:d1b4690b3f8b 596
AnnaBridge 165:d1b4690b3f8b 597 /**
AnnaBridge 165:d1b4690b3f8b 598 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 599 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 165:d1b4690b3f8b 600 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 165:d1b4690b3f8b 601 @{
AnnaBridge 165:d1b4690b3f8b 602 */
AnnaBridge 165:d1b4690b3f8b 603
AnnaBridge 165:d1b4690b3f8b 604 /**
AnnaBridge 165:d1b4690b3f8b 605 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 165:d1b4690b3f8b 606 */
AnnaBridge 165:d1b4690b3f8b 607 typedef struct
AnnaBridge 165:d1b4690b3f8b 608 {
AnnaBridge 165:d1b4690b3f8b 609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 165:d1b4690b3f8b 610 uint32_t RESERVED0[6U];
AnnaBridge 165:d1b4690b3f8b 611 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 165:d1b4690b3f8b 612 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 165:d1b4690b3f8b 613 uint32_t RESERVED1[1U];
AnnaBridge 165:d1b4690b3f8b 614 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 165:d1b4690b3f8b 615 uint32_t RESERVED2[1U];
AnnaBridge 165:d1b4690b3f8b 616 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 165:d1b4690b3f8b 617 uint32_t RESERVED3[1U];
AnnaBridge 165:d1b4690b3f8b 618 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 165:d1b4690b3f8b 619 uint32_t RESERVED4[1U];
AnnaBridge 165:d1b4690b3f8b 620 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 165:d1b4690b3f8b 621 uint32_t RESERVED5[1U];
AnnaBridge 165:d1b4690b3f8b 622 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 165:d1b4690b3f8b 623 uint32_t RESERVED6[1U];
AnnaBridge 165:d1b4690b3f8b 624 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 165:d1b4690b3f8b 625 uint32_t RESERVED7[1U];
AnnaBridge 165:d1b4690b3f8b 626 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 165:d1b4690b3f8b 627 uint32_t RESERVED8[1U];
AnnaBridge 165:d1b4690b3f8b 628 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
AnnaBridge 165:d1b4690b3f8b 629 uint32_t RESERVED9[1U];
AnnaBridge 165:d1b4690b3f8b 630 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
AnnaBridge 165:d1b4690b3f8b 631 uint32_t RESERVED10[1U];
AnnaBridge 165:d1b4690b3f8b 632 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
AnnaBridge 165:d1b4690b3f8b 633 uint32_t RESERVED11[1U];
AnnaBridge 165:d1b4690b3f8b 634 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
AnnaBridge 165:d1b4690b3f8b 635 uint32_t RESERVED12[1U];
AnnaBridge 165:d1b4690b3f8b 636 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
AnnaBridge 165:d1b4690b3f8b 637 uint32_t RESERVED13[1U];
AnnaBridge 165:d1b4690b3f8b 638 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
AnnaBridge 165:d1b4690b3f8b 639 uint32_t RESERVED14[1U];
AnnaBridge 165:d1b4690b3f8b 640 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
AnnaBridge 165:d1b4690b3f8b 641 uint32_t RESERVED15[1U];
AnnaBridge 165:d1b4690b3f8b 642 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
AnnaBridge 165:d1b4690b3f8b 643 uint32_t RESERVED16[1U];
AnnaBridge 165:d1b4690b3f8b 644 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
AnnaBridge 165:d1b4690b3f8b 645 uint32_t RESERVED17[1U];
AnnaBridge 165:d1b4690b3f8b 646 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
AnnaBridge 165:d1b4690b3f8b 647 uint32_t RESERVED18[1U];
AnnaBridge 165:d1b4690b3f8b 648 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
AnnaBridge 165:d1b4690b3f8b 649 uint32_t RESERVED19[1U];
AnnaBridge 165:d1b4690b3f8b 650 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
AnnaBridge 165:d1b4690b3f8b 651 uint32_t RESERVED20[1U];
AnnaBridge 165:d1b4690b3f8b 652 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
AnnaBridge 165:d1b4690b3f8b 653 uint32_t RESERVED21[1U];
AnnaBridge 165:d1b4690b3f8b 654 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
AnnaBridge 165:d1b4690b3f8b 655 uint32_t RESERVED22[1U];
AnnaBridge 165:d1b4690b3f8b 656 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
AnnaBridge 165:d1b4690b3f8b 657 uint32_t RESERVED23[1U];
AnnaBridge 165:d1b4690b3f8b 658 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
AnnaBridge 165:d1b4690b3f8b 659 uint32_t RESERVED24[1U];
AnnaBridge 165:d1b4690b3f8b 660 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
AnnaBridge 165:d1b4690b3f8b 661 uint32_t RESERVED25[1U];
AnnaBridge 165:d1b4690b3f8b 662 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
AnnaBridge 165:d1b4690b3f8b 663 uint32_t RESERVED26[1U];
AnnaBridge 165:d1b4690b3f8b 664 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
AnnaBridge 165:d1b4690b3f8b 665 uint32_t RESERVED27[1U];
AnnaBridge 165:d1b4690b3f8b 666 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
AnnaBridge 165:d1b4690b3f8b 667 uint32_t RESERVED28[1U];
AnnaBridge 165:d1b4690b3f8b 668 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
AnnaBridge 165:d1b4690b3f8b 669 uint32_t RESERVED29[1U];
AnnaBridge 165:d1b4690b3f8b 670 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
AnnaBridge 165:d1b4690b3f8b 671 uint32_t RESERVED30[1U];
AnnaBridge 165:d1b4690b3f8b 672 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
AnnaBridge 165:d1b4690b3f8b 673 uint32_t RESERVED31[1U];
AnnaBridge 165:d1b4690b3f8b 674 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
AnnaBridge 165:d1b4690b3f8b 675 } DWT_Type;
AnnaBridge 165:d1b4690b3f8b 676
AnnaBridge 165:d1b4690b3f8b 677 /* DWT Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 678 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 165:d1b4690b3f8b 679 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 165:d1b4690b3f8b 680
AnnaBridge 165:d1b4690b3f8b 681 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 165:d1b4690b3f8b 682 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 165:d1b4690b3f8b 683
AnnaBridge 165:d1b4690b3f8b 684 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 165:d1b4690b3f8b 685 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 165:d1b4690b3f8b 686
AnnaBridge 165:d1b4690b3f8b 687 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 165:d1b4690b3f8b 688 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 165:d1b4690b3f8b 689
AnnaBridge 165:d1b4690b3f8b 690 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 165:d1b4690b3f8b 691 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 165:d1b4690b3f8b 692
AnnaBridge 165:d1b4690b3f8b 693 /* DWT Comparator Function Register Definitions */
AnnaBridge 165:d1b4690b3f8b 694 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
AnnaBridge 165:d1b4690b3f8b 695 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
AnnaBridge 165:d1b4690b3f8b 696
AnnaBridge 165:d1b4690b3f8b 697 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 165:d1b4690b3f8b 698 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 165:d1b4690b3f8b 699
AnnaBridge 165:d1b4690b3f8b 700 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 165:d1b4690b3f8b 701 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 165:d1b4690b3f8b 702
AnnaBridge 165:d1b4690b3f8b 703 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
AnnaBridge 165:d1b4690b3f8b 704 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
AnnaBridge 165:d1b4690b3f8b 705
AnnaBridge 165:d1b4690b3f8b 706 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
AnnaBridge 165:d1b4690b3f8b 707 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
AnnaBridge 165:d1b4690b3f8b 708
AnnaBridge 165:d1b4690b3f8b 709 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 165:d1b4690b3f8b 710
AnnaBridge 165:d1b4690b3f8b 711
AnnaBridge 165:d1b4690b3f8b 712 /**
AnnaBridge 165:d1b4690b3f8b 713 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 714 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 165:d1b4690b3f8b 715 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 165:d1b4690b3f8b 716 @{
AnnaBridge 165:d1b4690b3f8b 717 */
AnnaBridge 165:d1b4690b3f8b 718
AnnaBridge 165:d1b4690b3f8b 719 /**
AnnaBridge 165:d1b4690b3f8b 720 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 165:d1b4690b3f8b 721 */
AnnaBridge 165:d1b4690b3f8b 722 typedef struct
AnnaBridge 165:d1b4690b3f8b 723 {
AnnaBridge 165:d1b4690b3f8b 724 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 165:d1b4690b3f8b 725 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 165:d1b4690b3f8b 726 uint32_t RESERVED0[2U];
AnnaBridge 165:d1b4690b3f8b 727 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 165:d1b4690b3f8b 728 uint32_t RESERVED1[55U];
AnnaBridge 165:d1b4690b3f8b 729 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 165:d1b4690b3f8b 730 uint32_t RESERVED2[131U];
AnnaBridge 165:d1b4690b3f8b 731 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 165:d1b4690b3f8b 732 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 165:d1b4690b3f8b 733 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 165:d1b4690b3f8b 734 uint32_t RESERVED3[759U];
AnnaBridge 165:d1b4690b3f8b 735 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 165:d1b4690b3f8b 736 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 165:d1b4690b3f8b 737 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 165:d1b4690b3f8b 738 uint32_t RESERVED4[1U];
AnnaBridge 165:d1b4690b3f8b 739 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 165:d1b4690b3f8b 740 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 165:d1b4690b3f8b 741 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 165:d1b4690b3f8b 742 uint32_t RESERVED5[39U];
AnnaBridge 165:d1b4690b3f8b 743 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 165:d1b4690b3f8b 744 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 165:d1b4690b3f8b 745 uint32_t RESERVED7[8U];
AnnaBridge 165:d1b4690b3f8b 746 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 165:d1b4690b3f8b 747 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 165:d1b4690b3f8b 748 } TPI_Type;
AnnaBridge 165:d1b4690b3f8b 749
AnnaBridge 165:d1b4690b3f8b 750 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 165:d1b4690b3f8b 751 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 165:d1b4690b3f8b 752 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 165:d1b4690b3f8b 753
AnnaBridge 165:d1b4690b3f8b 754 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 165:d1b4690b3f8b 755 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 165:d1b4690b3f8b 756 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 165:d1b4690b3f8b 757
AnnaBridge 165:d1b4690b3f8b 758 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 165:d1b4690b3f8b 759 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 165:d1b4690b3f8b 760 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 165:d1b4690b3f8b 761
AnnaBridge 165:d1b4690b3f8b 762 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 165:d1b4690b3f8b 763 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 165:d1b4690b3f8b 764
AnnaBridge 165:d1b4690b3f8b 765 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 165:d1b4690b3f8b 766 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 165:d1b4690b3f8b 767
AnnaBridge 165:d1b4690b3f8b 768 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 165:d1b4690b3f8b 769 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 165:d1b4690b3f8b 770
AnnaBridge 165:d1b4690b3f8b 771 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 772 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 165:d1b4690b3f8b 773 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 165:d1b4690b3f8b 774
AnnaBridge 165:d1b4690b3f8b 775 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 165:d1b4690b3f8b 776 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 165:d1b4690b3f8b 777
AnnaBridge 165:d1b4690b3f8b 778 /* TPI TRIGGER Register Definitions */
AnnaBridge 165:d1b4690b3f8b 779 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 165:d1b4690b3f8b 780 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 165:d1b4690b3f8b 781
AnnaBridge 165:d1b4690b3f8b 782 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 165:d1b4690b3f8b 783 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 165:d1b4690b3f8b 784 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 165:d1b4690b3f8b 785
AnnaBridge 165:d1b4690b3f8b 786 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 165:d1b4690b3f8b 787 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 165:d1b4690b3f8b 788
AnnaBridge 165:d1b4690b3f8b 789 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 165:d1b4690b3f8b 790 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 165:d1b4690b3f8b 791
AnnaBridge 165:d1b4690b3f8b 792 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 165:d1b4690b3f8b 793 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 165:d1b4690b3f8b 794
AnnaBridge 165:d1b4690b3f8b 795 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 165:d1b4690b3f8b 796 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 165:d1b4690b3f8b 797
AnnaBridge 165:d1b4690b3f8b 798 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 165:d1b4690b3f8b 799 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 165:d1b4690b3f8b 800
AnnaBridge 165:d1b4690b3f8b 801 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 165:d1b4690b3f8b 802 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 165:d1b4690b3f8b 803
AnnaBridge 165:d1b4690b3f8b 804 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 165:d1b4690b3f8b 805 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 165:d1b4690b3f8b 806 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 165:d1b4690b3f8b 807
AnnaBridge 165:d1b4690b3f8b 808 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 165:d1b4690b3f8b 809 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 165:d1b4690b3f8b 810 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 165:d1b4690b3f8b 811
AnnaBridge 165:d1b4690b3f8b 812 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 165:d1b4690b3f8b 813 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 165:d1b4690b3f8b 814
AnnaBridge 165:d1b4690b3f8b 815 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 165:d1b4690b3f8b 816 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 165:d1b4690b3f8b 817
AnnaBridge 165:d1b4690b3f8b 818 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 165:d1b4690b3f8b 819 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 165:d1b4690b3f8b 820
AnnaBridge 165:d1b4690b3f8b 821 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 165:d1b4690b3f8b 822 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 165:d1b4690b3f8b 823
AnnaBridge 165:d1b4690b3f8b 824 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 165:d1b4690b3f8b 825 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 165:d1b4690b3f8b 826
AnnaBridge 165:d1b4690b3f8b 827 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 165:d1b4690b3f8b 828 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 165:d1b4690b3f8b 829
AnnaBridge 165:d1b4690b3f8b 830 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 165:d1b4690b3f8b 831 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 165:d1b4690b3f8b 832 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 165:d1b4690b3f8b 833
AnnaBridge 165:d1b4690b3f8b 834 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 835 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 165:d1b4690b3f8b 836 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 165:d1b4690b3f8b 837
AnnaBridge 165:d1b4690b3f8b 838 /* TPI DEVID Register Definitions */
AnnaBridge 165:d1b4690b3f8b 839 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 165:d1b4690b3f8b 840 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 165:d1b4690b3f8b 841
AnnaBridge 165:d1b4690b3f8b 842 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 165:d1b4690b3f8b 843 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 165:d1b4690b3f8b 844
AnnaBridge 165:d1b4690b3f8b 845 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 165:d1b4690b3f8b 846 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 165:d1b4690b3f8b 847
AnnaBridge 165:d1b4690b3f8b 848 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 165:d1b4690b3f8b 849 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 165:d1b4690b3f8b 850
AnnaBridge 165:d1b4690b3f8b 851 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 165:d1b4690b3f8b 852 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 165:d1b4690b3f8b 853
AnnaBridge 165:d1b4690b3f8b 854 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 165:d1b4690b3f8b 855 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 165:d1b4690b3f8b 856
AnnaBridge 165:d1b4690b3f8b 857 /* TPI DEVTYPE Register Definitions */
AnnaBridge 165:d1b4690b3f8b 858 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 165:d1b4690b3f8b 859 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 165:d1b4690b3f8b 860
AnnaBridge 165:d1b4690b3f8b 861 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 165:d1b4690b3f8b 862 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 165:d1b4690b3f8b 863
AnnaBridge 165:d1b4690b3f8b 864 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 165:d1b4690b3f8b 865
AnnaBridge 165:d1b4690b3f8b 866
AnnaBridge 165:d1b4690b3f8b 867 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 868 /**
AnnaBridge 165:d1b4690b3f8b 869 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 870 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 165:d1b4690b3f8b 871 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 165:d1b4690b3f8b 872 @{
AnnaBridge 165:d1b4690b3f8b 873 */
AnnaBridge 165:d1b4690b3f8b 874
AnnaBridge 165:d1b4690b3f8b 875 /**
AnnaBridge 165:d1b4690b3f8b 876 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 165:d1b4690b3f8b 877 */
AnnaBridge 165:d1b4690b3f8b 878 typedef struct
AnnaBridge 165:d1b4690b3f8b 879 {
AnnaBridge 165:d1b4690b3f8b 880 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 165:d1b4690b3f8b 881 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 165:d1b4690b3f8b 882 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
AnnaBridge 165:d1b4690b3f8b 883 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 165:d1b4690b3f8b 884 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
AnnaBridge 165:d1b4690b3f8b 885 uint32_t RESERVED0[7U];
AnnaBridge 165:d1b4690b3f8b 886 union {
AnnaBridge 165:d1b4690b3f8b 887 __IOM uint32_t MAIR[2];
AnnaBridge 165:d1b4690b3f8b 888 struct {
AnnaBridge 165:d1b4690b3f8b 889 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
AnnaBridge 165:d1b4690b3f8b 890 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
AnnaBridge 165:d1b4690b3f8b 891 };
AnnaBridge 165:d1b4690b3f8b 892 };
AnnaBridge 165:d1b4690b3f8b 893 } MPU_Type;
AnnaBridge 165:d1b4690b3f8b 894
AnnaBridge 165:d1b4690b3f8b 895 #define MPU_TYPE_RALIASES 1U
AnnaBridge 165:d1b4690b3f8b 896
AnnaBridge 165:d1b4690b3f8b 897 /* MPU Type Register Definitions */
AnnaBridge 165:d1b4690b3f8b 898 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 165:d1b4690b3f8b 899 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 165:d1b4690b3f8b 900
AnnaBridge 165:d1b4690b3f8b 901 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 165:d1b4690b3f8b 902 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 165:d1b4690b3f8b 903
AnnaBridge 165:d1b4690b3f8b 904 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 165:d1b4690b3f8b 905 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 165:d1b4690b3f8b 906
AnnaBridge 165:d1b4690b3f8b 907 /* MPU Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 908 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 165:d1b4690b3f8b 909 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 165:d1b4690b3f8b 910
AnnaBridge 165:d1b4690b3f8b 911 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 165:d1b4690b3f8b 912 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 165:d1b4690b3f8b 913
AnnaBridge 165:d1b4690b3f8b 914 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 165:d1b4690b3f8b 915 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 165:d1b4690b3f8b 916
AnnaBridge 165:d1b4690b3f8b 917 /* MPU Region Number Register Definitions */
AnnaBridge 165:d1b4690b3f8b 918 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 165:d1b4690b3f8b 919 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 165:d1b4690b3f8b 920
AnnaBridge 165:d1b4690b3f8b 921 /* MPU Region Base Address Register Definitions */
AnnaBridge 165:d1b4690b3f8b 922 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
AnnaBridge 165:d1b4690b3f8b 923 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
AnnaBridge 165:d1b4690b3f8b 924
AnnaBridge 165:d1b4690b3f8b 925 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
AnnaBridge 165:d1b4690b3f8b 926 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
AnnaBridge 165:d1b4690b3f8b 927
AnnaBridge 165:d1b4690b3f8b 928 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
AnnaBridge 165:d1b4690b3f8b 929 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
AnnaBridge 165:d1b4690b3f8b 930
AnnaBridge 165:d1b4690b3f8b 931 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
AnnaBridge 165:d1b4690b3f8b 932 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
AnnaBridge 165:d1b4690b3f8b 933
AnnaBridge 165:d1b4690b3f8b 934 /* MPU Region Limit Address Register Definitions */
AnnaBridge 165:d1b4690b3f8b 935 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
AnnaBridge 165:d1b4690b3f8b 936 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
AnnaBridge 165:d1b4690b3f8b 937
AnnaBridge 165:d1b4690b3f8b 938 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
AnnaBridge 165:d1b4690b3f8b 939 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
AnnaBridge 165:d1b4690b3f8b 940
AnnaBridge 165:d1b4690b3f8b 941 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
AnnaBridge 165:d1b4690b3f8b 942 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
AnnaBridge 165:d1b4690b3f8b 943
AnnaBridge 165:d1b4690b3f8b 944 /* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge 165:d1b4690b3f8b 945 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
AnnaBridge 165:d1b4690b3f8b 946 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
AnnaBridge 165:d1b4690b3f8b 947
AnnaBridge 165:d1b4690b3f8b 948 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
AnnaBridge 165:d1b4690b3f8b 949 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
AnnaBridge 165:d1b4690b3f8b 950
AnnaBridge 165:d1b4690b3f8b 951 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
AnnaBridge 165:d1b4690b3f8b 952 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
AnnaBridge 165:d1b4690b3f8b 953
AnnaBridge 165:d1b4690b3f8b 954 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
AnnaBridge 165:d1b4690b3f8b 955 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
AnnaBridge 165:d1b4690b3f8b 956
AnnaBridge 165:d1b4690b3f8b 957 /* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge 165:d1b4690b3f8b 958 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
AnnaBridge 165:d1b4690b3f8b 959 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
AnnaBridge 165:d1b4690b3f8b 960
AnnaBridge 165:d1b4690b3f8b 961 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
AnnaBridge 165:d1b4690b3f8b 962 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
AnnaBridge 165:d1b4690b3f8b 963
AnnaBridge 165:d1b4690b3f8b 964 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
AnnaBridge 165:d1b4690b3f8b 965 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
AnnaBridge 165:d1b4690b3f8b 966
AnnaBridge 165:d1b4690b3f8b 967 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
AnnaBridge 165:d1b4690b3f8b 968 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
AnnaBridge 165:d1b4690b3f8b 969
AnnaBridge 165:d1b4690b3f8b 970 /*@} end of group CMSIS_MPU */
AnnaBridge 165:d1b4690b3f8b 971 #endif
AnnaBridge 165:d1b4690b3f8b 972
AnnaBridge 165:d1b4690b3f8b 973
AnnaBridge 165:d1b4690b3f8b 974 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 165:d1b4690b3f8b 975 /**
AnnaBridge 165:d1b4690b3f8b 976 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 977 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge 165:d1b4690b3f8b 978 \brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge 165:d1b4690b3f8b 979 @{
AnnaBridge 165:d1b4690b3f8b 980 */
AnnaBridge 165:d1b4690b3f8b 981
AnnaBridge 165:d1b4690b3f8b 982 /**
AnnaBridge 165:d1b4690b3f8b 983 \brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge 165:d1b4690b3f8b 984 */
AnnaBridge 165:d1b4690b3f8b 985 typedef struct
AnnaBridge 165:d1b4690b3f8b 986 {
AnnaBridge 165:d1b4690b3f8b 987 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
AnnaBridge 165:d1b4690b3f8b 988 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
AnnaBridge 165:d1b4690b3f8b 989 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 990 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
AnnaBridge 165:d1b4690b3f8b 991 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
AnnaBridge 165:d1b4690b3f8b 992 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
AnnaBridge 165:d1b4690b3f8b 993 #endif
AnnaBridge 165:d1b4690b3f8b 994 } SAU_Type;
AnnaBridge 165:d1b4690b3f8b 995
AnnaBridge 165:d1b4690b3f8b 996 /* SAU Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 997 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
AnnaBridge 165:d1b4690b3f8b 998 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
AnnaBridge 165:d1b4690b3f8b 999
AnnaBridge 165:d1b4690b3f8b 1000 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
AnnaBridge 165:d1b4690b3f8b 1001 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
AnnaBridge 165:d1b4690b3f8b 1002
AnnaBridge 165:d1b4690b3f8b 1003 /* SAU Type Register Definitions */
AnnaBridge 165:d1b4690b3f8b 1004 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
AnnaBridge 165:d1b4690b3f8b 1005 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
AnnaBridge 165:d1b4690b3f8b 1006
AnnaBridge 165:d1b4690b3f8b 1007 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 1008 /* SAU Region Number Register Definitions */
AnnaBridge 165:d1b4690b3f8b 1009 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
AnnaBridge 165:d1b4690b3f8b 1010 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
AnnaBridge 165:d1b4690b3f8b 1011
AnnaBridge 165:d1b4690b3f8b 1012 /* SAU Region Base Address Register Definitions */
AnnaBridge 165:d1b4690b3f8b 1013 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
AnnaBridge 165:d1b4690b3f8b 1014 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
AnnaBridge 165:d1b4690b3f8b 1015
AnnaBridge 165:d1b4690b3f8b 1016 /* SAU Region Limit Address Register Definitions */
AnnaBridge 165:d1b4690b3f8b 1017 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
AnnaBridge 165:d1b4690b3f8b 1018 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
AnnaBridge 165:d1b4690b3f8b 1019
AnnaBridge 165:d1b4690b3f8b 1020 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
AnnaBridge 165:d1b4690b3f8b 1021 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
AnnaBridge 165:d1b4690b3f8b 1022
AnnaBridge 165:d1b4690b3f8b 1023 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
AnnaBridge 165:d1b4690b3f8b 1024 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
AnnaBridge 165:d1b4690b3f8b 1025
AnnaBridge 165:d1b4690b3f8b 1026 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge 165:d1b4690b3f8b 1027
AnnaBridge 165:d1b4690b3f8b 1028 /*@} end of group CMSIS_SAU */
AnnaBridge 165:d1b4690b3f8b 1029 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 165:d1b4690b3f8b 1030
AnnaBridge 165:d1b4690b3f8b 1031
AnnaBridge 165:d1b4690b3f8b 1032 /**
AnnaBridge 165:d1b4690b3f8b 1033 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 1034 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 165:d1b4690b3f8b 1035 \brief Type definitions for the Core Debug Registers
AnnaBridge 165:d1b4690b3f8b 1036 @{
AnnaBridge 165:d1b4690b3f8b 1037 */
AnnaBridge 165:d1b4690b3f8b 1038
AnnaBridge 165:d1b4690b3f8b 1039 /**
AnnaBridge 165:d1b4690b3f8b 1040 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 165:d1b4690b3f8b 1041 */
AnnaBridge 165:d1b4690b3f8b 1042 typedef struct
AnnaBridge 165:d1b4690b3f8b 1043 {
AnnaBridge 165:d1b4690b3f8b 1044 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 165:d1b4690b3f8b 1045 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 165:d1b4690b3f8b 1046 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 165:d1b4690b3f8b 1047 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 165:d1b4690b3f8b 1048 uint32_t RESERVED4[1U];
AnnaBridge 165:d1b4690b3f8b 1049 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
AnnaBridge 165:d1b4690b3f8b 1050 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
AnnaBridge 165:d1b4690b3f8b 1051 } CoreDebug_Type;
AnnaBridge 165:d1b4690b3f8b 1052
AnnaBridge 165:d1b4690b3f8b 1053 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 165:d1b4690b3f8b 1054 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 165:d1b4690b3f8b 1055 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 165:d1b4690b3f8b 1056
AnnaBridge 165:d1b4690b3f8b 1057 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
AnnaBridge 165:d1b4690b3f8b 1058 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
AnnaBridge 165:d1b4690b3f8b 1059
AnnaBridge 165:d1b4690b3f8b 1060 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 165:d1b4690b3f8b 1061 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 165:d1b4690b3f8b 1062
AnnaBridge 165:d1b4690b3f8b 1063 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 165:d1b4690b3f8b 1064 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 165:d1b4690b3f8b 1065
AnnaBridge 165:d1b4690b3f8b 1066 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 165:d1b4690b3f8b 1067 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 165:d1b4690b3f8b 1068
AnnaBridge 165:d1b4690b3f8b 1069 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 165:d1b4690b3f8b 1070 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 165:d1b4690b3f8b 1071
AnnaBridge 165:d1b4690b3f8b 1072 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 165:d1b4690b3f8b 1073 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 165:d1b4690b3f8b 1074
AnnaBridge 165:d1b4690b3f8b 1075 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 165:d1b4690b3f8b 1076 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 165:d1b4690b3f8b 1077
AnnaBridge 165:d1b4690b3f8b 1078 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 165:d1b4690b3f8b 1079 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 165:d1b4690b3f8b 1080
AnnaBridge 165:d1b4690b3f8b 1081 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 165:d1b4690b3f8b 1082 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 165:d1b4690b3f8b 1083
AnnaBridge 165:d1b4690b3f8b 1084 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 165:d1b4690b3f8b 1085 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 165:d1b4690b3f8b 1086
AnnaBridge 165:d1b4690b3f8b 1087 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 165:d1b4690b3f8b 1088 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 165:d1b4690b3f8b 1089
AnnaBridge 165:d1b4690b3f8b 1090 /* Debug Core Register Selector Register Definitions */
AnnaBridge 165:d1b4690b3f8b 1091 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 165:d1b4690b3f8b 1092 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 165:d1b4690b3f8b 1093
AnnaBridge 165:d1b4690b3f8b 1094 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 165:d1b4690b3f8b 1095 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 165:d1b4690b3f8b 1096
AnnaBridge 165:d1b4690b3f8b 1097 /* Debug Exception and Monitor Control Register */
AnnaBridge 165:d1b4690b3f8b 1098 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
AnnaBridge 165:d1b4690b3f8b 1099 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
AnnaBridge 165:d1b4690b3f8b 1100
AnnaBridge 165:d1b4690b3f8b 1101 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 165:d1b4690b3f8b 1102 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 165:d1b4690b3f8b 1103
AnnaBridge 165:d1b4690b3f8b 1104 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 165:d1b4690b3f8b 1105 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 165:d1b4690b3f8b 1106
AnnaBridge 165:d1b4690b3f8b 1107 /* Debug Authentication Control Register Definitions */
AnnaBridge 165:d1b4690b3f8b 1108 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
AnnaBridge 165:d1b4690b3f8b 1109 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
AnnaBridge 165:d1b4690b3f8b 1110
AnnaBridge 165:d1b4690b3f8b 1111 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
AnnaBridge 165:d1b4690b3f8b 1112 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
AnnaBridge 165:d1b4690b3f8b 1113
AnnaBridge 165:d1b4690b3f8b 1114 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
AnnaBridge 165:d1b4690b3f8b 1115 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
AnnaBridge 165:d1b4690b3f8b 1116
AnnaBridge 165:d1b4690b3f8b 1117 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
AnnaBridge 165:d1b4690b3f8b 1118 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
AnnaBridge 165:d1b4690b3f8b 1119
AnnaBridge 165:d1b4690b3f8b 1120 /* Debug Security Control and Status Register Definitions */
AnnaBridge 165:d1b4690b3f8b 1121 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
AnnaBridge 165:d1b4690b3f8b 1122 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
AnnaBridge 165:d1b4690b3f8b 1123
AnnaBridge 165:d1b4690b3f8b 1124 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
AnnaBridge 165:d1b4690b3f8b 1125 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
AnnaBridge 165:d1b4690b3f8b 1126
AnnaBridge 165:d1b4690b3f8b 1127 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
AnnaBridge 165:d1b4690b3f8b 1128 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
AnnaBridge 165:d1b4690b3f8b 1129
AnnaBridge 165:d1b4690b3f8b 1130 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 165:d1b4690b3f8b 1131
AnnaBridge 165:d1b4690b3f8b 1132
AnnaBridge 165:d1b4690b3f8b 1133 /**
AnnaBridge 165:d1b4690b3f8b 1134 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 1135 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 165:d1b4690b3f8b 1136 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 165:d1b4690b3f8b 1137 @{
AnnaBridge 165:d1b4690b3f8b 1138 */
AnnaBridge 165:d1b4690b3f8b 1139
AnnaBridge 165:d1b4690b3f8b 1140 /**
AnnaBridge 165:d1b4690b3f8b 1141 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 165:d1b4690b3f8b 1142 \param[in] field Name of the register bit field.
AnnaBridge 165:d1b4690b3f8b 1143 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 165:d1b4690b3f8b 1144 \return Masked and shifted value.
AnnaBridge 165:d1b4690b3f8b 1145 */
AnnaBridge 165:d1b4690b3f8b 1146 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 165:d1b4690b3f8b 1147
AnnaBridge 165:d1b4690b3f8b 1148 /**
AnnaBridge 165:d1b4690b3f8b 1149 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 165:d1b4690b3f8b 1150 \param[in] field Name of the register bit field.
AnnaBridge 165:d1b4690b3f8b 1151 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 165:d1b4690b3f8b 1152 \return Masked and shifted bit field value.
AnnaBridge 165:d1b4690b3f8b 1153 */
AnnaBridge 165:d1b4690b3f8b 1154 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 165:d1b4690b3f8b 1155
AnnaBridge 165:d1b4690b3f8b 1156 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 165:d1b4690b3f8b 1157
AnnaBridge 165:d1b4690b3f8b 1158
AnnaBridge 165:d1b4690b3f8b 1159 /**
AnnaBridge 165:d1b4690b3f8b 1160 \ingroup CMSIS_core_register
AnnaBridge 165:d1b4690b3f8b 1161 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 165:d1b4690b3f8b 1162 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 165:d1b4690b3f8b 1163 @{
AnnaBridge 165:d1b4690b3f8b 1164 */
AnnaBridge 165:d1b4690b3f8b 1165
AnnaBridge 165:d1b4690b3f8b 1166 /* Memory mapping of Core Hardware */
AnnaBridge 165:d1b4690b3f8b 1167 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 165:d1b4690b3f8b 1168 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 165:d1b4690b3f8b 1169 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 165:d1b4690b3f8b 1170 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 165:d1b4690b3f8b 1171 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 165:d1b4690b3f8b 1172 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 165:d1b4690b3f8b 1173 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 165:d1b4690b3f8b 1174
AnnaBridge 165:d1b4690b3f8b 1175
AnnaBridge 165:d1b4690b3f8b 1176 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 165:d1b4690b3f8b 1177 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 165:d1b4690b3f8b 1178 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 165:d1b4690b3f8b 1179 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 165:d1b4690b3f8b 1180 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 165:d1b4690b3f8b 1181 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
AnnaBridge 165:d1b4690b3f8b 1182
AnnaBridge 165:d1b4690b3f8b 1183 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 1184 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 165:d1b4690b3f8b 1185 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 165:d1b4690b3f8b 1186 #endif
AnnaBridge 165:d1b4690b3f8b 1187
AnnaBridge 165:d1b4690b3f8b 1188 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 165:d1b4690b3f8b 1189 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
AnnaBridge 165:d1b4690b3f8b 1190 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
AnnaBridge 165:d1b4690b3f8b 1191 #endif
AnnaBridge 165:d1b4690b3f8b 1192
AnnaBridge 165:d1b4690b3f8b 1193 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 165:d1b4690b3f8b 1194 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1195 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1196 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1197 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1198 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1199
AnnaBridge 165:d1b4690b3f8b 1200 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1201 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1202 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1203 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1204
AnnaBridge 165:d1b4690b3f8b 1205 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 1206 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1207 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 165:d1b4690b3f8b 1208 #endif
AnnaBridge 165:d1b4690b3f8b 1209
AnnaBridge 165:d1b4690b3f8b 1210 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 165:d1b4690b3f8b 1211 /*@} */
AnnaBridge 165:d1b4690b3f8b 1212
AnnaBridge 165:d1b4690b3f8b 1213
AnnaBridge 165:d1b4690b3f8b 1214
AnnaBridge 165:d1b4690b3f8b 1215 /*******************************************************************************
AnnaBridge 165:d1b4690b3f8b 1216 * Hardware Abstraction Layer
AnnaBridge 165:d1b4690b3f8b 1217 Core Function Interface contains:
AnnaBridge 165:d1b4690b3f8b 1218 - Core NVIC Functions
AnnaBridge 165:d1b4690b3f8b 1219 - Core SysTick Functions
AnnaBridge 165:d1b4690b3f8b 1220 - Core Register Access Functions
AnnaBridge 165:d1b4690b3f8b 1221 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 1222 /**
AnnaBridge 165:d1b4690b3f8b 1223 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 165:d1b4690b3f8b 1224 */
AnnaBridge 165:d1b4690b3f8b 1225
AnnaBridge 165:d1b4690b3f8b 1226
AnnaBridge 165:d1b4690b3f8b 1227
AnnaBridge 165:d1b4690b3f8b 1228 /* ########################## NVIC functions #################################### */
AnnaBridge 165:d1b4690b3f8b 1229 /**
AnnaBridge 165:d1b4690b3f8b 1230 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 165:d1b4690b3f8b 1231 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 165:d1b4690b3f8b 1232 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 165:d1b4690b3f8b 1233 @{
AnnaBridge 165:d1b4690b3f8b 1234 */
AnnaBridge 165:d1b4690b3f8b 1235
AnnaBridge 165:d1b4690b3f8b 1236 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 165:d1b4690b3f8b 1237 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 165:d1b4690b3f8b 1238 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 165:d1b4690b3f8b 1239 #endif
AnnaBridge 165:d1b4690b3f8b 1240 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 165:d1b4690b3f8b 1241 #else
AnnaBridge 165:d1b4690b3f8b 1242 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */
AnnaBridge 165:d1b4690b3f8b 1243 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */
AnnaBridge 165:d1b4690b3f8b 1244 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 165:d1b4690b3f8b 1245 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 165:d1b4690b3f8b 1246 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 165:d1b4690b3f8b 1247 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 165:d1b4690b3f8b 1248 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 165:d1b4690b3f8b 1249 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 165:d1b4690b3f8b 1250 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 165:d1b4690b3f8b 1251 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 165:d1b4690b3f8b 1252 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 165:d1b4690b3f8b 1253 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 165:d1b4690b3f8b 1254 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 165:d1b4690b3f8b 1255
AnnaBridge 165:d1b4690b3f8b 1256 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 165:d1b4690b3f8b 1257 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 165:d1b4690b3f8b 1258 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 165:d1b4690b3f8b 1259 #endif
AnnaBridge 165:d1b4690b3f8b 1260 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 165:d1b4690b3f8b 1261 #else
AnnaBridge 165:d1b4690b3f8b 1262 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 165:d1b4690b3f8b 1263 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 165:d1b4690b3f8b 1264 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 165:d1b4690b3f8b 1265
AnnaBridge 165:d1b4690b3f8b 1266 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 165:d1b4690b3f8b 1267
AnnaBridge 165:d1b4690b3f8b 1268
AnnaBridge 165:d1b4690b3f8b 1269 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 165:d1b4690b3f8b 1270 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 165:d1b4690b3f8b 1271 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 165:d1b4690b3f8b 1272 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 165:d1b4690b3f8b 1273 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 165:d1b4690b3f8b 1274
AnnaBridge 165:d1b4690b3f8b 1275
AnnaBridge 165:d1b4690b3f8b 1276 /**
AnnaBridge 165:d1b4690b3f8b 1277 \brief Enable Interrupt
AnnaBridge 165:d1b4690b3f8b 1278 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 165:d1b4690b3f8b 1279 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1280 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1281 */
AnnaBridge 165:d1b4690b3f8b 1282 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1283 {
AnnaBridge 165:d1b4690b3f8b 1284 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1285 {
AnnaBridge 165:d1b4690b3f8b 1286 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 1287 }
AnnaBridge 165:d1b4690b3f8b 1288 }
AnnaBridge 165:d1b4690b3f8b 1289
AnnaBridge 165:d1b4690b3f8b 1290
AnnaBridge 165:d1b4690b3f8b 1291 /**
AnnaBridge 165:d1b4690b3f8b 1292 \brief Get Interrupt Enable status
AnnaBridge 165:d1b4690b3f8b 1293 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 165:d1b4690b3f8b 1294 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1295 \return 0 Interrupt is not enabled.
AnnaBridge 165:d1b4690b3f8b 1296 \return 1 Interrupt is enabled.
AnnaBridge 165:d1b4690b3f8b 1297 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1298 */
AnnaBridge 165:d1b4690b3f8b 1299 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1300 {
AnnaBridge 165:d1b4690b3f8b 1301 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1302 {
AnnaBridge 165:d1b4690b3f8b 1303 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1304 }
AnnaBridge 165:d1b4690b3f8b 1305 else
AnnaBridge 165:d1b4690b3f8b 1306 {
AnnaBridge 165:d1b4690b3f8b 1307 return(0U);
AnnaBridge 165:d1b4690b3f8b 1308 }
AnnaBridge 165:d1b4690b3f8b 1309 }
AnnaBridge 165:d1b4690b3f8b 1310
AnnaBridge 165:d1b4690b3f8b 1311
AnnaBridge 165:d1b4690b3f8b 1312 /**
AnnaBridge 165:d1b4690b3f8b 1313 \brief Disable Interrupt
AnnaBridge 165:d1b4690b3f8b 1314 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 165:d1b4690b3f8b 1315 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1316 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1317 */
AnnaBridge 165:d1b4690b3f8b 1318 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1319 {
AnnaBridge 165:d1b4690b3f8b 1320 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1321 {
AnnaBridge 165:d1b4690b3f8b 1322 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 1323 __DSB();
AnnaBridge 165:d1b4690b3f8b 1324 __ISB();
AnnaBridge 165:d1b4690b3f8b 1325 }
AnnaBridge 165:d1b4690b3f8b 1326 }
AnnaBridge 165:d1b4690b3f8b 1327
AnnaBridge 165:d1b4690b3f8b 1328
AnnaBridge 165:d1b4690b3f8b 1329 /**
AnnaBridge 165:d1b4690b3f8b 1330 \brief Get Pending Interrupt
AnnaBridge 165:d1b4690b3f8b 1331 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 165:d1b4690b3f8b 1332 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1333 \return 0 Interrupt status is not pending.
AnnaBridge 165:d1b4690b3f8b 1334 \return 1 Interrupt status is pending.
AnnaBridge 165:d1b4690b3f8b 1335 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1336 */
AnnaBridge 165:d1b4690b3f8b 1337 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1338 {
AnnaBridge 165:d1b4690b3f8b 1339 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1340 {
AnnaBridge 165:d1b4690b3f8b 1341 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1342 }
AnnaBridge 165:d1b4690b3f8b 1343 else
AnnaBridge 165:d1b4690b3f8b 1344 {
AnnaBridge 165:d1b4690b3f8b 1345 return(0U);
AnnaBridge 165:d1b4690b3f8b 1346 }
AnnaBridge 165:d1b4690b3f8b 1347 }
AnnaBridge 165:d1b4690b3f8b 1348
AnnaBridge 165:d1b4690b3f8b 1349
AnnaBridge 165:d1b4690b3f8b 1350 /**
AnnaBridge 165:d1b4690b3f8b 1351 \brief Set Pending Interrupt
AnnaBridge 165:d1b4690b3f8b 1352 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 165:d1b4690b3f8b 1353 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1354 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1355 */
AnnaBridge 165:d1b4690b3f8b 1356 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1357 {
AnnaBridge 165:d1b4690b3f8b 1358 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1359 {
AnnaBridge 165:d1b4690b3f8b 1360 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 1361 }
AnnaBridge 165:d1b4690b3f8b 1362 }
AnnaBridge 165:d1b4690b3f8b 1363
AnnaBridge 165:d1b4690b3f8b 1364
AnnaBridge 165:d1b4690b3f8b 1365 /**
AnnaBridge 165:d1b4690b3f8b 1366 \brief Clear Pending Interrupt
AnnaBridge 165:d1b4690b3f8b 1367 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 165:d1b4690b3f8b 1368 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1369 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1370 */
AnnaBridge 165:d1b4690b3f8b 1371 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1372 {
AnnaBridge 165:d1b4690b3f8b 1373 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1374 {
AnnaBridge 165:d1b4690b3f8b 1375 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 1376 }
AnnaBridge 165:d1b4690b3f8b 1377 }
AnnaBridge 165:d1b4690b3f8b 1378
AnnaBridge 165:d1b4690b3f8b 1379
AnnaBridge 165:d1b4690b3f8b 1380 /**
AnnaBridge 165:d1b4690b3f8b 1381 \brief Get Active Interrupt
AnnaBridge 165:d1b4690b3f8b 1382 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 165:d1b4690b3f8b 1383 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1384 \return 0 Interrupt status is not active.
AnnaBridge 165:d1b4690b3f8b 1385 \return 1 Interrupt status is active.
AnnaBridge 165:d1b4690b3f8b 1386 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1387 */
AnnaBridge 165:d1b4690b3f8b 1388 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1389 {
AnnaBridge 165:d1b4690b3f8b 1390 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1391 {
AnnaBridge 165:d1b4690b3f8b 1392 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1393 }
AnnaBridge 165:d1b4690b3f8b 1394 else
AnnaBridge 165:d1b4690b3f8b 1395 {
AnnaBridge 165:d1b4690b3f8b 1396 return(0U);
AnnaBridge 165:d1b4690b3f8b 1397 }
AnnaBridge 165:d1b4690b3f8b 1398 }
AnnaBridge 165:d1b4690b3f8b 1399
AnnaBridge 165:d1b4690b3f8b 1400
AnnaBridge 165:d1b4690b3f8b 1401 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 165:d1b4690b3f8b 1402 /**
AnnaBridge 165:d1b4690b3f8b 1403 \brief Get Interrupt Target State
AnnaBridge 165:d1b4690b3f8b 1404 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 165:d1b4690b3f8b 1405 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1406 \return 0 if interrupt is assigned to Secure
AnnaBridge 165:d1b4690b3f8b 1407 \return 1 if interrupt is assigned to Non Secure
AnnaBridge 165:d1b4690b3f8b 1408 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1409 */
AnnaBridge 165:d1b4690b3f8b 1410 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1411 {
AnnaBridge 165:d1b4690b3f8b 1412 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1413 {
AnnaBridge 165:d1b4690b3f8b 1414 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1415 }
AnnaBridge 165:d1b4690b3f8b 1416 else
AnnaBridge 165:d1b4690b3f8b 1417 {
AnnaBridge 165:d1b4690b3f8b 1418 return(0U);
AnnaBridge 165:d1b4690b3f8b 1419 }
AnnaBridge 165:d1b4690b3f8b 1420 }
AnnaBridge 165:d1b4690b3f8b 1421
AnnaBridge 165:d1b4690b3f8b 1422
AnnaBridge 165:d1b4690b3f8b 1423 /**
AnnaBridge 165:d1b4690b3f8b 1424 \brief Set Interrupt Target State
AnnaBridge 165:d1b4690b3f8b 1425 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 165:d1b4690b3f8b 1426 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1427 \return 0 if interrupt is assigned to Secure
AnnaBridge 165:d1b4690b3f8b 1428 1 if interrupt is assigned to Non Secure
AnnaBridge 165:d1b4690b3f8b 1429 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1430 */
AnnaBridge 165:d1b4690b3f8b 1431 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1432 {
AnnaBridge 165:d1b4690b3f8b 1433 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1434 {
AnnaBridge 165:d1b4690b3f8b 1435 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge 165:d1b4690b3f8b 1436 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1437 }
AnnaBridge 165:d1b4690b3f8b 1438 else
AnnaBridge 165:d1b4690b3f8b 1439 {
AnnaBridge 165:d1b4690b3f8b 1440 return(0U);
AnnaBridge 165:d1b4690b3f8b 1441 }
AnnaBridge 165:d1b4690b3f8b 1442 }
AnnaBridge 165:d1b4690b3f8b 1443
AnnaBridge 165:d1b4690b3f8b 1444
AnnaBridge 165:d1b4690b3f8b 1445 /**
AnnaBridge 165:d1b4690b3f8b 1446 \brief Clear Interrupt Target State
AnnaBridge 165:d1b4690b3f8b 1447 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 165:d1b4690b3f8b 1448 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1449 \return 0 if interrupt is assigned to Secure
AnnaBridge 165:d1b4690b3f8b 1450 1 if interrupt is assigned to Non Secure
AnnaBridge 165:d1b4690b3f8b 1451 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1452 */
AnnaBridge 165:d1b4690b3f8b 1453 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1454 {
AnnaBridge 165:d1b4690b3f8b 1455 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1456 {
AnnaBridge 165:d1b4690b3f8b 1457 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge 165:d1b4690b3f8b 1458 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1459 }
AnnaBridge 165:d1b4690b3f8b 1460 else
AnnaBridge 165:d1b4690b3f8b 1461 {
AnnaBridge 165:d1b4690b3f8b 1462 return(0U);
AnnaBridge 165:d1b4690b3f8b 1463 }
AnnaBridge 165:d1b4690b3f8b 1464 }
AnnaBridge 165:d1b4690b3f8b 1465 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 165:d1b4690b3f8b 1466
AnnaBridge 165:d1b4690b3f8b 1467
AnnaBridge 165:d1b4690b3f8b 1468 /**
AnnaBridge 165:d1b4690b3f8b 1469 \brief Set Interrupt Priority
AnnaBridge 165:d1b4690b3f8b 1470 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 165:d1b4690b3f8b 1471 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 1472 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 1473 \param [in] IRQn Interrupt number.
AnnaBridge 165:d1b4690b3f8b 1474 \param [in] priority Priority to set.
AnnaBridge 165:d1b4690b3f8b 1475 \note The priority cannot be set for every processor exception.
AnnaBridge 165:d1b4690b3f8b 1476 */
AnnaBridge 165:d1b4690b3f8b 1477 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 165:d1b4690b3f8b 1478 {
AnnaBridge 165:d1b4690b3f8b 1479 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1480 {
AnnaBridge 165:d1b4690b3f8b 1481 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 165:d1b4690b3f8b 1482 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 165:d1b4690b3f8b 1483 }
AnnaBridge 165:d1b4690b3f8b 1484 else
AnnaBridge 165:d1b4690b3f8b 1485 {
AnnaBridge 165:d1b4690b3f8b 1486 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 165:d1b4690b3f8b 1487 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 165:d1b4690b3f8b 1488 }
AnnaBridge 165:d1b4690b3f8b 1489 }
AnnaBridge 165:d1b4690b3f8b 1490
AnnaBridge 165:d1b4690b3f8b 1491
AnnaBridge 165:d1b4690b3f8b 1492 /**
AnnaBridge 165:d1b4690b3f8b 1493 \brief Get Interrupt Priority
AnnaBridge 165:d1b4690b3f8b 1494 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 165:d1b4690b3f8b 1495 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 1496 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 1497 \param [in] IRQn Interrupt number.
AnnaBridge 165:d1b4690b3f8b 1498 \return Interrupt Priority.
AnnaBridge 165:d1b4690b3f8b 1499 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 165:d1b4690b3f8b 1500 */
AnnaBridge 165:d1b4690b3f8b 1501 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1502 {
AnnaBridge 165:d1b4690b3f8b 1503
AnnaBridge 165:d1b4690b3f8b 1504 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1505 {
AnnaBridge 165:d1b4690b3f8b 1506 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 165:d1b4690b3f8b 1507 }
AnnaBridge 165:d1b4690b3f8b 1508 else
AnnaBridge 165:d1b4690b3f8b 1509 {
AnnaBridge 165:d1b4690b3f8b 1510 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 165:d1b4690b3f8b 1511 }
AnnaBridge 165:d1b4690b3f8b 1512 }
AnnaBridge 165:d1b4690b3f8b 1513
AnnaBridge 165:d1b4690b3f8b 1514
AnnaBridge 165:d1b4690b3f8b 1515 /**
AnnaBridge 165:d1b4690b3f8b 1516 \brief Set Interrupt Vector
AnnaBridge 165:d1b4690b3f8b 1517 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 165:d1b4690b3f8b 1518 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 1519 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 1520 VTOR must been relocated to SRAM before.
AnnaBridge 165:d1b4690b3f8b 1521 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 165:d1b4690b3f8b 1522 \param [in] IRQn Interrupt number
AnnaBridge 165:d1b4690b3f8b 1523 \param [in] vector Address of interrupt handler function
AnnaBridge 165:d1b4690b3f8b 1524 */
AnnaBridge 165:d1b4690b3f8b 1525 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 165:d1b4690b3f8b 1526 {
AnnaBridge 165:d1b4690b3f8b 1527 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 1528 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 165:d1b4690b3f8b 1529 #else
AnnaBridge 165:d1b4690b3f8b 1530 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 165:d1b4690b3f8b 1531 #endif
AnnaBridge 165:d1b4690b3f8b 1532 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 165:d1b4690b3f8b 1533 }
AnnaBridge 165:d1b4690b3f8b 1534
AnnaBridge 165:d1b4690b3f8b 1535
AnnaBridge 165:d1b4690b3f8b 1536 /**
AnnaBridge 165:d1b4690b3f8b 1537 \brief Get Interrupt Vector
AnnaBridge 165:d1b4690b3f8b 1538 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 165:d1b4690b3f8b 1539 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 1540 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 1541 \param [in] IRQn Interrupt number.
AnnaBridge 165:d1b4690b3f8b 1542 \return Address of interrupt handler function
AnnaBridge 165:d1b4690b3f8b 1543 */
AnnaBridge 165:d1b4690b3f8b 1544 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1545 {
AnnaBridge 165:d1b4690b3f8b 1546 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 1547 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 165:d1b4690b3f8b 1548 #else
AnnaBridge 165:d1b4690b3f8b 1549 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 165:d1b4690b3f8b 1550 #endif
AnnaBridge 165:d1b4690b3f8b 1551 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 165:d1b4690b3f8b 1552 }
AnnaBridge 165:d1b4690b3f8b 1553
AnnaBridge 165:d1b4690b3f8b 1554
AnnaBridge 165:d1b4690b3f8b 1555 /**
AnnaBridge 165:d1b4690b3f8b 1556 \brief System Reset
AnnaBridge 165:d1b4690b3f8b 1557 \details Initiates a system reset request to reset the MCU.
AnnaBridge 165:d1b4690b3f8b 1558 */
AnnaBridge 165:d1b4690b3f8b 1559 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 165:d1b4690b3f8b 1560 {
AnnaBridge 165:d1b4690b3f8b 1561 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 165:d1b4690b3f8b 1562 buffered write are completed before reset */
AnnaBridge 165:d1b4690b3f8b 1563 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 165:d1b4690b3f8b 1564 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 165:d1b4690b3f8b 1565 __DSB(); /* Ensure completion of memory access */
AnnaBridge 165:d1b4690b3f8b 1566
AnnaBridge 165:d1b4690b3f8b 1567 for(;;) /* wait until reset */
AnnaBridge 165:d1b4690b3f8b 1568 {
AnnaBridge 165:d1b4690b3f8b 1569 __NOP();
AnnaBridge 165:d1b4690b3f8b 1570 }
AnnaBridge 165:d1b4690b3f8b 1571 }
AnnaBridge 165:d1b4690b3f8b 1572
AnnaBridge 165:d1b4690b3f8b 1573 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 165:d1b4690b3f8b 1574 /**
AnnaBridge 165:d1b4690b3f8b 1575 \brief Enable Interrupt (non-secure)
AnnaBridge 165:d1b4690b3f8b 1576 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 165:d1b4690b3f8b 1577 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1578 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1579 */
AnnaBridge 165:d1b4690b3f8b 1580 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1581 {
AnnaBridge 165:d1b4690b3f8b 1582 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1583 {
AnnaBridge 165:d1b4690b3f8b 1584 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 1585 }
AnnaBridge 165:d1b4690b3f8b 1586 }
AnnaBridge 165:d1b4690b3f8b 1587
AnnaBridge 165:d1b4690b3f8b 1588
AnnaBridge 165:d1b4690b3f8b 1589 /**
AnnaBridge 165:d1b4690b3f8b 1590 \brief Get Interrupt Enable status (non-secure)
AnnaBridge 165:d1b4690b3f8b 1591 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 165:d1b4690b3f8b 1592 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1593 \return 0 Interrupt is not enabled.
AnnaBridge 165:d1b4690b3f8b 1594 \return 1 Interrupt is enabled.
AnnaBridge 165:d1b4690b3f8b 1595 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1596 */
AnnaBridge 165:d1b4690b3f8b 1597 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1598 {
AnnaBridge 165:d1b4690b3f8b 1599 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1600 {
AnnaBridge 165:d1b4690b3f8b 1601 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1602 }
AnnaBridge 165:d1b4690b3f8b 1603 else
AnnaBridge 165:d1b4690b3f8b 1604 {
AnnaBridge 165:d1b4690b3f8b 1605 return(0U);
AnnaBridge 165:d1b4690b3f8b 1606 }
AnnaBridge 165:d1b4690b3f8b 1607 }
AnnaBridge 165:d1b4690b3f8b 1608
AnnaBridge 165:d1b4690b3f8b 1609
AnnaBridge 165:d1b4690b3f8b 1610 /**
AnnaBridge 165:d1b4690b3f8b 1611 \brief Disable Interrupt (non-secure)
AnnaBridge 165:d1b4690b3f8b 1612 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 165:d1b4690b3f8b 1613 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1614 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1615 */
AnnaBridge 165:d1b4690b3f8b 1616 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1617 {
AnnaBridge 165:d1b4690b3f8b 1618 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1619 {
AnnaBridge 165:d1b4690b3f8b 1620 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 1621 }
AnnaBridge 165:d1b4690b3f8b 1622 }
AnnaBridge 165:d1b4690b3f8b 1623
AnnaBridge 165:d1b4690b3f8b 1624
AnnaBridge 165:d1b4690b3f8b 1625 /**
AnnaBridge 165:d1b4690b3f8b 1626 \brief Get Pending Interrupt (non-secure)
AnnaBridge 165:d1b4690b3f8b 1627 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge 165:d1b4690b3f8b 1628 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1629 \return 0 Interrupt status is not pending.
AnnaBridge 165:d1b4690b3f8b 1630 \return 1 Interrupt status is pending.
AnnaBridge 165:d1b4690b3f8b 1631 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1632 */
AnnaBridge 165:d1b4690b3f8b 1633 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1634 {
AnnaBridge 165:d1b4690b3f8b 1635 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1636 {
AnnaBridge 165:d1b4690b3f8b 1637 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1638 }
AnnaBridge 165:d1b4690b3f8b 1639 else
AnnaBridge 165:d1b4690b3f8b 1640 {
AnnaBridge 165:d1b4690b3f8b 1641 return(0U);
AnnaBridge 165:d1b4690b3f8b 1642 }
AnnaBridge 165:d1b4690b3f8b 1643 }
AnnaBridge 165:d1b4690b3f8b 1644
AnnaBridge 165:d1b4690b3f8b 1645
AnnaBridge 165:d1b4690b3f8b 1646 /**
AnnaBridge 165:d1b4690b3f8b 1647 \brief Set Pending Interrupt (non-secure)
AnnaBridge 165:d1b4690b3f8b 1648 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 165:d1b4690b3f8b 1649 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1650 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1651 */
AnnaBridge 165:d1b4690b3f8b 1652 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1653 {
AnnaBridge 165:d1b4690b3f8b 1654 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1655 {
AnnaBridge 165:d1b4690b3f8b 1656 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 1657 }
AnnaBridge 165:d1b4690b3f8b 1658 }
AnnaBridge 165:d1b4690b3f8b 1659
AnnaBridge 165:d1b4690b3f8b 1660
AnnaBridge 165:d1b4690b3f8b 1661 /**
AnnaBridge 165:d1b4690b3f8b 1662 \brief Clear Pending Interrupt (non-secure)
AnnaBridge 165:d1b4690b3f8b 1663 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 165:d1b4690b3f8b 1664 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1665 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1666 */
AnnaBridge 165:d1b4690b3f8b 1667 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1668 {
AnnaBridge 165:d1b4690b3f8b 1669 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1670 {
AnnaBridge 165:d1b4690b3f8b 1671 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 165:d1b4690b3f8b 1672 }
AnnaBridge 165:d1b4690b3f8b 1673 }
AnnaBridge 165:d1b4690b3f8b 1674
AnnaBridge 165:d1b4690b3f8b 1675
AnnaBridge 165:d1b4690b3f8b 1676 /**
AnnaBridge 165:d1b4690b3f8b 1677 \brief Get Active Interrupt (non-secure)
AnnaBridge 165:d1b4690b3f8b 1678 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge 165:d1b4690b3f8b 1679 \param [in] IRQn Device specific interrupt number.
AnnaBridge 165:d1b4690b3f8b 1680 \return 0 Interrupt status is not active.
AnnaBridge 165:d1b4690b3f8b 1681 \return 1 Interrupt status is active.
AnnaBridge 165:d1b4690b3f8b 1682 \note IRQn must not be negative.
AnnaBridge 165:d1b4690b3f8b 1683 */
AnnaBridge 165:d1b4690b3f8b 1684 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1685 {
AnnaBridge 165:d1b4690b3f8b 1686 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1687 {
AnnaBridge 165:d1b4690b3f8b 1688 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 165:d1b4690b3f8b 1689 }
AnnaBridge 165:d1b4690b3f8b 1690 else
AnnaBridge 165:d1b4690b3f8b 1691 {
AnnaBridge 165:d1b4690b3f8b 1692 return(0U);
AnnaBridge 165:d1b4690b3f8b 1693 }
AnnaBridge 165:d1b4690b3f8b 1694 }
AnnaBridge 165:d1b4690b3f8b 1695
AnnaBridge 165:d1b4690b3f8b 1696
AnnaBridge 165:d1b4690b3f8b 1697 /**
AnnaBridge 165:d1b4690b3f8b 1698 \brief Set Interrupt Priority (non-secure)
AnnaBridge 165:d1b4690b3f8b 1699 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 165:d1b4690b3f8b 1700 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 1701 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 1702 \param [in] IRQn Interrupt number.
AnnaBridge 165:d1b4690b3f8b 1703 \param [in] priority Priority to set.
AnnaBridge 165:d1b4690b3f8b 1704 \note The priority cannot be set for every non-secure processor exception.
AnnaBridge 165:d1b4690b3f8b 1705 */
AnnaBridge 165:d1b4690b3f8b 1706 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 165:d1b4690b3f8b 1707 {
AnnaBridge 165:d1b4690b3f8b 1708 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1709 {
AnnaBridge 165:d1b4690b3f8b 1710 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 165:d1b4690b3f8b 1711 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 165:d1b4690b3f8b 1712 }
AnnaBridge 165:d1b4690b3f8b 1713 else
AnnaBridge 165:d1b4690b3f8b 1714 {
AnnaBridge 165:d1b4690b3f8b 1715 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 165:d1b4690b3f8b 1716 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 165:d1b4690b3f8b 1717 }
AnnaBridge 165:d1b4690b3f8b 1718 }
AnnaBridge 165:d1b4690b3f8b 1719
AnnaBridge 165:d1b4690b3f8b 1720
AnnaBridge 165:d1b4690b3f8b 1721 /**
AnnaBridge 165:d1b4690b3f8b 1722 \brief Get Interrupt Priority (non-secure)
AnnaBridge 165:d1b4690b3f8b 1723 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 165:d1b4690b3f8b 1724 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 165:d1b4690b3f8b 1725 or negative to specify a processor exception.
AnnaBridge 165:d1b4690b3f8b 1726 \param [in] IRQn Interrupt number.
AnnaBridge 165:d1b4690b3f8b 1727 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 165:d1b4690b3f8b 1728 */
AnnaBridge 165:d1b4690b3f8b 1729 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge 165:d1b4690b3f8b 1730 {
AnnaBridge 165:d1b4690b3f8b 1731
AnnaBridge 165:d1b4690b3f8b 1732 if ((int32_t)(IRQn) >= 0)
AnnaBridge 165:d1b4690b3f8b 1733 {
AnnaBridge 165:d1b4690b3f8b 1734 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 165:d1b4690b3f8b 1735 }
AnnaBridge 165:d1b4690b3f8b 1736 else
AnnaBridge 165:d1b4690b3f8b 1737 {
AnnaBridge 165:d1b4690b3f8b 1738 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 165:d1b4690b3f8b 1739 }
AnnaBridge 165:d1b4690b3f8b 1740 }
AnnaBridge 165:d1b4690b3f8b 1741 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 165:d1b4690b3f8b 1742
AnnaBridge 165:d1b4690b3f8b 1743 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 165:d1b4690b3f8b 1744
AnnaBridge 165:d1b4690b3f8b 1745 /* ########################## MPU functions #################################### */
AnnaBridge 165:d1b4690b3f8b 1746
AnnaBridge 165:d1b4690b3f8b 1747 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 165:d1b4690b3f8b 1748
AnnaBridge 165:d1b4690b3f8b 1749 #include "mpu_armv8.h"
AnnaBridge 165:d1b4690b3f8b 1750
AnnaBridge 165:d1b4690b3f8b 1751 #endif
AnnaBridge 165:d1b4690b3f8b 1752
AnnaBridge 165:d1b4690b3f8b 1753 /* ########################## FPU functions #################################### */
AnnaBridge 165:d1b4690b3f8b 1754 /**
AnnaBridge 165:d1b4690b3f8b 1755 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 165:d1b4690b3f8b 1756 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 165:d1b4690b3f8b 1757 \brief Function that provides FPU type.
AnnaBridge 165:d1b4690b3f8b 1758 @{
AnnaBridge 165:d1b4690b3f8b 1759 */
AnnaBridge 165:d1b4690b3f8b 1760
AnnaBridge 165:d1b4690b3f8b 1761 /**
AnnaBridge 165:d1b4690b3f8b 1762 \brief get FPU type
AnnaBridge 165:d1b4690b3f8b 1763 \details returns the FPU type
AnnaBridge 165:d1b4690b3f8b 1764 \returns
AnnaBridge 165:d1b4690b3f8b 1765 - \b 0: No FPU
AnnaBridge 165:d1b4690b3f8b 1766 - \b 1: Single precision FPU
AnnaBridge 165:d1b4690b3f8b 1767 - \b 2: Double + Single precision FPU
AnnaBridge 165:d1b4690b3f8b 1768 */
AnnaBridge 165:d1b4690b3f8b 1769 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 165:d1b4690b3f8b 1770 {
AnnaBridge 165:d1b4690b3f8b 1771 return 0U; /* No FPU */
AnnaBridge 165:d1b4690b3f8b 1772 }
AnnaBridge 165:d1b4690b3f8b 1773
AnnaBridge 165:d1b4690b3f8b 1774
AnnaBridge 165:d1b4690b3f8b 1775 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 165:d1b4690b3f8b 1776
AnnaBridge 165:d1b4690b3f8b 1777
AnnaBridge 165:d1b4690b3f8b 1778
AnnaBridge 165:d1b4690b3f8b 1779 /* ########################## SAU functions #################################### */
AnnaBridge 165:d1b4690b3f8b 1780 /**
AnnaBridge 165:d1b4690b3f8b 1781 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 165:d1b4690b3f8b 1782 \defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge 165:d1b4690b3f8b 1783 \brief Functions that configure the SAU.
AnnaBridge 165:d1b4690b3f8b 1784 @{
AnnaBridge 165:d1b4690b3f8b 1785 */
AnnaBridge 165:d1b4690b3f8b 1786
AnnaBridge 165:d1b4690b3f8b 1787 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 165:d1b4690b3f8b 1788
AnnaBridge 165:d1b4690b3f8b 1789 /**
AnnaBridge 165:d1b4690b3f8b 1790 \brief Enable SAU
AnnaBridge 165:d1b4690b3f8b 1791 \details Enables the Security Attribution Unit (SAU).
AnnaBridge 165:d1b4690b3f8b 1792 */
AnnaBridge 165:d1b4690b3f8b 1793 __STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge 165:d1b4690b3f8b 1794 {
AnnaBridge 165:d1b4690b3f8b 1795 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
AnnaBridge 165:d1b4690b3f8b 1796 }
AnnaBridge 165:d1b4690b3f8b 1797
AnnaBridge 165:d1b4690b3f8b 1798
AnnaBridge 165:d1b4690b3f8b 1799
AnnaBridge 165:d1b4690b3f8b 1800 /**
AnnaBridge 165:d1b4690b3f8b 1801 \brief Disable SAU
AnnaBridge 165:d1b4690b3f8b 1802 \details Disables the Security Attribution Unit (SAU).
AnnaBridge 165:d1b4690b3f8b 1803 */
AnnaBridge 165:d1b4690b3f8b 1804 __STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge 165:d1b4690b3f8b 1805 {
AnnaBridge 165:d1b4690b3f8b 1806 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge 165:d1b4690b3f8b 1807 }
AnnaBridge 165:d1b4690b3f8b 1808
AnnaBridge 165:d1b4690b3f8b 1809 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 165:d1b4690b3f8b 1810
AnnaBridge 165:d1b4690b3f8b 1811 /*@} end of CMSIS_Core_SAUFunctions */
AnnaBridge 165:d1b4690b3f8b 1812
AnnaBridge 165:d1b4690b3f8b 1813
AnnaBridge 165:d1b4690b3f8b 1814
AnnaBridge 165:d1b4690b3f8b 1815
AnnaBridge 165:d1b4690b3f8b 1816 /* ################################## SysTick function ############################################ */
AnnaBridge 165:d1b4690b3f8b 1817 /**
AnnaBridge 165:d1b4690b3f8b 1818 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 165:d1b4690b3f8b 1819 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 165:d1b4690b3f8b 1820 \brief Functions that configure the System.
AnnaBridge 165:d1b4690b3f8b 1821 @{
AnnaBridge 165:d1b4690b3f8b 1822 */
AnnaBridge 165:d1b4690b3f8b 1823
AnnaBridge 165:d1b4690b3f8b 1824 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 165:d1b4690b3f8b 1825
AnnaBridge 165:d1b4690b3f8b 1826 /**
AnnaBridge 165:d1b4690b3f8b 1827 \brief System Tick Configuration
AnnaBridge 165:d1b4690b3f8b 1828 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 165:d1b4690b3f8b 1829 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 165:d1b4690b3f8b 1830 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 165:d1b4690b3f8b 1831 \return 0 Function succeeded.
AnnaBridge 165:d1b4690b3f8b 1832 \return 1 Function failed.
AnnaBridge 165:d1b4690b3f8b 1833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 165:d1b4690b3f8b 1834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 165:d1b4690b3f8b 1835 must contain a vendor-specific implementation of this function.
AnnaBridge 165:d1b4690b3f8b 1836 */
AnnaBridge 165:d1b4690b3f8b 1837 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 165:d1b4690b3f8b 1838 {
AnnaBridge 165:d1b4690b3f8b 1839 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 165:d1b4690b3f8b 1840 {
AnnaBridge 165:d1b4690b3f8b 1841 return (1UL); /* Reload value impossible */
AnnaBridge 165:d1b4690b3f8b 1842 }
AnnaBridge 165:d1b4690b3f8b 1843
AnnaBridge 165:d1b4690b3f8b 1844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 165:d1b4690b3f8b 1845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 165:d1b4690b3f8b 1846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 165:d1b4690b3f8b 1847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 165:d1b4690b3f8b 1848 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 165:d1b4690b3f8b 1849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 165:d1b4690b3f8b 1850 return (0UL); /* Function successful */
AnnaBridge 165:d1b4690b3f8b 1851 }
AnnaBridge 165:d1b4690b3f8b 1852
AnnaBridge 165:d1b4690b3f8b 1853 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 165:d1b4690b3f8b 1854 /**
AnnaBridge 165:d1b4690b3f8b 1855 \brief System Tick Configuration (non-secure)
AnnaBridge 165:d1b4690b3f8b 1856 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge 165:d1b4690b3f8b 1857 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 165:d1b4690b3f8b 1858 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 165:d1b4690b3f8b 1859 \return 0 Function succeeded.
AnnaBridge 165:d1b4690b3f8b 1860 \return 1 Function failed.
AnnaBridge 165:d1b4690b3f8b 1861 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 165:d1b4690b3f8b 1862 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 165:d1b4690b3f8b 1863 must contain a vendor-specific implementation of this function.
AnnaBridge 165:d1b4690b3f8b 1864
AnnaBridge 165:d1b4690b3f8b 1865 */
AnnaBridge 165:d1b4690b3f8b 1866 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge 165:d1b4690b3f8b 1867 {
AnnaBridge 165:d1b4690b3f8b 1868 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 165:d1b4690b3f8b 1869 {
AnnaBridge 165:d1b4690b3f8b 1870 return (1UL); /* Reload value impossible */
AnnaBridge 165:d1b4690b3f8b 1871 }
AnnaBridge 165:d1b4690b3f8b 1872
AnnaBridge 165:d1b4690b3f8b 1873 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 165:d1b4690b3f8b 1874 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 165:d1b4690b3f8b 1875 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 165:d1b4690b3f8b 1876 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 165:d1b4690b3f8b 1877 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 165:d1b4690b3f8b 1878 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 165:d1b4690b3f8b 1879 return (0UL); /* Function successful */
AnnaBridge 165:d1b4690b3f8b 1880 }
AnnaBridge 165:d1b4690b3f8b 1881 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 165:d1b4690b3f8b 1882
AnnaBridge 165:d1b4690b3f8b 1883 #endif
AnnaBridge 165:d1b4690b3f8b 1884
AnnaBridge 165:d1b4690b3f8b 1885 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 165:d1b4690b3f8b 1886
AnnaBridge 165:d1b4690b3f8b 1887
AnnaBridge 165:d1b4690b3f8b 1888
AnnaBridge 165:d1b4690b3f8b 1889
AnnaBridge 165:d1b4690b3f8b 1890 #ifdef __cplusplus
AnnaBridge 165:d1b4690b3f8b 1891 }
AnnaBridge 165:d1b4690b3f8b 1892 #endif
AnnaBridge 165:d1b4690b3f8b 1893
AnnaBridge 165:d1b4690b3f8b 1894 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
AnnaBridge 165:d1b4690b3f8b 1895
AnnaBridge 165:d1b4690b3f8b 1896 #endif /* __CMSIS_GENERIC */