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TARGET_VBLUNO52/core_cm3.h@160:5571c4ff569f, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 16:13:02 2018 +0000
Revision:
160:5571c4ff569f
Parent:
148:fd96258d940d 
mbed library. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 148:fd96258d940d 1 /**************************************************************************//**
Kojto 148:fd96258d940d 2 * @file core_cm3.h
Kojto 148:fd96258d940d 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Anna Bridge 160:5571c4ff569f 4 * @version V5.0.3
Anna Bridge 160:5571c4ff569f 5 * @date 09. August 2017
Kojto 148:fd96258d940d 6 ******************************************************************************/
Kojto 148:fd96258d940d 7 /*
Kojto 148:fd96258d940d 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
Kojto 148:fd96258d940d 9 *
Kojto 148:fd96258d940d 10 * SPDX-License-Identifier: Apache-2.0
Kojto 148:fd96258d940d 11 *
Kojto 148:fd96258d940d 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Kojto 148:fd96258d940d 13 * not use this file except in compliance with the License.
Kojto 148:fd96258d940d 14 * You may obtain a copy of the License at
Kojto 148:fd96258d940d 15 *
Kojto 148:fd96258d940d 16 * www.apache.org/licenses/LICENSE-2.0
Kojto 148:fd96258d940d 17 *
Kojto 148:fd96258d940d 18 * Unless required by applicable law or agreed to in writing, software
Kojto 148:fd96258d940d 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Kojto 148:fd96258d940d 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 148:fd96258d940d 21 * See the License for the specific language governing permissions and
Kojto 148:fd96258d940d 22 * limitations under the License.
Kojto 148:fd96258d940d 23 */
Kojto 148:fd96258d940d 24
Kojto 148:fd96258d940d 25 #if defined ( __ICCARM__ )
Kojto 148:fd96258d940d 26 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 148:fd96258d940d 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Kojto 148:fd96258d940d 28 #pragma clang system_header /* treat file as system include file */
Kojto 148:fd96258d940d 29 #endif
Kojto 148:fd96258d940d 30
Kojto 148:fd96258d940d 31 #ifndef __CORE_CM3_H_GENERIC
Kojto 148:fd96258d940d 32 #define __CORE_CM3_H_GENERIC
Kojto 148:fd96258d940d 33
Kojto 148:fd96258d940d 34 #include <stdint.h>
Kojto 148:fd96258d940d 35
Kojto 148:fd96258d940d 36 #ifdef __cplusplus
Kojto 148:fd96258d940d 37 extern "C" {
Kojto 148:fd96258d940d 38 #endif
Kojto 148:fd96258d940d 39
Kojto 148:fd96258d940d 40 /**
Kojto 148:fd96258d940d 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 148:fd96258d940d 42 CMSIS violates the following MISRA-C:2004 rules:
Kojto 148:fd96258d940d 43
Kojto 148:fd96258d940d 44 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 148:fd96258d940d 45 Function definitions in header files are used to allow 'inlining'.
Kojto 148:fd96258d940d 46
Kojto 148:fd96258d940d 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 148:fd96258d940d 48 Unions are used for effective representation of core registers.
Kojto 148:fd96258d940d 49
Kojto 148:fd96258d940d 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 148:fd96258d940d 51 Function-like macros are used to allow more efficient code.
Kojto 148:fd96258d940d 52 */
Kojto 148:fd96258d940d 53
Kojto 148:fd96258d940d 54
Kojto 148:fd96258d940d 55 /*******************************************************************************
Kojto 148:fd96258d940d 56 * CMSIS definitions
Kojto 148:fd96258d940d 57 ******************************************************************************/
Kojto 148:fd96258d940d 58 /**
Kojto 148:fd96258d940d 59 \ingroup Cortex_M3
Kojto 148:fd96258d940d 60 @{
Kojto 148:fd96258d940d 61 */
Kojto 148:fd96258d940d 62
Anna Bridge 160:5571c4ff569f 63 #include "cmsis_version.h"
Anna Bridge 160:5571c4ff569f 64
Kojto 148:fd96258d940d 65 /* CMSIS CM3 definitions */
Anna Bridge 160:5571c4ff569f 66 #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 160:5571c4ff569f 67 #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Kojto 148:fd96258d940d 68 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 160:5571c4ff569f 69 __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Kojto 148:fd96258d940d 70
Kojto 148:fd96258d940d 71 #define __CORTEX_M (3U) /*!< Cortex-M Core */
Kojto 148:fd96258d940d 72
Kojto 148:fd96258d940d 73 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 148:fd96258d940d 74 This core does not support an FPU at all
Kojto 148:fd96258d940d 75 */
Kojto 148:fd96258d940d 76 #define __FPU_USED 0U
Kojto 148:fd96258d940d 77
Kojto 148:fd96258d940d 78 #if defined ( __CC_ARM )
Kojto 148:fd96258d940d 79 #if defined __TARGET_FPU_VFP
Kojto 148:fd96258d940d 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 81 #endif
Kojto 148:fd96258d940d 82
Kojto 148:fd96258d940d 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Kojto 148:fd96258d940d 84 #if defined __ARM_PCS_VFP
Kojto 148:fd96258d940d 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 86 #endif
Kojto 148:fd96258d940d 87
Kojto 148:fd96258d940d 88 #elif defined ( __GNUC__ )
Kojto 148:fd96258d940d 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 148:fd96258d940d 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 91 #endif
Kojto 148:fd96258d940d 92
Kojto 148:fd96258d940d 93 #elif defined ( __ICCARM__ )
Kojto 148:fd96258d940d 94 #if defined __ARMVFP__
Kojto 148:fd96258d940d 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 96 #endif
Kojto 148:fd96258d940d 97
Kojto 148:fd96258d940d 98 #elif defined ( __TI_ARM__ )
Kojto 148:fd96258d940d 99 #if defined __TI_VFP_SUPPORT__
Kojto 148:fd96258d940d 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 101 #endif
Kojto 148:fd96258d940d 102
Kojto 148:fd96258d940d 103 #elif defined ( __TASKING__ )
Kojto 148:fd96258d940d 104 #if defined __FPU_VFP__
Kojto 148:fd96258d940d 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 106 #endif
Kojto 148:fd96258d940d 107
Kojto 148:fd96258d940d 108 #elif defined ( __CSMC__ )
Kojto 148:fd96258d940d 109 #if ( __CSMC__ & 0x400U)
Kojto 148:fd96258d940d 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 111 #endif
Kojto 148:fd96258d940d 112
Kojto 148:fd96258d940d 113 #endif
Kojto 148:fd96258d940d 114
Kojto 148:fd96258d940d 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Kojto 148:fd96258d940d 116
Kojto 148:fd96258d940d 117
Kojto 148:fd96258d940d 118 #ifdef __cplusplus
Kojto 148:fd96258d940d 119 }
Kojto 148:fd96258d940d 120 #endif
Kojto 148:fd96258d940d 121
Kojto 148:fd96258d940d 122 #endif /* __CORE_CM3_H_GENERIC */
Kojto 148:fd96258d940d 123
Kojto 148:fd96258d940d 124 #ifndef __CMSIS_GENERIC
Kojto 148:fd96258d940d 125
Kojto 148:fd96258d940d 126 #ifndef __CORE_CM3_H_DEPENDANT
Kojto 148:fd96258d940d 127 #define __CORE_CM3_H_DEPENDANT
Kojto 148:fd96258d940d 128
Kojto 148:fd96258d940d 129 #ifdef __cplusplus
Kojto 148:fd96258d940d 130 extern "C" {
Kojto 148:fd96258d940d 131 #endif
Kojto 148:fd96258d940d 132
Kojto 148:fd96258d940d 133 /* check device defines and use defaults */
Kojto 148:fd96258d940d 134 #if defined __CHECK_DEVICE_DEFINES
Kojto 148:fd96258d940d 135 #ifndef __CM3_REV
Kojto 148:fd96258d940d 136 #define __CM3_REV 0x0200U
Kojto 148:fd96258d940d 137 #warning "__CM3_REV not defined in device header file; using default!"
Kojto 148:fd96258d940d 138 #endif
Kojto 148:fd96258d940d 139
Kojto 148:fd96258d940d 140 #ifndef __MPU_PRESENT
Kojto 148:fd96258d940d 141 #define __MPU_PRESENT 0U
Kojto 148:fd96258d940d 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 148:fd96258d940d 143 #endif
Kojto 148:fd96258d940d 144
Kojto 148:fd96258d940d 145 #ifndef __NVIC_PRIO_BITS
Kojto 148:fd96258d940d 146 #define __NVIC_PRIO_BITS 3U
Kojto 148:fd96258d940d 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 148:fd96258d940d 148 #endif
Kojto 148:fd96258d940d 149
Kojto 148:fd96258d940d 150 #ifndef __Vendor_SysTickConfig
Kojto 148:fd96258d940d 151 #define __Vendor_SysTickConfig 0U
Kojto 148:fd96258d940d 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 148:fd96258d940d 153 #endif
Kojto 148:fd96258d940d 154 #endif
Kojto 148:fd96258d940d 155
Kojto 148:fd96258d940d 156 /* IO definitions (access restrictions to peripheral registers) */
Kojto 148:fd96258d940d 157 /**
Kojto 148:fd96258d940d 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 148:fd96258d940d 159
Kojto 148:fd96258d940d 160 <strong>IO Type Qualifiers</strong> are used
Kojto 148:fd96258d940d 161 \li to specify the access to peripheral variables.
Kojto 148:fd96258d940d 162 \li for automatic generation of peripheral register debug information.
Kojto 148:fd96258d940d 163 */
Kojto 148:fd96258d940d 164 #ifdef __cplusplus
Kojto 148:fd96258d940d 165 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 148:fd96258d940d 166 #else
Kojto 148:fd96258d940d 167 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 148:fd96258d940d 168 #endif
Kojto 148:fd96258d940d 169 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 148:fd96258d940d 170 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 148:fd96258d940d 171
Kojto 148:fd96258d940d 172 /* following defines should be used for structure members */
Kojto 148:fd96258d940d 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Kojto 148:fd96258d940d 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
Kojto 148:fd96258d940d 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Kojto 148:fd96258d940d 176
Kojto 148:fd96258d940d 177 /*@} end of group Cortex_M3 */
Kojto 148:fd96258d940d 178
Kojto 148:fd96258d940d 179
Kojto 148:fd96258d940d 180
Kojto 148:fd96258d940d 181 /*******************************************************************************
Kojto 148:fd96258d940d 182 * Register Abstraction
Kojto 148:fd96258d940d 183 Core Register contain:
Kojto 148:fd96258d940d 184 - Core Register
Kojto 148:fd96258d940d 185 - Core NVIC Register
Kojto 148:fd96258d940d 186 - Core SCB Register
Kojto 148:fd96258d940d 187 - Core SysTick Register
Kojto 148:fd96258d940d 188 - Core Debug Register
Kojto 148:fd96258d940d 189 - Core MPU Register
Kojto 148:fd96258d940d 190 ******************************************************************************/
Kojto 148:fd96258d940d 191 /**
Kojto 148:fd96258d940d 192 \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 148:fd96258d940d 193 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 148:fd96258d940d 194 */
Kojto 148:fd96258d940d 195
Kojto 148:fd96258d940d 196 /**
Kojto 148:fd96258d940d 197 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 198 \defgroup CMSIS_CORE Status and Control Registers
Kojto 148:fd96258d940d 199 \brief Core Register type definitions.
Kojto 148:fd96258d940d 200 @{
Kojto 148:fd96258d940d 201 */
Kojto 148:fd96258d940d 202
Kojto 148:fd96258d940d 203 /**
Kojto 148:fd96258d940d 204 \brief Union type to access the Application Program Status Register (APSR).
Kojto 148:fd96258d940d 205 */
Kojto 148:fd96258d940d 206 typedef union
Kojto 148:fd96258d940d 207 {
Kojto 148:fd96258d940d 208 struct
Kojto 148:fd96258d940d 209 {
Kojto 148:fd96258d940d 210 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 148:fd96258d940d 211 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 148:fd96258d940d 212 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 148:fd96258d940d 213 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 148:fd96258d940d 214 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 148:fd96258d940d 215 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 148:fd96258d940d 216 } b; /*!< Structure used for bit access */
Kojto 148:fd96258d940d 217 uint32_t w; /*!< Type used for word access */
Kojto 148:fd96258d940d 218 } APSR_Type;
Kojto 148:fd96258d940d 219
Kojto 148:fd96258d940d 220 /* APSR Register Definitions */
Kojto 148:fd96258d940d 221 #define APSR_N_Pos 31U /*!< APSR: N Position */
Kojto 148:fd96258d940d 222 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 148:fd96258d940d 223
Kojto 148:fd96258d940d 224 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Kojto 148:fd96258d940d 225 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 148:fd96258d940d 226
Kojto 148:fd96258d940d 227 #define APSR_C_Pos 29U /*!< APSR: C Position */
Kojto 148:fd96258d940d 228 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 148:fd96258d940d 229
Kojto 148:fd96258d940d 230 #define APSR_V_Pos 28U /*!< APSR: V Position */
Kojto 148:fd96258d940d 231 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 148:fd96258d940d 232
Kojto 148:fd96258d940d 233 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
Kojto 148:fd96258d940d 234 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 148:fd96258d940d 235
Kojto 148:fd96258d940d 236
Kojto 148:fd96258d940d 237 /**
Kojto 148:fd96258d940d 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 148:fd96258d940d 239 */
Kojto 148:fd96258d940d 240 typedef union
Kojto 148:fd96258d940d 241 {
Kojto 148:fd96258d940d 242 struct
Kojto 148:fd96258d940d 243 {
Kojto 148:fd96258d940d 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 148:fd96258d940d 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 148:fd96258d940d 246 } b; /*!< Structure used for bit access */
Kojto 148:fd96258d940d 247 uint32_t w; /*!< Type used for word access */
Kojto 148:fd96258d940d 248 } IPSR_Type;
Kojto 148:fd96258d940d 249
Kojto 148:fd96258d940d 250 /* IPSR Register Definitions */
Kojto 148:fd96258d940d 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Kojto 148:fd96258d940d 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 148:fd96258d940d 253
Kojto 148:fd96258d940d 254
Kojto 148:fd96258d940d 255 /**
Kojto 148:fd96258d940d 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 148:fd96258d940d 257 */
Kojto 148:fd96258d940d 258 typedef union
Kojto 148:fd96258d940d 259 {
Kojto 148:fd96258d940d 260 struct
Kojto 148:fd96258d940d 261 {
Kojto 148:fd96258d940d 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 148:fd96258d940d 263 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
Kojto 148:fd96258d940d 264 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
Kojto 148:fd96258d940d 265 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
Kojto 148:fd96258d940d 266 uint32_t T:1; /*!< bit: 24 Thumb bit */
Kojto 148:fd96258d940d 267 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
Kojto 148:fd96258d940d 268 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 148:fd96258d940d 269 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 148:fd96258d940d 270 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 148:fd96258d940d 271 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 148:fd96258d940d 272 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 148:fd96258d940d 273 } b; /*!< Structure used for bit access */
Kojto 148:fd96258d940d 274 uint32_t w; /*!< Type used for word access */
Kojto 148:fd96258d940d 275 } xPSR_Type;
Kojto 148:fd96258d940d 276
Kojto 148:fd96258d940d 277 /* xPSR Register Definitions */
Kojto 148:fd96258d940d 278 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Kojto 148:fd96258d940d 279 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 148:fd96258d940d 280
Kojto 148:fd96258d940d 281 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Kojto 148:fd96258d940d 282 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 148:fd96258d940d 283
Kojto 148:fd96258d940d 284 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Kojto 148:fd96258d940d 285 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 148:fd96258d940d 286
Kojto 148:fd96258d940d 287 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Kojto 148:fd96258d940d 288 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 148:fd96258d940d 289
Kojto 148:fd96258d940d 290 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
Kojto 148:fd96258d940d 291 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 148:fd96258d940d 292
Kojto 148:fd96258d940d 293 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
Kojto 148:fd96258d940d 294 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
Kojto 148:fd96258d940d 295
Kojto 148:fd96258d940d 296 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Kojto 148:fd96258d940d 297 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 148:fd96258d940d 298
Kojto 148:fd96258d940d 299 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
Kojto 148:fd96258d940d 300 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
Kojto 148:fd96258d940d 301
Kojto 148:fd96258d940d 302 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Kojto 148:fd96258d940d 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 148:fd96258d940d 304
Kojto 148:fd96258d940d 305
Kojto 148:fd96258d940d 306 /**
Kojto 148:fd96258d940d 307 \brief Union type to access the Control Registers (CONTROL).
Kojto 148:fd96258d940d 308 */
Kojto 148:fd96258d940d 309 typedef union
Kojto 148:fd96258d940d 310 {
Kojto 148:fd96258d940d 311 struct
Kojto 148:fd96258d940d 312 {
Kojto 148:fd96258d940d 313 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 148:fd96258d940d 314 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 148:fd96258d940d 315 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 148:fd96258d940d 316 } b; /*!< Structure used for bit access */
Kojto 148:fd96258d940d 317 uint32_t w; /*!< Type used for word access */
Kojto 148:fd96258d940d 318 } CONTROL_Type;
Kojto 148:fd96258d940d 319
Kojto 148:fd96258d940d 320 /* CONTROL Register Definitions */
Kojto 148:fd96258d940d 321 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Kojto 148:fd96258d940d 322 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 148:fd96258d940d 323
Kojto 148:fd96258d940d 324 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Kojto 148:fd96258d940d 325 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 148:fd96258d940d 326
Kojto 148:fd96258d940d 327 /*@} end of group CMSIS_CORE */
Kojto 148:fd96258d940d 328
Kojto 148:fd96258d940d 329
Kojto 148:fd96258d940d 330 /**
Kojto 148:fd96258d940d 331 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 332 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 148:fd96258d940d 333 \brief Type definitions for the NVIC Registers
Kojto 148:fd96258d940d 334 @{
Kojto 148:fd96258d940d 335 */
Kojto 148:fd96258d940d 336
Kojto 148:fd96258d940d 337 /**
Kojto 148:fd96258d940d 338 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 148:fd96258d940d 339 */
Kojto 148:fd96258d940d 340 typedef struct
Kojto 148:fd96258d940d 341 {
Kojto 148:fd96258d940d 342 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 148:fd96258d940d 343 uint32_t RESERVED0[24U];
Kojto 148:fd96258d940d 344 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 148:fd96258d940d 345 uint32_t RSERVED1[24U];
Kojto 148:fd96258d940d 346 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 148:fd96258d940d 347 uint32_t RESERVED2[24U];
Kojto 148:fd96258d940d 348 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 148:fd96258d940d 349 uint32_t RESERVED3[24U];
Kojto 148:fd96258d940d 350 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 148:fd96258d940d 351 uint32_t RESERVED4[56U];
Kojto 148:fd96258d940d 352 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 148:fd96258d940d 353 uint32_t RESERVED5[644U];
Kojto 148:fd96258d940d 354 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 148:fd96258d940d 355 } NVIC_Type;
Kojto 148:fd96258d940d 356
Kojto 148:fd96258d940d 357 /* Software Triggered Interrupt Register Definitions */
Kojto 148:fd96258d940d 358 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
Kojto 148:fd96258d940d 359 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Kojto 148:fd96258d940d 360
Kojto 148:fd96258d940d 361 /*@} end of group CMSIS_NVIC */
Kojto 148:fd96258d940d 362
Kojto 148:fd96258d940d 363
Kojto 148:fd96258d940d 364 /**
Kojto 148:fd96258d940d 365 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 366 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 148:fd96258d940d 367 \brief Type definitions for the System Control Block Registers
Kojto 148:fd96258d940d 368 @{
Kojto 148:fd96258d940d 369 */
Kojto 148:fd96258d940d 370
Kojto 148:fd96258d940d 371 /**
Kojto 148:fd96258d940d 372 \brief Structure type to access the System Control Block (SCB).
Kojto 148:fd96258d940d 373 */
Kojto 148:fd96258d940d 374 typedef struct
Kojto 148:fd96258d940d 375 {
Kojto 148:fd96258d940d 376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 148:fd96258d940d 377 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 148:fd96258d940d 378 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 148:fd96258d940d 379 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 148:fd96258d940d 380 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 148:fd96258d940d 381 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 148:fd96258d940d 382 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 148:fd96258d940d 383 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 148:fd96258d940d 384 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 148:fd96258d940d 385 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 148:fd96258d940d 386 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 148:fd96258d940d 387 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 148:fd96258d940d 388 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 148:fd96258d940d 389 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 148:fd96258d940d 390 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 148:fd96258d940d 391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 148:fd96258d940d 392 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 148:fd96258d940d 393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 148:fd96258d940d 394 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 148:fd96258d940d 395 uint32_t RESERVED0[5U];
Kojto 148:fd96258d940d 396 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 148:fd96258d940d 397 } SCB_Type;
Kojto 148:fd96258d940d 398
Kojto 148:fd96258d940d 399 /* SCB CPUID Register Definitions */
Kojto 148:fd96258d940d 400 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 148:fd96258d940d 401 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 148:fd96258d940d 402
Kojto 148:fd96258d940d 403 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Kojto 148:fd96258d940d 404 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 148:fd96258d940d 405
Kojto 148:fd96258d940d 406 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 148:fd96258d940d 407 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 148:fd96258d940d 408
Kojto 148:fd96258d940d 409 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Kojto 148:fd96258d940d 410 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 148:fd96258d940d 411
Kojto 148:fd96258d940d 412 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Kojto 148:fd96258d940d 413 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 148:fd96258d940d 414
Kojto 148:fd96258d940d 415 /* SCB Interrupt Control State Register Definitions */
Kojto 148:fd96258d940d 416 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Kojto 148:fd96258d940d 417 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 148:fd96258d940d 418
Kojto 148:fd96258d940d 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Kojto 148:fd96258d940d 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 148:fd96258d940d 421
Kojto 148:fd96258d940d 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Kojto 148:fd96258d940d 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 148:fd96258d940d 424
Kojto 148:fd96258d940d 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Kojto 148:fd96258d940d 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 148:fd96258d940d 427
Kojto 148:fd96258d940d 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Kojto 148:fd96258d940d 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 148:fd96258d940d 430
Kojto 148:fd96258d940d 431 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 148:fd96258d940d 432 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 148:fd96258d940d 433
Kojto 148:fd96258d940d 434 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Kojto 148:fd96258d940d 435 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 148:fd96258d940d 436
Kojto 148:fd96258d940d 437 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Kojto 148:fd96258d940d 438 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 148:fd96258d940d 439
Kojto 148:fd96258d940d 440 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
Kojto 148:fd96258d940d 441 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 148:fd96258d940d 442
Kojto 148:fd96258d940d 443 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Kojto 148:fd96258d940d 444 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 148:fd96258d940d 445
Kojto 148:fd96258d940d 446 /* SCB Vector Table Offset Register Definitions */
Kojto 148:fd96258d940d 447 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
Kojto 148:fd96258d940d 448 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
Kojto 148:fd96258d940d 449 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Kojto 148:fd96258d940d 450
Kojto 148:fd96258d940d 451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Kojto 148:fd96258d940d 452 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 148:fd96258d940d 453 #else
Kojto 148:fd96258d940d 454 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Kojto 148:fd96258d940d 455 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 148:fd96258d940d 456 #endif
Kojto 148:fd96258d940d 457
Kojto 148:fd96258d940d 458 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 148:fd96258d940d 459 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Kojto 148:fd96258d940d 460 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 148:fd96258d940d 461
Kojto 148:fd96258d940d 462 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 148:fd96258d940d 463 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 148:fd96258d940d 464
Kojto 148:fd96258d940d 465 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Kojto 148:fd96258d940d 466 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 148:fd96258d940d 467
Kojto 148:fd96258d940d 468 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
Kojto 148:fd96258d940d 469 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 148:fd96258d940d 470
Kojto 148:fd96258d940d 471 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 148:fd96258d940d 472 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 148:fd96258d940d 473
Kojto 148:fd96258d940d 474 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 148:fd96258d940d 475 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 148:fd96258d940d 476
Kojto 148:fd96258d940d 477 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
Kojto 148:fd96258d940d 478 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 148:fd96258d940d 479
Kojto 148:fd96258d940d 480 /* SCB System Control Register Definitions */
Kojto 148:fd96258d940d 481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Kojto 148:fd96258d940d 482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 148:fd96258d940d 483
Kojto 148:fd96258d940d 484 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Kojto 148:fd96258d940d 485 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 148:fd96258d940d 486
Kojto 148:fd96258d940d 487 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 148:fd96258d940d 488 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 148:fd96258d940d 489
Kojto 148:fd96258d940d 490 /* SCB Configuration Control Register Definitions */
Kojto 148:fd96258d940d 491 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Kojto 148:fd96258d940d 492 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 148:fd96258d940d 493
Kojto 148:fd96258d940d 494 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
Kojto 148:fd96258d940d 495 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 148:fd96258d940d 496
Kojto 148:fd96258d940d 497 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
Kojto 148:fd96258d940d 498 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 148:fd96258d940d 499
Kojto 148:fd96258d940d 500 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 148:fd96258d940d 501 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 148:fd96258d940d 502
Kojto 148:fd96258d940d 503 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
Kojto 148:fd96258d940d 504 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 148:fd96258d940d 505
Kojto 148:fd96258d940d 506 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 148:fd96258d940d 507 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 148:fd96258d940d 508
Kojto 148:fd96258d940d 509 /* SCB System Handler Control and State Register Definitions */
Kojto 148:fd96258d940d 510 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 148:fd96258d940d 511 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 148:fd96258d940d 512
Kojto 148:fd96258d940d 513 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 148:fd96258d940d 514 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 148:fd96258d940d 515
Kojto 148:fd96258d940d 516 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 148:fd96258d940d 517 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 148:fd96258d940d 518
Kojto 148:fd96258d940d 519 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 148:fd96258d940d 520 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 148:fd96258d940d 521
Kojto 148:fd96258d940d 522 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 148:fd96258d940d 523 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 148:fd96258d940d 524
Kojto 148:fd96258d940d 525 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 148:fd96258d940d 526 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 148:fd96258d940d 527
Kojto 148:fd96258d940d 528 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 148:fd96258d940d 529 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 148:fd96258d940d 530
Kojto 148:fd96258d940d 531 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 148:fd96258d940d 532 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 148:fd96258d940d 533
Kojto 148:fd96258d940d 534 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
Kojto 148:fd96258d940d 535 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 148:fd96258d940d 536
Kojto 148:fd96258d940d 537 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
Kojto 148:fd96258d940d 538 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 148:fd96258d940d 539
Kojto 148:fd96258d940d 540 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
Kojto 148:fd96258d940d 541 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 148:fd96258d940d 542
Kojto 148:fd96258d940d 543 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 148:fd96258d940d 544 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 148:fd96258d940d 545
Kojto 148:fd96258d940d 546 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 148:fd96258d940d 547 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 148:fd96258d940d 548
Kojto 148:fd96258d940d 549 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 148:fd96258d940d 550 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 148:fd96258d940d 551
Kojto 148:fd96258d940d 552 /* SCB Configurable Fault Status Register Definitions */
Kojto 148:fd96258d940d 553 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 148:fd96258d940d 554 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 148:fd96258d940d 555
Kojto 148:fd96258d940d 556 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 148:fd96258d940d 557 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 148:fd96258d940d 558
Kojto 148:fd96258d940d 559 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 148:fd96258d940d 560 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 148:fd96258d940d 561
Kojto 148:fd96258d940d 562 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
Kojto 148:fd96258d940d 563 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
Kojto 148:fd96258d940d 564 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
Kojto 148:fd96258d940d 565
Kojto 148:fd96258d940d 566 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
Kojto 148:fd96258d940d 567 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
Kojto 148:fd96258d940d 568
Kojto 148:fd96258d940d 569 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
Kojto 148:fd96258d940d 570 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
Kojto 148:fd96258d940d 571
Kojto 148:fd96258d940d 572 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
Kojto 148:fd96258d940d 573 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
Kojto 148:fd96258d940d 574
Kojto 148:fd96258d940d 575 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
Kojto 148:fd96258d940d 576 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
Kojto 148:fd96258d940d 577
Kojto 148:fd96258d940d 578 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
Kojto 148:fd96258d940d 579 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
Kojto 148:fd96258d940d 580 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
Kojto 148:fd96258d940d 581
Kojto 148:fd96258d940d 582 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
Kojto 148:fd96258d940d 583 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
Kojto 148:fd96258d940d 584
Kojto 148:fd96258d940d 585 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
Kojto 148:fd96258d940d 586 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
Kojto 148:fd96258d940d 587
Kojto 148:fd96258d940d 588 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
Kojto 148:fd96258d940d 589 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
Kojto 148:fd96258d940d 590
Kojto 148:fd96258d940d 591 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
Kojto 148:fd96258d940d 592 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
Kojto 148:fd96258d940d 593
Kojto 148:fd96258d940d 594 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
Kojto 148:fd96258d940d 595 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
Kojto 148:fd96258d940d 596
Kojto 148:fd96258d940d 597 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
Kojto 148:fd96258d940d 598 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
Kojto 148:fd96258d940d 599 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
Kojto 148:fd96258d940d 600
Kojto 148:fd96258d940d 601 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
Kojto 148:fd96258d940d 602 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
Kojto 148:fd96258d940d 603
Kojto 148:fd96258d940d 604 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
Kojto 148:fd96258d940d 605 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
Kojto 148:fd96258d940d 606
Kojto 148:fd96258d940d 607 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
Kojto 148:fd96258d940d 608 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
Kojto 148:fd96258d940d 609
Kojto 148:fd96258d940d 610 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
Kojto 148:fd96258d940d 611 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
Kojto 148:fd96258d940d 612
Kojto 148:fd96258d940d 613 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
Kojto 148:fd96258d940d 614 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
Kojto 148:fd96258d940d 615
Kojto 148:fd96258d940d 616 /* SCB Hard Fault Status Register Definitions */
Kojto 148:fd96258d940d 617 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
Kojto 148:fd96258d940d 618 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 148:fd96258d940d 619
Kojto 148:fd96258d940d 620 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
Kojto 148:fd96258d940d 621 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 148:fd96258d940d 622
Kojto 148:fd96258d940d 623 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
Kojto 148:fd96258d940d 624 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 148:fd96258d940d 625
Kojto 148:fd96258d940d 626 /* SCB Debug Fault Status Register Definitions */
Kojto 148:fd96258d940d 627 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
Kojto 148:fd96258d940d 628 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 148:fd96258d940d 629
Kojto 148:fd96258d940d 630 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
Kojto 148:fd96258d940d 631 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 148:fd96258d940d 632
Kojto 148:fd96258d940d 633 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
Kojto 148:fd96258d940d 634 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 148:fd96258d940d 635
Kojto 148:fd96258d940d 636 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
Kojto 148:fd96258d940d 637 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 148:fd96258d940d 638
Kojto 148:fd96258d940d 639 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
Kojto 148:fd96258d940d 640 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Kojto 148:fd96258d940d 641
Kojto 148:fd96258d940d 642 /*@} end of group CMSIS_SCB */
Kojto 148:fd96258d940d 643
Kojto 148:fd96258d940d 644
Kojto 148:fd96258d940d 645 /**
Kojto 148:fd96258d940d 646 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 647 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 148:fd96258d940d 648 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 148:fd96258d940d 649 @{
Kojto 148:fd96258d940d 650 */
Kojto 148:fd96258d940d 651
Kojto 148:fd96258d940d 652 /**
Kojto 148:fd96258d940d 653 \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 148:fd96258d940d 654 */
Kojto 148:fd96258d940d 655 typedef struct
Kojto 148:fd96258d940d 656 {
Kojto 148:fd96258d940d 657 uint32_t RESERVED0[1U];
Kojto 148:fd96258d940d 658 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 148:fd96258d940d 659 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
Kojto 148:fd96258d940d 660 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 148:fd96258d940d 661 #else
Kojto 148:fd96258d940d 662 uint32_t RESERVED1[1U];
Kojto 148:fd96258d940d 663 #endif
Kojto 148:fd96258d940d 664 } SCnSCB_Type;
Kojto 148:fd96258d940d 665
Kojto 148:fd96258d940d 666 /* Interrupt Controller Type Register Definitions */
Kojto 148:fd96258d940d 667 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
Kojto 148:fd96258d940d 668 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Kojto 148:fd96258d940d 669
Kojto 148:fd96258d940d 670 /* Auxiliary Control Register Definitions */
Kojto 148:fd96258d940d 671
Kojto 148:fd96258d940d 672 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
Kojto 148:fd96258d940d 673 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Kojto 148:fd96258d940d 674
Kojto 148:fd96258d940d 675 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
Kojto 148:fd96258d940d 676 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
Kojto 148:fd96258d940d 677
Kojto 148:fd96258d940d 678 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
Kojto 148:fd96258d940d 679 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 148:fd96258d940d 680
Kojto 148:fd96258d940d 681 /*@} end of group CMSIS_SCnotSCB */
Kojto 148:fd96258d940d 682
Kojto 148:fd96258d940d 683
Kojto 148:fd96258d940d 684 /**
Kojto 148:fd96258d940d 685 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 686 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 148:fd96258d940d 687 \brief Type definitions for the System Timer Registers.
Kojto 148:fd96258d940d 688 @{
Kojto 148:fd96258d940d 689 */
Kojto 148:fd96258d940d 690
Kojto 148:fd96258d940d 691 /**
Kojto 148:fd96258d940d 692 \brief Structure type to access the System Timer (SysTick).
Kojto 148:fd96258d940d 693 */
Kojto 148:fd96258d940d 694 typedef struct
Kojto 148:fd96258d940d 695 {
Kojto 148:fd96258d940d 696 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 148:fd96258d940d 697 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 148:fd96258d940d 698 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 148:fd96258d940d 699 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 148:fd96258d940d 700 } SysTick_Type;
Kojto 148:fd96258d940d 701
Kojto 148:fd96258d940d 702 /* SysTick Control / Status Register Definitions */
Kojto 148:fd96258d940d 703 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 148:fd96258d940d 704 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 148:fd96258d940d 705
Kojto 148:fd96258d940d 706 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 148:fd96258d940d 707 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 148:fd96258d940d 708
Kojto 148:fd96258d940d 709 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Kojto 148:fd96258d940d 710 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 148:fd96258d940d 711
Kojto 148:fd96258d940d 712 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Kojto 148:fd96258d940d 713 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 148:fd96258d940d 714
Kojto 148:fd96258d940d 715 /* SysTick Reload Register Definitions */
Kojto 148:fd96258d940d 716 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Kojto 148:fd96258d940d 717 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 148:fd96258d940d 718
Kojto 148:fd96258d940d 719 /* SysTick Current Register Definitions */
Kojto 148:fd96258d940d 720 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Kojto 148:fd96258d940d 721 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 148:fd96258d940d 722
Kojto 148:fd96258d940d 723 /* SysTick Calibration Register Definitions */
Kojto 148:fd96258d940d 724 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Kojto 148:fd96258d940d 725 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 148:fd96258d940d 726
Kojto 148:fd96258d940d 727 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Kojto 148:fd96258d940d 728 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 148:fd96258d940d 729
Kojto 148:fd96258d940d 730 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Kojto 148:fd96258d940d 731 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 148:fd96258d940d 732
Kojto 148:fd96258d940d 733 /*@} end of group CMSIS_SysTick */
Kojto 148:fd96258d940d 734
Kojto 148:fd96258d940d 735
Kojto 148:fd96258d940d 736 /**
Kojto 148:fd96258d940d 737 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 738 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 148:fd96258d940d 739 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 148:fd96258d940d 740 @{
Kojto 148:fd96258d940d 741 */
Kojto 148:fd96258d940d 742
Kojto 148:fd96258d940d 743 /**
Kojto 148:fd96258d940d 744 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 148:fd96258d940d 745 */
Kojto 148:fd96258d940d 746 typedef struct
Kojto 148:fd96258d940d 747 {
Kojto 148:fd96258d940d 748 __OM union
Kojto 148:fd96258d940d 749 {
Kojto 148:fd96258d940d 750 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 148:fd96258d940d 751 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 148:fd96258d940d 752 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 148:fd96258d940d 753 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 148:fd96258d940d 754 uint32_t RESERVED0[864U];
Kojto 148:fd96258d940d 755 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 148:fd96258d940d 756 uint32_t RESERVED1[15U];
Kojto 148:fd96258d940d 757 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 148:fd96258d940d 758 uint32_t RESERVED2[15U];
Kojto 148:fd96258d940d 759 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 148:fd96258d940d 760 uint32_t RESERVED3[29U];
Kojto 148:fd96258d940d 761 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 148:fd96258d940d 762 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 148:fd96258d940d 763 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 148:fd96258d940d 764 uint32_t RESERVED4[43U];
Kojto 148:fd96258d940d 765 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 148:fd96258d940d 766 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 148:fd96258d940d 767 uint32_t RESERVED5[6U];
Kojto 148:fd96258d940d 768 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 148:fd96258d940d 769 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 148:fd96258d940d 770 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 148:fd96258d940d 771 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 148:fd96258d940d 772 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 148:fd96258d940d 773 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 148:fd96258d940d 774 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 148:fd96258d940d 775 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 148:fd96258d940d 776 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 148:fd96258d940d 777 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 148:fd96258d940d 778 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 148:fd96258d940d 779 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 148:fd96258d940d 780 } ITM_Type;
Kojto 148:fd96258d940d 781
Kojto 148:fd96258d940d 782 /* ITM Trace Privilege Register Definitions */
Kojto 148:fd96258d940d 783 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
Kojto 148:fd96258d940d 784 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Kojto 148:fd96258d940d 785
Kojto 148:fd96258d940d 786 /* ITM Trace Control Register Definitions */
Kojto 148:fd96258d940d 787 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
Kojto 148:fd96258d940d 788 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 148:fd96258d940d 789
Kojto 148:fd96258d940d 790 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
Kojto 148:fd96258d940d 791 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 148:fd96258d940d 792
Kojto 148:fd96258d940d 793 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
Kojto 148:fd96258d940d 794 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 148:fd96258d940d 795
Kojto 148:fd96258d940d 796 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
Kojto 148:fd96258d940d 797 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 148:fd96258d940d 798
Kojto 148:fd96258d940d 799 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
Kojto 148:fd96258d940d 800 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 148:fd96258d940d 801
Kojto 148:fd96258d940d 802 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
Kojto 148:fd96258d940d 803 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 148:fd96258d940d 804
Kojto 148:fd96258d940d 805 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
Kojto 148:fd96258d940d 806 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 148:fd96258d940d 807
Kojto 148:fd96258d940d 808 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
Kojto 148:fd96258d940d 809 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 148:fd96258d940d 810
Kojto 148:fd96258d940d 811 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
Kojto 148:fd96258d940d 812 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 148:fd96258d940d 813
Kojto 148:fd96258d940d 814 /* ITM Integration Write Register Definitions */
Kojto 148:fd96258d940d 815 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
Kojto 148:fd96258d940d 816 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Kojto 148:fd96258d940d 817
Kojto 148:fd96258d940d 818 /* ITM Integration Read Register Definitions */
Kojto 148:fd96258d940d 819 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
Kojto 148:fd96258d940d 820 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Kojto 148:fd96258d940d 821
Kojto 148:fd96258d940d 822 /* ITM Integration Mode Control Register Definitions */
Kojto 148:fd96258d940d 823 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
Kojto 148:fd96258d940d 824 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 148:fd96258d940d 825
Kojto 148:fd96258d940d 826 /* ITM Lock Status Register Definitions */
Kojto 148:fd96258d940d 827 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
Kojto 148:fd96258d940d 828 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 148:fd96258d940d 829
Kojto 148:fd96258d940d 830 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
Kojto 148:fd96258d940d 831 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 148:fd96258d940d 832
Kojto 148:fd96258d940d 833 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
Kojto 148:fd96258d940d 834 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Kojto 148:fd96258d940d 835
Kojto 148:fd96258d940d 836 /*@}*/ /* end of group CMSIS_ITM */
Kojto 148:fd96258d940d 837
Kojto 148:fd96258d940d 838
Kojto 148:fd96258d940d 839 /**
Kojto 148:fd96258d940d 840 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 841 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 148:fd96258d940d 842 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 148:fd96258d940d 843 @{
Kojto 148:fd96258d940d 844 */
Kojto 148:fd96258d940d 845
Kojto 148:fd96258d940d 846 /**
Kojto 148:fd96258d940d 847 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 148:fd96258d940d 848 */
Kojto 148:fd96258d940d 849 typedef struct
Kojto 148:fd96258d940d 850 {
Kojto 148:fd96258d940d 851 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 148:fd96258d940d 852 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 148:fd96258d940d 853 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 148:fd96258d940d 854 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 148:fd96258d940d 855 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 148:fd96258d940d 856 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 148:fd96258d940d 857 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 148:fd96258d940d 858 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 148:fd96258d940d 859 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 148:fd96258d940d 860 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 148:fd96258d940d 861 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 148:fd96258d940d 862 uint32_t RESERVED0[1U];
Kojto 148:fd96258d940d 863 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 148:fd96258d940d 864 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 148:fd96258d940d 865 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 148:fd96258d940d 866 uint32_t RESERVED1[1U];
Kojto 148:fd96258d940d 867 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 148:fd96258d940d 868 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 148:fd96258d940d 869 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 148:fd96258d940d 870 uint32_t RESERVED2[1U];
Kojto 148:fd96258d940d 871 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 148:fd96258d940d 872 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 148:fd96258d940d 873 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 148:fd96258d940d 874 } DWT_Type;
Kojto 148:fd96258d940d 875
Kojto 148:fd96258d940d 876 /* DWT Control Register Definitions */
Kojto 148:fd96258d940d 877 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
Kojto 148:fd96258d940d 878 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 148:fd96258d940d 879
Kojto 148:fd96258d940d 880 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
Kojto 148:fd96258d940d 881 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 148:fd96258d940d 882
Kojto 148:fd96258d940d 883 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 148:fd96258d940d 884 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 148:fd96258d940d 885
Kojto 148:fd96258d940d 886 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
Kojto 148:fd96258d940d 887 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 148:fd96258d940d 888
Kojto 148:fd96258d940d 889 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
Kojto 148:fd96258d940d 890 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 148:fd96258d940d 891
Kojto 148:fd96258d940d 892 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
Kojto 148:fd96258d940d 893 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 148:fd96258d940d 894
Kojto 148:fd96258d940d 895 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 148:fd96258d940d 896 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 148:fd96258d940d 897
Kojto 148:fd96258d940d 898 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
Kojto 148:fd96258d940d 899 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 148:fd96258d940d 900
Kojto 148:fd96258d940d 901 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 148:fd96258d940d 902 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 148:fd96258d940d 903
Kojto 148:fd96258d940d 904 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
Kojto 148:fd96258d940d 905 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 148:fd96258d940d 906
Kojto 148:fd96258d940d 907 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
Kojto 148:fd96258d940d 908 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 148:fd96258d940d 909
Kojto 148:fd96258d940d 910 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
Kojto 148:fd96258d940d 911 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 148:fd96258d940d 912
Kojto 148:fd96258d940d 913 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 148:fd96258d940d 914 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 148:fd96258d940d 915
Kojto 148:fd96258d940d 916 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
Kojto 148:fd96258d940d 917 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 148:fd96258d940d 918
Kojto 148:fd96258d940d 919 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
Kojto 148:fd96258d940d 920 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 148:fd96258d940d 921
Kojto 148:fd96258d940d 922 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
Kojto 148:fd96258d940d 923 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 148:fd96258d940d 924
Kojto 148:fd96258d940d 925 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
Kojto 148:fd96258d940d 926 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 148:fd96258d940d 927
Kojto 148:fd96258d940d 928 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
Kojto 148:fd96258d940d 929 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 148:fd96258d940d 930
Kojto 148:fd96258d940d 931 /* DWT CPI Count Register Definitions */
Kojto 148:fd96258d940d 932 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
Kojto 148:fd96258d940d 933 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Kojto 148:fd96258d940d 934
Kojto 148:fd96258d940d 935 /* DWT Exception Overhead Count Register Definitions */
Kojto 148:fd96258d940d 936 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
Kojto 148:fd96258d940d 937 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 148:fd96258d940d 938
Kojto 148:fd96258d940d 939 /* DWT Sleep Count Register Definitions */
Kojto 148:fd96258d940d 940 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 148:fd96258d940d 941 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 148:fd96258d940d 942
Kojto 148:fd96258d940d 943 /* DWT LSU Count Register Definitions */
Kojto 148:fd96258d940d 944 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
Kojto 148:fd96258d940d 945 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 148:fd96258d940d 946
Kojto 148:fd96258d940d 947 /* DWT Folded-instruction Count Register Definitions */
Kojto 148:fd96258d940d 948 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 148:fd96258d940d 949 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 148:fd96258d940d 950
Kojto 148:fd96258d940d 951 /* DWT Comparator Mask Register Definitions */
Kojto 148:fd96258d940d 952 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
Kojto 148:fd96258d940d 953 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Kojto 148:fd96258d940d 954
Kojto 148:fd96258d940d 955 /* DWT Comparator Function Register Definitions */
Kojto 148:fd96258d940d 956 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
Kojto 148:fd96258d940d 957 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 148:fd96258d940d 958
Kojto 148:fd96258d940d 959 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 148:fd96258d940d 960 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 148:fd96258d940d 961
Kojto 148:fd96258d940d 962 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 148:fd96258d940d 963 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 148:fd96258d940d 964
Kojto 148:fd96258d940d 965 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 148:fd96258d940d 966 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 148:fd96258d940d 967
Kojto 148:fd96258d940d 968 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 148:fd96258d940d 969 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 148:fd96258d940d 970
Kojto 148:fd96258d940d 971 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 148:fd96258d940d 972 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 148:fd96258d940d 973
Kojto 148:fd96258d940d 974 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 148:fd96258d940d 975 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 148:fd96258d940d 976
Kojto 148:fd96258d940d 977 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 148:fd96258d940d 978 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 148:fd96258d940d 979
Kojto 148:fd96258d940d 980 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
Kojto 148:fd96258d940d 981 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 148:fd96258d940d 982
Kojto 148:fd96258d940d 983 /*@}*/ /* end of group CMSIS_DWT */
Kojto 148:fd96258d940d 984
Kojto 148:fd96258d940d 985
Kojto 148:fd96258d940d 986 /**
Kojto 148:fd96258d940d 987 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 988 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 148:fd96258d940d 989 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 148:fd96258d940d 990 @{
Kojto 148:fd96258d940d 991 */
Kojto 148:fd96258d940d 992
Kojto 148:fd96258d940d 993 /**
Kojto 148:fd96258d940d 994 \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 148:fd96258d940d 995 */
Kojto 148:fd96258d940d 996 typedef struct
Kojto 148:fd96258d940d 997 {
Kojto 148:fd96258d940d 998 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 148:fd96258d940d 999 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 148:fd96258d940d 1000 uint32_t RESERVED0[2U];
Kojto 148:fd96258d940d 1001 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 148:fd96258d940d 1002 uint32_t RESERVED1[55U];
Kojto 148:fd96258d940d 1003 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 148:fd96258d940d 1004 uint32_t RESERVED2[131U];
Kojto 148:fd96258d940d 1005 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 148:fd96258d940d 1006 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 148:fd96258d940d 1007 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 148:fd96258d940d 1008 uint32_t RESERVED3[759U];
Kojto 148:fd96258d940d 1009 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 148:fd96258d940d 1010 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 148:fd96258d940d 1011 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 148:fd96258d940d 1012 uint32_t RESERVED4[1U];
Kojto 148:fd96258d940d 1013 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 148:fd96258d940d 1014 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 148:fd96258d940d 1015 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 148:fd96258d940d 1016 uint32_t RESERVED5[39U];
Kojto 148:fd96258d940d 1017 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 148:fd96258d940d 1018 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 148:fd96258d940d 1019 uint32_t RESERVED7[8U];
Kojto 148:fd96258d940d 1020 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 148:fd96258d940d 1021 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 148:fd96258d940d 1022 } TPI_Type;
Kojto 148:fd96258d940d 1023
Kojto 148:fd96258d940d 1024 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 148:fd96258d940d 1025 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
Kojto 148:fd96258d940d 1026 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Kojto 148:fd96258d940d 1027
Kojto 148:fd96258d940d 1028 /* TPI Selected Pin Protocol Register Definitions */
Kojto 148:fd96258d940d 1029 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
Kojto 148:fd96258d940d 1030 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Kojto 148:fd96258d940d 1031
Kojto 148:fd96258d940d 1032 /* TPI Formatter and Flush Status Register Definitions */
Kojto 148:fd96258d940d 1033 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
Kojto 148:fd96258d940d 1034 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 148:fd96258d940d 1035
Kojto 148:fd96258d940d 1036 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
Kojto 148:fd96258d940d 1037 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 148:fd96258d940d 1038
Kojto 148:fd96258d940d 1039 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
Kojto 148:fd96258d940d 1040 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 148:fd96258d940d 1041
Kojto 148:fd96258d940d 1042 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
Kojto 148:fd96258d940d 1043 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Kojto 148:fd96258d940d 1044
Kojto 148:fd96258d940d 1045 /* TPI Formatter and Flush Control Register Definitions */
Kojto 148:fd96258d940d 1046 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
Kojto 148:fd96258d940d 1047 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 148:fd96258d940d 1048
Kojto 148:fd96258d940d 1049 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
Kojto 148:fd96258d940d 1050 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 148:fd96258d940d 1051
Kojto 148:fd96258d940d 1052 /* TPI TRIGGER Register Definitions */
Kojto 148:fd96258d940d 1053 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
Kojto 148:fd96258d940d 1054 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 148:fd96258d940d 1055
Kojto 148:fd96258d940d 1056 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 148:fd96258d940d 1057 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 148:fd96258d940d 1058 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 148:fd96258d940d 1059
Kojto 148:fd96258d940d 1060 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 148:fd96258d940d 1061 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 148:fd96258d940d 1062
Kojto 148:fd96258d940d 1063 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 148:fd96258d940d 1064 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 148:fd96258d940d 1065
Kojto 148:fd96258d940d 1066 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 148:fd96258d940d 1067 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 148:fd96258d940d 1068
Kojto 148:fd96258d940d 1069 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
Kojto 148:fd96258d940d 1070 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 148:fd96258d940d 1071
Kojto 148:fd96258d940d 1072 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
Kojto 148:fd96258d940d 1073 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 148:fd96258d940d 1074
Kojto 148:fd96258d940d 1075 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
Kojto 148:fd96258d940d 1076 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Kojto 148:fd96258d940d 1077
Kojto 148:fd96258d940d 1078 /* TPI ITATBCTR2 Register Definitions */
Kojto 148:fd96258d940d 1079 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 148:fd96258d940d 1080 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 148:fd96258d940d 1081
Kojto 148:fd96258d940d 1082 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 148:fd96258d940d 1083 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 148:fd96258d940d 1084 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 148:fd96258d940d 1085
Kojto 148:fd96258d940d 1086 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 148:fd96258d940d 1087 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 148:fd96258d940d 1088
Kojto 148:fd96258d940d 1089 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 148:fd96258d940d 1090 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 148:fd96258d940d 1091
Kojto 148:fd96258d940d 1092 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 148:fd96258d940d 1093 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 148:fd96258d940d 1094
Kojto 148:fd96258d940d 1095 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
Kojto 148:fd96258d940d 1096 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 148:fd96258d940d 1097
Kojto 148:fd96258d940d 1098 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
Kojto 148:fd96258d940d 1099 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 148:fd96258d940d 1100
Kojto 148:fd96258d940d 1101 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
Kojto 148:fd96258d940d 1102 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Kojto 148:fd96258d940d 1103
Kojto 148:fd96258d940d 1104 /* TPI ITATBCTR0 Register Definitions */
Kojto 148:fd96258d940d 1105 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 148:fd96258d940d 1106 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 148:fd96258d940d 1107
Kojto 148:fd96258d940d 1108 /* TPI Integration Mode Control Register Definitions */
Kojto 148:fd96258d940d 1109 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
Kojto 148:fd96258d940d 1110 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Kojto 148:fd96258d940d 1111
Kojto 148:fd96258d940d 1112 /* TPI DEVID Register Definitions */
Kojto 148:fd96258d940d 1113 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
Kojto 148:fd96258d940d 1114 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 148:fd96258d940d 1115
Kojto 148:fd96258d940d 1116 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
Kojto 148:fd96258d940d 1117 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 148:fd96258d940d 1118
Kojto 148:fd96258d940d 1119 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
Kojto 148:fd96258d940d 1120 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 148:fd96258d940d 1121
Kojto 148:fd96258d940d 1122 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
Kojto 148:fd96258d940d 1123 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 148:fd96258d940d 1124
Kojto 148:fd96258d940d 1125 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
Kojto 148:fd96258d940d 1126 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 148:fd96258d940d 1127
Kojto 148:fd96258d940d 1128 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
Kojto 148:fd96258d940d 1129 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 148:fd96258d940d 1130
Kojto 148:fd96258d940d 1131 /* TPI DEVTYPE Register Definitions */
Kojto 148:fd96258d940d 1132 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
Kojto 148:fd96258d940d 1133 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 148:fd96258d940d 1134
Kojto 148:fd96258d940d 1135 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
Kojto 148:fd96258d940d 1136 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 148:fd96258d940d 1137
Kojto 148:fd96258d940d 1138 /*@}*/ /* end of group CMSIS_TPI */
Kojto 148:fd96258d940d 1139
Kojto 148:fd96258d940d 1140
Kojto 148:fd96258d940d 1141 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto 148:fd96258d940d 1142 /**
Kojto 148:fd96258d940d 1143 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 1144 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 148:fd96258d940d 1145 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 148:fd96258d940d 1146 @{
Kojto 148:fd96258d940d 1147 */
Kojto 148:fd96258d940d 1148
Kojto 148:fd96258d940d 1149 /**
Kojto 148:fd96258d940d 1150 \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 148:fd96258d940d 1151 */
Kojto 148:fd96258d940d 1152 typedef struct
Kojto 148:fd96258d940d 1153 {
Kojto 148:fd96258d940d 1154 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 148:fd96258d940d 1155 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 148:fd96258d940d 1156 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 148:fd96258d940d 1157 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 148:fd96258d940d 1158 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 148:fd96258d940d 1159 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 148:fd96258d940d 1160 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 148:fd96258d940d 1161 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 148:fd96258d940d 1162 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 148:fd96258d940d 1163 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 148:fd96258d940d 1164 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 148:fd96258d940d 1165 } MPU_Type;
Kojto 148:fd96258d940d 1166
Anna Bridge 160:5571c4ff569f 1167 #define MPU_TYPE_RALIASES 4U
Anna Bridge 160:5571c4ff569f 1168
Kojto 148:fd96258d940d 1169 /* MPU Type Register Definitions */
Kojto 148:fd96258d940d 1170 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Kojto 148:fd96258d940d 1171 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 148:fd96258d940d 1172
Kojto 148:fd96258d940d 1173 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Kojto 148:fd96258d940d 1174 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 148:fd96258d940d 1175
Kojto 148:fd96258d940d 1176 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Kojto 148:fd96258d940d 1177 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 148:fd96258d940d 1178
Kojto 148:fd96258d940d 1179 /* MPU Control Register Definitions */
Kojto 148:fd96258d940d 1180 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 148:fd96258d940d 1181 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 148:fd96258d940d 1182
Kojto 148:fd96258d940d 1183 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Kojto 148:fd96258d940d 1184 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 148:fd96258d940d 1185
Kojto 148:fd96258d940d 1186 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Kojto 148:fd96258d940d 1187 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 148:fd96258d940d 1188
Kojto 148:fd96258d940d 1189 /* MPU Region Number Register Definitions */
Kojto 148:fd96258d940d 1190 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Kojto 148:fd96258d940d 1191 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 148:fd96258d940d 1192
Kojto 148:fd96258d940d 1193 /* MPU Region Base Address Register Definitions */
Kojto 148:fd96258d940d 1194 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
Kojto 148:fd96258d940d 1195 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 148:fd96258d940d 1196
Kojto 148:fd96258d940d 1197 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Kojto 148:fd96258d940d 1198 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 148:fd96258d940d 1199
Kojto 148:fd96258d940d 1200 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Kojto 148:fd96258d940d 1201 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 148:fd96258d940d 1202
Kojto 148:fd96258d940d 1203 /* MPU Region Attribute and Size Register Definitions */
Kojto 148:fd96258d940d 1204 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 148:fd96258d940d 1205 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 148:fd96258d940d 1206
Kojto 148:fd96258d940d 1207 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Kojto 148:fd96258d940d 1208 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 148:fd96258d940d 1209
Kojto 148:fd96258d940d 1210 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Kojto 148:fd96258d940d 1211 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 148:fd96258d940d 1212
Kojto 148:fd96258d940d 1213 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Kojto 148:fd96258d940d 1214 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 148:fd96258d940d 1215
Kojto 148:fd96258d940d 1216 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Kojto 148:fd96258d940d 1217 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 148:fd96258d940d 1218
Kojto 148:fd96258d940d 1219 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Kojto 148:fd96258d940d 1220 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 148:fd96258d940d 1221
Kojto 148:fd96258d940d 1222 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Kojto 148:fd96258d940d 1223 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 148:fd96258d940d 1224
Kojto 148:fd96258d940d 1225 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Kojto 148:fd96258d940d 1226 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 148:fd96258d940d 1227
Kojto 148:fd96258d940d 1228 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Kojto 148:fd96258d940d 1229 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 148:fd96258d940d 1230
Kojto 148:fd96258d940d 1231 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Kojto 148:fd96258d940d 1232 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 148:fd96258d940d 1233
Kojto 148:fd96258d940d 1234 /*@} end of group CMSIS_MPU */
Kojto 148:fd96258d940d 1235 #endif
Kojto 148:fd96258d940d 1236
Kojto 148:fd96258d940d 1237
Kojto 148:fd96258d940d 1238 /**
Kojto 148:fd96258d940d 1239 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 1240 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 148:fd96258d940d 1241 \brief Type definitions for the Core Debug Registers
Kojto 148:fd96258d940d 1242 @{
Kojto 148:fd96258d940d 1243 */
Kojto 148:fd96258d940d 1244
Kojto 148:fd96258d940d 1245 /**
Kojto 148:fd96258d940d 1246 \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 148:fd96258d940d 1247 */
Kojto 148:fd96258d940d 1248 typedef struct
Kojto 148:fd96258d940d 1249 {
Kojto 148:fd96258d940d 1250 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 148:fd96258d940d 1251 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 148:fd96258d940d 1252 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 148:fd96258d940d 1253 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 148:fd96258d940d 1254 } CoreDebug_Type;
Kojto 148:fd96258d940d 1255
Kojto 148:fd96258d940d 1256 /* Debug Halting Control and Status Register Definitions */
Kojto 148:fd96258d940d 1257 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 148:fd96258d940d 1258 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 148:fd96258d940d 1259
Kojto 148:fd96258d940d 1260 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 148:fd96258d940d 1261 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 148:fd96258d940d 1262
Kojto 148:fd96258d940d 1263 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 148:fd96258d940d 1264 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 148:fd96258d940d 1265
Kojto 148:fd96258d940d 1266 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 148:fd96258d940d 1267 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 148:fd96258d940d 1268
Kojto 148:fd96258d940d 1269 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 148:fd96258d940d 1270 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 148:fd96258d940d 1271
Kojto 148:fd96258d940d 1272 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 148:fd96258d940d 1273 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 148:fd96258d940d 1274
Kojto 148:fd96258d940d 1275 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 148:fd96258d940d 1276 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 148:fd96258d940d 1277
Kojto 148:fd96258d940d 1278 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 148:fd96258d940d 1279 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 148:fd96258d940d 1280
Kojto 148:fd96258d940d 1281 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 148:fd96258d940d 1282 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 148:fd96258d940d 1283
Kojto 148:fd96258d940d 1284 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 148:fd96258d940d 1285 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 148:fd96258d940d 1286
Kojto 148:fd96258d940d 1287 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 148:fd96258d940d 1288 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 148:fd96258d940d 1289
Kojto 148:fd96258d940d 1290 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 148:fd96258d940d 1291 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 148:fd96258d940d 1292
Kojto 148:fd96258d940d 1293 /* Debug Core Register Selector Register Definitions */
Kojto 148:fd96258d940d 1294 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 148:fd96258d940d 1295 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 148:fd96258d940d 1296
Kojto 148:fd96258d940d 1297 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 148:fd96258d940d 1298 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 148:fd96258d940d 1299
Kojto 148:fd96258d940d 1300 /* Debug Exception and Monitor Control Register Definitions */
Kojto 148:fd96258d940d 1301 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 148:fd96258d940d 1302 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 148:fd96258d940d 1303
Kojto 148:fd96258d940d 1304 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 148:fd96258d940d 1305 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 148:fd96258d940d 1306
Kojto 148:fd96258d940d 1307 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 148:fd96258d940d 1308 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 148:fd96258d940d 1309
Kojto 148:fd96258d940d 1310 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 148:fd96258d940d 1311 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 148:fd96258d940d 1312
Kojto 148:fd96258d940d 1313 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 148:fd96258d940d 1314 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 148:fd96258d940d 1315
Kojto 148:fd96258d940d 1316 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 148:fd96258d940d 1317 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 148:fd96258d940d 1318
Kojto 148:fd96258d940d 1319 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 148:fd96258d940d 1320 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 148:fd96258d940d 1321
Kojto 148:fd96258d940d 1322 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 148:fd96258d940d 1323 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 148:fd96258d940d 1324
Kojto 148:fd96258d940d 1325 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 148:fd96258d940d 1326 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 148:fd96258d940d 1327
Kojto 148:fd96258d940d 1328 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 148:fd96258d940d 1329 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 148:fd96258d940d 1330
Kojto 148:fd96258d940d 1331 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 148:fd96258d940d 1332 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 148:fd96258d940d 1333
Kojto 148:fd96258d940d 1334 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 148:fd96258d940d 1335 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 148:fd96258d940d 1336
Kojto 148:fd96258d940d 1337 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 148:fd96258d940d 1338 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 148:fd96258d940d 1339
Kojto 148:fd96258d940d 1340 /*@} end of group CMSIS_CoreDebug */
Kojto 148:fd96258d940d 1341
Kojto 148:fd96258d940d 1342
Kojto 148:fd96258d940d 1343 /**
Kojto 148:fd96258d940d 1344 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 1345 \defgroup CMSIS_core_bitfield Core register bit field macros
Kojto 148:fd96258d940d 1346 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Kojto 148:fd96258d940d 1347 @{
Kojto 148:fd96258d940d 1348 */
Kojto 148:fd96258d940d 1349
Kojto 148:fd96258d940d 1350 /**
Kojto 148:fd96258d940d 1351 \brief Mask and shift a bit field value for use in a register bit range.
Kojto 148:fd96258d940d 1352 \param[in] field Name of the register bit field.
Kojto 148:fd96258d940d 1353 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Kojto 148:fd96258d940d 1354 \return Masked and shifted value.
Kojto 148:fd96258d940d 1355 */
Kojto 148:fd96258d940d 1356 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Kojto 148:fd96258d940d 1357
Kojto 148:fd96258d940d 1358 /**
Kojto 148:fd96258d940d 1359 \brief Mask and shift a register value to extract a bit filed value.
Kojto 148:fd96258d940d 1360 \param[in] field Name of the register bit field.
Kojto 148:fd96258d940d 1361 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Kojto 148:fd96258d940d 1362 \return Masked and shifted bit field value.
Kojto 148:fd96258d940d 1363 */
Kojto 148:fd96258d940d 1364 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Kojto 148:fd96258d940d 1365
Kojto 148:fd96258d940d 1366 /*@} end of group CMSIS_core_bitfield */
Kojto 148:fd96258d940d 1367
Kojto 148:fd96258d940d 1368
Kojto 148:fd96258d940d 1369 /**
Kojto 148:fd96258d940d 1370 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 1371 \defgroup CMSIS_core_base Core Definitions
Kojto 148:fd96258d940d 1372 \brief Definitions for base addresses, unions, and structures.
Kojto 148:fd96258d940d 1373 @{
Kojto 148:fd96258d940d 1374 */
Kojto 148:fd96258d940d 1375
Kojto 148:fd96258d940d 1376 /* Memory mapping of Core Hardware */
Kojto 148:fd96258d940d 1377 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 148:fd96258d940d 1378 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 148:fd96258d940d 1379 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 148:fd96258d940d 1380 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 148:fd96258d940d 1381 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 148:fd96258d940d 1382 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 148:fd96258d940d 1383 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 148:fd96258d940d 1384 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 148:fd96258d940d 1385
Kojto 148:fd96258d940d 1386 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 148:fd96258d940d 1387 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 148:fd96258d940d 1388 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 148:fd96258d940d 1389 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 148:fd96258d940d 1390 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 148:fd96258d940d 1391 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 148:fd96258d940d 1392 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 148:fd96258d940d 1393 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 148:fd96258d940d 1394
Kojto 148:fd96258d940d 1395 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto 148:fd96258d940d 1396 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 148:fd96258d940d 1397 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 148:fd96258d940d 1398 #endif
Kojto 148:fd96258d940d 1399
Kojto 148:fd96258d940d 1400 /*@} */
Kojto 148:fd96258d940d 1401
Kojto 148:fd96258d940d 1402
Kojto 148:fd96258d940d 1403
Kojto 148:fd96258d940d 1404 /*******************************************************************************
Kojto 148:fd96258d940d 1405 * Hardware Abstraction Layer
Kojto 148:fd96258d940d 1406 Core Function Interface contains:
Kojto 148:fd96258d940d 1407 - Core NVIC Functions
Kojto 148:fd96258d940d 1408 - Core SysTick Functions
Kojto 148:fd96258d940d 1409 - Core Debug Functions
Kojto 148:fd96258d940d 1410 - Core Register Access Functions
Kojto 148:fd96258d940d 1411 ******************************************************************************/
Kojto 148:fd96258d940d 1412 /**
Kojto 148:fd96258d940d 1413 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 148:fd96258d940d 1414 */
Kojto 148:fd96258d940d 1415
Kojto 148:fd96258d940d 1416
Kojto 148:fd96258d940d 1417
Kojto 148:fd96258d940d 1418 /* ########################## NVIC functions #################################### */
Kojto 148:fd96258d940d 1419 /**
Kojto 148:fd96258d940d 1420 \ingroup CMSIS_Core_FunctionInterface
Kojto 148:fd96258d940d 1421 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 148:fd96258d940d 1422 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 148:fd96258d940d 1423 @{
Kojto 148:fd96258d940d 1424 */
Kojto 148:fd96258d940d 1425
Kojto 148:fd96258d940d 1426 #ifdef CMSIS_NVIC_VIRTUAL
Kojto 148:fd96258d940d 1427 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto 148:fd96258d940d 1428 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Kojto 148:fd96258d940d 1429 #endif
Kojto 148:fd96258d940d 1430 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto 148:fd96258d940d 1431 #else
Kojto 148:fd96258d940d 1432 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Kojto 148:fd96258d940d 1433 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Kojto 148:fd96258d940d 1434 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Kojto 148:fd96258d940d 1435 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Kojto 148:fd96258d940d 1436 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Kojto 148:fd96258d940d 1437 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Kojto 148:fd96258d940d 1438 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Kojto 148:fd96258d940d 1439 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Kojto 148:fd96258d940d 1440 #define NVIC_GetActive __NVIC_GetActive
Kojto 148:fd96258d940d 1441 #define NVIC_SetPriority __NVIC_SetPriority
Kojto 148:fd96258d940d 1442 #define NVIC_GetPriority __NVIC_GetPriority
Kojto 148:fd96258d940d 1443 #define NVIC_SystemReset __NVIC_SystemReset
Kojto 148:fd96258d940d 1444 #endif /* CMSIS_NVIC_VIRTUAL */
Kojto 148:fd96258d940d 1445
Kojto 148:fd96258d940d 1446 #ifdef CMSIS_VECTAB_VIRTUAL
Kojto 148:fd96258d940d 1447 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto 148:fd96258d940d 1448 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Kojto 148:fd96258d940d 1449 #endif
Kojto 148:fd96258d940d 1450 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto 148:fd96258d940d 1451 #else
Kojto 148:fd96258d940d 1452 #define NVIC_SetVector __NVIC_SetVector
Kojto 148:fd96258d940d 1453 #define NVIC_GetVector __NVIC_GetVector
Kojto 148:fd96258d940d 1454 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Kojto 148:fd96258d940d 1455
Kojto 148:fd96258d940d 1456 #define NVIC_USER_IRQ_OFFSET 16
Kojto 148:fd96258d940d 1457
Kojto 148:fd96258d940d 1458
Kojto 148:fd96258d940d 1459
Kojto 148:fd96258d940d 1460 /**
Kojto 148:fd96258d940d 1461 \brief Set Priority Grouping
Kojto 148:fd96258d940d 1462 \details Sets the priority grouping field using the required unlock sequence.
Kojto 148:fd96258d940d 1463 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 148:fd96258d940d 1464 Only values from 0..7 are used.
Kojto 148:fd96258d940d 1465 In case of a conflict between priority grouping and available
Kojto 148:fd96258d940d 1466 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 148:fd96258d940d 1467 \param [in] PriorityGroup Priority grouping field.
Kojto 148:fd96258d940d 1468 */
Kojto 148:fd96258d940d 1469 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 148:fd96258d940d 1470 {
Kojto 148:fd96258d940d 1471 uint32_t reg_value;
Kojto 148:fd96258d940d 1472 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 148:fd96258d940d 1473
Kojto 148:fd96258d940d 1474 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 148:fd96258d940d 1475 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 148:fd96258d940d 1476 reg_value = (reg_value |
Kojto 148:fd96258d940d 1477 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 148:fd96258d940d 1478 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
Kojto 148:fd96258d940d 1479 SCB->AIRCR = reg_value;
Kojto 148:fd96258d940d 1480 }
Kojto 148:fd96258d940d 1481
Kojto 148:fd96258d940d 1482
Kojto 148:fd96258d940d 1483 /**
Kojto 148:fd96258d940d 1484 \brief Get Priority Grouping
Kojto 148:fd96258d940d 1485 \details Reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 148:fd96258d940d 1486 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 148:fd96258d940d 1487 */
Kojto 148:fd96258d940d 1488 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Kojto 148:fd96258d940d 1489 {
Kojto 148:fd96258d940d 1490 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto 148:fd96258d940d 1491 }
Kojto 148:fd96258d940d 1492
Kojto 148:fd96258d940d 1493
Kojto 148:fd96258d940d 1494 /**
Kojto 148:fd96258d940d 1495 \brief Enable Interrupt
Kojto 148:fd96258d940d 1496 \details Enables a device specific interrupt in the NVIC interrupt controller.
Kojto 148:fd96258d940d 1497 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 1498 \note IRQn must not be negative.
Kojto 148:fd96258d940d 1499 */
Kojto 148:fd96258d940d 1500 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1501 {
Kojto 148:fd96258d940d 1502 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1503 {
Kojto 148:fd96258d940d 1504 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 148:fd96258d940d 1505 }
Kojto 148:fd96258d940d 1506 }
Kojto 148:fd96258d940d 1507
Kojto 148:fd96258d940d 1508
Kojto 148:fd96258d940d 1509 /**
Kojto 148:fd96258d940d 1510 \brief Get Interrupt Enable status
Kojto 148:fd96258d940d 1511 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Kojto 148:fd96258d940d 1512 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 1513 \return 0 Interrupt is not enabled.
Kojto 148:fd96258d940d 1514 \return 1 Interrupt is enabled.
Kojto 148:fd96258d940d 1515 \note IRQn must not be negative.
Kojto 148:fd96258d940d 1516 */
Kojto 148:fd96258d940d 1517 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1518 {
Kojto 148:fd96258d940d 1519 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1520 {
Kojto 148:fd96258d940d 1521 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 148:fd96258d940d 1522 }
Kojto 148:fd96258d940d 1523 else
Kojto 148:fd96258d940d 1524 {
Kojto 148:fd96258d940d 1525 return(0U);
Kojto 148:fd96258d940d 1526 }
Kojto 148:fd96258d940d 1527 }
Kojto 148:fd96258d940d 1528
Kojto 148:fd96258d940d 1529
Kojto 148:fd96258d940d 1530 /**
Kojto 148:fd96258d940d 1531 \brief Disable Interrupt
Kojto 148:fd96258d940d 1532 \details Disables a device specific interrupt in the NVIC interrupt controller.
Kojto 148:fd96258d940d 1533 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 1534 \note IRQn must not be negative.
Kojto 148:fd96258d940d 1535 */
Kojto 148:fd96258d940d 1536 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1537 {
Kojto 148:fd96258d940d 1538 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1539 {
Kojto 148:fd96258d940d 1540 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 148:fd96258d940d 1541 __DSB();
Kojto 148:fd96258d940d 1542 __ISB();
Kojto 148:fd96258d940d 1543 }
Kojto 148:fd96258d940d 1544 }
Kojto 148:fd96258d940d 1545
Kojto 148:fd96258d940d 1546
Kojto 148:fd96258d940d 1547 /**
Kojto 148:fd96258d940d 1548 \brief Get Pending Interrupt
Kojto 148:fd96258d940d 1549 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Kojto 148:fd96258d940d 1550 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 1551 \return 0 Interrupt status is not pending.
Kojto 148:fd96258d940d 1552 \return 1 Interrupt status is pending.
Kojto 148:fd96258d940d 1553 \note IRQn must not be negative.
Kojto 148:fd96258d940d 1554 */
Kojto 148:fd96258d940d 1555 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1556 {
Kojto 148:fd96258d940d 1557 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1558 {
Kojto 148:fd96258d940d 1559 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 148:fd96258d940d 1560 }
Kojto 148:fd96258d940d 1561 else
Kojto 148:fd96258d940d 1562 {
Kojto 148:fd96258d940d 1563 return(0U);
Kojto 148:fd96258d940d 1564 }
Kojto 148:fd96258d940d 1565 }
Kojto 148:fd96258d940d 1566
Kojto 148:fd96258d940d 1567
Kojto 148:fd96258d940d 1568 /**
Kojto 148:fd96258d940d 1569 \brief Set Pending Interrupt
Kojto 148:fd96258d940d 1570 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Kojto 148:fd96258d940d 1571 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 1572 \note IRQn must not be negative.
Kojto 148:fd96258d940d 1573 */
Kojto 148:fd96258d940d 1574 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1575 {
Kojto 148:fd96258d940d 1576 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1577 {
Kojto 148:fd96258d940d 1578 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 148:fd96258d940d 1579 }
Kojto 148:fd96258d940d 1580 }
Kojto 148:fd96258d940d 1581
Kojto 148:fd96258d940d 1582
Kojto 148:fd96258d940d 1583 /**
Kojto 148:fd96258d940d 1584 \brief Clear Pending Interrupt
Kojto 148:fd96258d940d 1585 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Kojto 148:fd96258d940d 1586 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 1587 \note IRQn must not be negative.
Kojto 148:fd96258d940d 1588 */
Kojto 148:fd96258d940d 1589 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1590 {
Kojto 148:fd96258d940d 1591 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1592 {
Kojto 148:fd96258d940d 1593 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 148:fd96258d940d 1594 }
Kojto 148:fd96258d940d 1595 }
Kojto 148:fd96258d940d 1596
Kojto 148:fd96258d940d 1597
Kojto 148:fd96258d940d 1598 /**
Kojto 148:fd96258d940d 1599 \brief Get Active Interrupt
Kojto 148:fd96258d940d 1600 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Kojto 148:fd96258d940d 1601 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 1602 \return 0 Interrupt status is not active.
Kojto 148:fd96258d940d 1603 \return 1 Interrupt status is active.
Kojto 148:fd96258d940d 1604 \note IRQn must not be negative.
Kojto 148:fd96258d940d 1605 */
Kojto 148:fd96258d940d 1606 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1607 {
Kojto 148:fd96258d940d 1608 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1609 {
Kojto 148:fd96258d940d 1610 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 148:fd96258d940d 1611 }
Kojto 148:fd96258d940d 1612 else
Kojto 148:fd96258d940d 1613 {
Kojto 148:fd96258d940d 1614 return(0U);
Kojto 148:fd96258d940d 1615 }
Kojto 148:fd96258d940d 1616 }
Kojto 148:fd96258d940d 1617
Kojto 148:fd96258d940d 1618
Kojto 148:fd96258d940d 1619 /**
Kojto 148:fd96258d940d 1620 \brief Set Interrupt Priority
Kojto 148:fd96258d940d 1621 \details Sets the priority of a device specific interrupt or a processor exception.
Kojto 148:fd96258d940d 1622 The interrupt number can be positive to specify a device specific interrupt,
Kojto 148:fd96258d940d 1623 or negative to specify a processor exception.
Kojto 148:fd96258d940d 1624 \param [in] IRQn Interrupt number.
Kojto 148:fd96258d940d 1625 \param [in] priority Priority to set.
Kojto 148:fd96258d940d 1626 \note The priority cannot be set for every processor exception.
Kojto 148:fd96258d940d 1627 */
Kojto 148:fd96258d940d 1628 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 148:fd96258d940d 1629 {
Kojto 148:fd96258d940d 1630 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1631 {
Kojto 148:fd96258d940d 1632 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 148:fd96258d940d 1633 }
Kojto 148:fd96258d940d 1634 else
Kojto 148:fd96258d940d 1635 {
Kojto 148:fd96258d940d 1636 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 148:fd96258d940d 1637 }
Kojto 148:fd96258d940d 1638 }
Kojto 148:fd96258d940d 1639
Kojto 148:fd96258d940d 1640
Kojto 148:fd96258d940d 1641 /**
Kojto 148:fd96258d940d 1642 \brief Get Interrupt Priority
Kojto 148:fd96258d940d 1643 \details Reads the priority of a device specific interrupt or a processor exception.
Kojto 148:fd96258d940d 1644 The interrupt number can be positive to specify a device specific interrupt,
Kojto 148:fd96258d940d 1645 or negative to specify a processor exception.
Kojto 148:fd96258d940d 1646 \param [in] IRQn Interrupt number.
Kojto 148:fd96258d940d 1647 \return Interrupt Priority.
Kojto 148:fd96258d940d 1648 Value is aligned automatically to the implemented priority bits of the microcontroller.
Kojto 148:fd96258d940d 1649 */
Kojto 148:fd96258d940d 1650 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1651 {
Kojto 148:fd96258d940d 1652
Kojto 148:fd96258d940d 1653 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 1654 {
Kojto 148:fd96258d940d 1655 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Kojto 148:fd96258d940d 1656 }
Kojto 148:fd96258d940d 1657 else
Kojto 148:fd96258d940d 1658 {
Kojto 148:fd96258d940d 1659 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Kojto 148:fd96258d940d 1660 }
Kojto 148:fd96258d940d 1661 }
Kojto 148:fd96258d940d 1662
Kojto 148:fd96258d940d 1663
Kojto 148:fd96258d940d 1664 /**
Kojto 148:fd96258d940d 1665 \brief Encode Priority
Kojto 148:fd96258d940d 1666 \details Encodes the priority for an interrupt with the given priority group,
Kojto 148:fd96258d940d 1667 preemptive priority value, and subpriority value.
Kojto 148:fd96258d940d 1668 In case of a conflict between priority grouping and available
Kojto 148:fd96258d940d 1669 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 148:fd96258d940d 1670 \param [in] PriorityGroup Used priority group.
Kojto 148:fd96258d940d 1671 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 148:fd96258d940d 1672 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 148:fd96258d940d 1673 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 148:fd96258d940d 1674 */
Kojto 148:fd96258d940d 1675 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 148:fd96258d940d 1676 {
Kojto 148:fd96258d940d 1677 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 148:fd96258d940d 1678 uint32_t PreemptPriorityBits;
Kojto 148:fd96258d940d 1679 uint32_t SubPriorityBits;
Kojto 148:fd96258d940d 1680
Kojto 148:fd96258d940d 1681 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 148:fd96258d940d 1682 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 148:fd96258d940d 1683
Kojto 148:fd96258d940d 1684 return (
Kojto 148:fd96258d940d 1685 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 148:fd96258d940d 1686 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto 148:fd96258d940d 1687 );
Kojto 148:fd96258d940d 1688 }
Kojto 148:fd96258d940d 1689
Kojto 148:fd96258d940d 1690
Kojto 148:fd96258d940d 1691 /**
Kojto 148:fd96258d940d 1692 \brief Decode Priority
Kojto 148:fd96258d940d 1693 \details Decodes an interrupt priority value with a given priority group to
Kojto 148:fd96258d940d 1694 preemptive priority value and subpriority value.
Kojto 148:fd96258d940d 1695 In case of a conflict between priority grouping and available
Kojto 148:fd96258d940d 1696 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto 148:fd96258d940d 1697 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 148:fd96258d940d 1698 \param [in] PriorityGroup Used priority group.
Kojto 148:fd96258d940d 1699 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 148:fd96258d940d 1700 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 148:fd96258d940d 1701 */
Kojto 148:fd96258d940d 1702 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
Kojto 148:fd96258d940d 1703 {
Kojto 148:fd96258d940d 1704 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 148:fd96258d940d 1705 uint32_t PreemptPriorityBits;
Kojto 148:fd96258d940d 1706 uint32_t SubPriorityBits;
Kojto 148:fd96258d940d 1707
Kojto 148:fd96258d940d 1708 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 148:fd96258d940d 1709 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 148:fd96258d940d 1710
Kojto 148:fd96258d940d 1711 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 148:fd96258d940d 1712 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto 148:fd96258d940d 1713 }
Kojto 148:fd96258d940d 1714
Kojto 148:fd96258d940d 1715
Kojto 148:fd96258d940d 1716 /**
Kojto 148:fd96258d940d 1717 \brief Set Interrupt Vector
Kojto 148:fd96258d940d 1718 \details Sets an interrupt vector in SRAM based interrupt vector table.
Kojto 148:fd96258d940d 1719 The interrupt number can be positive to specify a device specific interrupt,
Kojto 148:fd96258d940d 1720 or negative to specify a processor exception.
Kojto 148:fd96258d940d 1721 VTOR must been relocated to SRAM before.
Kojto 148:fd96258d940d 1722 \param [in] IRQn Interrupt number
Kojto 148:fd96258d940d 1723 \param [in] vector Address of interrupt handler function
Kojto 148:fd96258d940d 1724 */
Kojto 148:fd96258d940d 1725 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Kojto 148:fd96258d940d 1726 {
Kojto 148:fd96258d940d 1727 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Kojto 148:fd96258d940d 1728 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Kojto 148:fd96258d940d 1729 }
Kojto 148:fd96258d940d 1730
Kojto 148:fd96258d940d 1731
Kojto 148:fd96258d940d 1732 /**
Kojto 148:fd96258d940d 1733 \brief Get Interrupt Vector
Kojto 148:fd96258d940d 1734 \details Reads an interrupt vector from interrupt vector table.
Kojto 148:fd96258d940d 1735 The interrupt number can be positive to specify a device specific interrupt,
Kojto 148:fd96258d940d 1736 or negative to specify a processor exception.
Kojto 148:fd96258d940d 1737 \param [in] IRQn Interrupt number.
Kojto 148:fd96258d940d 1738 \return Address of interrupt handler function
Kojto 148:fd96258d940d 1739 */
Kojto 148:fd96258d940d 1740 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Kojto 148:fd96258d940d 1741 {
Kojto 148:fd96258d940d 1742 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Kojto 148:fd96258d940d 1743 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Kojto 148:fd96258d940d 1744 }
Kojto 148:fd96258d940d 1745
Kojto 148:fd96258d940d 1746
Kojto 148:fd96258d940d 1747 /**
Kojto 148:fd96258d940d 1748 \brief System Reset
Kojto 148:fd96258d940d 1749 \details Initiates a system reset request to reset the MCU.
Kojto 148:fd96258d940d 1750 */
Kojto 148:fd96258d940d 1751 __STATIC_INLINE void __NVIC_SystemReset(void)
Kojto 148:fd96258d940d 1752 {
Kojto 148:fd96258d940d 1753 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 148:fd96258d940d 1754 buffered write are completed before reset */
Kojto 148:fd96258d940d 1755 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 148:fd96258d940d 1756 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 148:fd96258d940d 1757 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 148:fd96258d940d 1758 __DSB(); /* Ensure completion of memory access */
Kojto 148:fd96258d940d 1759
Kojto 148:fd96258d940d 1760 for(;;) /* wait until reset */
Kojto 148:fd96258d940d 1761 {
Kojto 148:fd96258d940d 1762 __NOP();
Kojto 148:fd96258d940d 1763 }
Kojto 148:fd96258d940d 1764 }
Kojto 148:fd96258d940d 1765
Kojto 148:fd96258d940d 1766 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 148:fd96258d940d 1767
Anna Bridge 160:5571c4ff569f 1768 /* ########################## MPU functions #################################### */
Anna Bridge 160:5571c4ff569f 1769
Anna Bridge 160:5571c4ff569f 1770 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 1771
Anna Bridge 160:5571c4ff569f 1772 #include "mpu_armv7.h"
Anna Bridge 160:5571c4ff569f 1773
Anna Bridge 160:5571c4ff569f 1774 #endif
Kojto 148:fd96258d940d 1775
Kojto 148:fd96258d940d 1776 /* ########################## FPU functions #################################### */
Kojto 148:fd96258d940d 1777 /**
Kojto 148:fd96258d940d 1778 \ingroup CMSIS_Core_FunctionInterface
Kojto 148:fd96258d940d 1779 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Kojto 148:fd96258d940d 1780 \brief Function that provides FPU type.
Kojto 148:fd96258d940d 1781 @{
Kojto 148:fd96258d940d 1782 */
Kojto 148:fd96258d940d 1783
Kojto 148:fd96258d940d 1784 /**
Kojto 148:fd96258d940d 1785 \brief get FPU type
Kojto 148:fd96258d940d 1786 \details returns the FPU type
Kojto 148:fd96258d940d 1787 \returns
Kojto 148:fd96258d940d 1788 - \b 0: No FPU
Kojto 148:fd96258d940d 1789 - \b 1: Single precision FPU
Kojto 148:fd96258d940d 1790 - \b 2: Double + Single precision FPU
Kojto 148:fd96258d940d 1791 */
Kojto 148:fd96258d940d 1792 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Kojto 148:fd96258d940d 1793 {
Kojto 148:fd96258d940d 1794 return 0U; /* No FPU */
Kojto 148:fd96258d940d 1795 }
Kojto 148:fd96258d940d 1796
Kojto 148:fd96258d940d 1797
Kojto 148:fd96258d940d 1798 /*@} end of CMSIS_Core_FpuFunctions */
Kojto 148:fd96258d940d 1799
Kojto 148:fd96258d940d 1800
Kojto 148:fd96258d940d 1801
Kojto 148:fd96258d940d 1802 /* ################################## SysTick function ############################################ */
Kojto 148:fd96258d940d 1803 /**
Kojto 148:fd96258d940d 1804 \ingroup CMSIS_Core_FunctionInterface
Kojto 148:fd96258d940d 1805 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 148:fd96258d940d 1806 \brief Functions that configure the System.
Kojto 148:fd96258d940d 1807 @{
Kojto 148:fd96258d940d 1808 */
Kojto 148:fd96258d940d 1809
Kojto 148:fd96258d940d 1810 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Kojto 148:fd96258d940d 1811
Kojto 148:fd96258d940d 1812 /**
Kojto 148:fd96258d940d 1813 \brief System Tick Configuration
Kojto 148:fd96258d940d 1814 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 148:fd96258d940d 1815 Counter is in free running mode to generate periodic interrupts.
Kojto 148:fd96258d940d 1816 \param [in] ticks Number of ticks between two interrupts.
Kojto 148:fd96258d940d 1817 \return 0 Function succeeded.
Kojto 148:fd96258d940d 1818 \return 1 Function failed.
Kojto 148:fd96258d940d 1819 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 148:fd96258d940d 1820 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 148:fd96258d940d 1821 must contain a vendor-specific implementation of this function.
Kojto 148:fd96258d940d 1822 */
Kojto 148:fd96258d940d 1823 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 148:fd96258d940d 1824 {
Kojto 148:fd96258d940d 1825 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Kojto 148:fd96258d940d 1826 {
Kojto 148:fd96258d940d 1827 return (1UL); /* Reload value impossible */
Kojto 148:fd96258d940d 1828 }
Kojto 148:fd96258d940d 1829
Kojto 148:fd96258d940d 1830 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 148:fd96258d940d 1831 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 148:fd96258d940d 1832 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 148:fd96258d940d 1833 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 148:fd96258d940d 1834 SysTick_CTRL_TICKINT_Msk |
Kojto 148:fd96258d940d 1835 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 148:fd96258d940d 1836 return (0UL); /* Function successful */
Kojto 148:fd96258d940d 1837 }
Kojto 148:fd96258d940d 1838
Kojto 148:fd96258d940d 1839 #endif
Kojto 148:fd96258d940d 1840
Kojto 148:fd96258d940d 1841 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 148:fd96258d940d 1842
Kojto 148:fd96258d940d 1843
Kojto 148:fd96258d940d 1844
Kojto 148:fd96258d940d 1845 /* ##################################### Debug In/Output function ########################################### */
Kojto 148:fd96258d940d 1846 /**
Kojto 148:fd96258d940d 1847 \ingroup CMSIS_Core_FunctionInterface
Kojto 148:fd96258d940d 1848 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 148:fd96258d940d 1849 \brief Functions that access the ITM debug interface.
Kojto 148:fd96258d940d 1850 @{
Kojto 148:fd96258d940d 1851 */
Kojto 148:fd96258d940d 1852
Kojto 148:fd96258d940d 1853 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 148:fd96258d940d 1854 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 148:fd96258d940d 1855
Kojto 148:fd96258d940d 1856
Kojto 148:fd96258d940d 1857 /**
Kojto 148:fd96258d940d 1858 \brief ITM Send Character
Kojto 148:fd96258d940d 1859 \details Transmits a character via the ITM channel 0, and
Kojto 148:fd96258d940d 1860 \li Just returns when no debugger is connected that has booked the output.
Kojto 148:fd96258d940d 1861 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 148:fd96258d940d 1862 \param [in] ch Character to transmit.
Kojto 148:fd96258d940d 1863 \returns Character to transmit.
Kojto 148:fd96258d940d 1864 */
Kojto 148:fd96258d940d 1865 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 148:fd96258d940d 1866 {
Kojto 148:fd96258d940d 1867 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 148:fd96258d940d 1868 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto 148:fd96258d940d 1869 {
Kojto 148:fd96258d940d 1870 while (ITM->PORT[0U].u32 == 0UL)
Kojto 148:fd96258d940d 1871 {
Kojto 148:fd96258d940d 1872 __NOP();
Kojto 148:fd96258d940d 1873 }
Kojto 148:fd96258d940d 1874 ITM->PORT[0U].u8 = (uint8_t)ch;
Kojto 148:fd96258d940d 1875 }
Kojto 148:fd96258d940d 1876 return (ch);
Kojto 148:fd96258d940d 1877 }
Kojto 148:fd96258d940d 1878
Kojto 148:fd96258d940d 1879
Kojto 148:fd96258d940d 1880 /**
Kojto 148:fd96258d940d 1881 \brief ITM Receive Character
Kojto 148:fd96258d940d 1882 \details Inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 148:fd96258d940d 1883 \return Received character.
Kojto 148:fd96258d940d 1884 \return -1 No character pending.
Kojto 148:fd96258d940d 1885 */
Kojto 148:fd96258d940d 1886 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
Kojto 148:fd96258d940d 1887 {
Kojto 148:fd96258d940d 1888 int32_t ch = -1; /* no character available */
Kojto 148:fd96258d940d 1889
Kojto 148:fd96258d940d 1890 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
Kojto 148:fd96258d940d 1891 {
Kojto 148:fd96258d940d 1892 ch = ITM_RxBuffer;
Kojto 148:fd96258d940d 1893 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 148:fd96258d940d 1894 }
Kojto 148:fd96258d940d 1895
Kojto 148:fd96258d940d 1896 return (ch);
Kojto 148:fd96258d940d 1897 }
Kojto 148:fd96258d940d 1898
Kojto 148:fd96258d940d 1899
Kojto 148:fd96258d940d 1900 /**
Kojto 148:fd96258d940d 1901 \brief ITM Check Character
Kojto 148:fd96258d940d 1902 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 148:fd96258d940d 1903 \return 0 No character available.
Kojto 148:fd96258d940d 1904 \return 1 Character available.
Kojto 148:fd96258d940d 1905 */
Kojto 148:fd96258d940d 1906 __STATIC_INLINE int32_t ITM_CheckChar (void)
Kojto 148:fd96258d940d 1907 {
Kojto 148:fd96258d940d 1908
Kojto 148:fd96258d940d 1909 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
Kojto 148:fd96258d940d 1910 {
Kojto 148:fd96258d940d 1911 return (0); /* no character available */
Kojto 148:fd96258d940d 1912 }
Kojto 148:fd96258d940d 1913 else
Kojto 148:fd96258d940d 1914 {
Kojto 148:fd96258d940d 1915 return (1); /* character available */
Kojto 148:fd96258d940d 1916 }
Kojto 148:fd96258d940d 1917 }
Kojto 148:fd96258d940d 1918
Kojto 148:fd96258d940d 1919 /*@} end of CMSIS_core_DebugFunctions */
Kojto 148:fd96258d940d 1920
Kojto 148:fd96258d940d 1921
Kojto 148:fd96258d940d 1922
Kojto 148:fd96258d940d 1923
Kojto 148:fd96258d940d 1924 #ifdef __cplusplus
Kojto 148:fd96258d940d 1925 }
Kojto 148:fd96258d940d 1926 #endif
Kojto 148:fd96258d940d 1927
Kojto 148:fd96258d940d 1928 #endif /* __CORE_CM3_H_DEPENDANT */
Kojto 148:fd96258d940d 1929
Kojto 148:fd96258d940d 1930 #endif /* __CMSIS_GENERIC */