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TARGET_VBLUNO52/core_armv8mml.h@160:5571c4ff569f, 2018-01-17 (annotated)

Committer:: Anna Bridge
Date:: Wed Jan 17 16:13:02 2018 +0000
Revision:: 160:5571c4ff569f
Parent:: 148:fd96258d940d

mbed library. Release version 158

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	148:fd96258d940d	1	/************************************************************************//
Kojto	148:fd96258d940d	2	* @file core_armv8mml.h
Kojto	148:fd96258d940d	3	* @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File
Anna Bridge	160:5571c4ff569f	4	* @version V5.0.3
Anna Bridge	160:5571c4ff569f	5	* @date 09. August 2017
Kojto	148:fd96258d940d	6	******************************************************************************/
Kojto	148:fd96258d940d	7	/*
Kojto	148:fd96258d940d	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
Kojto	148:fd96258d940d	9	*
Kojto	148:fd96258d940d	10	* SPDX-License-Identifier: Apache-2.0
Kojto	148:fd96258d940d	11	*
Kojto	148:fd96258d940d	12	* Licensed under the Apache License, Version 2.0 (the License); you may
Kojto	148:fd96258d940d	13	* not use this file except in compliance with the License.
Kojto	148:fd96258d940d	14	* You may obtain a copy of the License at
Kojto	148:fd96258d940d	15	*
Kojto	148:fd96258d940d	16	* www.apache.org/licenses/LICENSE-2.0
Kojto	148:fd96258d940d	17	*
Kojto	148:fd96258d940d	18	* Unless required by applicable law or agreed to in writing, software
Kojto	148:fd96258d940d	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
Kojto	148:fd96258d940d	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto	148:fd96258d940d	21	* See the License for the specific language governing permissions and
Kojto	148:fd96258d940d	22	* limitations under the License.
Kojto	148:fd96258d940d	23	*/
Kojto	148:fd96258d940d	24
Kojto	148:fd96258d940d	25	#if defined ( __ICCARM__ )
Kojto	148:fd96258d940d	26	#pragma system_include /* treat file as system include file for MISRA check */
Kojto	148:fd96258d940d	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Kojto	148:fd96258d940d	28	#pragma clang system_header /* treat file as system include file */
Kojto	148:fd96258d940d	29	#endif
Kojto	148:fd96258d940d	30
Kojto	148:fd96258d940d	31	#ifndef __CORE_ARMV8MML_H_GENERIC
Kojto	148:fd96258d940d	32	#define __CORE_ARMV8MML_H_GENERIC
Kojto	148:fd96258d940d	33
Kojto	148:fd96258d940d	34	#include <stdint.h>
Kojto	148:fd96258d940d	35
Kojto	148:fd96258d940d	36	#ifdef __cplusplus
Kojto	148:fd96258d940d	37	extern "C" {
Kojto	148:fd96258d940d	38	#endif
Kojto	148:fd96258d940d	39
Kojto	148:fd96258d940d	40	/**
Kojto	148:fd96258d940d	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto	148:fd96258d940d	42	CMSIS violates the following MISRA-C:2004 rules:
Kojto	148:fd96258d940d	43
Kojto	148:fd96258d940d	44	\li Required Rule 8.5, object/function definition in header file.<br>
Kojto	148:fd96258d940d	45	Function definitions in header files are used to allow 'inlining'.
Kojto	148:fd96258d940d	46
Kojto	148:fd96258d940d	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto	148:fd96258d940d	48	Unions are used for effective representation of core registers.
Kojto	148:fd96258d940d	49
Kojto	148:fd96258d940d	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto	148:fd96258d940d	51	Function-like macros are used to allow more efficient code.
Kojto	148:fd96258d940d	52	*/
Kojto	148:fd96258d940d	53
Kojto	148:fd96258d940d	54
Kojto	148:fd96258d940d	55	/*******************************************************************************
Kojto	148:fd96258d940d	56	* CMSIS definitions
Kojto	148:fd96258d940d	57	******************************************************************************/
Kojto	148:fd96258d940d	58	/**
Kojto	148:fd96258d940d	59	\ingroup Cortex_ARMv8MML
Kojto	148:fd96258d940d	60	@{
Kojto	148:fd96258d940d	61	*/
Kojto	148:fd96258d940d	62
Anna Bridge	160:5571c4ff569f	63	#include "cmsis_version.h"
Anna Bridge	160:5571c4ff569f	64
Kojto	148:fd96258d940d	65	/* CMSIS ARMv8MML definitions */
Anna Bridge	160:5571c4ff569f	66	#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	160:5571c4ff569f	67	#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
Kojto	148:fd96258d940d	68	#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	160:5571c4ff569f	69	__ARMv8MML_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
Kojto	148:fd96258d940d	70
Kojto	148:fd96258d940d	71	#define __CORTEX_M (81U) /!< Cortex-M Core /
Kojto	148:fd96258d940d	72
Kojto	148:fd96258d940d	73	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	148:fd96258d940d	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Kojto	148:fd96258d940d	75	*/
Kojto	148:fd96258d940d	76	#if defined ( __CC_ARM )
Kojto	148:fd96258d940d	77	#if defined __TARGET_FPU_VFP
Kojto	148:fd96258d940d	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Kojto	148:fd96258d940d	79	#define __FPU_USED 1U
Kojto	148:fd96258d940d	80	#else
Kojto	148:fd96258d940d	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	82	#define __FPU_USED 0U
Kojto	148:fd96258d940d	83	#endif
Kojto	148:fd96258d940d	84	#else
Kojto	148:fd96258d940d	85	#define __FPU_USED 0U
Kojto	148:fd96258d940d	86	#endif
Kojto	148:fd96258d940d	87
Anna Bridge	160:5571c4ff569f	88	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	160:5571c4ff569f	89	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	90	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	91	#else
Anna Bridge	160:5571c4ff569f	92	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	93	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	94	#endif
Anna Bridge	160:5571c4ff569f	95	#else
Anna Bridge	160:5571c4ff569f	96	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	97	#endif
Anna Bridge	160:5571c4ff569f	98
Kojto	148:fd96258d940d	99	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Kojto	148:fd96258d940d	100	#if defined __ARM_PCS_VFP
Kojto	148:fd96258d940d	101	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Kojto	148:fd96258d940d	102	#define __FPU_USED 1U
Kojto	148:fd96258d940d	103	#else
Kojto	148:fd96258d940d	104	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	105	#define __FPU_USED 0U
Kojto	148:fd96258d940d	106	#endif
Kojto	148:fd96258d940d	107	#else
Kojto	148:fd96258d940d	108	#define __FPU_USED 0U
Kojto	148:fd96258d940d	109	#endif
Kojto	148:fd96258d940d	110
Anna Bridge	160:5571c4ff569f	111	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	160:5571c4ff569f	112	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	113	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	114	#else
Anna Bridge	160:5571c4ff569f	115	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	116	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	117	#endif
Anna Bridge	160:5571c4ff569f	118	#else
Anna Bridge	160:5571c4ff569f	119	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	120	#endif
Anna Bridge	160:5571c4ff569f	121
Kojto	148:fd96258d940d	122	#elif defined ( __GNUC__ )
Kojto	148:fd96258d940d	123	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	148:fd96258d940d	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Kojto	148:fd96258d940d	125	#define __FPU_USED 1U
Kojto	148:fd96258d940d	126	#else
Kojto	148:fd96258d940d	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	128	#define __FPU_USED 0U
Kojto	148:fd96258d940d	129	#endif
Kojto	148:fd96258d940d	130	#else
Kojto	148:fd96258d940d	131	#define __FPU_USED 0U
Kojto	148:fd96258d940d	132	#endif
Anna Bridge	160:5571c4ff569f	133
Anna Bridge	160:5571c4ff569f	134	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	160:5571c4ff569f	135	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	136	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	137	#else
Anna Bridge	160:5571c4ff569f	138	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	139	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	140	#endif
Anna Bridge	160:5571c4ff569f	141	#else
Anna Bridge	160:5571c4ff569f	142	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	143	#endif
Anna Bridge	160:5571c4ff569f	144
Kojto	148:fd96258d940d	145	#elif defined ( __ICCARM__ )
Kojto	148:fd96258d940d	146	#if defined __ARMVFP__
Kojto	148:fd96258d940d	147	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Kojto	148:fd96258d940d	148	#define __FPU_USED 1U
Kojto	148:fd96258d940d	149	#else
Kojto	148:fd96258d940d	150	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	151	#define __FPU_USED 0U
Kojto	148:fd96258d940d	152	#endif
Kojto	148:fd96258d940d	153	#else
Kojto	148:fd96258d940d	154	#define __FPU_USED 0U
Kojto	148:fd96258d940d	155	#endif
Kojto	148:fd96258d940d	156
Anna Bridge	160:5571c4ff569f	157	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	160:5571c4ff569f	158	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	159	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	160	#else
Anna Bridge	160:5571c4ff569f	161	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	162	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	163	#endif
Anna Bridge	160:5571c4ff569f	164	#else
Anna Bridge	160:5571c4ff569f	165	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	166	#endif
Anna Bridge	160:5571c4ff569f	167
Kojto	148:fd96258d940d	168	#elif defined ( __TI_ARM__ )
Kojto	148:fd96258d940d	169	#if defined __TI_VFP_SUPPORT__
Kojto	148:fd96258d940d	170	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Kojto	148:fd96258d940d	171	#define __FPU_USED 1U
Kojto	148:fd96258d940d	172	#else
Kojto	148:fd96258d940d	173	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	174	#define __FPU_USED 0U
Kojto	148:fd96258d940d	175	#endif
Kojto	148:fd96258d940d	176	#else
Kojto	148:fd96258d940d	177	#define __FPU_USED 0U
Kojto	148:fd96258d940d	178	#endif
Kojto	148:fd96258d940d	179
Kojto	148:fd96258d940d	180	#elif defined ( __TASKING__ )
Kojto	148:fd96258d940d	181	#if defined __FPU_VFP__
Kojto	148:fd96258d940d	182	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Kojto	148:fd96258d940d	183	#define __FPU_USED 1U
Kojto	148:fd96258d940d	184	#else
Kojto	148:fd96258d940d	185	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	186	#define __FPU_USED 0U
Kojto	148:fd96258d940d	187	#endif
Kojto	148:fd96258d940d	188	#else
Kojto	148:fd96258d940d	189	#define __FPU_USED 0U
Kojto	148:fd96258d940d	190	#endif
Kojto	148:fd96258d940d	191
Kojto	148:fd96258d940d	192	#elif defined ( __CSMC__ )
Kojto	148:fd96258d940d	193	#if ( __CSMC__ & 0x400U)
Kojto	148:fd96258d940d	194	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Kojto	148:fd96258d940d	195	#define __FPU_USED 1U
Kojto	148:fd96258d940d	196	#else
Kojto	148:fd96258d940d	197	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	198	#define __FPU_USED 0U
Kojto	148:fd96258d940d	199	#endif
Kojto	148:fd96258d940d	200	#else
Kojto	148:fd96258d940d	201	#define __FPU_USED 0U
Kojto	148:fd96258d940d	202	#endif
Kojto	148:fd96258d940d	203
Kojto	148:fd96258d940d	204	#endif
Kojto	148:fd96258d940d	205
Kojto	148:fd96258d940d	206	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Kojto	148:fd96258d940d	207
Kojto	148:fd96258d940d	208
Kojto	148:fd96258d940d	209	#ifdef __cplusplus
Kojto	148:fd96258d940d	210	}
Kojto	148:fd96258d940d	211	#endif
Kojto	148:fd96258d940d	212
Kojto	148:fd96258d940d	213	#endif /* __CORE_ARMV8MML_H_GENERIC */
Kojto	148:fd96258d940d	214
Kojto	148:fd96258d940d	215	#ifndef __CMSIS_GENERIC
Kojto	148:fd96258d940d	216
Kojto	148:fd96258d940d	217	#ifndef __CORE_ARMV8MML_H_DEPENDANT
Kojto	148:fd96258d940d	218	#define __CORE_ARMV8MML_H_DEPENDANT
Kojto	148:fd96258d940d	219
Kojto	148:fd96258d940d	220	#ifdef __cplusplus
Kojto	148:fd96258d940d	221	extern "C" {
Kojto	148:fd96258d940d	222	#endif
Kojto	148:fd96258d940d	223
Kojto	148:fd96258d940d	224	/* check device defines and use defaults */
Kojto	148:fd96258d940d	225	#if defined __CHECK_DEVICE_DEFINES
Kojto	148:fd96258d940d	226	#ifndef __ARMv8MML_REV
Kojto	148:fd96258d940d	227	#define __ARMv8MML_REV 0x0000U
Kojto	148:fd96258d940d	228	#warning "__ARMv8MML_REV not defined in device header file; using default!"
Kojto	148:fd96258d940d	229	#endif
Kojto	148:fd96258d940d	230
Kojto	148:fd96258d940d	231	#ifndef __FPU_PRESENT
Kojto	148:fd96258d940d	232	#define __FPU_PRESENT 0U
Kojto	148:fd96258d940d	233	#warning "__FPU_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	234	#endif
Kojto	148:fd96258d940d	235
Kojto	148:fd96258d940d	236	#ifndef __MPU_PRESENT
Kojto	148:fd96258d940d	237	#define __MPU_PRESENT 0U
Kojto	148:fd96258d940d	238	#warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	239	#endif
Kojto	148:fd96258d940d	240
Kojto	148:fd96258d940d	241	#ifndef __SAUREGION_PRESENT
Kojto	148:fd96258d940d	242	#define __SAUREGION_PRESENT 0U
Kojto	148:fd96258d940d	243	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	244	#endif
Kojto	148:fd96258d940d	245
Kojto	148:fd96258d940d	246	#ifndef __DSP_PRESENT
Kojto	148:fd96258d940d	247	#define __DSP_PRESENT 0U
Kojto	148:fd96258d940d	248	#warning "__DSP_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	249	#endif
Kojto	148:fd96258d940d	250
Kojto	148:fd96258d940d	251	#ifndef __NVIC_PRIO_BITS
Kojto	148:fd96258d940d	252	#define __NVIC_PRIO_BITS 3U
Kojto	148:fd96258d940d	253	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto	148:fd96258d940d	254	#endif
Kojto	148:fd96258d940d	255
Kojto	148:fd96258d940d	256	#ifndef __Vendor_SysTickConfig
Kojto	148:fd96258d940d	257	#define __Vendor_SysTickConfig 0U
Kojto	148:fd96258d940d	258	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto	148:fd96258d940d	259	#endif
Kojto	148:fd96258d940d	260	#endif
Kojto	148:fd96258d940d	261
Kojto	148:fd96258d940d	262	/* IO definitions (access restrictions to peripheral registers) */
Kojto	148:fd96258d940d	263	/**
Kojto	148:fd96258d940d	264	\defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto	148:fd96258d940d	265
Kojto	148:fd96258d940d	266	<strong>IO Type Qualifiers</strong> are used
Kojto	148:fd96258d940d	267	\li to specify the access to peripheral variables.
Kojto	148:fd96258d940d	268	\li for automatic generation of peripheral register debug information.
Kojto	148:fd96258d940d	269	*/
Kojto	148:fd96258d940d	270	#ifdef __cplusplus
Kojto	148:fd96258d940d	271	#define __I volatile /!< Defines 'read only' permissions /
Kojto	148:fd96258d940d	272	#else
Kojto	148:fd96258d940d	273	#define __I volatile const /!< Defines 'read only' permissions /
Kojto	148:fd96258d940d	274	#endif
Kojto	148:fd96258d940d	275	#define __O volatile /!< Defines 'write only' permissions /
Kojto	148:fd96258d940d	276	#define __IO volatile /!< Defines 'read / write' permissions /
Kojto	148:fd96258d940d	277
Kojto	148:fd96258d940d	278	/* following defines should be used for structure members */
Kojto	148:fd96258d940d	279	#define __IM volatile const /! Defines 'read only' structure member permissions /
Kojto	148:fd96258d940d	280	#define __OM volatile /! Defines 'write only' structure member permissions /
Kojto	148:fd96258d940d	281	#define __IOM volatile /! Defines 'read / write' structure member permissions /
Kojto	148:fd96258d940d	282
Kojto	148:fd96258d940d	283	/@} end of group ARMv8MML /
Kojto	148:fd96258d940d	284
Kojto	148:fd96258d940d	285
Kojto	148:fd96258d940d	286
Kojto	148:fd96258d940d	287	/*******************************************************************************
Kojto	148:fd96258d940d	288	* Register Abstraction
Kojto	148:fd96258d940d	289	Core Register contain:
Kojto	148:fd96258d940d	290	- Core Register
Kojto	148:fd96258d940d	291	- Core NVIC Register
Kojto	148:fd96258d940d	292	- Core SCB Register
Kojto	148:fd96258d940d	293	- Core SysTick Register
Kojto	148:fd96258d940d	294	- Core Debug Register
Kojto	148:fd96258d940d	295	- Core MPU Register
Kojto	148:fd96258d940d	296	- Core SAU Register
Kojto	148:fd96258d940d	297	- Core FPU Register
Kojto	148:fd96258d940d	298	******************************************************************************/
Kojto	148:fd96258d940d	299	/**
Kojto	148:fd96258d940d	300	\defgroup CMSIS_core_register Defines and Type Definitions
Kojto	148:fd96258d940d	301	\brief Type definitions and defines for Cortex-M processor based devices.
Kojto	148:fd96258d940d	302	*/
Kojto	148:fd96258d940d	303
Kojto	148:fd96258d940d	304	/**
Kojto	148:fd96258d940d	305	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	306	\defgroup CMSIS_CORE Status and Control Registers
Kojto	148:fd96258d940d	307	\brief Core Register type definitions.
Kojto	148:fd96258d940d	308	@{
Kojto	148:fd96258d940d	309	*/
Kojto	148:fd96258d940d	310
Kojto	148:fd96258d940d	311	/**
Kojto	148:fd96258d940d	312	\brief Union type to access the Application Program Status Register (APSR).
Kojto	148:fd96258d940d	313	*/
Kojto	148:fd96258d940d	314	typedef union
Kojto	148:fd96258d940d	315	{
Kojto	148:fd96258d940d	316	struct
Kojto	148:fd96258d940d	317	{
Kojto	148:fd96258d940d	318	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Kojto	148:fd96258d940d	319	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	148:fd96258d940d	320	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Kojto	148:fd96258d940d	321	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	148:fd96258d940d	322	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	148:fd96258d940d	323	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	148:fd96258d940d	324	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	148:fd96258d940d	325	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	148:fd96258d940d	326	} b; /!< Structure used for bit access /
Kojto	148:fd96258d940d	327	uint32_t w; /!< Type used for word access /
Kojto	148:fd96258d940d	328	} APSR_Type;
Kojto	148:fd96258d940d	329
Kojto	148:fd96258d940d	330	/* APSR Register Definitions */
Kojto	148:fd96258d940d	331	#define APSR_N_Pos 31U /!< APSR: N Position /
Kojto	148:fd96258d940d	332	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	148:fd96258d940d	333
Kojto	148:fd96258d940d	334	#define APSR_Z_Pos 30U /!< APSR: Z Position /
Kojto	148:fd96258d940d	335	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	148:fd96258d940d	336
Kojto	148:fd96258d940d	337	#define APSR_C_Pos 29U /!< APSR: C Position /
Kojto	148:fd96258d940d	338	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	148:fd96258d940d	339
Kojto	148:fd96258d940d	340	#define APSR_V_Pos 28U /!< APSR: V Position /
Kojto	148:fd96258d940d	341	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	148:fd96258d940d	342
Kojto	148:fd96258d940d	343	#define APSR_Q_Pos 27U /!< APSR: Q Position /
Kojto	148:fd96258d940d	344	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Kojto	148:fd96258d940d	345
Kojto	148:fd96258d940d	346	#define APSR_GE_Pos 16U /!< APSR: GE Position /
Kojto	148:fd96258d940d	347	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Kojto	148:fd96258d940d	348
Kojto	148:fd96258d940d	349
Kojto	148:fd96258d940d	350	/**
Kojto	148:fd96258d940d	351	\brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto	148:fd96258d940d	352	*/
Kojto	148:fd96258d940d	353	typedef union
Kojto	148:fd96258d940d	354	{
Kojto	148:fd96258d940d	355	struct
Kojto	148:fd96258d940d	356	{
Kojto	148:fd96258d940d	357	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	148:fd96258d940d	358	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Kojto	148:fd96258d940d	359	} b; /!< Structure used for bit access /
Kojto	148:fd96258d940d	360	uint32_t w; /!< Type used for word access /
Kojto	148:fd96258d940d	361	} IPSR_Type;
Kojto	148:fd96258d940d	362
Kojto	148:fd96258d940d	363	/* IPSR Register Definitions */
Kojto	148:fd96258d940d	364	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
Kojto	148:fd96258d940d	365	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	148:fd96258d940d	366
Kojto	148:fd96258d940d	367
Kojto	148:fd96258d940d	368	/**
Kojto	148:fd96258d940d	369	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto	148:fd96258d940d	370	*/
Kojto	148:fd96258d940d	371	typedef union
Kojto	148:fd96258d940d	372	{
Kojto	148:fd96258d940d	373	struct
Kojto	148:fd96258d940d	374	{
Kojto	148:fd96258d940d	375	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	148:fd96258d940d	376	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Kojto	148:fd96258d940d	377	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	148:fd96258d940d	378	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Kojto	148:fd96258d940d	379	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Kojto	148:fd96258d940d	380	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Kojto	148:fd96258d940d	381	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	148:fd96258d940d	382	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	148:fd96258d940d	383	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	148:fd96258d940d	384	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	148:fd96258d940d	385	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	148:fd96258d940d	386	} b; /!< Structure used for bit access /
Kojto	148:fd96258d940d	387	uint32_t w; /!< Type used for word access /
Kojto	148:fd96258d940d	388	} xPSR_Type;
Kojto	148:fd96258d940d	389
Kojto	148:fd96258d940d	390	/* xPSR Register Definitions */
Kojto	148:fd96258d940d	391	#define xPSR_N_Pos 31U /!< xPSR: N Position /
Kojto	148:fd96258d940d	392	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	148:fd96258d940d	393
Kojto	148:fd96258d940d	394	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
Kojto	148:fd96258d940d	395	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	148:fd96258d940d	396
Kojto	148:fd96258d940d	397	#define xPSR_C_Pos 29U /!< xPSR: C Position /
Kojto	148:fd96258d940d	398	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	148:fd96258d940d	399
Kojto	148:fd96258d940d	400	#define xPSR_V_Pos 28U /!< xPSR: V Position /
Kojto	148:fd96258d940d	401	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	148:fd96258d940d	402
Kojto	148:fd96258d940d	403	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
Kojto	148:fd96258d940d	404	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Kojto	148:fd96258d940d	405
Kojto	148:fd96258d940d	406	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
Kojto	148:fd96258d940d	407	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Kojto	148:fd96258d940d	408
Kojto	148:fd96258d940d	409	#define xPSR_T_Pos 24U /!< xPSR: T Position /
Kojto	148:fd96258d940d	410	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	148:fd96258d940d	411
Kojto	148:fd96258d940d	412	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
Kojto	148:fd96258d940d	413	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Kojto	148:fd96258d940d	414
Kojto	148:fd96258d940d	415	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
Kojto	148:fd96258d940d	416	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	148:fd96258d940d	417
Kojto	148:fd96258d940d	418
Kojto	148:fd96258d940d	419	/**
Kojto	148:fd96258d940d	420	\brief Union type to access the Control Registers (CONTROL).
Kojto	148:fd96258d940d	421	*/
Kojto	148:fd96258d940d	422	typedef union
Kojto	148:fd96258d940d	423	{
Kojto	148:fd96258d940d	424	struct
Kojto	148:fd96258d940d	425	{
Kojto	148:fd96258d940d	426	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Kojto	148:fd96258d940d	427	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
Kojto	148:fd96258d940d	428	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
Kojto	148:fd96258d940d	429	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
Kojto	148:fd96258d940d	430	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
Kojto	148:fd96258d940d	431	} b; /!< Structure used for bit access /
Kojto	148:fd96258d940d	432	uint32_t w; /!< Type used for word access /
Kojto	148:fd96258d940d	433	} CONTROL_Type;
Kojto	148:fd96258d940d	434
Kojto	148:fd96258d940d	435	/* CONTROL Register Definitions */
Kojto	148:fd96258d940d	436	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
Kojto	148:fd96258d940d	437	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
Kojto	148:fd96258d940d	438
Kojto	148:fd96258d940d	439	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
Kojto	148:fd96258d940d	440	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Kojto	148:fd96258d940d	441
Kojto	148:fd96258d940d	442	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
Kojto	148:fd96258d940d	443	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	148:fd96258d940d	444
Kojto	148:fd96258d940d	445	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
Kojto	148:fd96258d940d	446	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	148:fd96258d940d	447
Kojto	148:fd96258d940d	448	/@} end of group CMSIS_CORE /
Kojto	148:fd96258d940d	449
Kojto	148:fd96258d940d	450
Kojto	148:fd96258d940d	451	/**
Kojto	148:fd96258d940d	452	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	453	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto	148:fd96258d940d	454	\brief Type definitions for the NVIC Registers
Kojto	148:fd96258d940d	455	@{
Kojto	148:fd96258d940d	456	*/
Kojto	148:fd96258d940d	457
Kojto	148:fd96258d940d	458	/**
Kojto	148:fd96258d940d	459	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto	148:fd96258d940d	460	*/
Kojto	148:fd96258d940d	461	typedef struct
Kojto	148:fd96258d940d	462	{
Kojto	148:fd96258d940d	463	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Kojto	148:fd96258d940d	464	uint32_t RESERVED0[16U];
Kojto	148:fd96258d940d	465	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Kojto	148:fd96258d940d	466	uint32_t RSERVED1[16U];
Kojto	148:fd96258d940d	467	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Kojto	148:fd96258d940d	468	uint32_t RESERVED2[16U];
Kojto	148:fd96258d940d	469	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Kojto	148:fd96258d940d	470	uint32_t RESERVED3[16U];
Kojto	148:fd96258d940d	471	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Kojto	148:fd96258d940d	472	uint32_t RESERVED4[16U];
Kojto	148:fd96258d940d	473	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
Kojto	148:fd96258d940d	474	uint32_t RESERVED5[16U];
Kojto	148:fd96258d940d	475	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Kojto	148:fd96258d940d	476	uint32_t RESERVED6[580U];
Kojto	148:fd96258d940d	477	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Kojto	148:fd96258d940d	478	} NVIC_Type;
Kojto	148:fd96258d940d	479
Kojto	148:fd96258d940d	480	/* Software Triggered Interrupt Register Definitions */
Kojto	148:fd96258d940d	481	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
Kojto	148:fd96258d940d	482	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Kojto	148:fd96258d940d	483
Kojto	148:fd96258d940d	484	/@} end of group CMSIS_NVIC /
Kojto	148:fd96258d940d	485
Kojto	148:fd96258d940d	486
Kojto	148:fd96258d940d	487	/**
Kojto	148:fd96258d940d	488	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	489	\defgroup CMSIS_SCB System Control Block (SCB)
Kojto	148:fd96258d940d	490	\brief Type definitions for the System Control Block Registers
Kojto	148:fd96258d940d	491	@{
Kojto	148:fd96258d940d	492	*/
Kojto	148:fd96258d940d	493
Kojto	148:fd96258d940d	494	/**
Kojto	148:fd96258d940d	495	\brief Structure type to access the System Control Block (SCB).
Kojto	148:fd96258d940d	496	*/
Kojto	148:fd96258d940d	497	typedef struct
Kojto	148:fd96258d940d	498	{
Kojto	148:fd96258d940d	499	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Kojto	148:fd96258d940d	500	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Kojto	148:fd96258d940d	501	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Kojto	148:fd96258d940d	502	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Kojto	148:fd96258d940d	503	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Kojto	148:fd96258d940d	504	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Kojto	148:fd96258d940d	505	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Kojto	148:fd96258d940d	506	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Kojto	148:fd96258d940d	507	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Kojto	148:fd96258d940d	508	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Kojto	148:fd96258d940d	509	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Kojto	148:fd96258d940d	510	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Kojto	148:fd96258d940d	511	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Kojto	148:fd96258d940d	512	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Kojto	148:fd96258d940d	513	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Kojto	148:fd96258d940d	514	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Kojto	148:fd96258d940d	515	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Kojto	148:fd96258d940d	516	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Kojto	148:fd96258d940d	517	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Kojto	148:fd96258d940d	518	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
Kojto	148:fd96258d940d	519	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
Kojto	148:fd96258d940d	520	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
Kojto	148:fd96258d940d	521	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
Kojto	148:fd96258d940d	522	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Kojto	148:fd96258d940d	523	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
Kojto	148:fd96258d940d	524	uint32_t RESERVED3[92U];
Kojto	148:fd96258d940d	525	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
Kojto	148:fd96258d940d	526	uint32_t RESERVED4[15U];
Kojto	148:fd96258d940d	527	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
Kojto	148:fd96258d940d	528	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Anna Bridge	160:5571c4ff569f	529	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
Kojto	148:fd96258d940d	530	uint32_t RESERVED5[1U];
Kojto	148:fd96258d940d	531	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
Kojto	148:fd96258d940d	532	uint32_t RESERVED6[1U];
Kojto	148:fd96258d940d	533	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
Kojto	148:fd96258d940d	534	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
Kojto	148:fd96258d940d	535	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
Kojto	148:fd96258d940d	536	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
Kojto	148:fd96258d940d	537	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
Kojto	148:fd96258d940d	538	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
Kojto	148:fd96258d940d	539	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
Kojto	148:fd96258d940d	540	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
Kojto	148:fd96258d940d	541	uint32_t RESERVED7[6U];
Kojto	148:fd96258d940d	542	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
Kojto	148:fd96258d940d	543	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
Kojto	148:fd96258d940d	544	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
Kojto	148:fd96258d940d	545	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
Kojto	148:fd96258d940d	546	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
Kojto	148:fd96258d940d	547	uint32_t RESERVED8[1U];
Kojto	148:fd96258d940d	548	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
Kojto	148:fd96258d940d	549	} SCB_Type;
Kojto	148:fd96258d940d	550
Kojto	148:fd96258d940d	551	/* SCB CPUID Register Definitions */
Kojto	148:fd96258d940d	552	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
Kojto	148:fd96258d940d	553	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Kojto	148:fd96258d940d	554
Kojto	148:fd96258d940d	555	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
Kojto	148:fd96258d940d	556	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Kojto	148:fd96258d940d	557
Kojto	148:fd96258d940d	558	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
Kojto	148:fd96258d940d	559	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Kojto	148:fd96258d940d	560
Kojto	148:fd96258d940d	561	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
Kojto	148:fd96258d940d	562	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Kojto	148:fd96258d940d	563
Kojto	148:fd96258d940d	564	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
Kojto	148:fd96258d940d	565	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Kojto	148:fd96258d940d	566
Kojto	148:fd96258d940d	567	/* SCB Interrupt Control State Register Definitions */
Kojto	148:fd96258d940d	568	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
Kojto	148:fd96258d940d	569	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
Kojto	148:fd96258d940d	570
Kojto	148:fd96258d940d	571	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
Kojto	148:fd96258d940d	572	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
Kojto	148:fd96258d940d	573
Kojto	148:fd96258d940d	574	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
Kojto	148:fd96258d940d	575	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Kojto	148:fd96258d940d	576
Kojto	148:fd96258d940d	577	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
Kojto	148:fd96258d940d	578	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Kojto	148:fd96258d940d	579
Kojto	148:fd96258d940d	580	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
Kojto	148:fd96258d940d	581	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Kojto	148:fd96258d940d	582
Kojto	148:fd96258d940d	583	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
Kojto	148:fd96258d940d	584	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Kojto	148:fd96258d940d	585
Kojto	148:fd96258d940d	586	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
Kojto	148:fd96258d940d	587	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
Kojto	148:fd96258d940d	588
Kojto	148:fd96258d940d	589	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
Kojto	148:fd96258d940d	590	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Kojto	148:fd96258d940d	591
Kojto	148:fd96258d940d	592	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
Kojto	148:fd96258d940d	593	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Kojto	148:fd96258d940d	594
Kojto	148:fd96258d940d	595	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
Kojto	148:fd96258d940d	596	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Kojto	148:fd96258d940d	597
Kojto	148:fd96258d940d	598	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
Kojto	148:fd96258d940d	599	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Kojto	148:fd96258d940d	600
Kojto	148:fd96258d940d	601	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
Kojto	148:fd96258d940d	602	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Kojto	148:fd96258d940d	603
Kojto	148:fd96258d940d	604	/* SCB Vector Table Offset Register Definitions */
Kojto	148:fd96258d940d	605	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
Kojto	148:fd96258d940d	606	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	148:fd96258d940d	607
Kojto	148:fd96258d940d	608	/* SCB Application Interrupt and Reset Control Register Definitions */
Kojto	148:fd96258d940d	609	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
Kojto	148:fd96258d940d	610	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Kojto	148:fd96258d940d	611
Kojto	148:fd96258d940d	612	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
Kojto	148:fd96258d940d	613	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Kojto	148:fd96258d940d	614
Kojto	148:fd96258d940d	615	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
Kojto	148:fd96258d940d	616	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Kojto	148:fd96258d940d	617
Kojto	148:fd96258d940d	618	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
Kojto	148:fd96258d940d	619	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
Kojto	148:fd96258d940d	620
Kojto	148:fd96258d940d	621	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
Kojto	148:fd96258d940d	622	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
Kojto	148:fd96258d940d	623
Kojto	148:fd96258d940d	624	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
Kojto	148:fd96258d940d	625	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Kojto	148:fd96258d940d	626
Kojto	148:fd96258d940d	627	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
Kojto	148:fd96258d940d	628	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
Kojto	148:fd96258d940d	629
Kojto	148:fd96258d940d	630	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
Kojto	148:fd96258d940d	631	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Kojto	148:fd96258d940d	632
Kojto	148:fd96258d940d	633	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
Kojto	148:fd96258d940d	634	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Kojto	148:fd96258d940d	635
Kojto	148:fd96258d940d	636	/* SCB System Control Register Definitions */
Kojto	148:fd96258d940d	637	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
Kojto	148:fd96258d940d	638	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Kojto	148:fd96258d940d	639
Kojto	148:fd96258d940d	640	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
Kojto	148:fd96258d940d	641	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
Kojto	148:fd96258d940d	642
Kojto	148:fd96258d940d	643	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
Kojto	148:fd96258d940d	644	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Kojto	148:fd96258d940d	645
Kojto	148:fd96258d940d	646	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
Kojto	148:fd96258d940d	647	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Kojto	148:fd96258d940d	648
Kojto	148:fd96258d940d	649	/* SCB Configuration Control Register Definitions */
Kojto	148:fd96258d940d	650	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
Kojto	148:fd96258d940d	651	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
Kojto	148:fd96258d940d	652
Kojto	148:fd96258d940d	653	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
Kojto	148:fd96258d940d	654	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
Kojto	148:fd96258d940d	655
Kojto	148:fd96258d940d	656	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
Kojto	148:fd96258d940d	657	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
Kojto	148:fd96258d940d	658
Kojto	148:fd96258d940d	659	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
Kojto	148:fd96258d940d	660	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
Kojto	148:fd96258d940d	661
Kojto	148:fd96258d940d	662	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
Kojto	148:fd96258d940d	663	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Kojto	148:fd96258d940d	664
Kojto	148:fd96258d940d	665	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
Kojto	148:fd96258d940d	666	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Kojto	148:fd96258d940d	667
Kojto	148:fd96258d940d	668	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
Kojto	148:fd96258d940d	669	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Kojto	148:fd96258d940d	670
Kojto	148:fd96258d940d	671	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
Kojto	148:fd96258d940d	672	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Kojto	148:fd96258d940d	673
Kojto	148:fd96258d940d	674	/* SCB System Handler Control and State Register Definitions */
Kojto	148:fd96258d940d	675	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
Kojto	148:fd96258d940d	676	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
Kojto	148:fd96258d940d	677
Kojto	148:fd96258d940d	678	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
Kojto	148:fd96258d940d	679	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
Kojto	148:fd96258d940d	680
Kojto	148:fd96258d940d	681	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
Kojto	148:fd96258d940d	682	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
Kojto	148:fd96258d940d	683
Kojto	148:fd96258d940d	684	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
Kojto	148:fd96258d940d	685	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Kojto	148:fd96258d940d	686
Kojto	148:fd96258d940d	687	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
Kojto	148:fd96258d940d	688	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Kojto	148:fd96258d940d	689
Kojto	148:fd96258d940d	690	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
Kojto	148:fd96258d940d	691	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Kojto	148:fd96258d940d	692
Kojto	148:fd96258d940d	693	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
Kojto	148:fd96258d940d	694	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Kojto	148:fd96258d940d	695
Kojto	148:fd96258d940d	696	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
Kojto	148:fd96258d940d	697	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Kojto	148:fd96258d940d	698
Kojto	148:fd96258d940d	699	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
Kojto	148:fd96258d940d	700	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Kojto	148:fd96258d940d	701
Kojto	148:fd96258d940d	702	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
Kojto	148:fd96258d940d	703	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Kojto	148:fd96258d940d	704
Kojto	148:fd96258d940d	705	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
Kojto	148:fd96258d940d	706	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Kojto	148:fd96258d940d	707
Kojto	148:fd96258d940d	708	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
Kojto	148:fd96258d940d	709	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Kojto	148:fd96258d940d	710
Kojto	148:fd96258d940d	711	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
Kojto	148:fd96258d940d	712	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Kojto	148:fd96258d940d	713
Kojto	148:fd96258d940d	714	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
Kojto	148:fd96258d940d	715	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Kojto	148:fd96258d940d	716
Kojto	148:fd96258d940d	717	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
Kojto	148:fd96258d940d	718	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
Kojto	148:fd96258d940d	719
Kojto	148:fd96258d940d	720	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
Kojto	148:fd96258d940d	721	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
Kojto	148:fd96258d940d	722
Kojto	148:fd96258d940d	723	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
Kojto	148:fd96258d940d	724	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Kojto	148:fd96258d940d	725
Kojto	148:fd96258d940d	726	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
Kojto	148:fd96258d940d	727	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
Kojto	148:fd96258d940d	728
Kojto	148:fd96258d940d	729	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
Kojto	148:fd96258d940d	730	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Kojto	148:fd96258d940d	731
Kojto	148:fd96258d940d	732	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	148:fd96258d940d	733	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Kojto	148:fd96258d940d	734
Kojto	148:fd96258d940d	735	/* SCB Configurable Fault Status Register Definitions */
Kojto	148:fd96258d940d	736	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
Kojto	148:fd96258d940d	737	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Kojto	148:fd96258d940d	738
Kojto	148:fd96258d940d	739	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
Kojto	148:fd96258d940d	740	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Kojto	148:fd96258d940d	741
Kojto	148:fd96258d940d	742	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	148:fd96258d940d	743	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Kojto	148:fd96258d940d	744
Kojto	148:fd96258d940d	745	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
Kojto	148:fd96258d940d	746	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
Kojto	148:fd96258d940d	747	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
Kojto	148:fd96258d940d	748
Kojto	148:fd96258d940d	749	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
Kojto	148:fd96258d940d	750	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
Kojto	148:fd96258d940d	751
Kojto	148:fd96258d940d	752	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
Kojto	148:fd96258d940d	753	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
Kojto	148:fd96258d940d	754
Kojto	148:fd96258d940d	755	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
Kojto	148:fd96258d940d	756	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
Kojto	148:fd96258d940d	757
Kojto	148:fd96258d940d	758	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
Kojto	148:fd96258d940d	759	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
Kojto	148:fd96258d940d	760
Kojto	148:fd96258d940d	761	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
Kojto	148:fd96258d940d	762	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
Kojto	148:fd96258d940d	763
Kojto	148:fd96258d940d	764	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
Kojto	148:fd96258d940d	765	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
Kojto	148:fd96258d940d	766	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
Kojto	148:fd96258d940d	767
Kojto	148:fd96258d940d	768	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
Kojto	148:fd96258d940d	769	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
Kojto	148:fd96258d940d	770
Kojto	148:fd96258d940d	771	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
Kojto	148:fd96258d940d	772	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
Kojto	148:fd96258d940d	773
Kojto	148:fd96258d940d	774	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
Kojto	148:fd96258d940d	775	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
Kojto	148:fd96258d940d	776
Kojto	148:fd96258d940d	777	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
Kojto	148:fd96258d940d	778	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
Kojto	148:fd96258d940d	779
Kojto	148:fd96258d940d	780	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
Kojto	148:fd96258d940d	781	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
Kojto	148:fd96258d940d	782
Kojto	148:fd96258d940d	783	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
Kojto	148:fd96258d940d	784	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
Kojto	148:fd96258d940d	785
Kojto	148:fd96258d940d	786	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
Kojto	148:fd96258d940d	787	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
Kojto	148:fd96258d940d	788	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
Kojto	148:fd96258d940d	789
Kojto	148:fd96258d940d	790	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
Kojto	148:fd96258d940d	791	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
Kojto	148:fd96258d940d	792
Kojto	148:fd96258d940d	793	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
Kojto	148:fd96258d940d	794	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
Kojto	148:fd96258d940d	795
Kojto	148:fd96258d940d	796	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
Kojto	148:fd96258d940d	797	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
Kojto	148:fd96258d940d	798
Kojto	148:fd96258d940d	799	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
Kojto	148:fd96258d940d	800	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
Kojto	148:fd96258d940d	801
Kojto	148:fd96258d940d	802	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
Kojto	148:fd96258d940d	803	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
Kojto	148:fd96258d940d	804
Kojto	148:fd96258d940d	805	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
Kojto	148:fd96258d940d	806	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
Kojto	148:fd96258d940d	807
Kojto	148:fd96258d940d	808	/* SCB Hard Fault Status Register Definitions */
Kojto	148:fd96258d940d	809	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
Kojto	148:fd96258d940d	810	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Kojto	148:fd96258d940d	811
Kojto	148:fd96258d940d	812	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
Kojto	148:fd96258d940d	813	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Kojto	148:fd96258d940d	814
Kojto	148:fd96258d940d	815	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
Kojto	148:fd96258d940d	816	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Kojto	148:fd96258d940d	817
Kojto	148:fd96258d940d	818	/* SCB Debug Fault Status Register Definitions */
Kojto	148:fd96258d940d	819	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
Kojto	148:fd96258d940d	820	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Kojto	148:fd96258d940d	821
Kojto	148:fd96258d940d	822	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
Kojto	148:fd96258d940d	823	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Kojto	148:fd96258d940d	824
Kojto	148:fd96258d940d	825	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
Kojto	148:fd96258d940d	826	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Kojto	148:fd96258d940d	827
Kojto	148:fd96258d940d	828	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
Kojto	148:fd96258d940d	829	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Kojto	148:fd96258d940d	830
Kojto	148:fd96258d940d	831	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
Kojto	148:fd96258d940d	832	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Kojto	148:fd96258d940d	833
Kojto	148:fd96258d940d	834	/* SCB Non-Secure Access Control Register Definitions */
Kojto	148:fd96258d940d	835	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
Kojto	148:fd96258d940d	836	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
Kojto	148:fd96258d940d	837
Kojto	148:fd96258d940d	838	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
Kojto	148:fd96258d940d	839	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
Kojto	148:fd96258d940d	840
Kojto	148:fd96258d940d	841	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
Kojto	148:fd96258d940d	842	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
Kojto	148:fd96258d940d	843
Kojto	148:fd96258d940d	844	/* SCB Cache Level ID Register Definitions */
Kojto	148:fd96258d940d	845	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
Kojto	148:fd96258d940d	846	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
Kojto	148:fd96258d940d	847
Kojto	148:fd96258d940d	848	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
Kojto	148:fd96258d940d	849	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
Kojto	148:fd96258d940d	850
Kojto	148:fd96258d940d	851	/* SCB Cache Type Register Definitions */
Kojto	148:fd96258d940d	852	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
Kojto	148:fd96258d940d	853	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
Kojto	148:fd96258d940d	854
Kojto	148:fd96258d940d	855	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
Kojto	148:fd96258d940d	856	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
Kojto	148:fd96258d940d	857
Kojto	148:fd96258d940d	858	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
Kojto	148:fd96258d940d	859	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
Kojto	148:fd96258d940d	860
Kojto	148:fd96258d940d	861	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
Kojto	148:fd96258d940d	862	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
Kojto	148:fd96258d940d	863
Kojto	148:fd96258d940d	864	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
Kojto	148:fd96258d940d	865	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
Kojto	148:fd96258d940d	866
Kojto	148:fd96258d940d	867	/* SCB Cache Size ID Register Definitions */
Kojto	148:fd96258d940d	868	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
Kojto	148:fd96258d940d	869	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
Kojto	148:fd96258d940d	870
Kojto	148:fd96258d940d	871	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
Kojto	148:fd96258d940d	872	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
Kojto	148:fd96258d940d	873
Kojto	148:fd96258d940d	874	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
Kojto	148:fd96258d940d	875	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
Kojto	148:fd96258d940d	876
Kojto	148:fd96258d940d	877	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
Kojto	148:fd96258d940d	878	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
Kojto	148:fd96258d940d	879
Kojto	148:fd96258d940d	880	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
Kojto	148:fd96258d940d	881	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
Kojto	148:fd96258d940d	882
Kojto	148:fd96258d940d	883	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
Kojto	148:fd96258d940d	884	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
Kojto	148:fd96258d940d	885
Kojto	148:fd96258d940d	886	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
Kojto	148:fd96258d940d	887	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
Kojto	148:fd96258d940d	888
Kojto	148:fd96258d940d	889	/* SCB Cache Size Selection Register Definitions */
Kojto	148:fd96258d940d	890	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
Kojto	148:fd96258d940d	891	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
Kojto	148:fd96258d940d	892
Kojto	148:fd96258d940d	893	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
Kojto	148:fd96258d940d	894	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
Kojto	148:fd96258d940d	895
Kojto	148:fd96258d940d	896	/* SCB Software Triggered Interrupt Register Definitions */
Kojto	148:fd96258d940d	897	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
Kojto	148:fd96258d940d	898	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
Kojto	148:fd96258d940d	899
Kojto	148:fd96258d940d	900	/* SCB D-Cache Invalidate by Set-way Register Definitions */
Kojto	148:fd96258d940d	901	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
Kojto	148:fd96258d940d	902	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
Kojto	148:fd96258d940d	903
Kojto	148:fd96258d940d	904	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
Kojto	148:fd96258d940d	905	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
Kojto	148:fd96258d940d	906
Kojto	148:fd96258d940d	907	/* SCB D-Cache Clean by Set-way Register Definitions */
Kojto	148:fd96258d940d	908	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
Kojto	148:fd96258d940d	909	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
Kojto	148:fd96258d940d	910
Kojto	148:fd96258d940d	911	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
Kojto	148:fd96258d940d	912	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
Kojto	148:fd96258d940d	913
Kojto	148:fd96258d940d	914	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
Kojto	148:fd96258d940d	915	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
Kojto	148:fd96258d940d	916	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
Kojto	148:fd96258d940d	917
Kojto	148:fd96258d940d	918	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
Kojto	148:fd96258d940d	919	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
Kojto	148:fd96258d940d	920
Kojto	148:fd96258d940d	921	/* Instruction Tightly-Coupled Memory Control Register Definitions */
Kojto	148:fd96258d940d	922	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
Kojto	148:fd96258d940d	923	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
Kojto	148:fd96258d940d	924
Kojto	148:fd96258d940d	925	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
Kojto	148:fd96258d940d	926	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
Kojto	148:fd96258d940d	927
Kojto	148:fd96258d940d	928	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
Kojto	148:fd96258d940d	929	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
Kojto	148:fd96258d940d	930
Kojto	148:fd96258d940d	931	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
Kojto	148:fd96258d940d	932	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
Kojto	148:fd96258d940d	933
Kojto	148:fd96258d940d	934	/* Data Tightly-Coupled Memory Control Register Definitions */
Kojto	148:fd96258d940d	935	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
Kojto	148:fd96258d940d	936	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
Kojto	148:fd96258d940d	937
Kojto	148:fd96258d940d	938	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
Kojto	148:fd96258d940d	939	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
Kojto	148:fd96258d940d	940
Kojto	148:fd96258d940d	941	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
Kojto	148:fd96258d940d	942	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
Kojto	148:fd96258d940d	943
Kojto	148:fd96258d940d	944	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
Kojto	148:fd96258d940d	945	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
Kojto	148:fd96258d940d	946
Kojto	148:fd96258d940d	947	/* AHBP Control Register Definitions */
Kojto	148:fd96258d940d	948	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
Kojto	148:fd96258d940d	949	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
Kojto	148:fd96258d940d	950
Kojto	148:fd96258d940d	951	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
Kojto	148:fd96258d940d	952	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
Kojto	148:fd96258d940d	953
Kojto	148:fd96258d940d	954	/* L1 Cache Control Register Definitions */
Kojto	148:fd96258d940d	955	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
Kojto	148:fd96258d940d	956	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
Kojto	148:fd96258d940d	957
Kojto	148:fd96258d940d	958	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
Kojto	148:fd96258d940d	959	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
Kojto	148:fd96258d940d	960
Kojto	148:fd96258d940d	961	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
Kojto	148:fd96258d940d	962	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
Kojto	148:fd96258d940d	963
Kojto	148:fd96258d940d	964	/* AHBS Control Register Definitions */
Kojto	148:fd96258d940d	965	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
Kojto	148:fd96258d940d	966	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
Kojto	148:fd96258d940d	967
Kojto	148:fd96258d940d	968	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
Kojto	148:fd96258d940d	969	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
Kojto	148:fd96258d940d	970
Kojto	148:fd96258d940d	971	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
Kojto	148:fd96258d940d	972	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
Kojto	148:fd96258d940d	973
Kojto	148:fd96258d940d	974	/* Auxiliary Bus Fault Status Register Definitions */
Kojto	148:fd96258d940d	975	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
Kojto	148:fd96258d940d	976	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
Kojto	148:fd96258d940d	977
Kojto	148:fd96258d940d	978	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
Kojto	148:fd96258d940d	979	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
Kojto	148:fd96258d940d	980
Kojto	148:fd96258d940d	981	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
Kojto	148:fd96258d940d	982	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
Kojto	148:fd96258d940d	983
Kojto	148:fd96258d940d	984	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
Kojto	148:fd96258d940d	985	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
Kojto	148:fd96258d940d	986
Kojto	148:fd96258d940d	987	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
Kojto	148:fd96258d940d	988	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
Kojto	148:fd96258d940d	989
Kojto	148:fd96258d940d	990	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
Kojto	148:fd96258d940d	991	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
Kojto	148:fd96258d940d	992
Kojto	148:fd96258d940d	993	/@} end of group CMSIS_SCB /
Kojto	148:fd96258d940d	994
Kojto	148:fd96258d940d	995
Kojto	148:fd96258d940d	996	/**
Kojto	148:fd96258d940d	997	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	998	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto	148:fd96258d940d	999	\brief Type definitions for the System Control and ID Register not in the SCB
Kojto	148:fd96258d940d	1000	@{
Kojto	148:fd96258d940d	1001	*/
Kojto	148:fd96258d940d	1002
Kojto	148:fd96258d940d	1003	/**
Kojto	148:fd96258d940d	1004	\brief Structure type to access the System Control and ID Register not in the SCB.
Kojto	148:fd96258d940d	1005	*/
Kojto	148:fd96258d940d	1006	typedef struct
Kojto	148:fd96258d940d	1007	{
Kojto	148:fd96258d940d	1008	uint32_t RESERVED0[1U];
Kojto	148:fd96258d940d	1009	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Kojto	148:fd96258d940d	1010	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Kojto	148:fd96258d940d	1011	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
Kojto	148:fd96258d940d	1012	} SCnSCB_Type;
Kojto	148:fd96258d940d	1013
Kojto	148:fd96258d940d	1014	/* Interrupt Controller Type Register Definitions */
Kojto	148:fd96258d940d	1015	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
Kojto	148:fd96258d940d	1016	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Kojto	148:fd96258d940d	1017
Kojto	148:fd96258d940d	1018	/@} end of group CMSIS_SCnotSCB /
Kojto	148:fd96258d940d	1019
Kojto	148:fd96258d940d	1020
Kojto	148:fd96258d940d	1021	/**
Kojto	148:fd96258d940d	1022	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1023	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto	148:fd96258d940d	1024	\brief Type definitions for the System Timer Registers.
Kojto	148:fd96258d940d	1025	@{
Kojto	148:fd96258d940d	1026	*/
Kojto	148:fd96258d940d	1027
Kojto	148:fd96258d940d	1028	/**
Kojto	148:fd96258d940d	1029	\brief Structure type to access the System Timer (SysTick).
Kojto	148:fd96258d940d	1030	*/
Kojto	148:fd96258d940d	1031	typedef struct
Kojto	148:fd96258d940d	1032	{
Kojto	148:fd96258d940d	1033	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Kojto	148:fd96258d940d	1034	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Kojto	148:fd96258d940d	1035	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Kojto	148:fd96258d940d	1036	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Kojto	148:fd96258d940d	1037	} SysTick_Type;
Kojto	148:fd96258d940d	1038
Kojto	148:fd96258d940d	1039	/* SysTick Control / Status Register Definitions */
Kojto	148:fd96258d940d	1040	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
Kojto	148:fd96258d940d	1041	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Kojto	148:fd96258d940d	1042
Kojto	148:fd96258d940d	1043	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
Kojto	148:fd96258d940d	1044	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Kojto	148:fd96258d940d	1045
Kojto	148:fd96258d940d	1046	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
Kojto	148:fd96258d940d	1047	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Kojto	148:fd96258d940d	1048
Kojto	148:fd96258d940d	1049	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
Kojto	148:fd96258d940d	1050	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Kojto	148:fd96258d940d	1051
Kojto	148:fd96258d940d	1052	/* SysTick Reload Register Definitions */
Kojto	148:fd96258d940d	1053	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
Kojto	148:fd96258d940d	1054	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Kojto	148:fd96258d940d	1055
Kojto	148:fd96258d940d	1056	/* SysTick Current Register Definitions */
Kojto	148:fd96258d940d	1057	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
Kojto	148:fd96258d940d	1058	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Kojto	148:fd96258d940d	1059
Kojto	148:fd96258d940d	1060	/* SysTick Calibration Register Definitions */
Kojto	148:fd96258d940d	1061	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
Kojto	148:fd96258d940d	1062	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Kojto	148:fd96258d940d	1063
Kojto	148:fd96258d940d	1064	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
Kojto	148:fd96258d940d	1065	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Kojto	148:fd96258d940d	1066
Kojto	148:fd96258d940d	1067	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
Kojto	148:fd96258d940d	1068	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Kojto	148:fd96258d940d	1069
Kojto	148:fd96258d940d	1070	/@} end of group CMSIS_SysTick /
Kojto	148:fd96258d940d	1071
Kojto	148:fd96258d940d	1072
Kojto	148:fd96258d940d	1073	/**
Kojto	148:fd96258d940d	1074	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1075	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto	148:fd96258d940d	1076	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto	148:fd96258d940d	1077	@{
Kojto	148:fd96258d940d	1078	*/
Kojto	148:fd96258d940d	1079
Kojto	148:fd96258d940d	1080	/**
Kojto	148:fd96258d940d	1081	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto	148:fd96258d940d	1082	*/
Kojto	148:fd96258d940d	1083	typedef struct
Kojto	148:fd96258d940d	1084	{
Kojto	148:fd96258d940d	1085	__OM union
Kojto	148:fd96258d940d	1086	{
Kojto	148:fd96258d940d	1087	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Kojto	148:fd96258d940d	1088	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Kojto	148:fd96258d940d	1089	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Kojto	148:fd96258d940d	1090	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Kojto	148:fd96258d940d	1091	uint32_t RESERVED0[864U];
Kojto	148:fd96258d940d	1092	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Kojto	148:fd96258d940d	1093	uint32_t RESERVED1[15U];
Kojto	148:fd96258d940d	1094	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Kojto	148:fd96258d940d	1095	uint32_t RESERVED2[15U];
Kojto	148:fd96258d940d	1096	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Kojto	148:fd96258d940d	1097	uint32_t RESERVED3[29U];
Kojto	148:fd96258d940d	1098	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Kojto	148:fd96258d940d	1099	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Kojto	148:fd96258d940d	1100	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Kojto	148:fd96258d940d	1101	uint32_t RESERVED4[43U];
Kojto	148:fd96258d940d	1102	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Kojto	148:fd96258d940d	1103	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Kojto	148:fd96258d940d	1104	uint32_t RESERVED5[1U];
Kojto	148:fd96258d940d	1105	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
Kojto	148:fd96258d940d	1106	uint32_t RESERVED6[4U];
Kojto	148:fd96258d940d	1107	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Kojto	148:fd96258d940d	1108	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Kojto	148:fd96258d940d	1109	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Kojto	148:fd96258d940d	1110	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Kojto	148:fd96258d940d	1111	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Kojto	148:fd96258d940d	1112	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Kojto	148:fd96258d940d	1113	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Kojto	148:fd96258d940d	1114	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Kojto	148:fd96258d940d	1115	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Kojto	148:fd96258d940d	1116	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Kojto	148:fd96258d940d	1117	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Kojto	148:fd96258d940d	1118	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Kojto	148:fd96258d940d	1119	} ITM_Type;
Kojto	148:fd96258d940d	1120
Kojto	148:fd96258d940d	1121	/* ITM Stimulus Port Register Definitions */
Kojto	148:fd96258d940d	1122	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
Kojto	148:fd96258d940d	1123	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
Kojto	148:fd96258d940d	1124
Kojto	148:fd96258d940d	1125	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
Kojto	148:fd96258d940d	1126	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
Kojto	148:fd96258d940d	1127
Kojto	148:fd96258d940d	1128	/* ITM Trace Privilege Register Definitions */
Kojto	148:fd96258d940d	1129	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Kojto	148:fd96258d940d	1130	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Kojto	148:fd96258d940d	1131
Kojto	148:fd96258d940d	1132	/* ITM Trace Control Register Definitions */
Kojto	148:fd96258d940d	1133	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
Kojto	148:fd96258d940d	1134	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Kojto	148:fd96258d940d	1135
Kojto	148:fd96258d940d	1136	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
Kojto	148:fd96258d940d	1137	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
Kojto	148:fd96258d940d	1138
Kojto	148:fd96258d940d	1139	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
Kojto	148:fd96258d940d	1140	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Kojto	148:fd96258d940d	1141
Kojto	148:fd96258d940d	1142	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
Kojto	148:fd96258d940d	1143	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
Kojto	148:fd96258d940d	1144
Kojto	148:fd96258d940d	1145	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
Kojto	148:fd96258d940d	1146	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
Kojto	148:fd96258d940d	1147
Kojto	148:fd96258d940d	1148	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
Kojto	148:fd96258d940d	1149	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Kojto	148:fd96258d940d	1150
Kojto	148:fd96258d940d	1151	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
Kojto	148:fd96258d940d	1152	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Kojto	148:fd96258d940d	1153
Kojto	148:fd96258d940d	1154	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
Kojto	148:fd96258d940d	1155	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Kojto	148:fd96258d940d	1156
Kojto	148:fd96258d940d	1157	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
Kojto	148:fd96258d940d	1158	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Kojto	148:fd96258d940d	1159
Kojto	148:fd96258d940d	1160	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
Kojto	148:fd96258d940d	1161	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Kojto	148:fd96258d940d	1162
Kojto	148:fd96258d940d	1163	/* ITM Integration Write Register Definitions */
Kojto	148:fd96258d940d	1164	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
Kojto	148:fd96258d940d	1165	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Kojto	148:fd96258d940d	1166
Kojto	148:fd96258d940d	1167	/* ITM Integration Read Register Definitions */
Kojto	148:fd96258d940d	1168	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
Kojto	148:fd96258d940d	1169	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Kojto	148:fd96258d940d	1170
Kojto	148:fd96258d940d	1171	/* ITM Integration Mode Control Register Definitions */
Kojto	148:fd96258d940d	1172	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
Kojto	148:fd96258d940d	1173	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Kojto	148:fd96258d940d	1174
Kojto	148:fd96258d940d	1175	/* ITM Lock Status Register Definitions */
Kojto	148:fd96258d940d	1176	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
Kojto	148:fd96258d940d	1177	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Kojto	148:fd96258d940d	1178
Kojto	148:fd96258d940d	1179	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
Kojto	148:fd96258d940d	1180	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Kojto	148:fd96258d940d	1181
Kojto	148:fd96258d940d	1182	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
Kojto	148:fd96258d940d	1183	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Kojto	148:fd96258d940d	1184
Kojto	148:fd96258d940d	1185	/@}/ /* end of group CMSIS_ITM */
Kojto	148:fd96258d940d	1186
Kojto	148:fd96258d940d	1187
Kojto	148:fd96258d940d	1188	/**
Kojto	148:fd96258d940d	1189	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1190	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto	148:fd96258d940d	1191	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto	148:fd96258d940d	1192	@{
Kojto	148:fd96258d940d	1193	*/
Kojto	148:fd96258d940d	1194
Kojto	148:fd96258d940d	1195	/**
Kojto	148:fd96258d940d	1196	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto	148:fd96258d940d	1197	*/
Kojto	148:fd96258d940d	1198	typedef struct
Kojto	148:fd96258d940d	1199	{
Kojto	148:fd96258d940d	1200	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Kojto	148:fd96258d940d	1201	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Kojto	148:fd96258d940d	1202	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Kojto	148:fd96258d940d	1203	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Kojto	148:fd96258d940d	1204	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Kojto	148:fd96258d940d	1205	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Kojto	148:fd96258d940d	1206	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Kojto	148:fd96258d940d	1207	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Kojto	148:fd96258d940d	1208	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Kojto	148:fd96258d940d	1209	uint32_t RESERVED1[1U];
Kojto	148:fd96258d940d	1210	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Kojto	148:fd96258d940d	1211	uint32_t RESERVED2[1U];
Kojto	148:fd96258d940d	1212	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Kojto	148:fd96258d940d	1213	uint32_t RESERVED3[1U];
Kojto	148:fd96258d940d	1214	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Kojto	148:fd96258d940d	1215	uint32_t RESERVED4[1U];
Kojto	148:fd96258d940d	1216	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Kojto	148:fd96258d940d	1217	uint32_t RESERVED5[1U];
Kojto	148:fd96258d940d	1218	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Kojto	148:fd96258d940d	1219	uint32_t RESERVED6[1U];
Kojto	148:fd96258d940d	1220	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Kojto	148:fd96258d940d	1221	uint32_t RESERVED7[1U];
Kojto	148:fd96258d940d	1222	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Kojto	148:fd96258d940d	1223	uint32_t RESERVED8[1U];
Kojto	148:fd96258d940d	1224	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
Kojto	148:fd96258d940d	1225	uint32_t RESERVED9[1U];
Kojto	148:fd96258d940d	1226	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
Kojto	148:fd96258d940d	1227	uint32_t RESERVED10[1U];
Kojto	148:fd96258d940d	1228	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
Kojto	148:fd96258d940d	1229	uint32_t RESERVED11[1U];
Kojto	148:fd96258d940d	1230	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
Kojto	148:fd96258d940d	1231	uint32_t RESERVED12[1U];
Kojto	148:fd96258d940d	1232	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
Kojto	148:fd96258d940d	1233	uint32_t RESERVED13[1U];
Kojto	148:fd96258d940d	1234	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
Kojto	148:fd96258d940d	1235	uint32_t RESERVED14[1U];
Kojto	148:fd96258d940d	1236	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
Kojto	148:fd96258d940d	1237	uint32_t RESERVED15[1U];
Kojto	148:fd96258d940d	1238	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
Kojto	148:fd96258d940d	1239	uint32_t RESERVED16[1U];
Kojto	148:fd96258d940d	1240	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
Kojto	148:fd96258d940d	1241	uint32_t RESERVED17[1U];
Kojto	148:fd96258d940d	1242	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
Kojto	148:fd96258d940d	1243	uint32_t RESERVED18[1U];
Kojto	148:fd96258d940d	1244	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
Kojto	148:fd96258d940d	1245	uint32_t RESERVED19[1U];
Kojto	148:fd96258d940d	1246	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
Kojto	148:fd96258d940d	1247	uint32_t RESERVED20[1U];
Kojto	148:fd96258d940d	1248	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
Kojto	148:fd96258d940d	1249	uint32_t RESERVED21[1U];
Kojto	148:fd96258d940d	1250	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
Kojto	148:fd96258d940d	1251	uint32_t RESERVED22[1U];
Kojto	148:fd96258d940d	1252	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
Kojto	148:fd96258d940d	1253	uint32_t RESERVED23[1U];
Kojto	148:fd96258d940d	1254	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
Kojto	148:fd96258d940d	1255	uint32_t RESERVED24[1U];
Kojto	148:fd96258d940d	1256	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
Kojto	148:fd96258d940d	1257	uint32_t RESERVED25[1U];
Kojto	148:fd96258d940d	1258	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
Kojto	148:fd96258d940d	1259	uint32_t RESERVED26[1U];
Kojto	148:fd96258d940d	1260	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
Kojto	148:fd96258d940d	1261	uint32_t RESERVED27[1U];
Kojto	148:fd96258d940d	1262	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
Kojto	148:fd96258d940d	1263	uint32_t RESERVED28[1U];
Kojto	148:fd96258d940d	1264	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
Kojto	148:fd96258d940d	1265	uint32_t RESERVED29[1U];
Kojto	148:fd96258d940d	1266	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
Kojto	148:fd96258d940d	1267	uint32_t RESERVED30[1U];
Kojto	148:fd96258d940d	1268	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
Kojto	148:fd96258d940d	1269	uint32_t RESERVED31[1U];
Kojto	148:fd96258d940d	1270	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
Kojto	148:fd96258d940d	1271	uint32_t RESERVED32[934U];
Kojto	148:fd96258d940d	1272	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
Kojto	148:fd96258d940d	1273	uint32_t RESERVED33[1U];
Kojto	148:fd96258d940d	1274	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
Kojto	148:fd96258d940d	1275	} DWT_Type;
Kojto	148:fd96258d940d	1276
Kojto	148:fd96258d940d	1277	/* DWT Control Register Definitions */
Kojto	148:fd96258d940d	1278	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
Kojto	148:fd96258d940d	1279	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Kojto	148:fd96258d940d	1280
Kojto	148:fd96258d940d	1281	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
Kojto	148:fd96258d940d	1282	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Kojto	148:fd96258d940d	1283
Kojto	148:fd96258d940d	1284	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
Kojto	148:fd96258d940d	1285	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Kojto	148:fd96258d940d	1286
Kojto	148:fd96258d940d	1287	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
Kojto	148:fd96258d940d	1288	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Kojto	148:fd96258d940d	1289
Kojto	148:fd96258d940d	1290	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
Kojto	148:fd96258d940d	1291	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Kojto	148:fd96258d940d	1292
Kojto	148:fd96258d940d	1293	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
Kojto	148:fd96258d940d	1294	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
Kojto	148:fd96258d940d	1295
Kojto	148:fd96258d940d	1296	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
Kojto	148:fd96258d940d	1297	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Kojto	148:fd96258d940d	1298
Kojto	148:fd96258d940d	1299	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
Kojto	148:fd96258d940d	1300	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Kojto	148:fd96258d940d	1301
Kojto	148:fd96258d940d	1302	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
Kojto	148:fd96258d940d	1303	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Kojto	148:fd96258d940d	1304
Kojto	148:fd96258d940d	1305	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
Kojto	148:fd96258d940d	1306	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Kojto	148:fd96258d940d	1307
Kojto	148:fd96258d940d	1308	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
Kojto	148:fd96258d940d	1309	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Kojto	148:fd96258d940d	1310
Kojto	148:fd96258d940d	1311	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
Kojto	148:fd96258d940d	1312	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Kojto	148:fd96258d940d	1313
Kojto	148:fd96258d940d	1314	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
Kojto	148:fd96258d940d	1315	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Kojto	148:fd96258d940d	1316
Kojto	148:fd96258d940d	1317	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
Kojto	148:fd96258d940d	1318	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Kojto	148:fd96258d940d	1319
Kojto	148:fd96258d940d	1320	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
Kojto	148:fd96258d940d	1321	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Kojto	148:fd96258d940d	1322
Kojto	148:fd96258d940d	1323	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
Kojto	148:fd96258d940d	1324	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Kojto	148:fd96258d940d	1325
Kojto	148:fd96258d940d	1326	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
Kojto	148:fd96258d940d	1327	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Kojto	148:fd96258d940d	1328
Kojto	148:fd96258d940d	1329	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
Kojto	148:fd96258d940d	1330	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Kojto	148:fd96258d940d	1331
Kojto	148:fd96258d940d	1332	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
Kojto	148:fd96258d940d	1333	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Kojto	148:fd96258d940d	1334
Kojto	148:fd96258d940d	1335	/* DWT CPI Count Register Definitions */
Kojto	148:fd96258d940d	1336	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
Kojto	148:fd96258d940d	1337	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Kojto	148:fd96258d940d	1338
Kojto	148:fd96258d940d	1339	/* DWT Exception Overhead Count Register Definitions */
Kojto	148:fd96258d940d	1340	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
Kojto	148:fd96258d940d	1341	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Kojto	148:fd96258d940d	1342
Kojto	148:fd96258d940d	1343	/* DWT Sleep Count Register Definitions */
Kojto	148:fd96258d940d	1344	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	148:fd96258d940d	1345	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Kojto	148:fd96258d940d	1346
Kojto	148:fd96258d940d	1347	/* DWT LSU Count Register Definitions */
Kojto	148:fd96258d940d	1348	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
Kojto	148:fd96258d940d	1349	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Kojto	148:fd96258d940d	1350
Kojto	148:fd96258d940d	1351	/* DWT Folded-instruction Count Register Definitions */
Kojto	148:fd96258d940d	1352	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	148:fd96258d940d	1353	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Kojto	148:fd96258d940d	1354
Kojto	148:fd96258d940d	1355	/* DWT Comparator Function Register Definitions */
Kojto	148:fd96258d940d	1356	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
Kojto	148:fd96258d940d	1357	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
Kojto	148:fd96258d940d	1358
Kojto	148:fd96258d940d	1359	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
Kojto	148:fd96258d940d	1360	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Kojto	148:fd96258d940d	1361
Kojto	148:fd96258d940d	1362	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
Kojto	148:fd96258d940d	1363	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Kojto	148:fd96258d940d	1364
Kojto	148:fd96258d940d	1365	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
Kojto	148:fd96258d940d	1366	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
Kojto	148:fd96258d940d	1367
Kojto	148:fd96258d940d	1368	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
Kojto	148:fd96258d940d	1369	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
Kojto	148:fd96258d940d	1370
Kojto	148:fd96258d940d	1371	/@}/ /* end of group CMSIS_DWT */
Kojto	148:fd96258d940d	1372
Kojto	148:fd96258d940d	1373
Kojto	148:fd96258d940d	1374	/**
Kojto	148:fd96258d940d	1375	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1376	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto	148:fd96258d940d	1377	\brief Type definitions for the Trace Port Interface (TPI)
Kojto	148:fd96258d940d	1378	@{
Kojto	148:fd96258d940d	1379	*/
Kojto	148:fd96258d940d	1380
Kojto	148:fd96258d940d	1381	/**
Kojto	148:fd96258d940d	1382	\brief Structure type to access the Trace Port Interface Register (TPI).
Kojto	148:fd96258d940d	1383	*/
Kojto	148:fd96258d940d	1384	typedef struct
Kojto	148:fd96258d940d	1385	{
Kojto	148:fd96258d940d	1386	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Kojto	148:fd96258d940d	1387	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Kojto	148:fd96258d940d	1388	uint32_t RESERVED0[2U];
Kojto	148:fd96258d940d	1389	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Kojto	148:fd96258d940d	1390	uint32_t RESERVED1[55U];
Kojto	148:fd96258d940d	1391	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Kojto	148:fd96258d940d	1392	uint32_t RESERVED2[131U];
Kojto	148:fd96258d940d	1393	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Kojto	148:fd96258d940d	1394	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Kojto	148:fd96258d940d	1395	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Kojto	148:fd96258d940d	1396	uint32_t RESERVED3[759U];
Kojto	148:fd96258d940d	1397	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Kojto	148:fd96258d940d	1398	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Kojto	148:fd96258d940d	1399	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Kojto	148:fd96258d940d	1400	uint32_t RESERVED4[1U];
Kojto	148:fd96258d940d	1401	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Kojto	148:fd96258d940d	1402	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Kojto	148:fd96258d940d	1403	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Kojto	148:fd96258d940d	1404	uint32_t RESERVED5[39U];
Kojto	148:fd96258d940d	1405	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Kojto	148:fd96258d940d	1406	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Kojto	148:fd96258d940d	1407	uint32_t RESERVED7[8U];
Kojto	148:fd96258d940d	1408	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Kojto	148:fd96258d940d	1409	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Kojto	148:fd96258d940d	1410	} TPI_Type;
Kojto	148:fd96258d940d	1411
Kojto	148:fd96258d940d	1412	/* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto	148:fd96258d940d	1413	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
Kojto	148:fd96258d940d	1414	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Kojto	148:fd96258d940d	1415
Kojto	148:fd96258d940d	1416	/* TPI Selected Pin Protocol Register Definitions */
Kojto	148:fd96258d940d	1417	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
Kojto	148:fd96258d940d	1418	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Kojto	148:fd96258d940d	1419
Kojto	148:fd96258d940d	1420	/* TPI Formatter and Flush Status Register Definitions */
Kojto	148:fd96258d940d	1421	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
Kojto	148:fd96258d940d	1422	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Kojto	148:fd96258d940d	1423
Kojto	148:fd96258d940d	1424	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
Kojto	148:fd96258d940d	1425	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Kojto	148:fd96258d940d	1426
Kojto	148:fd96258d940d	1427	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
Kojto	148:fd96258d940d	1428	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Kojto	148:fd96258d940d	1429
Kojto	148:fd96258d940d	1430	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
Kojto	148:fd96258d940d	1431	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Kojto	148:fd96258d940d	1432
Kojto	148:fd96258d940d	1433	/* TPI Formatter and Flush Control Register Definitions */
Kojto	148:fd96258d940d	1434	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
Kojto	148:fd96258d940d	1435	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Kojto	148:fd96258d940d	1436
Kojto	148:fd96258d940d	1437	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
Kojto	148:fd96258d940d	1438	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Kojto	148:fd96258d940d	1439
Kojto	148:fd96258d940d	1440	/* TPI TRIGGER Register Definitions */
Kojto	148:fd96258d940d	1441	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
Kojto	148:fd96258d940d	1442	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Kojto	148:fd96258d940d	1443
Kojto	148:fd96258d940d	1444	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto	148:fd96258d940d	1445	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
Kojto	148:fd96258d940d	1446	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Kojto	148:fd96258d940d	1447
Kojto	148:fd96258d940d	1448	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
Kojto	148:fd96258d940d	1449	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Kojto	148:fd96258d940d	1450
Kojto	148:fd96258d940d	1451	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
Kojto	148:fd96258d940d	1452	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Kojto	148:fd96258d940d	1453
Kojto	148:fd96258d940d	1454	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
Kojto	148:fd96258d940d	1455	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Kojto	148:fd96258d940d	1456
Kojto	148:fd96258d940d	1457	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
Kojto	148:fd96258d940d	1458	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Kojto	148:fd96258d940d	1459
Kojto	148:fd96258d940d	1460	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
Kojto	148:fd96258d940d	1461	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Kojto	148:fd96258d940d	1462
Kojto	148:fd96258d940d	1463	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
Kojto	148:fd96258d940d	1464	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Kojto	148:fd96258d940d	1465
Kojto	148:fd96258d940d	1466	/* TPI ITATBCTR2 Register Definitions */
Kojto	148:fd96258d940d	1467	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
Kojto	148:fd96258d940d	1468	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Kojto	148:fd96258d940d	1469
Kojto	148:fd96258d940d	1470	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto	148:fd96258d940d	1471	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
Kojto	148:fd96258d940d	1472	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Kojto	148:fd96258d940d	1473
Kojto	148:fd96258d940d	1474	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
Kojto	148:fd96258d940d	1475	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Kojto	148:fd96258d940d	1476
Kojto	148:fd96258d940d	1477	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
Kojto	148:fd96258d940d	1478	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Kojto	148:fd96258d940d	1479
Kojto	148:fd96258d940d	1480	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
Kojto	148:fd96258d940d	1481	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Kojto	148:fd96258d940d	1482
Kojto	148:fd96258d940d	1483	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
Kojto	148:fd96258d940d	1484	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Kojto	148:fd96258d940d	1485
Kojto	148:fd96258d940d	1486	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
Kojto	148:fd96258d940d	1487	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Kojto	148:fd96258d940d	1488
Kojto	148:fd96258d940d	1489	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
Kojto	148:fd96258d940d	1490	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Kojto	148:fd96258d940d	1491
Kojto	148:fd96258d940d	1492	/* TPI ITATBCTR0 Register Definitions */
Kojto	148:fd96258d940d	1493	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
Kojto	148:fd96258d940d	1494	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Kojto	148:fd96258d940d	1495
Kojto	148:fd96258d940d	1496	/* TPI Integration Mode Control Register Definitions */
Kojto	148:fd96258d940d	1497	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
Kojto	148:fd96258d940d	1498	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Kojto	148:fd96258d940d	1499
Kojto	148:fd96258d940d	1500	/* TPI DEVID Register Definitions */
Kojto	148:fd96258d940d	1501	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
Kojto	148:fd96258d940d	1502	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Kojto	148:fd96258d940d	1503
Kojto	148:fd96258d940d	1504	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
Kojto	148:fd96258d940d	1505	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Kojto	148:fd96258d940d	1506
Kojto	148:fd96258d940d	1507	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
Kojto	148:fd96258d940d	1508	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Kojto	148:fd96258d940d	1509
Kojto	148:fd96258d940d	1510	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
Kojto	148:fd96258d940d	1511	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Kojto	148:fd96258d940d	1512
Kojto	148:fd96258d940d	1513	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
Kojto	148:fd96258d940d	1514	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Kojto	148:fd96258d940d	1515
Kojto	148:fd96258d940d	1516	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
Kojto	148:fd96258d940d	1517	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Kojto	148:fd96258d940d	1518
Kojto	148:fd96258d940d	1519	/* TPI DEVTYPE Register Definitions */
Kojto	148:fd96258d940d	1520	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
Kojto	148:fd96258d940d	1521	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Kojto	148:fd96258d940d	1522
Kojto	148:fd96258d940d	1523	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
Kojto	148:fd96258d940d	1524	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	148:fd96258d940d	1525
Kojto	148:fd96258d940d	1526	/@}/ /* end of group CMSIS_TPI */
Kojto	148:fd96258d940d	1527
Kojto	148:fd96258d940d	1528
Kojto	148:fd96258d940d	1529	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto	148:fd96258d940d	1530	/**
Kojto	148:fd96258d940d	1531	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1532	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto	148:fd96258d940d	1533	\brief Type definitions for the Memory Protection Unit (MPU)
Kojto	148:fd96258d940d	1534	@{
Kojto	148:fd96258d940d	1535	*/
Kojto	148:fd96258d940d	1536
Kojto	148:fd96258d940d	1537	/**
Kojto	148:fd96258d940d	1538	\brief Structure type to access the Memory Protection Unit (MPU).
Kojto	148:fd96258d940d	1539	*/
Kojto	148:fd96258d940d	1540	typedef struct
Kojto	148:fd96258d940d	1541	{
Kojto	148:fd96258d940d	1542	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Kojto	148:fd96258d940d	1543	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Kojto	148:fd96258d940d	1544	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
Kojto	148:fd96258d940d	1545	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Kojto	148:fd96258d940d	1546	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
Kojto	148:fd96258d940d	1547	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
Kojto	148:fd96258d940d	1548	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
Kojto	148:fd96258d940d	1549	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
Kojto	148:fd96258d940d	1550	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
Kojto	148:fd96258d940d	1551	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
Kojto	148:fd96258d940d	1552	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
Kojto	148:fd96258d940d	1553	uint32_t RESERVED0[1];
Anna Bridge	160:5571c4ff569f	1554	union {
Anna Bridge	160:5571c4ff569f	1555	__IOM uint32_t MAIR[2];
Anna Bridge	160:5571c4ff569f	1556	struct {
Kojto	148:fd96258d940d	1557	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
Kojto	148:fd96258d940d	1558	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
Anna Bridge	160:5571c4ff569f	1559	};
Anna Bridge	160:5571c4ff569f	1560	};
Kojto	148:fd96258d940d	1561	} MPU_Type;
Kojto	148:fd96258d940d	1562
Anna Bridge	160:5571c4ff569f	1563	#define MPU_TYPE_RALIASES 4U
Anna Bridge	160:5571c4ff569f	1564
Kojto	148:fd96258d940d	1565	/* MPU Type Register Definitions */
Kojto	148:fd96258d940d	1566	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
Kojto	148:fd96258d940d	1567	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Kojto	148:fd96258d940d	1568
Kojto	148:fd96258d940d	1569	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
Kojto	148:fd96258d940d	1570	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Kojto	148:fd96258d940d	1571
Kojto	148:fd96258d940d	1572	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
Kojto	148:fd96258d940d	1573	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Kojto	148:fd96258d940d	1574
Kojto	148:fd96258d940d	1575	/* MPU Control Register Definitions */
Kojto	148:fd96258d940d	1576	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
Kojto	148:fd96258d940d	1577	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Kojto	148:fd96258d940d	1578
Kojto	148:fd96258d940d	1579	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
Kojto	148:fd96258d940d	1580	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Kojto	148:fd96258d940d	1581
Kojto	148:fd96258d940d	1582	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
Kojto	148:fd96258d940d	1583	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Kojto	148:fd96258d940d	1584
Kojto	148:fd96258d940d	1585	/* MPU Region Number Register Definitions */
Kojto	148:fd96258d940d	1586	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
Kojto	148:fd96258d940d	1587	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Kojto	148:fd96258d940d	1588
Kojto	148:fd96258d940d	1589	/* MPU Region Base Address Register Definitions */
Kojto	148:fd96258d940d	1590	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
Kojto	148:fd96258d940d	1591	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Kojto	148:fd96258d940d	1592
Kojto	148:fd96258d940d	1593	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
Kojto	148:fd96258d940d	1594	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
Kojto	148:fd96258d940d	1595
Kojto	148:fd96258d940d	1596	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
Kojto	148:fd96258d940d	1597	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
Kojto	148:fd96258d940d	1598
Kojto	148:fd96258d940d	1599	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
Kojto	148:fd96258d940d	1600	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
Kojto	148:fd96258d940d	1601
Kojto	148:fd96258d940d	1602	/* MPU Region Limit Address Register Definitions */
Kojto	148:fd96258d940d	1603	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
Kojto	148:fd96258d940d	1604	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
Kojto	148:fd96258d940d	1605
Kojto	148:fd96258d940d	1606	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
Kojto	148:fd96258d940d	1607	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
Kojto	148:fd96258d940d	1608
Kojto	148:fd96258d940d	1609	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
Kojto	148:fd96258d940d	1610	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
Kojto	148:fd96258d940d	1611
Kojto	148:fd96258d940d	1612	/* MPU Memory Attribute Indirection Register 0 Definitions */
Kojto	148:fd96258d940d	1613	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
Kojto	148:fd96258d940d	1614	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
Kojto	148:fd96258d940d	1615
Kojto	148:fd96258d940d	1616	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
Kojto	148:fd96258d940d	1617	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
Kojto	148:fd96258d940d	1618
Kojto	148:fd96258d940d	1619	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
Kojto	148:fd96258d940d	1620	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
Kojto	148:fd96258d940d	1621
Kojto	148:fd96258d940d	1622	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
Kojto	148:fd96258d940d	1623	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
Kojto	148:fd96258d940d	1624
Kojto	148:fd96258d940d	1625	/* MPU Memory Attribute Indirection Register 1 Definitions */
Kojto	148:fd96258d940d	1626	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
Kojto	148:fd96258d940d	1627	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
Kojto	148:fd96258d940d	1628
Kojto	148:fd96258d940d	1629	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
Kojto	148:fd96258d940d	1630	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
Kojto	148:fd96258d940d	1631
Kojto	148:fd96258d940d	1632	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
Kojto	148:fd96258d940d	1633	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
Kojto	148:fd96258d940d	1634
Kojto	148:fd96258d940d	1635	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
Kojto	148:fd96258d940d	1636	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
Kojto	148:fd96258d940d	1637
Kojto	148:fd96258d940d	1638	/@} end of group CMSIS_MPU /
Kojto	148:fd96258d940d	1639	#endif
Kojto	148:fd96258d940d	1640
Kojto	148:fd96258d940d	1641
Kojto	148:fd96258d940d	1642	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	1643	/**
Kojto	148:fd96258d940d	1644	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1645	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
Kojto	148:fd96258d940d	1646	\brief Type definitions for the Security Attribution Unit (SAU)
Kojto	148:fd96258d940d	1647	@{
Kojto	148:fd96258d940d	1648	*/
Kojto	148:fd96258d940d	1649
Kojto	148:fd96258d940d	1650	/**
Kojto	148:fd96258d940d	1651	\brief Structure type to access the Security Attribution Unit (SAU).
Kojto	148:fd96258d940d	1652	*/
Kojto	148:fd96258d940d	1653	typedef struct
Kojto	148:fd96258d940d	1654	{
Kojto	148:fd96258d940d	1655	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
Kojto	148:fd96258d940d	1656	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
Kojto	148:fd96258d940d	1657	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Kojto	148:fd96258d940d	1658	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
Kojto	148:fd96258d940d	1659	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
Kojto	148:fd96258d940d	1660	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
Kojto	148:fd96258d940d	1661	#else
Kojto	148:fd96258d940d	1662	uint32_t RESERVED0[3];
Kojto	148:fd96258d940d	1663	#endif
Kojto	148:fd96258d940d	1664	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
Kojto	148:fd96258d940d	1665	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
Kojto	148:fd96258d940d	1666	} SAU_Type;
Kojto	148:fd96258d940d	1667
Kojto	148:fd96258d940d	1668	/* SAU Control Register Definitions */
Kojto	148:fd96258d940d	1669	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
Kojto	148:fd96258d940d	1670	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
Kojto	148:fd96258d940d	1671
Kojto	148:fd96258d940d	1672	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
Kojto	148:fd96258d940d	1673	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
Kojto	148:fd96258d940d	1674
Kojto	148:fd96258d940d	1675	/* SAU Type Register Definitions */
Kojto	148:fd96258d940d	1676	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
Kojto	148:fd96258d940d	1677	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
Kojto	148:fd96258d940d	1678
Kojto	148:fd96258d940d	1679	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Kojto	148:fd96258d940d	1680	/* SAU Region Number Register Definitions */
Kojto	148:fd96258d940d	1681	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
Kojto	148:fd96258d940d	1682	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
Kojto	148:fd96258d940d	1683
Kojto	148:fd96258d940d	1684	/* SAU Region Base Address Register Definitions */
Kojto	148:fd96258d940d	1685	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
Kojto	148:fd96258d940d	1686	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
Kojto	148:fd96258d940d	1687
Kojto	148:fd96258d940d	1688	/* SAU Region Limit Address Register Definitions */
Kojto	148:fd96258d940d	1689	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
Kojto	148:fd96258d940d	1690	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
Kojto	148:fd96258d940d	1691
Kojto	148:fd96258d940d	1692	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
Kojto	148:fd96258d940d	1693	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
Kojto	148:fd96258d940d	1694
Kojto	148:fd96258d940d	1695	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
Kojto	148:fd96258d940d	1696	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
Kojto	148:fd96258d940d	1697
Kojto	148:fd96258d940d	1698	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
Kojto	148:fd96258d940d	1699
Kojto	148:fd96258d940d	1700	/* Secure Fault Status Register Definitions */
Kojto	148:fd96258d940d	1701	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
Kojto	148:fd96258d940d	1702	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
Kojto	148:fd96258d940d	1703
Kojto	148:fd96258d940d	1704	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
Kojto	148:fd96258d940d	1705	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
Kojto	148:fd96258d940d	1706
Kojto	148:fd96258d940d	1707	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
Kojto	148:fd96258d940d	1708	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
Kojto	148:fd96258d940d	1709
Kojto	148:fd96258d940d	1710	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
Kojto	148:fd96258d940d	1711	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
Kojto	148:fd96258d940d	1712
Kojto	148:fd96258d940d	1713	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
Kojto	148:fd96258d940d	1714	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
Kojto	148:fd96258d940d	1715
Kojto	148:fd96258d940d	1716	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
Kojto	148:fd96258d940d	1717	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
Kojto	148:fd96258d940d	1718
Kojto	148:fd96258d940d	1719	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
Kojto	148:fd96258d940d	1720	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
Kojto	148:fd96258d940d	1721
Kojto	148:fd96258d940d	1722	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
Kojto	148:fd96258d940d	1723	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
Kojto	148:fd96258d940d	1724
Kojto	148:fd96258d940d	1725	/@} end of group CMSIS_SAU /
Kojto	148:fd96258d940d	1726	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	1727
Kojto	148:fd96258d940d	1728
Kojto	148:fd96258d940d	1729	/**
Kojto	148:fd96258d940d	1730	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1731	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Kojto	148:fd96258d940d	1732	\brief Type definitions for the Floating Point Unit (FPU)
Kojto	148:fd96258d940d	1733	@{
Kojto	148:fd96258d940d	1734	*/
Kojto	148:fd96258d940d	1735
Kojto	148:fd96258d940d	1736	/**
Kojto	148:fd96258d940d	1737	\brief Structure type to access the Floating Point Unit (FPU).
Kojto	148:fd96258d940d	1738	*/
Kojto	148:fd96258d940d	1739	typedef struct
Kojto	148:fd96258d940d	1740	{
Kojto	148:fd96258d940d	1741	uint32_t RESERVED0[1U];
Kojto	148:fd96258d940d	1742	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Kojto	148:fd96258d940d	1743	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Kojto	148:fd96258d940d	1744	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Kojto	148:fd96258d940d	1745	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Kojto	148:fd96258d940d	1746	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Kojto	148:fd96258d940d	1747	} FPU_Type;
Kojto	148:fd96258d940d	1748
Kojto	148:fd96258d940d	1749	/* Floating-Point Context Control Register Definitions */
Kojto	148:fd96258d940d	1750	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
Kojto	148:fd96258d940d	1751	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Kojto	148:fd96258d940d	1752
Kojto	148:fd96258d940d	1753	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
Kojto	148:fd96258d940d	1754	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Kojto	148:fd96258d940d	1755
Kojto	148:fd96258d940d	1756	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
Kojto	148:fd96258d940d	1757	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
Kojto	148:fd96258d940d	1758
Kojto	148:fd96258d940d	1759	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
Kojto	148:fd96258d940d	1760	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
Kojto	148:fd96258d940d	1761
Kojto	148:fd96258d940d	1762	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
Kojto	148:fd96258d940d	1763	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
Kojto	148:fd96258d940d	1764
Kojto	148:fd96258d940d	1765	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
Kojto	148:fd96258d940d	1766	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
Kojto	148:fd96258d940d	1767
Kojto	148:fd96258d940d	1768	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
Kojto	148:fd96258d940d	1769	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
Kojto	148:fd96258d940d	1770
Kojto	148:fd96258d940d	1771	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
Kojto	148:fd96258d940d	1772	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
Kojto	148:fd96258d940d	1773
Kojto	148:fd96258d940d	1774	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
Kojto	148:fd96258d940d	1775	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Kojto	148:fd96258d940d	1776
Kojto	148:fd96258d940d	1777	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
Kojto	148:fd96258d940d	1778	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
Kojto	148:fd96258d940d	1779
Kojto	148:fd96258d940d	1780	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
Kojto	148:fd96258d940d	1781	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Kojto	148:fd96258d940d	1782
Kojto	148:fd96258d940d	1783	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
Kojto	148:fd96258d940d	1784	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Kojto	148:fd96258d940d	1785
Kojto	148:fd96258d940d	1786	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
Kojto	148:fd96258d940d	1787	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Kojto	148:fd96258d940d	1788
Kojto	148:fd96258d940d	1789	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
Kojto	148:fd96258d940d	1790	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Kojto	148:fd96258d940d	1791
Kojto	148:fd96258d940d	1792	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
Kojto	148:fd96258d940d	1793	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
Kojto	148:fd96258d940d	1794
Kojto	148:fd96258d940d	1795	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
Kojto	148:fd96258d940d	1796	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Kojto	148:fd96258d940d	1797
Kojto	148:fd96258d940d	1798	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
Kojto	148:fd96258d940d	1799	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Kojto	148:fd96258d940d	1800
Kojto	148:fd96258d940d	1801	/* Floating-Point Context Address Register Definitions */
Kojto	148:fd96258d940d	1802	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
Kojto	148:fd96258d940d	1803	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Kojto	148:fd96258d940d	1804
Kojto	148:fd96258d940d	1805	/* Floating-Point Default Status Control Register Definitions */
Kojto	148:fd96258d940d	1806	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
Kojto	148:fd96258d940d	1807	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Kojto	148:fd96258d940d	1808
Kojto	148:fd96258d940d	1809	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
Kojto	148:fd96258d940d	1810	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Kojto	148:fd96258d940d	1811
Kojto	148:fd96258d940d	1812	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
Kojto	148:fd96258d940d	1813	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Kojto	148:fd96258d940d	1814
Kojto	148:fd96258d940d	1815	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
Kojto	148:fd96258d940d	1816	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Kojto	148:fd96258d940d	1817
Kojto	148:fd96258d940d	1818	/* Media and FP Feature Register 0 Definitions */
Kojto	148:fd96258d940d	1819	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
Kojto	148:fd96258d940d	1820	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Kojto	148:fd96258d940d	1821
Kojto	148:fd96258d940d	1822	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
Kojto	148:fd96258d940d	1823	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Kojto	148:fd96258d940d	1824
Kojto	148:fd96258d940d	1825	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
Kojto	148:fd96258d940d	1826	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Kojto	148:fd96258d940d	1827
Kojto	148:fd96258d940d	1828	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
Kojto	148:fd96258d940d	1829	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Kojto	148:fd96258d940d	1830
Kojto	148:fd96258d940d	1831	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
Kojto	148:fd96258d940d	1832	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Kojto	148:fd96258d940d	1833
Kojto	148:fd96258d940d	1834	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
Kojto	148:fd96258d940d	1835	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Kojto	148:fd96258d940d	1836
Kojto	148:fd96258d940d	1837	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
Kojto	148:fd96258d940d	1838	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Kojto	148:fd96258d940d	1839
Kojto	148:fd96258d940d	1840	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
Kojto	148:fd96258d940d	1841	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Kojto	148:fd96258d940d	1842
Kojto	148:fd96258d940d	1843	/* Media and FP Feature Register 1 Definitions */
Kojto	148:fd96258d940d	1844	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
Kojto	148:fd96258d940d	1845	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Kojto	148:fd96258d940d	1846
Kojto	148:fd96258d940d	1847	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
Kojto	148:fd96258d940d	1848	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Kojto	148:fd96258d940d	1849
Kojto	148:fd96258d940d	1850	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
Kojto	148:fd96258d940d	1851	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Kojto	148:fd96258d940d	1852
Kojto	148:fd96258d940d	1853	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
Kojto	148:fd96258d940d	1854	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Kojto	148:fd96258d940d	1855
Kojto	148:fd96258d940d	1856	/@} end of group CMSIS_FPU /
Kojto	148:fd96258d940d	1857
Kojto	148:fd96258d940d	1858
Kojto	148:fd96258d940d	1859	/**
Kojto	148:fd96258d940d	1860	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1861	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto	148:fd96258d940d	1862	\brief Type definitions for the Core Debug Registers
Kojto	148:fd96258d940d	1863	@{
Kojto	148:fd96258d940d	1864	*/
Kojto	148:fd96258d940d	1865
Kojto	148:fd96258d940d	1866	/**
Kojto	148:fd96258d940d	1867	\brief Structure type to access the Core Debug Register (CoreDebug).
Kojto	148:fd96258d940d	1868	*/
Kojto	148:fd96258d940d	1869	typedef struct
Kojto	148:fd96258d940d	1870	{
Kojto	148:fd96258d940d	1871	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Kojto	148:fd96258d940d	1872	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Kojto	148:fd96258d940d	1873	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Kojto	148:fd96258d940d	1874	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Kojto	148:fd96258d940d	1875	uint32_t RESERVED4[1U];
Kojto	148:fd96258d940d	1876	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
Kojto	148:fd96258d940d	1877	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
Kojto	148:fd96258d940d	1878	} CoreDebug_Type;
Kojto	148:fd96258d940d	1879
Kojto	148:fd96258d940d	1880	/* Debug Halting Control and Status Register Definitions */
Kojto	148:fd96258d940d	1881	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
Kojto	148:fd96258d940d	1882	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Kojto	148:fd96258d940d	1883
Kojto	148:fd96258d940d	1884	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
Kojto	148:fd96258d940d	1885	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
Kojto	148:fd96258d940d	1886
Kojto	148:fd96258d940d	1887	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
Kojto	148:fd96258d940d	1888	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Kojto	148:fd96258d940d	1889
Kojto	148:fd96258d940d	1890	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Kojto	148:fd96258d940d	1891	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Kojto	148:fd96258d940d	1892
Kojto	148:fd96258d940d	1893	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
Kojto	148:fd96258d940d	1894	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Kojto	148:fd96258d940d	1895
Kojto	148:fd96258d940d	1896	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
Kojto	148:fd96258d940d	1897	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Kojto	148:fd96258d940d	1898
Kojto	148:fd96258d940d	1899	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
Kojto	148:fd96258d940d	1900	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Kojto	148:fd96258d940d	1901
Kojto	148:fd96258d940d	1902	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
Kojto	148:fd96258d940d	1903	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Kojto	148:fd96258d940d	1904
Kojto	148:fd96258d940d	1905	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Kojto	148:fd96258d940d	1906	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Kojto	148:fd96258d940d	1907
Kojto	148:fd96258d940d	1908	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
Kojto	148:fd96258d940d	1909	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Kojto	148:fd96258d940d	1910
Kojto	148:fd96258d940d	1911	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
Kojto	148:fd96258d940d	1912	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Kojto	148:fd96258d940d	1913
Kojto	148:fd96258d940d	1914	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
Kojto	148:fd96258d940d	1915	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Kojto	148:fd96258d940d	1916
Kojto	148:fd96258d940d	1917	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	148:fd96258d940d	1918	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Kojto	148:fd96258d940d	1919
Kojto	148:fd96258d940d	1920	/* Debug Core Register Selector Register Definitions */
Kojto	148:fd96258d940d	1921	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
Kojto	148:fd96258d940d	1922	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Kojto	148:fd96258d940d	1923
Kojto	148:fd96258d940d	1924	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
Kojto	148:fd96258d940d	1925	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Kojto	148:fd96258d940d	1926
Kojto	148:fd96258d940d	1927	/* Debug Exception and Monitor Control Register Definitions */
Kojto	148:fd96258d940d	1928	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
Kojto	148:fd96258d940d	1929	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Kojto	148:fd96258d940d	1930
Kojto	148:fd96258d940d	1931	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
Kojto	148:fd96258d940d	1932	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Kojto	148:fd96258d940d	1933
Kojto	148:fd96258d940d	1934	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
Kojto	148:fd96258d940d	1935	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Kojto	148:fd96258d940d	1936
Kojto	148:fd96258d940d	1937	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
Kojto	148:fd96258d940d	1938	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Kojto	148:fd96258d940d	1939
Kojto	148:fd96258d940d	1940	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
Kojto	148:fd96258d940d	1941	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Kojto	148:fd96258d940d	1942
Kojto	148:fd96258d940d	1943	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
Kojto	148:fd96258d940d	1944	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Kojto	148:fd96258d940d	1945
Kojto	148:fd96258d940d	1946	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
Kojto	148:fd96258d940d	1947	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Kojto	148:fd96258d940d	1948
Kojto	148:fd96258d940d	1949	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
Kojto	148:fd96258d940d	1950	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Kojto	148:fd96258d940d	1951
Kojto	148:fd96258d940d	1952	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
Kojto	148:fd96258d940d	1953	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Kojto	148:fd96258d940d	1954
Kojto	148:fd96258d940d	1955	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
Kojto	148:fd96258d940d	1956	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Kojto	148:fd96258d940d	1957
Kojto	148:fd96258d940d	1958	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
Kojto	148:fd96258d940d	1959	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Kojto	148:fd96258d940d	1960
Kojto	148:fd96258d940d	1961	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
Kojto	148:fd96258d940d	1962	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Kojto	148:fd96258d940d	1963
Kojto	148:fd96258d940d	1964	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	148:fd96258d940d	1965	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Kojto	148:fd96258d940d	1966
Kojto	148:fd96258d940d	1967	/* Debug Authentication Control Register Definitions */
Kojto	148:fd96258d940d	1968	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
Kojto	148:fd96258d940d	1969	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
Kojto	148:fd96258d940d	1970
Kojto	148:fd96258d940d	1971	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
Kojto	148:fd96258d940d	1972	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
Kojto	148:fd96258d940d	1973
Kojto	148:fd96258d940d	1974	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
Kojto	148:fd96258d940d	1975	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
Kojto	148:fd96258d940d	1976
Kojto	148:fd96258d940d	1977	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
Kojto	148:fd96258d940d	1978	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
Kojto	148:fd96258d940d	1979
Kojto	148:fd96258d940d	1980	/* Debug Security Control and Status Register Definitions */
Kojto	148:fd96258d940d	1981	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
Kojto	148:fd96258d940d	1982	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
Kojto	148:fd96258d940d	1983
Kojto	148:fd96258d940d	1984	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
Kojto	148:fd96258d940d	1985	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
Kojto	148:fd96258d940d	1986
Kojto	148:fd96258d940d	1987	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
Kojto	148:fd96258d940d	1988	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
Kojto	148:fd96258d940d	1989
Kojto	148:fd96258d940d	1990	/@} end of group CMSIS_CoreDebug /
Kojto	148:fd96258d940d	1991
Kojto	148:fd96258d940d	1992
Kojto	148:fd96258d940d	1993	/**
Kojto	148:fd96258d940d	1994	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1995	\defgroup CMSIS_core_bitfield Core register bit field macros
Kojto	148:fd96258d940d	1996	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Kojto	148:fd96258d940d	1997	@{
Kojto	148:fd96258d940d	1998	*/
Kojto	148:fd96258d940d	1999
Kojto	148:fd96258d940d	2000	/**
Kojto	148:fd96258d940d	2001	\brief Mask and shift a bit field value for use in a register bit range.
Kojto	148:fd96258d940d	2002	\param[in] field Name of the register bit field.
Kojto	148:fd96258d940d	2003	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Kojto	148:fd96258d940d	2004	\return Masked and shifted value.
Kojto	148:fd96258d940d	2005	*/
Kojto	148:fd96258d940d	2006	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Kojto	148:fd96258d940d	2007
Kojto	148:fd96258d940d	2008	/**
Kojto	148:fd96258d940d	2009	\brief Mask and shift a register value to extract a bit filed value.
Kojto	148:fd96258d940d	2010	\param[in] field Name of the register bit field.
Kojto	148:fd96258d940d	2011	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Kojto	148:fd96258d940d	2012	\return Masked and shifted bit field value.
Kojto	148:fd96258d940d	2013	*/
Kojto	148:fd96258d940d	2014	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Kojto	148:fd96258d940d	2015
Kojto	148:fd96258d940d	2016	/@} end of group CMSIS_core_bitfield /
Kojto	148:fd96258d940d	2017
Kojto	148:fd96258d940d	2018
Kojto	148:fd96258d940d	2019	/**
Kojto	148:fd96258d940d	2020	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	2021	\defgroup CMSIS_core_base Core Definitions
Kojto	148:fd96258d940d	2022	\brief Definitions for base addresses, unions, and structures.
Kojto	148:fd96258d940d	2023	@{
Kojto	148:fd96258d940d	2024	*/
Kojto	148:fd96258d940d	2025
Kojto	148:fd96258d940d	2026	/* Memory mapping of Core Hardware */
Kojto	148:fd96258d940d	2027	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Kojto	148:fd96258d940d	2028	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Kojto	148:fd96258d940d	2029	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Kojto	148:fd96258d940d	2030	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Kojto	148:fd96258d940d	2031	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Kojto	148:fd96258d940d	2032	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Kojto	148:fd96258d940d	2033	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Kojto	148:fd96258d940d	2034	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Kojto	148:fd96258d940d	2035
Kojto	148:fd96258d940d	2036	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Kojto	148:fd96258d940d	2037	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Kojto	148:fd96258d940d	2038	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Kojto	148:fd96258d940d	2039	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Kojto	148:fd96258d940d	2040	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Kojto	148:fd96258d940d	2041	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Kojto	148:fd96258d940d	2042	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Kojto	148:fd96258d940d	2043	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
Kojto	148:fd96258d940d	2044
Kojto	148:fd96258d940d	2045	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto	148:fd96258d940d	2046	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Kojto	148:fd96258d940d	2047	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Kojto	148:fd96258d940d	2048	#endif
Kojto	148:fd96258d940d	2049
Kojto	148:fd96258d940d	2050	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	2051	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
Kojto	148:fd96258d940d	2052	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
Kojto	148:fd96258d940d	2053	#endif
Kojto	148:fd96258d940d	2054
Kojto	148:fd96258d940d	2055	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Kojto	148:fd96258d940d	2056	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Kojto	148:fd96258d940d	2057
Kojto	148:fd96258d940d	2058	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	2059	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
Kojto	148:fd96258d940d	2060	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
Kojto	148:fd96258d940d	2061	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
Kojto	148:fd96258d940d	2062	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
Kojto	148:fd96258d940d	2063	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
Kojto	148:fd96258d940d	2064
Kojto	148:fd96258d940d	2065	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
Kojto	148:fd96258d940d	2066	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
Kojto	148:fd96258d940d	2067	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
Kojto	148:fd96258d940d	2068	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
Kojto	148:fd96258d940d	2069	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
Kojto	148:fd96258d940d	2070
Kojto	148:fd96258d940d	2071	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto	148:fd96258d940d	2072	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
Kojto	148:fd96258d940d	2073	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
Kojto	148:fd96258d940d	2074	#endif
Kojto	148:fd96258d940d	2075
Kojto	148:fd96258d940d	2076	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
Kojto	148:fd96258d940d	2077	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
Kojto	148:fd96258d940d	2078
Kojto	148:fd96258d940d	2079	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	2080	/@} /
Kojto	148:fd96258d940d	2081
Kojto	148:fd96258d940d	2082
Kojto	148:fd96258d940d	2083
Kojto	148:fd96258d940d	2084	/*******************************************************************************
Kojto	148:fd96258d940d	2085	* Hardware Abstraction Layer
Kojto	148:fd96258d940d	2086	Core Function Interface contains:
Kojto	148:fd96258d940d	2087	- Core NVIC Functions
Kojto	148:fd96258d940d	2088	- Core SysTick Functions
Kojto	148:fd96258d940d	2089	- Core Debug Functions
Kojto	148:fd96258d940d	2090	- Core Register Access Functions
Kojto	148:fd96258d940d	2091	******************************************************************************/
Kojto	148:fd96258d940d	2092	/**
Kojto	148:fd96258d940d	2093	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto	148:fd96258d940d	2094	*/
Kojto	148:fd96258d940d	2095
Kojto	148:fd96258d940d	2096
Kojto	148:fd96258d940d	2097
Kojto	148:fd96258d940d	2098	/* ########################## NVIC functions #################################### */
Kojto	148:fd96258d940d	2099	/**
Kojto	148:fd96258d940d	2100	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	2101	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto	148:fd96258d940d	2102	\brief Functions that manage interrupts and exceptions via the NVIC.
Kojto	148:fd96258d940d	2103	@{
Kojto	148:fd96258d940d	2104	*/
Kojto	148:fd96258d940d	2105
Kojto	148:fd96258d940d	2106	#ifdef CMSIS_NVIC_VIRTUAL
Kojto	148:fd96258d940d	2107	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto	148:fd96258d940d	2108	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Kojto	148:fd96258d940d	2109	#endif
Kojto	148:fd96258d940d	2110	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto	148:fd96258d940d	2111	#else
Kojto	148:fd96258d940d	2112	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Kojto	148:fd96258d940d	2113	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Kojto	148:fd96258d940d	2114	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Kojto	148:fd96258d940d	2115	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Kojto	148:fd96258d940d	2116	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Kojto	148:fd96258d940d	2117	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Kojto	148:fd96258d940d	2118	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Kojto	148:fd96258d940d	2119	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Kojto	148:fd96258d940d	2120	#define NVIC_GetActive __NVIC_GetActive
Kojto	148:fd96258d940d	2121	#define NVIC_SetPriority __NVIC_SetPriority
Kojto	148:fd96258d940d	2122	#define NVIC_GetPriority __NVIC_GetPriority
Kojto	148:fd96258d940d	2123	#define NVIC_SystemReset __NVIC_SystemReset
Kojto	148:fd96258d940d	2124	#endif /* CMSIS_NVIC_VIRTUAL */
Kojto	148:fd96258d940d	2125
Kojto	148:fd96258d940d	2126	#ifdef CMSIS_VECTAB_VIRTUAL
Kojto	148:fd96258d940d	2127	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto	148:fd96258d940d	2128	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Kojto	148:fd96258d940d	2129	#endif
Kojto	148:fd96258d940d	2130	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto	148:fd96258d940d	2131	#else
Kojto	148:fd96258d940d	2132	#define NVIC_SetVector __NVIC_SetVector
Kojto	148:fd96258d940d	2133	#define NVIC_GetVector __NVIC_GetVector
Kojto	148:fd96258d940d	2134	#endif /* (CMSIS_VECTAB_VIRTUAL) */
Kojto	148:fd96258d940d	2135
Kojto	148:fd96258d940d	2136	#define NVIC_USER_IRQ_OFFSET 16
Kojto	148:fd96258d940d	2137
Kojto	148:fd96258d940d	2138
Kojto	148:fd96258d940d	2139
Kojto	148:fd96258d940d	2140	/**
Kojto	148:fd96258d940d	2141	\brief Set Priority Grouping
Kojto	148:fd96258d940d	2142	\details Sets the priority grouping field using the required unlock sequence.
Kojto	148:fd96258d940d	2143	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto	148:fd96258d940d	2144	Only values from 0..7 are used.
Kojto	148:fd96258d940d	2145	In case of a conflict between priority grouping and available
Kojto	148:fd96258d940d	2146	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	148:fd96258d940d	2147	\param [in] PriorityGroup Priority grouping field.
Kojto	148:fd96258d940d	2148	*/
Kojto	148:fd96258d940d	2149	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto	148:fd96258d940d	2150	{
Kojto	148:fd96258d940d	2151	uint32_t reg_value;
Kojto	148:fd96258d940d	2152	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	148:fd96258d940d	2153
Kojto	148:fd96258d940d	2154	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	148:fd96258d940d	2155	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	148:fd96258d940d	2156	reg_value = (reg_value \|
Kojto	148:fd96258d940d	2157	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	148:fd96258d940d	2158	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
Kojto	148:fd96258d940d	2159	SCB->AIRCR = reg_value;
Kojto	148:fd96258d940d	2160	}
Kojto	148:fd96258d940d	2161
Kojto	148:fd96258d940d	2162
Kojto	148:fd96258d940d	2163	/**
Kojto	148:fd96258d940d	2164	\brief Get Priority Grouping
Kojto	148:fd96258d940d	2165	\details Reads the priority grouping field from the NVIC Interrupt Controller.
Kojto	148:fd96258d940d	2166	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto	148:fd96258d940d	2167	*/
Kojto	148:fd96258d940d	2168	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Kojto	148:fd96258d940d	2169	{
Kojto	148:fd96258d940d	2170	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto	148:fd96258d940d	2171	}
Kojto	148:fd96258d940d	2172
Kojto	148:fd96258d940d	2173
Kojto	148:fd96258d940d	2174	/**
Kojto	148:fd96258d940d	2175	\brief Enable Interrupt
Kojto	148:fd96258d940d	2176	\details Enables a device specific interrupt in the NVIC interrupt controller.
Kojto	148:fd96258d940d	2177	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2178	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2179	*/
Kojto	148:fd96258d940d	2180	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2181	{
Kojto	148:fd96258d940d	2182	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2183	{
Kojto	148:fd96258d940d	2184	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	2185	}
Kojto	148:fd96258d940d	2186	}
Kojto	148:fd96258d940d	2187
Kojto	148:fd96258d940d	2188
Kojto	148:fd96258d940d	2189	/**
Kojto	148:fd96258d940d	2190	\brief Get Interrupt Enable status
Kojto	148:fd96258d940d	2191	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Kojto	148:fd96258d940d	2192	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2193	\return 0 Interrupt is not enabled.
Kojto	148:fd96258d940d	2194	\return 1 Interrupt is enabled.
Kojto	148:fd96258d940d	2195	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2196	*/
Kojto	148:fd96258d940d	2197	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2198	{
Kojto	148:fd96258d940d	2199	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2200	{
Kojto	148:fd96258d940d	2201	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2202	}
Kojto	148:fd96258d940d	2203	else
Kojto	148:fd96258d940d	2204	{
Kojto	148:fd96258d940d	2205	return(0U);
Kojto	148:fd96258d940d	2206	}
Kojto	148:fd96258d940d	2207	}
Kojto	148:fd96258d940d	2208
Kojto	148:fd96258d940d	2209
Kojto	148:fd96258d940d	2210	/**
Kojto	148:fd96258d940d	2211	\brief Disable Interrupt
Kojto	148:fd96258d940d	2212	\details Disables a device specific interrupt in the NVIC interrupt controller.
Kojto	148:fd96258d940d	2213	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2214	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2215	*/
Kojto	148:fd96258d940d	2216	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2217	{
Kojto	148:fd96258d940d	2218	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2219	{
Kojto	148:fd96258d940d	2220	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	2221	__DSB();
Kojto	148:fd96258d940d	2222	__ISB();
Kojto	148:fd96258d940d	2223	}
Kojto	148:fd96258d940d	2224	}
Kojto	148:fd96258d940d	2225
Kojto	148:fd96258d940d	2226
Kojto	148:fd96258d940d	2227	/**
Kojto	148:fd96258d940d	2228	\brief Get Pending Interrupt
Kojto	148:fd96258d940d	2229	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Kojto	148:fd96258d940d	2230	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2231	\return 0 Interrupt status is not pending.
Kojto	148:fd96258d940d	2232	\return 1 Interrupt status is pending.
Kojto	148:fd96258d940d	2233	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2234	*/
Kojto	148:fd96258d940d	2235	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2236	{
Kojto	148:fd96258d940d	2237	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2238	{
Kojto	148:fd96258d940d	2239	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2240	}
Kojto	148:fd96258d940d	2241	else
Kojto	148:fd96258d940d	2242	{
Kojto	148:fd96258d940d	2243	return(0U);
Kojto	148:fd96258d940d	2244	}
Kojto	148:fd96258d940d	2245	}
Kojto	148:fd96258d940d	2246
Kojto	148:fd96258d940d	2247
Kojto	148:fd96258d940d	2248	/**
Kojto	148:fd96258d940d	2249	\brief Set Pending Interrupt
Kojto	148:fd96258d940d	2250	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Kojto	148:fd96258d940d	2251	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2252	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2253	*/
Kojto	148:fd96258d940d	2254	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2255	{
Kojto	148:fd96258d940d	2256	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2257	{
Kojto	148:fd96258d940d	2258	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	2259	}
Kojto	148:fd96258d940d	2260	}
Kojto	148:fd96258d940d	2261
Kojto	148:fd96258d940d	2262
Kojto	148:fd96258d940d	2263	/**
Kojto	148:fd96258d940d	2264	\brief Clear Pending Interrupt
Kojto	148:fd96258d940d	2265	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Kojto	148:fd96258d940d	2266	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2267	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2268	*/
Kojto	148:fd96258d940d	2269	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2270	{
Kojto	148:fd96258d940d	2271	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2272	{
Kojto	148:fd96258d940d	2273	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	2274	}
Kojto	148:fd96258d940d	2275	}
Kojto	148:fd96258d940d	2276
Kojto	148:fd96258d940d	2277
Kojto	148:fd96258d940d	2278	/**
Kojto	148:fd96258d940d	2279	\brief Get Active Interrupt
Kojto	148:fd96258d940d	2280	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Kojto	148:fd96258d940d	2281	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2282	\return 0 Interrupt status is not active.
Kojto	148:fd96258d940d	2283	\return 1 Interrupt status is active.
Kojto	148:fd96258d940d	2284	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2285	*/
Kojto	148:fd96258d940d	2286	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2287	{
Kojto	148:fd96258d940d	2288	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2289	{
Kojto	148:fd96258d940d	2290	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2291	}
Kojto	148:fd96258d940d	2292	else
Kojto	148:fd96258d940d	2293	{
Kojto	148:fd96258d940d	2294	return(0U);
Kojto	148:fd96258d940d	2295	}
Kojto	148:fd96258d940d	2296	}
Kojto	148:fd96258d940d	2297
Kojto	148:fd96258d940d	2298
Kojto	148:fd96258d940d	2299	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	2300	/**
Kojto	148:fd96258d940d	2301	\brief Get Interrupt Target State
Kojto	148:fd96258d940d	2302	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Kojto	148:fd96258d940d	2303	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2304	\return 0 if interrupt is assigned to Secure
Kojto	148:fd96258d940d	2305	\return 1 if interrupt is assigned to Non Secure
Kojto	148:fd96258d940d	2306	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2307	*/
Kojto	148:fd96258d940d	2308	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2309	{
Kojto	148:fd96258d940d	2310	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2311	{
Kojto	148:fd96258d940d	2312	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2313	}
Kojto	148:fd96258d940d	2314	else
Kojto	148:fd96258d940d	2315	{
Kojto	148:fd96258d940d	2316	return(0U);
Kojto	148:fd96258d940d	2317	}
Kojto	148:fd96258d940d	2318	}
Kojto	148:fd96258d940d	2319
Kojto	148:fd96258d940d	2320
Kojto	148:fd96258d940d	2321	/**
Kojto	148:fd96258d940d	2322	\brief Set Interrupt Target State
Kojto	148:fd96258d940d	2323	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Kojto	148:fd96258d940d	2324	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2325	\return 0 if interrupt is assigned to Secure
Kojto	148:fd96258d940d	2326	1 if interrupt is assigned to Non Secure
Kojto	148:fd96258d940d	2327	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2328	*/
Kojto	148:fd96258d940d	2329	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2330	{
Kojto	148:fd96258d940d	2331	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2332	{
Kojto	148:fd96258d940d	2333	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
Kojto	148:fd96258d940d	2334	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2335	}
Kojto	148:fd96258d940d	2336	else
Kojto	148:fd96258d940d	2337	{
Kojto	148:fd96258d940d	2338	return(0U);
Kojto	148:fd96258d940d	2339	}
Kojto	148:fd96258d940d	2340	}
Kojto	148:fd96258d940d	2341
Kojto	148:fd96258d940d	2342
Kojto	148:fd96258d940d	2343	/**
Kojto	148:fd96258d940d	2344	\brief Clear Interrupt Target State
Kojto	148:fd96258d940d	2345	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Kojto	148:fd96258d940d	2346	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2347	\return 0 if interrupt is assigned to Secure
Kojto	148:fd96258d940d	2348	1 if interrupt is assigned to Non Secure
Kojto	148:fd96258d940d	2349	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2350	*/
Kojto	148:fd96258d940d	2351	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2352	{
Kojto	148:fd96258d940d	2353	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2354	{
Kojto	148:fd96258d940d	2355	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
Kojto	148:fd96258d940d	2356	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2357	}
Kojto	148:fd96258d940d	2358	else
Kojto	148:fd96258d940d	2359	{
Kojto	148:fd96258d940d	2360	return(0U);
Kojto	148:fd96258d940d	2361	}
Kojto	148:fd96258d940d	2362	}
Kojto	148:fd96258d940d	2363	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	2364
Kojto	148:fd96258d940d	2365
Kojto	148:fd96258d940d	2366	/**
Kojto	148:fd96258d940d	2367	\brief Set Interrupt Priority
Kojto	148:fd96258d940d	2368	\details Sets the priority of a device specific interrupt or a processor exception.
Kojto	148:fd96258d940d	2369	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	2370	or negative to specify a processor exception.
Kojto	148:fd96258d940d	2371	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	2372	\param [in] priority Priority to set.
Kojto	148:fd96258d940d	2373	\note The priority cannot be set for every processor exception.
Kojto	148:fd96258d940d	2374	*/
Kojto	148:fd96258d940d	2375	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto	148:fd96258d940d	2376	{
Kojto	148:fd96258d940d	2377	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2378	{
Kojto	148:fd96258d940d	2379	NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	148:fd96258d940d	2380	}
Kojto	148:fd96258d940d	2381	else
Kojto	148:fd96258d940d	2382	{
Kojto	148:fd96258d940d	2383	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	148:fd96258d940d	2384	}
Kojto	148:fd96258d940d	2385	}
Kojto	148:fd96258d940d	2386
Kojto	148:fd96258d940d	2387
Kojto	148:fd96258d940d	2388	/**
Kojto	148:fd96258d940d	2389	\brief Get Interrupt Priority
Kojto	148:fd96258d940d	2390	\details Reads the priority of a device specific interrupt or a processor exception.
Kojto	148:fd96258d940d	2391	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	2392	or negative to specify a processor exception.
Kojto	148:fd96258d940d	2393	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	2394	\return Interrupt Priority.
Kojto	148:fd96258d940d	2395	Value is aligned automatically to the implemented priority bits of the microcontroller.
Kojto	148:fd96258d940d	2396	*/
Kojto	148:fd96258d940d	2397	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2398	{
Kojto	148:fd96258d940d	2399
Kojto	148:fd96258d940d	2400	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2401	{
Kojto	148:fd96258d940d	2402	return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Kojto	148:fd96258d940d	2403	}
Kojto	148:fd96258d940d	2404	else
Kojto	148:fd96258d940d	2405	{
Kojto	148:fd96258d940d	2406	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Kojto	148:fd96258d940d	2407	}
Kojto	148:fd96258d940d	2408	}
Kojto	148:fd96258d940d	2409
Kojto	148:fd96258d940d	2410
Kojto	148:fd96258d940d	2411	/**
Kojto	148:fd96258d940d	2412	\brief Encode Priority
Kojto	148:fd96258d940d	2413	\details Encodes the priority for an interrupt with the given priority group,
Kojto	148:fd96258d940d	2414	preemptive priority value, and subpriority value.
Kojto	148:fd96258d940d	2415	In case of a conflict between priority grouping and available
Kojto	148:fd96258d940d	2416	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	148:fd96258d940d	2417	\param [in] PriorityGroup Used priority group.
Kojto	148:fd96258d940d	2418	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto	148:fd96258d940d	2419	\param [in] SubPriority Subpriority value (starting from 0).
Kojto	148:fd96258d940d	2420	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto	148:fd96258d940d	2421	*/
Kojto	148:fd96258d940d	2422	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto	148:fd96258d940d	2423	{
Kojto	148:fd96258d940d	2424	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	148:fd96258d940d	2425	uint32_t PreemptPriorityBits;
Kojto	148:fd96258d940d	2426	uint32_t SubPriorityBits;
Kojto	148:fd96258d940d	2427
Kojto	148:fd96258d940d	2428	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	148:fd96258d940d	2429	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	148:fd96258d940d	2430
Kojto	148:fd96258d940d	2431	return (
Kojto	148:fd96258d940d	2432	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Kojto	148:fd96258d940d	2433	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto	148:fd96258d940d	2434	);
Kojto	148:fd96258d940d	2435	}
Kojto	148:fd96258d940d	2436
Kojto	148:fd96258d940d	2437
Kojto	148:fd96258d940d	2438	/**
Kojto	148:fd96258d940d	2439	\brief Decode Priority
Kojto	148:fd96258d940d	2440	\details Decodes an interrupt priority value with a given priority group to
Kojto	148:fd96258d940d	2441	preemptive priority value and subpriority value.
Kojto	148:fd96258d940d	2442	In case of a conflict between priority grouping and available
Kojto	148:fd96258d940d	2443	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto	148:fd96258d940d	2444	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto	148:fd96258d940d	2445	\param [in] PriorityGroup Used priority group.
Kojto	148:fd96258d940d	2446	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto	148:fd96258d940d	2447	\param [out] pSubPriority Subpriority value (starting from 0).
Kojto	148:fd96258d940d	2448	*/
Kojto	148:fd96258d940d	2449	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
Kojto	148:fd96258d940d	2450	{
Kojto	148:fd96258d940d	2451	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	148:fd96258d940d	2452	uint32_t PreemptPriorityBits;
Kojto	148:fd96258d940d	2453	uint32_t SubPriorityBits;
Kojto	148:fd96258d940d	2454
Kojto	148:fd96258d940d	2455	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	148:fd96258d940d	2456	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	148:fd96258d940d	2457
Kojto	148:fd96258d940d	2458	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto	148:fd96258d940d	2459	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto	148:fd96258d940d	2460	}
Kojto	148:fd96258d940d	2461
Kojto	148:fd96258d940d	2462
Kojto	148:fd96258d940d	2463	/**
Kojto	148:fd96258d940d	2464	\brief Set Interrupt Vector
Kojto	148:fd96258d940d	2465	\details Sets an interrupt vector in SRAM based interrupt vector table.
Kojto	148:fd96258d940d	2466	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	2467	or negative to specify a processor exception.
Kojto	148:fd96258d940d	2468	VTOR must been relocated to SRAM before.
Kojto	148:fd96258d940d	2469	\param [in] IRQn Interrupt number
Kojto	148:fd96258d940d	2470	\param [in] vector Address of interrupt handler function
Kojto	148:fd96258d940d	2471	*/
Kojto	148:fd96258d940d	2472	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Kojto	148:fd96258d940d	2473	{
Kojto	148:fd96258d940d	2474	uint32_t vectors = (uint32_t )SCB->VTOR;
Kojto	148:fd96258d940d	2475	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Kojto	148:fd96258d940d	2476	}
Kojto	148:fd96258d940d	2477
Kojto	148:fd96258d940d	2478
Kojto	148:fd96258d940d	2479	/**
Kojto	148:fd96258d940d	2480	\brief Get Interrupt Vector
Kojto	148:fd96258d940d	2481	\details Reads an interrupt vector from interrupt vector table.
Kojto	148:fd96258d940d	2482	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	2483	or negative to specify a processor exception.
Kojto	148:fd96258d940d	2484	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	2485	\return Address of interrupt handler function
Kojto	148:fd96258d940d	2486	*/
Kojto	148:fd96258d940d	2487	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2488	{
Kojto	148:fd96258d940d	2489	uint32_t vectors = (uint32_t )SCB->VTOR;
Kojto	148:fd96258d940d	2490	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Kojto	148:fd96258d940d	2491	}
Kojto	148:fd96258d940d	2492
Kojto	148:fd96258d940d	2493
Kojto	148:fd96258d940d	2494	/**
Kojto	148:fd96258d940d	2495	\brief System Reset
Kojto	148:fd96258d940d	2496	\details Initiates a system reset request to reset the MCU.
Kojto	148:fd96258d940d	2497	*/
Kojto	148:fd96258d940d	2498	__STATIC_INLINE void __NVIC_SystemReset(void)
Kojto	148:fd96258d940d	2499	{
Kojto	148:fd96258d940d	2500	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	148:fd96258d940d	2501	buffered write are completed before reset */
Kojto	148:fd96258d940d	2502	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	148:fd96258d940d	2503	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	148:fd96258d940d	2504	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto	148:fd96258d940d	2505	__DSB(); /* Ensure completion of memory access */
Kojto	148:fd96258d940d	2506
Kojto	148:fd96258d940d	2507	for(;;) /* wait until reset */
Kojto	148:fd96258d940d	2508	{
Kojto	148:fd96258d940d	2509	__NOP();
Kojto	148:fd96258d940d	2510	}
Kojto	148:fd96258d940d	2511	}
Kojto	148:fd96258d940d	2512
Kojto	148:fd96258d940d	2513	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	2514	/**
Kojto	148:fd96258d940d	2515	\brief Set Priority Grouping (non-secure)
Kojto	148:fd96258d940d	2516	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
Kojto	148:fd96258d940d	2517	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto	148:fd96258d940d	2518	Only values from 0..7 are used.
Kojto	148:fd96258d940d	2519	In case of a conflict between priority grouping and available
Kojto	148:fd96258d940d	2520	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	148:fd96258d940d	2521	\param [in] PriorityGroup Priority grouping field.
Kojto	148:fd96258d940d	2522	*/
Kojto	148:fd96258d940d	2523	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
Kojto	148:fd96258d940d	2524	{
Kojto	148:fd96258d940d	2525	uint32_t reg_value;
Kojto	148:fd96258d940d	2526	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	148:fd96258d940d	2527
Kojto	148:fd96258d940d	2528	reg_value = SCB_NS->AIRCR; /* read old register configuration */
Kojto	148:fd96258d940d	2529	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	148:fd96258d940d	2530	reg_value = (reg_value \|
Kojto	148:fd96258d940d	2531	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	148:fd96258d940d	2532	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
Kojto	148:fd96258d940d	2533	SCB_NS->AIRCR = reg_value;
Kojto	148:fd96258d940d	2534	}
Kojto	148:fd96258d940d	2535
Kojto	148:fd96258d940d	2536
Kojto	148:fd96258d940d	2537	/**
Kojto	148:fd96258d940d	2538	\brief Get Priority Grouping (non-secure)
Kojto	148:fd96258d940d	2539	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
Kojto	148:fd96258d940d	2540	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto	148:fd96258d940d	2541	*/
Kojto	148:fd96258d940d	2542	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
Kojto	148:fd96258d940d	2543	{
Kojto	148:fd96258d940d	2544	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto	148:fd96258d940d	2545	}
Kojto	148:fd96258d940d	2546
Kojto	148:fd96258d940d	2547
Kojto	148:fd96258d940d	2548	/**
Kojto	148:fd96258d940d	2549	\brief Enable Interrupt (non-secure)
Kojto	148:fd96258d940d	2550	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Kojto	148:fd96258d940d	2551	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2552	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2553	*/
Kojto	148:fd96258d940d	2554	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2555	{
Kojto	148:fd96258d940d	2556	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2557	{
Kojto	148:fd96258d940d	2558	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	2559	}
Kojto	148:fd96258d940d	2560	}
Kojto	148:fd96258d940d	2561
Kojto	148:fd96258d940d	2562
Kojto	148:fd96258d940d	2563	/**
Kojto	148:fd96258d940d	2564	\brief Get Interrupt Enable status (non-secure)
Kojto	148:fd96258d940d	2565	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
Kojto	148:fd96258d940d	2566	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2567	\return 0 Interrupt is not enabled.
Kojto	148:fd96258d940d	2568	\return 1 Interrupt is enabled.
Kojto	148:fd96258d940d	2569	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2570	*/
Kojto	148:fd96258d940d	2571	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2572	{
Kojto	148:fd96258d940d	2573	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2574	{
Kojto	148:fd96258d940d	2575	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2576	}
Kojto	148:fd96258d940d	2577	else
Kojto	148:fd96258d940d	2578	{
Kojto	148:fd96258d940d	2579	return(0U);
Kojto	148:fd96258d940d	2580	}
Kojto	148:fd96258d940d	2581	}
Kojto	148:fd96258d940d	2582
Kojto	148:fd96258d940d	2583
Kojto	148:fd96258d940d	2584	/**
Kojto	148:fd96258d940d	2585	\brief Disable Interrupt (non-secure)
Kojto	148:fd96258d940d	2586	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Kojto	148:fd96258d940d	2587	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2588	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2589	*/
Kojto	148:fd96258d940d	2590	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2591	{
Kojto	148:fd96258d940d	2592	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2593	{
Kojto	148:fd96258d940d	2594	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	2595	}
Kojto	148:fd96258d940d	2596	}
Kojto	148:fd96258d940d	2597
Kojto	148:fd96258d940d	2598
Kojto	148:fd96258d940d	2599	/**
Kojto	148:fd96258d940d	2600	\brief Get Pending Interrupt (non-secure)
Kojto	148:fd96258d940d	2601	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
Kojto	148:fd96258d940d	2602	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2603	\return 0 Interrupt status is not pending.
Kojto	148:fd96258d940d	2604	\return 1 Interrupt status is pending.
Kojto	148:fd96258d940d	2605	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2606	*/
Kojto	148:fd96258d940d	2607	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2608	{
Kojto	148:fd96258d940d	2609	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2610	{
Kojto	148:fd96258d940d	2611	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2612	}
Kojto	148:fd96258d940d	2613	else
Kojto	148:fd96258d940d	2614	{
Kojto	148:fd96258d940d	2615	return(0U);
Kojto	148:fd96258d940d	2616	}
Kojto	148:fd96258d940d	2617	}
Kojto	148:fd96258d940d	2618
Kojto	148:fd96258d940d	2619
Kojto	148:fd96258d940d	2620	/**
Kojto	148:fd96258d940d	2621	\brief Set Pending Interrupt (non-secure)
Kojto	148:fd96258d940d	2622	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Kojto	148:fd96258d940d	2623	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2624	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2625	*/
Kojto	148:fd96258d940d	2626	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2627	{
Kojto	148:fd96258d940d	2628	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2629	{
Kojto	148:fd96258d940d	2630	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	2631	}
Kojto	148:fd96258d940d	2632	}
Kojto	148:fd96258d940d	2633
Kojto	148:fd96258d940d	2634
Kojto	148:fd96258d940d	2635	/**
Kojto	148:fd96258d940d	2636	\brief Clear Pending Interrupt (non-secure)
Kojto	148:fd96258d940d	2637	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Kojto	148:fd96258d940d	2638	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2639	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2640	*/
Kojto	148:fd96258d940d	2641	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2642	{
Kojto	148:fd96258d940d	2643	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2644	{
Kojto	148:fd96258d940d	2645	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	2646	}
Kojto	148:fd96258d940d	2647	}
Kojto	148:fd96258d940d	2648
Kojto	148:fd96258d940d	2649
Kojto	148:fd96258d940d	2650	/**
Kojto	148:fd96258d940d	2651	\brief Get Active Interrupt (non-secure)
Kojto	148:fd96258d940d	2652	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
Kojto	148:fd96258d940d	2653	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	2654	\return 0 Interrupt status is not active.
Kojto	148:fd96258d940d	2655	\return 1 Interrupt status is active.
Kojto	148:fd96258d940d	2656	\note IRQn must not be negative.
Kojto	148:fd96258d940d	2657	*/
Kojto	148:fd96258d940d	2658	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2659	{
Kojto	148:fd96258d940d	2660	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2661	{
Kojto	148:fd96258d940d	2662	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	2663	}
Kojto	148:fd96258d940d	2664	else
Kojto	148:fd96258d940d	2665	{
Kojto	148:fd96258d940d	2666	return(0U);
Kojto	148:fd96258d940d	2667	}
Kojto	148:fd96258d940d	2668	}
Kojto	148:fd96258d940d	2669
Kojto	148:fd96258d940d	2670
Kojto	148:fd96258d940d	2671	/**
Kojto	148:fd96258d940d	2672	\brief Set Interrupt Priority (non-secure)
Kojto	148:fd96258d940d	2673	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Kojto	148:fd96258d940d	2674	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	2675	or negative to specify a processor exception.
Kojto	148:fd96258d940d	2676	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	2677	\param [in] priority Priority to set.
Kojto	148:fd96258d940d	2678	\note The priority cannot be set for every non-secure processor exception.
Kojto	148:fd96258d940d	2679	*/
Kojto	148:fd96258d940d	2680	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
Kojto	148:fd96258d940d	2681	{
Kojto	148:fd96258d940d	2682	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2683	{
Kojto	148:fd96258d940d	2684	NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	148:fd96258d940d	2685	}
Kojto	148:fd96258d940d	2686	else
Kojto	148:fd96258d940d	2687	{
Kojto	148:fd96258d940d	2688	SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	148:fd96258d940d	2689	}
Kojto	148:fd96258d940d	2690	}
Kojto	148:fd96258d940d	2691
Kojto	148:fd96258d940d	2692
Kojto	148:fd96258d940d	2693	/**
Kojto	148:fd96258d940d	2694	\brief Get Interrupt Priority (non-secure)
Kojto	148:fd96258d940d	2695	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Kojto	148:fd96258d940d	2696	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	2697	or negative to specify a processor exception.
Kojto	148:fd96258d940d	2698	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	2699	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
Kojto	148:fd96258d940d	2700	*/
Kojto	148:fd96258d940d	2701	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	2702	{
Kojto	148:fd96258d940d	2703
Kojto	148:fd96258d940d	2704	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	2705	{
Kojto	148:fd96258d940d	2706	return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Kojto	148:fd96258d940d	2707	}
Kojto	148:fd96258d940d	2708	else
Kojto	148:fd96258d940d	2709	{
Kojto	148:fd96258d940d	2710	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Kojto	148:fd96258d940d	2711	}
Kojto	148:fd96258d940d	2712	}
Kojto	148:fd96258d940d	2713	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	2714
Kojto	148:fd96258d940d	2715	/@} end of CMSIS_Core_NVICFunctions /
Kojto	148:fd96258d940d	2716
Anna Bridge	160:5571c4ff569f	2717	/* ########################## MPU functions #################################### */
Anna Bridge	160:5571c4ff569f	2718
Anna Bridge	160:5571c4ff569f	2719	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	2720
Anna Bridge	160:5571c4ff569f	2721	#include "mpu_armv8.h"
Anna Bridge	160:5571c4ff569f	2722
Anna Bridge	160:5571c4ff569f	2723	#endif
Kojto	148:fd96258d940d	2724
Kojto	148:fd96258d940d	2725	/* ########################## FPU functions #################################### */
Kojto	148:fd96258d940d	2726	/**
Kojto	148:fd96258d940d	2727	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	2728	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Kojto	148:fd96258d940d	2729	\brief Function that provides FPU type.
Kojto	148:fd96258d940d	2730	@{
Kojto	148:fd96258d940d	2731	*/
Kojto	148:fd96258d940d	2732
Kojto	148:fd96258d940d	2733	/**
Kojto	148:fd96258d940d	2734	\brief get FPU type
Kojto	148:fd96258d940d	2735	\details returns the FPU type
Kojto	148:fd96258d940d	2736	\returns
Kojto	148:fd96258d940d	2737	- \b 0: No FPU
Kojto	148:fd96258d940d	2738	- \b 1: Single precision FPU
Kojto	148:fd96258d940d	2739	- \b 2: Double + Single precision FPU
Kojto	148:fd96258d940d	2740	*/
Kojto	148:fd96258d940d	2741	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Kojto	148:fd96258d940d	2742	{
Kojto	148:fd96258d940d	2743	uint32_t mvfr0;
Kojto	148:fd96258d940d	2744
Kojto	148:fd96258d940d	2745	mvfr0 = FPU->MVFR0;
Kojto	148:fd96258d940d	2746	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
Kojto	148:fd96258d940d	2747	{
Kojto	148:fd96258d940d	2748	return 2U; /* Double + Single precision FPU */
Kojto	148:fd96258d940d	2749	}
Kojto	148:fd96258d940d	2750	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
Kojto	148:fd96258d940d	2751	{
Kojto	148:fd96258d940d	2752	return 1U; /* Single precision FPU */
Kojto	148:fd96258d940d	2753	}
Kojto	148:fd96258d940d	2754	else
Kojto	148:fd96258d940d	2755	{
Kojto	148:fd96258d940d	2756	return 0U; /* No FPU */
Kojto	148:fd96258d940d	2757	}
Kojto	148:fd96258d940d	2758	}
Kojto	148:fd96258d940d	2759
Kojto	148:fd96258d940d	2760
Kojto	148:fd96258d940d	2761	/@} end of CMSIS_Core_FpuFunctions /
Kojto	148:fd96258d940d	2762
Kojto	148:fd96258d940d	2763
Kojto	148:fd96258d940d	2764
Kojto	148:fd96258d940d	2765	/* ########################## SAU functions #################################### */
Kojto	148:fd96258d940d	2766	/**
Kojto	148:fd96258d940d	2767	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	2768	\defgroup CMSIS_Core_SAUFunctions SAU Functions
Kojto	148:fd96258d940d	2769	\brief Functions that configure the SAU.
Kojto	148:fd96258d940d	2770	@{
Kojto	148:fd96258d940d	2771	*/
Kojto	148:fd96258d940d	2772
Kojto	148:fd96258d940d	2773	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	2774
Kojto	148:fd96258d940d	2775	/**
Kojto	148:fd96258d940d	2776	\brief Enable SAU
Kojto	148:fd96258d940d	2777	\details Enables the Security Attribution Unit (SAU).
Kojto	148:fd96258d940d	2778	*/
Kojto	148:fd96258d940d	2779	__STATIC_INLINE void TZ_SAU_Enable(void)
Kojto	148:fd96258d940d	2780	{
Kojto	148:fd96258d940d	2781	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
Kojto	148:fd96258d940d	2782	}
Kojto	148:fd96258d940d	2783
Kojto	148:fd96258d940d	2784
Kojto	148:fd96258d940d	2785
Kojto	148:fd96258d940d	2786	/**
Kojto	148:fd96258d940d	2787	\brief Disable SAU
Kojto	148:fd96258d940d	2788	\details Disables the Security Attribution Unit (SAU).
Kojto	148:fd96258d940d	2789	*/
Kojto	148:fd96258d940d	2790	__STATIC_INLINE void TZ_SAU_Disable(void)
Kojto	148:fd96258d940d	2791	{
Kojto	148:fd96258d940d	2792	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
Kojto	148:fd96258d940d	2793	}
Kojto	148:fd96258d940d	2794
Kojto	148:fd96258d940d	2795	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	2796
Kojto	148:fd96258d940d	2797	/@} end of CMSIS_Core_SAUFunctions /
Kojto	148:fd96258d940d	2798
Kojto	148:fd96258d940d	2799
Kojto	148:fd96258d940d	2800
Kojto	148:fd96258d940d	2801
Kojto	148:fd96258d940d	2802	/* ################################## SysTick function ############################################ */
Kojto	148:fd96258d940d	2803	/**
Kojto	148:fd96258d940d	2804	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	2805	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto	148:fd96258d940d	2806	\brief Functions that configure the System.
Kojto	148:fd96258d940d	2807	@{
Kojto	148:fd96258d940d	2808	*/
Kojto	148:fd96258d940d	2809
Kojto	148:fd96258d940d	2810	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Kojto	148:fd96258d940d	2811
Kojto	148:fd96258d940d	2812	/**
Kojto	148:fd96258d940d	2813	\brief System Tick Configuration
Kojto	148:fd96258d940d	2814	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto	148:fd96258d940d	2815	Counter is in free running mode to generate periodic interrupts.
Kojto	148:fd96258d940d	2816	\param [in] ticks Number of ticks between two interrupts.
Kojto	148:fd96258d940d	2817	\return 0 Function succeeded.
Kojto	148:fd96258d940d	2818	\return 1 Function failed.
Kojto	148:fd96258d940d	2819	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	148:fd96258d940d	2820	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	148:fd96258d940d	2821	must contain a vendor-specific implementation of this function.
Kojto	148:fd96258d940d	2822	*/
Kojto	148:fd96258d940d	2823	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto	148:fd96258d940d	2824	{
Kojto	148:fd96258d940d	2825	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Kojto	148:fd96258d940d	2826	{
Kojto	148:fd96258d940d	2827	return (1UL); /* Reload value impossible */
Kojto	148:fd96258d940d	2828	}
Kojto	148:fd96258d940d	2829
Kojto	148:fd96258d940d	2830	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	148:fd96258d940d	2831	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	148:fd96258d940d	2832	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto	148:fd96258d940d	2833	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	148:fd96258d940d	2834	SysTick_CTRL_TICKINT_Msk \|
Kojto	148:fd96258d940d	2835	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	148:fd96258d940d	2836	return (0UL); /* Function successful */
Kojto	148:fd96258d940d	2837	}
Kojto	148:fd96258d940d	2838
Kojto	148:fd96258d940d	2839	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	2840	/**
Kojto	148:fd96258d940d	2841	\brief System Tick Configuration (non-secure)
Kojto	148:fd96258d940d	2842	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Kojto	148:fd96258d940d	2843	Counter is in free running mode to generate periodic interrupts.
Kojto	148:fd96258d940d	2844	\param [in] ticks Number of ticks between two interrupts.
Kojto	148:fd96258d940d	2845	\return 0 Function succeeded.
Kojto	148:fd96258d940d	2846	\return 1 Function failed.
Kojto	148:fd96258d940d	2847	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	148:fd96258d940d	2848	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	148:fd96258d940d	2849	must contain a vendor-specific implementation of this function.
Kojto	148:fd96258d940d	2850
Kojto	148:fd96258d940d	2851	*/
Kojto	148:fd96258d940d	2852	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
Kojto	148:fd96258d940d	2853	{
Kojto	148:fd96258d940d	2854	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Kojto	148:fd96258d940d	2855	{
Kojto	148:fd96258d940d	2856	return (1UL); /* Reload value impossible */
Kojto	148:fd96258d940d	2857	}
Kojto	148:fd96258d940d	2858
Kojto	148:fd96258d940d	2859	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	148:fd96258d940d	2860	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	148:fd96258d940d	2861	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto	148:fd96258d940d	2862	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	148:fd96258d940d	2863	SysTick_CTRL_TICKINT_Msk \|
Kojto	148:fd96258d940d	2864	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	148:fd96258d940d	2865	return (0UL); /* Function successful */
Kojto	148:fd96258d940d	2866	}
Kojto	148:fd96258d940d	2867	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	2868
Kojto	148:fd96258d940d	2869	#endif
Kojto	148:fd96258d940d	2870
Kojto	148:fd96258d940d	2871	/@} end of CMSIS_Core_SysTickFunctions /
Kojto	148:fd96258d940d	2872
Kojto	148:fd96258d940d	2873
Kojto	148:fd96258d940d	2874
Kojto	148:fd96258d940d	2875	/* ##################################### Debug In/Output function ########################################### */
Kojto	148:fd96258d940d	2876	/**
Kojto	148:fd96258d940d	2877	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	2878	\defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto	148:fd96258d940d	2879	\brief Functions that access the ITM debug interface.
Kojto	148:fd96258d940d	2880	@{
Kojto	148:fd96258d940d	2881	*/
Kojto	148:fd96258d940d	2882
Kojto	148:fd96258d940d	2883	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Kojto	148:fd96258d940d	2884	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Kojto	148:fd96258d940d	2885
Kojto	148:fd96258d940d	2886
Kojto	148:fd96258d940d	2887	/**
Kojto	148:fd96258d940d	2888	\brief ITM Send Character
Kojto	148:fd96258d940d	2889	\details Transmits a character via the ITM channel 0, and
Kojto	148:fd96258d940d	2890	\li Just returns when no debugger is connected that has booked the output.
Kojto	148:fd96258d940d	2891	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto	148:fd96258d940d	2892	\param [in] ch Character to transmit.
Kojto	148:fd96258d940d	2893	\returns Character to transmit.
Kojto	148:fd96258d940d	2894	*/
Kojto	148:fd96258d940d	2895	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto	148:fd96258d940d	2896	{
Kojto	148:fd96258d940d	2897	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto	148:fd96258d940d	2898	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto	148:fd96258d940d	2899	{
Kojto	148:fd96258d940d	2900	while (ITM->PORT[0U].u32 == 0UL)
Kojto	148:fd96258d940d	2901	{
Kojto	148:fd96258d940d	2902	__NOP();
Kojto	148:fd96258d940d	2903	}
Kojto	148:fd96258d940d	2904	ITM->PORT[0U].u8 = (uint8_t)ch;
Kojto	148:fd96258d940d	2905	}
Kojto	148:fd96258d940d	2906	return (ch);
Kojto	148:fd96258d940d	2907	}
Kojto	148:fd96258d940d	2908
Kojto	148:fd96258d940d	2909
Kojto	148:fd96258d940d	2910	/**
Kojto	148:fd96258d940d	2911	\brief ITM Receive Character
Kojto	148:fd96258d940d	2912	\details Inputs a character via the external variable \ref ITM_RxBuffer.
Kojto	148:fd96258d940d	2913	\return Received character.
Kojto	148:fd96258d940d	2914	\return -1 No character pending.
Kojto	148:fd96258d940d	2915	*/
Kojto	148:fd96258d940d	2916	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
Kojto	148:fd96258d940d	2917	{
Kojto	148:fd96258d940d	2918	int32_t ch = -1; /* no character available */
Kojto	148:fd96258d940d	2919
Kojto	148:fd96258d940d	2920	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
Kojto	148:fd96258d940d	2921	{
Kojto	148:fd96258d940d	2922	ch = ITM_RxBuffer;
Kojto	148:fd96258d940d	2923	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto	148:fd96258d940d	2924	}
Kojto	148:fd96258d940d	2925
Kojto	148:fd96258d940d	2926	return (ch);
Kojto	148:fd96258d940d	2927	}
Kojto	148:fd96258d940d	2928
Kojto	148:fd96258d940d	2929
Kojto	148:fd96258d940d	2930	/**
Kojto	148:fd96258d940d	2931	\brief ITM Check Character
Kojto	148:fd96258d940d	2932	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto	148:fd96258d940d	2933	\return 0 No character available.
Kojto	148:fd96258d940d	2934	\return 1 Character available.
Kojto	148:fd96258d940d	2935	*/
Kojto	148:fd96258d940d	2936	__STATIC_INLINE int32_t ITM_CheckChar (void)
Kojto	148:fd96258d940d	2937	{
Kojto	148:fd96258d940d	2938
Kojto	148:fd96258d940d	2939	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
Kojto	148:fd96258d940d	2940	{
Kojto	148:fd96258d940d	2941	return (0); /* no character available */
Kojto	148:fd96258d940d	2942	}
Kojto	148:fd96258d940d	2943	else
Kojto	148:fd96258d940d	2944	{
Kojto	148:fd96258d940d	2945	return (1); /* character available */
Kojto	148:fd96258d940d	2946	}
Kojto	148:fd96258d940d	2947	}
Kojto	148:fd96258d940d	2948
Kojto	148:fd96258d940d	2949	/@} end of CMSIS_core_DebugFunctions /
Kojto	148:fd96258d940d	2950
Kojto	148:fd96258d940d	2951
Kojto	148:fd96258d940d	2952
Kojto	148:fd96258d940d	2953
Kojto	148:fd96258d940d	2954	#ifdef __cplusplus
Kojto	148:fd96258d940d	2955	}
Kojto	148:fd96258d940d	2956	#endif
Kojto	148:fd96258d940d	2957
Kojto	148:fd96258d940d	2958	#endif /* __CORE_ARMV8MML_H_DEPENDANT */
Kojto	148:fd96258d940d	2959
Kojto	148:fd96258d940d	2960	#endif /* __CMSIS_GENERIC */