mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_VBLUNO52/core_armv8mbl.h@160:5571c4ff569f, 2018-01-17 (annotated)

Committer:: Anna Bridge
Date:: Wed Jan 17 16:13:02 2018 +0000
Revision:: 160:5571c4ff569f
Parent:: 148:fd96258d940d

mbed library. Release version 158

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	148:fd96258d940d	1	/************************************************************************//
Kojto	148:fd96258d940d	2	* @file core_armv8mbl.h
Kojto	148:fd96258d940d	3	* @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File
Anna Bridge	160:5571c4ff569f	4	* @version V5.0.3
Anna Bridge	160:5571c4ff569f	5	* @date 09. August 2017
Kojto	148:fd96258d940d	6	******************************************************************************/
Kojto	148:fd96258d940d	7	/*
Kojto	148:fd96258d940d	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
Kojto	148:fd96258d940d	9	*
Kojto	148:fd96258d940d	10	* SPDX-License-Identifier: Apache-2.0
Kojto	148:fd96258d940d	11	*
Kojto	148:fd96258d940d	12	* Licensed under the Apache License, Version 2.0 (the License); you may
Kojto	148:fd96258d940d	13	* not use this file except in compliance with the License.
Kojto	148:fd96258d940d	14	* You may obtain a copy of the License at
Kojto	148:fd96258d940d	15	*
Kojto	148:fd96258d940d	16	* www.apache.org/licenses/LICENSE-2.0
Kojto	148:fd96258d940d	17	*
Kojto	148:fd96258d940d	18	* Unless required by applicable law or agreed to in writing, software
Kojto	148:fd96258d940d	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
Kojto	148:fd96258d940d	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto	148:fd96258d940d	21	* See the License for the specific language governing permissions and
Kojto	148:fd96258d940d	22	* limitations under the License.
Kojto	148:fd96258d940d	23	*/
Kojto	148:fd96258d940d	24
Kojto	148:fd96258d940d	25	#if defined ( __ICCARM__ )
Kojto	148:fd96258d940d	26	#pragma system_include /* treat file as system include file for MISRA check */
Kojto	148:fd96258d940d	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Kojto	148:fd96258d940d	28	#pragma clang system_header /* treat file as system include file */
Kojto	148:fd96258d940d	29	#endif
Kojto	148:fd96258d940d	30
Kojto	148:fd96258d940d	31	#ifndef __CORE_ARMV8MBL_H_GENERIC
Kojto	148:fd96258d940d	32	#define __CORE_ARMV8MBL_H_GENERIC
Kojto	148:fd96258d940d	33
Kojto	148:fd96258d940d	34	#include <stdint.h>
Kojto	148:fd96258d940d	35
Kojto	148:fd96258d940d	36	#ifdef __cplusplus
Kojto	148:fd96258d940d	37	extern "C" {
Kojto	148:fd96258d940d	38	#endif
Kojto	148:fd96258d940d	39
Kojto	148:fd96258d940d	40	/**
Kojto	148:fd96258d940d	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto	148:fd96258d940d	42	CMSIS violates the following MISRA-C:2004 rules:
Kojto	148:fd96258d940d	43
Kojto	148:fd96258d940d	44	\li Required Rule 8.5, object/function definition in header file.<br>
Kojto	148:fd96258d940d	45	Function definitions in header files are used to allow 'inlining'.
Kojto	148:fd96258d940d	46
Kojto	148:fd96258d940d	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto	148:fd96258d940d	48	Unions are used for effective representation of core registers.
Kojto	148:fd96258d940d	49
Kojto	148:fd96258d940d	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto	148:fd96258d940d	51	Function-like macros are used to allow more efficient code.
Kojto	148:fd96258d940d	52	*/
Kojto	148:fd96258d940d	53
Kojto	148:fd96258d940d	54
Kojto	148:fd96258d940d	55	/*******************************************************************************
Kojto	148:fd96258d940d	56	* CMSIS definitions
Kojto	148:fd96258d940d	57	******************************************************************************/
Kojto	148:fd96258d940d	58	/**
Kojto	148:fd96258d940d	59	\ingroup Cortex_ARMv8MBL
Kojto	148:fd96258d940d	60	@{
Kojto	148:fd96258d940d	61	*/
Anna Bridge	160:5571c4ff569f	62
Anna Bridge	160:5571c4ff569f	63	#include "cmsis_version.h"
Kojto	148:fd96258d940d	64
Anna Bridge	160:5571c4ff569f	65	/* CMSIS definitions */
Anna Bridge	160:5571c4ff569f	66	#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	160:5571c4ff569f	67	#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
Kojto	148:fd96258d940d	68	#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	160:5571c4ff569f	69	__ARMv8MBL_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
Kojto	148:fd96258d940d	70
Kojto	148:fd96258d940d	71	#define __CORTEX_M ( 2U) /!< Cortex-M Core /
Kojto	148:fd96258d940d	72
Kojto	148:fd96258d940d	73	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	148:fd96258d940d	74	This core does not support an FPU at all
Kojto	148:fd96258d940d	75	*/
Kojto	148:fd96258d940d	76	#define __FPU_USED 0U
Kojto	148:fd96258d940d	77
Kojto	148:fd96258d940d	78	#if defined ( __CC_ARM )
Kojto	148:fd96258d940d	79	#if defined __TARGET_FPU_VFP
Kojto	148:fd96258d940d	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	81	#endif
Kojto	148:fd96258d940d	82
Kojto	148:fd96258d940d	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Kojto	148:fd96258d940d	84	#if defined __ARM_PCS_VFP
Kojto	148:fd96258d940d	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	86	#endif
Kojto	148:fd96258d940d	87
Kojto	148:fd96258d940d	88	#elif defined ( __GNUC__ )
Kojto	148:fd96258d940d	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	148:fd96258d940d	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	91	#endif
Kojto	148:fd96258d940d	92
Kojto	148:fd96258d940d	93	#elif defined ( __ICCARM__ )
Kojto	148:fd96258d940d	94	#if defined __ARMVFP__
Kojto	148:fd96258d940d	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	96	#endif
Kojto	148:fd96258d940d	97
Kojto	148:fd96258d940d	98	#elif defined ( __TI_ARM__ )
Kojto	148:fd96258d940d	99	#if defined __TI_VFP_SUPPORT__
Kojto	148:fd96258d940d	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	101	#endif
Kojto	148:fd96258d940d	102
Kojto	148:fd96258d940d	103	#elif defined ( __TASKING__ )
Kojto	148:fd96258d940d	104	#if defined __FPU_VFP__
Kojto	148:fd96258d940d	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	106	#endif
Kojto	148:fd96258d940d	107
Kojto	148:fd96258d940d	108	#elif defined ( __CSMC__ )
Kojto	148:fd96258d940d	109	#if ( __CSMC__ & 0x400U)
Kojto	148:fd96258d940d	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	148:fd96258d940d	111	#endif
Kojto	148:fd96258d940d	112
Kojto	148:fd96258d940d	113	#endif
Kojto	148:fd96258d940d	114
Kojto	148:fd96258d940d	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Kojto	148:fd96258d940d	116
Kojto	148:fd96258d940d	117
Kojto	148:fd96258d940d	118	#ifdef __cplusplus
Kojto	148:fd96258d940d	119	}
Kojto	148:fd96258d940d	120	#endif
Kojto	148:fd96258d940d	121
Kojto	148:fd96258d940d	122	#endif /* __CORE_ARMV8MBL_H_GENERIC */
Kojto	148:fd96258d940d	123
Kojto	148:fd96258d940d	124	#ifndef __CMSIS_GENERIC
Kojto	148:fd96258d940d	125
Kojto	148:fd96258d940d	126	#ifndef __CORE_ARMV8MBL_H_DEPENDANT
Kojto	148:fd96258d940d	127	#define __CORE_ARMV8MBL_H_DEPENDANT
Kojto	148:fd96258d940d	128
Kojto	148:fd96258d940d	129	#ifdef __cplusplus
Kojto	148:fd96258d940d	130	extern "C" {
Kojto	148:fd96258d940d	131	#endif
Kojto	148:fd96258d940d	132
Kojto	148:fd96258d940d	133	/* check device defines and use defaults */
Kojto	148:fd96258d940d	134	#if defined __CHECK_DEVICE_DEFINES
Kojto	148:fd96258d940d	135	#ifndef __ARMv8MBL_REV
Kojto	148:fd96258d940d	136	#define __ARMv8MBL_REV 0x0000U
Kojto	148:fd96258d940d	137	#warning "__ARMv8MBL_REV not defined in device header file; using default!"
Kojto	148:fd96258d940d	138	#endif
Kojto	148:fd96258d940d	139
Kojto	148:fd96258d940d	140	#ifndef __FPU_PRESENT
Kojto	148:fd96258d940d	141	#define __FPU_PRESENT 0U
Kojto	148:fd96258d940d	142	#warning "__FPU_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	143	#endif
Kojto	148:fd96258d940d	144
Kojto	148:fd96258d940d	145	#ifndef __MPU_PRESENT
Kojto	148:fd96258d940d	146	#define __MPU_PRESENT 0U
Kojto	148:fd96258d940d	147	#warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	148	#endif
Kojto	148:fd96258d940d	149
Kojto	148:fd96258d940d	150	#ifndef __SAUREGION_PRESENT
Kojto	148:fd96258d940d	151	#define __SAUREGION_PRESENT 0U
Kojto	148:fd96258d940d	152	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	153	#endif
Kojto	148:fd96258d940d	154
Kojto	148:fd96258d940d	155	#ifndef __VTOR_PRESENT
Kojto	148:fd96258d940d	156	#define __VTOR_PRESENT 0U
Kojto	148:fd96258d940d	157	#warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	158	#endif
Kojto	148:fd96258d940d	159
Kojto	148:fd96258d940d	160	#ifndef __NVIC_PRIO_BITS
Kojto	148:fd96258d940d	161	#define __NVIC_PRIO_BITS 2U
Kojto	148:fd96258d940d	162	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto	148:fd96258d940d	163	#endif
Kojto	148:fd96258d940d	164
Kojto	148:fd96258d940d	165	#ifndef __Vendor_SysTickConfig
Kojto	148:fd96258d940d	166	#define __Vendor_SysTickConfig 0U
Kojto	148:fd96258d940d	167	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto	148:fd96258d940d	168	#endif
Kojto	148:fd96258d940d	169
Kojto	148:fd96258d940d	170	#ifndef __ETM_PRESENT
Kojto	148:fd96258d940d	171	#define __ETM_PRESENT 0U
Kojto	148:fd96258d940d	172	#warning "__ETM_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	173	#endif
Kojto	148:fd96258d940d	174
Kojto	148:fd96258d940d	175	#ifndef __MTB_PRESENT
Kojto	148:fd96258d940d	176	#define __MTB_PRESENT 0U
Kojto	148:fd96258d940d	177	#warning "__MTB_PRESENT not defined in device header file; using default!"
Kojto	148:fd96258d940d	178	#endif
Kojto	148:fd96258d940d	179
Kojto	148:fd96258d940d	180	#endif
Kojto	148:fd96258d940d	181
Kojto	148:fd96258d940d	182	/* IO definitions (access restrictions to peripheral registers) */
Kojto	148:fd96258d940d	183	/**
Kojto	148:fd96258d940d	184	\defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto	148:fd96258d940d	185
Kojto	148:fd96258d940d	186	<strong>IO Type Qualifiers</strong> are used
Kojto	148:fd96258d940d	187	\li to specify the access to peripheral variables.
Kojto	148:fd96258d940d	188	\li for automatic generation of peripheral register debug information.
Kojto	148:fd96258d940d	189	*/
Kojto	148:fd96258d940d	190	#ifdef __cplusplus
Kojto	148:fd96258d940d	191	#define __I volatile /!< Defines 'read only' permissions /
Kojto	148:fd96258d940d	192	#else
Kojto	148:fd96258d940d	193	#define __I volatile const /!< Defines 'read only' permissions /
Kojto	148:fd96258d940d	194	#endif
Kojto	148:fd96258d940d	195	#define __O volatile /!< Defines 'write only' permissions /
Kojto	148:fd96258d940d	196	#define __IO volatile /!< Defines 'read / write' permissions /
Kojto	148:fd96258d940d	197
Kojto	148:fd96258d940d	198	/* following defines should be used for structure members */
Kojto	148:fd96258d940d	199	#define __IM volatile const /! Defines 'read only' structure member permissions /
Kojto	148:fd96258d940d	200	#define __OM volatile /! Defines 'write only' structure member permissions /
Kojto	148:fd96258d940d	201	#define __IOM volatile /! Defines 'read / write' structure member permissions /
Kojto	148:fd96258d940d	202
Kojto	148:fd96258d940d	203	/@} end of group ARMv8MBL /
Kojto	148:fd96258d940d	204
Kojto	148:fd96258d940d	205
Kojto	148:fd96258d940d	206
Kojto	148:fd96258d940d	207	/*******************************************************************************
Kojto	148:fd96258d940d	208	* Register Abstraction
Kojto	148:fd96258d940d	209	Core Register contain:
Kojto	148:fd96258d940d	210	- Core Register
Kojto	148:fd96258d940d	211	- Core NVIC Register
Kojto	148:fd96258d940d	212	- Core SCB Register
Kojto	148:fd96258d940d	213	- Core SysTick Register
Kojto	148:fd96258d940d	214	- Core Debug Register
Kojto	148:fd96258d940d	215	- Core MPU Register
Kojto	148:fd96258d940d	216	- Core SAU Register
Kojto	148:fd96258d940d	217	******************************************************************************/
Kojto	148:fd96258d940d	218	/**
Kojto	148:fd96258d940d	219	\defgroup CMSIS_core_register Defines and Type Definitions
Kojto	148:fd96258d940d	220	\brief Type definitions and defines for Cortex-M processor based devices.
Kojto	148:fd96258d940d	221	*/
Kojto	148:fd96258d940d	222
Kojto	148:fd96258d940d	223	/**
Kojto	148:fd96258d940d	224	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	225	\defgroup CMSIS_CORE Status and Control Registers
Kojto	148:fd96258d940d	226	\brief Core Register type definitions.
Kojto	148:fd96258d940d	227	@{
Kojto	148:fd96258d940d	228	*/
Kojto	148:fd96258d940d	229
Kojto	148:fd96258d940d	230	/**
Kojto	148:fd96258d940d	231	\brief Union type to access the Application Program Status Register (APSR).
Kojto	148:fd96258d940d	232	*/
Kojto	148:fd96258d940d	233	typedef union
Kojto	148:fd96258d940d	234	{
Kojto	148:fd96258d940d	235	struct
Kojto	148:fd96258d940d	236	{
Kojto	148:fd96258d940d	237	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
Kojto	148:fd96258d940d	238	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	148:fd96258d940d	239	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	148:fd96258d940d	240	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	148:fd96258d940d	241	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	148:fd96258d940d	242	} b; /!< Structure used for bit access /
Kojto	148:fd96258d940d	243	uint32_t w; /!< Type used for word access /
Kojto	148:fd96258d940d	244	} APSR_Type;
Kojto	148:fd96258d940d	245
Kojto	148:fd96258d940d	246	/* APSR Register Definitions */
Kojto	148:fd96258d940d	247	#define APSR_N_Pos 31U /!< APSR: N Position /
Kojto	148:fd96258d940d	248	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	148:fd96258d940d	249
Kojto	148:fd96258d940d	250	#define APSR_Z_Pos 30U /!< APSR: Z Position /
Kojto	148:fd96258d940d	251	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	148:fd96258d940d	252
Kojto	148:fd96258d940d	253	#define APSR_C_Pos 29U /!< APSR: C Position /
Kojto	148:fd96258d940d	254	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	148:fd96258d940d	255
Kojto	148:fd96258d940d	256	#define APSR_V_Pos 28U /!< APSR: V Position /
Kojto	148:fd96258d940d	257	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	148:fd96258d940d	258
Kojto	148:fd96258d940d	259
Kojto	148:fd96258d940d	260	/**
Kojto	148:fd96258d940d	261	\brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto	148:fd96258d940d	262	*/
Kojto	148:fd96258d940d	263	typedef union
Kojto	148:fd96258d940d	264	{
Kojto	148:fd96258d940d	265	struct
Kojto	148:fd96258d940d	266	{
Kojto	148:fd96258d940d	267	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	148:fd96258d940d	268	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Kojto	148:fd96258d940d	269	} b; /!< Structure used for bit access /
Kojto	148:fd96258d940d	270	uint32_t w; /!< Type used for word access /
Kojto	148:fd96258d940d	271	} IPSR_Type;
Kojto	148:fd96258d940d	272
Kojto	148:fd96258d940d	273	/* IPSR Register Definitions */
Kojto	148:fd96258d940d	274	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
Kojto	148:fd96258d940d	275	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	148:fd96258d940d	276
Kojto	148:fd96258d940d	277
Kojto	148:fd96258d940d	278	/**
Kojto	148:fd96258d940d	279	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto	148:fd96258d940d	280	*/
Kojto	148:fd96258d940d	281	typedef union
Kojto	148:fd96258d940d	282	{
Kojto	148:fd96258d940d	283	struct
Kojto	148:fd96258d940d	284	{
Kojto	148:fd96258d940d	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	148:fd96258d940d	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
Kojto	148:fd96258d940d	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Kojto	148:fd96258d940d	288	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
Kojto	148:fd96258d940d	289	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	148:fd96258d940d	290	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	148:fd96258d940d	291	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	148:fd96258d940d	292	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	148:fd96258d940d	293	} b; /!< Structure used for bit access /
Kojto	148:fd96258d940d	294	uint32_t w; /!< Type used for word access /
Kojto	148:fd96258d940d	295	} xPSR_Type;
Kojto	148:fd96258d940d	296
Kojto	148:fd96258d940d	297	/* xPSR Register Definitions */
Kojto	148:fd96258d940d	298	#define xPSR_N_Pos 31U /!< xPSR: N Position /
Kojto	148:fd96258d940d	299	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	148:fd96258d940d	300
Kojto	148:fd96258d940d	301	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
Kojto	148:fd96258d940d	302	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	148:fd96258d940d	303
Kojto	148:fd96258d940d	304	#define xPSR_C_Pos 29U /!< xPSR: C Position /
Kojto	148:fd96258d940d	305	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	148:fd96258d940d	306
Kojto	148:fd96258d940d	307	#define xPSR_V_Pos 28U /!< xPSR: V Position /
Kojto	148:fd96258d940d	308	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	148:fd96258d940d	309
Kojto	148:fd96258d940d	310	#define xPSR_T_Pos 24U /!< xPSR: T Position /
Kojto	148:fd96258d940d	311	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	148:fd96258d940d	312
Kojto	148:fd96258d940d	313	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
Kojto	148:fd96258d940d	314	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	148:fd96258d940d	315
Kojto	148:fd96258d940d	316
Kojto	148:fd96258d940d	317	/**
Kojto	148:fd96258d940d	318	\brief Union type to access the Control Registers (CONTROL).
Kojto	148:fd96258d940d	319	*/
Kojto	148:fd96258d940d	320	typedef union
Kojto	148:fd96258d940d	321	{
Kojto	148:fd96258d940d	322	struct
Kojto	148:fd96258d940d	323	{
Kojto	148:fd96258d940d	324	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Kojto	148:fd96258d940d	325	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
Kojto	148:fd96258d940d	326	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
Kojto	148:fd96258d940d	327	} b; /!< Structure used for bit access /
Kojto	148:fd96258d940d	328	uint32_t w; /!< Type used for word access /
Kojto	148:fd96258d940d	329	} CONTROL_Type;
Kojto	148:fd96258d940d	330
Kojto	148:fd96258d940d	331	/* CONTROL Register Definitions */
Kojto	148:fd96258d940d	332	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
Kojto	148:fd96258d940d	333	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	148:fd96258d940d	334
Kojto	148:fd96258d940d	335	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
Kojto	148:fd96258d940d	336	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	148:fd96258d940d	337
Kojto	148:fd96258d940d	338	/@} end of group CMSIS_CORE /
Kojto	148:fd96258d940d	339
Kojto	148:fd96258d940d	340
Kojto	148:fd96258d940d	341	/**
Kojto	148:fd96258d940d	342	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	343	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto	148:fd96258d940d	344	\brief Type definitions for the NVIC Registers
Kojto	148:fd96258d940d	345	@{
Kojto	148:fd96258d940d	346	*/
Kojto	148:fd96258d940d	347
Kojto	148:fd96258d940d	348	/**
Kojto	148:fd96258d940d	349	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto	148:fd96258d940d	350	*/
Kojto	148:fd96258d940d	351	typedef struct
Kojto	148:fd96258d940d	352	{
Kojto	148:fd96258d940d	353	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Kojto	148:fd96258d940d	354	uint32_t RESERVED0[16U];
Kojto	148:fd96258d940d	355	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Kojto	148:fd96258d940d	356	uint32_t RSERVED1[16U];
Kojto	148:fd96258d940d	357	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Kojto	148:fd96258d940d	358	uint32_t RESERVED2[16U];
Kojto	148:fd96258d940d	359	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Kojto	148:fd96258d940d	360	uint32_t RESERVED3[16U];
Kojto	148:fd96258d940d	361	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Kojto	148:fd96258d940d	362	uint32_t RESERVED4[16U];
Kojto	148:fd96258d940d	363	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
Kojto	148:fd96258d940d	364	uint32_t RESERVED5[16U];
Kojto	148:fd96258d940d	365	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
Kojto	148:fd96258d940d	366	} NVIC_Type;
Kojto	148:fd96258d940d	367
Kojto	148:fd96258d940d	368	/@} end of group CMSIS_NVIC /
Kojto	148:fd96258d940d	369
Kojto	148:fd96258d940d	370
Kojto	148:fd96258d940d	371	/**
Kojto	148:fd96258d940d	372	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	373	\defgroup CMSIS_SCB System Control Block (SCB)
Kojto	148:fd96258d940d	374	\brief Type definitions for the System Control Block Registers
Kojto	148:fd96258d940d	375	@{
Kojto	148:fd96258d940d	376	*/
Kojto	148:fd96258d940d	377
Kojto	148:fd96258d940d	378	/**
Kojto	148:fd96258d940d	379	\brief Structure type to access the System Control Block (SCB).
Kojto	148:fd96258d940d	380	*/
Kojto	148:fd96258d940d	381	typedef struct
Kojto	148:fd96258d940d	382	{
Kojto	148:fd96258d940d	383	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Kojto	148:fd96258d940d	384	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Kojto	148:fd96258d940d	385	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Kojto	148:fd96258d940d	386	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Kojto	148:fd96258d940d	387	#else
Kojto	148:fd96258d940d	388	uint32_t RESERVED0;
Kojto	148:fd96258d940d	389	#endif
Kojto	148:fd96258d940d	390	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Kojto	148:fd96258d940d	391	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Kojto	148:fd96258d940d	392	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Kojto	148:fd96258d940d	393	uint32_t RESERVED1;
Kojto	148:fd96258d940d	394	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
Kojto	148:fd96258d940d	395	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Kojto	148:fd96258d940d	396	} SCB_Type;
Kojto	148:fd96258d940d	397
Kojto	148:fd96258d940d	398	/* SCB CPUID Register Definitions */
Kojto	148:fd96258d940d	399	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
Kojto	148:fd96258d940d	400	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Kojto	148:fd96258d940d	401
Kojto	148:fd96258d940d	402	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
Kojto	148:fd96258d940d	403	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Kojto	148:fd96258d940d	404
Kojto	148:fd96258d940d	405	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
Kojto	148:fd96258d940d	406	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Kojto	148:fd96258d940d	407
Kojto	148:fd96258d940d	408	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
Kojto	148:fd96258d940d	409	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Kojto	148:fd96258d940d	410
Kojto	148:fd96258d940d	411	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
Kojto	148:fd96258d940d	412	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Kojto	148:fd96258d940d	413
Kojto	148:fd96258d940d	414	/* SCB Interrupt Control State Register Definitions */
Kojto	148:fd96258d940d	415	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
Kojto	148:fd96258d940d	416	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
Kojto	148:fd96258d940d	417
Kojto	148:fd96258d940d	418	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
Kojto	148:fd96258d940d	419	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
Kojto	148:fd96258d940d	420
Kojto	148:fd96258d940d	421	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
Kojto	148:fd96258d940d	422	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Kojto	148:fd96258d940d	423
Kojto	148:fd96258d940d	424	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
Kojto	148:fd96258d940d	425	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Kojto	148:fd96258d940d	426
Kojto	148:fd96258d940d	427	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
Kojto	148:fd96258d940d	428	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Kojto	148:fd96258d940d	429
Kojto	148:fd96258d940d	430	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
Kojto	148:fd96258d940d	431	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Kojto	148:fd96258d940d	432
Kojto	148:fd96258d940d	433	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
Kojto	148:fd96258d940d	434	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
Kojto	148:fd96258d940d	435
Kojto	148:fd96258d940d	436	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
Kojto	148:fd96258d940d	437	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Kojto	148:fd96258d940d	438
Kojto	148:fd96258d940d	439	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
Kojto	148:fd96258d940d	440	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Kojto	148:fd96258d940d	441
Kojto	148:fd96258d940d	442	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
Kojto	148:fd96258d940d	443	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Kojto	148:fd96258d940d	444
Kojto	148:fd96258d940d	445	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
Kojto	148:fd96258d940d	446	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Kojto	148:fd96258d940d	447
Kojto	148:fd96258d940d	448	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
Kojto	148:fd96258d940d	449	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Kojto	148:fd96258d940d	450
Kojto	148:fd96258d940d	451	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Kojto	148:fd96258d940d	452	/* SCB Vector Table Offset Register Definitions */
Kojto	148:fd96258d940d	453	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
Kojto	148:fd96258d940d	454	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	148:fd96258d940d	455	#endif
Kojto	148:fd96258d940d	456
Kojto	148:fd96258d940d	457	/* SCB Application Interrupt and Reset Control Register Definitions */
Kojto	148:fd96258d940d	458	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
Kojto	148:fd96258d940d	459	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Kojto	148:fd96258d940d	460
Kojto	148:fd96258d940d	461	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
Kojto	148:fd96258d940d	462	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Kojto	148:fd96258d940d	463
Kojto	148:fd96258d940d	464	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
Kojto	148:fd96258d940d	465	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Kojto	148:fd96258d940d	466
Kojto	148:fd96258d940d	467	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
Kojto	148:fd96258d940d	468	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
Kojto	148:fd96258d940d	469
Kojto	148:fd96258d940d	470	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
Kojto	148:fd96258d940d	471	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
Kojto	148:fd96258d940d	472
Kojto	148:fd96258d940d	473	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
Kojto	148:fd96258d940d	474	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
Kojto	148:fd96258d940d	475
Kojto	148:fd96258d940d	476	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
Kojto	148:fd96258d940d	477	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Kojto	148:fd96258d940d	478
Kojto	148:fd96258d940d	479	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
Kojto	148:fd96258d940d	480	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Kojto	148:fd96258d940d	481
Kojto	148:fd96258d940d	482	/* SCB System Control Register Definitions */
Kojto	148:fd96258d940d	483	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
Kojto	148:fd96258d940d	484	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Kojto	148:fd96258d940d	485
Kojto	148:fd96258d940d	486	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
Kojto	148:fd96258d940d	487	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
Kojto	148:fd96258d940d	488
Kojto	148:fd96258d940d	489	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
Kojto	148:fd96258d940d	490	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Kojto	148:fd96258d940d	491
Kojto	148:fd96258d940d	492	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
Kojto	148:fd96258d940d	493	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Kojto	148:fd96258d940d	494
Kojto	148:fd96258d940d	495	/* SCB Configuration Control Register Definitions */
Kojto	148:fd96258d940d	496	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
Kojto	148:fd96258d940d	497	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
Kojto	148:fd96258d940d	498
Kojto	148:fd96258d940d	499	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
Kojto	148:fd96258d940d	500	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
Kojto	148:fd96258d940d	501
Kojto	148:fd96258d940d	502	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
Kojto	148:fd96258d940d	503	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
Kojto	148:fd96258d940d	504
Kojto	148:fd96258d940d	505	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
Kojto	148:fd96258d940d	506	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
Kojto	148:fd96258d940d	507
Kojto	148:fd96258d940d	508	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
Kojto	148:fd96258d940d	509	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Kojto	148:fd96258d940d	510
Kojto	148:fd96258d940d	511	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
Kojto	148:fd96258d940d	512	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Kojto	148:fd96258d940d	513
Kojto	148:fd96258d940d	514	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
Kojto	148:fd96258d940d	515	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Kojto	148:fd96258d940d	516
Kojto	148:fd96258d940d	517	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
Kojto	148:fd96258d940d	518	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Kojto	148:fd96258d940d	519
Kojto	148:fd96258d940d	520	/* SCB System Handler Control and State Register Definitions */
Kojto	148:fd96258d940d	521	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
Kojto	148:fd96258d940d	522	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
Kojto	148:fd96258d940d	523
Kojto	148:fd96258d940d	524	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
Kojto	148:fd96258d940d	525	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Kojto	148:fd96258d940d	526
Kojto	148:fd96258d940d	527	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
Kojto	148:fd96258d940d	528	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Kojto	148:fd96258d940d	529
Kojto	148:fd96258d940d	530	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
Kojto	148:fd96258d940d	531	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Kojto	148:fd96258d940d	532
Kojto	148:fd96258d940d	533	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
Kojto	148:fd96258d940d	534	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Kojto	148:fd96258d940d	535
Kojto	148:fd96258d940d	536	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
Kojto	148:fd96258d940d	537	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
Kojto	148:fd96258d940d	538
Kojto	148:fd96258d940d	539	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
Kojto	148:fd96258d940d	540	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
Kojto	148:fd96258d940d	541
Kojto	148:fd96258d940d	542	/@} end of group CMSIS_SCB /
Kojto	148:fd96258d940d	543
Kojto	148:fd96258d940d	544
Kojto	148:fd96258d940d	545	/**
Kojto	148:fd96258d940d	546	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	547	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto	148:fd96258d940d	548	\brief Type definitions for the System Timer Registers.
Kojto	148:fd96258d940d	549	@{
Kojto	148:fd96258d940d	550	*/
Kojto	148:fd96258d940d	551
Kojto	148:fd96258d940d	552	/**
Kojto	148:fd96258d940d	553	\brief Structure type to access the System Timer (SysTick).
Kojto	148:fd96258d940d	554	*/
Kojto	148:fd96258d940d	555	typedef struct
Kojto	148:fd96258d940d	556	{
Kojto	148:fd96258d940d	557	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Kojto	148:fd96258d940d	558	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Kojto	148:fd96258d940d	559	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Kojto	148:fd96258d940d	560	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Kojto	148:fd96258d940d	561	} SysTick_Type;
Kojto	148:fd96258d940d	562
Kojto	148:fd96258d940d	563	/* SysTick Control / Status Register Definitions */
Kojto	148:fd96258d940d	564	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
Kojto	148:fd96258d940d	565	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Kojto	148:fd96258d940d	566
Kojto	148:fd96258d940d	567	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
Kojto	148:fd96258d940d	568	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Kojto	148:fd96258d940d	569
Kojto	148:fd96258d940d	570	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
Kojto	148:fd96258d940d	571	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Kojto	148:fd96258d940d	572
Kojto	148:fd96258d940d	573	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
Kojto	148:fd96258d940d	574	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Kojto	148:fd96258d940d	575
Kojto	148:fd96258d940d	576	/* SysTick Reload Register Definitions */
Kojto	148:fd96258d940d	577	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
Kojto	148:fd96258d940d	578	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Kojto	148:fd96258d940d	579
Kojto	148:fd96258d940d	580	/* SysTick Current Register Definitions */
Kojto	148:fd96258d940d	581	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
Kojto	148:fd96258d940d	582	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Kojto	148:fd96258d940d	583
Kojto	148:fd96258d940d	584	/* SysTick Calibration Register Definitions */
Kojto	148:fd96258d940d	585	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
Kojto	148:fd96258d940d	586	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Kojto	148:fd96258d940d	587
Kojto	148:fd96258d940d	588	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
Kojto	148:fd96258d940d	589	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Kojto	148:fd96258d940d	590
Kojto	148:fd96258d940d	591	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
Kojto	148:fd96258d940d	592	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Kojto	148:fd96258d940d	593
Kojto	148:fd96258d940d	594	/@} end of group CMSIS_SysTick /
Kojto	148:fd96258d940d	595
Kojto	148:fd96258d940d	596
Kojto	148:fd96258d940d	597	/**
Kojto	148:fd96258d940d	598	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	599	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto	148:fd96258d940d	600	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto	148:fd96258d940d	601	@{
Kojto	148:fd96258d940d	602	*/
Kojto	148:fd96258d940d	603
Kojto	148:fd96258d940d	604	/**
Kojto	148:fd96258d940d	605	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto	148:fd96258d940d	606	*/
Kojto	148:fd96258d940d	607	typedef struct
Kojto	148:fd96258d940d	608	{
Kojto	148:fd96258d940d	609	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Kojto	148:fd96258d940d	610	uint32_t RESERVED0[6U];
Kojto	148:fd96258d940d	611	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Kojto	148:fd96258d940d	612	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Kojto	148:fd96258d940d	613	uint32_t RESERVED1[1U];
Kojto	148:fd96258d940d	614	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Kojto	148:fd96258d940d	615	uint32_t RESERVED2[1U];
Kojto	148:fd96258d940d	616	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Kojto	148:fd96258d940d	617	uint32_t RESERVED3[1U];
Kojto	148:fd96258d940d	618	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Kojto	148:fd96258d940d	619	uint32_t RESERVED4[1U];
Kojto	148:fd96258d940d	620	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Kojto	148:fd96258d940d	621	uint32_t RESERVED5[1U];
Kojto	148:fd96258d940d	622	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Kojto	148:fd96258d940d	623	uint32_t RESERVED6[1U];
Kojto	148:fd96258d940d	624	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Kojto	148:fd96258d940d	625	uint32_t RESERVED7[1U];
Kojto	148:fd96258d940d	626	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Kojto	148:fd96258d940d	627	uint32_t RESERVED8[1U];
Kojto	148:fd96258d940d	628	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
Kojto	148:fd96258d940d	629	uint32_t RESERVED9[1U];
Kojto	148:fd96258d940d	630	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
Kojto	148:fd96258d940d	631	uint32_t RESERVED10[1U];
Kojto	148:fd96258d940d	632	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
Kojto	148:fd96258d940d	633	uint32_t RESERVED11[1U];
Kojto	148:fd96258d940d	634	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
Kojto	148:fd96258d940d	635	uint32_t RESERVED12[1U];
Kojto	148:fd96258d940d	636	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
Kojto	148:fd96258d940d	637	uint32_t RESERVED13[1U];
Kojto	148:fd96258d940d	638	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
Kojto	148:fd96258d940d	639	uint32_t RESERVED14[1U];
Kojto	148:fd96258d940d	640	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
Kojto	148:fd96258d940d	641	uint32_t RESERVED15[1U];
Kojto	148:fd96258d940d	642	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
Kojto	148:fd96258d940d	643	uint32_t RESERVED16[1U];
Kojto	148:fd96258d940d	644	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
Kojto	148:fd96258d940d	645	uint32_t RESERVED17[1U];
Kojto	148:fd96258d940d	646	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
Kojto	148:fd96258d940d	647	uint32_t RESERVED18[1U];
Kojto	148:fd96258d940d	648	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
Kojto	148:fd96258d940d	649	uint32_t RESERVED19[1U];
Kojto	148:fd96258d940d	650	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
Kojto	148:fd96258d940d	651	uint32_t RESERVED20[1U];
Kojto	148:fd96258d940d	652	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
Kojto	148:fd96258d940d	653	uint32_t RESERVED21[1U];
Kojto	148:fd96258d940d	654	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
Kojto	148:fd96258d940d	655	uint32_t RESERVED22[1U];
Kojto	148:fd96258d940d	656	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
Kojto	148:fd96258d940d	657	uint32_t RESERVED23[1U];
Kojto	148:fd96258d940d	658	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
Kojto	148:fd96258d940d	659	uint32_t RESERVED24[1U];
Kojto	148:fd96258d940d	660	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
Kojto	148:fd96258d940d	661	uint32_t RESERVED25[1U];
Kojto	148:fd96258d940d	662	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
Kojto	148:fd96258d940d	663	uint32_t RESERVED26[1U];
Kojto	148:fd96258d940d	664	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
Kojto	148:fd96258d940d	665	uint32_t RESERVED27[1U];
Kojto	148:fd96258d940d	666	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
Kojto	148:fd96258d940d	667	uint32_t RESERVED28[1U];
Kojto	148:fd96258d940d	668	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
Kojto	148:fd96258d940d	669	uint32_t RESERVED29[1U];
Kojto	148:fd96258d940d	670	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
Kojto	148:fd96258d940d	671	uint32_t RESERVED30[1U];
Kojto	148:fd96258d940d	672	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
Kojto	148:fd96258d940d	673	uint32_t RESERVED31[1U];
Kojto	148:fd96258d940d	674	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
Kojto	148:fd96258d940d	675	} DWT_Type;
Kojto	148:fd96258d940d	676
Kojto	148:fd96258d940d	677	/* DWT Control Register Definitions */
Kojto	148:fd96258d940d	678	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
Kojto	148:fd96258d940d	679	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Kojto	148:fd96258d940d	680
Kojto	148:fd96258d940d	681	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
Kojto	148:fd96258d940d	682	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Kojto	148:fd96258d940d	683
Kojto	148:fd96258d940d	684	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
Kojto	148:fd96258d940d	685	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Kojto	148:fd96258d940d	686
Kojto	148:fd96258d940d	687	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
Kojto	148:fd96258d940d	688	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Kojto	148:fd96258d940d	689
Kojto	148:fd96258d940d	690	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
Kojto	148:fd96258d940d	691	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Kojto	148:fd96258d940d	692
Kojto	148:fd96258d940d	693	/* DWT Comparator Function Register Definitions */
Kojto	148:fd96258d940d	694	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
Kojto	148:fd96258d940d	695	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
Kojto	148:fd96258d940d	696
Kojto	148:fd96258d940d	697	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
Kojto	148:fd96258d940d	698	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Kojto	148:fd96258d940d	699
Kojto	148:fd96258d940d	700	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
Kojto	148:fd96258d940d	701	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Kojto	148:fd96258d940d	702
Kojto	148:fd96258d940d	703	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
Kojto	148:fd96258d940d	704	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
Kojto	148:fd96258d940d	705
Kojto	148:fd96258d940d	706	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
Kojto	148:fd96258d940d	707	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
Kojto	148:fd96258d940d	708
Kojto	148:fd96258d940d	709	/@}/ /* end of group CMSIS_DWT */
Kojto	148:fd96258d940d	710
Kojto	148:fd96258d940d	711
Kojto	148:fd96258d940d	712	/**
Kojto	148:fd96258d940d	713	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	714	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto	148:fd96258d940d	715	\brief Type definitions for the Trace Port Interface (TPI)
Kojto	148:fd96258d940d	716	@{
Kojto	148:fd96258d940d	717	*/
Kojto	148:fd96258d940d	718
Kojto	148:fd96258d940d	719	/**
Kojto	148:fd96258d940d	720	\brief Structure type to access the Trace Port Interface Register (TPI).
Kojto	148:fd96258d940d	721	*/
Kojto	148:fd96258d940d	722	typedef struct
Kojto	148:fd96258d940d	723	{
Kojto	148:fd96258d940d	724	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Kojto	148:fd96258d940d	725	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Kojto	148:fd96258d940d	726	uint32_t RESERVED0[2U];
Kojto	148:fd96258d940d	727	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Kojto	148:fd96258d940d	728	uint32_t RESERVED1[55U];
Kojto	148:fd96258d940d	729	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Kojto	148:fd96258d940d	730	uint32_t RESERVED2[131U];
Kojto	148:fd96258d940d	731	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Kojto	148:fd96258d940d	732	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Kojto	148:fd96258d940d	733	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Kojto	148:fd96258d940d	734	uint32_t RESERVED3[759U];
Kojto	148:fd96258d940d	735	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Kojto	148:fd96258d940d	736	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Kojto	148:fd96258d940d	737	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Kojto	148:fd96258d940d	738	uint32_t RESERVED4[1U];
Kojto	148:fd96258d940d	739	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Kojto	148:fd96258d940d	740	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Kojto	148:fd96258d940d	741	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Kojto	148:fd96258d940d	742	uint32_t RESERVED5[39U];
Kojto	148:fd96258d940d	743	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Kojto	148:fd96258d940d	744	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Kojto	148:fd96258d940d	745	uint32_t RESERVED7[8U];
Kojto	148:fd96258d940d	746	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Kojto	148:fd96258d940d	747	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Kojto	148:fd96258d940d	748	} TPI_Type;
Kojto	148:fd96258d940d	749
Kojto	148:fd96258d940d	750	/* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto	148:fd96258d940d	751	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
Kojto	148:fd96258d940d	752	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Kojto	148:fd96258d940d	753
Kojto	148:fd96258d940d	754	/* TPI Selected Pin Protocol Register Definitions */
Kojto	148:fd96258d940d	755	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
Kojto	148:fd96258d940d	756	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Kojto	148:fd96258d940d	757
Kojto	148:fd96258d940d	758	/* TPI Formatter and Flush Status Register Definitions */
Kojto	148:fd96258d940d	759	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
Kojto	148:fd96258d940d	760	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Kojto	148:fd96258d940d	761
Kojto	148:fd96258d940d	762	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
Kojto	148:fd96258d940d	763	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Kojto	148:fd96258d940d	764
Kojto	148:fd96258d940d	765	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
Kojto	148:fd96258d940d	766	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Kojto	148:fd96258d940d	767
Kojto	148:fd96258d940d	768	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
Kojto	148:fd96258d940d	769	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Kojto	148:fd96258d940d	770
Kojto	148:fd96258d940d	771	/* TPI Formatter and Flush Control Register Definitions */
Kojto	148:fd96258d940d	772	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
Kojto	148:fd96258d940d	773	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Kojto	148:fd96258d940d	774
Kojto	148:fd96258d940d	775	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
Kojto	148:fd96258d940d	776	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Kojto	148:fd96258d940d	777
Kojto	148:fd96258d940d	778	/* TPI TRIGGER Register Definitions */
Kojto	148:fd96258d940d	779	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
Kojto	148:fd96258d940d	780	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Kojto	148:fd96258d940d	781
Kojto	148:fd96258d940d	782	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto	148:fd96258d940d	783	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
Kojto	148:fd96258d940d	784	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Kojto	148:fd96258d940d	785
Kojto	148:fd96258d940d	786	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
Kojto	148:fd96258d940d	787	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Kojto	148:fd96258d940d	788
Kojto	148:fd96258d940d	789	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
Kojto	148:fd96258d940d	790	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Kojto	148:fd96258d940d	791
Kojto	148:fd96258d940d	792	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
Kojto	148:fd96258d940d	793	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Kojto	148:fd96258d940d	794
Kojto	148:fd96258d940d	795	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
Kojto	148:fd96258d940d	796	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Kojto	148:fd96258d940d	797
Kojto	148:fd96258d940d	798	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
Kojto	148:fd96258d940d	799	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Kojto	148:fd96258d940d	800
Kojto	148:fd96258d940d	801	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
Kojto	148:fd96258d940d	802	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Kojto	148:fd96258d940d	803
Kojto	148:fd96258d940d	804	/* TPI ITATBCTR2 Register Definitions */
Kojto	148:fd96258d940d	805	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
Kojto	148:fd96258d940d	806	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Kojto	148:fd96258d940d	807
Kojto	148:fd96258d940d	808	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto	148:fd96258d940d	809	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
Kojto	148:fd96258d940d	810	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Kojto	148:fd96258d940d	811
Kojto	148:fd96258d940d	812	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
Kojto	148:fd96258d940d	813	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Kojto	148:fd96258d940d	814
Kojto	148:fd96258d940d	815	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
Kojto	148:fd96258d940d	816	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Kojto	148:fd96258d940d	817
Kojto	148:fd96258d940d	818	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
Kojto	148:fd96258d940d	819	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Kojto	148:fd96258d940d	820
Kojto	148:fd96258d940d	821	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
Kojto	148:fd96258d940d	822	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Kojto	148:fd96258d940d	823
Kojto	148:fd96258d940d	824	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
Kojto	148:fd96258d940d	825	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Kojto	148:fd96258d940d	826
Kojto	148:fd96258d940d	827	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
Kojto	148:fd96258d940d	828	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Kojto	148:fd96258d940d	829
Kojto	148:fd96258d940d	830	/* TPI ITATBCTR0 Register Definitions */
Kojto	148:fd96258d940d	831	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
Kojto	148:fd96258d940d	832	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Kojto	148:fd96258d940d	833
Kojto	148:fd96258d940d	834	/* TPI Integration Mode Control Register Definitions */
Kojto	148:fd96258d940d	835	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
Kojto	148:fd96258d940d	836	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Kojto	148:fd96258d940d	837
Kojto	148:fd96258d940d	838	/* TPI DEVID Register Definitions */
Kojto	148:fd96258d940d	839	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
Kojto	148:fd96258d940d	840	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Kojto	148:fd96258d940d	841
Kojto	148:fd96258d940d	842	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
Kojto	148:fd96258d940d	843	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Kojto	148:fd96258d940d	844
Kojto	148:fd96258d940d	845	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
Kojto	148:fd96258d940d	846	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Kojto	148:fd96258d940d	847
Kojto	148:fd96258d940d	848	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
Kojto	148:fd96258d940d	849	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Kojto	148:fd96258d940d	850
Kojto	148:fd96258d940d	851	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
Kojto	148:fd96258d940d	852	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Kojto	148:fd96258d940d	853
Kojto	148:fd96258d940d	854	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
Kojto	148:fd96258d940d	855	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Kojto	148:fd96258d940d	856
Kojto	148:fd96258d940d	857	/* TPI DEVTYPE Register Definitions */
Kojto	148:fd96258d940d	858	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
Kojto	148:fd96258d940d	859	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Kojto	148:fd96258d940d	860
Kojto	148:fd96258d940d	861	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
Kojto	148:fd96258d940d	862	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	148:fd96258d940d	863
Kojto	148:fd96258d940d	864	/@}/ /* end of group CMSIS_TPI */
Kojto	148:fd96258d940d	865
Kojto	148:fd96258d940d	866
Kojto	148:fd96258d940d	867	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto	148:fd96258d940d	868	/**
Kojto	148:fd96258d940d	869	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	870	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto	148:fd96258d940d	871	\brief Type definitions for the Memory Protection Unit (MPU)
Kojto	148:fd96258d940d	872	@{
Kojto	148:fd96258d940d	873	*/
Kojto	148:fd96258d940d	874
Kojto	148:fd96258d940d	875	/**
Kojto	148:fd96258d940d	876	\brief Structure type to access the Memory Protection Unit (MPU).
Kojto	148:fd96258d940d	877	*/
Kojto	148:fd96258d940d	878	typedef struct
Kojto	148:fd96258d940d	879	{
Kojto	148:fd96258d940d	880	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Kojto	148:fd96258d940d	881	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Kojto	148:fd96258d940d	882	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
Kojto	148:fd96258d940d	883	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Kojto	148:fd96258d940d	884	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
Kojto	148:fd96258d940d	885	uint32_t RESERVED0[7U];
Anna Bridge	160:5571c4ff569f	886	union {
Anna Bridge	160:5571c4ff569f	887	__IOM uint32_t MAIR[2];
Anna Bridge	160:5571c4ff569f	888	struct {
Kojto	148:fd96258d940d	889	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
Kojto	148:fd96258d940d	890	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
Anna Bridge	160:5571c4ff569f	891	};
Anna Bridge	160:5571c4ff569f	892	};
Kojto	148:fd96258d940d	893	} MPU_Type;
Kojto	148:fd96258d940d	894
Anna Bridge	160:5571c4ff569f	895	#define MPU_TYPE_RALIASES 1U
Anna Bridge	160:5571c4ff569f	896
Kojto	148:fd96258d940d	897	/* MPU Type Register Definitions */
Kojto	148:fd96258d940d	898	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
Kojto	148:fd96258d940d	899	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Kojto	148:fd96258d940d	900
Kojto	148:fd96258d940d	901	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
Kojto	148:fd96258d940d	902	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Kojto	148:fd96258d940d	903
Kojto	148:fd96258d940d	904	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
Kojto	148:fd96258d940d	905	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Kojto	148:fd96258d940d	906
Kojto	148:fd96258d940d	907	/* MPU Control Register Definitions */
Kojto	148:fd96258d940d	908	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
Kojto	148:fd96258d940d	909	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Kojto	148:fd96258d940d	910
Kojto	148:fd96258d940d	911	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
Kojto	148:fd96258d940d	912	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Kojto	148:fd96258d940d	913
Kojto	148:fd96258d940d	914	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
Kojto	148:fd96258d940d	915	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Kojto	148:fd96258d940d	916
Kojto	148:fd96258d940d	917	/* MPU Region Number Register Definitions */
Kojto	148:fd96258d940d	918	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
Kojto	148:fd96258d940d	919	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Kojto	148:fd96258d940d	920
Kojto	148:fd96258d940d	921	/* MPU Region Base Address Register Definitions */
Kojto	148:fd96258d940d	922	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
Kojto	148:fd96258d940d	923	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
Kojto	148:fd96258d940d	924
Kojto	148:fd96258d940d	925	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
Kojto	148:fd96258d940d	926	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
Kojto	148:fd96258d940d	927
Kojto	148:fd96258d940d	928	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
Kojto	148:fd96258d940d	929	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
Kojto	148:fd96258d940d	930
Kojto	148:fd96258d940d	931	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
Kojto	148:fd96258d940d	932	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
Kojto	148:fd96258d940d	933
Kojto	148:fd96258d940d	934	/* MPU Region Limit Address Register Definitions */
Kojto	148:fd96258d940d	935	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
Kojto	148:fd96258d940d	936	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
Kojto	148:fd96258d940d	937
Kojto	148:fd96258d940d	938	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
Kojto	148:fd96258d940d	939	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
Kojto	148:fd96258d940d	940
Kojto	148:fd96258d940d	941	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
Kojto	148:fd96258d940d	942	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
Kojto	148:fd96258d940d	943
Kojto	148:fd96258d940d	944	/* MPU Memory Attribute Indirection Register 0 Definitions */
Kojto	148:fd96258d940d	945	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
Kojto	148:fd96258d940d	946	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
Kojto	148:fd96258d940d	947
Kojto	148:fd96258d940d	948	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
Kojto	148:fd96258d940d	949	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
Kojto	148:fd96258d940d	950
Kojto	148:fd96258d940d	951	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
Kojto	148:fd96258d940d	952	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
Kojto	148:fd96258d940d	953
Kojto	148:fd96258d940d	954	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
Kojto	148:fd96258d940d	955	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
Kojto	148:fd96258d940d	956
Kojto	148:fd96258d940d	957	/* MPU Memory Attribute Indirection Register 1 Definitions */
Kojto	148:fd96258d940d	958	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
Kojto	148:fd96258d940d	959	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
Kojto	148:fd96258d940d	960
Kojto	148:fd96258d940d	961	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
Kojto	148:fd96258d940d	962	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
Kojto	148:fd96258d940d	963
Kojto	148:fd96258d940d	964	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
Kojto	148:fd96258d940d	965	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
Kojto	148:fd96258d940d	966
Kojto	148:fd96258d940d	967	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
Kojto	148:fd96258d940d	968	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
Kojto	148:fd96258d940d	969
Kojto	148:fd96258d940d	970	/@} end of group CMSIS_MPU /
Kojto	148:fd96258d940d	971	#endif
Kojto	148:fd96258d940d	972
Kojto	148:fd96258d940d	973
Kojto	148:fd96258d940d	974	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	975	/**
Kojto	148:fd96258d940d	976	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	977	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
Kojto	148:fd96258d940d	978	\brief Type definitions for the Security Attribution Unit (SAU)
Kojto	148:fd96258d940d	979	@{
Kojto	148:fd96258d940d	980	*/
Kojto	148:fd96258d940d	981
Kojto	148:fd96258d940d	982	/**
Kojto	148:fd96258d940d	983	\brief Structure type to access the Security Attribution Unit (SAU).
Kojto	148:fd96258d940d	984	*/
Kojto	148:fd96258d940d	985	typedef struct
Kojto	148:fd96258d940d	986	{
Kojto	148:fd96258d940d	987	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
Kojto	148:fd96258d940d	988	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
Kojto	148:fd96258d940d	989	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Kojto	148:fd96258d940d	990	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
Kojto	148:fd96258d940d	991	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
Kojto	148:fd96258d940d	992	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
Kojto	148:fd96258d940d	993	#endif
Kojto	148:fd96258d940d	994	} SAU_Type;
Kojto	148:fd96258d940d	995
Kojto	148:fd96258d940d	996	/* SAU Control Register Definitions */
Kojto	148:fd96258d940d	997	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
Kojto	148:fd96258d940d	998	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
Kojto	148:fd96258d940d	999
Kojto	148:fd96258d940d	1000	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
Kojto	148:fd96258d940d	1001	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
Kojto	148:fd96258d940d	1002
Kojto	148:fd96258d940d	1003	/* SAU Type Register Definitions */
Kojto	148:fd96258d940d	1004	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
Kojto	148:fd96258d940d	1005	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
Kojto	148:fd96258d940d	1006
Kojto	148:fd96258d940d	1007	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Kojto	148:fd96258d940d	1008	/* SAU Region Number Register Definitions */
Kojto	148:fd96258d940d	1009	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
Kojto	148:fd96258d940d	1010	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
Kojto	148:fd96258d940d	1011
Kojto	148:fd96258d940d	1012	/* SAU Region Base Address Register Definitions */
Kojto	148:fd96258d940d	1013	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
Kojto	148:fd96258d940d	1014	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
Kojto	148:fd96258d940d	1015
Kojto	148:fd96258d940d	1016	/* SAU Region Limit Address Register Definitions */
Kojto	148:fd96258d940d	1017	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
Kojto	148:fd96258d940d	1018	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
Kojto	148:fd96258d940d	1019
Kojto	148:fd96258d940d	1020	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
Kojto	148:fd96258d940d	1021	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
Kojto	148:fd96258d940d	1022
Kojto	148:fd96258d940d	1023	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
Kojto	148:fd96258d940d	1024	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
Kojto	148:fd96258d940d	1025
Kojto	148:fd96258d940d	1026	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
Kojto	148:fd96258d940d	1027
Kojto	148:fd96258d940d	1028	/@} end of group CMSIS_SAU /
Kojto	148:fd96258d940d	1029	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	1030
Kojto	148:fd96258d940d	1031
Kojto	148:fd96258d940d	1032	/**
Kojto	148:fd96258d940d	1033	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1034	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto	148:fd96258d940d	1035	\brief Type definitions for the Core Debug Registers
Kojto	148:fd96258d940d	1036	@{
Kojto	148:fd96258d940d	1037	*/
Kojto	148:fd96258d940d	1038
Kojto	148:fd96258d940d	1039	/**
Kojto	148:fd96258d940d	1040	\brief Structure type to access the Core Debug Register (CoreDebug).
Kojto	148:fd96258d940d	1041	*/
Kojto	148:fd96258d940d	1042	typedef struct
Kojto	148:fd96258d940d	1043	{
Kojto	148:fd96258d940d	1044	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Kojto	148:fd96258d940d	1045	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Kojto	148:fd96258d940d	1046	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Kojto	148:fd96258d940d	1047	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Kojto	148:fd96258d940d	1048	uint32_t RESERVED4[1U];
Kojto	148:fd96258d940d	1049	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
Kojto	148:fd96258d940d	1050	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
Kojto	148:fd96258d940d	1051	} CoreDebug_Type;
Kojto	148:fd96258d940d	1052
Kojto	148:fd96258d940d	1053	/* Debug Halting Control and Status Register Definitions */
Kojto	148:fd96258d940d	1054	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
Kojto	148:fd96258d940d	1055	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Kojto	148:fd96258d940d	1056
Kojto	148:fd96258d940d	1057	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
Kojto	148:fd96258d940d	1058	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
Kojto	148:fd96258d940d	1059
Kojto	148:fd96258d940d	1060	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
Kojto	148:fd96258d940d	1061	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Kojto	148:fd96258d940d	1062
Kojto	148:fd96258d940d	1063	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Kojto	148:fd96258d940d	1064	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Kojto	148:fd96258d940d	1065
Kojto	148:fd96258d940d	1066	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
Kojto	148:fd96258d940d	1067	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Kojto	148:fd96258d940d	1068
Kojto	148:fd96258d940d	1069	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
Kojto	148:fd96258d940d	1070	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Kojto	148:fd96258d940d	1071
Kojto	148:fd96258d940d	1072	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
Kojto	148:fd96258d940d	1073	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Kojto	148:fd96258d940d	1074
Kojto	148:fd96258d940d	1075	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
Kojto	148:fd96258d940d	1076	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Kojto	148:fd96258d940d	1077
Kojto	148:fd96258d940d	1078	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
Kojto	148:fd96258d940d	1079	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Kojto	148:fd96258d940d	1080
Kojto	148:fd96258d940d	1081	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
Kojto	148:fd96258d940d	1082	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Kojto	148:fd96258d940d	1083
Kojto	148:fd96258d940d	1084	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
Kojto	148:fd96258d940d	1085	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Kojto	148:fd96258d940d	1086
Kojto	148:fd96258d940d	1087	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	148:fd96258d940d	1088	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Kojto	148:fd96258d940d	1089
Kojto	148:fd96258d940d	1090	/* Debug Core Register Selector Register Definitions */
Kojto	148:fd96258d940d	1091	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
Kojto	148:fd96258d940d	1092	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Kojto	148:fd96258d940d	1093
Kojto	148:fd96258d940d	1094	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
Kojto	148:fd96258d940d	1095	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Kojto	148:fd96258d940d	1096
Kojto	148:fd96258d940d	1097	/* Debug Exception and Monitor Control Register */
Kojto	148:fd96258d940d	1098	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
Kojto	148:fd96258d940d	1099	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
Kojto	148:fd96258d940d	1100
Kojto	148:fd96258d940d	1101	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
Kojto	148:fd96258d940d	1102	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Kojto	148:fd96258d940d	1103
Kojto	148:fd96258d940d	1104	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	148:fd96258d940d	1105	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Kojto	148:fd96258d940d	1106
Kojto	148:fd96258d940d	1107	/* Debug Authentication Control Register Definitions */
Kojto	148:fd96258d940d	1108	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
Kojto	148:fd96258d940d	1109	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
Kojto	148:fd96258d940d	1110
Kojto	148:fd96258d940d	1111	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
Kojto	148:fd96258d940d	1112	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
Kojto	148:fd96258d940d	1113
Kojto	148:fd96258d940d	1114	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
Kojto	148:fd96258d940d	1115	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
Kojto	148:fd96258d940d	1116
Kojto	148:fd96258d940d	1117	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
Kojto	148:fd96258d940d	1118	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
Kojto	148:fd96258d940d	1119
Kojto	148:fd96258d940d	1120	/* Debug Security Control and Status Register Definitions */
Kojto	148:fd96258d940d	1121	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
Kojto	148:fd96258d940d	1122	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
Kojto	148:fd96258d940d	1123
Kojto	148:fd96258d940d	1124	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
Kojto	148:fd96258d940d	1125	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
Kojto	148:fd96258d940d	1126
Kojto	148:fd96258d940d	1127	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
Kojto	148:fd96258d940d	1128	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
Kojto	148:fd96258d940d	1129
Kojto	148:fd96258d940d	1130	/@} end of group CMSIS_CoreDebug /
Kojto	148:fd96258d940d	1131
Kojto	148:fd96258d940d	1132
Kojto	148:fd96258d940d	1133	/**
Kojto	148:fd96258d940d	1134	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1135	\defgroup CMSIS_core_bitfield Core register bit field macros
Kojto	148:fd96258d940d	1136	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Kojto	148:fd96258d940d	1137	@{
Kojto	148:fd96258d940d	1138	*/
Kojto	148:fd96258d940d	1139
Kojto	148:fd96258d940d	1140	/**
Kojto	148:fd96258d940d	1141	\brief Mask and shift a bit field value for use in a register bit range.
Kojto	148:fd96258d940d	1142	\param[in] field Name of the register bit field.
Kojto	148:fd96258d940d	1143	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Kojto	148:fd96258d940d	1144	\return Masked and shifted value.
Kojto	148:fd96258d940d	1145	*/
Kojto	148:fd96258d940d	1146	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Kojto	148:fd96258d940d	1147
Kojto	148:fd96258d940d	1148	/**
Kojto	148:fd96258d940d	1149	\brief Mask and shift a register value to extract a bit filed value.
Kojto	148:fd96258d940d	1150	\param[in] field Name of the register bit field.
Kojto	148:fd96258d940d	1151	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Kojto	148:fd96258d940d	1152	\return Masked and shifted bit field value.
Kojto	148:fd96258d940d	1153	*/
Kojto	148:fd96258d940d	1154	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Kojto	148:fd96258d940d	1155
Kojto	148:fd96258d940d	1156	/@} end of group CMSIS_core_bitfield /
Kojto	148:fd96258d940d	1157
Kojto	148:fd96258d940d	1158
Kojto	148:fd96258d940d	1159	/**
Kojto	148:fd96258d940d	1160	\ingroup CMSIS_core_register
Kojto	148:fd96258d940d	1161	\defgroup CMSIS_core_base Core Definitions
Kojto	148:fd96258d940d	1162	\brief Definitions for base addresses, unions, and structures.
Kojto	148:fd96258d940d	1163	@{
Kojto	148:fd96258d940d	1164	*/
Kojto	148:fd96258d940d	1165
Kojto	148:fd96258d940d	1166	/* Memory mapping of Core Hardware */
Kojto	148:fd96258d940d	1167	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Kojto	148:fd96258d940d	1168	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Kojto	148:fd96258d940d	1169	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Kojto	148:fd96258d940d	1170	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Kojto	148:fd96258d940d	1171	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Kojto	148:fd96258d940d	1172	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Kojto	148:fd96258d940d	1173	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Kojto	148:fd96258d940d	1174
Kojto	148:fd96258d940d	1175
Kojto	148:fd96258d940d	1176	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Kojto	148:fd96258d940d	1177	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Kojto	148:fd96258d940d	1178	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Kojto	148:fd96258d940d	1179	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Kojto	148:fd96258d940d	1180	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Kojto	148:fd96258d940d	1181	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
Kojto	148:fd96258d940d	1182
Kojto	148:fd96258d940d	1183	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto	148:fd96258d940d	1184	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Kojto	148:fd96258d940d	1185	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Kojto	148:fd96258d940d	1186	#endif
Kojto	148:fd96258d940d	1187
Kojto	148:fd96258d940d	1188	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	1189	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
Kojto	148:fd96258d940d	1190	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
Kojto	148:fd96258d940d	1191	#endif
Kojto	148:fd96258d940d	1192
Kojto	148:fd96258d940d	1193	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	1194	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
Kojto	148:fd96258d940d	1195	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
Kojto	148:fd96258d940d	1196	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
Kojto	148:fd96258d940d	1197	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
Kojto	148:fd96258d940d	1198	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
Kojto	148:fd96258d940d	1199
Kojto	148:fd96258d940d	1200	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
Kojto	148:fd96258d940d	1201	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
Kojto	148:fd96258d940d	1202	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
Kojto	148:fd96258d940d	1203	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
Kojto	148:fd96258d940d	1204
Kojto	148:fd96258d940d	1205	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto	148:fd96258d940d	1206	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
Kojto	148:fd96258d940d	1207	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
Kojto	148:fd96258d940d	1208	#endif
Kojto	148:fd96258d940d	1209
Kojto	148:fd96258d940d	1210	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	1211	/@} /
Kojto	148:fd96258d940d	1212
Kojto	148:fd96258d940d	1213
Kojto	148:fd96258d940d	1214
Kojto	148:fd96258d940d	1215	/*******************************************************************************
Kojto	148:fd96258d940d	1216	* Hardware Abstraction Layer
Kojto	148:fd96258d940d	1217	Core Function Interface contains:
Kojto	148:fd96258d940d	1218	- Core NVIC Functions
Kojto	148:fd96258d940d	1219	- Core SysTick Functions
Kojto	148:fd96258d940d	1220	- Core Register Access Functions
Kojto	148:fd96258d940d	1221	******************************************************************************/
Kojto	148:fd96258d940d	1222	/**
Kojto	148:fd96258d940d	1223	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto	148:fd96258d940d	1224	*/
Kojto	148:fd96258d940d	1225
Kojto	148:fd96258d940d	1226
Kojto	148:fd96258d940d	1227
Kojto	148:fd96258d940d	1228	/* ########################## NVIC functions #################################### */
Kojto	148:fd96258d940d	1229	/**
Kojto	148:fd96258d940d	1230	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	1231	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto	148:fd96258d940d	1232	\brief Functions that manage interrupts and exceptions via the NVIC.
Kojto	148:fd96258d940d	1233	@{
Kojto	148:fd96258d940d	1234	*/
Kojto	148:fd96258d940d	1235
Kojto	148:fd96258d940d	1236	#ifdef CMSIS_NVIC_VIRTUAL
Kojto	148:fd96258d940d	1237	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto	148:fd96258d940d	1238	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Kojto	148:fd96258d940d	1239	#endif
Kojto	148:fd96258d940d	1240	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto	148:fd96258d940d	1241	#else
Kojto	148:fd96258d940d	1242	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline /
Kojto	148:fd96258d940d	1243	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline /
Kojto	148:fd96258d940d	1244	#define NVIC_EnableIRQ __NVIC_EnableIRQ
Kojto	148:fd96258d940d	1245	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Kojto	148:fd96258d940d	1246	#define NVIC_DisableIRQ __NVIC_DisableIRQ
Kojto	148:fd96258d940d	1247	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Kojto	148:fd96258d940d	1248	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Kojto	148:fd96258d940d	1249	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Kojto	148:fd96258d940d	1250	#define NVIC_GetActive __NVIC_GetActive
Kojto	148:fd96258d940d	1251	#define NVIC_SetPriority __NVIC_SetPriority
Kojto	148:fd96258d940d	1252	#define NVIC_GetPriority __NVIC_GetPriority
Kojto	148:fd96258d940d	1253	#define NVIC_SystemReset __NVIC_SystemReset
Kojto	148:fd96258d940d	1254	#endif /* CMSIS_NVIC_VIRTUAL */
Kojto	148:fd96258d940d	1255
Kojto	148:fd96258d940d	1256	#ifdef CMSIS_VECTAB_VIRTUAL
Kojto	148:fd96258d940d	1257	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto	148:fd96258d940d	1258	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Kojto	148:fd96258d940d	1259	#endif
Kojto	148:fd96258d940d	1260	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto	148:fd96258d940d	1261	#else
Kojto	148:fd96258d940d	1262	#define NVIC_SetVector __NVIC_SetVector
Kojto	148:fd96258d940d	1263	#define NVIC_GetVector __NVIC_GetVector
Kojto	148:fd96258d940d	1264	#endif /* (CMSIS_VECTAB_VIRTUAL) */
Kojto	148:fd96258d940d	1265
Kojto	148:fd96258d940d	1266	#define NVIC_USER_IRQ_OFFSET 16
Kojto	148:fd96258d940d	1267
Kojto	148:fd96258d940d	1268
Kojto	148:fd96258d940d	1269	/* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto	148:fd96258d940d	1270	/* The following MACROS handle generation of the register offset and byte masks */
Kojto	148:fd96258d940d	1271	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto	148:fd96258d940d	1272	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto	148:fd96258d940d	1273	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto	148:fd96258d940d	1274
Kojto	148:fd96258d940d	1275
Kojto	148:fd96258d940d	1276	/**
Kojto	148:fd96258d940d	1277	\brief Enable Interrupt
Kojto	148:fd96258d940d	1278	\details Enables a device specific interrupt in the NVIC interrupt controller.
Kojto	148:fd96258d940d	1279	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1280	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1281	*/
Kojto	148:fd96258d940d	1282	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1283	{
Kojto	148:fd96258d940d	1284	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1285	{
Kojto	148:fd96258d940d	1286	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	1287	}
Kojto	148:fd96258d940d	1288	}
Kojto	148:fd96258d940d	1289
Kojto	148:fd96258d940d	1290
Kojto	148:fd96258d940d	1291	/**
Kojto	148:fd96258d940d	1292	\brief Get Interrupt Enable status
Kojto	148:fd96258d940d	1293	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Kojto	148:fd96258d940d	1294	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1295	\return 0 Interrupt is not enabled.
Kojto	148:fd96258d940d	1296	\return 1 Interrupt is enabled.
Kojto	148:fd96258d940d	1297	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1298	*/
Kojto	148:fd96258d940d	1299	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1300	{
Kojto	148:fd96258d940d	1301	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1302	{
Kojto	148:fd96258d940d	1303	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1304	}
Kojto	148:fd96258d940d	1305	else
Kojto	148:fd96258d940d	1306	{
Kojto	148:fd96258d940d	1307	return(0U);
Kojto	148:fd96258d940d	1308	}
Kojto	148:fd96258d940d	1309	}
Kojto	148:fd96258d940d	1310
Kojto	148:fd96258d940d	1311
Kojto	148:fd96258d940d	1312	/**
Kojto	148:fd96258d940d	1313	\brief Disable Interrupt
Kojto	148:fd96258d940d	1314	\details Disables a device specific interrupt in the NVIC interrupt controller.
Kojto	148:fd96258d940d	1315	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1316	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1317	*/
Kojto	148:fd96258d940d	1318	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1319	{
Kojto	148:fd96258d940d	1320	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1321	{
Kojto	148:fd96258d940d	1322	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	1323	__DSB();
Kojto	148:fd96258d940d	1324	__ISB();
Kojto	148:fd96258d940d	1325	}
Kojto	148:fd96258d940d	1326	}
Kojto	148:fd96258d940d	1327
Kojto	148:fd96258d940d	1328
Kojto	148:fd96258d940d	1329	/**
Kojto	148:fd96258d940d	1330	\brief Get Pending Interrupt
Kojto	148:fd96258d940d	1331	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Kojto	148:fd96258d940d	1332	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1333	\return 0 Interrupt status is not pending.
Kojto	148:fd96258d940d	1334	\return 1 Interrupt status is pending.
Kojto	148:fd96258d940d	1335	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1336	*/
Kojto	148:fd96258d940d	1337	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1338	{
Kojto	148:fd96258d940d	1339	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1340	{
Kojto	148:fd96258d940d	1341	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1342	}
Kojto	148:fd96258d940d	1343	else
Kojto	148:fd96258d940d	1344	{
Kojto	148:fd96258d940d	1345	return(0U);
Kojto	148:fd96258d940d	1346	}
Kojto	148:fd96258d940d	1347	}
Kojto	148:fd96258d940d	1348
Kojto	148:fd96258d940d	1349
Kojto	148:fd96258d940d	1350	/**
Kojto	148:fd96258d940d	1351	\brief Set Pending Interrupt
Kojto	148:fd96258d940d	1352	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Kojto	148:fd96258d940d	1353	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1354	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1355	*/
Kojto	148:fd96258d940d	1356	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1357	{
Kojto	148:fd96258d940d	1358	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1359	{
Kojto	148:fd96258d940d	1360	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	1361	}
Kojto	148:fd96258d940d	1362	}
Kojto	148:fd96258d940d	1363
Kojto	148:fd96258d940d	1364
Kojto	148:fd96258d940d	1365	/**
Kojto	148:fd96258d940d	1366	\brief Clear Pending Interrupt
Kojto	148:fd96258d940d	1367	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Kojto	148:fd96258d940d	1368	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1369	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1370	*/
Kojto	148:fd96258d940d	1371	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1372	{
Kojto	148:fd96258d940d	1373	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1374	{
Kojto	148:fd96258d940d	1375	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	1376	}
Kojto	148:fd96258d940d	1377	}
Kojto	148:fd96258d940d	1378
Kojto	148:fd96258d940d	1379
Kojto	148:fd96258d940d	1380	/**
Kojto	148:fd96258d940d	1381	\brief Get Active Interrupt
Kojto	148:fd96258d940d	1382	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Kojto	148:fd96258d940d	1383	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1384	\return 0 Interrupt status is not active.
Kojto	148:fd96258d940d	1385	\return 1 Interrupt status is active.
Kojto	148:fd96258d940d	1386	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1387	*/
Kojto	148:fd96258d940d	1388	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1389	{
Kojto	148:fd96258d940d	1390	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1391	{
Kojto	148:fd96258d940d	1392	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1393	}
Kojto	148:fd96258d940d	1394	else
Kojto	148:fd96258d940d	1395	{
Kojto	148:fd96258d940d	1396	return(0U);
Kojto	148:fd96258d940d	1397	}
Kojto	148:fd96258d940d	1398	}
Kojto	148:fd96258d940d	1399
Kojto	148:fd96258d940d	1400
Kojto	148:fd96258d940d	1401	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	1402	/**
Kojto	148:fd96258d940d	1403	\brief Get Interrupt Target State
Kojto	148:fd96258d940d	1404	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Kojto	148:fd96258d940d	1405	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1406	\return 0 if interrupt is assigned to Secure
Kojto	148:fd96258d940d	1407	\return 1 if interrupt is assigned to Non Secure
Kojto	148:fd96258d940d	1408	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1409	*/
Kojto	148:fd96258d940d	1410	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1411	{
Kojto	148:fd96258d940d	1412	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1413	{
Kojto	148:fd96258d940d	1414	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1415	}
Kojto	148:fd96258d940d	1416	else
Kojto	148:fd96258d940d	1417	{
Kojto	148:fd96258d940d	1418	return(0U);
Kojto	148:fd96258d940d	1419	}
Kojto	148:fd96258d940d	1420	}
Kojto	148:fd96258d940d	1421
Kojto	148:fd96258d940d	1422
Kojto	148:fd96258d940d	1423	/**
Kojto	148:fd96258d940d	1424	\brief Set Interrupt Target State
Kojto	148:fd96258d940d	1425	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Kojto	148:fd96258d940d	1426	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1427	\return 0 if interrupt is assigned to Secure
Kojto	148:fd96258d940d	1428	1 if interrupt is assigned to Non Secure
Kojto	148:fd96258d940d	1429	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1430	*/
Kojto	148:fd96258d940d	1431	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1432	{
Kojto	148:fd96258d940d	1433	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1434	{
Kojto	148:fd96258d940d	1435	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
Kojto	148:fd96258d940d	1436	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1437	}
Kojto	148:fd96258d940d	1438	else
Kojto	148:fd96258d940d	1439	{
Kojto	148:fd96258d940d	1440	return(0U);
Kojto	148:fd96258d940d	1441	}
Kojto	148:fd96258d940d	1442	}
Kojto	148:fd96258d940d	1443
Kojto	148:fd96258d940d	1444
Kojto	148:fd96258d940d	1445	/**
Kojto	148:fd96258d940d	1446	\brief Clear Interrupt Target State
Kojto	148:fd96258d940d	1447	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Kojto	148:fd96258d940d	1448	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1449	\return 0 if interrupt is assigned to Secure
Kojto	148:fd96258d940d	1450	1 if interrupt is assigned to Non Secure
Kojto	148:fd96258d940d	1451	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1452	*/
Kojto	148:fd96258d940d	1453	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1454	{
Kojto	148:fd96258d940d	1455	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1456	{
Kojto	148:fd96258d940d	1457	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
Kojto	148:fd96258d940d	1458	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1459	}
Kojto	148:fd96258d940d	1460	else
Kojto	148:fd96258d940d	1461	{
Kojto	148:fd96258d940d	1462	return(0U);
Kojto	148:fd96258d940d	1463	}
Kojto	148:fd96258d940d	1464	}
Kojto	148:fd96258d940d	1465	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	1466
Kojto	148:fd96258d940d	1467
Kojto	148:fd96258d940d	1468	/**
Kojto	148:fd96258d940d	1469	\brief Set Interrupt Priority
Kojto	148:fd96258d940d	1470	\details Sets the priority of a device specific interrupt or a processor exception.
Kojto	148:fd96258d940d	1471	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	1472	or negative to specify a processor exception.
Kojto	148:fd96258d940d	1473	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	1474	\param [in] priority Priority to set.
Kojto	148:fd96258d940d	1475	\note The priority cannot be set for every processor exception.
Kojto	148:fd96258d940d	1476	*/
Kojto	148:fd96258d940d	1477	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto	148:fd96258d940d	1478	{
Kojto	148:fd96258d940d	1479	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1480	{
Kojto	148:fd96258d940d	1481	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
Kojto	148:fd96258d940d	1482	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto	148:fd96258d940d	1483	}
Kojto	148:fd96258d940d	1484	else
Kojto	148:fd96258d940d	1485	{
Kojto	148:fd96258d940d	1486	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
Kojto	148:fd96258d940d	1487	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto	148:fd96258d940d	1488	}
Kojto	148:fd96258d940d	1489	}
Kojto	148:fd96258d940d	1490
Kojto	148:fd96258d940d	1491
Kojto	148:fd96258d940d	1492	/**
Kojto	148:fd96258d940d	1493	\brief Get Interrupt Priority
Kojto	148:fd96258d940d	1494	\details Reads the priority of a device specific interrupt or a processor exception.
Kojto	148:fd96258d940d	1495	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	1496	or negative to specify a processor exception.
Kojto	148:fd96258d940d	1497	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	1498	\return Interrupt Priority.
Kojto	148:fd96258d940d	1499	Value is aligned automatically to the implemented priority bits of the microcontroller.
Kojto	148:fd96258d940d	1500	*/
Kojto	148:fd96258d940d	1501	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1502	{
Kojto	148:fd96258d940d	1503
Kojto	148:fd96258d940d	1504	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1505	{
Kojto	148:fd96258d940d	1506	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Kojto	148:fd96258d940d	1507	}
Kojto	148:fd96258d940d	1508	else
Kojto	148:fd96258d940d	1509	{
Kojto	148:fd96258d940d	1510	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Kojto	148:fd96258d940d	1511	}
Kojto	148:fd96258d940d	1512	}
Kojto	148:fd96258d940d	1513
Kojto	148:fd96258d940d	1514
Kojto	148:fd96258d940d	1515	/**
Kojto	148:fd96258d940d	1516	\brief Set Interrupt Vector
Kojto	148:fd96258d940d	1517	\details Sets an interrupt vector in SRAM based interrupt vector table.
Kojto	148:fd96258d940d	1518	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	1519	or negative to specify a processor exception.
Kojto	148:fd96258d940d	1520	VTOR must been relocated to SRAM before.
Kojto	148:fd96258d940d	1521	If VTOR is not present address 0 must be mapped to SRAM.
Kojto	148:fd96258d940d	1522	\param [in] IRQn Interrupt number
Kojto	148:fd96258d940d	1523	\param [in] vector Address of interrupt handler function
Kojto	148:fd96258d940d	1524	*/
Kojto	148:fd96258d940d	1525	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Kojto	148:fd96258d940d	1526	{
Kojto	148:fd96258d940d	1527	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Kojto	148:fd96258d940d	1528	uint32_t vectors = (uint32_t )SCB->VTOR;
Kojto	148:fd96258d940d	1529	#else
Kojto	148:fd96258d940d	1530	uint32_t vectors = (uint32_t )0x0U;
Kojto	148:fd96258d940d	1531	#endif
Kojto	148:fd96258d940d	1532	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Kojto	148:fd96258d940d	1533	}
Kojto	148:fd96258d940d	1534
Kojto	148:fd96258d940d	1535
Kojto	148:fd96258d940d	1536	/**
Kojto	148:fd96258d940d	1537	\brief Get Interrupt Vector
Kojto	148:fd96258d940d	1538	\details Reads an interrupt vector from interrupt vector table.
Kojto	148:fd96258d940d	1539	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	1540	or negative to specify a processor exception.
Kojto	148:fd96258d940d	1541	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	1542	\return Address of interrupt handler function
Kojto	148:fd96258d940d	1543	*/
Kojto	148:fd96258d940d	1544	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1545	{
Kojto	148:fd96258d940d	1546	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Kojto	148:fd96258d940d	1547	uint32_t vectors = (uint32_t )SCB->VTOR;
Kojto	148:fd96258d940d	1548	#else
Kojto	148:fd96258d940d	1549	uint32_t vectors = (uint32_t )0x0U;
Kojto	148:fd96258d940d	1550	#endif
Kojto	148:fd96258d940d	1551	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Kojto	148:fd96258d940d	1552	}
Kojto	148:fd96258d940d	1553
Kojto	148:fd96258d940d	1554
Kojto	148:fd96258d940d	1555	/**
Kojto	148:fd96258d940d	1556	\brief System Reset
Kojto	148:fd96258d940d	1557	\details Initiates a system reset request to reset the MCU.
Kojto	148:fd96258d940d	1558	*/
Kojto	148:fd96258d940d	1559	__STATIC_INLINE void __NVIC_SystemReset(void)
Kojto	148:fd96258d940d	1560	{
Kojto	148:fd96258d940d	1561	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	148:fd96258d940d	1562	buffered write are completed before reset */
Kojto	148:fd96258d940d	1563	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	148:fd96258d940d	1564	SCB_AIRCR_SYSRESETREQ_Msk);
Kojto	148:fd96258d940d	1565	__DSB(); /* Ensure completion of memory access */
Kojto	148:fd96258d940d	1566
Kojto	148:fd96258d940d	1567	for(;;) /* wait until reset */
Kojto	148:fd96258d940d	1568	{
Kojto	148:fd96258d940d	1569	__NOP();
Kojto	148:fd96258d940d	1570	}
Kojto	148:fd96258d940d	1571	}
Kojto	148:fd96258d940d	1572
Kojto	148:fd96258d940d	1573	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	1574	/**
Kojto	148:fd96258d940d	1575	\brief Enable Interrupt (non-secure)
Kojto	148:fd96258d940d	1576	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Kojto	148:fd96258d940d	1577	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1578	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1579	*/
Kojto	148:fd96258d940d	1580	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1581	{
Kojto	148:fd96258d940d	1582	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1583	{
Kojto	148:fd96258d940d	1584	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	1585	}
Kojto	148:fd96258d940d	1586	}
Kojto	148:fd96258d940d	1587
Kojto	148:fd96258d940d	1588
Kojto	148:fd96258d940d	1589	/**
Kojto	148:fd96258d940d	1590	\brief Get Interrupt Enable status (non-secure)
Kojto	148:fd96258d940d	1591	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
Kojto	148:fd96258d940d	1592	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1593	\return 0 Interrupt is not enabled.
Kojto	148:fd96258d940d	1594	\return 1 Interrupt is enabled.
Kojto	148:fd96258d940d	1595	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1596	*/
Kojto	148:fd96258d940d	1597	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1598	{
Kojto	148:fd96258d940d	1599	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1600	{
Kojto	148:fd96258d940d	1601	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1602	}
Kojto	148:fd96258d940d	1603	else
Kojto	148:fd96258d940d	1604	{
Kojto	148:fd96258d940d	1605	return(0U);
Kojto	148:fd96258d940d	1606	}
Kojto	148:fd96258d940d	1607	}
Kojto	148:fd96258d940d	1608
Kojto	148:fd96258d940d	1609
Kojto	148:fd96258d940d	1610	/**
Kojto	148:fd96258d940d	1611	\brief Disable Interrupt (non-secure)
Kojto	148:fd96258d940d	1612	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Kojto	148:fd96258d940d	1613	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1614	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1615	*/
Kojto	148:fd96258d940d	1616	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1617	{
Kojto	148:fd96258d940d	1618	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1619	{
Kojto	148:fd96258d940d	1620	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	1621	}
Kojto	148:fd96258d940d	1622	}
Kojto	148:fd96258d940d	1623
Kojto	148:fd96258d940d	1624
Kojto	148:fd96258d940d	1625	/**
Kojto	148:fd96258d940d	1626	\brief Get Pending Interrupt (non-secure)
Kojto	148:fd96258d940d	1627	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
Kojto	148:fd96258d940d	1628	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1629	\return 0 Interrupt status is not pending.
Kojto	148:fd96258d940d	1630	\return 1 Interrupt status is pending.
Kojto	148:fd96258d940d	1631	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1632	*/
Kojto	148:fd96258d940d	1633	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1634	{
Kojto	148:fd96258d940d	1635	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1636	{
Kojto	148:fd96258d940d	1637	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1638	}
Anna Bridge	160:5571c4ff569f	1639	else
Anna Bridge	160:5571c4ff569f	1640	{
Anna Bridge	160:5571c4ff569f	1641	return(0U);
Anna Bridge	160:5571c4ff569f	1642	}
Kojto	148:fd96258d940d	1643	}
Kojto	148:fd96258d940d	1644
Kojto	148:fd96258d940d	1645
Kojto	148:fd96258d940d	1646	/**
Kojto	148:fd96258d940d	1647	\brief Set Pending Interrupt (non-secure)
Kojto	148:fd96258d940d	1648	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Kojto	148:fd96258d940d	1649	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1650	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1651	*/
Kojto	148:fd96258d940d	1652	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1653	{
Kojto	148:fd96258d940d	1654	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1655	{
Kojto	148:fd96258d940d	1656	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	1657	}
Kojto	148:fd96258d940d	1658	}
Kojto	148:fd96258d940d	1659
Kojto	148:fd96258d940d	1660
Kojto	148:fd96258d940d	1661	/**
Kojto	148:fd96258d940d	1662	\brief Clear Pending Interrupt (non-secure)
Kojto	148:fd96258d940d	1663	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Kojto	148:fd96258d940d	1664	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1665	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1666	*/
Kojto	148:fd96258d940d	1667	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1668	{
Kojto	148:fd96258d940d	1669	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1670	{
Kojto	148:fd96258d940d	1671	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	148:fd96258d940d	1672	}
Kojto	148:fd96258d940d	1673	}
Kojto	148:fd96258d940d	1674
Kojto	148:fd96258d940d	1675
Kojto	148:fd96258d940d	1676	/**
Kojto	148:fd96258d940d	1677	\brief Get Active Interrupt (non-secure)
Kojto	148:fd96258d940d	1678	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
Kojto	148:fd96258d940d	1679	\param [in] IRQn Device specific interrupt number.
Kojto	148:fd96258d940d	1680	\return 0 Interrupt status is not active.
Kojto	148:fd96258d940d	1681	\return 1 Interrupt status is active.
Kojto	148:fd96258d940d	1682	\note IRQn must not be negative.
Kojto	148:fd96258d940d	1683	*/
Kojto	148:fd96258d940d	1684	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1685	{
Kojto	148:fd96258d940d	1686	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1687	{
Kojto	148:fd96258d940d	1688	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	148:fd96258d940d	1689	}
Kojto	148:fd96258d940d	1690	else
Kojto	148:fd96258d940d	1691	{
Kojto	148:fd96258d940d	1692	return(0U);
Kojto	148:fd96258d940d	1693	}
Kojto	148:fd96258d940d	1694	}
Kojto	148:fd96258d940d	1695
Kojto	148:fd96258d940d	1696
Kojto	148:fd96258d940d	1697	/**
Kojto	148:fd96258d940d	1698	\brief Set Interrupt Priority (non-secure)
Kojto	148:fd96258d940d	1699	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Kojto	148:fd96258d940d	1700	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	1701	or negative to specify a processor exception.
Kojto	148:fd96258d940d	1702	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	1703	\param [in] priority Priority to set.
Kojto	148:fd96258d940d	1704	\note The priority cannot be set for every non-secure processor exception.
Kojto	148:fd96258d940d	1705	*/
Kojto	148:fd96258d940d	1706	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
Kojto	148:fd96258d940d	1707	{
Kojto	148:fd96258d940d	1708	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1709	{
Kojto	148:fd96258d940d	1710	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
Kojto	148:fd96258d940d	1711	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto	148:fd96258d940d	1712	}
Kojto	148:fd96258d940d	1713	else
Kojto	148:fd96258d940d	1714	{
Kojto	148:fd96258d940d	1715	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
Kojto	148:fd96258d940d	1716	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto	148:fd96258d940d	1717	}
Kojto	148:fd96258d940d	1718	}
Kojto	148:fd96258d940d	1719
Kojto	148:fd96258d940d	1720
Kojto	148:fd96258d940d	1721	/**
Kojto	148:fd96258d940d	1722	\brief Get Interrupt Priority (non-secure)
Kojto	148:fd96258d940d	1723	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Kojto	148:fd96258d940d	1724	The interrupt number can be positive to specify a device specific interrupt,
Kojto	148:fd96258d940d	1725	or negative to specify a processor exception.
Kojto	148:fd96258d940d	1726	\param [in] IRQn Interrupt number.
Kojto	148:fd96258d940d	1727	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
Kojto	148:fd96258d940d	1728	*/
Kojto	148:fd96258d940d	1729	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
Kojto	148:fd96258d940d	1730	{
Kojto	148:fd96258d940d	1731
Kojto	148:fd96258d940d	1732	if ((int32_t)(IRQn) >= 0)
Kojto	148:fd96258d940d	1733	{
Kojto	148:fd96258d940d	1734	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Kojto	148:fd96258d940d	1735	}
Kojto	148:fd96258d940d	1736	else
Kojto	148:fd96258d940d	1737	{
Kojto	148:fd96258d940d	1738	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Kojto	148:fd96258d940d	1739	}
Kojto	148:fd96258d940d	1740	}
Kojto	148:fd96258d940d	1741	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	1742
Kojto	148:fd96258d940d	1743	/@} end of CMSIS_Core_NVICFunctions /
Kojto	148:fd96258d940d	1744
Anna Bridge	160:5571c4ff569f	1745	/* ########################## MPU functions #################################### */
Anna Bridge	160:5571c4ff569f	1746
Anna Bridge	160:5571c4ff569f	1747	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	1748
Anna Bridge	160:5571c4ff569f	1749	#include "mpu_armv8.h"
Anna Bridge	160:5571c4ff569f	1750
Anna Bridge	160:5571c4ff569f	1751	#endif
Kojto	148:fd96258d940d	1752
Kojto	148:fd96258d940d	1753	/* ########################## FPU functions #################################### */
Kojto	148:fd96258d940d	1754	/**
Kojto	148:fd96258d940d	1755	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	1756	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Kojto	148:fd96258d940d	1757	\brief Function that provides FPU type.
Kojto	148:fd96258d940d	1758	@{
Kojto	148:fd96258d940d	1759	*/
Kojto	148:fd96258d940d	1760
Kojto	148:fd96258d940d	1761	/**
Kojto	148:fd96258d940d	1762	\brief get FPU type
Kojto	148:fd96258d940d	1763	\details returns the FPU type
Kojto	148:fd96258d940d	1764	\returns
Kojto	148:fd96258d940d	1765	- \b 0: No FPU
Kojto	148:fd96258d940d	1766	- \b 1: Single precision FPU
Kojto	148:fd96258d940d	1767	- \b 2: Double + Single precision FPU
Kojto	148:fd96258d940d	1768	*/
Kojto	148:fd96258d940d	1769	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Kojto	148:fd96258d940d	1770	{
Kojto	148:fd96258d940d	1771	return 0U; /* No FPU */
Kojto	148:fd96258d940d	1772	}
Kojto	148:fd96258d940d	1773
Kojto	148:fd96258d940d	1774
Kojto	148:fd96258d940d	1775	/@} end of CMSIS_Core_FpuFunctions /
Kojto	148:fd96258d940d	1776
Kojto	148:fd96258d940d	1777
Kojto	148:fd96258d940d	1778
Kojto	148:fd96258d940d	1779	/* ########################## SAU functions #################################### */
Kojto	148:fd96258d940d	1780	/**
Kojto	148:fd96258d940d	1781	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	1782	\defgroup CMSIS_Core_SAUFunctions SAU Functions
Kojto	148:fd96258d940d	1783	\brief Functions that configure the SAU.
Kojto	148:fd96258d940d	1784	@{
Kojto	148:fd96258d940d	1785	*/
Kojto	148:fd96258d940d	1786
Kojto	148:fd96258d940d	1787	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	1788
Kojto	148:fd96258d940d	1789	/**
Kojto	148:fd96258d940d	1790	\brief Enable SAU
Kojto	148:fd96258d940d	1791	\details Enables the Security Attribution Unit (SAU).
Kojto	148:fd96258d940d	1792	*/
Kojto	148:fd96258d940d	1793	__STATIC_INLINE void TZ_SAU_Enable(void)
Kojto	148:fd96258d940d	1794	{
Kojto	148:fd96258d940d	1795	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
Kojto	148:fd96258d940d	1796	}
Kojto	148:fd96258d940d	1797
Kojto	148:fd96258d940d	1798
Kojto	148:fd96258d940d	1799
Kojto	148:fd96258d940d	1800	/**
Kojto	148:fd96258d940d	1801	\brief Disable SAU
Kojto	148:fd96258d940d	1802	\details Disables the Security Attribution Unit (SAU).
Kojto	148:fd96258d940d	1803	*/
Kojto	148:fd96258d940d	1804	__STATIC_INLINE void TZ_SAU_Disable(void)
Kojto	148:fd96258d940d	1805	{
Kojto	148:fd96258d940d	1806	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
Kojto	148:fd96258d940d	1807	}
Kojto	148:fd96258d940d	1808
Kojto	148:fd96258d940d	1809	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	1810
Kojto	148:fd96258d940d	1811	/@} end of CMSIS_Core_SAUFunctions /
Kojto	148:fd96258d940d	1812
Kojto	148:fd96258d940d	1813
Kojto	148:fd96258d940d	1814
Kojto	148:fd96258d940d	1815
Kojto	148:fd96258d940d	1816	/* ################################## SysTick function ############################################ */
Kojto	148:fd96258d940d	1817	/**
Kojto	148:fd96258d940d	1818	\ingroup CMSIS_Core_FunctionInterface
Kojto	148:fd96258d940d	1819	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto	148:fd96258d940d	1820	\brief Functions that configure the System.
Kojto	148:fd96258d940d	1821	@{
Kojto	148:fd96258d940d	1822	*/
Kojto	148:fd96258d940d	1823
Kojto	148:fd96258d940d	1824	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Kojto	148:fd96258d940d	1825
Kojto	148:fd96258d940d	1826	/**
Kojto	148:fd96258d940d	1827	\brief System Tick Configuration
Kojto	148:fd96258d940d	1828	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto	148:fd96258d940d	1829	Counter is in free running mode to generate periodic interrupts.
Kojto	148:fd96258d940d	1830	\param [in] ticks Number of ticks between two interrupts.
Kojto	148:fd96258d940d	1831	\return 0 Function succeeded.
Kojto	148:fd96258d940d	1832	\return 1 Function failed.
Kojto	148:fd96258d940d	1833	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	148:fd96258d940d	1834	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	148:fd96258d940d	1835	must contain a vendor-specific implementation of this function.
Kojto	148:fd96258d940d	1836	*/
Kojto	148:fd96258d940d	1837	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto	148:fd96258d940d	1838	{
Kojto	148:fd96258d940d	1839	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Kojto	148:fd96258d940d	1840	{
Kojto	148:fd96258d940d	1841	return (1UL); /* Reload value impossible */
Kojto	148:fd96258d940d	1842	}
Kojto	148:fd96258d940d	1843
Kojto	148:fd96258d940d	1844	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	148:fd96258d940d	1845	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	148:fd96258d940d	1846	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto	148:fd96258d940d	1847	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	148:fd96258d940d	1848	SysTick_CTRL_TICKINT_Msk \|
Kojto	148:fd96258d940d	1849	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	148:fd96258d940d	1850	return (0UL); /* Function successful */
Kojto	148:fd96258d940d	1851	}
Kojto	148:fd96258d940d	1852
Kojto	148:fd96258d940d	1853	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Kojto	148:fd96258d940d	1854	/**
Kojto	148:fd96258d940d	1855	\brief System Tick Configuration (non-secure)
Kojto	148:fd96258d940d	1856	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Kojto	148:fd96258d940d	1857	Counter is in free running mode to generate periodic interrupts.
Kojto	148:fd96258d940d	1858	\param [in] ticks Number of ticks between two interrupts.
Kojto	148:fd96258d940d	1859	\return 0 Function succeeded.
Kojto	148:fd96258d940d	1860	\return 1 Function failed.
Kojto	148:fd96258d940d	1861	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	148:fd96258d940d	1862	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	148:fd96258d940d	1863	must contain a vendor-specific implementation of this function.
Kojto	148:fd96258d940d	1864
Kojto	148:fd96258d940d	1865	*/
Kojto	148:fd96258d940d	1866	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
Kojto	148:fd96258d940d	1867	{
Kojto	148:fd96258d940d	1868	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Kojto	148:fd96258d940d	1869	{
Kojto	148:fd96258d940d	1870	return (1UL); /* Reload value impossible */
Kojto	148:fd96258d940d	1871	}
Kojto	148:fd96258d940d	1872
Kojto	148:fd96258d940d	1873	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	148:fd96258d940d	1874	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	148:fd96258d940d	1875	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto	148:fd96258d940d	1876	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	148:fd96258d940d	1877	SysTick_CTRL_TICKINT_Msk \|
Kojto	148:fd96258d940d	1878	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	148:fd96258d940d	1879	return (0UL); /* Function successful */
Kojto	148:fd96258d940d	1880	}
Kojto	148:fd96258d940d	1881	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Kojto	148:fd96258d940d	1882
Kojto	148:fd96258d940d	1883	#endif
Kojto	148:fd96258d940d	1884
Kojto	148:fd96258d940d	1885	/@} end of CMSIS_Core_SysTickFunctions /
Kojto	148:fd96258d940d	1886
Kojto	148:fd96258d940d	1887
Kojto	148:fd96258d940d	1888
Kojto	148:fd96258d940d	1889
Kojto	148:fd96258d940d	1890	#ifdef __cplusplus
Kojto	148:fd96258d940d	1891	}
Kojto	148:fd96258d940d	1892	#endif
Kojto	148:fd96258d940d	1893
Kojto	148:fd96258d940d	1894	#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
Kojto	148:fd96258d940d	1895
Kojto	148:fd96258d940d	1896	#endif /* __CMSIS_GENERIC */