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TARGET_NUCLEO_L496ZG_P/core_cm3.h@160:5571c4ff569f, 2018-01-17 (annotated)

Committer:: Anna Bridge
Date:: Wed Jan 17 16:13:02 2018 +0000
Revision:: 160:5571c4ff569f
Parent:: 158:1c57384330a6
Child:: 169:a7c7b631e539

mbed library. Release version 158

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	158:1c57384330a6	1	/************************************************************************//
AnnaBridge	158:1c57384330a6	2	* @file core_cm3.h
AnnaBridge	158:1c57384330a6	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Anna Bridge	160:5571c4ff569f	4	* @version V5.0.3
Anna Bridge	160:5571c4ff569f	5	* @date 09. August 2017
AnnaBridge	158:1c57384330a6	6	******************************************************************************/
AnnaBridge	158:1c57384330a6	7	/*
AnnaBridge	158:1c57384330a6	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	158:1c57384330a6	9	*
AnnaBridge	158:1c57384330a6	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	158:1c57384330a6	11	*
AnnaBridge	158:1c57384330a6	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	158:1c57384330a6	13	* not use this file except in compliance with the License.
AnnaBridge	158:1c57384330a6	14	* You may obtain a copy of the License at
AnnaBridge	158:1c57384330a6	15	*
AnnaBridge	158:1c57384330a6	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	158:1c57384330a6	17	*
AnnaBridge	158:1c57384330a6	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	158:1c57384330a6	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	158:1c57384330a6	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	158:1c57384330a6	21	* See the License for the specific language governing permissions and
AnnaBridge	158:1c57384330a6	22	* limitations under the License.
AnnaBridge	158:1c57384330a6	23	*/
AnnaBridge	158:1c57384330a6	24
AnnaBridge	158:1c57384330a6	25	#if defined ( __ICCARM__ )
AnnaBridge	158:1c57384330a6	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	158:1c57384330a6	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	158:1c57384330a6	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	158:1c57384330a6	29	#endif
AnnaBridge	158:1c57384330a6	30
AnnaBridge	158:1c57384330a6	31	#ifndef __CORE_CM3_H_GENERIC
AnnaBridge	158:1c57384330a6	32	#define __CORE_CM3_H_GENERIC
AnnaBridge	158:1c57384330a6	33
AnnaBridge	158:1c57384330a6	34	#include <stdint.h>
AnnaBridge	158:1c57384330a6	35
AnnaBridge	158:1c57384330a6	36	#ifdef __cplusplus
AnnaBridge	158:1c57384330a6	37	extern "C" {
AnnaBridge	158:1c57384330a6	38	#endif
AnnaBridge	158:1c57384330a6	39
AnnaBridge	158:1c57384330a6	40	/**
AnnaBridge	158:1c57384330a6	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	158:1c57384330a6	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	158:1c57384330a6	43
AnnaBridge	158:1c57384330a6	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	158:1c57384330a6	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	158:1c57384330a6	46
AnnaBridge	158:1c57384330a6	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	158:1c57384330a6	48	Unions are used for effective representation of core registers.
AnnaBridge	158:1c57384330a6	49
AnnaBridge	158:1c57384330a6	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	158:1c57384330a6	51	Function-like macros are used to allow more efficient code.
AnnaBridge	158:1c57384330a6	52	*/
AnnaBridge	158:1c57384330a6	53
AnnaBridge	158:1c57384330a6	54
AnnaBridge	158:1c57384330a6	55	/*******************************************************************************
AnnaBridge	158:1c57384330a6	56	* CMSIS definitions
AnnaBridge	158:1c57384330a6	57	******************************************************************************/
AnnaBridge	158:1c57384330a6	58	/**
AnnaBridge	158:1c57384330a6	59	\ingroup Cortex_M3
AnnaBridge	158:1c57384330a6	60	@{
AnnaBridge	158:1c57384330a6	61	*/
AnnaBridge	158:1c57384330a6	62
Anna Bridge	160:5571c4ff569f	63	#include "cmsis_version.h"
Anna Bridge	160:5571c4ff569f	64
AnnaBridge	158:1c57384330a6	65	/* CMSIS CM3 definitions */
Anna Bridge	160:5571c4ff569f	66	#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	160:5571c4ff569f	67	#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	158:1c57384330a6	68	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	160:5571c4ff569f	69	__CM3_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	158:1c57384330a6	70
AnnaBridge	158:1c57384330a6	71	#define __CORTEX_M (3U) /!< Cortex-M Core /
AnnaBridge	158:1c57384330a6	72
AnnaBridge	158:1c57384330a6	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	158:1c57384330a6	74	This core does not support an FPU at all
AnnaBridge	158:1c57384330a6	75	*/
AnnaBridge	158:1c57384330a6	76	#define __FPU_USED 0U
AnnaBridge	158:1c57384330a6	77
AnnaBridge	158:1c57384330a6	78	#if defined ( __CC_ARM )
AnnaBridge	158:1c57384330a6	79	#if defined __TARGET_FPU_VFP
AnnaBridge	158:1c57384330a6	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	158:1c57384330a6	81	#endif
AnnaBridge	158:1c57384330a6	82
AnnaBridge	158:1c57384330a6	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	158:1c57384330a6	84	#if defined __ARM_PCS_VFP
AnnaBridge	158:1c57384330a6	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	158:1c57384330a6	86	#endif
AnnaBridge	158:1c57384330a6	87
AnnaBridge	158:1c57384330a6	88	#elif defined ( __GNUC__ )
AnnaBridge	158:1c57384330a6	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	158:1c57384330a6	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	158:1c57384330a6	91	#endif
AnnaBridge	158:1c57384330a6	92
AnnaBridge	158:1c57384330a6	93	#elif defined ( __ICCARM__ )
AnnaBridge	158:1c57384330a6	94	#if defined __ARMVFP__
AnnaBridge	158:1c57384330a6	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	158:1c57384330a6	96	#endif
AnnaBridge	158:1c57384330a6	97
AnnaBridge	158:1c57384330a6	98	#elif defined ( __TI_ARM__ )
AnnaBridge	158:1c57384330a6	99	#if defined __TI_VFP_SUPPORT__
AnnaBridge	158:1c57384330a6	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	158:1c57384330a6	101	#endif
AnnaBridge	158:1c57384330a6	102
AnnaBridge	158:1c57384330a6	103	#elif defined ( __TASKING__ )
AnnaBridge	158:1c57384330a6	104	#if defined __FPU_VFP__
AnnaBridge	158:1c57384330a6	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	158:1c57384330a6	106	#endif
AnnaBridge	158:1c57384330a6	107
AnnaBridge	158:1c57384330a6	108	#elif defined ( __CSMC__ )
AnnaBridge	158:1c57384330a6	109	#if ( __CSMC__ & 0x400U)
AnnaBridge	158:1c57384330a6	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	158:1c57384330a6	111	#endif
AnnaBridge	158:1c57384330a6	112
AnnaBridge	158:1c57384330a6	113	#endif
AnnaBridge	158:1c57384330a6	114
AnnaBridge	158:1c57384330a6	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	158:1c57384330a6	116
AnnaBridge	158:1c57384330a6	117
AnnaBridge	158:1c57384330a6	118	#ifdef __cplusplus
AnnaBridge	158:1c57384330a6	119	}
AnnaBridge	158:1c57384330a6	120	#endif
AnnaBridge	158:1c57384330a6	121
AnnaBridge	158:1c57384330a6	122	#endif /* __CORE_CM3_H_GENERIC */
AnnaBridge	158:1c57384330a6	123
AnnaBridge	158:1c57384330a6	124	#ifndef __CMSIS_GENERIC
AnnaBridge	158:1c57384330a6	125
AnnaBridge	158:1c57384330a6	126	#ifndef __CORE_CM3_H_DEPENDANT
AnnaBridge	158:1c57384330a6	127	#define __CORE_CM3_H_DEPENDANT
AnnaBridge	158:1c57384330a6	128
AnnaBridge	158:1c57384330a6	129	#ifdef __cplusplus
AnnaBridge	158:1c57384330a6	130	extern "C" {
AnnaBridge	158:1c57384330a6	131	#endif
AnnaBridge	158:1c57384330a6	132
AnnaBridge	158:1c57384330a6	133	/* check device defines and use defaults */
AnnaBridge	158:1c57384330a6	134	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	158:1c57384330a6	135	#ifndef __CM3_REV
AnnaBridge	158:1c57384330a6	136	#define __CM3_REV 0x0200U
AnnaBridge	158:1c57384330a6	137	#warning "__CM3_REV not defined in device header file; using default!"
AnnaBridge	158:1c57384330a6	138	#endif
AnnaBridge	158:1c57384330a6	139
AnnaBridge	158:1c57384330a6	140	#ifndef __MPU_PRESENT
AnnaBridge	158:1c57384330a6	141	#define __MPU_PRESENT 0U
AnnaBridge	158:1c57384330a6	142	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	158:1c57384330a6	143	#endif
AnnaBridge	158:1c57384330a6	144
AnnaBridge	158:1c57384330a6	145	#ifndef __NVIC_PRIO_BITS
AnnaBridge	158:1c57384330a6	146	#define __NVIC_PRIO_BITS 3U
AnnaBridge	158:1c57384330a6	147	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	158:1c57384330a6	148	#endif
AnnaBridge	158:1c57384330a6	149
AnnaBridge	158:1c57384330a6	150	#ifndef __Vendor_SysTickConfig
AnnaBridge	158:1c57384330a6	151	#define __Vendor_SysTickConfig 0U
AnnaBridge	158:1c57384330a6	152	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	158:1c57384330a6	153	#endif
AnnaBridge	158:1c57384330a6	154	#endif
AnnaBridge	158:1c57384330a6	155
AnnaBridge	158:1c57384330a6	156	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	158:1c57384330a6	157	/**
AnnaBridge	158:1c57384330a6	158	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	158:1c57384330a6	159
AnnaBridge	158:1c57384330a6	160	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	158:1c57384330a6	161	\li to specify the access to peripheral variables.
AnnaBridge	158:1c57384330a6	162	\li for automatic generation of peripheral register debug information.
AnnaBridge	158:1c57384330a6	163	*/
AnnaBridge	158:1c57384330a6	164	#ifdef __cplusplus
AnnaBridge	158:1c57384330a6	165	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	158:1c57384330a6	166	#else
AnnaBridge	158:1c57384330a6	167	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	158:1c57384330a6	168	#endif
AnnaBridge	158:1c57384330a6	169	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	158:1c57384330a6	170	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	158:1c57384330a6	171
AnnaBridge	158:1c57384330a6	172	/* following defines should be used for structure members */
AnnaBridge	158:1c57384330a6	173	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	158:1c57384330a6	174	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	158:1c57384330a6	175	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	158:1c57384330a6	176
AnnaBridge	158:1c57384330a6	177	/@} end of group Cortex_M3 /
AnnaBridge	158:1c57384330a6	178
AnnaBridge	158:1c57384330a6	179
AnnaBridge	158:1c57384330a6	180
AnnaBridge	158:1c57384330a6	181	/*******************************************************************************
AnnaBridge	158:1c57384330a6	182	* Register Abstraction
AnnaBridge	158:1c57384330a6	183	Core Register contain:
AnnaBridge	158:1c57384330a6	184	- Core Register
AnnaBridge	158:1c57384330a6	185	- Core NVIC Register
AnnaBridge	158:1c57384330a6	186	- Core SCB Register
AnnaBridge	158:1c57384330a6	187	- Core SysTick Register
AnnaBridge	158:1c57384330a6	188	- Core Debug Register
AnnaBridge	158:1c57384330a6	189	- Core MPU Register
AnnaBridge	158:1c57384330a6	190	******************************************************************************/
AnnaBridge	158:1c57384330a6	191	/**
AnnaBridge	158:1c57384330a6	192	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	158:1c57384330a6	193	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	158:1c57384330a6	194	*/
AnnaBridge	158:1c57384330a6	195
AnnaBridge	158:1c57384330a6	196	/**
AnnaBridge	158:1c57384330a6	197	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	198	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	158:1c57384330a6	199	\brief Core Register type definitions.
AnnaBridge	158:1c57384330a6	200	@{
AnnaBridge	158:1c57384330a6	201	*/
AnnaBridge	158:1c57384330a6	202
AnnaBridge	158:1c57384330a6	203	/**
AnnaBridge	158:1c57384330a6	204	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	158:1c57384330a6	205	*/
AnnaBridge	158:1c57384330a6	206	typedef union
AnnaBridge	158:1c57384330a6	207	{
AnnaBridge	158:1c57384330a6	208	struct
AnnaBridge	158:1c57384330a6	209	{
AnnaBridge	158:1c57384330a6	210	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
AnnaBridge	158:1c57384330a6	211	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	158:1c57384330a6	212	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	158:1c57384330a6	213	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	158:1c57384330a6	214	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	158:1c57384330a6	215	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	158:1c57384330a6	216	} b; /!< Structure used for bit access /
AnnaBridge	158:1c57384330a6	217	uint32_t w; /!< Type used for word access /
AnnaBridge	158:1c57384330a6	218	} APSR_Type;
AnnaBridge	158:1c57384330a6	219
AnnaBridge	158:1c57384330a6	220	/* APSR Register Definitions */
AnnaBridge	158:1c57384330a6	221	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	158:1c57384330a6	222	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	158:1c57384330a6	223
AnnaBridge	158:1c57384330a6	224	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	158:1c57384330a6	225	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	158:1c57384330a6	226
AnnaBridge	158:1c57384330a6	227	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	158:1c57384330a6	228	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	158:1c57384330a6	229
AnnaBridge	158:1c57384330a6	230	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	158:1c57384330a6	231	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	158:1c57384330a6	232
AnnaBridge	158:1c57384330a6	233	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	158:1c57384330a6	234	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	158:1c57384330a6	235
AnnaBridge	158:1c57384330a6	236
AnnaBridge	158:1c57384330a6	237	/**
AnnaBridge	158:1c57384330a6	238	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	158:1c57384330a6	239	*/
AnnaBridge	158:1c57384330a6	240	typedef union
AnnaBridge	158:1c57384330a6	241	{
AnnaBridge	158:1c57384330a6	242	struct
AnnaBridge	158:1c57384330a6	243	{
AnnaBridge	158:1c57384330a6	244	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	158:1c57384330a6	245	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	158:1c57384330a6	246	} b; /!< Structure used for bit access /
AnnaBridge	158:1c57384330a6	247	uint32_t w; /!< Type used for word access /
AnnaBridge	158:1c57384330a6	248	} IPSR_Type;
AnnaBridge	158:1c57384330a6	249
AnnaBridge	158:1c57384330a6	250	/* IPSR Register Definitions */
AnnaBridge	158:1c57384330a6	251	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	158:1c57384330a6	252	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	158:1c57384330a6	253
AnnaBridge	158:1c57384330a6	254
AnnaBridge	158:1c57384330a6	255	/**
AnnaBridge	158:1c57384330a6	256	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	158:1c57384330a6	257	*/
AnnaBridge	158:1c57384330a6	258	typedef union
AnnaBridge	158:1c57384330a6	259	{
AnnaBridge	158:1c57384330a6	260	struct
AnnaBridge	158:1c57384330a6	261	{
AnnaBridge	158:1c57384330a6	262	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	158:1c57384330a6	263	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	158:1c57384330a6	264	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	158:1c57384330a6	265	uint32_t _reserved1:8; /!< bit: 16..23 Reserved /
AnnaBridge	158:1c57384330a6	266	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	158:1c57384330a6	267	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	158:1c57384330a6	268	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	158:1c57384330a6	269	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	158:1c57384330a6	270	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	158:1c57384330a6	271	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	158:1c57384330a6	272	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	158:1c57384330a6	273	} b; /!< Structure used for bit access /
AnnaBridge	158:1c57384330a6	274	uint32_t w; /!< Type used for word access /
AnnaBridge	158:1c57384330a6	275	} xPSR_Type;
AnnaBridge	158:1c57384330a6	276
AnnaBridge	158:1c57384330a6	277	/* xPSR Register Definitions */
AnnaBridge	158:1c57384330a6	278	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	158:1c57384330a6	279	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	158:1c57384330a6	280
AnnaBridge	158:1c57384330a6	281	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	158:1c57384330a6	282	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	158:1c57384330a6	283
AnnaBridge	158:1c57384330a6	284	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	158:1c57384330a6	285	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	158:1c57384330a6	286
AnnaBridge	158:1c57384330a6	287	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	158:1c57384330a6	288	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	158:1c57384330a6	289
AnnaBridge	158:1c57384330a6	290	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	158:1c57384330a6	291	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	158:1c57384330a6	292
AnnaBridge	158:1c57384330a6	293	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	158:1c57384330a6	294	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
AnnaBridge	158:1c57384330a6	295
AnnaBridge	158:1c57384330a6	296	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	158:1c57384330a6	297	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	158:1c57384330a6	298
AnnaBridge	158:1c57384330a6	299	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	158:1c57384330a6	300	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	158:1c57384330a6	301
AnnaBridge	158:1c57384330a6	302	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	158:1c57384330a6	303	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	158:1c57384330a6	304
AnnaBridge	158:1c57384330a6	305
AnnaBridge	158:1c57384330a6	306	/**
AnnaBridge	158:1c57384330a6	307	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	158:1c57384330a6	308	*/
AnnaBridge	158:1c57384330a6	309	typedef union
AnnaBridge	158:1c57384330a6	310	{
AnnaBridge	158:1c57384330a6	311	struct
AnnaBridge	158:1c57384330a6	312	{
AnnaBridge	158:1c57384330a6	313	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	158:1c57384330a6	314	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	158:1c57384330a6	315	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
AnnaBridge	158:1c57384330a6	316	} b; /!< Structure used for bit access /
AnnaBridge	158:1c57384330a6	317	uint32_t w; /!< Type used for word access /
AnnaBridge	158:1c57384330a6	318	} CONTROL_Type;
AnnaBridge	158:1c57384330a6	319
AnnaBridge	158:1c57384330a6	320	/* CONTROL Register Definitions */
AnnaBridge	158:1c57384330a6	321	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	158:1c57384330a6	322	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	158:1c57384330a6	323
AnnaBridge	158:1c57384330a6	324	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	158:1c57384330a6	325	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	158:1c57384330a6	326
AnnaBridge	158:1c57384330a6	327	/@} end of group CMSIS_CORE /
AnnaBridge	158:1c57384330a6	328
AnnaBridge	158:1c57384330a6	329
AnnaBridge	158:1c57384330a6	330	/**
AnnaBridge	158:1c57384330a6	331	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	332	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	158:1c57384330a6	333	\brief Type definitions for the NVIC Registers
AnnaBridge	158:1c57384330a6	334	@{
AnnaBridge	158:1c57384330a6	335	*/
AnnaBridge	158:1c57384330a6	336
AnnaBridge	158:1c57384330a6	337	/**
AnnaBridge	158:1c57384330a6	338	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	158:1c57384330a6	339	*/
AnnaBridge	158:1c57384330a6	340	typedef struct
AnnaBridge	158:1c57384330a6	341	{
AnnaBridge	158:1c57384330a6	342	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	158:1c57384330a6	343	uint32_t RESERVED0[24U];
AnnaBridge	158:1c57384330a6	344	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	158:1c57384330a6	345	uint32_t RSERVED1[24U];
AnnaBridge	158:1c57384330a6	346	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	158:1c57384330a6	347	uint32_t RESERVED2[24U];
AnnaBridge	158:1c57384330a6	348	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	158:1c57384330a6	349	uint32_t RESERVED3[24U];
AnnaBridge	158:1c57384330a6	350	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	158:1c57384330a6	351	uint32_t RESERVED4[56U];
AnnaBridge	158:1c57384330a6	352	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	158:1c57384330a6	353	uint32_t RESERVED5[644U];
AnnaBridge	158:1c57384330a6	354	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	158:1c57384330a6	355	} NVIC_Type;
AnnaBridge	158:1c57384330a6	356
AnnaBridge	158:1c57384330a6	357	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	158:1c57384330a6	358	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	158:1c57384330a6	359	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	158:1c57384330a6	360
AnnaBridge	158:1c57384330a6	361	/@} end of group CMSIS_NVIC /
AnnaBridge	158:1c57384330a6	362
AnnaBridge	158:1c57384330a6	363
AnnaBridge	158:1c57384330a6	364	/**
AnnaBridge	158:1c57384330a6	365	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	366	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	158:1c57384330a6	367	\brief Type definitions for the System Control Block Registers
AnnaBridge	158:1c57384330a6	368	@{
AnnaBridge	158:1c57384330a6	369	*/
AnnaBridge	158:1c57384330a6	370
AnnaBridge	158:1c57384330a6	371	/**
AnnaBridge	158:1c57384330a6	372	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	158:1c57384330a6	373	*/
AnnaBridge	158:1c57384330a6	374	typedef struct
AnnaBridge	158:1c57384330a6	375	{
AnnaBridge	158:1c57384330a6	376	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	158:1c57384330a6	377	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	158:1c57384330a6	378	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	158:1c57384330a6	379	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	158:1c57384330a6	380	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	158:1c57384330a6	381	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	158:1c57384330a6	382	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	158:1c57384330a6	383	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	158:1c57384330a6	384	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	158:1c57384330a6	385	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	158:1c57384330a6	386	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	158:1c57384330a6	387	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	158:1c57384330a6	388	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	158:1c57384330a6	389	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	158:1c57384330a6	390	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	158:1c57384330a6	391	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	158:1c57384330a6	392	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	158:1c57384330a6	393	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	158:1c57384330a6	394	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	158:1c57384330a6	395	uint32_t RESERVED0[5U];
AnnaBridge	158:1c57384330a6	396	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	158:1c57384330a6	397	} SCB_Type;
AnnaBridge	158:1c57384330a6	398
AnnaBridge	158:1c57384330a6	399	/* SCB CPUID Register Definitions */
AnnaBridge	158:1c57384330a6	400	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	158:1c57384330a6	401	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	158:1c57384330a6	402
AnnaBridge	158:1c57384330a6	403	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	158:1c57384330a6	404	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	158:1c57384330a6	405
AnnaBridge	158:1c57384330a6	406	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	158:1c57384330a6	407	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	158:1c57384330a6	408
AnnaBridge	158:1c57384330a6	409	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	158:1c57384330a6	410	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	158:1c57384330a6	411
AnnaBridge	158:1c57384330a6	412	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	158:1c57384330a6	413	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	158:1c57384330a6	414
AnnaBridge	158:1c57384330a6	415	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	158:1c57384330a6	416	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
AnnaBridge	158:1c57384330a6	417	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
AnnaBridge	158:1c57384330a6	418
AnnaBridge	158:1c57384330a6	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	158:1c57384330a6	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	158:1c57384330a6	421
AnnaBridge	158:1c57384330a6	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	158:1c57384330a6	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	158:1c57384330a6	424
AnnaBridge	158:1c57384330a6	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	158:1c57384330a6	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	158:1c57384330a6	427
AnnaBridge	158:1c57384330a6	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	158:1c57384330a6	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	158:1c57384330a6	430
AnnaBridge	158:1c57384330a6	431	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	158:1c57384330a6	432	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	158:1c57384330a6	433
AnnaBridge	158:1c57384330a6	434	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	158:1c57384330a6	435	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	158:1c57384330a6	436
AnnaBridge	158:1c57384330a6	437	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	158:1c57384330a6	438	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	158:1c57384330a6	439
AnnaBridge	158:1c57384330a6	440	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	158:1c57384330a6	441	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	158:1c57384330a6	442
AnnaBridge	158:1c57384330a6	443	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	158:1c57384330a6	444	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	158:1c57384330a6	445
AnnaBridge	158:1c57384330a6	446	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	158:1c57384330a6	447	#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
AnnaBridge	158:1c57384330a6	448	#define SCB_VTOR_TBLBASE_Pos 29U /!< SCB VTOR: TBLBASE Position /
AnnaBridge	158:1c57384330a6	449	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
AnnaBridge	158:1c57384330a6	450
AnnaBridge	158:1c57384330a6	451	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	158:1c57384330a6	452	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	158:1c57384330a6	453	#else
AnnaBridge	158:1c57384330a6	454	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	158:1c57384330a6	455	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	158:1c57384330a6	456	#endif
AnnaBridge	158:1c57384330a6	457
AnnaBridge	158:1c57384330a6	458	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	158:1c57384330a6	459	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	158:1c57384330a6	460	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	158:1c57384330a6	461
AnnaBridge	158:1c57384330a6	462	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	158:1c57384330a6	463	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	158:1c57384330a6	464
AnnaBridge	158:1c57384330a6	465	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	158:1c57384330a6	466	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	158:1c57384330a6	467
AnnaBridge	158:1c57384330a6	468	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	158:1c57384330a6	469	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	158:1c57384330a6	470
AnnaBridge	158:1c57384330a6	471	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	158:1c57384330a6	472	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	158:1c57384330a6	473
AnnaBridge	158:1c57384330a6	474	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	158:1c57384330a6	475	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	158:1c57384330a6	476
AnnaBridge	158:1c57384330a6	477	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
AnnaBridge	158:1c57384330a6	478	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
AnnaBridge	158:1c57384330a6	479
AnnaBridge	158:1c57384330a6	480	/* SCB System Control Register Definitions */
AnnaBridge	158:1c57384330a6	481	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	158:1c57384330a6	482	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	158:1c57384330a6	483
AnnaBridge	158:1c57384330a6	484	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	158:1c57384330a6	485	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	158:1c57384330a6	486
AnnaBridge	158:1c57384330a6	487	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	158:1c57384330a6	488	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	158:1c57384330a6	489
AnnaBridge	158:1c57384330a6	490	/* SCB Configuration Control Register Definitions */
AnnaBridge	158:1c57384330a6	491	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
AnnaBridge	158:1c57384330a6	492	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
AnnaBridge	158:1c57384330a6	493
AnnaBridge	158:1c57384330a6	494	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	158:1c57384330a6	495	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	158:1c57384330a6	496
AnnaBridge	158:1c57384330a6	497	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	158:1c57384330a6	498	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	158:1c57384330a6	499
AnnaBridge	158:1c57384330a6	500	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	158:1c57384330a6	501	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	158:1c57384330a6	502
AnnaBridge	158:1c57384330a6	503	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	158:1c57384330a6	504	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	158:1c57384330a6	505
AnnaBridge	158:1c57384330a6	506	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
AnnaBridge	158:1c57384330a6	507	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
AnnaBridge	158:1c57384330a6	508
AnnaBridge	158:1c57384330a6	509	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	158:1c57384330a6	510	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	158:1c57384330a6	511	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	158:1c57384330a6	512
AnnaBridge	158:1c57384330a6	513	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	158:1c57384330a6	514	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	158:1c57384330a6	515
AnnaBridge	158:1c57384330a6	516	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	158:1c57384330a6	517	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	158:1c57384330a6	518
AnnaBridge	158:1c57384330a6	519	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	158:1c57384330a6	520	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	158:1c57384330a6	521
AnnaBridge	158:1c57384330a6	522	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	158:1c57384330a6	523	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	158:1c57384330a6	524
AnnaBridge	158:1c57384330a6	525	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	158:1c57384330a6	526	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	158:1c57384330a6	527
AnnaBridge	158:1c57384330a6	528	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	158:1c57384330a6	529	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	158:1c57384330a6	530
AnnaBridge	158:1c57384330a6	531	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	158:1c57384330a6	532	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	158:1c57384330a6	533
AnnaBridge	158:1c57384330a6	534	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	158:1c57384330a6	535	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	158:1c57384330a6	536
AnnaBridge	158:1c57384330a6	537	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	158:1c57384330a6	538	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	158:1c57384330a6	539
AnnaBridge	158:1c57384330a6	540	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	158:1c57384330a6	541	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	158:1c57384330a6	542
AnnaBridge	158:1c57384330a6	543	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	158:1c57384330a6	544	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	158:1c57384330a6	545
AnnaBridge	158:1c57384330a6	546	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	158:1c57384330a6	547	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	158:1c57384330a6	548
AnnaBridge	158:1c57384330a6	549	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	158:1c57384330a6	550	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	158:1c57384330a6	551
AnnaBridge	158:1c57384330a6	552	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	158:1c57384330a6	553	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	158:1c57384330a6	554	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	158:1c57384330a6	555
AnnaBridge	158:1c57384330a6	556	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	158:1c57384330a6	557	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	158:1c57384330a6	558
AnnaBridge	158:1c57384330a6	559	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	158:1c57384330a6	560	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	158:1c57384330a6	561
AnnaBridge	158:1c57384330a6	562	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	158:1c57384330a6	563	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	158:1c57384330a6	564	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	158:1c57384330a6	565
AnnaBridge	158:1c57384330a6	566	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	158:1c57384330a6	567	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	158:1c57384330a6	568
AnnaBridge	158:1c57384330a6	569	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	158:1c57384330a6	570	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	158:1c57384330a6	571
AnnaBridge	158:1c57384330a6	572	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	158:1c57384330a6	573	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	158:1c57384330a6	574
AnnaBridge	158:1c57384330a6	575	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	158:1c57384330a6	576	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	158:1c57384330a6	577
AnnaBridge	158:1c57384330a6	578	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	158:1c57384330a6	579	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	158:1c57384330a6	580	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	158:1c57384330a6	581
AnnaBridge	158:1c57384330a6	582	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	158:1c57384330a6	583	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	158:1c57384330a6	584
AnnaBridge	158:1c57384330a6	585	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	158:1c57384330a6	586	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	158:1c57384330a6	587
AnnaBridge	158:1c57384330a6	588	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	158:1c57384330a6	589	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	158:1c57384330a6	590
AnnaBridge	158:1c57384330a6	591	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	158:1c57384330a6	592	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	158:1c57384330a6	593
AnnaBridge	158:1c57384330a6	594	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	158:1c57384330a6	595	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	158:1c57384330a6	596
AnnaBridge	158:1c57384330a6	597	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	158:1c57384330a6	598	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	158:1c57384330a6	599	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	158:1c57384330a6	600
AnnaBridge	158:1c57384330a6	601	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	158:1c57384330a6	602	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	158:1c57384330a6	603
AnnaBridge	158:1c57384330a6	604	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	158:1c57384330a6	605	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	158:1c57384330a6	606
AnnaBridge	158:1c57384330a6	607	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	158:1c57384330a6	608	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	158:1c57384330a6	609
AnnaBridge	158:1c57384330a6	610	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	158:1c57384330a6	611	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	158:1c57384330a6	612
AnnaBridge	158:1c57384330a6	613	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	158:1c57384330a6	614	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	158:1c57384330a6	615
AnnaBridge	158:1c57384330a6	616	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	158:1c57384330a6	617	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	158:1c57384330a6	618	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	158:1c57384330a6	619
AnnaBridge	158:1c57384330a6	620	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	158:1c57384330a6	621	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	158:1c57384330a6	622
AnnaBridge	158:1c57384330a6	623	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	158:1c57384330a6	624	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	158:1c57384330a6	625
AnnaBridge	158:1c57384330a6	626	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	158:1c57384330a6	627	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	158:1c57384330a6	628	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	158:1c57384330a6	629
AnnaBridge	158:1c57384330a6	630	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	158:1c57384330a6	631	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	158:1c57384330a6	632
AnnaBridge	158:1c57384330a6	633	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	158:1c57384330a6	634	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	158:1c57384330a6	635
AnnaBridge	158:1c57384330a6	636	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	158:1c57384330a6	637	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	158:1c57384330a6	638
AnnaBridge	158:1c57384330a6	639	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	158:1c57384330a6	640	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	158:1c57384330a6	641
AnnaBridge	158:1c57384330a6	642	/@} end of group CMSIS_SCB /
AnnaBridge	158:1c57384330a6	643
AnnaBridge	158:1c57384330a6	644
AnnaBridge	158:1c57384330a6	645	/**
AnnaBridge	158:1c57384330a6	646	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	647	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	158:1c57384330a6	648	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	158:1c57384330a6	649	@{
AnnaBridge	158:1c57384330a6	650	*/
AnnaBridge	158:1c57384330a6	651
AnnaBridge	158:1c57384330a6	652	/**
AnnaBridge	158:1c57384330a6	653	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	158:1c57384330a6	654	*/
AnnaBridge	158:1c57384330a6	655	typedef struct
AnnaBridge	158:1c57384330a6	656	{
AnnaBridge	158:1c57384330a6	657	uint32_t RESERVED0[1U];
AnnaBridge	158:1c57384330a6	658	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	158:1c57384330a6	659	#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
AnnaBridge	158:1c57384330a6	660	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	158:1c57384330a6	661	#else
AnnaBridge	158:1c57384330a6	662	uint32_t RESERVED1[1U];
AnnaBridge	158:1c57384330a6	663	#endif
AnnaBridge	158:1c57384330a6	664	} SCnSCB_Type;
AnnaBridge	158:1c57384330a6	665
AnnaBridge	158:1c57384330a6	666	/* Interrupt Controller Type Register Definitions */
AnnaBridge	158:1c57384330a6	667	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	158:1c57384330a6	668	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	158:1c57384330a6	669
AnnaBridge	158:1c57384330a6	670	/* Auxiliary Control Register Definitions */
AnnaBridge	158:1c57384330a6	671
AnnaBridge	158:1c57384330a6	672	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
AnnaBridge	158:1c57384330a6	673	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
AnnaBridge	158:1c57384330a6	674
AnnaBridge	158:1c57384330a6	675	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
AnnaBridge	158:1c57384330a6	676	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
AnnaBridge	158:1c57384330a6	677
AnnaBridge	158:1c57384330a6	678	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
AnnaBridge	158:1c57384330a6	679	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	158:1c57384330a6	680
AnnaBridge	158:1c57384330a6	681	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	158:1c57384330a6	682
AnnaBridge	158:1c57384330a6	683
AnnaBridge	158:1c57384330a6	684	/**
AnnaBridge	158:1c57384330a6	685	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	686	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	158:1c57384330a6	687	\brief Type definitions for the System Timer Registers.
AnnaBridge	158:1c57384330a6	688	@{
AnnaBridge	158:1c57384330a6	689	*/
AnnaBridge	158:1c57384330a6	690
AnnaBridge	158:1c57384330a6	691	/**
AnnaBridge	158:1c57384330a6	692	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	158:1c57384330a6	693	*/
AnnaBridge	158:1c57384330a6	694	typedef struct
AnnaBridge	158:1c57384330a6	695	{
AnnaBridge	158:1c57384330a6	696	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	158:1c57384330a6	697	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	158:1c57384330a6	698	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	158:1c57384330a6	699	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	158:1c57384330a6	700	} SysTick_Type;
AnnaBridge	158:1c57384330a6	701
AnnaBridge	158:1c57384330a6	702	/* SysTick Control / Status Register Definitions */
AnnaBridge	158:1c57384330a6	703	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	158:1c57384330a6	704	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	158:1c57384330a6	705
AnnaBridge	158:1c57384330a6	706	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	158:1c57384330a6	707	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	158:1c57384330a6	708
AnnaBridge	158:1c57384330a6	709	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	158:1c57384330a6	710	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	158:1c57384330a6	711
AnnaBridge	158:1c57384330a6	712	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	158:1c57384330a6	713	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	158:1c57384330a6	714
AnnaBridge	158:1c57384330a6	715	/* SysTick Reload Register Definitions */
AnnaBridge	158:1c57384330a6	716	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	158:1c57384330a6	717	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	158:1c57384330a6	718
AnnaBridge	158:1c57384330a6	719	/* SysTick Current Register Definitions */
AnnaBridge	158:1c57384330a6	720	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	158:1c57384330a6	721	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	158:1c57384330a6	722
AnnaBridge	158:1c57384330a6	723	/* SysTick Calibration Register Definitions */
AnnaBridge	158:1c57384330a6	724	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	158:1c57384330a6	725	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	158:1c57384330a6	726
AnnaBridge	158:1c57384330a6	727	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	158:1c57384330a6	728	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	158:1c57384330a6	729
AnnaBridge	158:1c57384330a6	730	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	158:1c57384330a6	731	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	158:1c57384330a6	732
AnnaBridge	158:1c57384330a6	733	/@} end of group CMSIS_SysTick /
AnnaBridge	158:1c57384330a6	734
AnnaBridge	158:1c57384330a6	735
AnnaBridge	158:1c57384330a6	736	/**
AnnaBridge	158:1c57384330a6	737	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	738	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	158:1c57384330a6	739	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	158:1c57384330a6	740	@{
AnnaBridge	158:1c57384330a6	741	*/
AnnaBridge	158:1c57384330a6	742
AnnaBridge	158:1c57384330a6	743	/**
AnnaBridge	158:1c57384330a6	744	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	158:1c57384330a6	745	*/
AnnaBridge	158:1c57384330a6	746	typedef struct
AnnaBridge	158:1c57384330a6	747	{
AnnaBridge	158:1c57384330a6	748	__OM union
AnnaBridge	158:1c57384330a6	749	{
AnnaBridge	158:1c57384330a6	750	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	158:1c57384330a6	751	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	158:1c57384330a6	752	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	158:1c57384330a6	753	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	158:1c57384330a6	754	uint32_t RESERVED0[864U];
AnnaBridge	158:1c57384330a6	755	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	158:1c57384330a6	756	uint32_t RESERVED1[15U];
AnnaBridge	158:1c57384330a6	757	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	158:1c57384330a6	758	uint32_t RESERVED2[15U];
AnnaBridge	158:1c57384330a6	759	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	158:1c57384330a6	760	uint32_t RESERVED3[29U];
AnnaBridge	158:1c57384330a6	761	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	158:1c57384330a6	762	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	158:1c57384330a6	763	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	158:1c57384330a6	764	uint32_t RESERVED4[43U];
AnnaBridge	158:1c57384330a6	765	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	158:1c57384330a6	766	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	158:1c57384330a6	767	uint32_t RESERVED5[6U];
AnnaBridge	158:1c57384330a6	768	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	158:1c57384330a6	769	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	158:1c57384330a6	770	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	158:1c57384330a6	771	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	158:1c57384330a6	772	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	158:1c57384330a6	773	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	158:1c57384330a6	774	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	158:1c57384330a6	775	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	158:1c57384330a6	776	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	158:1c57384330a6	777	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	158:1c57384330a6	778	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	158:1c57384330a6	779	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	158:1c57384330a6	780	} ITM_Type;
AnnaBridge	158:1c57384330a6	781
AnnaBridge	158:1c57384330a6	782	/* ITM Trace Privilege Register Definitions */
AnnaBridge	158:1c57384330a6	783	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
AnnaBridge	158:1c57384330a6	784	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	158:1c57384330a6	785
AnnaBridge	158:1c57384330a6	786	/* ITM Trace Control Register Definitions */
AnnaBridge	158:1c57384330a6	787	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	158:1c57384330a6	788	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	158:1c57384330a6	789
AnnaBridge	158:1c57384330a6	790	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	158:1c57384330a6	791	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	158:1c57384330a6	792
AnnaBridge	158:1c57384330a6	793	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	158:1c57384330a6	794	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	158:1c57384330a6	795
AnnaBridge	158:1c57384330a6	796	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
AnnaBridge	158:1c57384330a6	797	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
AnnaBridge	158:1c57384330a6	798
AnnaBridge	158:1c57384330a6	799	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	158:1c57384330a6	800	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	158:1c57384330a6	801
AnnaBridge	158:1c57384330a6	802	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	158:1c57384330a6	803	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	158:1c57384330a6	804
AnnaBridge	158:1c57384330a6	805	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	158:1c57384330a6	806	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	158:1c57384330a6	807
AnnaBridge	158:1c57384330a6	808	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	158:1c57384330a6	809	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	158:1c57384330a6	810
AnnaBridge	158:1c57384330a6	811	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	158:1c57384330a6	812	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	158:1c57384330a6	813
AnnaBridge	158:1c57384330a6	814	/* ITM Integration Write Register Definitions */
AnnaBridge	158:1c57384330a6	815	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	158:1c57384330a6	816	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	158:1c57384330a6	817
AnnaBridge	158:1c57384330a6	818	/* ITM Integration Read Register Definitions */
AnnaBridge	158:1c57384330a6	819	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	158:1c57384330a6	820	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	158:1c57384330a6	821
AnnaBridge	158:1c57384330a6	822	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	158:1c57384330a6	823	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	158:1c57384330a6	824	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	158:1c57384330a6	825
AnnaBridge	158:1c57384330a6	826	/* ITM Lock Status Register Definitions */
AnnaBridge	158:1c57384330a6	827	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	158:1c57384330a6	828	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	158:1c57384330a6	829
AnnaBridge	158:1c57384330a6	830	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	158:1c57384330a6	831	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	158:1c57384330a6	832
AnnaBridge	158:1c57384330a6	833	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	158:1c57384330a6	834	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	158:1c57384330a6	835
AnnaBridge	158:1c57384330a6	836	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	158:1c57384330a6	837
AnnaBridge	158:1c57384330a6	838
AnnaBridge	158:1c57384330a6	839	/**
AnnaBridge	158:1c57384330a6	840	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	841	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	158:1c57384330a6	842	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	158:1c57384330a6	843	@{
AnnaBridge	158:1c57384330a6	844	*/
AnnaBridge	158:1c57384330a6	845
AnnaBridge	158:1c57384330a6	846	/**
AnnaBridge	158:1c57384330a6	847	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	158:1c57384330a6	848	*/
AnnaBridge	158:1c57384330a6	849	typedef struct
AnnaBridge	158:1c57384330a6	850	{
AnnaBridge	158:1c57384330a6	851	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	158:1c57384330a6	852	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	158:1c57384330a6	853	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	158:1c57384330a6	854	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	158:1c57384330a6	855	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	158:1c57384330a6	856	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	158:1c57384330a6	857	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	158:1c57384330a6	858	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	158:1c57384330a6	859	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	158:1c57384330a6	860	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	158:1c57384330a6	861	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	158:1c57384330a6	862	uint32_t RESERVED0[1U];
AnnaBridge	158:1c57384330a6	863	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	158:1c57384330a6	864	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	158:1c57384330a6	865	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	158:1c57384330a6	866	uint32_t RESERVED1[1U];
AnnaBridge	158:1c57384330a6	867	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	158:1c57384330a6	868	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	158:1c57384330a6	869	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	158:1c57384330a6	870	uint32_t RESERVED2[1U];
AnnaBridge	158:1c57384330a6	871	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	158:1c57384330a6	872	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	158:1c57384330a6	873	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	158:1c57384330a6	874	} DWT_Type;
AnnaBridge	158:1c57384330a6	875
AnnaBridge	158:1c57384330a6	876	/* DWT Control Register Definitions */
AnnaBridge	158:1c57384330a6	877	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	158:1c57384330a6	878	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	158:1c57384330a6	879
AnnaBridge	158:1c57384330a6	880	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	158:1c57384330a6	881	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	158:1c57384330a6	882
AnnaBridge	158:1c57384330a6	883	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	158:1c57384330a6	884	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	158:1c57384330a6	885
AnnaBridge	158:1c57384330a6	886	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	158:1c57384330a6	887	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	158:1c57384330a6	888
AnnaBridge	158:1c57384330a6	889	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	158:1c57384330a6	890	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	158:1c57384330a6	891
AnnaBridge	158:1c57384330a6	892	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	158:1c57384330a6	893	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	158:1c57384330a6	894
AnnaBridge	158:1c57384330a6	895	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	158:1c57384330a6	896	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	158:1c57384330a6	897
AnnaBridge	158:1c57384330a6	898	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	158:1c57384330a6	899	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	158:1c57384330a6	900
AnnaBridge	158:1c57384330a6	901	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	158:1c57384330a6	902	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	158:1c57384330a6	903
AnnaBridge	158:1c57384330a6	904	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	158:1c57384330a6	905	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	158:1c57384330a6	906
AnnaBridge	158:1c57384330a6	907	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	158:1c57384330a6	908	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	158:1c57384330a6	909
AnnaBridge	158:1c57384330a6	910	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	158:1c57384330a6	911	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	158:1c57384330a6	912
AnnaBridge	158:1c57384330a6	913	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	158:1c57384330a6	914	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	158:1c57384330a6	915
AnnaBridge	158:1c57384330a6	916	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	158:1c57384330a6	917	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	158:1c57384330a6	918
AnnaBridge	158:1c57384330a6	919	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	158:1c57384330a6	920	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	158:1c57384330a6	921
AnnaBridge	158:1c57384330a6	922	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	158:1c57384330a6	923	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	158:1c57384330a6	924
AnnaBridge	158:1c57384330a6	925	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	158:1c57384330a6	926	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	158:1c57384330a6	927
AnnaBridge	158:1c57384330a6	928	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	158:1c57384330a6	929	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	158:1c57384330a6	930
AnnaBridge	158:1c57384330a6	931	/* DWT CPI Count Register Definitions */
AnnaBridge	158:1c57384330a6	932	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	158:1c57384330a6	933	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	158:1c57384330a6	934
AnnaBridge	158:1c57384330a6	935	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	158:1c57384330a6	936	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	158:1c57384330a6	937	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	158:1c57384330a6	938
AnnaBridge	158:1c57384330a6	939	/* DWT Sleep Count Register Definitions */
AnnaBridge	158:1c57384330a6	940	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	158:1c57384330a6	941	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	158:1c57384330a6	942
AnnaBridge	158:1c57384330a6	943	/* DWT LSU Count Register Definitions */
AnnaBridge	158:1c57384330a6	944	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	158:1c57384330a6	945	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	158:1c57384330a6	946
AnnaBridge	158:1c57384330a6	947	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	158:1c57384330a6	948	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	158:1c57384330a6	949	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	158:1c57384330a6	950
AnnaBridge	158:1c57384330a6	951	/* DWT Comparator Mask Register Definitions */
AnnaBridge	158:1c57384330a6	952	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
AnnaBridge	158:1c57384330a6	953	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
AnnaBridge	158:1c57384330a6	954
AnnaBridge	158:1c57384330a6	955	/* DWT Comparator Function Register Definitions */
AnnaBridge	158:1c57384330a6	956	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	158:1c57384330a6	957	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	158:1c57384330a6	958
AnnaBridge	158:1c57384330a6	959	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
AnnaBridge	158:1c57384330a6	960	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
AnnaBridge	158:1c57384330a6	961
AnnaBridge	158:1c57384330a6	962	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
AnnaBridge	158:1c57384330a6	963	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
AnnaBridge	158:1c57384330a6	964
AnnaBridge	158:1c57384330a6	965	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	158:1c57384330a6	966	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	158:1c57384330a6	967
AnnaBridge	158:1c57384330a6	968	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
AnnaBridge	158:1c57384330a6	969	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
AnnaBridge	158:1c57384330a6	970
AnnaBridge	158:1c57384330a6	971	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
AnnaBridge	158:1c57384330a6	972	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
AnnaBridge	158:1c57384330a6	973
AnnaBridge	158:1c57384330a6	974	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
AnnaBridge	158:1c57384330a6	975	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
AnnaBridge	158:1c57384330a6	976
AnnaBridge	158:1c57384330a6	977	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
AnnaBridge	158:1c57384330a6	978	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
AnnaBridge	158:1c57384330a6	979
AnnaBridge	158:1c57384330a6	980	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
AnnaBridge	158:1c57384330a6	981	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
AnnaBridge	158:1c57384330a6	982
AnnaBridge	158:1c57384330a6	983	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	158:1c57384330a6	984
AnnaBridge	158:1c57384330a6	985
AnnaBridge	158:1c57384330a6	986	/**
AnnaBridge	158:1c57384330a6	987	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	988	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	158:1c57384330a6	989	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	158:1c57384330a6	990	@{
AnnaBridge	158:1c57384330a6	991	*/
AnnaBridge	158:1c57384330a6	992
AnnaBridge	158:1c57384330a6	993	/**
AnnaBridge	158:1c57384330a6	994	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	158:1c57384330a6	995	*/
AnnaBridge	158:1c57384330a6	996	typedef struct
AnnaBridge	158:1c57384330a6	997	{
AnnaBridge	158:1c57384330a6	998	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	158:1c57384330a6	999	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	158:1c57384330a6	1000	uint32_t RESERVED0[2U];
AnnaBridge	158:1c57384330a6	1001	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	158:1c57384330a6	1002	uint32_t RESERVED1[55U];
AnnaBridge	158:1c57384330a6	1003	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	158:1c57384330a6	1004	uint32_t RESERVED2[131U];
AnnaBridge	158:1c57384330a6	1005	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	158:1c57384330a6	1006	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	158:1c57384330a6	1007	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	158:1c57384330a6	1008	uint32_t RESERVED3[759U];
AnnaBridge	158:1c57384330a6	1009	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	158:1c57384330a6	1010	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	158:1c57384330a6	1011	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	158:1c57384330a6	1012	uint32_t RESERVED4[1U];
AnnaBridge	158:1c57384330a6	1013	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	158:1c57384330a6	1014	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	158:1c57384330a6	1015	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	158:1c57384330a6	1016	uint32_t RESERVED5[39U];
AnnaBridge	158:1c57384330a6	1017	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	158:1c57384330a6	1018	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	158:1c57384330a6	1019	uint32_t RESERVED7[8U];
AnnaBridge	158:1c57384330a6	1020	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	158:1c57384330a6	1021	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	158:1c57384330a6	1022	} TPI_Type;
AnnaBridge	158:1c57384330a6	1023
AnnaBridge	158:1c57384330a6	1024	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	158:1c57384330a6	1025	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	158:1c57384330a6	1026	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	158:1c57384330a6	1027
AnnaBridge	158:1c57384330a6	1028	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	158:1c57384330a6	1029	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	158:1c57384330a6	1030	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	158:1c57384330a6	1031
AnnaBridge	158:1c57384330a6	1032	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	158:1c57384330a6	1033	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	158:1c57384330a6	1034	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	158:1c57384330a6	1035
AnnaBridge	158:1c57384330a6	1036	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	158:1c57384330a6	1037	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	158:1c57384330a6	1038
AnnaBridge	158:1c57384330a6	1039	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	158:1c57384330a6	1040	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	158:1c57384330a6	1041
AnnaBridge	158:1c57384330a6	1042	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	158:1c57384330a6	1043	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	158:1c57384330a6	1044
AnnaBridge	158:1c57384330a6	1045	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	158:1c57384330a6	1046	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	158:1c57384330a6	1047	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	158:1c57384330a6	1048
AnnaBridge	158:1c57384330a6	1049	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	158:1c57384330a6	1050	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	158:1c57384330a6	1051
AnnaBridge	158:1c57384330a6	1052	/* TPI TRIGGER Register Definitions */
AnnaBridge	158:1c57384330a6	1053	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	158:1c57384330a6	1054	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	158:1c57384330a6	1055
AnnaBridge	158:1c57384330a6	1056	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	158:1c57384330a6	1057	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	158:1c57384330a6	1058	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	158:1c57384330a6	1059
AnnaBridge	158:1c57384330a6	1060	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	158:1c57384330a6	1061	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	158:1c57384330a6	1062
AnnaBridge	158:1c57384330a6	1063	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	158:1c57384330a6	1064	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	158:1c57384330a6	1065
AnnaBridge	158:1c57384330a6	1066	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	158:1c57384330a6	1067	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	158:1c57384330a6	1068
AnnaBridge	158:1c57384330a6	1069	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	158:1c57384330a6	1070	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	158:1c57384330a6	1071
AnnaBridge	158:1c57384330a6	1072	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	158:1c57384330a6	1073	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	158:1c57384330a6	1074
AnnaBridge	158:1c57384330a6	1075	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	158:1c57384330a6	1076	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	158:1c57384330a6	1077
AnnaBridge	158:1c57384330a6	1078	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	158:1c57384330a6	1079	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	158:1c57384330a6	1080	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	158:1c57384330a6	1081
AnnaBridge	158:1c57384330a6	1082	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	158:1c57384330a6	1083	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	158:1c57384330a6	1084	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	158:1c57384330a6	1085
AnnaBridge	158:1c57384330a6	1086	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	158:1c57384330a6	1087	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	158:1c57384330a6	1088
AnnaBridge	158:1c57384330a6	1089	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	158:1c57384330a6	1090	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	158:1c57384330a6	1091
AnnaBridge	158:1c57384330a6	1092	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	158:1c57384330a6	1093	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	158:1c57384330a6	1094
AnnaBridge	158:1c57384330a6	1095	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	158:1c57384330a6	1096	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	158:1c57384330a6	1097
AnnaBridge	158:1c57384330a6	1098	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	158:1c57384330a6	1099	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	158:1c57384330a6	1100
AnnaBridge	158:1c57384330a6	1101	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	158:1c57384330a6	1102	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	158:1c57384330a6	1103
AnnaBridge	158:1c57384330a6	1104	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	158:1c57384330a6	1105	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	158:1c57384330a6	1106	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	158:1c57384330a6	1107
AnnaBridge	158:1c57384330a6	1108	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	158:1c57384330a6	1109	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	158:1c57384330a6	1110	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	158:1c57384330a6	1111
AnnaBridge	158:1c57384330a6	1112	/* TPI DEVID Register Definitions */
AnnaBridge	158:1c57384330a6	1113	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	158:1c57384330a6	1114	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	158:1c57384330a6	1115
AnnaBridge	158:1c57384330a6	1116	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	158:1c57384330a6	1117	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	158:1c57384330a6	1118
AnnaBridge	158:1c57384330a6	1119	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	158:1c57384330a6	1120	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	158:1c57384330a6	1121
AnnaBridge	158:1c57384330a6	1122	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	158:1c57384330a6	1123	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	158:1c57384330a6	1124
AnnaBridge	158:1c57384330a6	1125	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	158:1c57384330a6	1126	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	158:1c57384330a6	1127
AnnaBridge	158:1c57384330a6	1128	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	158:1c57384330a6	1129	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	158:1c57384330a6	1130
AnnaBridge	158:1c57384330a6	1131	/* TPI DEVTYPE Register Definitions */
AnnaBridge	158:1c57384330a6	1132	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	158:1c57384330a6	1133	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	158:1c57384330a6	1134
AnnaBridge	158:1c57384330a6	1135	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	158:1c57384330a6	1136	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	158:1c57384330a6	1137
AnnaBridge	158:1c57384330a6	1138	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	158:1c57384330a6	1139
AnnaBridge	158:1c57384330a6	1140
AnnaBridge	158:1c57384330a6	1141	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	158:1c57384330a6	1142	/**
AnnaBridge	158:1c57384330a6	1143	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	1144	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	158:1c57384330a6	1145	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	158:1c57384330a6	1146	@{
AnnaBridge	158:1c57384330a6	1147	*/
AnnaBridge	158:1c57384330a6	1148
AnnaBridge	158:1c57384330a6	1149	/**
AnnaBridge	158:1c57384330a6	1150	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	158:1c57384330a6	1151	*/
AnnaBridge	158:1c57384330a6	1152	typedef struct
AnnaBridge	158:1c57384330a6	1153	{
AnnaBridge	158:1c57384330a6	1154	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	158:1c57384330a6	1155	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	158:1c57384330a6	1156	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	158:1c57384330a6	1157	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	158:1c57384330a6	1158	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	158:1c57384330a6	1159	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	158:1c57384330a6	1160	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	158:1c57384330a6	1161	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	158:1c57384330a6	1162	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	158:1c57384330a6	1163	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	158:1c57384330a6	1164	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
AnnaBridge	158:1c57384330a6	1165	} MPU_Type;
AnnaBridge	158:1c57384330a6	1166
Anna Bridge	160:5571c4ff569f	1167	#define MPU_TYPE_RALIASES 4U
Anna Bridge	160:5571c4ff569f	1168
AnnaBridge	158:1c57384330a6	1169	/* MPU Type Register Definitions */
AnnaBridge	158:1c57384330a6	1170	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	158:1c57384330a6	1171	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	158:1c57384330a6	1172
AnnaBridge	158:1c57384330a6	1173	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	158:1c57384330a6	1174	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	158:1c57384330a6	1175
AnnaBridge	158:1c57384330a6	1176	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	158:1c57384330a6	1177	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	158:1c57384330a6	1178
AnnaBridge	158:1c57384330a6	1179	/* MPU Control Register Definitions */
AnnaBridge	158:1c57384330a6	1180	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	158:1c57384330a6	1181	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	158:1c57384330a6	1182
AnnaBridge	158:1c57384330a6	1183	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	158:1c57384330a6	1184	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	158:1c57384330a6	1185
AnnaBridge	158:1c57384330a6	1186	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	158:1c57384330a6	1187	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	158:1c57384330a6	1188
AnnaBridge	158:1c57384330a6	1189	/* MPU Region Number Register Definitions */
AnnaBridge	158:1c57384330a6	1190	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	158:1c57384330a6	1191	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	158:1c57384330a6	1192
AnnaBridge	158:1c57384330a6	1193	/* MPU Region Base Address Register Definitions */
AnnaBridge	158:1c57384330a6	1194	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	158:1c57384330a6	1195	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	158:1c57384330a6	1196
AnnaBridge	158:1c57384330a6	1197	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
AnnaBridge	158:1c57384330a6	1198	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
AnnaBridge	158:1c57384330a6	1199
AnnaBridge	158:1c57384330a6	1200	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
AnnaBridge	158:1c57384330a6	1201	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
AnnaBridge	158:1c57384330a6	1202
AnnaBridge	158:1c57384330a6	1203	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	158:1c57384330a6	1204	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
AnnaBridge	158:1c57384330a6	1205	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
AnnaBridge	158:1c57384330a6	1206
AnnaBridge	158:1c57384330a6	1207	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
AnnaBridge	158:1c57384330a6	1208	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
AnnaBridge	158:1c57384330a6	1209
AnnaBridge	158:1c57384330a6	1210	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
AnnaBridge	158:1c57384330a6	1211	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
AnnaBridge	158:1c57384330a6	1212
AnnaBridge	158:1c57384330a6	1213	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
AnnaBridge	158:1c57384330a6	1214	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
AnnaBridge	158:1c57384330a6	1215
AnnaBridge	158:1c57384330a6	1216	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
AnnaBridge	158:1c57384330a6	1217	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
AnnaBridge	158:1c57384330a6	1218
AnnaBridge	158:1c57384330a6	1219	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
AnnaBridge	158:1c57384330a6	1220	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
AnnaBridge	158:1c57384330a6	1221
AnnaBridge	158:1c57384330a6	1222	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
AnnaBridge	158:1c57384330a6	1223	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
AnnaBridge	158:1c57384330a6	1224
AnnaBridge	158:1c57384330a6	1225	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
AnnaBridge	158:1c57384330a6	1226	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
AnnaBridge	158:1c57384330a6	1227
AnnaBridge	158:1c57384330a6	1228	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
AnnaBridge	158:1c57384330a6	1229	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
AnnaBridge	158:1c57384330a6	1230
AnnaBridge	158:1c57384330a6	1231	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
AnnaBridge	158:1c57384330a6	1232	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
AnnaBridge	158:1c57384330a6	1233
AnnaBridge	158:1c57384330a6	1234	/@} end of group CMSIS_MPU /
AnnaBridge	158:1c57384330a6	1235	#endif
AnnaBridge	158:1c57384330a6	1236
AnnaBridge	158:1c57384330a6	1237
AnnaBridge	158:1c57384330a6	1238	/**
AnnaBridge	158:1c57384330a6	1239	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	1240	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	158:1c57384330a6	1241	\brief Type definitions for the Core Debug Registers
AnnaBridge	158:1c57384330a6	1242	@{
AnnaBridge	158:1c57384330a6	1243	*/
AnnaBridge	158:1c57384330a6	1244
AnnaBridge	158:1c57384330a6	1245	/**
AnnaBridge	158:1c57384330a6	1246	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	158:1c57384330a6	1247	*/
AnnaBridge	158:1c57384330a6	1248	typedef struct
AnnaBridge	158:1c57384330a6	1249	{
AnnaBridge	158:1c57384330a6	1250	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	158:1c57384330a6	1251	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	158:1c57384330a6	1252	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	158:1c57384330a6	1253	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	158:1c57384330a6	1254	} CoreDebug_Type;
AnnaBridge	158:1c57384330a6	1255
AnnaBridge	158:1c57384330a6	1256	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	158:1c57384330a6	1257	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	158:1c57384330a6	1258	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	158:1c57384330a6	1259
AnnaBridge	158:1c57384330a6	1260	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	158:1c57384330a6	1261	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	158:1c57384330a6	1262
AnnaBridge	158:1c57384330a6	1263	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	158:1c57384330a6	1264	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	158:1c57384330a6	1265
AnnaBridge	158:1c57384330a6	1266	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	158:1c57384330a6	1267	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	158:1c57384330a6	1268
AnnaBridge	158:1c57384330a6	1269	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	158:1c57384330a6	1270	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	158:1c57384330a6	1271
AnnaBridge	158:1c57384330a6	1272	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	158:1c57384330a6	1273	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	158:1c57384330a6	1274
AnnaBridge	158:1c57384330a6	1275	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	158:1c57384330a6	1276	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	158:1c57384330a6	1277
AnnaBridge	158:1c57384330a6	1278	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	158:1c57384330a6	1279	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	158:1c57384330a6	1280
AnnaBridge	158:1c57384330a6	1281	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	158:1c57384330a6	1282	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	158:1c57384330a6	1283
AnnaBridge	158:1c57384330a6	1284	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	158:1c57384330a6	1285	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	158:1c57384330a6	1286
AnnaBridge	158:1c57384330a6	1287	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	158:1c57384330a6	1288	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	158:1c57384330a6	1289
AnnaBridge	158:1c57384330a6	1290	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	158:1c57384330a6	1291	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	158:1c57384330a6	1292
AnnaBridge	158:1c57384330a6	1293	/* Debug Core Register Selector Register Definitions */
AnnaBridge	158:1c57384330a6	1294	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	158:1c57384330a6	1295	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	158:1c57384330a6	1296
AnnaBridge	158:1c57384330a6	1297	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	158:1c57384330a6	1298	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	158:1c57384330a6	1299
AnnaBridge	158:1c57384330a6	1300	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	158:1c57384330a6	1301	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	158:1c57384330a6	1302	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	158:1c57384330a6	1303
AnnaBridge	158:1c57384330a6	1304	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	158:1c57384330a6	1305	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	158:1c57384330a6	1306
AnnaBridge	158:1c57384330a6	1307	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	158:1c57384330a6	1308	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	158:1c57384330a6	1309
AnnaBridge	158:1c57384330a6	1310	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	158:1c57384330a6	1311	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	158:1c57384330a6	1312
AnnaBridge	158:1c57384330a6	1313	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	158:1c57384330a6	1314	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	158:1c57384330a6	1315
AnnaBridge	158:1c57384330a6	1316	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	158:1c57384330a6	1317	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	158:1c57384330a6	1318
AnnaBridge	158:1c57384330a6	1319	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	158:1c57384330a6	1320	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	158:1c57384330a6	1321
AnnaBridge	158:1c57384330a6	1322	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	158:1c57384330a6	1323	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	158:1c57384330a6	1324
AnnaBridge	158:1c57384330a6	1325	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	158:1c57384330a6	1326	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	158:1c57384330a6	1327
AnnaBridge	158:1c57384330a6	1328	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	158:1c57384330a6	1329	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	158:1c57384330a6	1330
AnnaBridge	158:1c57384330a6	1331	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	158:1c57384330a6	1332	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	158:1c57384330a6	1333
AnnaBridge	158:1c57384330a6	1334	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	158:1c57384330a6	1335	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	158:1c57384330a6	1336
AnnaBridge	158:1c57384330a6	1337	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	158:1c57384330a6	1338	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	158:1c57384330a6	1339
AnnaBridge	158:1c57384330a6	1340	/@} end of group CMSIS_CoreDebug /
AnnaBridge	158:1c57384330a6	1341
AnnaBridge	158:1c57384330a6	1342
AnnaBridge	158:1c57384330a6	1343	/**
AnnaBridge	158:1c57384330a6	1344	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	1345	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	158:1c57384330a6	1346	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	158:1c57384330a6	1347	@{
AnnaBridge	158:1c57384330a6	1348	*/
AnnaBridge	158:1c57384330a6	1349
AnnaBridge	158:1c57384330a6	1350	/**
AnnaBridge	158:1c57384330a6	1351	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	158:1c57384330a6	1352	\param[in] field Name of the register bit field.
AnnaBridge	158:1c57384330a6	1353	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	158:1c57384330a6	1354	\return Masked and shifted value.
AnnaBridge	158:1c57384330a6	1355	*/
AnnaBridge	158:1c57384330a6	1356	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	158:1c57384330a6	1357
AnnaBridge	158:1c57384330a6	1358	/**
AnnaBridge	158:1c57384330a6	1359	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	158:1c57384330a6	1360	\param[in] field Name of the register bit field.
AnnaBridge	158:1c57384330a6	1361	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	158:1c57384330a6	1362	\return Masked and shifted bit field value.
AnnaBridge	158:1c57384330a6	1363	*/
AnnaBridge	158:1c57384330a6	1364	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	158:1c57384330a6	1365
AnnaBridge	158:1c57384330a6	1366	/@} end of group CMSIS_core_bitfield /
AnnaBridge	158:1c57384330a6	1367
AnnaBridge	158:1c57384330a6	1368
AnnaBridge	158:1c57384330a6	1369	/**
AnnaBridge	158:1c57384330a6	1370	\ingroup CMSIS_core_register
AnnaBridge	158:1c57384330a6	1371	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	158:1c57384330a6	1372	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	158:1c57384330a6	1373	@{
AnnaBridge	158:1c57384330a6	1374	*/
AnnaBridge	158:1c57384330a6	1375
AnnaBridge	158:1c57384330a6	1376	/* Memory mapping of Core Hardware */
AnnaBridge	158:1c57384330a6	1377	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	158:1c57384330a6	1378	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	158:1c57384330a6	1379	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	158:1c57384330a6	1380	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	158:1c57384330a6	1381	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	158:1c57384330a6	1382	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	158:1c57384330a6	1383	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	158:1c57384330a6	1384	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	158:1c57384330a6	1385
AnnaBridge	158:1c57384330a6	1386	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	158:1c57384330a6	1387	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	158:1c57384330a6	1388	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	158:1c57384330a6	1389	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	158:1c57384330a6	1390	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	158:1c57384330a6	1391	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	158:1c57384330a6	1392	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	158:1c57384330a6	1393	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	158:1c57384330a6	1394
AnnaBridge	158:1c57384330a6	1395	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	158:1c57384330a6	1396	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	158:1c57384330a6	1397	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	158:1c57384330a6	1398	#endif
AnnaBridge	158:1c57384330a6	1399
AnnaBridge	158:1c57384330a6	1400	/@} /
AnnaBridge	158:1c57384330a6	1401
AnnaBridge	158:1c57384330a6	1402
AnnaBridge	158:1c57384330a6	1403
AnnaBridge	158:1c57384330a6	1404	/*******************************************************************************
AnnaBridge	158:1c57384330a6	1405	* Hardware Abstraction Layer
AnnaBridge	158:1c57384330a6	1406	Core Function Interface contains:
AnnaBridge	158:1c57384330a6	1407	- Core NVIC Functions
AnnaBridge	158:1c57384330a6	1408	- Core SysTick Functions
AnnaBridge	158:1c57384330a6	1409	- Core Debug Functions
AnnaBridge	158:1c57384330a6	1410	- Core Register Access Functions
AnnaBridge	158:1c57384330a6	1411	******************************************************************************/
AnnaBridge	158:1c57384330a6	1412	/**
AnnaBridge	158:1c57384330a6	1413	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	158:1c57384330a6	1414	*/
AnnaBridge	158:1c57384330a6	1415
AnnaBridge	158:1c57384330a6	1416
AnnaBridge	158:1c57384330a6	1417
AnnaBridge	158:1c57384330a6	1418	/* ########################## NVIC functions #################################### */
AnnaBridge	158:1c57384330a6	1419	/**
AnnaBridge	158:1c57384330a6	1420	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	158:1c57384330a6	1421	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	158:1c57384330a6	1422	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	158:1c57384330a6	1423	@{
AnnaBridge	158:1c57384330a6	1424	*/
AnnaBridge	158:1c57384330a6	1425
AnnaBridge	158:1c57384330a6	1426	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	158:1c57384330a6	1427	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	158:1c57384330a6	1428	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	158:1c57384330a6	1429	#endif
AnnaBridge	158:1c57384330a6	1430	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	158:1c57384330a6	1431	#else
AnnaBridge	158:1c57384330a6	1432	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	158:1c57384330a6	1433	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	158:1c57384330a6	1434	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	158:1c57384330a6	1435	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	158:1c57384330a6	1436	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	158:1c57384330a6	1437	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	158:1c57384330a6	1438	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	158:1c57384330a6	1439	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	158:1c57384330a6	1440	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	158:1c57384330a6	1441	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	158:1c57384330a6	1442	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	158:1c57384330a6	1443	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	158:1c57384330a6	1444	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	158:1c57384330a6	1445
AnnaBridge	158:1c57384330a6	1446	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	158:1c57384330a6	1447	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	158:1c57384330a6	1448	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	158:1c57384330a6	1449	#endif
AnnaBridge	158:1c57384330a6	1450	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	158:1c57384330a6	1451	#else
AnnaBridge	158:1c57384330a6	1452	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	158:1c57384330a6	1453	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	158:1c57384330a6	1454	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	158:1c57384330a6	1455
AnnaBridge	158:1c57384330a6	1456	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	158:1c57384330a6	1457
AnnaBridge	158:1c57384330a6	1458
AnnaBridge	158:1c57384330a6	1459
AnnaBridge	158:1c57384330a6	1460	/**
AnnaBridge	158:1c57384330a6	1461	\brief Set Priority Grouping
AnnaBridge	158:1c57384330a6	1462	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	158:1c57384330a6	1463	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	158:1c57384330a6	1464	Only values from 0..7 are used.
AnnaBridge	158:1c57384330a6	1465	In case of a conflict between priority grouping and available
AnnaBridge	158:1c57384330a6	1466	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	158:1c57384330a6	1467	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	158:1c57384330a6	1468	*/
AnnaBridge	158:1c57384330a6	1469	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	158:1c57384330a6	1470	{
AnnaBridge	158:1c57384330a6	1471	uint32_t reg_value;
AnnaBridge	158:1c57384330a6	1472	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	158:1c57384330a6	1473
AnnaBridge	158:1c57384330a6	1474	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	158:1c57384330a6	1475	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	158:1c57384330a6	1476	reg_value = (reg_value \|
AnnaBridge	158:1c57384330a6	1477	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	158:1c57384330a6	1478	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge	158:1c57384330a6	1479	SCB->AIRCR = reg_value;
AnnaBridge	158:1c57384330a6	1480	}
AnnaBridge	158:1c57384330a6	1481
AnnaBridge	158:1c57384330a6	1482
AnnaBridge	158:1c57384330a6	1483	/**
AnnaBridge	158:1c57384330a6	1484	\brief Get Priority Grouping
AnnaBridge	158:1c57384330a6	1485	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	158:1c57384330a6	1486	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	158:1c57384330a6	1487	*/
AnnaBridge	158:1c57384330a6	1488	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	158:1c57384330a6	1489	{
AnnaBridge	158:1c57384330a6	1490	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	158:1c57384330a6	1491	}
AnnaBridge	158:1c57384330a6	1492
AnnaBridge	158:1c57384330a6	1493
AnnaBridge	158:1c57384330a6	1494	/**
AnnaBridge	158:1c57384330a6	1495	\brief Enable Interrupt
AnnaBridge	158:1c57384330a6	1496	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	158:1c57384330a6	1497	\param [in] IRQn Device specific interrupt number.
AnnaBridge	158:1c57384330a6	1498	\note IRQn must not be negative.
AnnaBridge	158:1c57384330a6	1499	*/
AnnaBridge	158:1c57384330a6	1500	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1501	{
AnnaBridge	158:1c57384330a6	1502	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1503	{
AnnaBridge	158:1c57384330a6	1504	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	158:1c57384330a6	1505	}
AnnaBridge	158:1c57384330a6	1506	}
AnnaBridge	158:1c57384330a6	1507
AnnaBridge	158:1c57384330a6	1508
AnnaBridge	158:1c57384330a6	1509	/**
AnnaBridge	158:1c57384330a6	1510	\brief Get Interrupt Enable status
AnnaBridge	158:1c57384330a6	1511	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	158:1c57384330a6	1512	\param [in] IRQn Device specific interrupt number.
AnnaBridge	158:1c57384330a6	1513	\return 0 Interrupt is not enabled.
AnnaBridge	158:1c57384330a6	1514	\return 1 Interrupt is enabled.
AnnaBridge	158:1c57384330a6	1515	\note IRQn must not be negative.
AnnaBridge	158:1c57384330a6	1516	*/
AnnaBridge	158:1c57384330a6	1517	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1518	{
AnnaBridge	158:1c57384330a6	1519	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1520	{
AnnaBridge	158:1c57384330a6	1521	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	158:1c57384330a6	1522	}
AnnaBridge	158:1c57384330a6	1523	else
AnnaBridge	158:1c57384330a6	1524	{
AnnaBridge	158:1c57384330a6	1525	return(0U);
AnnaBridge	158:1c57384330a6	1526	}
AnnaBridge	158:1c57384330a6	1527	}
AnnaBridge	158:1c57384330a6	1528
AnnaBridge	158:1c57384330a6	1529
AnnaBridge	158:1c57384330a6	1530	/**
AnnaBridge	158:1c57384330a6	1531	\brief Disable Interrupt
AnnaBridge	158:1c57384330a6	1532	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	158:1c57384330a6	1533	\param [in] IRQn Device specific interrupt number.
AnnaBridge	158:1c57384330a6	1534	\note IRQn must not be negative.
AnnaBridge	158:1c57384330a6	1535	*/
AnnaBridge	158:1c57384330a6	1536	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1537	{
AnnaBridge	158:1c57384330a6	1538	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1539	{
AnnaBridge	158:1c57384330a6	1540	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	158:1c57384330a6	1541	__DSB();
AnnaBridge	158:1c57384330a6	1542	__ISB();
AnnaBridge	158:1c57384330a6	1543	}
AnnaBridge	158:1c57384330a6	1544	}
AnnaBridge	158:1c57384330a6	1545
AnnaBridge	158:1c57384330a6	1546
AnnaBridge	158:1c57384330a6	1547	/**
AnnaBridge	158:1c57384330a6	1548	\brief Get Pending Interrupt
AnnaBridge	158:1c57384330a6	1549	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	158:1c57384330a6	1550	\param [in] IRQn Device specific interrupt number.
AnnaBridge	158:1c57384330a6	1551	\return 0 Interrupt status is not pending.
AnnaBridge	158:1c57384330a6	1552	\return 1 Interrupt status is pending.
AnnaBridge	158:1c57384330a6	1553	\note IRQn must not be negative.
AnnaBridge	158:1c57384330a6	1554	*/
AnnaBridge	158:1c57384330a6	1555	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1556	{
AnnaBridge	158:1c57384330a6	1557	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1558	{
AnnaBridge	158:1c57384330a6	1559	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	158:1c57384330a6	1560	}
AnnaBridge	158:1c57384330a6	1561	else
AnnaBridge	158:1c57384330a6	1562	{
AnnaBridge	158:1c57384330a6	1563	return(0U);
AnnaBridge	158:1c57384330a6	1564	}
AnnaBridge	158:1c57384330a6	1565	}
AnnaBridge	158:1c57384330a6	1566
AnnaBridge	158:1c57384330a6	1567
AnnaBridge	158:1c57384330a6	1568	/**
AnnaBridge	158:1c57384330a6	1569	\brief Set Pending Interrupt
AnnaBridge	158:1c57384330a6	1570	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	158:1c57384330a6	1571	\param [in] IRQn Device specific interrupt number.
AnnaBridge	158:1c57384330a6	1572	\note IRQn must not be negative.
AnnaBridge	158:1c57384330a6	1573	*/
AnnaBridge	158:1c57384330a6	1574	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1575	{
AnnaBridge	158:1c57384330a6	1576	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1577	{
AnnaBridge	158:1c57384330a6	1578	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	158:1c57384330a6	1579	}
AnnaBridge	158:1c57384330a6	1580	}
AnnaBridge	158:1c57384330a6	1581
AnnaBridge	158:1c57384330a6	1582
AnnaBridge	158:1c57384330a6	1583	/**
AnnaBridge	158:1c57384330a6	1584	\brief Clear Pending Interrupt
AnnaBridge	158:1c57384330a6	1585	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	158:1c57384330a6	1586	\param [in] IRQn Device specific interrupt number.
AnnaBridge	158:1c57384330a6	1587	\note IRQn must not be negative.
AnnaBridge	158:1c57384330a6	1588	*/
AnnaBridge	158:1c57384330a6	1589	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1590	{
AnnaBridge	158:1c57384330a6	1591	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1592	{
AnnaBridge	158:1c57384330a6	1593	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	158:1c57384330a6	1594	}
AnnaBridge	158:1c57384330a6	1595	}
AnnaBridge	158:1c57384330a6	1596
AnnaBridge	158:1c57384330a6	1597
AnnaBridge	158:1c57384330a6	1598	/**
AnnaBridge	158:1c57384330a6	1599	\brief Get Active Interrupt
AnnaBridge	158:1c57384330a6	1600	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	158:1c57384330a6	1601	\param [in] IRQn Device specific interrupt number.
AnnaBridge	158:1c57384330a6	1602	\return 0 Interrupt status is not active.
AnnaBridge	158:1c57384330a6	1603	\return 1 Interrupt status is active.
AnnaBridge	158:1c57384330a6	1604	\note IRQn must not be negative.
AnnaBridge	158:1c57384330a6	1605	*/
AnnaBridge	158:1c57384330a6	1606	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1607	{
AnnaBridge	158:1c57384330a6	1608	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1609	{
AnnaBridge	158:1c57384330a6	1610	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	158:1c57384330a6	1611	}
AnnaBridge	158:1c57384330a6	1612	else
AnnaBridge	158:1c57384330a6	1613	{
AnnaBridge	158:1c57384330a6	1614	return(0U);
AnnaBridge	158:1c57384330a6	1615	}
AnnaBridge	158:1c57384330a6	1616	}
AnnaBridge	158:1c57384330a6	1617
AnnaBridge	158:1c57384330a6	1618
AnnaBridge	158:1c57384330a6	1619	/**
AnnaBridge	158:1c57384330a6	1620	\brief Set Interrupt Priority
AnnaBridge	158:1c57384330a6	1621	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	158:1c57384330a6	1622	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	158:1c57384330a6	1623	or negative to specify a processor exception.
AnnaBridge	158:1c57384330a6	1624	\param [in] IRQn Interrupt number.
AnnaBridge	158:1c57384330a6	1625	\param [in] priority Priority to set.
AnnaBridge	158:1c57384330a6	1626	\note The priority cannot be set for every processor exception.
AnnaBridge	158:1c57384330a6	1627	*/
AnnaBridge	158:1c57384330a6	1628	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	158:1c57384330a6	1629	{
AnnaBridge	158:1c57384330a6	1630	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1631	{
AnnaBridge	158:1c57384330a6	1632	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	158:1c57384330a6	1633	}
AnnaBridge	158:1c57384330a6	1634	else
AnnaBridge	158:1c57384330a6	1635	{
AnnaBridge	158:1c57384330a6	1636	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	158:1c57384330a6	1637	}
AnnaBridge	158:1c57384330a6	1638	}
AnnaBridge	158:1c57384330a6	1639
AnnaBridge	158:1c57384330a6	1640
AnnaBridge	158:1c57384330a6	1641	/**
AnnaBridge	158:1c57384330a6	1642	\brief Get Interrupt Priority
AnnaBridge	158:1c57384330a6	1643	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	158:1c57384330a6	1644	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	158:1c57384330a6	1645	or negative to specify a processor exception.
AnnaBridge	158:1c57384330a6	1646	\param [in] IRQn Interrupt number.
AnnaBridge	158:1c57384330a6	1647	\return Interrupt Priority.
AnnaBridge	158:1c57384330a6	1648	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	158:1c57384330a6	1649	*/
AnnaBridge	158:1c57384330a6	1650	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1651	{
AnnaBridge	158:1c57384330a6	1652
AnnaBridge	158:1c57384330a6	1653	if ((int32_t)(IRQn) >= 0)
AnnaBridge	158:1c57384330a6	1654	{
AnnaBridge	158:1c57384330a6	1655	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	158:1c57384330a6	1656	}
AnnaBridge	158:1c57384330a6	1657	else
AnnaBridge	158:1c57384330a6	1658	{
AnnaBridge	158:1c57384330a6	1659	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	158:1c57384330a6	1660	}
AnnaBridge	158:1c57384330a6	1661	}
AnnaBridge	158:1c57384330a6	1662
AnnaBridge	158:1c57384330a6	1663
AnnaBridge	158:1c57384330a6	1664	/**
AnnaBridge	158:1c57384330a6	1665	\brief Encode Priority
AnnaBridge	158:1c57384330a6	1666	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	158:1c57384330a6	1667	preemptive priority value, and subpriority value.
AnnaBridge	158:1c57384330a6	1668	In case of a conflict between priority grouping and available
AnnaBridge	158:1c57384330a6	1669	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	158:1c57384330a6	1670	\param [in] PriorityGroup Used priority group.
AnnaBridge	158:1c57384330a6	1671	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	158:1c57384330a6	1672	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	158:1c57384330a6	1673	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	158:1c57384330a6	1674	*/
AnnaBridge	158:1c57384330a6	1675	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	158:1c57384330a6	1676	{
AnnaBridge	158:1c57384330a6	1677	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	158:1c57384330a6	1678	uint32_t PreemptPriorityBits;
AnnaBridge	158:1c57384330a6	1679	uint32_t SubPriorityBits;
AnnaBridge	158:1c57384330a6	1680
AnnaBridge	158:1c57384330a6	1681	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	158:1c57384330a6	1682	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	158:1c57384330a6	1683
AnnaBridge	158:1c57384330a6	1684	return (
AnnaBridge	158:1c57384330a6	1685	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	158:1c57384330a6	1686	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	158:1c57384330a6	1687	);
AnnaBridge	158:1c57384330a6	1688	}
AnnaBridge	158:1c57384330a6	1689
AnnaBridge	158:1c57384330a6	1690
AnnaBridge	158:1c57384330a6	1691	/**
AnnaBridge	158:1c57384330a6	1692	\brief Decode Priority
AnnaBridge	158:1c57384330a6	1693	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	158:1c57384330a6	1694	preemptive priority value and subpriority value.
AnnaBridge	158:1c57384330a6	1695	In case of a conflict between priority grouping and available
AnnaBridge	158:1c57384330a6	1696	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	158:1c57384330a6	1697	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	158:1c57384330a6	1698	\param [in] PriorityGroup Used priority group.
AnnaBridge	158:1c57384330a6	1699	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	158:1c57384330a6	1700	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	158:1c57384330a6	1701	*/
AnnaBridge	158:1c57384330a6	1702	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	158:1c57384330a6	1703	{
AnnaBridge	158:1c57384330a6	1704	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	158:1c57384330a6	1705	uint32_t PreemptPriorityBits;
AnnaBridge	158:1c57384330a6	1706	uint32_t SubPriorityBits;
AnnaBridge	158:1c57384330a6	1707
AnnaBridge	158:1c57384330a6	1708	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	158:1c57384330a6	1709	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	158:1c57384330a6	1710
AnnaBridge	158:1c57384330a6	1711	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	158:1c57384330a6	1712	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	158:1c57384330a6	1713	}
AnnaBridge	158:1c57384330a6	1714
AnnaBridge	158:1c57384330a6	1715
AnnaBridge	158:1c57384330a6	1716	/**
AnnaBridge	158:1c57384330a6	1717	\brief Set Interrupt Vector
AnnaBridge	158:1c57384330a6	1718	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	158:1c57384330a6	1719	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	158:1c57384330a6	1720	or negative to specify a processor exception.
AnnaBridge	158:1c57384330a6	1721	VTOR must been relocated to SRAM before.
AnnaBridge	158:1c57384330a6	1722	\param [in] IRQn Interrupt number
AnnaBridge	158:1c57384330a6	1723	\param [in] vector Address of interrupt handler function
AnnaBridge	158:1c57384330a6	1724	*/
AnnaBridge	158:1c57384330a6	1725	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	158:1c57384330a6	1726	{
AnnaBridge	158:1c57384330a6	1727	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	158:1c57384330a6	1728	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	158:1c57384330a6	1729	}
AnnaBridge	158:1c57384330a6	1730
AnnaBridge	158:1c57384330a6	1731
AnnaBridge	158:1c57384330a6	1732	/**
AnnaBridge	158:1c57384330a6	1733	\brief Get Interrupt Vector
AnnaBridge	158:1c57384330a6	1734	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	158:1c57384330a6	1735	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	158:1c57384330a6	1736	or negative to specify a processor exception.
AnnaBridge	158:1c57384330a6	1737	\param [in] IRQn Interrupt number.
AnnaBridge	158:1c57384330a6	1738	\return Address of interrupt handler function
AnnaBridge	158:1c57384330a6	1739	*/
AnnaBridge	158:1c57384330a6	1740	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	158:1c57384330a6	1741	{
AnnaBridge	158:1c57384330a6	1742	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	158:1c57384330a6	1743	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	158:1c57384330a6	1744	}
AnnaBridge	158:1c57384330a6	1745
AnnaBridge	158:1c57384330a6	1746
AnnaBridge	158:1c57384330a6	1747	/**
AnnaBridge	158:1c57384330a6	1748	\brief System Reset
AnnaBridge	158:1c57384330a6	1749	\details Initiates a system reset request to reset the MCU.
AnnaBridge	158:1c57384330a6	1750	*/
AnnaBridge	158:1c57384330a6	1751	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	158:1c57384330a6	1752	{
AnnaBridge	158:1c57384330a6	1753	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	158:1c57384330a6	1754	buffered write are completed before reset */
AnnaBridge	158:1c57384330a6	1755	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	158:1c57384330a6	1756	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	158:1c57384330a6	1757	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	158:1c57384330a6	1758	__DSB(); /* Ensure completion of memory access */
AnnaBridge	158:1c57384330a6	1759
AnnaBridge	158:1c57384330a6	1760	for(;;) /* wait until reset */
AnnaBridge	158:1c57384330a6	1761	{
AnnaBridge	158:1c57384330a6	1762	__NOP();
AnnaBridge	158:1c57384330a6	1763	}
AnnaBridge	158:1c57384330a6	1764	}
AnnaBridge	158:1c57384330a6	1765
AnnaBridge	158:1c57384330a6	1766	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	158:1c57384330a6	1767
Anna Bridge	160:5571c4ff569f	1768	/* ########################## MPU functions #################################### */
Anna Bridge	160:5571c4ff569f	1769
Anna Bridge	160:5571c4ff569f	1770	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	1771
Anna Bridge	160:5571c4ff569f	1772	#include "mpu_armv7.h"
Anna Bridge	160:5571c4ff569f	1773
Anna Bridge	160:5571c4ff569f	1774	#endif
AnnaBridge	158:1c57384330a6	1775
AnnaBridge	158:1c57384330a6	1776	/* ########################## FPU functions #################################### */
AnnaBridge	158:1c57384330a6	1777	/**
AnnaBridge	158:1c57384330a6	1778	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	158:1c57384330a6	1779	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	158:1c57384330a6	1780	\brief Function that provides FPU type.
AnnaBridge	158:1c57384330a6	1781	@{
AnnaBridge	158:1c57384330a6	1782	*/
AnnaBridge	158:1c57384330a6	1783
AnnaBridge	158:1c57384330a6	1784	/**
AnnaBridge	158:1c57384330a6	1785	\brief get FPU type
AnnaBridge	158:1c57384330a6	1786	\details returns the FPU type
AnnaBridge	158:1c57384330a6	1787	\returns
AnnaBridge	158:1c57384330a6	1788	- \b 0: No FPU
AnnaBridge	158:1c57384330a6	1789	- \b 1: Single precision FPU
AnnaBridge	158:1c57384330a6	1790	- \b 2: Double + Single precision FPU
AnnaBridge	158:1c57384330a6	1791	*/
AnnaBridge	158:1c57384330a6	1792	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	158:1c57384330a6	1793	{
AnnaBridge	158:1c57384330a6	1794	return 0U; /* No FPU */
AnnaBridge	158:1c57384330a6	1795	}
AnnaBridge	158:1c57384330a6	1796
AnnaBridge	158:1c57384330a6	1797
AnnaBridge	158:1c57384330a6	1798	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	158:1c57384330a6	1799
AnnaBridge	158:1c57384330a6	1800
AnnaBridge	158:1c57384330a6	1801
AnnaBridge	158:1c57384330a6	1802	/* ################################## SysTick function ############################################ */
AnnaBridge	158:1c57384330a6	1803	/**
AnnaBridge	158:1c57384330a6	1804	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	158:1c57384330a6	1805	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	158:1c57384330a6	1806	\brief Functions that configure the System.
AnnaBridge	158:1c57384330a6	1807	@{
AnnaBridge	158:1c57384330a6	1808	*/
AnnaBridge	158:1c57384330a6	1809
AnnaBridge	158:1c57384330a6	1810	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	158:1c57384330a6	1811
AnnaBridge	158:1c57384330a6	1812	/**
AnnaBridge	158:1c57384330a6	1813	\brief System Tick Configuration
AnnaBridge	158:1c57384330a6	1814	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	158:1c57384330a6	1815	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	158:1c57384330a6	1816	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	158:1c57384330a6	1817	\return 0 Function succeeded.
AnnaBridge	158:1c57384330a6	1818	\return 1 Function failed.
AnnaBridge	158:1c57384330a6	1819	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	158:1c57384330a6	1820	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	158:1c57384330a6	1821	must contain a vendor-specific implementation of this function.
AnnaBridge	158:1c57384330a6	1822	*/
AnnaBridge	158:1c57384330a6	1823	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	158:1c57384330a6	1824	{
AnnaBridge	158:1c57384330a6	1825	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	158:1c57384330a6	1826	{
AnnaBridge	158:1c57384330a6	1827	return (1UL); /* Reload value impossible */
AnnaBridge	158:1c57384330a6	1828	}
AnnaBridge	158:1c57384330a6	1829
AnnaBridge	158:1c57384330a6	1830	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	158:1c57384330a6	1831	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	158:1c57384330a6	1832	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	158:1c57384330a6	1833	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	158:1c57384330a6	1834	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	158:1c57384330a6	1835	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	158:1c57384330a6	1836	return (0UL); /* Function successful */
AnnaBridge	158:1c57384330a6	1837	}
AnnaBridge	158:1c57384330a6	1838
AnnaBridge	158:1c57384330a6	1839	#endif
AnnaBridge	158:1c57384330a6	1840
AnnaBridge	158:1c57384330a6	1841	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	158:1c57384330a6	1842
AnnaBridge	158:1c57384330a6	1843
AnnaBridge	158:1c57384330a6	1844
AnnaBridge	158:1c57384330a6	1845	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	158:1c57384330a6	1846	/**
AnnaBridge	158:1c57384330a6	1847	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	158:1c57384330a6	1848	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	158:1c57384330a6	1849	\brief Functions that access the ITM debug interface.
AnnaBridge	158:1c57384330a6	1850	@{
AnnaBridge	158:1c57384330a6	1851	*/
AnnaBridge	158:1c57384330a6	1852
AnnaBridge	158:1c57384330a6	1853	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	158:1c57384330a6	1854	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	158:1c57384330a6	1855
AnnaBridge	158:1c57384330a6	1856
AnnaBridge	158:1c57384330a6	1857	/**
AnnaBridge	158:1c57384330a6	1858	\brief ITM Send Character
AnnaBridge	158:1c57384330a6	1859	\details Transmits a character via the ITM channel 0, and
AnnaBridge	158:1c57384330a6	1860	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	158:1c57384330a6	1861	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	158:1c57384330a6	1862	\param [in] ch Character to transmit.
AnnaBridge	158:1c57384330a6	1863	\returns Character to transmit.
AnnaBridge	158:1c57384330a6	1864	*/
AnnaBridge	158:1c57384330a6	1865	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	158:1c57384330a6	1866	{
AnnaBridge	158:1c57384330a6	1867	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	158:1c57384330a6	1868	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	158:1c57384330a6	1869	{
AnnaBridge	158:1c57384330a6	1870	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	158:1c57384330a6	1871	{
AnnaBridge	158:1c57384330a6	1872	__NOP();
AnnaBridge	158:1c57384330a6	1873	}
AnnaBridge	158:1c57384330a6	1874	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	158:1c57384330a6	1875	}
AnnaBridge	158:1c57384330a6	1876	return (ch);
AnnaBridge	158:1c57384330a6	1877	}
AnnaBridge	158:1c57384330a6	1878
AnnaBridge	158:1c57384330a6	1879
AnnaBridge	158:1c57384330a6	1880	/**
AnnaBridge	158:1c57384330a6	1881	\brief ITM Receive Character
AnnaBridge	158:1c57384330a6	1882	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	158:1c57384330a6	1883	\return Received character.
AnnaBridge	158:1c57384330a6	1884	\return -1 No character pending.
AnnaBridge	158:1c57384330a6	1885	*/
AnnaBridge	158:1c57384330a6	1886	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	158:1c57384330a6	1887	{
AnnaBridge	158:1c57384330a6	1888	int32_t ch = -1; /* no character available */
AnnaBridge	158:1c57384330a6	1889
AnnaBridge	158:1c57384330a6	1890	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	158:1c57384330a6	1891	{
AnnaBridge	158:1c57384330a6	1892	ch = ITM_RxBuffer;
AnnaBridge	158:1c57384330a6	1893	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	158:1c57384330a6	1894	}
AnnaBridge	158:1c57384330a6	1895
AnnaBridge	158:1c57384330a6	1896	return (ch);
AnnaBridge	158:1c57384330a6	1897	}
AnnaBridge	158:1c57384330a6	1898
AnnaBridge	158:1c57384330a6	1899
AnnaBridge	158:1c57384330a6	1900	/**
AnnaBridge	158:1c57384330a6	1901	\brief ITM Check Character
AnnaBridge	158:1c57384330a6	1902	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	158:1c57384330a6	1903	\return 0 No character available.
AnnaBridge	158:1c57384330a6	1904	\return 1 Character available.
AnnaBridge	158:1c57384330a6	1905	*/
AnnaBridge	158:1c57384330a6	1906	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	158:1c57384330a6	1907	{
AnnaBridge	158:1c57384330a6	1908
AnnaBridge	158:1c57384330a6	1909	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	158:1c57384330a6	1910	{
AnnaBridge	158:1c57384330a6	1911	return (0); /* no character available */
AnnaBridge	158:1c57384330a6	1912	}
AnnaBridge	158:1c57384330a6	1913	else
AnnaBridge	158:1c57384330a6	1914	{
AnnaBridge	158:1c57384330a6	1915	return (1); /* character available */
AnnaBridge	158:1c57384330a6	1916	}
AnnaBridge	158:1c57384330a6	1917	}
AnnaBridge	158:1c57384330a6	1918
AnnaBridge	158:1c57384330a6	1919	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	158:1c57384330a6	1920
AnnaBridge	158:1c57384330a6	1921
AnnaBridge	158:1c57384330a6	1922
AnnaBridge	158:1c57384330a6	1923
AnnaBridge	158:1c57384330a6	1924	#ifdef __cplusplus
AnnaBridge	158:1c57384330a6	1925	}
AnnaBridge	158:1c57384330a6	1926	#endif
AnnaBridge	158:1c57384330a6	1927
AnnaBridge	158:1c57384330a6	1928	#endif /* __CORE_CM3_H_DEPENDANT */
AnnaBridge	158:1c57384330a6	1929
AnnaBridge	158:1c57384330a6	1930	#endif /* __CMSIS_GENERIC */