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TARGET_NUCLEO_F401RE/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f401xe.h@160:5571c4ff569f, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 16:13:02 2018 +0000
Revision:
160:5571c4ff569f
Parent:
156:ff21514d8981
Child:
163:e59c8e839560
mbed library. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32f401xe.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V2.6.1
AnnaBridge 156:ff21514d8981 6 * @date 14-February-2017
AnnaBridge 156:ff21514d8981 7 * @brief CMSIS STM32F401xE Device Peripheral Access Layer Header File.
AnnaBridge 156:ff21514d8981 8 *
AnnaBridge 156:ff21514d8981 9 * This file contains:
AnnaBridge 156:ff21514d8981 10 * - Data structures and the address mapping for all peripherals
AnnaBridge 156:ff21514d8981 11 * - peripherals registers declarations and bits definition
AnnaBridge 156:ff21514d8981 12 * - Macros to access peripheral's registers hardware
AnnaBridge 156:ff21514d8981 13 *
AnnaBridge 156:ff21514d8981 14 ******************************************************************************
AnnaBridge 156:ff21514d8981 15 * @attention
AnnaBridge 156:ff21514d8981 16 *
AnnaBridge 156:ff21514d8981 17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 18 *
AnnaBridge 156:ff21514d8981 19 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 20 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 21 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 22 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 24 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 25 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 27 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 28 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 29 *
AnnaBridge 156:ff21514d8981 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 40 *
AnnaBridge 156:ff21514d8981 41 ******************************************************************************
AnnaBridge 156:ff21514d8981 42 */
AnnaBridge 156:ff21514d8981 43
AnnaBridge 156:ff21514d8981 44 /** @addtogroup CMSIS_Device
AnnaBridge 156:ff21514d8981 45 * @{
AnnaBridge 156:ff21514d8981 46 */
AnnaBridge 156:ff21514d8981 47
AnnaBridge 156:ff21514d8981 48 /** @addtogroup stm32f401xe
AnnaBridge 156:ff21514d8981 49 * @{
AnnaBridge 156:ff21514d8981 50 */
AnnaBridge 156:ff21514d8981 51
AnnaBridge 156:ff21514d8981 52 #ifndef __STM32F401xE_H
AnnaBridge 156:ff21514d8981 53 #define __STM32F401xE_H
AnnaBridge 156:ff21514d8981 54
AnnaBridge 156:ff21514d8981 55 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 56 extern "C" {
AnnaBridge 156:ff21514d8981 57 #endif /* __cplusplus */
AnnaBridge 156:ff21514d8981 58
AnnaBridge 156:ff21514d8981 59 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 156:ff21514d8981 60 * @{
AnnaBridge 156:ff21514d8981 61 */
AnnaBridge 156:ff21514d8981 62
AnnaBridge 156:ff21514d8981 63 /**
AnnaBridge 156:ff21514d8981 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
AnnaBridge 156:ff21514d8981 65 */
AnnaBridge 156:ff21514d8981 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
AnnaBridge 156:ff21514d8981 67 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
AnnaBridge 156:ff21514d8981 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
AnnaBridge 156:ff21514d8981 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 156:ff21514d8981 70 #ifndef __FPU_PRESENT
AnnaBridge 156:ff21514d8981 71 #define __FPU_PRESENT 1U /*!< FPU present */
AnnaBridge 156:ff21514d8981 72 #endif /* __FPU_PRESENT */
AnnaBridge 156:ff21514d8981 73
AnnaBridge 156:ff21514d8981 74 /**
AnnaBridge 156:ff21514d8981 75 * @}
AnnaBridge 156:ff21514d8981 76 */
AnnaBridge 156:ff21514d8981 77
AnnaBridge 156:ff21514d8981 78 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 156:ff21514d8981 79 * @{
AnnaBridge 156:ff21514d8981 80 */
AnnaBridge 156:ff21514d8981 81
AnnaBridge 156:ff21514d8981 82 /**
AnnaBridge 156:ff21514d8981 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
AnnaBridge 156:ff21514d8981 84 * in @ref Library_configuration_section
AnnaBridge 156:ff21514d8981 85 */
AnnaBridge 156:ff21514d8981 86 typedef enum
AnnaBridge 156:ff21514d8981 87 {
AnnaBridge 156:ff21514d8981 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 156:ff21514d8981 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 156:ff21514d8981 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 156:ff21514d8981 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 156:ff21514d8981 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 156:ff21514d8981 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 156:ff21514d8981 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 156:ff21514d8981 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 156:ff21514d8981 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 156:ff21514d8981 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 156:ff21514d8981 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 156:ff21514d8981 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 156:ff21514d8981 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 156:ff21514d8981 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 156:ff21514d8981 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 156:ff21514d8981 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 156:ff21514d8981 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 156:ff21514d8981 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 156:ff21514d8981 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 156:ff21514d8981 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 156:ff21514d8981 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 156:ff21514d8981 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
AnnaBridge 156:ff21514d8981 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
AnnaBridge 156:ff21514d8981 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
AnnaBridge 156:ff21514d8981 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
AnnaBridge 156:ff21514d8981 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
AnnaBridge 156:ff21514d8981 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
AnnaBridge 156:ff21514d8981 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
AnnaBridge 156:ff21514d8981 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
AnnaBridge 156:ff21514d8981 117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 156:ff21514d8981 118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
AnnaBridge 156:ff21514d8981 119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
AnnaBridge 156:ff21514d8981 120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
AnnaBridge 156:ff21514d8981 121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 156:ff21514d8981 122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 156:ff21514d8981 123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 156:ff21514d8981 124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
AnnaBridge 156:ff21514d8981 125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 156:ff21514d8981 126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 156:ff21514d8981 127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 156:ff21514d8981 128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 156:ff21514d8981 129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 156:ff21514d8981 130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 156:ff21514d8981 131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 156:ff21514d8981 132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 156:ff21514d8981 133 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 156:ff21514d8981 134 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 156:ff21514d8981 135 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
AnnaBridge 156:ff21514d8981 136 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
AnnaBridge 156:ff21514d8981 137 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
AnnaBridge 156:ff21514d8981 138 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
AnnaBridge 156:ff21514d8981 139 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
AnnaBridge 156:ff21514d8981 140 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
AnnaBridge 156:ff21514d8981 141 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
AnnaBridge 156:ff21514d8981 142 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
AnnaBridge 156:ff21514d8981 143 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
AnnaBridge 156:ff21514d8981 144 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
AnnaBridge 156:ff21514d8981 145 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
AnnaBridge 156:ff21514d8981 146 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
AnnaBridge 156:ff21514d8981 147 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
AnnaBridge 156:ff21514d8981 148 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
AnnaBridge 156:ff21514d8981 149 USART6_IRQn = 71, /*!< USART6 global interrupt */
AnnaBridge 156:ff21514d8981 150 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
AnnaBridge 156:ff21514d8981 151 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 156:ff21514d8981 152 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 156:ff21514d8981 153 SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
AnnaBridge 156:ff21514d8981 154 } IRQn_Type;
AnnaBridge 156:ff21514d8981 155
AnnaBridge 156:ff21514d8981 156 /**
AnnaBridge 156:ff21514d8981 157 * @}
AnnaBridge 156:ff21514d8981 158 */
AnnaBridge 156:ff21514d8981 159
AnnaBridge 156:ff21514d8981 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 156:ff21514d8981 161 #include "system_stm32f4xx.h"
AnnaBridge 156:ff21514d8981 162 #include <stdint.h>
AnnaBridge 156:ff21514d8981 163
AnnaBridge 156:ff21514d8981 164 /** @addtogroup Peripheral_registers_structures
AnnaBridge 156:ff21514d8981 165 * @{
AnnaBridge 156:ff21514d8981 166 */
AnnaBridge 156:ff21514d8981 167
AnnaBridge 156:ff21514d8981 168 /**
AnnaBridge 156:ff21514d8981 169 * @brief Analog to Digital Converter
AnnaBridge 156:ff21514d8981 170 */
AnnaBridge 156:ff21514d8981 171
AnnaBridge 156:ff21514d8981 172 typedef struct
AnnaBridge 156:ff21514d8981 173 {
AnnaBridge 156:ff21514d8981 174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
AnnaBridge 156:ff21514d8981 182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
AnnaBridge 156:ff21514d8981 183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
AnnaBridge 156:ff21514d8981 184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
AnnaBridge 156:ff21514d8981 185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
AnnaBridge 156:ff21514d8981 186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
AnnaBridge 156:ff21514d8981 187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
AnnaBridge 156:ff21514d8981 188 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
AnnaBridge 156:ff21514d8981 189 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
AnnaBridge 156:ff21514d8981 190 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
AnnaBridge 156:ff21514d8981 191 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
AnnaBridge 156:ff21514d8981 192 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
AnnaBridge 156:ff21514d8981 193 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
AnnaBridge 156:ff21514d8981 194 } ADC_TypeDef;
AnnaBridge 156:ff21514d8981 195
AnnaBridge 156:ff21514d8981 196 typedef struct
AnnaBridge 156:ff21514d8981 197 {
AnnaBridge 156:ff21514d8981 198 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
AnnaBridge 156:ff21514d8981 199 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
AnnaBridge 156:ff21514d8981 200 __IO uint32_t CDR; /*!< ADC common regular data register for dual
AnnaBridge 156:ff21514d8981 201 AND triple modes, Address offset: ADC1 base address + 0x308 */
AnnaBridge 156:ff21514d8981 202 } ADC_Common_TypeDef;
AnnaBridge 156:ff21514d8981 203
AnnaBridge 156:ff21514d8981 204 /**
AnnaBridge 156:ff21514d8981 205 * @brief CRC calculation unit
AnnaBridge 156:ff21514d8981 206 */
AnnaBridge 156:ff21514d8981 207
AnnaBridge 156:ff21514d8981 208 typedef struct
AnnaBridge 156:ff21514d8981 209 {
AnnaBridge 156:ff21514d8981 210 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 211 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 212 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 156:ff21514d8981 213 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 156:ff21514d8981 214 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 215 } CRC_TypeDef;
AnnaBridge 156:ff21514d8981 216
AnnaBridge 156:ff21514d8981 217 /**
AnnaBridge 156:ff21514d8981 218 * @brief Debug MCU
AnnaBridge 156:ff21514d8981 219 */
AnnaBridge 156:ff21514d8981 220
AnnaBridge 156:ff21514d8981 221 typedef struct
AnnaBridge 156:ff21514d8981 222 {
AnnaBridge 156:ff21514d8981 223 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 224 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 225 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 226 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 227 }DBGMCU_TypeDef;
AnnaBridge 156:ff21514d8981 228
AnnaBridge 156:ff21514d8981 229
AnnaBridge 156:ff21514d8981 230 /**
AnnaBridge 156:ff21514d8981 231 * @brief DMA Controller
AnnaBridge 156:ff21514d8981 232 */
AnnaBridge 156:ff21514d8981 233
AnnaBridge 156:ff21514d8981 234 typedef struct
AnnaBridge 156:ff21514d8981 235 {
AnnaBridge 156:ff21514d8981 236 __IO uint32_t CR; /*!< DMA stream x configuration register */
AnnaBridge 156:ff21514d8981 237 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
AnnaBridge 156:ff21514d8981 238 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
AnnaBridge 156:ff21514d8981 239 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
AnnaBridge 156:ff21514d8981 240 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
AnnaBridge 156:ff21514d8981 241 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
AnnaBridge 156:ff21514d8981 242 } DMA_Stream_TypeDef;
AnnaBridge 156:ff21514d8981 243
AnnaBridge 156:ff21514d8981 244 typedef struct
AnnaBridge 156:ff21514d8981 245 {
AnnaBridge 156:ff21514d8981 246 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 247 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 248 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 249 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 250 } DMA_TypeDef;
AnnaBridge 156:ff21514d8981 251
AnnaBridge 156:ff21514d8981 252 /**
AnnaBridge 156:ff21514d8981 253 * @brief External Interrupt/Event Controller
AnnaBridge 156:ff21514d8981 254 */
AnnaBridge 156:ff21514d8981 255
AnnaBridge 156:ff21514d8981 256 typedef struct
AnnaBridge 156:ff21514d8981 257 {
AnnaBridge 156:ff21514d8981 258 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 259 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 260 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 261 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 262 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 263 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 264 } EXTI_TypeDef;
AnnaBridge 156:ff21514d8981 265
AnnaBridge 156:ff21514d8981 266 /**
AnnaBridge 156:ff21514d8981 267 * @brief FLASH Registers
AnnaBridge 156:ff21514d8981 268 */
AnnaBridge 156:ff21514d8981 269
AnnaBridge 156:ff21514d8981 270 typedef struct
AnnaBridge 156:ff21514d8981 271 {
AnnaBridge 156:ff21514d8981 272 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 273 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 274 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 275 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 276 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 277 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 278 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 279 } FLASH_TypeDef;
AnnaBridge 156:ff21514d8981 280
AnnaBridge 156:ff21514d8981 281 /**
AnnaBridge 156:ff21514d8981 282 * @brief General Purpose I/O
AnnaBridge 156:ff21514d8981 283 */
AnnaBridge 156:ff21514d8981 284
AnnaBridge 156:ff21514d8981 285 typedef struct
AnnaBridge 156:ff21514d8981 286 {
AnnaBridge 156:ff21514d8981 287 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 288 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 289 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 290 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 291 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 292 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 293 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 294 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 156:ff21514d8981 295 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 156:ff21514d8981 296 } GPIO_TypeDef;
AnnaBridge 156:ff21514d8981 297
AnnaBridge 156:ff21514d8981 298 /**
AnnaBridge 156:ff21514d8981 299 * @brief System configuration controller
AnnaBridge 156:ff21514d8981 300 */
AnnaBridge 156:ff21514d8981 301
AnnaBridge 156:ff21514d8981 302 typedef struct
AnnaBridge 156:ff21514d8981 303 {
AnnaBridge 156:ff21514d8981 304 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 305 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 306 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 156:ff21514d8981 307 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
AnnaBridge 156:ff21514d8981 308 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
AnnaBridge 156:ff21514d8981 309 } SYSCFG_TypeDef;
AnnaBridge 156:ff21514d8981 310
AnnaBridge 156:ff21514d8981 311 /**
AnnaBridge 156:ff21514d8981 312 * @brief Inter-integrated Circuit Interface
AnnaBridge 156:ff21514d8981 313 */
AnnaBridge 156:ff21514d8981 314
AnnaBridge 156:ff21514d8981 315 typedef struct
AnnaBridge 156:ff21514d8981 316 {
AnnaBridge 156:ff21514d8981 317 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 318 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 319 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 320 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 321 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 322 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 323 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 324 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
AnnaBridge 156:ff21514d8981 325 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
AnnaBridge 156:ff21514d8981 326 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
AnnaBridge 156:ff21514d8981 327 } I2C_TypeDef;
AnnaBridge 156:ff21514d8981 328
AnnaBridge 156:ff21514d8981 329 /**
AnnaBridge 156:ff21514d8981 330 * @brief Independent WATCHDOG
AnnaBridge 156:ff21514d8981 331 */
AnnaBridge 156:ff21514d8981 332
AnnaBridge 156:ff21514d8981 333 typedef struct
AnnaBridge 156:ff21514d8981 334 {
AnnaBridge 156:ff21514d8981 335 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 336 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 337 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 338 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 339 } IWDG_TypeDef;
AnnaBridge 156:ff21514d8981 340
AnnaBridge 156:ff21514d8981 341
AnnaBridge 156:ff21514d8981 342 /**
AnnaBridge 156:ff21514d8981 343 * @brief Power Control
AnnaBridge 156:ff21514d8981 344 */
AnnaBridge 156:ff21514d8981 345
AnnaBridge 156:ff21514d8981 346 typedef struct
AnnaBridge 156:ff21514d8981 347 {
AnnaBridge 156:ff21514d8981 348 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 349 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 350 } PWR_TypeDef;
AnnaBridge 156:ff21514d8981 351
AnnaBridge 156:ff21514d8981 352 /**
AnnaBridge 156:ff21514d8981 353 * @brief Reset and Clock Control
AnnaBridge 156:ff21514d8981 354 */
AnnaBridge 156:ff21514d8981 355
AnnaBridge 156:ff21514d8981 356 typedef struct
AnnaBridge 156:ff21514d8981 357 {
AnnaBridge 156:ff21514d8981 358 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 359 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 360 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 361 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 362 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 363 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 364 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 365 uint32_t RESERVED0; /*!< Reserved, 0x1C */
AnnaBridge 156:ff21514d8981 366 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
AnnaBridge 156:ff21514d8981 367 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
AnnaBridge 156:ff21514d8981 368 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
AnnaBridge 156:ff21514d8981 369 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
AnnaBridge 156:ff21514d8981 370 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
AnnaBridge 156:ff21514d8981 371 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
AnnaBridge 156:ff21514d8981 372 uint32_t RESERVED2; /*!< Reserved, 0x3C */
AnnaBridge 156:ff21514d8981 373 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
AnnaBridge 156:ff21514d8981 374 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
AnnaBridge 156:ff21514d8981 375 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
AnnaBridge 156:ff21514d8981 376 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
AnnaBridge 156:ff21514d8981 377 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
AnnaBridge 156:ff21514d8981 378 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
AnnaBridge 156:ff21514d8981 379 uint32_t RESERVED4; /*!< Reserved, 0x5C */
AnnaBridge 156:ff21514d8981 380 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
AnnaBridge 156:ff21514d8981 381 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
AnnaBridge 156:ff21514d8981 382 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
AnnaBridge 156:ff21514d8981 383 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
AnnaBridge 156:ff21514d8981 384 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
AnnaBridge 156:ff21514d8981 385 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
AnnaBridge 156:ff21514d8981 386 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
AnnaBridge 156:ff21514d8981 387 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
AnnaBridge 156:ff21514d8981 388 uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
AnnaBridge 156:ff21514d8981 389 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
AnnaBridge 156:ff21514d8981 390 } RCC_TypeDef;
AnnaBridge 156:ff21514d8981 391
AnnaBridge 156:ff21514d8981 392 /**
AnnaBridge 156:ff21514d8981 393 * @brief Real-Time Clock
AnnaBridge 156:ff21514d8981 394 */
AnnaBridge 156:ff21514d8981 395
AnnaBridge 156:ff21514d8981 396 typedef struct
AnnaBridge 156:ff21514d8981 397 {
AnnaBridge 156:ff21514d8981 398 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 399 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 400 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 401 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 402 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 403 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 404 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 405 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 156:ff21514d8981 406 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 156:ff21514d8981 407 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 156:ff21514d8981 408 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 156:ff21514d8981 409 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 156:ff21514d8981 410 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 156:ff21514d8981 411 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 156:ff21514d8981 412 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 156:ff21514d8981 413 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 156:ff21514d8981 414 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
AnnaBridge 156:ff21514d8981 415 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 156:ff21514d8981 416 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 156:ff21514d8981 417 uint32_t RESERVED7; /*!< Reserved, 0x4C */
AnnaBridge 156:ff21514d8981 418 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
AnnaBridge 156:ff21514d8981 419 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 156:ff21514d8981 420 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 156:ff21514d8981 421 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 156:ff21514d8981 422 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 156:ff21514d8981 423 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 156:ff21514d8981 424 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 156:ff21514d8981 425 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 156:ff21514d8981 426 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 156:ff21514d8981 427 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 156:ff21514d8981 428 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 156:ff21514d8981 429 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 156:ff21514d8981 430 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 156:ff21514d8981 431 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 156:ff21514d8981 432 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 156:ff21514d8981 433 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 156:ff21514d8981 434 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 156:ff21514d8981 435 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 156:ff21514d8981 436 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 156:ff21514d8981 437 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 156:ff21514d8981 438 } RTC_TypeDef;
AnnaBridge 156:ff21514d8981 439
AnnaBridge 156:ff21514d8981 440 /**
AnnaBridge 156:ff21514d8981 441 * @brief SD host Interface
AnnaBridge 156:ff21514d8981 442 */
AnnaBridge 156:ff21514d8981 443
AnnaBridge 156:ff21514d8981 444 typedef struct
AnnaBridge 156:ff21514d8981 445 {
AnnaBridge 156:ff21514d8981 446 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 447 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 448 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 449 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 450 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 451 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 452 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 453 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
AnnaBridge 156:ff21514d8981 454 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
AnnaBridge 156:ff21514d8981 455 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
AnnaBridge 156:ff21514d8981 456 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
AnnaBridge 156:ff21514d8981 457 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
AnnaBridge 156:ff21514d8981 458 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
AnnaBridge 156:ff21514d8981 459 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
AnnaBridge 156:ff21514d8981 460 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
AnnaBridge 156:ff21514d8981 461 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
AnnaBridge 156:ff21514d8981 462 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
AnnaBridge 156:ff21514d8981 463 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
AnnaBridge 156:ff21514d8981 464 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
AnnaBridge 156:ff21514d8981 465 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
AnnaBridge 156:ff21514d8981 466 } SDIO_TypeDef;
AnnaBridge 156:ff21514d8981 467
AnnaBridge 156:ff21514d8981 468 /**
AnnaBridge 156:ff21514d8981 469 * @brief Serial Peripheral Interface
AnnaBridge 156:ff21514d8981 470 */
AnnaBridge 156:ff21514d8981 471
AnnaBridge 156:ff21514d8981 472 typedef struct
AnnaBridge 156:ff21514d8981 473 {
AnnaBridge 156:ff21514d8981 474 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 475 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 476 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 477 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 478 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 479 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 480 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 481 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 156:ff21514d8981 482 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 156:ff21514d8981 483 } SPI_TypeDef;
AnnaBridge 156:ff21514d8981 484
AnnaBridge 156:ff21514d8981 485
AnnaBridge 156:ff21514d8981 486 /**
AnnaBridge 156:ff21514d8981 487 * @brief TIM
AnnaBridge 156:ff21514d8981 488 */
AnnaBridge 156:ff21514d8981 489
AnnaBridge 156:ff21514d8981 490 typedef struct
AnnaBridge 156:ff21514d8981 491 {
AnnaBridge 156:ff21514d8981 492 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 493 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 494 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 495 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 496 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 497 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 498 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 499 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 156:ff21514d8981 500 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 156:ff21514d8981 501 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 156:ff21514d8981 502 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 156:ff21514d8981 503 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 156:ff21514d8981 504 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 156:ff21514d8981 505 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 156:ff21514d8981 506 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 156:ff21514d8981 507 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 156:ff21514d8981 508 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 156:ff21514d8981 509 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 156:ff21514d8981 510 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 156:ff21514d8981 511 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 156:ff21514d8981 512 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 156:ff21514d8981 513 } TIM_TypeDef;
AnnaBridge 156:ff21514d8981 514
AnnaBridge 156:ff21514d8981 515 /**
AnnaBridge 156:ff21514d8981 516 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 156:ff21514d8981 517 */
AnnaBridge 156:ff21514d8981 518
AnnaBridge 156:ff21514d8981 519 typedef struct
AnnaBridge 156:ff21514d8981 520 {
AnnaBridge 156:ff21514d8981 521 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 522 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 523 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 524 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
AnnaBridge 156:ff21514d8981 525 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
AnnaBridge 156:ff21514d8981 526 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
AnnaBridge 156:ff21514d8981 527 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
AnnaBridge 156:ff21514d8981 528 } USART_TypeDef;
AnnaBridge 156:ff21514d8981 529
AnnaBridge 156:ff21514d8981 530 /**
AnnaBridge 156:ff21514d8981 531 * @brief Window WATCHDOG
AnnaBridge 156:ff21514d8981 532 */
AnnaBridge 156:ff21514d8981 533
AnnaBridge 156:ff21514d8981 534 typedef struct
AnnaBridge 156:ff21514d8981 535 {
AnnaBridge 156:ff21514d8981 536 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 156:ff21514d8981 537 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 156:ff21514d8981 538 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 156:ff21514d8981 539 } WWDG_TypeDef;
AnnaBridge 156:ff21514d8981 540 /**
AnnaBridge 156:ff21514d8981 541 * @brief USB_OTG_Core_Registers
AnnaBridge 156:ff21514d8981 542 */
AnnaBridge 156:ff21514d8981 543 typedef struct
AnnaBridge 156:ff21514d8981 544 {
AnnaBridge 156:ff21514d8981 545 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 156:ff21514d8981 546 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 156:ff21514d8981 547 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 156:ff21514d8981 548 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 156:ff21514d8981 549 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 156:ff21514d8981 550 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 156:ff21514d8981 551 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 156:ff21514d8981 552 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 156:ff21514d8981 553 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 156:ff21514d8981 554 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 156:ff21514d8981 555 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 156:ff21514d8981 556 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 156:ff21514d8981 557 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 156:ff21514d8981 558 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 156:ff21514d8981 559 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 156:ff21514d8981 560 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
AnnaBridge 156:ff21514d8981 561 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 156:ff21514d8981 562 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 156:ff21514d8981 563 } USB_OTG_GlobalTypeDef;
AnnaBridge 156:ff21514d8981 564
AnnaBridge 156:ff21514d8981 565 /**
AnnaBridge 156:ff21514d8981 566 * @brief USB_OTG_device_Registers
AnnaBridge 156:ff21514d8981 567 */
AnnaBridge 156:ff21514d8981 568 typedef struct
AnnaBridge 156:ff21514d8981 569 {
AnnaBridge 156:ff21514d8981 570 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 156:ff21514d8981 571 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 156:ff21514d8981 572 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 156:ff21514d8981 573 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 156:ff21514d8981 574 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 156:ff21514d8981 575 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 156:ff21514d8981 576 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 156:ff21514d8981 577 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 156:ff21514d8981 578 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 156:ff21514d8981 579 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 156:ff21514d8981 580 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 156:ff21514d8981 581 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 156:ff21514d8981 582 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 156:ff21514d8981 583 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 156:ff21514d8981 584 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 156:ff21514d8981 585 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 156:ff21514d8981 586 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 156:ff21514d8981 587 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 156:ff21514d8981 588 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 156:ff21514d8981 589 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 156:ff21514d8981 590 } USB_OTG_DeviceTypeDef;
AnnaBridge 156:ff21514d8981 591
AnnaBridge 156:ff21514d8981 592 /**
AnnaBridge 156:ff21514d8981 593 * @brief USB_OTG_IN_Endpoint-Specific_Register
AnnaBridge 156:ff21514d8981 594 */
AnnaBridge 156:ff21514d8981 595 typedef struct
AnnaBridge 156:ff21514d8981 596 {
AnnaBridge 156:ff21514d8981 597 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 156:ff21514d8981 598 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 156:ff21514d8981 599 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 156:ff21514d8981 600 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 156:ff21514d8981 601 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 156:ff21514d8981 602 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 156:ff21514d8981 603 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 156:ff21514d8981 604 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 156:ff21514d8981 605 } USB_OTG_INEndpointTypeDef;
AnnaBridge 156:ff21514d8981 606
AnnaBridge 156:ff21514d8981 607 /**
AnnaBridge 156:ff21514d8981 608 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
AnnaBridge 156:ff21514d8981 609 */
AnnaBridge 156:ff21514d8981 610 typedef struct
AnnaBridge 156:ff21514d8981 611 {
AnnaBridge 156:ff21514d8981 612 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 156:ff21514d8981 613 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 156:ff21514d8981 614 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 156:ff21514d8981 615 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 156:ff21514d8981 616 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 156:ff21514d8981 617 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 156:ff21514d8981 618 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 156:ff21514d8981 619 } USB_OTG_OUTEndpointTypeDef;
AnnaBridge 156:ff21514d8981 620
AnnaBridge 156:ff21514d8981 621 /**
AnnaBridge 156:ff21514d8981 622 * @brief USB_OTG_Host_Mode_Register_Structures
AnnaBridge 156:ff21514d8981 623 */
AnnaBridge 156:ff21514d8981 624 typedef struct
AnnaBridge 156:ff21514d8981 625 {
AnnaBridge 156:ff21514d8981 626 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 156:ff21514d8981 627 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 156:ff21514d8981 628 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 156:ff21514d8981 629 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 156:ff21514d8981 630 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 156:ff21514d8981 631 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 156:ff21514d8981 632 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 156:ff21514d8981 633 } USB_OTG_HostTypeDef;
AnnaBridge 156:ff21514d8981 634
AnnaBridge 156:ff21514d8981 635 /**
AnnaBridge 156:ff21514d8981 636 * @brief USB_OTG_Host_Channel_Specific_Registers
AnnaBridge 156:ff21514d8981 637 */
AnnaBridge 156:ff21514d8981 638 typedef struct
AnnaBridge 156:ff21514d8981 639 {
AnnaBridge 156:ff21514d8981 640 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 156:ff21514d8981 641 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 156:ff21514d8981 642 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 156:ff21514d8981 643 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 156:ff21514d8981 644 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 156:ff21514d8981 645 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 156:ff21514d8981 646 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 156:ff21514d8981 647 } USB_OTG_HostChannelTypeDef;
AnnaBridge 156:ff21514d8981 648
AnnaBridge 156:ff21514d8981 649 /**
AnnaBridge 156:ff21514d8981 650 * @}
AnnaBridge 156:ff21514d8981 651 */
AnnaBridge 156:ff21514d8981 652
AnnaBridge 156:ff21514d8981 653 /** @addtogroup Peripheral_memory_map
AnnaBridge 156:ff21514d8981 654 * @{
AnnaBridge 156:ff21514d8981 655 */
AnnaBridge 156:ff21514d8981 656 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
AnnaBridge 156:ff21514d8981 657 #define SRAM1_BASE 0x20000000U /*!< SRAM1(96 KB) base address in the alias region */
AnnaBridge 156:ff21514d8981 658 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
AnnaBridge 156:ff21514d8981 659 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
AnnaBridge 156:ff21514d8981 660 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(96 KB) base address in the bit-band region */
AnnaBridge 156:ff21514d8981 661 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
AnnaBridge 156:ff21514d8981 662 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
AnnaBridge 156:ff21514d8981 663 #define FLASH_END 0x0807FFFFU /*!< FLASH end address */
AnnaBridge 156:ff21514d8981 664 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 156:ff21514d8981 665 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 156:ff21514d8981 666
AnnaBridge 156:ff21514d8981 667 /* Legacy defines */
AnnaBridge 156:ff21514d8981 668 #define SRAM_BASE SRAM1_BASE
AnnaBridge 156:ff21514d8981 669 #define SRAM_BB_BASE SRAM1_BB_BASE
AnnaBridge 156:ff21514d8981 670
AnnaBridge 156:ff21514d8981 671 /*!< Peripheral memory map */
AnnaBridge 156:ff21514d8981 672 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 156:ff21514d8981 673 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 156:ff21514d8981 674 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 156:ff21514d8981 675 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
AnnaBridge 156:ff21514d8981 676
AnnaBridge 156:ff21514d8981 677 /*!< APB1 peripherals */
AnnaBridge 156:ff21514d8981 678 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
AnnaBridge 156:ff21514d8981 679 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
AnnaBridge 156:ff21514d8981 680 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
AnnaBridge 156:ff21514d8981 681 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
AnnaBridge 156:ff21514d8981 682 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
AnnaBridge 156:ff21514d8981 683 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
AnnaBridge 156:ff21514d8981 684 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
AnnaBridge 156:ff21514d8981 685 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
AnnaBridge 156:ff21514d8981 686 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
AnnaBridge 156:ff21514d8981 687 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
AnnaBridge 156:ff21514d8981 688 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
AnnaBridge 156:ff21514d8981 689 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
AnnaBridge 156:ff21514d8981 690 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
AnnaBridge 156:ff21514d8981 691 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
AnnaBridge 156:ff21514d8981 692 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
AnnaBridge 156:ff21514d8981 693 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
AnnaBridge 156:ff21514d8981 694
AnnaBridge 156:ff21514d8981 695 /*!< APB2 peripherals */
AnnaBridge 156:ff21514d8981 696 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
AnnaBridge 156:ff21514d8981 697 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
AnnaBridge 156:ff21514d8981 698 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
AnnaBridge 156:ff21514d8981 699 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
AnnaBridge 156:ff21514d8981 700 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 156:ff21514d8981 701 /* Legacy define */
AnnaBridge 156:ff21514d8981 702 #define ADC_BASE ADC1_COMMON_BASE
AnnaBridge 156:ff21514d8981 703 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
AnnaBridge 156:ff21514d8981 704 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
AnnaBridge 156:ff21514d8981 705 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
AnnaBridge 156:ff21514d8981 706 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
AnnaBridge 156:ff21514d8981 707 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
AnnaBridge 156:ff21514d8981 708 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
AnnaBridge 156:ff21514d8981 709 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
AnnaBridge 156:ff21514d8981 710 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
AnnaBridge 156:ff21514d8981 711
AnnaBridge 156:ff21514d8981 712 /*!< AHB1 peripherals */
AnnaBridge 156:ff21514d8981 713 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
AnnaBridge 156:ff21514d8981 714 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
AnnaBridge 156:ff21514d8981 715 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
AnnaBridge 156:ff21514d8981 716 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
AnnaBridge 156:ff21514d8981 717 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
AnnaBridge 156:ff21514d8981 718 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
AnnaBridge 156:ff21514d8981 719 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
AnnaBridge 156:ff21514d8981 720 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
AnnaBridge 156:ff21514d8981 721 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
AnnaBridge 156:ff21514d8981 722 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
AnnaBridge 156:ff21514d8981 723 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
AnnaBridge 156:ff21514d8981 724 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
AnnaBridge 156:ff21514d8981 725 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
AnnaBridge 156:ff21514d8981 726 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
AnnaBridge 156:ff21514d8981 727 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
AnnaBridge 156:ff21514d8981 728 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
AnnaBridge 156:ff21514d8981 729 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
AnnaBridge 156:ff21514d8981 730 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
AnnaBridge 156:ff21514d8981 731 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
AnnaBridge 156:ff21514d8981 732 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
AnnaBridge 156:ff21514d8981 733 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
AnnaBridge 156:ff21514d8981 734 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
AnnaBridge 156:ff21514d8981 735 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
AnnaBridge 156:ff21514d8981 736 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
AnnaBridge 156:ff21514d8981 737 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
AnnaBridge 156:ff21514d8981 738 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
AnnaBridge 156:ff21514d8981 739 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
AnnaBridge 156:ff21514d8981 740
AnnaBridge 156:ff21514d8981 741
AnnaBridge 156:ff21514d8981 742 /*!< Debug MCU registers base address */
AnnaBridge 156:ff21514d8981 743 #define DBGMCU_BASE 0xE0042000U
AnnaBridge 156:ff21514d8981 744 /*!< USB registers base address */
AnnaBridge 156:ff21514d8981 745 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
AnnaBridge 156:ff21514d8981 746
AnnaBridge 156:ff21514d8981 747 #define USB_OTG_GLOBAL_BASE 0x000U
AnnaBridge 156:ff21514d8981 748 #define USB_OTG_DEVICE_BASE 0x800U
AnnaBridge 156:ff21514d8981 749 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
AnnaBridge 156:ff21514d8981 750 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
AnnaBridge 156:ff21514d8981 751 #define USB_OTG_EP_REG_SIZE 0x20U
AnnaBridge 156:ff21514d8981 752 #define USB_OTG_HOST_BASE 0x400U
AnnaBridge 156:ff21514d8981 753 #define USB_OTG_HOST_PORT_BASE 0x440U
AnnaBridge 156:ff21514d8981 754 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
AnnaBridge 156:ff21514d8981 755 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
AnnaBridge 156:ff21514d8981 756 #define USB_OTG_PCGCCTL_BASE 0xE00U
AnnaBridge 156:ff21514d8981 757 #define USB_OTG_FIFO_BASE 0x1000U
AnnaBridge 156:ff21514d8981 758 #define USB_OTG_FIFO_SIZE 0x1000U
AnnaBridge 156:ff21514d8981 759
AnnaBridge 156:ff21514d8981 760 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
AnnaBridge 156:ff21514d8981 761 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
AnnaBridge 156:ff21514d8981 762 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
AnnaBridge 156:ff21514d8981 763 /**
AnnaBridge 156:ff21514d8981 764 * @}
AnnaBridge 156:ff21514d8981 765 */
AnnaBridge 156:ff21514d8981 766
AnnaBridge 156:ff21514d8981 767 /** @addtogroup Peripheral_declaration
AnnaBridge 156:ff21514d8981 768 * @{
AnnaBridge 156:ff21514d8981 769 */
AnnaBridge 156:ff21514d8981 770 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 156:ff21514d8981 771 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 156:ff21514d8981 772 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
AnnaBridge 156:ff21514d8981 773 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 156:ff21514d8981 774 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 156:ff21514d8981 775 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 156:ff21514d8981 776 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 156:ff21514d8981 777 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
AnnaBridge 156:ff21514d8981 778 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 156:ff21514d8981 779 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 156:ff21514d8981 780 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
AnnaBridge 156:ff21514d8981 781 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 156:ff21514d8981 782 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 156:ff21514d8981 783 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 156:ff21514d8981 784 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 156:ff21514d8981 785 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 156:ff21514d8981 786 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 156:ff21514d8981 787 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 156:ff21514d8981 788 #define USART6 ((USART_TypeDef *) USART6_BASE)
AnnaBridge 156:ff21514d8981 789 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 156:ff21514d8981 790 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
AnnaBridge 156:ff21514d8981 791 /* Legacy define */
AnnaBridge 156:ff21514d8981 792 #define ADC ADC1_COMMON
AnnaBridge 156:ff21514d8981 793 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
AnnaBridge 156:ff21514d8981 794 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 156:ff21514d8981 795 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
AnnaBridge 156:ff21514d8981 796 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 156:ff21514d8981 797 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 156:ff21514d8981 798 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
AnnaBridge 156:ff21514d8981 799 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
AnnaBridge 156:ff21514d8981 800 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
AnnaBridge 156:ff21514d8981 801 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 156:ff21514d8981 802 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 156:ff21514d8981 803 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 156:ff21514d8981 804 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 156:ff21514d8981 805 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 156:ff21514d8981 806 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 156:ff21514d8981 807 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 156:ff21514d8981 808 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 156:ff21514d8981 809 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 156:ff21514d8981 810 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 156:ff21514d8981 811 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
AnnaBridge 156:ff21514d8981 812 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
AnnaBridge 156:ff21514d8981 813 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
AnnaBridge 156:ff21514d8981 814 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
AnnaBridge 156:ff21514d8981 815 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
AnnaBridge 156:ff21514d8981 816 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
AnnaBridge 156:ff21514d8981 817 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
AnnaBridge 156:ff21514d8981 818 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
AnnaBridge 156:ff21514d8981 819 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 156:ff21514d8981 820 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
AnnaBridge 156:ff21514d8981 821 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
AnnaBridge 156:ff21514d8981 822 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
AnnaBridge 156:ff21514d8981 823 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
AnnaBridge 156:ff21514d8981 824 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
AnnaBridge 156:ff21514d8981 825 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
AnnaBridge 156:ff21514d8981 826 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
AnnaBridge 156:ff21514d8981 827 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
AnnaBridge 156:ff21514d8981 828 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 156:ff21514d8981 829 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
AnnaBridge 156:ff21514d8981 830
AnnaBridge 156:ff21514d8981 831 /**
AnnaBridge 156:ff21514d8981 832 * @}
AnnaBridge 156:ff21514d8981 833 */
AnnaBridge 156:ff21514d8981 834
AnnaBridge 156:ff21514d8981 835 /** @addtogroup Exported_constants
AnnaBridge 156:ff21514d8981 836 * @{
AnnaBridge 156:ff21514d8981 837 */
AnnaBridge 156:ff21514d8981 838
AnnaBridge 156:ff21514d8981 839 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 156:ff21514d8981 840 * @{
AnnaBridge 156:ff21514d8981 841 */
AnnaBridge 156:ff21514d8981 842
AnnaBridge 156:ff21514d8981 843 /******************************************************************************/
AnnaBridge 156:ff21514d8981 844 /* Peripheral Registers_Bits_Definition */
AnnaBridge 156:ff21514d8981 845 /******************************************************************************/
AnnaBridge 156:ff21514d8981 846
AnnaBridge 156:ff21514d8981 847 /******************************************************************************/
AnnaBridge 156:ff21514d8981 848 /* */
AnnaBridge 156:ff21514d8981 849 /* Analog to Digital Converter */
AnnaBridge 156:ff21514d8981 850 /* */
AnnaBridge 156:ff21514d8981 851 /******************************************************************************/
AnnaBridge 156:ff21514d8981 852
AnnaBridge 156:ff21514d8981 853 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 156:ff21514d8981 854 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 156:ff21514d8981 855 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 856 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
AnnaBridge 156:ff21514d8981 857 #define ADC_SR_EOC_Pos (1U)
AnnaBridge 156:ff21514d8981 858 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 859 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
AnnaBridge 156:ff21514d8981 860 #define ADC_SR_JEOC_Pos (2U)
AnnaBridge 156:ff21514d8981 861 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 862 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
AnnaBridge 156:ff21514d8981 863 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 156:ff21514d8981 864 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 865 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
AnnaBridge 156:ff21514d8981 866 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 156:ff21514d8981 867 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 868 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
AnnaBridge 156:ff21514d8981 869 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 156:ff21514d8981 870 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 871 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 156:ff21514d8981 872
AnnaBridge 156:ff21514d8981 873 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 156:ff21514d8981 874 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 156:ff21514d8981 875 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 156:ff21514d8981 876 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 156:ff21514d8981 877 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 878 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 879 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 880 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 881 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 882 #define ADC_CR1_EOCIE_Pos (5U)
AnnaBridge 156:ff21514d8981 883 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 884 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
AnnaBridge 156:ff21514d8981 885 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 156:ff21514d8981 886 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 887 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 156:ff21514d8981 888 #define ADC_CR1_JEOCIE_Pos (7U)
AnnaBridge 156:ff21514d8981 889 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 890 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
AnnaBridge 156:ff21514d8981 891 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 156:ff21514d8981 892 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 893 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
AnnaBridge 156:ff21514d8981 894 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 156:ff21514d8981 895 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 896 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 156:ff21514d8981 897 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 156:ff21514d8981 898 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 899 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
AnnaBridge 156:ff21514d8981 900 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 156:ff21514d8981 901 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 902 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
AnnaBridge 156:ff21514d8981 903 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 156:ff21514d8981 904 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 905 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
AnnaBridge 156:ff21514d8981 906 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 156:ff21514d8981 907 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 156:ff21514d8981 908 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 156:ff21514d8981 909 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 910 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 911 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 912 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 156:ff21514d8981 913 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 914 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
AnnaBridge 156:ff21514d8981 915 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 156:ff21514d8981 916 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 917 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
AnnaBridge 156:ff21514d8981 918 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 156:ff21514d8981 919 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 156:ff21514d8981 920 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
AnnaBridge 156:ff21514d8981 921 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 922 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 923 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 156:ff21514d8981 924 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 925 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
AnnaBridge 156:ff21514d8981 926
AnnaBridge 156:ff21514d8981 927 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 156:ff21514d8981 928 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 156:ff21514d8981 929 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 930 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
AnnaBridge 156:ff21514d8981 931 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 156:ff21514d8981 932 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 933 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
AnnaBridge 156:ff21514d8981 934 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 156:ff21514d8981 935 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 936 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
AnnaBridge 156:ff21514d8981 937 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 156:ff21514d8981 938 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 939 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
AnnaBridge 156:ff21514d8981 940 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 156:ff21514d8981 941 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 942 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
AnnaBridge 156:ff21514d8981 943 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 156:ff21514d8981 944 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 945 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
AnnaBridge 156:ff21514d8981 946 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 156:ff21514d8981 947 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 156:ff21514d8981 948 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 156:ff21514d8981 949 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 950 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 951 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 952 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 953 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 156:ff21514d8981 954 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 955 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 156:ff21514d8981 956 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 957 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 958 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 156:ff21514d8981 959 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 960 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
AnnaBridge 156:ff21514d8981 961 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 156:ff21514d8981 962 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 156:ff21514d8981 963 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 156:ff21514d8981 964 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 965 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 966 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 967 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 968 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 156:ff21514d8981 969 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 156:ff21514d8981 970 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 156:ff21514d8981 971 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 972 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 973 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 156:ff21514d8981 974 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 975 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
AnnaBridge 156:ff21514d8981 976
AnnaBridge 156:ff21514d8981 977 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 156:ff21514d8981 978 #define ADC_SMPR1_SMP10_Pos (0U)
AnnaBridge 156:ff21514d8981 979 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 156:ff21514d8981 980 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 156:ff21514d8981 981 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 982 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 983 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 984 #define ADC_SMPR1_SMP11_Pos (3U)
AnnaBridge 156:ff21514d8981 985 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 156:ff21514d8981 986 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 156:ff21514d8981 987 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 988 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 989 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 990 #define ADC_SMPR1_SMP12_Pos (6U)
AnnaBridge 156:ff21514d8981 991 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 156:ff21514d8981 992 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 156:ff21514d8981 993 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 994 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 995 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 996 #define ADC_SMPR1_SMP13_Pos (9U)
AnnaBridge 156:ff21514d8981 997 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 156:ff21514d8981 998 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 156:ff21514d8981 999 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1000 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1001 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1002 #define ADC_SMPR1_SMP14_Pos (12U)
AnnaBridge 156:ff21514d8981 1003 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 156:ff21514d8981 1004 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 156:ff21514d8981 1005 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1006 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1007 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1008 #define ADC_SMPR1_SMP15_Pos (15U)
AnnaBridge 156:ff21514d8981 1009 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 156:ff21514d8981 1010 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 156:ff21514d8981 1011 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1012 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1013 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1014 #define ADC_SMPR1_SMP16_Pos (18U)
AnnaBridge 156:ff21514d8981 1015 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 156:ff21514d8981 1016 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 156:ff21514d8981 1017 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1018 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1019 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1020 #define ADC_SMPR1_SMP17_Pos (21U)
AnnaBridge 156:ff21514d8981 1021 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 156:ff21514d8981 1022 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 156:ff21514d8981 1023 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1024 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1025 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 1026 #define ADC_SMPR1_SMP18_Pos (24U)
AnnaBridge 156:ff21514d8981 1027 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 156:ff21514d8981 1028 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 156:ff21514d8981 1029 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1030 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 1031 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 1032
AnnaBridge 156:ff21514d8981 1033 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 156:ff21514d8981 1034 #define ADC_SMPR2_SMP0_Pos (0U)
AnnaBridge 156:ff21514d8981 1035 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 156:ff21514d8981 1036 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 156:ff21514d8981 1037 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1038 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1039 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1040 #define ADC_SMPR2_SMP1_Pos (3U)
AnnaBridge 156:ff21514d8981 1041 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 156:ff21514d8981 1042 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 156:ff21514d8981 1043 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1044 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1045 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1046 #define ADC_SMPR2_SMP2_Pos (6U)
AnnaBridge 156:ff21514d8981 1047 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 156:ff21514d8981 1048 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 156:ff21514d8981 1049 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1050 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1051 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1052 #define ADC_SMPR2_SMP3_Pos (9U)
AnnaBridge 156:ff21514d8981 1053 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 156:ff21514d8981 1054 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 156:ff21514d8981 1055 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1056 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1057 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1058 #define ADC_SMPR2_SMP4_Pos (12U)
AnnaBridge 156:ff21514d8981 1059 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 156:ff21514d8981 1060 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 156:ff21514d8981 1061 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1062 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1063 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1064 #define ADC_SMPR2_SMP5_Pos (15U)
AnnaBridge 156:ff21514d8981 1065 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 156:ff21514d8981 1066 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 156:ff21514d8981 1067 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1068 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1069 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1070 #define ADC_SMPR2_SMP6_Pos (18U)
AnnaBridge 156:ff21514d8981 1071 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 156:ff21514d8981 1072 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 156:ff21514d8981 1073 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1074 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1075 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1076 #define ADC_SMPR2_SMP7_Pos (21U)
AnnaBridge 156:ff21514d8981 1077 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 156:ff21514d8981 1078 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 156:ff21514d8981 1079 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1080 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1081 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 1082 #define ADC_SMPR2_SMP8_Pos (24U)
AnnaBridge 156:ff21514d8981 1083 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 156:ff21514d8981 1084 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 156:ff21514d8981 1085 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1086 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 1087 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 1088 #define ADC_SMPR2_SMP9_Pos (27U)
AnnaBridge 156:ff21514d8981 1089 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 156:ff21514d8981 1090 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 156:ff21514d8981 1091 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 1092 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 1093 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 1094
AnnaBridge 156:ff21514d8981 1095 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 156:ff21514d8981 1096 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 156:ff21514d8981 1097 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 1098 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
AnnaBridge 156:ff21514d8981 1099
AnnaBridge 156:ff21514d8981 1100 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 156:ff21514d8981 1101 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 156:ff21514d8981 1102 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 1103 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
AnnaBridge 156:ff21514d8981 1104
AnnaBridge 156:ff21514d8981 1105 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 156:ff21514d8981 1106 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 156:ff21514d8981 1107 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 1108 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
AnnaBridge 156:ff21514d8981 1109
AnnaBridge 156:ff21514d8981 1110 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 156:ff21514d8981 1111 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 156:ff21514d8981 1112 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 1113 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
AnnaBridge 156:ff21514d8981 1114
AnnaBridge 156:ff21514d8981 1115 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 156:ff21514d8981 1116 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 156:ff21514d8981 1117 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 1118 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
AnnaBridge 156:ff21514d8981 1119
AnnaBridge 156:ff21514d8981 1120 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 156:ff21514d8981 1121 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 156:ff21514d8981 1122 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 1123 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
AnnaBridge 156:ff21514d8981 1124
AnnaBridge 156:ff21514d8981 1125 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 156:ff21514d8981 1126 #define ADC_SQR1_SQ13_Pos (0U)
AnnaBridge 156:ff21514d8981 1127 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 156:ff21514d8981 1128 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1129 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1130 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1131 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1132 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1133 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1134 #define ADC_SQR1_SQ14_Pos (5U)
AnnaBridge 156:ff21514d8981 1135 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 156:ff21514d8981 1136 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1137 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1138 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1139 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1140 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1141 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1142 #define ADC_SQR1_SQ15_Pos (10U)
AnnaBridge 156:ff21514d8981 1143 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 156:ff21514d8981 1144 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1145 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1146 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1147 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1148 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1149 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1150 #define ADC_SQR1_SQ16_Pos (15U)
AnnaBridge 156:ff21514d8981 1151 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 156:ff21514d8981 1152 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1153 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1154 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1155 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1156 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1157 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1158 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 156:ff21514d8981 1159 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
AnnaBridge 156:ff21514d8981 1160 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 156:ff21514d8981 1161 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1162 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1163 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1164 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 1165
AnnaBridge 156:ff21514d8981 1166 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 156:ff21514d8981 1167 #define ADC_SQR2_SQ7_Pos (0U)
AnnaBridge 156:ff21514d8981 1168 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 156:ff21514d8981 1169 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1170 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1171 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1172 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1173 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1174 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1175 #define ADC_SQR2_SQ8_Pos (5U)
AnnaBridge 156:ff21514d8981 1176 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 156:ff21514d8981 1177 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1178 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1179 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1180 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1181 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1182 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1183 #define ADC_SQR2_SQ9_Pos (10U)
AnnaBridge 156:ff21514d8981 1184 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 156:ff21514d8981 1185 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1186 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1187 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1188 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1189 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1190 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1191 #define ADC_SQR2_SQ10_Pos (15U)
AnnaBridge 156:ff21514d8981 1192 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 156:ff21514d8981 1193 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1194 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1195 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1196 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1197 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1198 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1199 #define ADC_SQR2_SQ11_Pos (20U)
AnnaBridge 156:ff21514d8981 1200 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 156:ff21514d8981 1201 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1202 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1203 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1204 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1205 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 1206 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1207 #define ADC_SQR2_SQ12_Pos (25U)
AnnaBridge 156:ff21514d8981 1208 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 156:ff21514d8981 1209 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1210 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 1211 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 1212 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 1213 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 1214 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 1215
AnnaBridge 156:ff21514d8981 1216 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 156:ff21514d8981 1217 #define ADC_SQR3_SQ1_Pos (0U)
AnnaBridge 156:ff21514d8981 1218 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 156:ff21514d8981 1219 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1220 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1221 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1222 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1223 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1224 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1225 #define ADC_SQR3_SQ2_Pos (5U)
AnnaBridge 156:ff21514d8981 1226 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 156:ff21514d8981 1227 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1228 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1229 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1230 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1231 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1232 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1233 #define ADC_SQR3_SQ3_Pos (10U)
AnnaBridge 156:ff21514d8981 1234 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 156:ff21514d8981 1235 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1236 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1237 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1238 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1239 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1240 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1241 #define ADC_SQR3_SQ4_Pos (15U)
AnnaBridge 156:ff21514d8981 1242 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 156:ff21514d8981 1243 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1244 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1245 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1246 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1247 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1248 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1249 #define ADC_SQR3_SQ5_Pos (20U)
AnnaBridge 156:ff21514d8981 1250 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 156:ff21514d8981 1251 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1252 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1253 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1254 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1255 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 1256 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1257 #define ADC_SQR3_SQ6_Pos (25U)
AnnaBridge 156:ff21514d8981 1258 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 156:ff21514d8981 1259 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 156:ff21514d8981 1260 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 1261 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 1262 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 1263 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 1264 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 1265
AnnaBridge 156:ff21514d8981 1266 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 156:ff21514d8981 1267 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 156:ff21514d8981 1268 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 156:ff21514d8981 1269 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 156:ff21514d8981 1270 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1271 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1272 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1273 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1274 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1275 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 156:ff21514d8981 1276 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 156:ff21514d8981 1277 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 156:ff21514d8981 1278 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1279 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1280 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1281 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1282 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1283 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 156:ff21514d8981 1284 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 156:ff21514d8981 1285 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 156:ff21514d8981 1286 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1287 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1288 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1289 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1290 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1291 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 156:ff21514d8981 1292 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 156:ff21514d8981 1293 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 156:ff21514d8981 1294 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1295 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1296 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1297 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1298 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1299 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 156:ff21514d8981 1300 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 1301 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 156:ff21514d8981 1302 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1303 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1304
AnnaBridge 156:ff21514d8981 1305 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 156:ff21514d8981 1306 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 156:ff21514d8981 1307 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 1308 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
AnnaBridge 156:ff21514d8981 1309
AnnaBridge 156:ff21514d8981 1310 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 156:ff21514d8981 1311 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 156:ff21514d8981 1312 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 1313 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
AnnaBridge 156:ff21514d8981 1314
AnnaBridge 156:ff21514d8981 1315 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 156:ff21514d8981 1316 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 156:ff21514d8981 1317 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 1318 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
AnnaBridge 156:ff21514d8981 1319
AnnaBridge 156:ff21514d8981 1320 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 156:ff21514d8981 1321 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 156:ff21514d8981 1322 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 1323 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
AnnaBridge 156:ff21514d8981 1324
AnnaBridge 156:ff21514d8981 1325 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 156:ff21514d8981 1326 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 156:ff21514d8981 1327 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 1328 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
AnnaBridge 156:ff21514d8981 1329 #define ADC_DR_ADC2DATA_Pos (16U)
AnnaBridge 156:ff21514d8981 1330 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 1331 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
AnnaBridge 156:ff21514d8981 1332
AnnaBridge 156:ff21514d8981 1333 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 156:ff21514d8981 1334 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 156:ff21514d8981 1335 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1336 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
AnnaBridge 156:ff21514d8981 1337 #define ADC_CSR_EOC1_Pos (1U)
AnnaBridge 156:ff21514d8981 1338 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1339 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
AnnaBridge 156:ff21514d8981 1340 #define ADC_CSR_JEOC1_Pos (2U)
AnnaBridge 156:ff21514d8981 1341 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1342 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
AnnaBridge 156:ff21514d8981 1343 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 156:ff21514d8981 1344 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1345 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
AnnaBridge 156:ff21514d8981 1346 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 156:ff21514d8981 1347 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1348 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
AnnaBridge 156:ff21514d8981 1349 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 156:ff21514d8981 1350 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1351 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
AnnaBridge 156:ff21514d8981 1352
AnnaBridge 156:ff21514d8981 1353 /* Legacy defines */
AnnaBridge 156:ff21514d8981 1354 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
AnnaBridge 156:ff21514d8981 1355
AnnaBridge 156:ff21514d8981 1356 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 156:ff21514d8981 1357 #define ADC_CCR_MULTI_Pos (0U)
AnnaBridge 156:ff21514d8981 1358 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 156:ff21514d8981 1359 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 156:ff21514d8981 1360 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1361 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1362 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1363 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1364 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1365 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 156:ff21514d8981 1366 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 1367 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 156:ff21514d8981 1368 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1369 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1370 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1371 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1372 #define ADC_CCR_DDS_Pos (13U)
AnnaBridge 156:ff21514d8981 1373 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1374 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 156:ff21514d8981 1375 #define ADC_CCR_DMA_Pos (14U)
AnnaBridge 156:ff21514d8981 1376 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
AnnaBridge 156:ff21514d8981 1377 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 156:ff21514d8981 1378 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1379 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1380 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 156:ff21514d8981 1381 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 156:ff21514d8981 1382 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 156:ff21514d8981 1383 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1384 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1385 #define ADC_CCR_VBATE_Pos (22U)
AnnaBridge 156:ff21514d8981 1386 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1387 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
AnnaBridge 156:ff21514d8981 1388 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 156:ff21514d8981 1389 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 1390 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
AnnaBridge 156:ff21514d8981 1391
AnnaBridge 156:ff21514d8981 1392 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 156:ff21514d8981 1393 #define ADC_CDR_DATA1_Pos (0U)
AnnaBridge 156:ff21514d8981 1394 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 1395 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
AnnaBridge 156:ff21514d8981 1396 #define ADC_CDR_DATA2_Pos (16U)
AnnaBridge 156:ff21514d8981 1397 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 1398 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
AnnaBridge 156:ff21514d8981 1399
AnnaBridge 156:ff21514d8981 1400 /* Legacy defines */
AnnaBridge 156:ff21514d8981 1401 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
AnnaBridge 156:ff21514d8981 1402 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
AnnaBridge 156:ff21514d8981 1403
AnnaBridge 156:ff21514d8981 1404 /******************************************************************************/
AnnaBridge 156:ff21514d8981 1405 /* */
AnnaBridge 156:ff21514d8981 1406 /* CRC calculation unit */
AnnaBridge 156:ff21514d8981 1407 /* */
AnnaBridge 156:ff21514d8981 1408 /******************************************************************************/
AnnaBridge 156:ff21514d8981 1409 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 156:ff21514d8981 1410 #define CRC_DR_DR_Pos (0U)
AnnaBridge 156:ff21514d8981 1411 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 1412 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 156:ff21514d8981 1413
AnnaBridge 156:ff21514d8981 1414
AnnaBridge 156:ff21514d8981 1415 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 156:ff21514d8981 1416 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 156:ff21514d8981 1417 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 156:ff21514d8981 1418 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
AnnaBridge 156:ff21514d8981 1419
AnnaBridge 156:ff21514d8981 1420
AnnaBridge 156:ff21514d8981 1421 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 156:ff21514d8981 1422 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 156:ff21514d8981 1423 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1424 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
AnnaBridge 156:ff21514d8981 1425
AnnaBridge 156:ff21514d8981 1426
AnnaBridge 156:ff21514d8981 1427 /******************************************************************************/
AnnaBridge 156:ff21514d8981 1428 /* */
AnnaBridge 156:ff21514d8981 1429 /* DMA Controller */
AnnaBridge 156:ff21514d8981 1430 /* */
AnnaBridge 156:ff21514d8981 1431 /******************************************************************************/
AnnaBridge 156:ff21514d8981 1432 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 156:ff21514d8981 1433 #define DMA_SxCR_CHSEL_Pos (25U)
AnnaBridge 156:ff21514d8981 1434 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
AnnaBridge 156:ff21514d8981 1435 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
AnnaBridge 156:ff21514d8981 1436 #define DMA_SxCR_CHSEL_0 0x02000000U
AnnaBridge 156:ff21514d8981 1437 #define DMA_SxCR_CHSEL_1 0x04000000U
AnnaBridge 156:ff21514d8981 1438 #define DMA_SxCR_CHSEL_2 0x08000000U
AnnaBridge 156:ff21514d8981 1439 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 156:ff21514d8981 1440 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 156:ff21514d8981 1441 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
AnnaBridge 156:ff21514d8981 1442 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 1443 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1444 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 156:ff21514d8981 1445 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 156:ff21514d8981 1446 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
AnnaBridge 156:ff21514d8981 1447 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1448 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1449 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 156:ff21514d8981 1450 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1451 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
AnnaBridge 156:ff21514d8981 1452 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 156:ff21514d8981 1453 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1454 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
AnnaBridge 156:ff21514d8981 1455 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 156:ff21514d8981 1456 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 156:ff21514d8981 1457 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
AnnaBridge 156:ff21514d8981 1458 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1459 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1460 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 156:ff21514d8981 1461 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1462 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
AnnaBridge 156:ff21514d8981 1463 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 156:ff21514d8981 1464 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 156:ff21514d8981 1465 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
AnnaBridge 156:ff21514d8981 1466 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1467 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1468 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 156:ff21514d8981 1469 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 156:ff21514d8981 1470 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
AnnaBridge 156:ff21514d8981 1471 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1472 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1473 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 156:ff21514d8981 1474 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1475 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
AnnaBridge 156:ff21514d8981 1476 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 156:ff21514d8981 1477 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1478 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
AnnaBridge 156:ff21514d8981 1479 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 156:ff21514d8981 1480 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1481 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
AnnaBridge 156:ff21514d8981 1482 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 156:ff21514d8981 1483 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 156:ff21514d8981 1484 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
AnnaBridge 156:ff21514d8981 1485 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1486 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1487 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 156:ff21514d8981 1488 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1489 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
AnnaBridge 156:ff21514d8981 1490 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 156:ff21514d8981 1491 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1492 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
AnnaBridge 156:ff21514d8981 1493 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 156:ff21514d8981 1494 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1495 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
AnnaBridge 156:ff21514d8981 1496 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 156:ff21514d8981 1497 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1498 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
AnnaBridge 156:ff21514d8981 1499 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 156:ff21514d8981 1500 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1501 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
AnnaBridge 156:ff21514d8981 1502 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 156:ff21514d8981 1503 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1504 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
AnnaBridge 156:ff21514d8981 1505
AnnaBridge 156:ff21514d8981 1506 /* Legacy defines */
AnnaBridge 156:ff21514d8981 1507 #define DMA_SxCR_ACK_Pos (20U)
AnnaBridge 156:ff21514d8981 1508 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1509 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
AnnaBridge 156:ff21514d8981 1510
AnnaBridge 156:ff21514d8981 1511 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 156:ff21514d8981 1512 #define DMA_SxNDT_Pos (0U)
AnnaBridge 156:ff21514d8981 1513 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 1514 #define DMA_SxNDT DMA_SxNDT_Msk
AnnaBridge 156:ff21514d8981 1515 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1516 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1517 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1518 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1519 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1520 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1521 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1522 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1523 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1524 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1525 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1526 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1527 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1528 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1529 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1530 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1531
AnnaBridge 156:ff21514d8981 1532 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 156:ff21514d8981 1533 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 156:ff21514d8981 1534 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1535 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
AnnaBridge 156:ff21514d8981 1536 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 156:ff21514d8981 1537 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 156:ff21514d8981 1538 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
AnnaBridge 156:ff21514d8981 1539 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1540 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1541 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1542 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 156:ff21514d8981 1543 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1544 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
AnnaBridge 156:ff21514d8981 1545 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 156:ff21514d8981 1546 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 1547 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
AnnaBridge 156:ff21514d8981 1548 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1549 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1550
AnnaBridge 156:ff21514d8981 1551 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 156:ff21514d8981 1552 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 156:ff21514d8981 1553 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 1554 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
AnnaBridge 156:ff21514d8981 1555 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 156:ff21514d8981 1556 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 1557 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
AnnaBridge 156:ff21514d8981 1558 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 156:ff21514d8981 1559 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 1560 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
AnnaBridge 156:ff21514d8981 1561 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 156:ff21514d8981 1562 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1563 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
AnnaBridge 156:ff21514d8981 1564 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 156:ff21514d8981 1565 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1566 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
AnnaBridge 156:ff21514d8981 1567 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 156:ff21514d8981 1568 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1569 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
AnnaBridge 156:ff21514d8981 1570 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 156:ff21514d8981 1571 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1572 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
AnnaBridge 156:ff21514d8981 1573 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 156:ff21514d8981 1574 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1575 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
AnnaBridge 156:ff21514d8981 1576 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 156:ff21514d8981 1577 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1578 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
AnnaBridge 156:ff21514d8981 1579 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 156:ff21514d8981 1580 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1581 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
AnnaBridge 156:ff21514d8981 1582 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 156:ff21514d8981 1583 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1584 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
AnnaBridge 156:ff21514d8981 1585 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 156:ff21514d8981 1586 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1587 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
AnnaBridge 156:ff21514d8981 1588 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 156:ff21514d8981 1589 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1590 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
AnnaBridge 156:ff21514d8981 1591 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 156:ff21514d8981 1592 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1593 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
AnnaBridge 156:ff21514d8981 1594 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 156:ff21514d8981 1595 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1596 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
AnnaBridge 156:ff21514d8981 1597 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 156:ff21514d8981 1598 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1599 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
AnnaBridge 156:ff21514d8981 1600 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 156:ff21514d8981 1601 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1602 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
AnnaBridge 156:ff21514d8981 1603 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 156:ff21514d8981 1604 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1605 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
AnnaBridge 156:ff21514d8981 1606 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 156:ff21514d8981 1607 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1608 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
AnnaBridge 156:ff21514d8981 1609 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 156:ff21514d8981 1610 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1611 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
AnnaBridge 156:ff21514d8981 1612
AnnaBridge 156:ff21514d8981 1613 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 156:ff21514d8981 1614 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 156:ff21514d8981 1615 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 1616 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
AnnaBridge 156:ff21514d8981 1617 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 156:ff21514d8981 1618 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 1619 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
AnnaBridge 156:ff21514d8981 1620 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 156:ff21514d8981 1621 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 1622 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
AnnaBridge 156:ff21514d8981 1623 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 156:ff21514d8981 1624 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1625 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
AnnaBridge 156:ff21514d8981 1626 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 156:ff21514d8981 1627 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1628 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
AnnaBridge 156:ff21514d8981 1629 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 156:ff21514d8981 1630 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1631 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
AnnaBridge 156:ff21514d8981 1632 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 156:ff21514d8981 1633 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1634 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
AnnaBridge 156:ff21514d8981 1635 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 156:ff21514d8981 1636 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1637 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
AnnaBridge 156:ff21514d8981 1638 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 156:ff21514d8981 1639 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1640 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
AnnaBridge 156:ff21514d8981 1641 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 156:ff21514d8981 1642 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1643 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
AnnaBridge 156:ff21514d8981 1644 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 156:ff21514d8981 1645 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1646 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
AnnaBridge 156:ff21514d8981 1647 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 156:ff21514d8981 1648 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1649 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
AnnaBridge 156:ff21514d8981 1650 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 156:ff21514d8981 1651 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1652 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
AnnaBridge 156:ff21514d8981 1653 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 156:ff21514d8981 1654 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1655 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
AnnaBridge 156:ff21514d8981 1656 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 156:ff21514d8981 1657 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1658 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
AnnaBridge 156:ff21514d8981 1659 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 156:ff21514d8981 1660 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1661 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
AnnaBridge 156:ff21514d8981 1662 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 156:ff21514d8981 1663 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1664 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
AnnaBridge 156:ff21514d8981 1665 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 156:ff21514d8981 1666 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1667 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
AnnaBridge 156:ff21514d8981 1668 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 156:ff21514d8981 1669 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1670 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
AnnaBridge 156:ff21514d8981 1671 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 156:ff21514d8981 1672 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1673 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
AnnaBridge 156:ff21514d8981 1674
AnnaBridge 156:ff21514d8981 1675 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 156:ff21514d8981 1676 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 156:ff21514d8981 1677 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 1678 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
AnnaBridge 156:ff21514d8981 1679 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 156:ff21514d8981 1680 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 1681 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
AnnaBridge 156:ff21514d8981 1682 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 156:ff21514d8981 1683 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 1684 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
AnnaBridge 156:ff21514d8981 1685 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 156:ff21514d8981 1686 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1687 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
AnnaBridge 156:ff21514d8981 1688 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 156:ff21514d8981 1689 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1690 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
AnnaBridge 156:ff21514d8981 1691 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 156:ff21514d8981 1692 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1693 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
AnnaBridge 156:ff21514d8981 1694 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 156:ff21514d8981 1695 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1696 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
AnnaBridge 156:ff21514d8981 1697 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 156:ff21514d8981 1698 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1699 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
AnnaBridge 156:ff21514d8981 1700 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 156:ff21514d8981 1701 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1702 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
AnnaBridge 156:ff21514d8981 1703 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 156:ff21514d8981 1704 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1705 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
AnnaBridge 156:ff21514d8981 1706 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 156:ff21514d8981 1707 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1708 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
AnnaBridge 156:ff21514d8981 1709 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 156:ff21514d8981 1710 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1711 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
AnnaBridge 156:ff21514d8981 1712 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 156:ff21514d8981 1713 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1714 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
AnnaBridge 156:ff21514d8981 1715 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 156:ff21514d8981 1716 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1717 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
AnnaBridge 156:ff21514d8981 1718 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 156:ff21514d8981 1719 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1720 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
AnnaBridge 156:ff21514d8981 1721 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 156:ff21514d8981 1722 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1723 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
AnnaBridge 156:ff21514d8981 1724 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 156:ff21514d8981 1725 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1726 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
AnnaBridge 156:ff21514d8981 1727 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 156:ff21514d8981 1728 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1729 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
AnnaBridge 156:ff21514d8981 1730 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 156:ff21514d8981 1731 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1732 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
AnnaBridge 156:ff21514d8981 1733 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 156:ff21514d8981 1734 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1735 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
AnnaBridge 156:ff21514d8981 1736
AnnaBridge 156:ff21514d8981 1737 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 156:ff21514d8981 1738 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 156:ff21514d8981 1739 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 1740 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
AnnaBridge 156:ff21514d8981 1741 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 156:ff21514d8981 1742 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 1743 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
AnnaBridge 156:ff21514d8981 1744 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 156:ff21514d8981 1745 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 1746 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
AnnaBridge 156:ff21514d8981 1747 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 156:ff21514d8981 1748 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 1749 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
AnnaBridge 156:ff21514d8981 1750 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 156:ff21514d8981 1751 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1752 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
AnnaBridge 156:ff21514d8981 1753 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 156:ff21514d8981 1754 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1755 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
AnnaBridge 156:ff21514d8981 1756 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 156:ff21514d8981 1757 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1758 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
AnnaBridge 156:ff21514d8981 1759 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 156:ff21514d8981 1760 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1761 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
AnnaBridge 156:ff21514d8981 1762 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 156:ff21514d8981 1763 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1764 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
AnnaBridge 156:ff21514d8981 1765 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 156:ff21514d8981 1766 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1767 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
AnnaBridge 156:ff21514d8981 1768 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 156:ff21514d8981 1769 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1770 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
AnnaBridge 156:ff21514d8981 1771 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 156:ff21514d8981 1772 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1773 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
AnnaBridge 156:ff21514d8981 1774 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 156:ff21514d8981 1775 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1776 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
AnnaBridge 156:ff21514d8981 1777 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 156:ff21514d8981 1778 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1779 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
AnnaBridge 156:ff21514d8981 1780 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 156:ff21514d8981 1781 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1782 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
AnnaBridge 156:ff21514d8981 1783 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 156:ff21514d8981 1784 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1785 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
AnnaBridge 156:ff21514d8981 1786 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 156:ff21514d8981 1787 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1788 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
AnnaBridge 156:ff21514d8981 1789 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 156:ff21514d8981 1790 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1791 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
AnnaBridge 156:ff21514d8981 1792 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 156:ff21514d8981 1793 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1794 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
AnnaBridge 156:ff21514d8981 1795 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 156:ff21514d8981 1796 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1797 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
AnnaBridge 156:ff21514d8981 1798
AnnaBridge 156:ff21514d8981 1799 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 156:ff21514d8981 1800 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 156:ff21514d8981 1801 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 1802 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 156:ff21514d8981 1803
AnnaBridge 156:ff21514d8981 1804 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 156:ff21514d8981 1805 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 156:ff21514d8981 1806 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 1807 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
AnnaBridge 156:ff21514d8981 1808
AnnaBridge 156:ff21514d8981 1809 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 156:ff21514d8981 1810 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 156:ff21514d8981 1811 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 1812 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
AnnaBridge 156:ff21514d8981 1813
AnnaBridge 156:ff21514d8981 1814
AnnaBridge 156:ff21514d8981 1815 /******************************************************************************/
AnnaBridge 156:ff21514d8981 1816 /* */
AnnaBridge 156:ff21514d8981 1817 /* External Interrupt/Event Controller */
AnnaBridge 156:ff21514d8981 1818 /* */
AnnaBridge 156:ff21514d8981 1819 /******************************************************************************/
AnnaBridge 156:ff21514d8981 1820 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 156:ff21514d8981 1821 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 156:ff21514d8981 1822 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1823 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 156:ff21514d8981 1824 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 156:ff21514d8981 1825 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1826 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 156:ff21514d8981 1827 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 156:ff21514d8981 1828 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1829 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 156:ff21514d8981 1830 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 156:ff21514d8981 1831 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1832 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 156:ff21514d8981 1833 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 156:ff21514d8981 1834 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1835 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 156:ff21514d8981 1836 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 156:ff21514d8981 1837 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1838 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 156:ff21514d8981 1839 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 156:ff21514d8981 1840 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1841 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 156:ff21514d8981 1842 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 156:ff21514d8981 1843 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1844 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 156:ff21514d8981 1845 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 156:ff21514d8981 1846 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1847 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 156:ff21514d8981 1848 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 156:ff21514d8981 1849 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1850 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 156:ff21514d8981 1851 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 156:ff21514d8981 1852 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1853 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 156:ff21514d8981 1854 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 156:ff21514d8981 1855 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1856 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 156:ff21514d8981 1857 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 156:ff21514d8981 1858 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1859 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 156:ff21514d8981 1860 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 156:ff21514d8981 1861 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1862 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 156:ff21514d8981 1863 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 156:ff21514d8981 1864 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1865 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 156:ff21514d8981 1866 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 156:ff21514d8981 1867 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1868 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 156:ff21514d8981 1869 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 156:ff21514d8981 1870 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1871 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 156:ff21514d8981 1872 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 156:ff21514d8981 1873 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1874 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 156:ff21514d8981 1875 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 156:ff21514d8981 1876 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1877 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 156:ff21514d8981 1878 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 156:ff21514d8981 1879 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1880 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 156:ff21514d8981 1881 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 156:ff21514d8981 1882 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1883 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 156:ff21514d8981 1884 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 156:ff21514d8981 1885 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1886 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 156:ff21514d8981 1887 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 156:ff21514d8981 1888 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1889 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 156:ff21514d8981 1890
AnnaBridge 156:ff21514d8981 1891 /* Reference Defines */
AnnaBridge 156:ff21514d8981 1892 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 156:ff21514d8981 1893 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 156:ff21514d8981 1894 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 156:ff21514d8981 1895 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 156:ff21514d8981 1896 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 156:ff21514d8981 1897 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 156:ff21514d8981 1898 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 156:ff21514d8981 1899 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 156:ff21514d8981 1900 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 156:ff21514d8981 1901 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 156:ff21514d8981 1902 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 156:ff21514d8981 1903 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 156:ff21514d8981 1904 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 156:ff21514d8981 1905 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 156:ff21514d8981 1906 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 156:ff21514d8981 1907 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 156:ff21514d8981 1908 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 156:ff21514d8981 1909 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 156:ff21514d8981 1910 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 156:ff21514d8981 1911 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 156:ff21514d8981 1912 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 156:ff21514d8981 1913 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 156:ff21514d8981 1914 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 156:ff21514d8981 1915 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 156:ff21514d8981 1916 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
AnnaBridge 156:ff21514d8981 1917 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 156:ff21514d8981 1918
AnnaBridge 156:ff21514d8981 1919 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 156:ff21514d8981 1920 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 156:ff21514d8981 1921 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 1922 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 156:ff21514d8981 1923 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 156:ff21514d8981 1924 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 1925 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 156:ff21514d8981 1926 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 156:ff21514d8981 1927 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 1928 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 156:ff21514d8981 1929 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 156:ff21514d8981 1930 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 1931 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 156:ff21514d8981 1932 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 156:ff21514d8981 1933 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 1934 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 156:ff21514d8981 1935 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 156:ff21514d8981 1936 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 1937 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 156:ff21514d8981 1938 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 156:ff21514d8981 1939 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 1940 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 156:ff21514d8981 1941 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 156:ff21514d8981 1942 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 1943 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 156:ff21514d8981 1944 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 156:ff21514d8981 1945 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 1946 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 156:ff21514d8981 1947 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 156:ff21514d8981 1948 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 1949 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 156:ff21514d8981 1950 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 156:ff21514d8981 1951 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 1952 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 156:ff21514d8981 1953 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 156:ff21514d8981 1954 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 1955 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 156:ff21514d8981 1956 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 156:ff21514d8981 1957 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 1958 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 156:ff21514d8981 1959 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 156:ff21514d8981 1960 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 1961 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 156:ff21514d8981 1962 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 156:ff21514d8981 1963 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 1964 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 156:ff21514d8981 1965 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 156:ff21514d8981 1966 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 1967 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 156:ff21514d8981 1968 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 156:ff21514d8981 1969 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 1970 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 156:ff21514d8981 1971 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 156:ff21514d8981 1972 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 1973 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 156:ff21514d8981 1974 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 156:ff21514d8981 1975 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 1976 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 156:ff21514d8981 1977 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 156:ff21514d8981 1978 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 1979 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 156:ff21514d8981 1980 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 156:ff21514d8981 1981 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 1982 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 156:ff21514d8981 1983 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 156:ff21514d8981 1984 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 1985 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 156:ff21514d8981 1986 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 156:ff21514d8981 1987 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 1988 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 156:ff21514d8981 1989
AnnaBridge 156:ff21514d8981 1990 /* Reference Defines */
AnnaBridge 156:ff21514d8981 1991 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 156:ff21514d8981 1992 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 156:ff21514d8981 1993 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 156:ff21514d8981 1994 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 156:ff21514d8981 1995 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 156:ff21514d8981 1996 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 156:ff21514d8981 1997 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 156:ff21514d8981 1998 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 156:ff21514d8981 1999 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 156:ff21514d8981 2000 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 156:ff21514d8981 2001 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 156:ff21514d8981 2002 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 156:ff21514d8981 2003 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 156:ff21514d8981 2004 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 156:ff21514d8981 2005 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 156:ff21514d8981 2006 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 156:ff21514d8981 2007 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 156:ff21514d8981 2008 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 156:ff21514d8981 2009 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 156:ff21514d8981 2010 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 156:ff21514d8981 2011 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 156:ff21514d8981 2012 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 156:ff21514d8981 2013 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 156:ff21514d8981 2014
AnnaBridge 156:ff21514d8981 2015 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 156:ff21514d8981 2016 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 156:ff21514d8981 2017 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2018 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 156:ff21514d8981 2019 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 156:ff21514d8981 2020 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2021 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 156:ff21514d8981 2022 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 156:ff21514d8981 2023 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2024 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 156:ff21514d8981 2025 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 156:ff21514d8981 2026 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2027 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 156:ff21514d8981 2028 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 156:ff21514d8981 2029 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2030 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 156:ff21514d8981 2031 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 156:ff21514d8981 2032 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2033 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 156:ff21514d8981 2034 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 156:ff21514d8981 2035 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2036 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 156:ff21514d8981 2037 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 156:ff21514d8981 2038 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2039 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 156:ff21514d8981 2040 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 156:ff21514d8981 2041 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2042 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 156:ff21514d8981 2043 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 156:ff21514d8981 2044 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2045 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 156:ff21514d8981 2046 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 156:ff21514d8981 2047 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2048 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 156:ff21514d8981 2049 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 156:ff21514d8981 2050 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2051 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 156:ff21514d8981 2052 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 156:ff21514d8981 2053 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2054 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 156:ff21514d8981 2055 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 156:ff21514d8981 2056 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2057 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 156:ff21514d8981 2058 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 156:ff21514d8981 2059 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2060 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 156:ff21514d8981 2061 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 156:ff21514d8981 2062 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2063 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 156:ff21514d8981 2064 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 156:ff21514d8981 2065 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2066 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 156:ff21514d8981 2067 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 156:ff21514d8981 2068 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2069 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 156:ff21514d8981 2070 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 156:ff21514d8981 2071 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2072 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 156:ff21514d8981 2073 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 156:ff21514d8981 2074 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2075 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 156:ff21514d8981 2076 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 156:ff21514d8981 2077 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2078 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 156:ff21514d8981 2079 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 156:ff21514d8981 2080 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2081 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 156:ff21514d8981 2082 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 156:ff21514d8981 2083 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2084 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 156:ff21514d8981 2085
AnnaBridge 156:ff21514d8981 2086 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 156:ff21514d8981 2087 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 156:ff21514d8981 2088 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2089 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 156:ff21514d8981 2090 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 156:ff21514d8981 2091 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2092 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 156:ff21514d8981 2093 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 156:ff21514d8981 2094 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2095 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 156:ff21514d8981 2096 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 156:ff21514d8981 2097 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2098 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 156:ff21514d8981 2099 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 156:ff21514d8981 2100 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2101 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 156:ff21514d8981 2102 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 156:ff21514d8981 2103 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2104 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 156:ff21514d8981 2105 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 156:ff21514d8981 2106 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2107 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 156:ff21514d8981 2108 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 156:ff21514d8981 2109 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2110 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 156:ff21514d8981 2111 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 156:ff21514d8981 2112 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2113 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 156:ff21514d8981 2114 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 156:ff21514d8981 2115 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2116 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 156:ff21514d8981 2117 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 156:ff21514d8981 2118 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2119 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 156:ff21514d8981 2120 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 156:ff21514d8981 2121 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2122 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 156:ff21514d8981 2123 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 156:ff21514d8981 2124 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2125 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 156:ff21514d8981 2126 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 156:ff21514d8981 2127 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2128 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 156:ff21514d8981 2129 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 156:ff21514d8981 2130 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2131 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 156:ff21514d8981 2132 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 156:ff21514d8981 2133 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2134 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 156:ff21514d8981 2135 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 156:ff21514d8981 2136 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2137 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 156:ff21514d8981 2138 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 156:ff21514d8981 2139 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2140 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 156:ff21514d8981 2141 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 156:ff21514d8981 2142 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2143 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 156:ff21514d8981 2144 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 156:ff21514d8981 2145 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2146 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 156:ff21514d8981 2147 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 156:ff21514d8981 2148 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2149 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 156:ff21514d8981 2150 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 156:ff21514d8981 2151 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2152 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 156:ff21514d8981 2153 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 156:ff21514d8981 2154 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2155 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 156:ff21514d8981 2156
AnnaBridge 156:ff21514d8981 2157 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 156:ff21514d8981 2158 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 156:ff21514d8981 2159 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2160 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 156:ff21514d8981 2161 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 156:ff21514d8981 2162 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2163 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 156:ff21514d8981 2164 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 156:ff21514d8981 2165 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2166 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 156:ff21514d8981 2167 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 156:ff21514d8981 2168 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2169 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 156:ff21514d8981 2170 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 156:ff21514d8981 2171 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2172 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 156:ff21514d8981 2173 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 156:ff21514d8981 2174 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2175 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 156:ff21514d8981 2176 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 156:ff21514d8981 2177 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2178 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 156:ff21514d8981 2179 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 156:ff21514d8981 2180 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2181 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 156:ff21514d8981 2182 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 156:ff21514d8981 2183 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2184 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 156:ff21514d8981 2185 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 156:ff21514d8981 2186 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2187 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 156:ff21514d8981 2188 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 156:ff21514d8981 2189 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2190 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 156:ff21514d8981 2191 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 156:ff21514d8981 2192 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2193 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 156:ff21514d8981 2194 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 156:ff21514d8981 2195 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2196 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 156:ff21514d8981 2197 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 156:ff21514d8981 2198 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2199 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 156:ff21514d8981 2200 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 156:ff21514d8981 2201 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2202 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 156:ff21514d8981 2203 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 156:ff21514d8981 2204 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2205 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 156:ff21514d8981 2206 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 156:ff21514d8981 2207 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2208 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 156:ff21514d8981 2209 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 156:ff21514d8981 2210 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2211 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 156:ff21514d8981 2212 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 156:ff21514d8981 2213 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2214 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 156:ff21514d8981 2215 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 156:ff21514d8981 2216 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2217 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 156:ff21514d8981 2218 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 156:ff21514d8981 2219 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2220 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 156:ff21514d8981 2221 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 156:ff21514d8981 2222 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2223 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 156:ff21514d8981 2224 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 156:ff21514d8981 2225 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2226 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 156:ff21514d8981 2227
AnnaBridge 156:ff21514d8981 2228 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 156:ff21514d8981 2229 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 156:ff21514d8981 2230 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2231 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 156:ff21514d8981 2232 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 156:ff21514d8981 2233 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2234 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 156:ff21514d8981 2235 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 156:ff21514d8981 2236 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2237 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 156:ff21514d8981 2238 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 156:ff21514d8981 2239 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2240 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 156:ff21514d8981 2241 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 156:ff21514d8981 2242 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2243 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 156:ff21514d8981 2244 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 156:ff21514d8981 2245 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2246 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 156:ff21514d8981 2247 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 156:ff21514d8981 2248 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2249 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 156:ff21514d8981 2250 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 156:ff21514d8981 2251 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2252 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 156:ff21514d8981 2253 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 156:ff21514d8981 2254 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2255 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 156:ff21514d8981 2256 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 156:ff21514d8981 2257 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2258 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 156:ff21514d8981 2259 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 156:ff21514d8981 2260 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2261 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 156:ff21514d8981 2262 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 156:ff21514d8981 2263 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2264 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 156:ff21514d8981 2265 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 156:ff21514d8981 2266 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2267 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 156:ff21514d8981 2268 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 156:ff21514d8981 2269 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2270 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 156:ff21514d8981 2271 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 156:ff21514d8981 2272 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2273 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 156:ff21514d8981 2274 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 156:ff21514d8981 2275 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2276 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 156:ff21514d8981 2277 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 156:ff21514d8981 2278 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2279 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 156:ff21514d8981 2280 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 156:ff21514d8981 2281 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2282 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 156:ff21514d8981 2283 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 156:ff21514d8981 2284 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2285 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 156:ff21514d8981 2286 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 156:ff21514d8981 2287 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2288 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 156:ff21514d8981 2289 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 156:ff21514d8981 2290 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2291 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 156:ff21514d8981 2292 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 156:ff21514d8981 2293 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2294 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 156:ff21514d8981 2295 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 156:ff21514d8981 2296 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2297 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
AnnaBridge 156:ff21514d8981 2298
AnnaBridge 156:ff21514d8981 2299 /******************************************************************************/
AnnaBridge 156:ff21514d8981 2300 /* */
AnnaBridge 156:ff21514d8981 2301 /* FLASH */
AnnaBridge 156:ff21514d8981 2302 /* */
AnnaBridge 156:ff21514d8981 2303 /******************************************************************************/
AnnaBridge 156:ff21514d8981 2304 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 156:ff21514d8981 2305 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 156:ff21514d8981 2306 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 2307 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 156:ff21514d8981 2308 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 156:ff21514d8981 2309 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 156:ff21514d8981 2310 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 156:ff21514d8981 2311 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 156:ff21514d8981 2312 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 156:ff21514d8981 2313 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 156:ff21514d8981 2314 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 156:ff21514d8981 2315 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 156:ff21514d8981 2316
AnnaBridge 156:ff21514d8981 2317 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 156:ff21514d8981 2318 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2319 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 156:ff21514d8981 2320 #define FLASH_ACR_ICEN_Pos (9U)
AnnaBridge 156:ff21514d8981 2321 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2322 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
AnnaBridge 156:ff21514d8981 2323 #define FLASH_ACR_DCEN_Pos (10U)
AnnaBridge 156:ff21514d8981 2324 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2325 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
AnnaBridge 156:ff21514d8981 2326 #define FLASH_ACR_ICRST_Pos (11U)
AnnaBridge 156:ff21514d8981 2327 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2328 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
AnnaBridge 156:ff21514d8981 2329 #define FLASH_ACR_DCRST_Pos (12U)
AnnaBridge 156:ff21514d8981 2330 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2331 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
AnnaBridge 156:ff21514d8981 2332 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
AnnaBridge 156:ff21514d8981 2333 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
AnnaBridge 156:ff21514d8981 2334 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
AnnaBridge 156:ff21514d8981 2335 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
AnnaBridge 156:ff21514d8981 2336 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
AnnaBridge 156:ff21514d8981 2337 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
AnnaBridge 156:ff21514d8981 2338
AnnaBridge 156:ff21514d8981 2339 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 156:ff21514d8981 2340 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 156:ff21514d8981 2341 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2342 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 156:ff21514d8981 2343 #define FLASH_SR_SOP_Pos (1U)
AnnaBridge 156:ff21514d8981 2344 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2345 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
AnnaBridge 156:ff21514d8981 2346 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 156:ff21514d8981 2347 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2348 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 156:ff21514d8981 2349 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 156:ff21514d8981 2350 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2351 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 156:ff21514d8981 2352 #define FLASH_SR_PGPERR_Pos (6U)
AnnaBridge 156:ff21514d8981 2353 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2354 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
AnnaBridge 156:ff21514d8981 2355 #define FLASH_SR_PGSERR_Pos (7U)
AnnaBridge 156:ff21514d8981 2356 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2357 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 156:ff21514d8981 2358 #define FLASH_SR_RDERR_Pos (8U)
AnnaBridge 156:ff21514d8981 2359 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2360 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
AnnaBridge 156:ff21514d8981 2361 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 156:ff21514d8981 2362 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2363 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
AnnaBridge 156:ff21514d8981 2364
AnnaBridge 156:ff21514d8981 2365 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 156:ff21514d8981 2366 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 156:ff21514d8981 2367 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2368 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 156:ff21514d8981 2369 #define FLASH_CR_SER_Pos (1U)
AnnaBridge 156:ff21514d8981 2370 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2371 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 156:ff21514d8981 2372 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 156:ff21514d8981 2373 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2374 #define FLASH_CR_MER FLASH_CR_MER_Msk
AnnaBridge 156:ff21514d8981 2375 #define FLASH_CR_SNB_Pos (3U)
AnnaBridge 156:ff21514d8981 2376 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
AnnaBridge 156:ff21514d8981 2377 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 156:ff21514d8981 2378 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2379 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2380 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2381 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2382 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2383 #define FLASH_CR_PSIZE_Pos (8U)
AnnaBridge 156:ff21514d8981 2384 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 2385 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 156:ff21514d8981 2386 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2387 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2388 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 156:ff21514d8981 2389 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2390 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 156:ff21514d8981 2391 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 156:ff21514d8981 2392 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 2393 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 156:ff21514d8981 2394 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 156:ff21514d8981 2395 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 2396 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
AnnaBridge 156:ff21514d8981 2397
AnnaBridge 156:ff21514d8981 2398 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 156:ff21514d8981 2399 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 156:ff21514d8981 2400 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2401 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 156:ff21514d8981 2402 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
AnnaBridge 156:ff21514d8981 2403 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2404 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
AnnaBridge 156:ff21514d8981 2405
AnnaBridge 156:ff21514d8981 2406 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
AnnaBridge 156:ff21514d8981 2407 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
AnnaBridge 156:ff21514d8981 2408 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
AnnaBridge 156:ff21514d8981 2409 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 156:ff21514d8981 2410 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
AnnaBridge 156:ff21514d8981 2411 #define FLASH_OPTCR_WDG_SW_Pos (5U)
AnnaBridge 156:ff21514d8981 2412 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2413 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
AnnaBridge 156:ff21514d8981 2414 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
AnnaBridge 156:ff21514d8981 2415 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2416 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
AnnaBridge 156:ff21514d8981 2417 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
AnnaBridge 156:ff21514d8981 2418 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2419 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
AnnaBridge 156:ff21514d8981 2420 #define FLASH_OPTCR_RDP_Pos (8U)
AnnaBridge 156:ff21514d8981 2421 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 156:ff21514d8981 2422 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
AnnaBridge 156:ff21514d8981 2423 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2424 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2425 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2426 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2427 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2428 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2429 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2430 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2431 #define FLASH_OPTCR_nWRP_Pos (16U)
AnnaBridge 156:ff21514d8981 2432 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 156:ff21514d8981 2433 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
AnnaBridge 156:ff21514d8981 2434 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 156:ff21514d8981 2435 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 156:ff21514d8981 2436 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 156:ff21514d8981 2437 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 156:ff21514d8981 2438 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 156:ff21514d8981 2439 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 156:ff21514d8981 2440 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 156:ff21514d8981 2441 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 156:ff21514d8981 2442 #define FLASH_OPTCR_nWRP_8 0x01000000U
AnnaBridge 156:ff21514d8981 2443 #define FLASH_OPTCR_nWRP_9 0x02000000U
AnnaBridge 156:ff21514d8981 2444 #define FLASH_OPTCR_nWRP_10 0x04000000U
AnnaBridge 156:ff21514d8981 2445 #define FLASH_OPTCR_nWRP_11 0x08000000U
AnnaBridge 156:ff21514d8981 2446
AnnaBridge 156:ff21514d8981 2447 /****************** Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 156:ff21514d8981 2448 #define FLASH_OPTCR1_nWRP_Pos (16U)
AnnaBridge 156:ff21514d8981 2449 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 156:ff21514d8981 2450 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
AnnaBridge 156:ff21514d8981 2451 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2452 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2453 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2454 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2455 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2456 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2457 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2458 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 2459 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 2460 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 2461 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 2462 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 2463
AnnaBridge 156:ff21514d8981 2464 /******************************************************************************/
AnnaBridge 156:ff21514d8981 2465 /* */
AnnaBridge 156:ff21514d8981 2466 /* General Purpose I/O */
AnnaBridge 156:ff21514d8981 2467 /* */
AnnaBridge 156:ff21514d8981 2468 /******************************************************************************/
AnnaBridge 156:ff21514d8981 2469 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 156:ff21514d8981 2470 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 156:ff21514d8981 2471 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 2472 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 156:ff21514d8981 2473 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2474 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2475 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 156:ff21514d8981 2476 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 156:ff21514d8981 2477 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 156:ff21514d8981 2478 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2479 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2480 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 156:ff21514d8981 2481 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 156:ff21514d8981 2482 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 156:ff21514d8981 2483 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2484 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2485 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 156:ff21514d8981 2486 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 156:ff21514d8981 2487 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 156:ff21514d8981 2488 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2489 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2490 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 156:ff21514d8981 2491 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 2492 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 156:ff21514d8981 2493 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2494 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2495 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 156:ff21514d8981 2496 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 156:ff21514d8981 2497 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 156:ff21514d8981 2498 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2499 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2500 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 156:ff21514d8981 2501 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 156:ff21514d8981 2502 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 156:ff21514d8981 2503 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2504 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2505 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 156:ff21514d8981 2506 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 156:ff21514d8981 2507 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 156:ff21514d8981 2508 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2509 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2510 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 156:ff21514d8981 2511 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 156:ff21514d8981 2512 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 156:ff21514d8981 2513 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2514 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2515 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 156:ff21514d8981 2516 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 156:ff21514d8981 2517 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 156:ff21514d8981 2518 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2519 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2520 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 156:ff21514d8981 2521 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 2522 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 156:ff21514d8981 2523 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2524 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2525 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 156:ff21514d8981 2526 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 156:ff21514d8981 2527 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 156:ff21514d8981 2528 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2529 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 2530 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 156:ff21514d8981 2531 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 156:ff21514d8981 2532 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 156:ff21514d8981 2533 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 2534 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 2535 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 156:ff21514d8981 2536 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 156:ff21514d8981 2537 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 156:ff21514d8981 2538 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 2539 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 2540 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 156:ff21514d8981 2541 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 156:ff21514d8981 2542 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 156:ff21514d8981 2543 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 2544 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 2545 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 156:ff21514d8981 2546 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 156:ff21514d8981 2547 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 156:ff21514d8981 2548 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 2549 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 2550
AnnaBridge 156:ff21514d8981 2551 /* Legacy defines */
AnnaBridge 156:ff21514d8981 2552 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 156:ff21514d8981 2553 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 2554 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 156:ff21514d8981 2555 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2556 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2557 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 156:ff21514d8981 2558 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 156:ff21514d8981 2559 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 156:ff21514d8981 2560 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2561 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2562 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 156:ff21514d8981 2563 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 156:ff21514d8981 2564 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 156:ff21514d8981 2565 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2566 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2567 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 156:ff21514d8981 2568 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 156:ff21514d8981 2569 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 156:ff21514d8981 2570 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2571 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2572 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 156:ff21514d8981 2573 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 2574 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 156:ff21514d8981 2575 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2576 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2577 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 156:ff21514d8981 2578 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 156:ff21514d8981 2579 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 156:ff21514d8981 2580 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2581 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2582 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 156:ff21514d8981 2583 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 156:ff21514d8981 2584 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 156:ff21514d8981 2585 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2586 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2587 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 156:ff21514d8981 2588 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 156:ff21514d8981 2589 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 156:ff21514d8981 2590 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2591 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2592 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 156:ff21514d8981 2593 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 156:ff21514d8981 2594 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 156:ff21514d8981 2595 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2596 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2597 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 156:ff21514d8981 2598 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 156:ff21514d8981 2599 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 156:ff21514d8981 2600 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2601 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2602 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 156:ff21514d8981 2603 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 2604 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 156:ff21514d8981 2605 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2606 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2607 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 156:ff21514d8981 2608 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 156:ff21514d8981 2609 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 156:ff21514d8981 2610 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2611 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 2612 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 156:ff21514d8981 2613 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 156:ff21514d8981 2614 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 156:ff21514d8981 2615 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 2616 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 2617 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 156:ff21514d8981 2618 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 156:ff21514d8981 2619 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 156:ff21514d8981 2620 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 2621 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 2622 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 156:ff21514d8981 2623 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 156:ff21514d8981 2624 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 156:ff21514d8981 2625 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 2626 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 2627 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 156:ff21514d8981 2628 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 156:ff21514d8981 2629 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 156:ff21514d8981 2630 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 2631 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 2632
AnnaBridge 156:ff21514d8981 2633 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 156:ff21514d8981 2634 #define GPIO_OTYPER_OT0_Pos (0U)
AnnaBridge 156:ff21514d8981 2635 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2636 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
AnnaBridge 156:ff21514d8981 2637 #define GPIO_OTYPER_OT1_Pos (1U)
AnnaBridge 156:ff21514d8981 2638 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2639 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
AnnaBridge 156:ff21514d8981 2640 #define GPIO_OTYPER_OT2_Pos (2U)
AnnaBridge 156:ff21514d8981 2641 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2642 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
AnnaBridge 156:ff21514d8981 2643 #define GPIO_OTYPER_OT3_Pos (3U)
AnnaBridge 156:ff21514d8981 2644 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2645 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
AnnaBridge 156:ff21514d8981 2646 #define GPIO_OTYPER_OT4_Pos (4U)
AnnaBridge 156:ff21514d8981 2647 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2648 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
AnnaBridge 156:ff21514d8981 2649 #define GPIO_OTYPER_OT5_Pos (5U)
AnnaBridge 156:ff21514d8981 2650 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2651 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
AnnaBridge 156:ff21514d8981 2652 #define GPIO_OTYPER_OT6_Pos (6U)
AnnaBridge 156:ff21514d8981 2653 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2654 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
AnnaBridge 156:ff21514d8981 2655 #define GPIO_OTYPER_OT7_Pos (7U)
AnnaBridge 156:ff21514d8981 2656 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2657 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
AnnaBridge 156:ff21514d8981 2658 #define GPIO_OTYPER_OT8_Pos (8U)
AnnaBridge 156:ff21514d8981 2659 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2660 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
AnnaBridge 156:ff21514d8981 2661 #define GPIO_OTYPER_OT9_Pos (9U)
AnnaBridge 156:ff21514d8981 2662 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2663 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
AnnaBridge 156:ff21514d8981 2664 #define GPIO_OTYPER_OT10_Pos (10U)
AnnaBridge 156:ff21514d8981 2665 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2666 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
AnnaBridge 156:ff21514d8981 2667 #define GPIO_OTYPER_OT11_Pos (11U)
AnnaBridge 156:ff21514d8981 2668 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2669 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
AnnaBridge 156:ff21514d8981 2670 #define GPIO_OTYPER_OT12_Pos (12U)
AnnaBridge 156:ff21514d8981 2671 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2672 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
AnnaBridge 156:ff21514d8981 2673 #define GPIO_OTYPER_OT13_Pos (13U)
AnnaBridge 156:ff21514d8981 2674 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2675 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
AnnaBridge 156:ff21514d8981 2676 #define GPIO_OTYPER_OT14_Pos (14U)
AnnaBridge 156:ff21514d8981 2677 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2678 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
AnnaBridge 156:ff21514d8981 2679 #define GPIO_OTYPER_OT15_Pos (15U)
AnnaBridge 156:ff21514d8981 2680 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2681 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
AnnaBridge 156:ff21514d8981 2682
AnnaBridge 156:ff21514d8981 2683 /* Legacy defines */
AnnaBridge 156:ff21514d8981 2684 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
AnnaBridge 156:ff21514d8981 2685 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
AnnaBridge 156:ff21514d8981 2686 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
AnnaBridge 156:ff21514d8981 2687 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
AnnaBridge 156:ff21514d8981 2688 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
AnnaBridge 156:ff21514d8981 2689 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
AnnaBridge 156:ff21514d8981 2690 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
AnnaBridge 156:ff21514d8981 2691 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
AnnaBridge 156:ff21514d8981 2692 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
AnnaBridge 156:ff21514d8981 2693 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
AnnaBridge 156:ff21514d8981 2694 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
AnnaBridge 156:ff21514d8981 2695 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
AnnaBridge 156:ff21514d8981 2696 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
AnnaBridge 156:ff21514d8981 2697 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
AnnaBridge 156:ff21514d8981 2698 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
AnnaBridge 156:ff21514d8981 2699 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
AnnaBridge 156:ff21514d8981 2700
AnnaBridge 156:ff21514d8981 2701 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 156:ff21514d8981 2702 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
AnnaBridge 156:ff21514d8981 2703 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 2704 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
AnnaBridge 156:ff21514d8981 2705 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2706 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2707 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
AnnaBridge 156:ff21514d8981 2708 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 156:ff21514d8981 2709 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
AnnaBridge 156:ff21514d8981 2710 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2711 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2712 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
AnnaBridge 156:ff21514d8981 2713 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 156:ff21514d8981 2714 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
AnnaBridge 156:ff21514d8981 2715 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2716 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2717 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
AnnaBridge 156:ff21514d8981 2718 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 156:ff21514d8981 2719 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
AnnaBridge 156:ff21514d8981 2720 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2721 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2722 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
AnnaBridge 156:ff21514d8981 2723 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 2724 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
AnnaBridge 156:ff21514d8981 2725 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2726 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2727 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
AnnaBridge 156:ff21514d8981 2728 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 156:ff21514d8981 2729 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
AnnaBridge 156:ff21514d8981 2730 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2731 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2732 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
AnnaBridge 156:ff21514d8981 2733 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 156:ff21514d8981 2734 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
AnnaBridge 156:ff21514d8981 2735 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2736 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2737 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
AnnaBridge 156:ff21514d8981 2738 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 156:ff21514d8981 2739 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
AnnaBridge 156:ff21514d8981 2740 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2741 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2742 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
AnnaBridge 156:ff21514d8981 2743 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 156:ff21514d8981 2744 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
AnnaBridge 156:ff21514d8981 2745 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2746 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2747 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
AnnaBridge 156:ff21514d8981 2748 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 156:ff21514d8981 2749 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
AnnaBridge 156:ff21514d8981 2750 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2751 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2752 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
AnnaBridge 156:ff21514d8981 2753 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 2754 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
AnnaBridge 156:ff21514d8981 2755 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2756 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2757 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
AnnaBridge 156:ff21514d8981 2758 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 156:ff21514d8981 2759 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
AnnaBridge 156:ff21514d8981 2760 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2761 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 2762 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
AnnaBridge 156:ff21514d8981 2763 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 156:ff21514d8981 2764 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
AnnaBridge 156:ff21514d8981 2765 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 2766 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 2767 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
AnnaBridge 156:ff21514d8981 2768 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 156:ff21514d8981 2769 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
AnnaBridge 156:ff21514d8981 2770 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 2771 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 2772 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
AnnaBridge 156:ff21514d8981 2773 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 156:ff21514d8981 2774 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
AnnaBridge 156:ff21514d8981 2775 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 2776 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 2777 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
AnnaBridge 156:ff21514d8981 2778 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 156:ff21514d8981 2779 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
AnnaBridge 156:ff21514d8981 2780 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 2781 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 2782
AnnaBridge 156:ff21514d8981 2783 /* Legacy defines */
AnnaBridge 156:ff21514d8981 2784 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
AnnaBridge 156:ff21514d8981 2785 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
AnnaBridge 156:ff21514d8981 2786 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
AnnaBridge 156:ff21514d8981 2787 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
AnnaBridge 156:ff21514d8981 2788 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
AnnaBridge 156:ff21514d8981 2789 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
AnnaBridge 156:ff21514d8981 2790 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
AnnaBridge 156:ff21514d8981 2791 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
AnnaBridge 156:ff21514d8981 2792 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
AnnaBridge 156:ff21514d8981 2793 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
AnnaBridge 156:ff21514d8981 2794 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
AnnaBridge 156:ff21514d8981 2795 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
AnnaBridge 156:ff21514d8981 2796 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
AnnaBridge 156:ff21514d8981 2797 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
AnnaBridge 156:ff21514d8981 2798 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
AnnaBridge 156:ff21514d8981 2799 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
AnnaBridge 156:ff21514d8981 2800 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
AnnaBridge 156:ff21514d8981 2801 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
AnnaBridge 156:ff21514d8981 2802 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
AnnaBridge 156:ff21514d8981 2803 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
AnnaBridge 156:ff21514d8981 2804 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
AnnaBridge 156:ff21514d8981 2805 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
AnnaBridge 156:ff21514d8981 2806 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
AnnaBridge 156:ff21514d8981 2807 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
AnnaBridge 156:ff21514d8981 2808 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
AnnaBridge 156:ff21514d8981 2809 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
AnnaBridge 156:ff21514d8981 2810 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
AnnaBridge 156:ff21514d8981 2811 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
AnnaBridge 156:ff21514d8981 2812 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
AnnaBridge 156:ff21514d8981 2813 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
AnnaBridge 156:ff21514d8981 2814 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
AnnaBridge 156:ff21514d8981 2815 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
AnnaBridge 156:ff21514d8981 2816 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
AnnaBridge 156:ff21514d8981 2817 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
AnnaBridge 156:ff21514d8981 2818 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
AnnaBridge 156:ff21514d8981 2819 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
AnnaBridge 156:ff21514d8981 2820 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
AnnaBridge 156:ff21514d8981 2821 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
AnnaBridge 156:ff21514d8981 2822 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
AnnaBridge 156:ff21514d8981 2823 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
AnnaBridge 156:ff21514d8981 2824 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
AnnaBridge 156:ff21514d8981 2825 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
AnnaBridge 156:ff21514d8981 2826 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
AnnaBridge 156:ff21514d8981 2827 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
AnnaBridge 156:ff21514d8981 2828 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
AnnaBridge 156:ff21514d8981 2829 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
AnnaBridge 156:ff21514d8981 2830 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
AnnaBridge 156:ff21514d8981 2831 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
AnnaBridge 156:ff21514d8981 2832
AnnaBridge 156:ff21514d8981 2833 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 156:ff21514d8981 2834 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 156:ff21514d8981 2835 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 2836 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 156:ff21514d8981 2837 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2838 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2839 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 156:ff21514d8981 2840 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 156:ff21514d8981 2841 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 156:ff21514d8981 2842 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2843 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2844 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 156:ff21514d8981 2845 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 156:ff21514d8981 2846 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 156:ff21514d8981 2847 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2848 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2849 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 156:ff21514d8981 2850 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 156:ff21514d8981 2851 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 156:ff21514d8981 2852 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2853 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2854 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 156:ff21514d8981 2855 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 2856 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 156:ff21514d8981 2857 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2858 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2859 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 156:ff21514d8981 2860 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 156:ff21514d8981 2861 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 156:ff21514d8981 2862 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2863 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 2864 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 156:ff21514d8981 2865 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 156:ff21514d8981 2866 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 156:ff21514d8981 2867 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 2868 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 2869 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 156:ff21514d8981 2870 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 156:ff21514d8981 2871 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 156:ff21514d8981 2872 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 2873 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 2874 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 156:ff21514d8981 2875 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 156:ff21514d8981 2876 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 156:ff21514d8981 2877 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 2878 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 2879 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 156:ff21514d8981 2880 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 156:ff21514d8981 2881 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 156:ff21514d8981 2882 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 2883 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 2884 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 156:ff21514d8981 2885 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 2886 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 156:ff21514d8981 2887 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 2888 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 2889 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 156:ff21514d8981 2890 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 156:ff21514d8981 2891 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 156:ff21514d8981 2892 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 2893 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 2894 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 156:ff21514d8981 2895 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 156:ff21514d8981 2896 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 156:ff21514d8981 2897 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 2898 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 2899 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 156:ff21514d8981 2900 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 156:ff21514d8981 2901 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 156:ff21514d8981 2902 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 2903 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 2904 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 156:ff21514d8981 2905 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 156:ff21514d8981 2906 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 156:ff21514d8981 2907 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 2908 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 2909 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 156:ff21514d8981 2910 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 156:ff21514d8981 2911 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 156:ff21514d8981 2912 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 2913 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 2914
AnnaBridge 156:ff21514d8981 2915 /* Legacy defines */
AnnaBridge 156:ff21514d8981 2916 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
AnnaBridge 156:ff21514d8981 2917 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
AnnaBridge 156:ff21514d8981 2918 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
AnnaBridge 156:ff21514d8981 2919 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
AnnaBridge 156:ff21514d8981 2920 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
AnnaBridge 156:ff21514d8981 2921 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
AnnaBridge 156:ff21514d8981 2922 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
AnnaBridge 156:ff21514d8981 2923 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
AnnaBridge 156:ff21514d8981 2924 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
AnnaBridge 156:ff21514d8981 2925 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
AnnaBridge 156:ff21514d8981 2926 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
AnnaBridge 156:ff21514d8981 2927 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
AnnaBridge 156:ff21514d8981 2928 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
AnnaBridge 156:ff21514d8981 2929 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
AnnaBridge 156:ff21514d8981 2930 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
AnnaBridge 156:ff21514d8981 2931 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
AnnaBridge 156:ff21514d8981 2932 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
AnnaBridge 156:ff21514d8981 2933 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
AnnaBridge 156:ff21514d8981 2934 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
AnnaBridge 156:ff21514d8981 2935 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
AnnaBridge 156:ff21514d8981 2936 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
AnnaBridge 156:ff21514d8981 2937 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
AnnaBridge 156:ff21514d8981 2938 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
AnnaBridge 156:ff21514d8981 2939 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
AnnaBridge 156:ff21514d8981 2940 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
AnnaBridge 156:ff21514d8981 2941 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
AnnaBridge 156:ff21514d8981 2942 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
AnnaBridge 156:ff21514d8981 2943 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
AnnaBridge 156:ff21514d8981 2944 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
AnnaBridge 156:ff21514d8981 2945 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
AnnaBridge 156:ff21514d8981 2946 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
AnnaBridge 156:ff21514d8981 2947 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
AnnaBridge 156:ff21514d8981 2948 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
AnnaBridge 156:ff21514d8981 2949 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
AnnaBridge 156:ff21514d8981 2950 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
AnnaBridge 156:ff21514d8981 2951 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
AnnaBridge 156:ff21514d8981 2952 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
AnnaBridge 156:ff21514d8981 2953 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
AnnaBridge 156:ff21514d8981 2954 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
AnnaBridge 156:ff21514d8981 2955 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
AnnaBridge 156:ff21514d8981 2956 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
AnnaBridge 156:ff21514d8981 2957 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
AnnaBridge 156:ff21514d8981 2958 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
AnnaBridge 156:ff21514d8981 2959 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
AnnaBridge 156:ff21514d8981 2960 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
AnnaBridge 156:ff21514d8981 2961 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
AnnaBridge 156:ff21514d8981 2962 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
AnnaBridge 156:ff21514d8981 2963 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
AnnaBridge 156:ff21514d8981 2964
AnnaBridge 156:ff21514d8981 2965 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 156:ff21514d8981 2966 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 156:ff21514d8981 2967 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 2968 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 156:ff21514d8981 2969 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 156:ff21514d8981 2970 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 2971 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 156:ff21514d8981 2972 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 156:ff21514d8981 2973 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 2974 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 156:ff21514d8981 2975 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 156:ff21514d8981 2976 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 2977 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 156:ff21514d8981 2978 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 156:ff21514d8981 2979 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 2980 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 156:ff21514d8981 2981 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 156:ff21514d8981 2982 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 2983 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 156:ff21514d8981 2984 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 156:ff21514d8981 2985 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 2986 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 156:ff21514d8981 2987 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 156:ff21514d8981 2988 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 2989 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 156:ff21514d8981 2990 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 156:ff21514d8981 2991 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 2992 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 156:ff21514d8981 2993 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 156:ff21514d8981 2994 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 2995 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 156:ff21514d8981 2996 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 156:ff21514d8981 2997 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 2998 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 156:ff21514d8981 2999 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 156:ff21514d8981 3000 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3001 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 156:ff21514d8981 3002 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 156:ff21514d8981 3003 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3004 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 156:ff21514d8981 3005 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 156:ff21514d8981 3006 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3007 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 156:ff21514d8981 3008 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 156:ff21514d8981 3009 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3010 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 156:ff21514d8981 3011 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 156:ff21514d8981 3012 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3013 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 156:ff21514d8981 3014
AnnaBridge 156:ff21514d8981 3015 /* Legacy defines */
AnnaBridge 156:ff21514d8981 3016 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
AnnaBridge 156:ff21514d8981 3017 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
AnnaBridge 156:ff21514d8981 3018 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
AnnaBridge 156:ff21514d8981 3019 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
AnnaBridge 156:ff21514d8981 3020 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
AnnaBridge 156:ff21514d8981 3021 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
AnnaBridge 156:ff21514d8981 3022 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
AnnaBridge 156:ff21514d8981 3023 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
AnnaBridge 156:ff21514d8981 3024 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
AnnaBridge 156:ff21514d8981 3025 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
AnnaBridge 156:ff21514d8981 3026 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
AnnaBridge 156:ff21514d8981 3027 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
AnnaBridge 156:ff21514d8981 3028 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
AnnaBridge 156:ff21514d8981 3029 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
AnnaBridge 156:ff21514d8981 3030 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
AnnaBridge 156:ff21514d8981 3031 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
AnnaBridge 156:ff21514d8981 3032
AnnaBridge 156:ff21514d8981 3033 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 156:ff21514d8981 3034 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 156:ff21514d8981 3035 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3036 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 156:ff21514d8981 3037 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 156:ff21514d8981 3038 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3039 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 156:ff21514d8981 3040 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 156:ff21514d8981 3041 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3042 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 156:ff21514d8981 3043 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 156:ff21514d8981 3044 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3045 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 156:ff21514d8981 3046 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 156:ff21514d8981 3047 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3048 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 156:ff21514d8981 3049 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 156:ff21514d8981 3050 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3051 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 156:ff21514d8981 3052 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 156:ff21514d8981 3053 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3054 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 156:ff21514d8981 3055 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 156:ff21514d8981 3056 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3057 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 156:ff21514d8981 3058 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 156:ff21514d8981 3059 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3060 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 156:ff21514d8981 3061 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 156:ff21514d8981 3062 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3063 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 156:ff21514d8981 3064 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 156:ff21514d8981 3065 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3066 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 156:ff21514d8981 3067 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 156:ff21514d8981 3068 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3069 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 156:ff21514d8981 3070 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 156:ff21514d8981 3071 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3072 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 156:ff21514d8981 3073 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 156:ff21514d8981 3074 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3075 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 156:ff21514d8981 3076 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 156:ff21514d8981 3077 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3078 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 156:ff21514d8981 3079 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 156:ff21514d8981 3080 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3081 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 156:ff21514d8981 3082 /* Legacy defines */
AnnaBridge 156:ff21514d8981 3083 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
AnnaBridge 156:ff21514d8981 3084 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
AnnaBridge 156:ff21514d8981 3085 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
AnnaBridge 156:ff21514d8981 3086 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
AnnaBridge 156:ff21514d8981 3087 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
AnnaBridge 156:ff21514d8981 3088 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
AnnaBridge 156:ff21514d8981 3089 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
AnnaBridge 156:ff21514d8981 3090 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
AnnaBridge 156:ff21514d8981 3091 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
AnnaBridge 156:ff21514d8981 3092 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
AnnaBridge 156:ff21514d8981 3093 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
AnnaBridge 156:ff21514d8981 3094 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
AnnaBridge 156:ff21514d8981 3095 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
AnnaBridge 156:ff21514d8981 3096 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
AnnaBridge 156:ff21514d8981 3097 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
AnnaBridge 156:ff21514d8981 3098 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
AnnaBridge 156:ff21514d8981 3099
AnnaBridge 156:ff21514d8981 3100 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 156:ff21514d8981 3101 #define GPIO_BSRR_BS0_Pos (0U)
AnnaBridge 156:ff21514d8981 3102 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3103 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
AnnaBridge 156:ff21514d8981 3104 #define GPIO_BSRR_BS1_Pos (1U)
AnnaBridge 156:ff21514d8981 3105 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3106 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
AnnaBridge 156:ff21514d8981 3107 #define GPIO_BSRR_BS2_Pos (2U)
AnnaBridge 156:ff21514d8981 3108 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3109 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
AnnaBridge 156:ff21514d8981 3110 #define GPIO_BSRR_BS3_Pos (3U)
AnnaBridge 156:ff21514d8981 3111 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3112 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
AnnaBridge 156:ff21514d8981 3113 #define GPIO_BSRR_BS4_Pos (4U)
AnnaBridge 156:ff21514d8981 3114 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3115 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
AnnaBridge 156:ff21514d8981 3116 #define GPIO_BSRR_BS5_Pos (5U)
AnnaBridge 156:ff21514d8981 3117 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3118 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
AnnaBridge 156:ff21514d8981 3119 #define GPIO_BSRR_BS6_Pos (6U)
AnnaBridge 156:ff21514d8981 3120 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3121 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
AnnaBridge 156:ff21514d8981 3122 #define GPIO_BSRR_BS7_Pos (7U)
AnnaBridge 156:ff21514d8981 3123 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3124 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
AnnaBridge 156:ff21514d8981 3125 #define GPIO_BSRR_BS8_Pos (8U)
AnnaBridge 156:ff21514d8981 3126 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3127 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
AnnaBridge 156:ff21514d8981 3128 #define GPIO_BSRR_BS9_Pos (9U)
AnnaBridge 156:ff21514d8981 3129 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3130 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
AnnaBridge 156:ff21514d8981 3131 #define GPIO_BSRR_BS10_Pos (10U)
AnnaBridge 156:ff21514d8981 3132 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3133 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
AnnaBridge 156:ff21514d8981 3134 #define GPIO_BSRR_BS11_Pos (11U)
AnnaBridge 156:ff21514d8981 3135 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3136 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
AnnaBridge 156:ff21514d8981 3137 #define GPIO_BSRR_BS12_Pos (12U)
AnnaBridge 156:ff21514d8981 3138 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3139 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
AnnaBridge 156:ff21514d8981 3140 #define GPIO_BSRR_BS13_Pos (13U)
AnnaBridge 156:ff21514d8981 3141 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3142 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
AnnaBridge 156:ff21514d8981 3143 #define GPIO_BSRR_BS14_Pos (14U)
AnnaBridge 156:ff21514d8981 3144 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3145 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
AnnaBridge 156:ff21514d8981 3146 #define GPIO_BSRR_BS15_Pos (15U)
AnnaBridge 156:ff21514d8981 3147 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3148 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
AnnaBridge 156:ff21514d8981 3149 #define GPIO_BSRR_BR0_Pos (16U)
AnnaBridge 156:ff21514d8981 3150 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 3151 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
AnnaBridge 156:ff21514d8981 3152 #define GPIO_BSRR_BR1_Pos (17U)
AnnaBridge 156:ff21514d8981 3153 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 3154 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
AnnaBridge 156:ff21514d8981 3155 #define GPIO_BSRR_BR2_Pos (18U)
AnnaBridge 156:ff21514d8981 3156 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 3157 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
AnnaBridge 156:ff21514d8981 3158 #define GPIO_BSRR_BR3_Pos (19U)
AnnaBridge 156:ff21514d8981 3159 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 3160 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
AnnaBridge 156:ff21514d8981 3161 #define GPIO_BSRR_BR4_Pos (20U)
AnnaBridge 156:ff21514d8981 3162 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 3163 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
AnnaBridge 156:ff21514d8981 3164 #define GPIO_BSRR_BR5_Pos (21U)
AnnaBridge 156:ff21514d8981 3165 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 3166 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
AnnaBridge 156:ff21514d8981 3167 #define GPIO_BSRR_BR6_Pos (22U)
AnnaBridge 156:ff21514d8981 3168 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 3169 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
AnnaBridge 156:ff21514d8981 3170 #define GPIO_BSRR_BR7_Pos (23U)
AnnaBridge 156:ff21514d8981 3171 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 3172 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
AnnaBridge 156:ff21514d8981 3173 #define GPIO_BSRR_BR8_Pos (24U)
AnnaBridge 156:ff21514d8981 3174 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 3175 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
AnnaBridge 156:ff21514d8981 3176 #define GPIO_BSRR_BR9_Pos (25U)
AnnaBridge 156:ff21514d8981 3177 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 3178 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
AnnaBridge 156:ff21514d8981 3179 #define GPIO_BSRR_BR10_Pos (26U)
AnnaBridge 156:ff21514d8981 3180 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 3181 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
AnnaBridge 156:ff21514d8981 3182 #define GPIO_BSRR_BR11_Pos (27U)
AnnaBridge 156:ff21514d8981 3183 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 3184 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
AnnaBridge 156:ff21514d8981 3185 #define GPIO_BSRR_BR12_Pos (28U)
AnnaBridge 156:ff21514d8981 3186 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 3187 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
AnnaBridge 156:ff21514d8981 3188 #define GPIO_BSRR_BR13_Pos (29U)
AnnaBridge 156:ff21514d8981 3189 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 3190 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
AnnaBridge 156:ff21514d8981 3191 #define GPIO_BSRR_BR14_Pos (30U)
AnnaBridge 156:ff21514d8981 3192 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 3193 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
AnnaBridge 156:ff21514d8981 3194 #define GPIO_BSRR_BR15_Pos (31U)
AnnaBridge 156:ff21514d8981 3195 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 3196 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
AnnaBridge 156:ff21514d8981 3197
AnnaBridge 156:ff21514d8981 3198 /* Legacy defines */
AnnaBridge 156:ff21514d8981 3199 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
AnnaBridge 156:ff21514d8981 3200 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
AnnaBridge 156:ff21514d8981 3201 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
AnnaBridge 156:ff21514d8981 3202 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
AnnaBridge 156:ff21514d8981 3203 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
AnnaBridge 156:ff21514d8981 3204 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
AnnaBridge 156:ff21514d8981 3205 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
AnnaBridge 156:ff21514d8981 3206 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
AnnaBridge 156:ff21514d8981 3207 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
AnnaBridge 156:ff21514d8981 3208 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
AnnaBridge 156:ff21514d8981 3209 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
AnnaBridge 156:ff21514d8981 3210 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
AnnaBridge 156:ff21514d8981 3211 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
AnnaBridge 156:ff21514d8981 3212 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
AnnaBridge 156:ff21514d8981 3213 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
AnnaBridge 156:ff21514d8981 3214 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
AnnaBridge 156:ff21514d8981 3215 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
AnnaBridge 156:ff21514d8981 3216 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
AnnaBridge 156:ff21514d8981 3217 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
AnnaBridge 156:ff21514d8981 3218 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
AnnaBridge 156:ff21514d8981 3219 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
AnnaBridge 156:ff21514d8981 3220 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
AnnaBridge 156:ff21514d8981 3221 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
AnnaBridge 156:ff21514d8981 3222 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
AnnaBridge 156:ff21514d8981 3223 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
AnnaBridge 156:ff21514d8981 3224 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
AnnaBridge 156:ff21514d8981 3225 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
AnnaBridge 156:ff21514d8981 3226 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
AnnaBridge 156:ff21514d8981 3227 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
AnnaBridge 156:ff21514d8981 3228 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
AnnaBridge 156:ff21514d8981 3229 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
AnnaBridge 156:ff21514d8981 3230 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
AnnaBridge 156:ff21514d8981 3231 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 156:ff21514d8981 3232 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 156:ff21514d8981 3233 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3234 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 156:ff21514d8981 3235 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 156:ff21514d8981 3236 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3237 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 156:ff21514d8981 3238 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 156:ff21514d8981 3239 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3240 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 156:ff21514d8981 3241 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 156:ff21514d8981 3242 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3243 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 156:ff21514d8981 3244 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 156:ff21514d8981 3245 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3246 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 156:ff21514d8981 3247 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 156:ff21514d8981 3248 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3249 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 156:ff21514d8981 3250 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 156:ff21514d8981 3251 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3252 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 156:ff21514d8981 3253 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 156:ff21514d8981 3254 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3255 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 156:ff21514d8981 3256 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 156:ff21514d8981 3257 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3258 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 156:ff21514d8981 3259 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 156:ff21514d8981 3260 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3261 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 156:ff21514d8981 3262 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 156:ff21514d8981 3263 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3264 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 156:ff21514d8981 3265 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 156:ff21514d8981 3266 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3267 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 156:ff21514d8981 3268 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 156:ff21514d8981 3269 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3270 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 156:ff21514d8981 3271 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 156:ff21514d8981 3272 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3273 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 156:ff21514d8981 3274 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 156:ff21514d8981 3275 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3276 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 156:ff21514d8981 3277 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 156:ff21514d8981 3278 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3279 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 156:ff21514d8981 3280 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 156:ff21514d8981 3281 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 3282 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 156:ff21514d8981 3283 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 156:ff21514d8981 3284 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 156:ff21514d8981 3285 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 3286 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 156:ff21514d8981 3287 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3288 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3289 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3290 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3291 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 156:ff21514d8981 3292 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 3293 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 156:ff21514d8981 3294 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3295 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3296 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3297 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3298 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 156:ff21514d8981 3299 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 3300 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 156:ff21514d8981 3301 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3302 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3303 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3304 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3305 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 156:ff21514d8981 3306 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 156:ff21514d8981 3307 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 156:ff21514d8981 3308 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3309 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3310 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3311 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3312 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 156:ff21514d8981 3313 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 156:ff21514d8981 3314 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 156:ff21514d8981 3315 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 3316 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 3317 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 3318 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 3319 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 156:ff21514d8981 3320 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 156:ff21514d8981 3321 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 156:ff21514d8981 3322 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 3323 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 3324 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 3325 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 3326 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 156:ff21514d8981 3327 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 156:ff21514d8981 3328 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 156:ff21514d8981 3329 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 3330 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 3331 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 3332 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 3333 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 156:ff21514d8981 3334 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 156:ff21514d8981 3335 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 156:ff21514d8981 3336 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 3337 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 3338 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 3339 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 3340
AnnaBridge 156:ff21514d8981 3341 /* Legacy defines */
AnnaBridge 156:ff21514d8981 3342 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 156:ff21514d8981 3343 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
AnnaBridge 156:ff21514d8981 3344 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
AnnaBridge 156:ff21514d8981 3345 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
AnnaBridge 156:ff21514d8981 3346 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
AnnaBridge 156:ff21514d8981 3347 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 156:ff21514d8981 3348 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
AnnaBridge 156:ff21514d8981 3349 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
AnnaBridge 156:ff21514d8981 3350 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
AnnaBridge 156:ff21514d8981 3351 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
AnnaBridge 156:ff21514d8981 3352 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 156:ff21514d8981 3353 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
AnnaBridge 156:ff21514d8981 3354 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
AnnaBridge 156:ff21514d8981 3355 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
AnnaBridge 156:ff21514d8981 3356 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
AnnaBridge 156:ff21514d8981 3357 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 156:ff21514d8981 3358 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
AnnaBridge 156:ff21514d8981 3359 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
AnnaBridge 156:ff21514d8981 3360 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
AnnaBridge 156:ff21514d8981 3361 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
AnnaBridge 156:ff21514d8981 3362 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 156:ff21514d8981 3363 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
AnnaBridge 156:ff21514d8981 3364 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
AnnaBridge 156:ff21514d8981 3365 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
AnnaBridge 156:ff21514d8981 3366 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
AnnaBridge 156:ff21514d8981 3367 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 156:ff21514d8981 3368 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
AnnaBridge 156:ff21514d8981 3369 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
AnnaBridge 156:ff21514d8981 3370 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
AnnaBridge 156:ff21514d8981 3371 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
AnnaBridge 156:ff21514d8981 3372 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 156:ff21514d8981 3373 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
AnnaBridge 156:ff21514d8981 3374 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
AnnaBridge 156:ff21514d8981 3375 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
AnnaBridge 156:ff21514d8981 3376 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
AnnaBridge 156:ff21514d8981 3377 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 156:ff21514d8981 3378 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
AnnaBridge 156:ff21514d8981 3379 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
AnnaBridge 156:ff21514d8981 3380 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
AnnaBridge 156:ff21514d8981 3381 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
AnnaBridge 156:ff21514d8981 3382
AnnaBridge 156:ff21514d8981 3383 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 156:ff21514d8981 3384 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 156:ff21514d8981 3385 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 3386 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 156:ff21514d8981 3387 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3388 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3389 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3390 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3391 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 156:ff21514d8981 3392 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 3393 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 156:ff21514d8981 3394 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3395 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3396 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3397 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3398 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 156:ff21514d8981 3399 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 3400 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 156:ff21514d8981 3401 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3402 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3403 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3404 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3405 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 156:ff21514d8981 3406 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 156:ff21514d8981 3407 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 156:ff21514d8981 3408 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3409 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3410 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3411 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3412 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 156:ff21514d8981 3413 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 156:ff21514d8981 3414 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 156:ff21514d8981 3415 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 3416 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 3417 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 3418 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 3419 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 156:ff21514d8981 3420 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 156:ff21514d8981 3421 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 156:ff21514d8981 3422 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 3423 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 3424 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 3425 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 3426 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 156:ff21514d8981 3427 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 156:ff21514d8981 3428 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 156:ff21514d8981 3429 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 3430 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 3431 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 3432 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 3433 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 156:ff21514d8981 3434 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 156:ff21514d8981 3435 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 156:ff21514d8981 3436 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 3437 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 3438 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 3439 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 3440
AnnaBridge 156:ff21514d8981 3441 /* Legacy defines */
AnnaBridge 156:ff21514d8981 3442 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 156:ff21514d8981 3443 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
AnnaBridge 156:ff21514d8981 3444 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
AnnaBridge 156:ff21514d8981 3445 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
AnnaBridge 156:ff21514d8981 3446 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
AnnaBridge 156:ff21514d8981 3447 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 156:ff21514d8981 3448 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
AnnaBridge 156:ff21514d8981 3449 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
AnnaBridge 156:ff21514d8981 3450 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
AnnaBridge 156:ff21514d8981 3451 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
AnnaBridge 156:ff21514d8981 3452 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 156:ff21514d8981 3453 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
AnnaBridge 156:ff21514d8981 3454 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
AnnaBridge 156:ff21514d8981 3455 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
AnnaBridge 156:ff21514d8981 3456 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
AnnaBridge 156:ff21514d8981 3457 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 156:ff21514d8981 3458 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
AnnaBridge 156:ff21514d8981 3459 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
AnnaBridge 156:ff21514d8981 3460 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
AnnaBridge 156:ff21514d8981 3461 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
AnnaBridge 156:ff21514d8981 3462 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 156:ff21514d8981 3463 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
AnnaBridge 156:ff21514d8981 3464 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
AnnaBridge 156:ff21514d8981 3465 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
AnnaBridge 156:ff21514d8981 3466 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
AnnaBridge 156:ff21514d8981 3467 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 156:ff21514d8981 3468 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
AnnaBridge 156:ff21514d8981 3469 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
AnnaBridge 156:ff21514d8981 3470 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
AnnaBridge 156:ff21514d8981 3471 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
AnnaBridge 156:ff21514d8981 3472 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 156:ff21514d8981 3473 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
AnnaBridge 156:ff21514d8981 3474 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
AnnaBridge 156:ff21514d8981 3475 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
AnnaBridge 156:ff21514d8981 3476 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
AnnaBridge 156:ff21514d8981 3477 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 156:ff21514d8981 3478 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
AnnaBridge 156:ff21514d8981 3479 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
AnnaBridge 156:ff21514d8981 3480 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
AnnaBridge 156:ff21514d8981 3481 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
AnnaBridge 156:ff21514d8981 3482
AnnaBridge 156:ff21514d8981 3483 /****************** Bits definition for GPIO_BRR register ******************/
AnnaBridge 156:ff21514d8981 3484 #define GPIO_BRR_BR0_Pos (0U)
AnnaBridge 156:ff21514d8981 3485 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3486 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
AnnaBridge 156:ff21514d8981 3487 #define GPIO_BRR_BR1_Pos (1U)
AnnaBridge 156:ff21514d8981 3488 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3489 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
AnnaBridge 156:ff21514d8981 3490 #define GPIO_BRR_BR2_Pos (2U)
AnnaBridge 156:ff21514d8981 3491 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3492 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
AnnaBridge 156:ff21514d8981 3493 #define GPIO_BRR_BR3_Pos (3U)
AnnaBridge 156:ff21514d8981 3494 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3495 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
AnnaBridge 156:ff21514d8981 3496 #define GPIO_BRR_BR4_Pos (4U)
AnnaBridge 156:ff21514d8981 3497 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3498 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
AnnaBridge 156:ff21514d8981 3499 #define GPIO_BRR_BR5_Pos (5U)
AnnaBridge 156:ff21514d8981 3500 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3501 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
AnnaBridge 156:ff21514d8981 3502 #define GPIO_BRR_BR6_Pos (6U)
AnnaBridge 156:ff21514d8981 3503 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3504 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
AnnaBridge 156:ff21514d8981 3505 #define GPIO_BRR_BR7_Pos (7U)
AnnaBridge 156:ff21514d8981 3506 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3507 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
AnnaBridge 156:ff21514d8981 3508 #define GPIO_BRR_BR8_Pos (8U)
AnnaBridge 156:ff21514d8981 3509 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3510 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
AnnaBridge 156:ff21514d8981 3511 #define GPIO_BRR_BR9_Pos (9U)
AnnaBridge 156:ff21514d8981 3512 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3513 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
AnnaBridge 156:ff21514d8981 3514 #define GPIO_BRR_BR10_Pos (10U)
AnnaBridge 156:ff21514d8981 3515 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3516 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
AnnaBridge 156:ff21514d8981 3517 #define GPIO_BRR_BR11_Pos (11U)
AnnaBridge 156:ff21514d8981 3518 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3519 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
AnnaBridge 156:ff21514d8981 3520 #define GPIO_BRR_BR12_Pos (12U)
AnnaBridge 156:ff21514d8981 3521 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3522 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
AnnaBridge 156:ff21514d8981 3523 #define GPIO_BRR_BR13_Pos (13U)
AnnaBridge 156:ff21514d8981 3524 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3525 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
AnnaBridge 156:ff21514d8981 3526 #define GPIO_BRR_BR14_Pos (14U)
AnnaBridge 156:ff21514d8981 3527 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3528 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
AnnaBridge 156:ff21514d8981 3529 #define GPIO_BRR_BR15_Pos (15U)
AnnaBridge 156:ff21514d8981 3530 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3531 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
AnnaBridge 156:ff21514d8981 3532
AnnaBridge 156:ff21514d8981 3533
AnnaBridge 156:ff21514d8981 3534 /******************************************************************************/
AnnaBridge 156:ff21514d8981 3535 /* */
AnnaBridge 156:ff21514d8981 3536 /* Inter-integrated Circuit Interface */
AnnaBridge 156:ff21514d8981 3537 /* */
AnnaBridge 156:ff21514d8981 3538 /******************************************************************************/
AnnaBridge 156:ff21514d8981 3539 /******************* Bit definition for I2C_CR1 register ********************/
AnnaBridge 156:ff21514d8981 3540 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 156:ff21514d8981 3541 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3542 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
AnnaBridge 156:ff21514d8981 3543 #define I2C_CR1_SMBUS_Pos (1U)
AnnaBridge 156:ff21514d8981 3544 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3545 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
AnnaBridge 156:ff21514d8981 3546 #define I2C_CR1_SMBTYPE_Pos (3U)
AnnaBridge 156:ff21514d8981 3547 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3548 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
AnnaBridge 156:ff21514d8981 3549 #define I2C_CR1_ENARP_Pos (4U)
AnnaBridge 156:ff21514d8981 3550 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3551 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
AnnaBridge 156:ff21514d8981 3552 #define I2C_CR1_ENPEC_Pos (5U)
AnnaBridge 156:ff21514d8981 3553 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3554 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
AnnaBridge 156:ff21514d8981 3555 #define I2C_CR1_ENGC_Pos (6U)
AnnaBridge 156:ff21514d8981 3556 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3557 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
AnnaBridge 156:ff21514d8981 3558 #define I2C_CR1_NOSTRETCH_Pos (7U)
AnnaBridge 156:ff21514d8981 3559 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3560 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
AnnaBridge 156:ff21514d8981 3561 #define I2C_CR1_START_Pos (8U)
AnnaBridge 156:ff21514d8981 3562 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3563 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
AnnaBridge 156:ff21514d8981 3564 #define I2C_CR1_STOP_Pos (9U)
AnnaBridge 156:ff21514d8981 3565 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3566 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
AnnaBridge 156:ff21514d8981 3567 #define I2C_CR1_ACK_Pos (10U)
AnnaBridge 156:ff21514d8981 3568 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3569 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
AnnaBridge 156:ff21514d8981 3570 #define I2C_CR1_POS_Pos (11U)
AnnaBridge 156:ff21514d8981 3571 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3572 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
AnnaBridge 156:ff21514d8981 3573 #define I2C_CR1_PEC_Pos (12U)
AnnaBridge 156:ff21514d8981 3574 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3575 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
AnnaBridge 156:ff21514d8981 3576 #define I2C_CR1_ALERT_Pos (13U)
AnnaBridge 156:ff21514d8981 3577 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3578 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
AnnaBridge 156:ff21514d8981 3579 #define I2C_CR1_SWRST_Pos (15U)
AnnaBridge 156:ff21514d8981 3580 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3581 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
AnnaBridge 156:ff21514d8981 3582
AnnaBridge 156:ff21514d8981 3583 /******************* Bit definition for I2C_CR2 register ********************/
AnnaBridge 156:ff21514d8981 3584 #define I2C_CR2_FREQ_Pos (0U)
AnnaBridge 156:ff21514d8981 3585 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
AnnaBridge 156:ff21514d8981 3586 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
AnnaBridge 156:ff21514d8981 3587 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3588 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3589 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3590 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3591 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3592 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3593
AnnaBridge 156:ff21514d8981 3594 #define I2C_CR2_ITERREN_Pos (8U)
AnnaBridge 156:ff21514d8981 3595 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3596 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
AnnaBridge 156:ff21514d8981 3597 #define I2C_CR2_ITEVTEN_Pos (9U)
AnnaBridge 156:ff21514d8981 3598 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3599 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
AnnaBridge 156:ff21514d8981 3600 #define I2C_CR2_ITBUFEN_Pos (10U)
AnnaBridge 156:ff21514d8981 3601 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3602 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
AnnaBridge 156:ff21514d8981 3603 #define I2C_CR2_DMAEN_Pos (11U)
AnnaBridge 156:ff21514d8981 3604 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3605 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
AnnaBridge 156:ff21514d8981 3606 #define I2C_CR2_LAST_Pos (12U)
AnnaBridge 156:ff21514d8981 3607 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3608 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
AnnaBridge 156:ff21514d8981 3609
AnnaBridge 156:ff21514d8981 3610 /******************* Bit definition for I2C_OAR1 register *******************/
AnnaBridge 156:ff21514d8981 3611 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
AnnaBridge 156:ff21514d8981 3612 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
AnnaBridge 156:ff21514d8981 3613
AnnaBridge 156:ff21514d8981 3614 #define I2C_OAR1_ADD0_Pos (0U)
AnnaBridge 156:ff21514d8981 3615 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3616 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
AnnaBridge 156:ff21514d8981 3617 #define I2C_OAR1_ADD1_Pos (1U)
AnnaBridge 156:ff21514d8981 3618 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3619 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
AnnaBridge 156:ff21514d8981 3620 #define I2C_OAR1_ADD2_Pos (2U)
AnnaBridge 156:ff21514d8981 3621 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3622 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
AnnaBridge 156:ff21514d8981 3623 #define I2C_OAR1_ADD3_Pos (3U)
AnnaBridge 156:ff21514d8981 3624 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3625 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
AnnaBridge 156:ff21514d8981 3626 #define I2C_OAR1_ADD4_Pos (4U)
AnnaBridge 156:ff21514d8981 3627 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3628 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
AnnaBridge 156:ff21514d8981 3629 #define I2C_OAR1_ADD5_Pos (5U)
AnnaBridge 156:ff21514d8981 3630 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3631 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
AnnaBridge 156:ff21514d8981 3632 #define I2C_OAR1_ADD6_Pos (6U)
AnnaBridge 156:ff21514d8981 3633 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3634 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
AnnaBridge 156:ff21514d8981 3635 #define I2C_OAR1_ADD7_Pos (7U)
AnnaBridge 156:ff21514d8981 3636 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3637 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
AnnaBridge 156:ff21514d8981 3638 #define I2C_OAR1_ADD8_Pos (8U)
AnnaBridge 156:ff21514d8981 3639 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3640 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
AnnaBridge 156:ff21514d8981 3641 #define I2C_OAR1_ADD9_Pos (9U)
AnnaBridge 156:ff21514d8981 3642 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3643 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
AnnaBridge 156:ff21514d8981 3644
AnnaBridge 156:ff21514d8981 3645 #define I2C_OAR1_ADDMODE_Pos (15U)
AnnaBridge 156:ff21514d8981 3646 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3647 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
AnnaBridge 156:ff21514d8981 3648
AnnaBridge 156:ff21514d8981 3649 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 156:ff21514d8981 3650 #define I2C_OAR2_ENDUAL_Pos (0U)
AnnaBridge 156:ff21514d8981 3651 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3652 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
AnnaBridge 156:ff21514d8981 3653 #define I2C_OAR2_ADD2_Pos (1U)
AnnaBridge 156:ff21514d8981 3654 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
AnnaBridge 156:ff21514d8981 3655 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
AnnaBridge 156:ff21514d8981 3656
AnnaBridge 156:ff21514d8981 3657 /******************** Bit definition for I2C_DR register ********************/
AnnaBridge 156:ff21514d8981 3658 #define I2C_DR_DR_Pos (0U)
AnnaBridge 156:ff21514d8981 3659 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
AnnaBridge 156:ff21514d8981 3660 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
AnnaBridge 156:ff21514d8981 3661
AnnaBridge 156:ff21514d8981 3662 /******************* Bit definition for I2C_SR1 register ********************/
AnnaBridge 156:ff21514d8981 3663 #define I2C_SR1_SB_Pos (0U)
AnnaBridge 156:ff21514d8981 3664 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3665 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
AnnaBridge 156:ff21514d8981 3666 #define I2C_SR1_ADDR_Pos (1U)
AnnaBridge 156:ff21514d8981 3667 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3668 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
AnnaBridge 156:ff21514d8981 3669 #define I2C_SR1_BTF_Pos (2U)
AnnaBridge 156:ff21514d8981 3670 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3671 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
AnnaBridge 156:ff21514d8981 3672 #define I2C_SR1_ADD10_Pos (3U)
AnnaBridge 156:ff21514d8981 3673 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3674 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
AnnaBridge 156:ff21514d8981 3675 #define I2C_SR1_STOPF_Pos (4U)
AnnaBridge 156:ff21514d8981 3676 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3677 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
AnnaBridge 156:ff21514d8981 3678 #define I2C_SR1_RXNE_Pos (6U)
AnnaBridge 156:ff21514d8981 3679 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3680 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
AnnaBridge 156:ff21514d8981 3681 #define I2C_SR1_TXE_Pos (7U)
AnnaBridge 156:ff21514d8981 3682 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3683 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
AnnaBridge 156:ff21514d8981 3684 #define I2C_SR1_BERR_Pos (8U)
AnnaBridge 156:ff21514d8981 3685 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3686 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
AnnaBridge 156:ff21514d8981 3687 #define I2C_SR1_ARLO_Pos (9U)
AnnaBridge 156:ff21514d8981 3688 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3689 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
AnnaBridge 156:ff21514d8981 3690 #define I2C_SR1_AF_Pos (10U)
AnnaBridge 156:ff21514d8981 3691 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3692 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
AnnaBridge 156:ff21514d8981 3693 #define I2C_SR1_OVR_Pos (11U)
AnnaBridge 156:ff21514d8981 3694 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3695 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
AnnaBridge 156:ff21514d8981 3696 #define I2C_SR1_PECERR_Pos (12U)
AnnaBridge 156:ff21514d8981 3697 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3698 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
AnnaBridge 156:ff21514d8981 3699 #define I2C_SR1_TIMEOUT_Pos (14U)
AnnaBridge 156:ff21514d8981 3700 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3701 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
AnnaBridge 156:ff21514d8981 3702 #define I2C_SR1_SMBALERT_Pos (15U)
AnnaBridge 156:ff21514d8981 3703 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3704 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
AnnaBridge 156:ff21514d8981 3705
AnnaBridge 156:ff21514d8981 3706 /******************* Bit definition for I2C_SR2 register ********************/
AnnaBridge 156:ff21514d8981 3707 #define I2C_SR2_MSL_Pos (0U)
AnnaBridge 156:ff21514d8981 3708 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3709 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
AnnaBridge 156:ff21514d8981 3710 #define I2C_SR2_BUSY_Pos (1U)
AnnaBridge 156:ff21514d8981 3711 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3712 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
AnnaBridge 156:ff21514d8981 3713 #define I2C_SR2_TRA_Pos (2U)
AnnaBridge 156:ff21514d8981 3714 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3715 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
AnnaBridge 156:ff21514d8981 3716 #define I2C_SR2_GENCALL_Pos (4U)
AnnaBridge 156:ff21514d8981 3717 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3718 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
AnnaBridge 156:ff21514d8981 3719 #define I2C_SR2_SMBDEFAULT_Pos (5U)
AnnaBridge 156:ff21514d8981 3720 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3721 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
AnnaBridge 156:ff21514d8981 3722 #define I2C_SR2_SMBHOST_Pos (6U)
AnnaBridge 156:ff21514d8981 3723 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3724 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
AnnaBridge 156:ff21514d8981 3725 #define I2C_SR2_DUALF_Pos (7U)
AnnaBridge 156:ff21514d8981 3726 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3727 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
AnnaBridge 156:ff21514d8981 3728 #define I2C_SR2_PEC_Pos (8U)
AnnaBridge 156:ff21514d8981 3729 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
AnnaBridge 156:ff21514d8981 3730 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
AnnaBridge 156:ff21514d8981 3731
AnnaBridge 156:ff21514d8981 3732 /******************* Bit definition for I2C_CCR register ********************/
AnnaBridge 156:ff21514d8981 3733 #define I2C_CCR_CCR_Pos (0U)
AnnaBridge 156:ff21514d8981 3734 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 3735 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
AnnaBridge 156:ff21514d8981 3736 #define I2C_CCR_DUTY_Pos (14U)
AnnaBridge 156:ff21514d8981 3737 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3738 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
AnnaBridge 156:ff21514d8981 3739 #define I2C_CCR_FS_Pos (15U)
AnnaBridge 156:ff21514d8981 3740 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3741 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
AnnaBridge 156:ff21514d8981 3742
AnnaBridge 156:ff21514d8981 3743 /****************** Bit definition for I2C_TRISE register *******************/
AnnaBridge 156:ff21514d8981 3744 #define I2C_TRISE_TRISE_Pos (0U)
AnnaBridge 156:ff21514d8981 3745 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
AnnaBridge 156:ff21514d8981 3746 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
AnnaBridge 156:ff21514d8981 3747
AnnaBridge 156:ff21514d8981 3748 /****************** Bit definition for I2C_FLTR register *******************/
AnnaBridge 156:ff21514d8981 3749 #define I2C_FLTR_DNF_Pos (0U)
AnnaBridge 156:ff21514d8981 3750 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 3751 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
AnnaBridge 156:ff21514d8981 3752 #define I2C_FLTR_ANOFF_Pos (4U)
AnnaBridge 156:ff21514d8981 3753 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3754 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
AnnaBridge 156:ff21514d8981 3755
AnnaBridge 156:ff21514d8981 3756 /******************************************************************************/
AnnaBridge 156:ff21514d8981 3757 /* */
AnnaBridge 156:ff21514d8981 3758 /* Independent WATCHDOG */
AnnaBridge 156:ff21514d8981 3759 /* */
AnnaBridge 156:ff21514d8981 3760 /******************************************************************************/
AnnaBridge 156:ff21514d8981 3761 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 156:ff21514d8981 3762 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 156:ff21514d8981 3763 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 3764 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
AnnaBridge 156:ff21514d8981 3765
AnnaBridge 156:ff21514d8981 3766 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 156:ff21514d8981 3767 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 156:ff21514d8981 3768 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 156:ff21514d8981 3769 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 156:ff21514d8981 3770 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 156:ff21514d8981 3771 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 156:ff21514d8981 3772 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
AnnaBridge 156:ff21514d8981 3773
AnnaBridge 156:ff21514d8981 3774 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 156:ff21514d8981 3775 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 156:ff21514d8981 3776 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 3777 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
AnnaBridge 156:ff21514d8981 3778
AnnaBridge 156:ff21514d8981 3779 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 156:ff21514d8981 3780 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 156:ff21514d8981 3781 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3782 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
AnnaBridge 156:ff21514d8981 3783 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 156:ff21514d8981 3784 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3785 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
AnnaBridge 156:ff21514d8981 3786
AnnaBridge 156:ff21514d8981 3787
AnnaBridge 156:ff21514d8981 3788
AnnaBridge 156:ff21514d8981 3789 /******************************************************************************/
AnnaBridge 156:ff21514d8981 3790 /* */
AnnaBridge 156:ff21514d8981 3791 /* Power Control */
AnnaBridge 156:ff21514d8981 3792 /* */
AnnaBridge 156:ff21514d8981 3793 /******************************************************************************/
AnnaBridge 156:ff21514d8981 3794 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 156:ff21514d8981 3795 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 156:ff21514d8981 3796 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3797 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
AnnaBridge 156:ff21514d8981 3798 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 156:ff21514d8981 3799 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3800 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 156:ff21514d8981 3801 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 156:ff21514d8981 3802 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3803 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 156:ff21514d8981 3804 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 156:ff21514d8981 3805 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3806 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 156:ff21514d8981 3807 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 156:ff21514d8981 3808 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3809 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 156:ff21514d8981 3810
AnnaBridge 156:ff21514d8981 3811 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 156:ff21514d8981 3812 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 156:ff21514d8981 3813 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 156:ff21514d8981 3814 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3815 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3816 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3817
AnnaBridge 156:ff21514d8981 3818 /*!< PVD level configuration */
AnnaBridge 156:ff21514d8981 3819 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 156:ff21514d8981 3820 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
AnnaBridge 156:ff21514d8981 3821 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
AnnaBridge 156:ff21514d8981 3822 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
AnnaBridge 156:ff21514d8981 3823 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
AnnaBridge 156:ff21514d8981 3824 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
AnnaBridge 156:ff21514d8981 3825 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
AnnaBridge 156:ff21514d8981 3826 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
AnnaBridge 156:ff21514d8981 3827 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 156:ff21514d8981 3828 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3829 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 156:ff21514d8981 3830 #define PWR_CR_FPDS_Pos (9U)
AnnaBridge 156:ff21514d8981 3831 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3832 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
AnnaBridge 156:ff21514d8981 3833 #define PWR_CR_LPLVDS_Pos (10U)
AnnaBridge 156:ff21514d8981 3834 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3835 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
AnnaBridge 156:ff21514d8981 3836 #define PWR_CR_MRLVDS_Pos (11U)
AnnaBridge 156:ff21514d8981 3837 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3838 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
AnnaBridge 156:ff21514d8981 3839 #define PWR_CR_ADCDC1_Pos (13U)
AnnaBridge 156:ff21514d8981 3840 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3841 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 156:ff21514d8981 3842 #define PWR_CR_VOS_Pos (14U)
AnnaBridge 156:ff21514d8981 3843 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
AnnaBridge 156:ff21514d8981 3844 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 156:ff21514d8981 3845 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
AnnaBridge 156:ff21514d8981 3846 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
AnnaBridge 156:ff21514d8981 3847
AnnaBridge 156:ff21514d8981 3848 /* Legacy define */
AnnaBridge 156:ff21514d8981 3849 #define PWR_CR_PMODE PWR_CR_VOS
AnnaBridge 156:ff21514d8981 3850
AnnaBridge 156:ff21514d8981 3851 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 156:ff21514d8981 3852 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 156:ff21514d8981 3853 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3854 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 156:ff21514d8981 3855 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 156:ff21514d8981 3856 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3857 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 156:ff21514d8981 3858 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 156:ff21514d8981 3859 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3860 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 156:ff21514d8981 3861 #define PWR_CSR_BRR_Pos (3U)
AnnaBridge 156:ff21514d8981 3862 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3863 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
AnnaBridge 156:ff21514d8981 3864 #define PWR_CSR_EWUP_Pos (8U)
AnnaBridge 156:ff21514d8981 3865 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3866 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
AnnaBridge 156:ff21514d8981 3867 #define PWR_CSR_BRE_Pos (9U)
AnnaBridge 156:ff21514d8981 3868 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3869 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
AnnaBridge 156:ff21514d8981 3870 #define PWR_CSR_VOSRDY_Pos (14U)
AnnaBridge 156:ff21514d8981 3871 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3872 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
AnnaBridge 156:ff21514d8981 3873
AnnaBridge 156:ff21514d8981 3874 /* Legacy define */
AnnaBridge 156:ff21514d8981 3875 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
AnnaBridge 156:ff21514d8981 3876
AnnaBridge 156:ff21514d8981 3877 /******************************************************************************/
AnnaBridge 156:ff21514d8981 3878 /* */
AnnaBridge 156:ff21514d8981 3879 /* Reset and Clock Control */
AnnaBridge 156:ff21514d8981 3880 /* */
AnnaBridge 156:ff21514d8981 3881 /******************************************************************************/
AnnaBridge 156:ff21514d8981 3882 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 156:ff21514d8981 3883 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 156:ff21514d8981 3884 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3885 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 156:ff21514d8981 3886 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 156:ff21514d8981 3887 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3888 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 156:ff21514d8981 3889
AnnaBridge 156:ff21514d8981 3890 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 156:ff21514d8981 3891 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 156:ff21514d8981 3892 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 156:ff21514d8981 3893 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3894 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3895 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3896 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3897 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3898
AnnaBridge 156:ff21514d8981 3899 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 156:ff21514d8981 3900 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 156:ff21514d8981 3901 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 156:ff21514d8981 3902 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3903 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3904 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3905 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3906 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3907 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3908 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3909 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 3910
AnnaBridge 156:ff21514d8981 3911 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 156:ff21514d8981 3912 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 3913 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 156:ff21514d8981 3914 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 156:ff21514d8981 3915 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 3916 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 156:ff21514d8981 3917 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 156:ff21514d8981 3918 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 3919 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 156:ff21514d8981 3920 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 156:ff21514d8981 3921 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 3922 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 156:ff21514d8981 3923 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 156:ff21514d8981 3924 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 3925 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 156:ff21514d8981 3926 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 156:ff21514d8981 3927 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 3928 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 156:ff21514d8981 3929 /*
AnnaBridge 156:ff21514d8981 3930 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 156:ff21514d8981 3931 */
AnnaBridge 156:ff21514d8981 3932 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
AnnaBridge 156:ff21514d8981 3933
AnnaBridge 156:ff21514d8981 3934 #define RCC_CR_PLLI2SON_Pos (26U)
AnnaBridge 156:ff21514d8981 3935 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 3936 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
AnnaBridge 156:ff21514d8981 3937 #define RCC_CR_PLLI2SRDY_Pos (27U)
AnnaBridge 156:ff21514d8981 3938 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 3939 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
AnnaBridge 156:ff21514d8981 3940
AnnaBridge 156:ff21514d8981 3941 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 156:ff21514d8981 3942 #define RCC_PLLCFGR_PLLM_Pos (0U)
AnnaBridge 156:ff21514d8981 3943 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
AnnaBridge 156:ff21514d8981 3944 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 156:ff21514d8981 3945 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3946 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3947 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 3948 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 3949 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 3950 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 3951
AnnaBridge 156:ff21514d8981 3952 #define RCC_PLLCFGR_PLLN_Pos (6U)
AnnaBridge 156:ff21514d8981 3953 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
AnnaBridge 156:ff21514d8981 3954 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 156:ff21514d8981 3955 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 3956 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 3957 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 3958 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 3959 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 3960 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 3961 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 3962 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 3963 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 3964
AnnaBridge 156:ff21514d8981 3965 #define RCC_PLLCFGR_PLLP_Pos (16U)
AnnaBridge 156:ff21514d8981 3966 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
AnnaBridge 156:ff21514d8981 3967 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 156:ff21514d8981 3968 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 3969 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 3970
AnnaBridge 156:ff21514d8981 3971 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
AnnaBridge 156:ff21514d8981 3972 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 3973 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 156:ff21514d8981 3974 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
AnnaBridge 156:ff21514d8981 3975 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 3976 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
AnnaBridge 156:ff21514d8981 3977 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 156:ff21514d8981 3978
AnnaBridge 156:ff21514d8981 3979 #define RCC_PLLCFGR_PLLQ_Pos (24U)
AnnaBridge 156:ff21514d8981 3980 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
AnnaBridge 156:ff21514d8981 3981 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 156:ff21514d8981 3982 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 3983 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 3984 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 3985 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 3986
AnnaBridge 156:ff21514d8981 3987
AnnaBridge 156:ff21514d8981 3988 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 156:ff21514d8981 3989 /*!< SW configuration */
AnnaBridge 156:ff21514d8981 3990 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 156:ff21514d8981 3991 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 3992 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 156:ff21514d8981 3993 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 3994 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 3995
AnnaBridge 156:ff21514d8981 3996 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 156:ff21514d8981 3997 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 156:ff21514d8981 3998 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
AnnaBridge 156:ff21514d8981 3999
AnnaBridge 156:ff21514d8981 4000 /*!< SWS configuration */
AnnaBridge 156:ff21514d8981 4001 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 156:ff21514d8981 4002 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 156:ff21514d8981 4003 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 156:ff21514d8981 4004 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4005 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4006
AnnaBridge 156:ff21514d8981 4007 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 156:ff21514d8981 4008 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 156:ff21514d8981 4009 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
AnnaBridge 156:ff21514d8981 4010
AnnaBridge 156:ff21514d8981 4011 /*!< HPRE configuration */
AnnaBridge 156:ff21514d8981 4012 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 156:ff21514d8981 4013 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 4014 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 156:ff21514d8981 4015 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4016 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4017 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 4018 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4019
AnnaBridge 156:ff21514d8981 4020 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 156:ff21514d8981 4021 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 156:ff21514d8981 4022 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 156:ff21514d8981 4023 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 156:ff21514d8981 4024 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 156:ff21514d8981 4025 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 156:ff21514d8981 4026 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 156:ff21514d8981 4027 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 156:ff21514d8981 4028 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
AnnaBridge 156:ff21514d8981 4029
AnnaBridge 156:ff21514d8981 4030 /*!< PPRE1 configuration */
AnnaBridge 156:ff21514d8981 4031 #define RCC_CFGR_PPRE1_Pos (10U)
AnnaBridge 156:ff21514d8981 4032 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
AnnaBridge 156:ff21514d8981 4033 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 156:ff21514d8981 4034 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4035 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4036 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4037
AnnaBridge 156:ff21514d8981 4038 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 156:ff21514d8981 4039 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 156:ff21514d8981 4040 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 156:ff21514d8981 4041 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 156:ff21514d8981 4042 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
AnnaBridge 156:ff21514d8981 4043
AnnaBridge 156:ff21514d8981 4044 /*!< PPRE2 configuration */
AnnaBridge 156:ff21514d8981 4045 #define RCC_CFGR_PPRE2_Pos (13U)
AnnaBridge 156:ff21514d8981 4046 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
AnnaBridge 156:ff21514d8981 4047 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 156:ff21514d8981 4048 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4049 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4050 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4051
AnnaBridge 156:ff21514d8981 4052 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 156:ff21514d8981 4053 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 156:ff21514d8981 4054 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 156:ff21514d8981 4055 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 156:ff21514d8981 4056 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
AnnaBridge 156:ff21514d8981 4057
AnnaBridge 156:ff21514d8981 4058 /*!< RTCPRE configuration */
AnnaBridge 156:ff21514d8981 4059 #define RCC_CFGR_RTCPRE_Pos (16U)
AnnaBridge 156:ff21514d8981 4060 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
AnnaBridge 156:ff21514d8981 4061 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
AnnaBridge 156:ff21514d8981 4062 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4063 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4064 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4065 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 4066 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 4067
AnnaBridge 156:ff21514d8981 4068 /*!< MCO1 configuration */
AnnaBridge 156:ff21514d8981 4069 #define RCC_CFGR_MCO1_Pos (21U)
AnnaBridge 156:ff21514d8981 4070 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
AnnaBridge 156:ff21514d8981 4071 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
AnnaBridge 156:ff21514d8981 4072 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4073 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4074
AnnaBridge 156:ff21514d8981 4075 #define RCC_CFGR_I2SSRC_Pos (23U)
AnnaBridge 156:ff21514d8981 4076 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4077 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
AnnaBridge 156:ff21514d8981 4078
AnnaBridge 156:ff21514d8981 4079 #define RCC_CFGR_MCO1PRE_Pos (24U)
AnnaBridge 156:ff21514d8981 4080 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
AnnaBridge 156:ff21514d8981 4081 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
AnnaBridge 156:ff21514d8981 4082 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 4083 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 4084 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 4085
AnnaBridge 156:ff21514d8981 4086 #define RCC_CFGR_MCO2PRE_Pos (27U)
AnnaBridge 156:ff21514d8981 4087 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
AnnaBridge 156:ff21514d8981 4088 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
AnnaBridge 156:ff21514d8981 4089 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 4090 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 4091 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 4092
AnnaBridge 156:ff21514d8981 4093 #define RCC_CFGR_MCO2_Pos (30U)
AnnaBridge 156:ff21514d8981 4094 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
AnnaBridge 156:ff21514d8981 4095 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
AnnaBridge 156:ff21514d8981 4096 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 4097 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 4098
AnnaBridge 156:ff21514d8981 4099 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 156:ff21514d8981 4100 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 156:ff21514d8981 4101 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4102 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
AnnaBridge 156:ff21514d8981 4103 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 156:ff21514d8981 4104 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4105 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
AnnaBridge 156:ff21514d8981 4106 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 156:ff21514d8981 4107 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4108 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
AnnaBridge 156:ff21514d8981 4109 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 156:ff21514d8981 4110 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4111 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
AnnaBridge 156:ff21514d8981 4112 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 156:ff21514d8981 4113 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4114 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
AnnaBridge 156:ff21514d8981 4115 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
AnnaBridge 156:ff21514d8981 4116 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4117 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
AnnaBridge 156:ff21514d8981 4118
AnnaBridge 156:ff21514d8981 4119 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 156:ff21514d8981 4120 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4121 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
AnnaBridge 156:ff21514d8981 4122 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 156:ff21514d8981 4123 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4124 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
AnnaBridge 156:ff21514d8981 4125 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 156:ff21514d8981 4126 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4127 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
AnnaBridge 156:ff21514d8981 4128 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 156:ff21514d8981 4129 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4130 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
AnnaBridge 156:ff21514d8981 4131 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 156:ff21514d8981 4132 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4133 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
AnnaBridge 156:ff21514d8981 4134 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 156:ff21514d8981 4135 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4136 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
AnnaBridge 156:ff21514d8981 4137 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
AnnaBridge 156:ff21514d8981 4138 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4139 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
AnnaBridge 156:ff21514d8981 4140
AnnaBridge 156:ff21514d8981 4141 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 156:ff21514d8981 4142 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4143 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
AnnaBridge 156:ff21514d8981 4144 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 156:ff21514d8981 4145 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4146 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
AnnaBridge 156:ff21514d8981 4147 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 156:ff21514d8981 4148 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4149 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
AnnaBridge 156:ff21514d8981 4150 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 156:ff21514d8981 4151 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 4152 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
AnnaBridge 156:ff21514d8981 4153 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 156:ff21514d8981 4154 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 4155 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
AnnaBridge 156:ff21514d8981 4156 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
AnnaBridge 156:ff21514d8981 4157 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4158 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
AnnaBridge 156:ff21514d8981 4159
AnnaBridge 156:ff21514d8981 4160 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 156:ff21514d8981 4161 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4162 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
AnnaBridge 156:ff21514d8981 4163
AnnaBridge 156:ff21514d8981 4164 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 156:ff21514d8981 4165 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
AnnaBridge 156:ff21514d8981 4166 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4167 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
AnnaBridge 156:ff21514d8981 4168 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
AnnaBridge 156:ff21514d8981 4169 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4170 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
AnnaBridge 156:ff21514d8981 4171 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
AnnaBridge 156:ff21514d8981 4172 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4173 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
AnnaBridge 156:ff21514d8981 4174 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
AnnaBridge 156:ff21514d8981 4175 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4176 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
AnnaBridge 156:ff21514d8981 4177 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
AnnaBridge 156:ff21514d8981 4178 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4179 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
AnnaBridge 156:ff21514d8981 4180 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
AnnaBridge 156:ff21514d8981 4181 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4182 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
AnnaBridge 156:ff21514d8981 4183 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 156:ff21514d8981 4184 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4185 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 156:ff21514d8981 4186 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
AnnaBridge 156:ff21514d8981 4187 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4188 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 156:ff21514d8981 4189 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
AnnaBridge 156:ff21514d8981 4190 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4191 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 156:ff21514d8981 4192
AnnaBridge 156:ff21514d8981 4193 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 156:ff21514d8981 4194 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
AnnaBridge 156:ff21514d8981 4195 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4196 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
AnnaBridge 156:ff21514d8981 4197 /******************** Bit definition for RCC_AHB3RSTR register **************/
AnnaBridge 156:ff21514d8981 4198
AnnaBridge 156:ff21514d8981 4199
AnnaBridge 156:ff21514d8981 4200 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 156:ff21514d8981 4201 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 156:ff21514d8981 4202 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4203 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
AnnaBridge 156:ff21514d8981 4204 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 156:ff21514d8981 4205 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4206 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
AnnaBridge 156:ff21514d8981 4207 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
AnnaBridge 156:ff21514d8981 4208 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4209 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
AnnaBridge 156:ff21514d8981 4210 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 156:ff21514d8981 4211 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4212 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
AnnaBridge 156:ff21514d8981 4213 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 156:ff21514d8981 4214 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4215 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
AnnaBridge 156:ff21514d8981 4216 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 156:ff21514d8981 4217 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4218 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
AnnaBridge 156:ff21514d8981 4219 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
AnnaBridge 156:ff21514d8981 4220 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4221 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
AnnaBridge 156:ff21514d8981 4222 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 156:ff21514d8981 4223 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4224 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
AnnaBridge 156:ff21514d8981 4225 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 156:ff21514d8981 4226 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4227 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
AnnaBridge 156:ff21514d8981 4228 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 156:ff21514d8981 4229 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4230 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
AnnaBridge 156:ff21514d8981 4231 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
AnnaBridge 156:ff21514d8981 4232 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4233 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
AnnaBridge 156:ff21514d8981 4234 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 156:ff21514d8981 4235 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 4236 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
AnnaBridge 156:ff21514d8981 4237
AnnaBridge 156:ff21514d8981 4238 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 156:ff21514d8981 4239 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 156:ff21514d8981 4240 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4241 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 156:ff21514d8981 4242 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 156:ff21514d8981 4243 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4244 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 156:ff21514d8981 4245 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 156:ff21514d8981 4246 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4247 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 156:ff21514d8981 4248 #define RCC_APB2RSTR_ADCRST_Pos (8U)
AnnaBridge 156:ff21514d8981 4249 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4250 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
AnnaBridge 156:ff21514d8981 4251 #define RCC_APB2RSTR_SDIORST_Pos (11U)
AnnaBridge 156:ff21514d8981 4252 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4253 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
AnnaBridge 156:ff21514d8981 4254 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 156:ff21514d8981 4255 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4256 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 156:ff21514d8981 4257 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
AnnaBridge 156:ff21514d8981 4258 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4259 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
AnnaBridge 156:ff21514d8981 4260 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
AnnaBridge 156:ff21514d8981 4261 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4262 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 156:ff21514d8981 4263 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
AnnaBridge 156:ff21514d8981 4264 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4265 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
AnnaBridge 156:ff21514d8981 4266 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
AnnaBridge 156:ff21514d8981 4267 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4268 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
AnnaBridge 156:ff21514d8981 4269 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
AnnaBridge 156:ff21514d8981 4270 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4271 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
AnnaBridge 156:ff21514d8981 4272
AnnaBridge 156:ff21514d8981 4273 /* Old SPI1RST bit definition, maintained for legacy purpose */
AnnaBridge 156:ff21514d8981 4274 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
AnnaBridge 156:ff21514d8981 4275
AnnaBridge 156:ff21514d8981 4276 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 156:ff21514d8981 4277 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
AnnaBridge 156:ff21514d8981 4278 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4279 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
AnnaBridge 156:ff21514d8981 4280 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
AnnaBridge 156:ff21514d8981 4281 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4282 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
AnnaBridge 156:ff21514d8981 4283 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
AnnaBridge 156:ff21514d8981 4284 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4285 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
AnnaBridge 156:ff21514d8981 4286 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
AnnaBridge 156:ff21514d8981 4287 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4288 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
AnnaBridge 156:ff21514d8981 4289 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
AnnaBridge 156:ff21514d8981 4290 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4291 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
AnnaBridge 156:ff21514d8981 4292 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
AnnaBridge 156:ff21514d8981 4293 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4294 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
AnnaBridge 156:ff21514d8981 4295 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 156:ff21514d8981 4296 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4297 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 156:ff21514d8981 4298 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
AnnaBridge 156:ff21514d8981 4299 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4300 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 156:ff21514d8981 4301 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
AnnaBridge 156:ff21514d8981 4302 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4303 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 156:ff21514d8981 4304 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 156:ff21514d8981 4305 /*
AnnaBridge 156:ff21514d8981 4306 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 156:ff21514d8981 4307 */
AnnaBridge 156:ff21514d8981 4308 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
AnnaBridge 156:ff21514d8981 4309
AnnaBridge 156:ff21514d8981 4310 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
AnnaBridge 156:ff21514d8981 4311 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4312 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
AnnaBridge 156:ff21514d8981 4313
AnnaBridge 156:ff21514d8981 4314 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 156:ff21514d8981 4315 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 156:ff21514d8981 4316 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4317 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
AnnaBridge 156:ff21514d8981 4318 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 156:ff21514d8981 4319 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4320 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
AnnaBridge 156:ff21514d8981 4321 #define RCC_APB1ENR_TIM4EN_Pos (2U)
AnnaBridge 156:ff21514d8981 4322 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4323 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
AnnaBridge 156:ff21514d8981 4324 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 156:ff21514d8981 4325 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4326 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
AnnaBridge 156:ff21514d8981 4327 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 156:ff21514d8981 4328 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4329 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
AnnaBridge 156:ff21514d8981 4330 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 156:ff21514d8981 4331 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4332 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
AnnaBridge 156:ff21514d8981 4333 #define RCC_APB1ENR_SPI3EN_Pos (15U)
AnnaBridge 156:ff21514d8981 4334 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4335 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
AnnaBridge 156:ff21514d8981 4336 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 156:ff21514d8981 4337 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4338 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
AnnaBridge 156:ff21514d8981 4339 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 156:ff21514d8981 4340 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4341 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
AnnaBridge 156:ff21514d8981 4342 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 156:ff21514d8981 4343 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4344 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
AnnaBridge 156:ff21514d8981 4345 #define RCC_APB1ENR_I2C3EN_Pos (23U)
AnnaBridge 156:ff21514d8981 4346 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4347 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
AnnaBridge 156:ff21514d8981 4348 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 156:ff21514d8981 4349 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 4350 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
AnnaBridge 156:ff21514d8981 4351
AnnaBridge 156:ff21514d8981 4352 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 156:ff21514d8981 4353 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 156:ff21514d8981 4354 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4355 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 156:ff21514d8981 4356 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 156:ff21514d8981 4357 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4358 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 156:ff21514d8981 4359 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 156:ff21514d8981 4360 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4361 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 156:ff21514d8981 4362 #define RCC_APB2ENR_ADC1EN_Pos (8U)
AnnaBridge 156:ff21514d8981 4363 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4364 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
AnnaBridge 156:ff21514d8981 4365 #define RCC_APB2ENR_SDIOEN_Pos (11U)
AnnaBridge 156:ff21514d8981 4366 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4367 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
AnnaBridge 156:ff21514d8981 4368 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 156:ff21514d8981 4369 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4370 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 156:ff21514d8981 4371 #define RCC_APB2ENR_SPI4EN_Pos (13U)
AnnaBridge 156:ff21514d8981 4372 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4373 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
AnnaBridge 156:ff21514d8981 4374 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
AnnaBridge 156:ff21514d8981 4375 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4376 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 156:ff21514d8981 4377 #define RCC_APB2ENR_TIM9EN_Pos (16U)
AnnaBridge 156:ff21514d8981 4378 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4379 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
AnnaBridge 156:ff21514d8981 4380 #define RCC_APB2ENR_TIM10EN_Pos (17U)
AnnaBridge 156:ff21514d8981 4381 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4382 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
AnnaBridge 156:ff21514d8981 4383 #define RCC_APB2ENR_TIM11EN_Pos (18U)
AnnaBridge 156:ff21514d8981 4384 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4385 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
AnnaBridge 156:ff21514d8981 4386
AnnaBridge 156:ff21514d8981 4387 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 156:ff21514d8981 4388 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 156:ff21514d8981 4389 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4390 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
AnnaBridge 156:ff21514d8981 4391 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 156:ff21514d8981 4392 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4393 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
AnnaBridge 156:ff21514d8981 4394 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 156:ff21514d8981 4395 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4396 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
AnnaBridge 156:ff21514d8981 4397 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
AnnaBridge 156:ff21514d8981 4398 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4399 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
AnnaBridge 156:ff21514d8981 4400 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
AnnaBridge 156:ff21514d8981 4401 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4402 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
AnnaBridge 156:ff21514d8981 4403 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 156:ff21514d8981 4404 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4405 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
AnnaBridge 156:ff21514d8981 4406 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
AnnaBridge 156:ff21514d8981 4407 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4408 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
AnnaBridge 156:ff21514d8981 4409 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
AnnaBridge 156:ff21514d8981 4410 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4411 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
AnnaBridge 156:ff21514d8981 4412 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
AnnaBridge 156:ff21514d8981 4413 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4414 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
AnnaBridge 156:ff21514d8981 4415 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
AnnaBridge 156:ff21514d8981 4416 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4417 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 156:ff21514d8981 4418 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
AnnaBridge 156:ff21514d8981 4419 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4420 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 156:ff21514d8981 4421
AnnaBridge 156:ff21514d8981 4422
AnnaBridge 156:ff21514d8981 4423 /******************** Bit definition for RCC_AHB2LPENR register *************/
AnnaBridge 156:ff21514d8981 4424 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
AnnaBridge 156:ff21514d8981 4425 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4426 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
AnnaBridge 156:ff21514d8981 4427
AnnaBridge 156:ff21514d8981 4428 /******************** Bit definition for RCC_AHB3LPENR register *************/
AnnaBridge 156:ff21514d8981 4429
AnnaBridge 156:ff21514d8981 4430 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 156:ff21514d8981 4431 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
AnnaBridge 156:ff21514d8981 4432 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4433 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
AnnaBridge 156:ff21514d8981 4434 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
AnnaBridge 156:ff21514d8981 4435 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4436 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
AnnaBridge 156:ff21514d8981 4437 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
AnnaBridge 156:ff21514d8981 4438 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4439 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
AnnaBridge 156:ff21514d8981 4440 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 156:ff21514d8981 4441 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4442 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
AnnaBridge 156:ff21514d8981 4443 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 156:ff21514d8981 4444 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4445 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
AnnaBridge 156:ff21514d8981 4446 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 156:ff21514d8981 4447 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4448 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
AnnaBridge 156:ff21514d8981 4449 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
AnnaBridge 156:ff21514d8981 4450 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4451 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
AnnaBridge 156:ff21514d8981 4452 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 156:ff21514d8981 4453 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4454 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
AnnaBridge 156:ff21514d8981 4455 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 156:ff21514d8981 4456 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4457 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
AnnaBridge 156:ff21514d8981 4458 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 156:ff21514d8981 4459 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4460 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
AnnaBridge 156:ff21514d8981 4461 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
AnnaBridge 156:ff21514d8981 4462 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4463 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
AnnaBridge 156:ff21514d8981 4464 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 156:ff21514d8981 4465 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 4466 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
AnnaBridge 156:ff21514d8981 4467
AnnaBridge 156:ff21514d8981 4468 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 156:ff21514d8981 4469 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 156:ff21514d8981 4470 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4471 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 156:ff21514d8981 4472 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 156:ff21514d8981 4473 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4474 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 156:ff21514d8981 4475 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 156:ff21514d8981 4476 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4477 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 156:ff21514d8981 4478 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
AnnaBridge 156:ff21514d8981 4479 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4480 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
AnnaBridge 156:ff21514d8981 4481 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
AnnaBridge 156:ff21514d8981 4482 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4483 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
AnnaBridge 156:ff21514d8981 4484 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 156:ff21514d8981 4485 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4486 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 156:ff21514d8981 4487 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
AnnaBridge 156:ff21514d8981 4488 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4489 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
AnnaBridge 156:ff21514d8981 4490 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
AnnaBridge 156:ff21514d8981 4491 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4492 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
AnnaBridge 156:ff21514d8981 4493 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
AnnaBridge 156:ff21514d8981 4494 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4495 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
AnnaBridge 156:ff21514d8981 4496 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
AnnaBridge 156:ff21514d8981 4497 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4498 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
AnnaBridge 156:ff21514d8981 4499 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
AnnaBridge 156:ff21514d8981 4500 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4501 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
AnnaBridge 156:ff21514d8981 4502
AnnaBridge 156:ff21514d8981 4503 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 156:ff21514d8981 4504 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 156:ff21514d8981 4505 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4506 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 156:ff21514d8981 4507 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 156:ff21514d8981 4508 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4509 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 156:ff21514d8981 4510 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 156:ff21514d8981 4511 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4512 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 156:ff21514d8981 4513
AnnaBridge 156:ff21514d8981 4514 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 156:ff21514d8981 4515 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 4516 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 156:ff21514d8981 4517 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4518 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4519
AnnaBridge 156:ff21514d8981 4520 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 156:ff21514d8981 4521 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4522 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 156:ff21514d8981 4523 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 156:ff21514d8981 4524 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4525 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
AnnaBridge 156:ff21514d8981 4526
AnnaBridge 156:ff21514d8981 4527 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 156:ff21514d8981 4528 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 156:ff21514d8981 4529 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4530 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 156:ff21514d8981 4531 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 156:ff21514d8981 4532 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4533 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 156:ff21514d8981 4534 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 156:ff21514d8981 4535 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 4536 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 156:ff21514d8981 4537 #define RCC_CSR_BORRSTF_Pos (25U)
AnnaBridge 156:ff21514d8981 4538 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 4539 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
AnnaBridge 156:ff21514d8981 4540 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 156:ff21514d8981 4541 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 4542 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 156:ff21514d8981 4543 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 156:ff21514d8981 4544 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 4545 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
AnnaBridge 156:ff21514d8981 4546 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 156:ff21514d8981 4547 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 4548 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 156:ff21514d8981 4549 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 156:ff21514d8981 4550 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 4551 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 156:ff21514d8981 4552 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 156:ff21514d8981 4553 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 4554 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 156:ff21514d8981 4555 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 156:ff21514d8981 4556 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 4557 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 156:ff21514d8981 4558 /* Legacy defines */
AnnaBridge 156:ff21514d8981 4559 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
AnnaBridge 156:ff21514d8981 4560 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
AnnaBridge 156:ff21514d8981 4561
AnnaBridge 156:ff21514d8981 4562 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 156:ff21514d8981 4563 #define RCC_SSCGR_MODPER_Pos (0U)
AnnaBridge 156:ff21514d8981 4564 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
AnnaBridge 156:ff21514d8981 4565 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
AnnaBridge 156:ff21514d8981 4566 #define RCC_SSCGR_INCSTEP_Pos (13U)
AnnaBridge 156:ff21514d8981 4567 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
AnnaBridge 156:ff21514d8981 4568 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
AnnaBridge 156:ff21514d8981 4569 #define RCC_SSCGR_SPREADSEL_Pos (30U)
AnnaBridge 156:ff21514d8981 4570 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 4571 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
AnnaBridge 156:ff21514d8981 4572 #define RCC_SSCGR_SSCGEN_Pos (31U)
AnnaBridge 156:ff21514d8981 4573 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 4574 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
AnnaBridge 156:ff21514d8981 4575
AnnaBridge 156:ff21514d8981 4576 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
AnnaBridge 156:ff21514d8981 4577 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
AnnaBridge 156:ff21514d8981 4578 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
AnnaBridge 156:ff21514d8981 4579 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
AnnaBridge 156:ff21514d8981 4580 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 4581 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4582 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4583 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4584 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4585 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4586 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4587 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4588 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4589
AnnaBridge 156:ff21514d8981 4590 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
AnnaBridge 156:ff21514d8981 4591 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
AnnaBridge 156:ff21514d8981 4592 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
AnnaBridge 156:ff21514d8981 4593 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 4594 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 4595 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 4596
AnnaBridge 156:ff21514d8981 4597 /******************** Bit definition for RCC_DCKCFGR register ***************/
AnnaBridge 156:ff21514d8981 4598
AnnaBridge 156:ff21514d8981 4599 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
AnnaBridge 156:ff21514d8981 4600 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 4601 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
AnnaBridge 156:ff21514d8981 4602
AnnaBridge 156:ff21514d8981 4603
AnnaBridge 156:ff21514d8981 4604 /******************************************************************************/
AnnaBridge 156:ff21514d8981 4605 /* */
AnnaBridge 156:ff21514d8981 4606 /* Real-Time Clock (RTC) */
AnnaBridge 156:ff21514d8981 4607 /* */
AnnaBridge 156:ff21514d8981 4608 /******************************************************************************/
AnnaBridge 156:ff21514d8981 4609 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 156:ff21514d8981 4610 #define RTC_TR_PM_Pos (22U)
AnnaBridge 156:ff21514d8981 4611 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4612 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 156:ff21514d8981 4613 #define RTC_TR_HT_Pos (20U)
AnnaBridge 156:ff21514d8981 4614 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 4615 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 156:ff21514d8981 4616 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 4617 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4618 #define RTC_TR_HU_Pos (16U)
AnnaBridge 156:ff21514d8981 4619 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 156:ff21514d8981 4620 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 156:ff21514d8981 4621 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4622 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4623 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4624 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 4625 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 156:ff21514d8981 4626 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 156:ff21514d8981 4627 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 156:ff21514d8981 4628 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4629 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4630 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4631 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 156:ff21514d8981 4632 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 4633 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 156:ff21514d8981 4634 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4635 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4636 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4637 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4638 #define RTC_TR_ST_Pos (4U)
AnnaBridge 156:ff21514d8981 4639 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 4640 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 156:ff21514d8981 4641 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4642 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4643 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 4644 #define RTC_TR_SU_Pos (0U)
AnnaBridge 156:ff21514d8981 4645 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 4646 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 156:ff21514d8981 4647 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4648 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4649 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4650 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4651
AnnaBridge 156:ff21514d8981 4652 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 156:ff21514d8981 4653 #define RTC_DR_YT_Pos (20U)
AnnaBridge 156:ff21514d8981 4654 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 156:ff21514d8981 4655 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 156:ff21514d8981 4656 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 4657 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4658 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4659 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4660 #define RTC_DR_YU_Pos (16U)
AnnaBridge 156:ff21514d8981 4661 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 156:ff21514d8981 4662 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 156:ff21514d8981 4663 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4664 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4665 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4666 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 4667 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 156:ff21514d8981 4668 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 156:ff21514d8981 4669 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 156:ff21514d8981 4670 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4671 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4672 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4673 #define RTC_DR_MT_Pos (12U)
AnnaBridge 156:ff21514d8981 4674 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4675 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 156:ff21514d8981 4676 #define RTC_DR_MU_Pos (8U)
AnnaBridge 156:ff21514d8981 4677 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 4678 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 156:ff21514d8981 4679 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4680 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4681 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4682 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4683 #define RTC_DR_DT_Pos (4U)
AnnaBridge 156:ff21514d8981 4684 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 156:ff21514d8981 4685 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 156:ff21514d8981 4686 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4687 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4688 #define RTC_DR_DU_Pos (0U)
AnnaBridge 156:ff21514d8981 4689 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 4690 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 156:ff21514d8981 4691 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4692 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4693 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4694 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4695
AnnaBridge 156:ff21514d8981 4696 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 156:ff21514d8981 4697 #define RTC_CR_COE_Pos (23U)
AnnaBridge 156:ff21514d8981 4698 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4699 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 156:ff21514d8981 4700 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 156:ff21514d8981 4701 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 156:ff21514d8981 4702 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 156:ff21514d8981 4703 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4704 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4705 #define RTC_CR_POL_Pos (20U)
AnnaBridge 156:ff21514d8981 4706 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 4707 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 156:ff21514d8981 4708 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 156:ff21514d8981 4709 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 4710 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 156:ff21514d8981 4711 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 156:ff21514d8981 4712 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4713 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 156:ff21514d8981 4714 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 156:ff21514d8981 4715 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4716 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 156:ff21514d8981 4717 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 156:ff21514d8981 4718 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4719 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 156:ff21514d8981 4720 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 156:ff21514d8981 4721 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4722 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 156:ff21514d8981 4723 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 156:ff21514d8981 4724 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4725 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 156:ff21514d8981 4726 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 156:ff21514d8981 4727 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4728 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 156:ff21514d8981 4729 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 156:ff21514d8981 4730 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4731 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 156:ff21514d8981 4732 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 156:ff21514d8981 4733 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4734 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 156:ff21514d8981 4735 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 156:ff21514d8981 4736 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4737 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 156:ff21514d8981 4738 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 156:ff21514d8981 4739 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4740 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 156:ff21514d8981 4741 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 156:ff21514d8981 4742 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4743 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 156:ff21514d8981 4744 #define RTC_CR_DCE_Pos (7U)
AnnaBridge 156:ff21514d8981 4745 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4746 #define RTC_CR_DCE RTC_CR_DCE_Msk
AnnaBridge 156:ff21514d8981 4747 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 156:ff21514d8981 4748 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 4749 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 156:ff21514d8981 4750 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 156:ff21514d8981 4751 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4752 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 156:ff21514d8981 4753 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 156:ff21514d8981 4754 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4755 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 156:ff21514d8981 4756 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 156:ff21514d8981 4757 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4758 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 156:ff21514d8981 4759 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 156:ff21514d8981 4760 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 156:ff21514d8981 4761 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 156:ff21514d8981 4762 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4763 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4764 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4765
AnnaBridge 156:ff21514d8981 4766 /* Legacy defines */
AnnaBridge 156:ff21514d8981 4767 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 156:ff21514d8981 4768
AnnaBridge 156:ff21514d8981 4769 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 156:ff21514d8981 4770 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 156:ff21514d8981 4771 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4772 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 156:ff21514d8981 4773 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 156:ff21514d8981 4774 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4775 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 156:ff21514d8981 4776 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 156:ff21514d8981 4777 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4778 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 156:ff21514d8981 4779 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 156:ff21514d8981 4780 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4781 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 156:ff21514d8981 4782 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 156:ff21514d8981 4783 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4784 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 156:ff21514d8981 4785 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 156:ff21514d8981 4786 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4787 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 156:ff21514d8981 4788 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 156:ff21514d8981 4789 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4790 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 156:ff21514d8981 4791 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 156:ff21514d8981 4792 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4793 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 156:ff21514d8981 4794 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 156:ff21514d8981 4795 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4796 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 156:ff21514d8981 4797 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 156:ff21514d8981 4798 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 4799 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 156:ff21514d8981 4800 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 156:ff21514d8981 4801 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4802 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 156:ff21514d8981 4803 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 156:ff21514d8981 4804 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4805 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 156:ff21514d8981 4806 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 156:ff21514d8981 4807 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4808 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 156:ff21514d8981 4809 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 156:ff21514d8981 4810 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4811 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 156:ff21514d8981 4812 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 156:ff21514d8981 4813 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4814 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 156:ff21514d8981 4815 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 156:ff21514d8981 4816 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4817 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 156:ff21514d8981 4818
AnnaBridge 156:ff21514d8981 4819 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 156:ff21514d8981 4820 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 156:ff21514d8981 4821 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 156:ff21514d8981 4822 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 156:ff21514d8981 4823 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 156:ff21514d8981 4824 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 156:ff21514d8981 4825 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 156:ff21514d8981 4826
AnnaBridge 156:ff21514d8981 4827 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 156:ff21514d8981 4828 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 156:ff21514d8981 4829 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 4830 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 156:ff21514d8981 4831
AnnaBridge 156:ff21514d8981 4832 /******************** Bits definition for RTC_CALIBR register ***************/
AnnaBridge 156:ff21514d8981 4833 #define RTC_CALIBR_DCS_Pos (7U)
AnnaBridge 156:ff21514d8981 4834 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4835 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
AnnaBridge 156:ff21514d8981 4836 #define RTC_CALIBR_DC_Pos (0U)
AnnaBridge 156:ff21514d8981 4837 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
AnnaBridge 156:ff21514d8981 4838 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
AnnaBridge 156:ff21514d8981 4839
AnnaBridge 156:ff21514d8981 4840 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 156:ff21514d8981 4841 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 156:ff21514d8981 4842 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 4843 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 156:ff21514d8981 4844 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 156:ff21514d8981 4845 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 4846 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 156:ff21514d8981 4847 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 156:ff21514d8981 4848 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 156:ff21514d8981 4849 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 156:ff21514d8981 4850 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 4851 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 4852 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 156:ff21514d8981 4853 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 156:ff21514d8981 4854 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 156:ff21514d8981 4855 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 4856 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 4857 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 4858 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 4859 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 156:ff21514d8981 4860 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4861 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 156:ff21514d8981 4862 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 156:ff21514d8981 4863 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4864 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 156:ff21514d8981 4865 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 156:ff21514d8981 4866 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 4867 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 156:ff21514d8981 4868 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 4869 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4870 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 156:ff21514d8981 4871 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 156:ff21514d8981 4872 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 156:ff21514d8981 4873 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4874 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4875 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4876 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 4877 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 156:ff21514d8981 4878 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4879 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 156:ff21514d8981 4880 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 156:ff21514d8981 4881 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 156:ff21514d8981 4882 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 156:ff21514d8981 4883 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4884 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4885 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4886 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 156:ff21514d8981 4887 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 4888 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 156:ff21514d8981 4889 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4890 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4891 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4892 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4893 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 156:ff21514d8981 4894 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4895 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 156:ff21514d8981 4896 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 156:ff21514d8981 4897 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 4898 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 156:ff21514d8981 4899 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4900 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4901 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 4902 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 156:ff21514d8981 4903 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 4904 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 156:ff21514d8981 4905 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4906 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4907 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4908 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4909
AnnaBridge 156:ff21514d8981 4910 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 156:ff21514d8981 4911 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 156:ff21514d8981 4912 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 4913 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 156:ff21514d8981 4914 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 156:ff21514d8981 4915 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 4916 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 156:ff21514d8981 4917 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 156:ff21514d8981 4918 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 156:ff21514d8981 4919 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 156:ff21514d8981 4920 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 4921 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 4922 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 156:ff21514d8981 4923 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 156:ff21514d8981 4924 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 156:ff21514d8981 4925 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 4926 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 4927 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 4928 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 4929 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 156:ff21514d8981 4930 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 4931 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 156:ff21514d8981 4932 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 156:ff21514d8981 4933 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 4934 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 156:ff21514d8981 4935 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 156:ff21514d8981 4936 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 4937 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 156:ff21514d8981 4938 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 4939 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 4940 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 156:ff21514d8981 4941 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 156:ff21514d8981 4942 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 156:ff21514d8981 4943 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 4944 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 4945 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 4946 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 4947 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 156:ff21514d8981 4948 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 4949 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 156:ff21514d8981 4950 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 156:ff21514d8981 4951 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 156:ff21514d8981 4952 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 156:ff21514d8981 4953 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 4954 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 4955 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 4956 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 156:ff21514d8981 4957 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 4958 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 156:ff21514d8981 4959 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 4960 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 4961 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 4962 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 4963 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 156:ff21514d8981 4964 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 4965 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 156:ff21514d8981 4966 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 156:ff21514d8981 4967 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 4968 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 156:ff21514d8981 4969 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 4970 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 4971 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 4972 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 156:ff21514d8981 4973 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 4974 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 156:ff21514d8981 4975 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 4976 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 4977 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 4978 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 4979
AnnaBridge 156:ff21514d8981 4980 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 156:ff21514d8981 4981 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 156:ff21514d8981 4982 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 156:ff21514d8981 4983 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 156:ff21514d8981 4984
AnnaBridge 156:ff21514d8981 4985 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 156:ff21514d8981 4986 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 156:ff21514d8981 4987 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 4988 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 156:ff21514d8981 4989
AnnaBridge 156:ff21514d8981 4990 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 156:ff21514d8981 4991 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 156:ff21514d8981 4992 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 156:ff21514d8981 4993 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 156:ff21514d8981 4994 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 156:ff21514d8981 4995 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 4996 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 156:ff21514d8981 4997
AnnaBridge 156:ff21514d8981 4998 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 156:ff21514d8981 4999 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 156:ff21514d8981 5000 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 5001 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 156:ff21514d8981 5002 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 156:ff21514d8981 5003 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 5004 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 156:ff21514d8981 5005 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 5006 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 5007 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 156:ff21514d8981 5008 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 156:ff21514d8981 5009 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 156:ff21514d8981 5010 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 5011 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 5012 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 5013 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 5014 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 156:ff21514d8981 5015 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 156:ff21514d8981 5016 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 156:ff21514d8981 5017 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 5018 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5019 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5020 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 156:ff21514d8981 5021 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 5022 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 156:ff21514d8981 5023 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5024 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5025 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5026 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5027 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 156:ff21514d8981 5028 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 5029 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 156:ff21514d8981 5030 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5031 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5032 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 5033 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 156:ff21514d8981 5034 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 5035 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 156:ff21514d8981 5036 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5037 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5038 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5039 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5040
AnnaBridge 156:ff21514d8981 5041 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 156:ff21514d8981 5042 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 156:ff21514d8981 5043 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 156:ff21514d8981 5044 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 156:ff21514d8981 5045 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5046 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5047 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 5048 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 156:ff21514d8981 5049 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 5050 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 156:ff21514d8981 5051 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 156:ff21514d8981 5052 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 5053 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 156:ff21514d8981 5054 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5055 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5056 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5057 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5058 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 156:ff21514d8981 5059 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 156:ff21514d8981 5060 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 156:ff21514d8981 5061 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5062 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5063 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 156:ff21514d8981 5064 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 5065 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 156:ff21514d8981 5066 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5067 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5068 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5069 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5070
AnnaBridge 156:ff21514d8981 5071 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 156:ff21514d8981 5072 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 156:ff21514d8981 5073 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 5074 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 156:ff21514d8981 5075
AnnaBridge 156:ff21514d8981 5076 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 156:ff21514d8981 5077 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 156:ff21514d8981 5078 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 5079 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 156:ff21514d8981 5080 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 156:ff21514d8981 5081 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5082 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 156:ff21514d8981 5083 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 156:ff21514d8981 5084 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5085 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 156:ff21514d8981 5086 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 156:ff21514d8981 5087 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 156:ff21514d8981 5088 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 156:ff21514d8981 5089 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5090 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5091 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5092 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5093 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5094 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5095 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 5096 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5097 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5098
AnnaBridge 156:ff21514d8981 5099 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 156:ff21514d8981 5100 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
AnnaBridge 156:ff21514d8981 5101 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 5102 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
AnnaBridge 156:ff21514d8981 5103 #define RTC_TAFCR_TSINSEL_Pos (17U)
AnnaBridge 156:ff21514d8981 5104 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 5105 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
AnnaBridge 156:ff21514d8981 5106 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
AnnaBridge 156:ff21514d8981 5107 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 5108 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
AnnaBridge 156:ff21514d8981 5109 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 156:ff21514d8981 5110 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 5111 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 156:ff21514d8981 5112 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 156:ff21514d8981 5113 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 156:ff21514d8981 5114 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 156:ff21514d8981 5115 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5116 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5117 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 156:ff21514d8981 5118 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 156:ff21514d8981 5119 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 156:ff21514d8981 5120 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5121 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 5122 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 156:ff21514d8981 5123 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 156:ff21514d8981 5124 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 156:ff21514d8981 5125 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5126 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5127 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5128 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 156:ff21514d8981 5129 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5130 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 156:ff21514d8981 5131 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 156:ff21514d8981 5132 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5133 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 156:ff21514d8981 5134 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 156:ff21514d8981 5135 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5136 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 156:ff21514d8981 5137 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 156:ff21514d8981 5138 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5139 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 156:ff21514d8981 5140 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 156:ff21514d8981 5141 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5142 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 156:ff21514d8981 5143 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 156:ff21514d8981 5144 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5145 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 156:ff21514d8981 5146
AnnaBridge 156:ff21514d8981 5147 /* Legacy defines */
AnnaBridge 156:ff21514d8981 5148 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
AnnaBridge 156:ff21514d8981 5149
AnnaBridge 156:ff21514d8981 5150 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 156:ff21514d8981 5151 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 156:ff21514d8981 5152 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 156:ff21514d8981 5153 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 156:ff21514d8981 5154 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 5155 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 5156 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 5157 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 5158 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 156:ff21514d8981 5159 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 156:ff21514d8981 5160 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 156:ff21514d8981 5161
AnnaBridge 156:ff21514d8981 5162 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 156:ff21514d8981 5163 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 156:ff21514d8981 5164 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 156:ff21514d8981 5165 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 156:ff21514d8981 5166 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 5167 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 5168 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 5169 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 5170 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 156:ff21514d8981 5171 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 156:ff21514d8981 5172 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 156:ff21514d8981 5173
AnnaBridge 156:ff21514d8981 5174 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 156:ff21514d8981 5175 #define RTC_BKP0R_Pos (0U)
AnnaBridge 156:ff21514d8981 5176 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5177 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 156:ff21514d8981 5178
AnnaBridge 156:ff21514d8981 5179 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 156:ff21514d8981 5180 #define RTC_BKP1R_Pos (0U)
AnnaBridge 156:ff21514d8981 5181 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5182 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 156:ff21514d8981 5183
AnnaBridge 156:ff21514d8981 5184 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 156:ff21514d8981 5185 #define RTC_BKP2R_Pos (0U)
AnnaBridge 156:ff21514d8981 5186 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5187 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 156:ff21514d8981 5188
AnnaBridge 156:ff21514d8981 5189 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 156:ff21514d8981 5190 #define RTC_BKP3R_Pos (0U)
AnnaBridge 156:ff21514d8981 5191 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5192 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 156:ff21514d8981 5193
AnnaBridge 156:ff21514d8981 5194 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 156:ff21514d8981 5195 #define RTC_BKP4R_Pos (0U)
AnnaBridge 156:ff21514d8981 5196 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5197 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 156:ff21514d8981 5198
AnnaBridge 156:ff21514d8981 5199 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 156:ff21514d8981 5200 #define RTC_BKP5R_Pos (0U)
AnnaBridge 156:ff21514d8981 5201 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5202 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 156:ff21514d8981 5203
AnnaBridge 156:ff21514d8981 5204 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 156:ff21514d8981 5205 #define RTC_BKP6R_Pos (0U)
AnnaBridge 156:ff21514d8981 5206 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5207 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 156:ff21514d8981 5208
AnnaBridge 156:ff21514d8981 5209 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 156:ff21514d8981 5210 #define RTC_BKP7R_Pos (0U)
AnnaBridge 156:ff21514d8981 5211 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5212 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 156:ff21514d8981 5213
AnnaBridge 156:ff21514d8981 5214 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 156:ff21514d8981 5215 #define RTC_BKP8R_Pos (0U)
AnnaBridge 156:ff21514d8981 5216 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5217 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 156:ff21514d8981 5218
AnnaBridge 156:ff21514d8981 5219 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 156:ff21514d8981 5220 #define RTC_BKP9R_Pos (0U)
AnnaBridge 156:ff21514d8981 5221 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5222 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 156:ff21514d8981 5223
AnnaBridge 156:ff21514d8981 5224 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 156:ff21514d8981 5225 #define RTC_BKP10R_Pos (0U)
AnnaBridge 156:ff21514d8981 5226 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5227 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 156:ff21514d8981 5228
AnnaBridge 156:ff21514d8981 5229 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 156:ff21514d8981 5230 #define RTC_BKP11R_Pos (0U)
AnnaBridge 156:ff21514d8981 5231 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5232 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 156:ff21514d8981 5233
AnnaBridge 156:ff21514d8981 5234 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 156:ff21514d8981 5235 #define RTC_BKP12R_Pos (0U)
AnnaBridge 156:ff21514d8981 5236 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5237 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 156:ff21514d8981 5238
AnnaBridge 156:ff21514d8981 5239 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 156:ff21514d8981 5240 #define RTC_BKP13R_Pos (0U)
AnnaBridge 156:ff21514d8981 5241 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5242 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 156:ff21514d8981 5243
AnnaBridge 156:ff21514d8981 5244 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 156:ff21514d8981 5245 #define RTC_BKP14R_Pos (0U)
AnnaBridge 156:ff21514d8981 5246 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5247 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 156:ff21514d8981 5248
AnnaBridge 156:ff21514d8981 5249 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 156:ff21514d8981 5250 #define RTC_BKP15R_Pos (0U)
AnnaBridge 156:ff21514d8981 5251 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5252 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 156:ff21514d8981 5253
AnnaBridge 156:ff21514d8981 5254 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 156:ff21514d8981 5255 #define RTC_BKP16R_Pos (0U)
AnnaBridge 156:ff21514d8981 5256 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5257 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 156:ff21514d8981 5258
AnnaBridge 156:ff21514d8981 5259 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 156:ff21514d8981 5260 #define RTC_BKP17R_Pos (0U)
AnnaBridge 156:ff21514d8981 5261 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5262 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 156:ff21514d8981 5263
AnnaBridge 156:ff21514d8981 5264 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 156:ff21514d8981 5265 #define RTC_BKP18R_Pos (0U)
AnnaBridge 156:ff21514d8981 5266 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5267 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 156:ff21514d8981 5268
AnnaBridge 156:ff21514d8981 5269 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 156:ff21514d8981 5270 #define RTC_BKP19R_Pos (0U)
AnnaBridge 156:ff21514d8981 5271 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5272 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 156:ff21514d8981 5273
AnnaBridge 156:ff21514d8981 5274 /******************** Number of backup registers ******************************/
AnnaBridge 156:ff21514d8981 5275 #define RTC_BKP_NUMBER 0x000000014U
AnnaBridge 156:ff21514d8981 5276
AnnaBridge 156:ff21514d8981 5277
AnnaBridge 156:ff21514d8981 5278 /******************************************************************************/
AnnaBridge 156:ff21514d8981 5279 /* */
AnnaBridge 156:ff21514d8981 5280 /* SD host Interface */
AnnaBridge 156:ff21514d8981 5281 /* */
AnnaBridge 156:ff21514d8981 5282 /******************************************************************************/
AnnaBridge 156:ff21514d8981 5283 /****************** Bit definition for SDIO_POWER register ******************/
AnnaBridge 156:ff21514d8981 5284 #define SDIO_POWER_PWRCTRL_Pos (0U)
AnnaBridge 156:ff21514d8981 5285 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 5286 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 156:ff21514d8981 5287 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
AnnaBridge 156:ff21514d8981 5288 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
AnnaBridge 156:ff21514d8981 5289
AnnaBridge 156:ff21514d8981 5290 /****************** Bit definition for SDIO_CLKCR register ******************/
AnnaBridge 156:ff21514d8981 5291 #define SDIO_CLKCR_CLKDIV_Pos (0U)
AnnaBridge 156:ff21514d8981 5292 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
AnnaBridge 156:ff21514d8981 5293 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
AnnaBridge 156:ff21514d8981 5294 #define SDIO_CLKCR_CLKEN_Pos (8U)
AnnaBridge 156:ff21514d8981 5295 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5296 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
AnnaBridge 156:ff21514d8981 5297 #define SDIO_CLKCR_PWRSAV_Pos (9U)
AnnaBridge 156:ff21514d8981 5298 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5299 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
AnnaBridge 156:ff21514d8981 5300 #define SDIO_CLKCR_BYPASS_Pos (10U)
AnnaBridge 156:ff21514d8981 5301 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5302 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
AnnaBridge 156:ff21514d8981 5303
AnnaBridge 156:ff21514d8981 5304 #define SDIO_CLKCR_WIDBUS_Pos (11U)
AnnaBridge 156:ff21514d8981 5305 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
AnnaBridge 156:ff21514d8981 5306 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 156:ff21514d8981 5307 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
AnnaBridge 156:ff21514d8981 5308 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
AnnaBridge 156:ff21514d8981 5309
AnnaBridge 156:ff21514d8981 5310 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
AnnaBridge 156:ff21514d8981 5311 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5312 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
AnnaBridge 156:ff21514d8981 5313 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
AnnaBridge 156:ff21514d8981 5314 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5315 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
AnnaBridge 156:ff21514d8981 5316
AnnaBridge 156:ff21514d8981 5317 /******************* Bit definition for SDIO_ARG register *******************/
AnnaBridge 156:ff21514d8981 5318 #define SDIO_ARG_CMDARG_Pos (0U)
AnnaBridge 156:ff21514d8981 5319 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5320 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
AnnaBridge 156:ff21514d8981 5321
AnnaBridge 156:ff21514d8981 5322 /******************* Bit definition for SDIO_CMD register *******************/
AnnaBridge 156:ff21514d8981 5323 #define SDIO_CMD_CMDINDEX_Pos (0U)
AnnaBridge 156:ff21514d8981 5324 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
AnnaBridge 156:ff21514d8981 5325 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
AnnaBridge 156:ff21514d8981 5326
AnnaBridge 156:ff21514d8981 5327 #define SDIO_CMD_WAITRESP_Pos (6U)
AnnaBridge 156:ff21514d8981 5328 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
AnnaBridge 156:ff21514d8981 5329 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 156:ff21514d8981 5330 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 5331 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
AnnaBridge 156:ff21514d8981 5332
AnnaBridge 156:ff21514d8981 5333 #define SDIO_CMD_WAITINT_Pos (8U)
AnnaBridge 156:ff21514d8981 5334 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5335 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
AnnaBridge 156:ff21514d8981 5336 #define SDIO_CMD_WAITPEND_Pos (9U)
AnnaBridge 156:ff21514d8981 5337 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5338 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 156:ff21514d8981 5339 #define SDIO_CMD_CPSMEN_Pos (10U)
AnnaBridge 156:ff21514d8981 5340 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5341 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 156:ff21514d8981 5342 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
AnnaBridge 156:ff21514d8981 5343 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5344 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
AnnaBridge 156:ff21514d8981 5345 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
AnnaBridge 156:ff21514d8981 5346 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 5347 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
AnnaBridge 156:ff21514d8981 5348 #define SDIO_CMD_NIEN_Pos (13U)
AnnaBridge 156:ff21514d8981 5349 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5350 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
AnnaBridge 156:ff21514d8981 5351 #define SDIO_CMD_CEATACMD_Pos (14U)
AnnaBridge 156:ff21514d8981 5352 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5353 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
AnnaBridge 156:ff21514d8981 5354
AnnaBridge 156:ff21514d8981 5355 /***************** Bit definition for SDIO_RESPCMD register *****************/
AnnaBridge 156:ff21514d8981 5356 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
AnnaBridge 156:ff21514d8981 5357 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
AnnaBridge 156:ff21514d8981 5358 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
AnnaBridge 156:ff21514d8981 5359
AnnaBridge 156:ff21514d8981 5360 /****************** Bit definition for SDIO_RESP0 register ******************/
AnnaBridge 156:ff21514d8981 5361 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
AnnaBridge 156:ff21514d8981 5362 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5363 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
AnnaBridge 156:ff21514d8981 5364
AnnaBridge 156:ff21514d8981 5365 /****************** Bit definition for SDIO_RESP1 register ******************/
AnnaBridge 156:ff21514d8981 5366 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
AnnaBridge 156:ff21514d8981 5367 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5368 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
AnnaBridge 156:ff21514d8981 5369
AnnaBridge 156:ff21514d8981 5370 /****************** Bit definition for SDIO_RESP2 register ******************/
AnnaBridge 156:ff21514d8981 5371 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
AnnaBridge 156:ff21514d8981 5372 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5373 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
AnnaBridge 156:ff21514d8981 5374
AnnaBridge 156:ff21514d8981 5375 /****************** Bit definition for SDIO_RESP3 register ******************/
AnnaBridge 156:ff21514d8981 5376 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
AnnaBridge 156:ff21514d8981 5377 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5378 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
AnnaBridge 156:ff21514d8981 5379
AnnaBridge 156:ff21514d8981 5380 /****************** Bit definition for SDIO_RESP4 register ******************/
AnnaBridge 156:ff21514d8981 5381 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
AnnaBridge 156:ff21514d8981 5382 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5383 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
AnnaBridge 156:ff21514d8981 5384
AnnaBridge 156:ff21514d8981 5385 /****************** Bit definition for SDIO_DTIMER register *****************/
AnnaBridge 156:ff21514d8981 5386 #define SDIO_DTIMER_DATATIME_Pos (0U)
AnnaBridge 156:ff21514d8981 5387 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5388 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
AnnaBridge 156:ff21514d8981 5389
AnnaBridge 156:ff21514d8981 5390 /****************** Bit definition for SDIO_DLEN register *******************/
AnnaBridge 156:ff21514d8981 5391 #define SDIO_DLEN_DATALENGTH_Pos (0U)
AnnaBridge 156:ff21514d8981 5392 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
AnnaBridge 156:ff21514d8981 5393 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
AnnaBridge 156:ff21514d8981 5394
AnnaBridge 156:ff21514d8981 5395 /****************** Bit definition for SDIO_DCTRL register ******************/
AnnaBridge 156:ff21514d8981 5396 #define SDIO_DCTRL_DTEN_Pos (0U)
AnnaBridge 156:ff21514d8981 5397 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5398 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
AnnaBridge 156:ff21514d8981 5399 #define SDIO_DCTRL_DTDIR_Pos (1U)
AnnaBridge 156:ff21514d8981 5400 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5401 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
AnnaBridge 156:ff21514d8981 5402 #define SDIO_DCTRL_DTMODE_Pos (2U)
AnnaBridge 156:ff21514d8981 5403 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5404 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
AnnaBridge 156:ff21514d8981 5405 #define SDIO_DCTRL_DMAEN_Pos (3U)
AnnaBridge 156:ff21514d8981 5406 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5407 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
AnnaBridge 156:ff21514d8981 5408
AnnaBridge 156:ff21514d8981 5409 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
AnnaBridge 156:ff21514d8981 5410 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 5411 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 156:ff21514d8981 5412 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 5413 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 5414 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 5415 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
AnnaBridge 156:ff21514d8981 5416
AnnaBridge 156:ff21514d8981 5417 #define SDIO_DCTRL_RWSTART_Pos (8U)
AnnaBridge 156:ff21514d8981 5418 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5419 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
AnnaBridge 156:ff21514d8981 5420 #define SDIO_DCTRL_RWSTOP_Pos (9U)
AnnaBridge 156:ff21514d8981 5421 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5422 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
AnnaBridge 156:ff21514d8981 5423 #define SDIO_DCTRL_RWMOD_Pos (10U)
AnnaBridge 156:ff21514d8981 5424 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5425 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
AnnaBridge 156:ff21514d8981 5426 #define SDIO_DCTRL_SDIOEN_Pos (11U)
AnnaBridge 156:ff21514d8981 5427 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5428 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
AnnaBridge 156:ff21514d8981 5429
AnnaBridge 156:ff21514d8981 5430 /****************** Bit definition for SDIO_DCOUNT register *****************/
AnnaBridge 156:ff21514d8981 5431 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
AnnaBridge 156:ff21514d8981 5432 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
AnnaBridge 156:ff21514d8981 5433 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
AnnaBridge 156:ff21514d8981 5434
AnnaBridge 156:ff21514d8981 5435 /****************** Bit definition for SDIO_STA register ********************/
AnnaBridge 156:ff21514d8981 5436 #define SDIO_STA_CCRCFAIL_Pos (0U)
AnnaBridge 156:ff21514d8981 5437 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5438 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
AnnaBridge 156:ff21514d8981 5439 #define SDIO_STA_DCRCFAIL_Pos (1U)
AnnaBridge 156:ff21514d8981 5440 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5441 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
AnnaBridge 156:ff21514d8981 5442 #define SDIO_STA_CTIMEOUT_Pos (2U)
AnnaBridge 156:ff21514d8981 5443 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5444 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
AnnaBridge 156:ff21514d8981 5445 #define SDIO_STA_DTIMEOUT_Pos (3U)
AnnaBridge 156:ff21514d8981 5446 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5447 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
AnnaBridge 156:ff21514d8981 5448 #define SDIO_STA_TXUNDERR_Pos (4U)
AnnaBridge 156:ff21514d8981 5449 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5450 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
AnnaBridge 156:ff21514d8981 5451 #define SDIO_STA_RXOVERR_Pos (5U)
AnnaBridge 156:ff21514d8981 5452 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5453 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
AnnaBridge 156:ff21514d8981 5454 #define SDIO_STA_CMDREND_Pos (6U)
AnnaBridge 156:ff21514d8981 5455 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 5456 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
AnnaBridge 156:ff21514d8981 5457 #define SDIO_STA_CMDSENT_Pos (7U)
AnnaBridge 156:ff21514d8981 5458 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5459 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
AnnaBridge 156:ff21514d8981 5460 #define SDIO_STA_DATAEND_Pos (8U)
AnnaBridge 156:ff21514d8981 5461 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5462 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 156:ff21514d8981 5463 #define SDIO_STA_STBITERR_Pos (9U)
AnnaBridge 156:ff21514d8981 5464 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5465 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
AnnaBridge 156:ff21514d8981 5466 #define SDIO_STA_DBCKEND_Pos (10U)
AnnaBridge 156:ff21514d8981 5467 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5468 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
AnnaBridge 156:ff21514d8981 5469 #define SDIO_STA_CMDACT_Pos (11U)
AnnaBridge 156:ff21514d8981 5470 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5471 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
AnnaBridge 156:ff21514d8981 5472 #define SDIO_STA_TXACT_Pos (12U)
AnnaBridge 156:ff21514d8981 5473 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 5474 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
AnnaBridge 156:ff21514d8981 5475 #define SDIO_STA_RXACT_Pos (13U)
AnnaBridge 156:ff21514d8981 5476 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5477 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
AnnaBridge 156:ff21514d8981 5478 #define SDIO_STA_TXFIFOHE_Pos (14U)
AnnaBridge 156:ff21514d8981 5479 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5480 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 156:ff21514d8981 5481 #define SDIO_STA_RXFIFOHF_Pos (15U)
AnnaBridge 156:ff21514d8981 5482 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 5483 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 156:ff21514d8981 5484 #define SDIO_STA_TXFIFOF_Pos (16U)
AnnaBridge 156:ff21514d8981 5485 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 5486 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
AnnaBridge 156:ff21514d8981 5487 #define SDIO_STA_RXFIFOF_Pos (17U)
AnnaBridge 156:ff21514d8981 5488 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 5489 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
AnnaBridge 156:ff21514d8981 5490 #define SDIO_STA_TXFIFOE_Pos (18U)
AnnaBridge 156:ff21514d8981 5491 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 5492 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
AnnaBridge 156:ff21514d8981 5493 #define SDIO_STA_RXFIFOE_Pos (19U)
AnnaBridge 156:ff21514d8981 5494 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 5495 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
AnnaBridge 156:ff21514d8981 5496 #define SDIO_STA_TXDAVL_Pos (20U)
AnnaBridge 156:ff21514d8981 5497 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 5498 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
AnnaBridge 156:ff21514d8981 5499 #define SDIO_STA_RXDAVL_Pos (21U)
AnnaBridge 156:ff21514d8981 5500 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 5501 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
AnnaBridge 156:ff21514d8981 5502 #define SDIO_STA_SDIOIT_Pos (22U)
AnnaBridge 156:ff21514d8981 5503 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 5504 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
AnnaBridge 156:ff21514d8981 5505 #define SDIO_STA_CEATAEND_Pos (23U)
AnnaBridge 156:ff21514d8981 5506 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 5507 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
AnnaBridge 156:ff21514d8981 5508
AnnaBridge 156:ff21514d8981 5509 /******************* Bit definition for SDIO_ICR register *******************/
AnnaBridge 156:ff21514d8981 5510 #define SDIO_ICR_CCRCFAILC_Pos (0U)
AnnaBridge 156:ff21514d8981 5511 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5512 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
AnnaBridge 156:ff21514d8981 5513 #define SDIO_ICR_DCRCFAILC_Pos (1U)
AnnaBridge 156:ff21514d8981 5514 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5515 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
AnnaBridge 156:ff21514d8981 5516 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
AnnaBridge 156:ff21514d8981 5517 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5518 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
AnnaBridge 156:ff21514d8981 5519 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
AnnaBridge 156:ff21514d8981 5520 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5521 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
AnnaBridge 156:ff21514d8981 5522 #define SDIO_ICR_TXUNDERRC_Pos (4U)
AnnaBridge 156:ff21514d8981 5523 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5524 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
AnnaBridge 156:ff21514d8981 5525 #define SDIO_ICR_RXOVERRC_Pos (5U)
AnnaBridge 156:ff21514d8981 5526 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5527 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
AnnaBridge 156:ff21514d8981 5528 #define SDIO_ICR_CMDRENDC_Pos (6U)
AnnaBridge 156:ff21514d8981 5529 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 5530 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
AnnaBridge 156:ff21514d8981 5531 #define SDIO_ICR_CMDSENTC_Pos (7U)
AnnaBridge 156:ff21514d8981 5532 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5533 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
AnnaBridge 156:ff21514d8981 5534 #define SDIO_ICR_DATAENDC_Pos (8U)
AnnaBridge 156:ff21514d8981 5535 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5536 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
AnnaBridge 156:ff21514d8981 5537 #define SDIO_ICR_STBITERRC_Pos (9U)
AnnaBridge 156:ff21514d8981 5538 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5539 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
AnnaBridge 156:ff21514d8981 5540 #define SDIO_ICR_DBCKENDC_Pos (10U)
AnnaBridge 156:ff21514d8981 5541 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5542 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
AnnaBridge 156:ff21514d8981 5543 #define SDIO_ICR_SDIOITC_Pos (22U)
AnnaBridge 156:ff21514d8981 5544 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 5545 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
AnnaBridge 156:ff21514d8981 5546 #define SDIO_ICR_CEATAENDC_Pos (23U)
AnnaBridge 156:ff21514d8981 5547 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 5548 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
AnnaBridge 156:ff21514d8981 5549
AnnaBridge 156:ff21514d8981 5550 /****************** Bit definition for SDIO_MASK register *******************/
AnnaBridge 156:ff21514d8981 5551 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
AnnaBridge 156:ff21514d8981 5552 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5553 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 156:ff21514d8981 5554 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
AnnaBridge 156:ff21514d8981 5555 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5556 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 156:ff21514d8981 5557 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
AnnaBridge 156:ff21514d8981 5558 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5559 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
AnnaBridge 156:ff21514d8981 5560 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
AnnaBridge 156:ff21514d8981 5561 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5562 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
AnnaBridge 156:ff21514d8981 5563 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
AnnaBridge 156:ff21514d8981 5564 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5565 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 156:ff21514d8981 5566 #define SDIO_MASK_RXOVERRIE_Pos (5U)
AnnaBridge 156:ff21514d8981 5567 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5568 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 156:ff21514d8981 5569 #define SDIO_MASK_CMDRENDIE_Pos (6U)
AnnaBridge 156:ff21514d8981 5570 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 5571 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
AnnaBridge 156:ff21514d8981 5572 #define SDIO_MASK_CMDSENTIE_Pos (7U)
AnnaBridge 156:ff21514d8981 5573 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5574 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
AnnaBridge 156:ff21514d8981 5575 #define SDIO_MASK_DATAENDIE_Pos (8U)
AnnaBridge 156:ff21514d8981 5576 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5577 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
AnnaBridge 156:ff21514d8981 5578 #define SDIO_MASK_STBITERRIE_Pos (9U)
AnnaBridge 156:ff21514d8981 5579 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5580 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
AnnaBridge 156:ff21514d8981 5581 #define SDIO_MASK_DBCKENDIE_Pos (10U)
AnnaBridge 156:ff21514d8981 5582 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5583 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
AnnaBridge 156:ff21514d8981 5584 #define SDIO_MASK_CMDACTIE_Pos (11U)
AnnaBridge 156:ff21514d8981 5585 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5586 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
AnnaBridge 156:ff21514d8981 5587 #define SDIO_MASK_TXACTIE_Pos (12U)
AnnaBridge 156:ff21514d8981 5588 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 5589 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
AnnaBridge 156:ff21514d8981 5590 #define SDIO_MASK_RXACTIE_Pos (13U)
AnnaBridge 156:ff21514d8981 5591 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5592 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
AnnaBridge 156:ff21514d8981 5593 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
AnnaBridge 156:ff21514d8981 5594 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5595 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 156:ff21514d8981 5596 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
AnnaBridge 156:ff21514d8981 5597 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 5598 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 156:ff21514d8981 5599 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
AnnaBridge 156:ff21514d8981 5600 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 5601 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
AnnaBridge 156:ff21514d8981 5602 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
AnnaBridge 156:ff21514d8981 5603 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 5604 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 156:ff21514d8981 5605 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
AnnaBridge 156:ff21514d8981 5606 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 5607 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 156:ff21514d8981 5608 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
AnnaBridge 156:ff21514d8981 5609 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 5610 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
AnnaBridge 156:ff21514d8981 5611 #define SDIO_MASK_TXDAVLIE_Pos (20U)
AnnaBridge 156:ff21514d8981 5612 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 5613 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
AnnaBridge 156:ff21514d8981 5614 #define SDIO_MASK_RXDAVLIE_Pos (21U)
AnnaBridge 156:ff21514d8981 5615 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 5616 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
AnnaBridge 156:ff21514d8981 5617 #define SDIO_MASK_SDIOITIE_Pos (22U)
AnnaBridge 156:ff21514d8981 5618 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 5619 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
AnnaBridge 156:ff21514d8981 5620 #define SDIO_MASK_CEATAENDIE_Pos (23U)
AnnaBridge 156:ff21514d8981 5621 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 5622 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
AnnaBridge 156:ff21514d8981 5623
AnnaBridge 156:ff21514d8981 5624 /***************** Bit definition for SDIO_FIFOCNT register *****************/
AnnaBridge 156:ff21514d8981 5625 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
AnnaBridge 156:ff21514d8981 5626 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
AnnaBridge 156:ff21514d8981 5627 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
AnnaBridge 156:ff21514d8981 5628
AnnaBridge 156:ff21514d8981 5629 /****************** Bit definition for SDIO_FIFO register *******************/
AnnaBridge 156:ff21514d8981 5630 #define SDIO_FIFO_FIFODATA_Pos (0U)
AnnaBridge 156:ff21514d8981 5631 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 5632 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
AnnaBridge 156:ff21514d8981 5633
AnnaBridge 156:ff21514d8981 5634 /******************************************************************************/
AnnaBridge 156:ff21514d8981 5635 /* */
AnnaBridge 156:ff21514d8981 5636 /* Serial Peripheral Interface */
AnnaBridge 156:ff21514d8981 5637 /* */
AnnaBridge 156:ff21514d8981 5638 /******************************************************************************/
AnnaBridge 156:ff21514d8981 5639 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
AnnaBridge 156:ff21514d8981 5640
AnnaBridge 156:ff21514d8981 5641 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 156:ff21514d8981 5642 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 156:ff21514d8981 5643 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5644 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
AnnaBridge 156:ff21514d8981 5645 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 156:ff21514d8981 5646 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5647 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 156:ff21514d8981 5648 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 156:ff21514d8981 5649 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5650 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
AnnaBridge 156:ff21514d8981 5651
AnnaBridge 156:ff21514d8981 5652 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 156:ff21514d8981 5653 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 156:ff21514d8981 5654 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
AnnaBridge 156:ff21514d8981 5655 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5656 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5657 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5658
AnnaBridge 156:ff21514d8981 5659 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 156:ff21514d8981 5660 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 5661 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
AnnaBridge 156:ff21514d8981 5662 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 156:ff21514d8981 5663 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5664 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
AnnaBridge 156:ff21514d8981 5665 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 156:ff21514d8981 5666 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5667 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
AnnaBridge 156:ff21514d8981 5668 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 156:ff21514d8981 5669 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5670 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
AnnaBridge 156:ff21514d8981 5671 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 156:ff21514d8981 5672 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5673 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
AnnaBridge 156:ff21514d8981 5674 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 156:ff21514d8981 5675 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5676 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
AnnaBridge 156:ff21514d8981 5677 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 156:ff21514d8981 5678 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 5679 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
AnnaBridge 156:ff21514d8981 5680 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 156:ff21514d8981 5681 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 5682 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
AnnaBridge 156:ff21514d8981 5683 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 156:ff21514d8981 5684 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 5685 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
AnnaBridge 156:ff21514d8981 5686 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 156:ff21514d8981 5687 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 5688 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
AnnaBridge 156:ff21514d8981 5689
AnnaBridge 156:ff21514d8981 5690 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 156:ff21514d8981 5691 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 156:ff21514d8981 5692 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5693 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
AnnaBridge 156:ff21514d8981 5694 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 156:ff21514d8981 5695 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5696 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
AnnaBridge 156:ff21514d8981 5697 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 156:ff21514d8981 5698 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5699 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
AnnaBridge 156:ff21514d8981 5700 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 156:ff21514d8981 5701 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5702 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
AnnaBridge 156:ff21514d8981 5703 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 156:ff21514d8981 5704 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5705 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 156:ff21514d8981 5706 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 156:ff21514d8981 5707 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 5708 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
AnnaBridge 156:ff21514d8981 5709 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 156:ff21514d8981 5710 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5711 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
AnnaBridge 156:ff21514d8981 5712
AnnaBridge 156:ff21514d8981 5713 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 156:ff21514d8981 5714 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 156:ff21514d8981 5715 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5716 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
AnnaBridge 156:ff21514d8981 5717 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 156:ff21514d8981 5718 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5719 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
AnnaBridge 156:ff21514d8981 5720 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 156:ff21514d8981 5721 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5722 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
AnnaBridge 156:ff21514d8981 5723 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 156:ff21514d8981 5724 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5725 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
AnnaBridge 156:ff21514d8981 5726 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 156:ff21514d8981 5727 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5728 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
AnnaBridge 156:ff21514d8981 5729 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 156:ff21514d8981 5730 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5731 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
AnnaBridge 156:ff21514d8981 5732 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 156:ff21514d8981 5733 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 5734 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 156:ff21514d8981 5735 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 156:ff21514d8981 5736 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5737 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
AnnaBridge 156:ff21514d8981 5738 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 156:ff21514d8981 5739 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5740 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
AnnaBridge 156:ff21514d8981 5741
AnnaBridge 156:ff21514d8981 5742 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 156:ff21514d8981 5743 #define SPI_DR_DR_Pos (0U)
AnnaBridge 156:ff21514d8981 5744 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 5745 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
AnnaBridge 156:ff21514d8981 5746
AnnaBridge 156:ff21514d8981 5747 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 156:ff21514d8981 5748 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 156:ff21514d8981 5749 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 5750 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
AnnaBridge 156:ff21514d8981 5751
AnnaBridge 156:ff21514d8981 5752 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 156:ff21514d8981 5753 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 156:ff21514d8981 5754 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 5755 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
AnnaBridge 156:ff21514d8981 5756
AnnaBridge 156:ff21514d8981 5757 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 156:ff21514d8981 5758 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 156:ff21514d8981 5759 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 5760 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
AnnaBridge 156:ff21514d8981 5761
AnnaBridge 156:ff21514d8981 5762 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 156:ff21514d8981 5763 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 156:ff21514d8981 5764 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5765 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 156:ff21514d8981 5766
AnnaBridge 156:ff21514d8981 5767 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 156:ff21514d8981 5768 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 156:ff21514d8981 5769 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 156:ff21514d8981 5770 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5771 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 5772
AnnaBridge 156:ff21514d8981 5773 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 156:ff21514d8981 5774 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 5775 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 156:ff21514d8981 5776
AnnaBridge 156:ff21514d8981 5777 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 156:ff21514d8981 5778 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 156:ff21514d8981 5779 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 156:ff21514d8981 5780 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 5781 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 5782
AnnaBridge 156:ff21514d8981 5783 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 156:ff21514d8981 5784 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 5785 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 156:ff21514d8981 5786
AnnaBridge 156:ff21514d8981 5787 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 156:ff21514d8981 5788 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 5789 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 156:ff21514d8981 5790 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5791 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5792
AnnaBridge 156:ff21514d8981 5793 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 156:ff21514d8981 5794 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 5795 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 156:ff21514d8981 5796 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 156:ff21514d8981 5797 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 5798 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 156:ff21514d8981 5799
AnnaBridge 156:ff21514d8981 5800 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 156:ff21514d8981 5801 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 156:ff21514d8981 5802 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 156:ff21514d8981 5803 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 156:ff21514d8981 5804 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 156:ff21514d8981 5805 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 5806 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 156:ff21514d8981 5807 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 156:ff21514d8981 5808 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 5809 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 156:ff21514d8981 5810
AnnaBridge 156:ff21514d8981 5811 /******************************************************************************/
AnnaBridge 156:ff21514d8981 5812 /* */
AnnaBridge 156:ff21514d8981 5813 /* SYSCFG */
AnnaBridge 156:ff21514d8981 5814 /* */
AnnaBridge 156:ff21514d8981 5815 /******************************************************************************/
AnnaBridge 156:ff21514d8981 5816 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 156:ff21514d8981 5817 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 156:ff21514d8981 5818 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 5819 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 156:ff21514d8981 5820 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 5821 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 5822 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 156:ff21514d8981 5823 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
AnnaBridge 156:ff21514d8981 5824 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 5825 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 156:ff21514d8981 5826
AnnaBridge 156:ff21514d8981 5827 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 156:ff21514d8981 5828 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 156:ff21514d8981 5829 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 5830 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 156:ff21514d8981 5831 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 156:ff21514d8981 5832 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 5833 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 156:ff21514d8981 5834 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 156:ff21514d8981 5835 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 5836 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 156:ff21514d8981 5837 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 156:ff21514d8981 5838 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 156:ff21514d8981 5839 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 156:ff21514d8981 5840 /**
AnnaBridge 156:ff21514d8981 5841 * @brief EXTI0 configuration
AnnaBridge 156:ff21514d8981 5842 */
AnnaBridge 156:ff21514d8981 5843 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 156:ff21514d8981 5844 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 156:ff21514d8981 5845 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 156:ff21514d8981 5846 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
AnnaBridge 156:ff21514d8981 5847 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
AnnaBridge 156:ff21514d8981 5848 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 156:ff21514d8981 5849
AnnaBridge 156:ff21514d8981 5850 /**
AnnaBridge 156:ff21514d8981 5851 * @brief EXTI1 configuration
AnnaBridge 156:ff21514d8981 5852 */
AnnaBridge 156:ff21514d8981 5853 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 156:ff21514d8981 5854 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 156:ff21514d8981 5855 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 156:ff21514d8981 5856 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
AnnaBridge 156:ff21514d8981 5857 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
AnnaBridge 156:ff21514d8981 5858 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 156:ff21514d8981 5859
AnnaBridge 156:ff21514d8981 5860 /**
AnnaBridge 156:ff21514d8981 5861 * @brief EXTI2 configuration
AnnaBridge 156:ff21514d8981 5862 */
AnnaBridge 156:ff21514d8981 5863 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 156:ff21514d8981 5864 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 156:ff21514d8981 5865 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 156:ff21514d8981 5866 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
AnnaBridge 156:ff21514d8981 5867 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
AnnaBridge 156:ff21514d8981 5868 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 156:ff21514d8981 5869
AnnaBridge 156:ff21514d8981 5870 /**
AnnaBridge 156:ff21514d8981 5871 * @brief EXTI3 configuration
AnnaBridge 156:ff21514d8981 5872 */
AnnaBridge 156:ff21514d8981 5873 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 156:ff21514d8981 5874 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 156:ff21514d8981 5875 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 156:ff21514d8981 5876 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
AnnaBridge 156:ff21514d8981 5877 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
AnnaBridge 156:ff21514d8981 5878 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
AnnaBridge 156:ff21514d8981 5879
AnnaBridge 156:ff21514d8981 5880 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 156:ff21514d8981 5881 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 156:ff21514d8981 5882 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 5883 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 156:ff21514d8981 5884 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 156:ff21514d8981 5885 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 5886 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 156:ff21514d8981 5887 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 156:ff21514d8981 5888 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 5889 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 156:ff21514d8981 5890 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 156:ff21514d8981 5891 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 156:ff21514d8981 5892 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 156:ff21514d8981 5893
AnnaBridge 156:ff21514d8981 5894 /**
AnnaBridge 156:ff21514d8981 5895 * @brief EXTI4 configuration
AnnaBridge 156:ff21514d8981 5896 */
AnnaBridge 156:ff21514d8981 5897 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 156:ff21514d8981 5898 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 156:ff21514d8981 5899 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 156:ff21514d8981 5900 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
AnnaBridge 156:ff21514d8981 5901 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
AnnaBridge 156:ff21514d8981 5902 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 156:ff21514d8981 5903
AnnaBridge 156:ff21514d8981 5904 /**
AnnaBridge 156:ff21514d8981 5905 * @brief EXTI5 configuration
AnnaBridge 156:ff21514d8981 5906 */
AnnaBridge 156:ff21514d8981 5907 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 156:ff21514d8981 5908 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 156:ff21514d8981 5909 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 156:ff21514d8981 5910 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
AnnaBridge 156:ff21514d8981 5911 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
AnnaBridge 156:ff21514d8981 5912 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 156:ff21514d8981 5913
AnnaBridge 156:ff21514d8981 5914 /**
AnnaBridge 156:ff21514d8981 5915 * @brief EXTI6 configuration
AnnaBridge 156:ff21514d8981 5916 */
AnnaBridge 156:ff21514d8981 5917 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 156:ff21514d8981 5918 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 156:ff21514d8981 5919 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 156:ff21514d8981 5920 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
AnnaBridge 156:ff21514d8981 5921 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
AnnaBridge 156:ff21514d8981 5922 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 156:ff21514d8981 5923
AnnaBridge 156:ff21514d8981 5924 /**
AnnaBridge 156:ff21514d8981 5925 * @brief EXTI7 configuration
AnnaBridge 156:ff21514d8981 5926 */
AnnaBridge 156:ff21514d8981 5927 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 156:ff21514d8981 5928 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 156:ff21514d8981 5929 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 156:ff21514d8981 5930 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
AnnaBridge 156:ff21514d8981 5931 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
AnnaBridge 156:ff21514d8981 5932 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
AnnaBridge 156:ff21514d8981 5933
AnnaBridge 156:ff21514d8981 5934 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 156:ff21514d8981 5935 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 156:ff21514d8981 5936 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 5937 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 156:ff21514d8981 5938 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 156:ff21514d8981 5939 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 5940 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 156:ff21514d8981 5941 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 156:ff21514d8981 5942 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 5943 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 156:ff21514d8981 5944 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 156:ff21514d8981 5945 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 156:ff21514d8981 5946 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 156:ff21514d8981 5947
AnnaBridge 156:ff21514d8981 5948 /**
AnnaBridge 156:ff21514d8981 5949 * @brief EXTI8 configuration
AnnaBridge 156:ff21514d8981 5950 */
AnnaBridge 156:ff21514d8981 5951 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 156:ff21514d8981 5952 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 156:ff21514d8981 5953 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 156:ff21514d8981 5954 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
AnnaBridge 156:ff21514d8981 5955 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
AnnaBridge 156:ff21514d8981 5956 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 156:ff21514d8981 5957
AnnaBridge 156:ff21514d8981 5958 /**
AnnaBridge 156:ff21514d8981 5959 * @brief EXTI9 configuration
AnnaBridge 156:ff21514d8981 5960 */
AnnaBridge 156:ff21514d8981 5961 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 156:ff21514d8981 5962 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 156:ff21514d8981 5963 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 156:ff21514d8981 5964 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
AnnaBridge 156:ff21514d8981 5965 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
AnnaBridge 156:ff21514d8981 5966 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 156:ff21514d8981 5967
AnnaBridge 156:ff21514d8981 5968 /**
AnnaBridge 156:ff21514d8981 5969 * @brief EXTI10 configuration
AnnaBridge 156:ff21514d8981 5970 */
AnnaBridge 156:ff21514d8981 5971 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 156:ff21514d8981 5972 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 156:ff21514d8981 5973 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 156:ff21514d8981 5974 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
AnnaBridge 156:ff21514d8981 5975 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
AnnaBridge 156:ff21514d8981 5976 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 156:ff21514d8981 5977
AnnaBridge 156:ff21514d8981 5978 /**
AnnaBridge 156:ff21514d8981 5979 * @brief EXTI11 configuration
AnnaBridge 156:ff21514d8981 5980 */
AnnaBridge 156:ff21514d8981 5981 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 156:ff21514d8981 5982 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 156:ff21514d8981 5983 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 156:ff21514d8981 5984 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
AnnaBridge 156:ff21514d8981 5985 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
AnnaBridge 156:ff21514d8981 5986 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
AnnaBridge 156:ff21514d8981 5987
AnnaBridge 156:ff21514d8981 5988 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 156:ff21514d8981 5989 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 156:ff21514d8981 5990 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 5991 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 156:ff21514d8981 5992 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 156:ff21514d8981 5993 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 5994 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 156:ff21514d8981 5995 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 156:ff21514d8981 5996 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 5997 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 156:ff21514d8981 5998 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 156:ff21514d8981 5999 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 156:ff21514d8981 6000 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 156:ff21514d8981 6001
AnnaBridge 156:ff21514d8981 6002 /**
AnnaBridge 156:ff21514d8981 6003 * @brief EXTI12 configuration
AnnaBridge 156:ff21514d8981 6004 */
AnnaBridge 156:ff21514d8981 6005 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 156:ff21514d8981 6006 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 156:ff21514d8981 6007 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 156:ff21514d8981 6008 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
AnnaBridge 156:ff21514d8981 6009 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
AnnaBridge 156:ff21514d8981 6010 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 156:ff21514d8981 6011
AnnaBridge 156:ff21514d8981 6012 /**
AnnaBridge 156:ff21514d8981 6013 * @brief EXTI13 configuration
AnnaBridge 156:ff21514d8981 6014 */
AnnaBridge 156:ff21514d8981 6015 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 156:ff21514d8981 6016 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 156:ff21514d8981 6017 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 156:ff21514d8981 6018 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
AnnaBridge 156:ff21514d8981 6019 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
AnnaBridge 156:ff21514d8981 6020 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 156:ff21514d8981 6021
AnnaBridge 156:ff21514d8981 6022 /**
AnnaBridge 156:ff21514d8981 6023 * @brief EXTI14 configuration
AnnaBridge 156:ff21514d8981 6024 */
AnnaBridge 156:ff21514d8981 6025 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 156:ff21514d8981 6026 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 156:ff21514d8981 6027 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 156:ff21514d8981 6028 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
AnnaBridge 156:ff21514d8981 6029 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
AnnaBridge 156:ff21514d8981 6030 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 156:ff21514d8981 6031
AnnaBridge 156:ff21514d8981 6032 /**
AnnaBridge 156:ff21514d8981 6033 * @brief EXTI15 configuration
AnnaBridge 156:ff21514d8981 6034 */
AnnaBridge 156:ff21514d8981 6035 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 156:ff21514d8981 6036 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 156:ff21514d8981 6037 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 156:ff21514d8981 6038 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
AnnaBridge 156:ff21514d8981 6039 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
AnnaBridge 156:ff21514d8981 6040 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 156:ff21514d8981 6041
AnnaBridge 156:ff21514d8981 6042 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 156:ff21514d8981 6043 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
AnnaBridge 156:ff21514d8981 6044 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6045 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
AnnaBridge 156:ff21514d8981 6046 #define SYSCFG_CMPCR_READY_Pos (8U)
AnnaBridge 156:ff21514d8981 6047 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6048 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
AnnaBridge 156:ff21514d8981 6049
AnnaBridge 156:ff21514d8981 6050 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6051 /* */
AnnaBridge 156:ff21514d8981 6052 /* TIM */
AnnaBridge 156:ff21514d8981 6053 /* */
AnnaBridge 156:ff21514d8981 6054 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6055 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 156:ff21514d8981 6056 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 156:ff21514d8981 6057 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6058 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 156:ff21514d8981 6059 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 156:ff21514d8981 6060 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6061 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 156:ff21514d8981 6062 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 156:ff21514d8981 6063 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6064 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 156:ff21514d8981 6065 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 156:ff21514d8981 6066 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6067 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 156:ff21514d8981 6068 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 156:ff21514d8981 6069 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 6070 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 156:ff21514d8981 6071
AnnaBridge 156:ff21514d8981 6072 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 156:ff21514d8981 6073 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 156:ff21514d8981 6074 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 156:ff21514d8981 6075 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6076 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6077
AnnaBridge 156:ff21514d8981 6078 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 156:ff21514d8981 6079 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6080 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 156:ff21514d8981 6081
AnnaBridge 156:ff21514d8981 6082 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 156:ff21514d8981 6083 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 6084 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 156:ff21514d8981 6085 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
AnnaBridge 156:ff21514d8981 6086 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
AnnaBridge 156:ff21514d8981 6087
AnnaBridge 156:ff21514d8981 6088 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 156:ff21514d8981 6089 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 156:ff21514d8981 6090 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6091 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 156:ff21514d8981 6092 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 156:ff21514d8981 6093 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6094 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 156:ff21514d8981 6095 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 156:ff21514d8981 6096 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6097 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 156:ff21514d8981 6098
AnnaBridge 156:ff21514d8981 6099 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 156:ff21514d8981 6100 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 6101 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 156:ff21514d8981 6102 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6103 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6104 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6105
AnnaBridge 156:ff21514d8981 6106 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 156:ff21514d8981 6107 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6108 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 156:ff21514d8981 6109 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 156:ff21514d8981 6110 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6111 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 156:ff21514d8981 6112 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 156:ff21514d8981 6113 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6114 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 156:ff21514d8981 6115 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 156:ff21514d8981 6116 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6117 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 156:ff21514d8981 6118 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 156:ff21514d8981 6119 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6120 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 156:ff21514d8981 6121 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 156:ff21514d8981 6122 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 6123 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 156:ff21514d8981 6124 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 156:ff21514d8981 6125 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 6126 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 156:ff21514d8981 6127 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 156:ff21514d8981 6128 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 6129 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 156:ff21514d8981 6130
AnnaBridge 156:ff21514d8981 6131 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 156:ff21514d8981 6132 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 156:ff21514d8981 6133 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 156:ff21514d8981 6134 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 156:ff21514d8981 6135 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
AnnaBridge 156:ff21514d8981 6136 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
AnnaBridge 156:ff21514d8981 6137 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
AnnaBridge 156:ff21514d8981 6138
AnnaBridge 156:ff21514d8981 6139 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 156:ff21514d8981 6140 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 6141 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 156:ff21514d8981 6142 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6143 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6144 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6145
AnnaBridge 156:ff21514d8981 6146 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 156:ff21514d8981 6147 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6148 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 156:ff21514d8981 6149
AnnaBridge 156:ff21514d8981 6150 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 156:ff21514d8981 6151 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 156:ff21514d8981 6152 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 156:ff21514d8981 6153 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
AnnaBridge 156:ff21514d8981 6154 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
AnnaBridge 156:ff21514d8981 6155 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
AnnaBridge 156:ff21514d8981 6156 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
AnnaBridge 156:ff21514d8981 6157
AnnaBridge 156:ff21514d8981 6158 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 156:ff21514d8981 6159 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 156:ff21514d8981 6160 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 156:ff21514d8981 6161 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
AnnaBridge 156:ff21514d8981 6162 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
AnnaBridge 156:ff21514d8981 6163
AnnaBridge 156:ff21514d8981 6164 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 156:ff21514d8981 6165 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 6166 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 156:ff21514d8981 6167 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 156:ff21514d8981 6168 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 6169 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 156:ff21514d8981 6170
AnnaBridge 156:ff21514d8981 6171 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 156:ff21514d8981 6172 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 156:ff21514d8981 6173 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6174 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 156:ff21514d8981 6175 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 156:ff21514d8981 6176 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6177 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 156:ff21514d8981 6178 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 156:ff21514d8981 6179 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6180 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 156:ff21514d8981 6181 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 156:ff21514d8981 6182 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6183 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 156:ff21514d8981 6184 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 156:ff21514d8981 6185 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 6186 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 156:ff21514d8981 6187 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 156:ff21514d8981 6188 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6189 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 156:ff21514d8981 6190 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 156:ff21514d8981 6191 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6192 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 156:ff21514d8981 6193 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 156:ff21514d8981 6194 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6195 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 156:ff21514d8981 6196 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 156:ff21514d8981 6197 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6198 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 156:ff21514d8981 6199 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 156:ff21514d8981 6200 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6201 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 156:ff21514d8981 6202 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 156:ff21514d8981 6203 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6204 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 156:ff21514d8981 6205 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 156:ff21514d8981 6206 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6207 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 156:ff21514d8981 6208 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 156:ff21514d8981 6209 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 6210 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 156:ff21514d8981 6211 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 156:ff21514d8981 6212 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 6213 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 156:ff21514d8981 6214 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 156:ff21514d8981 6215 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 6216 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 156:ff21514d8981 6217
AnnaBridge 156:ff21514d8981 6218 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 156:ff21514d8981 6219 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 156:ff21514d8981 6220 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6221 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 156:ff21514d8981 6222 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 156:ff21514d8981 6223 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6224 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 156:ff21514d8981 6225 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 156:ff21514d8981 6226 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6227 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 156:ff21514d8981 6228 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 156:ff21514d8981 6229 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6230 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 156:ff21514d8981 6231 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 156:ff21514d8981 6232 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 6233 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 156:ff21514d8981 6234 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 156:ff21514d8981 6235 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6236 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 156:ff21514d8981 6237 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 156:ff21514d8981 6238 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6239 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 156:ff21514d8981 6240 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 156:ff21514d8981 6241 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6242 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 156:ff21514d8981 6243 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 156:ff21514d8981 6244 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6245 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 156:ff21514d8981 6246 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 156:ff21514d8981 6247 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6248 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 156:ff21514d8981 6249 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 156:ff21514d8981 6250 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6251 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 156:ff21514d8981 6252 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 156:ff21514d8981 6253 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 6254 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 156:ff21514d8981 6255
AnnaBridge 156:ff21514d8981 6256 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 156:ff21514d8981 6257 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 156:ff21514d8981 6258 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6259 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 156:ff21514d8981 6260 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 156:ff21514d8981 6261 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6262 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 156:ff21514d8981 6263 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 156:ff21514d8981 6264 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6265 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 156:ff21514d8981 6266 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 156:ff21514d8981 6267 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6268 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 156:ff21514d8981 6269 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 156:ff21514d8981 6270 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 6271 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 156:ff21514d8981 6272 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 156:ff21514d8981 6273 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6274 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 156:ff21514d8981 6275 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 156:ff21514d8981 6276 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6277 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 156:ff21514d8981 6278 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 156:ff21514d8981 6279 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6280 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 156:ff21514d8981 6281
AnnaBridge 156:ff21514d8981 6282 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 156:ff21514d8981 6283 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 156:ff21514d8981 6284 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 6285 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 156:ff21514d8981 6286 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
AnnaBridge 156:ff21514d8981 6287 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
AnnaBridge 156:ff21514d8981 6288
AnnaBridge 156:ff21514d8981 6289 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 156:ff21514d8981 6290 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6291 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 156:ff21514d8981 6292 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 156:ff21514d8981 6293 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6294 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 156:ff21514d8981 6295
AnnaBridge 156:ff21514d8981 6296 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 156:ff21514d8981 6297 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 6298 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 156:ff21514d8981 6299 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6300 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6301 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6302
AnnaBridge 156:ff21514d8981 6303 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 156:ff21514d8981 6304 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6305 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 156:ff21514d8981 6306
AnnaBridge 156:ff21514d8981 6307 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 156:ff21514d8981 6308 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 6309 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 156:ff21514d8981 6310 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
AnnaBridge 156:ff21514d8981 6311 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
AnnaBridge 156:ff21514d8981 6312
AnnaBridge 156:ff21514d8981 6313 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 156:ff21514d8981 6314 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6315 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 156:ff21514d8981 6316 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 156:ff21514d8981 6317 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6318 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 156:ff21514d8981 6319
AnnaBridge 156:ff21514d8981 6320 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 156:ff21514d8981 6321 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 156:ff21514d8981 6322 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 156:ff21514d8981 6323 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
AnnaBridge 156:ff21514d8981 6324 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
AnnaBridge 156:ff21514d8981 6325 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
AnnaBridge 156:ff21514d8981 6326
AnnaBridge 156:ff21514d8981 6327 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 156:ff21514d8981 6328 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 6329 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 156:ff21514d8981 6330
AnnaBridge 156:ff21514d8981 6331 /*----------------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 6332
AnnaBridge 156:ff21514d8981 6333 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 156:ff21514d8981 6334 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 156:ff21514d8981 6335 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 156:ff21514d8981 6336 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
AnnaBridge 156:ff21514d8981 6337 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
AnnaBridge 156:ff21514d8981 6338
AnnaBridge 156:ff21514d8981 6339 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 156:ff21514d8981 6340 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 6341 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 156:ff21514d8981 6342 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6343 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6344 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6345 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
AnnaBridge 156:ff21514d8981 6346
AnnaBridge 156:ff21514d8981 6347 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 156:ff21514d8981 6348 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 156:ff21514d8981 6349 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 156:ff21514d8981 6350 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
AnnaBridge 156:ff21514d8981 6351 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
AnnaBridge 156:ff21514d8981 6352
AnnaBridge 156:ff21514d8981 6353 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 156:ff21514d8981 6354 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 156:ff21514d8981 6355 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 156:ff21514d8981 6356 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
AnnaBridge 156:ff21514d8981 6357 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
AnnaBridge 156:ff21514d8981 6358 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
AnnaBridge 156:ff21514d8981 6359 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
AnnaBridge 156:ff21514d8981 6360
AnnaBridge 156:ff21514d8981 6361 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 156:ff21514d8981 6362 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 156:ff21514d8981 6363 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 6364 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 156:ff21514d8981 6365 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
AnnaBridge 156:ff21514d8981 6366 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
AnnaBridge 156:ff21514d8981 6367
AnnaBridge 156:ff21514d8981 6368 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 156:ff21514d8981 6369 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6370 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 156:ff21514d8981 6371 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 156:ff21514d8981 6372 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6373 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 156:ff21514d8981 6374
AnnaBridge 156:ff21514d8981 6375 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 156:ff21514d8981 6376 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 6377 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 156:ff21514d8981 6378 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6379 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6380 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6381
AnnaBridge 156:ff21514d8981 6382 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 156:ff21514d8981 6383 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6384 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 156:ff21514d8981 6385
AnnaBridge 156:ff21514d8981 6386 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 156:ff21514d8981 6387 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 6388 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 156:ff21514d8981 6389 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
AnnaBridge 156:ff21514d8981 6390 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
AnnaBridge 156:ff21514d8981 6391
AnnaBridge 156:ff21514d8981 6392 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 156:ff21514d8981 6393 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6394 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 156:ff21514d8981 6395 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 156:ff21514d8981 6396 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6397 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 156:ff21514d8981 6398
AnnaBridge 156:ff21514d8981 6399 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 156:ff21514d8981 6400 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 156:ff21514d8981 6401 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 156:ff21514d8981 6402 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
AnnaBridge 156:ff21514d8981 6403 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
AnnaBridge 156:ff21514d8981 6404 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
AnnaBridge 156:ff21514d8981 6405
AnnaBridge 156:ff21514d8981 6406 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 156:ff21514d8981 6407 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 6408 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 156:ff21514d8981 6409
AnnaBridge 156:ff21514d8981 6410 /*----------------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 6411
AnnaBridge 156:ff21514d8981 6412 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 156:ff21514d8981 6413 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 156:ff21514d8981 6414 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 156:ff21514d8981 6415 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
AnnaBridge 156:ff21514d8981 6416 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
AnnaBridge 156:ff21514d8981 6417
AnnaBridge 156:ff21514d8981 6418 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 156:ff21514d8981 6419 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 156:ff21514d8981 6420 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 156:ff21514d8981 6421 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6422 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6423 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6424 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
AnnaBridge 156:ff21514d8981 6425
AnnaBridge 156:ff21514d8981 6426 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 156:ff21514d8981 6427 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 156:ff21514d8981 6428 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 156:ff21514d8981 6429 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
AnnaBridge 156:ff21514d8981 6430 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
AnnaBridge 156:ff21514d8981 6431
AnnaBridge 156:ff21514d8981 6432 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 156:ff21514d8981 6433 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 156:ff21514d8981 6434 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 156:ff21514d8981 6435 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
AnnaBridge 156:ff21514d8981 6436 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
AnnaBridge 156:ff21514d8981 6437 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
AnnaBridge 156:ff21514d8981 6438 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
AnnaBridge 156:ff21514d8981 6439
AnnaBridge 156:ff21514d8981 6440 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 156:ff21514d8981 6441 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 156:ff21514d8981 6442 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6443 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 156:ff21514d8981 6444 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 156:ff21514d8981 6445 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6446 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 156:ff21514d8981 6447 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 156:ff21514d8981 6448 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6449 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 156:ff21514d8981 6450 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 156:ff21514d8981 6451 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6452 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 156:ff21514d8981 6453 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 156:ff21514d8981 6454 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 6455 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 156:ff21514d8981 6456 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 156:ff21514d8981 6457 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6458 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 156:ff21514d8981 6459 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 156:ff21514d8981 6460 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6461 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 156:ff21514d8981 6462 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 156:ff21514d8981 6463 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6464 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 156:ff21514d8981 6465 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 156:ff21514d8981 6466 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6467 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 156:ff21514d8981 6468 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 156:ff21514d8981 6469 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6470 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 156:ff21514d8981 6471 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 156:ff21514d8981 6472 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6473 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 156:ff21514d8981 6474 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 156:ff21514d8981 6475 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6476 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 156:ff21514d8981 6477 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 156:ff21514d8981 6478 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 6479 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 156:ff21514d8981 6480 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 156:ff21514d8981 6481 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 6482 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 156:ff21514d8981 6483 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 156:ff21514d8981 6484 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 6485 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 156:ff21514d8981 6486
AnnaBridge 156:ff21514d8981 6487 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 156:ff21514d8981 6488 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 156:ff21514d8981 6489 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 6490 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 156:ff21514d8981 6491
AnnaBridge 156:ff21514d8981 6492 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 156:ff21514d8981 6493 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 156:ff21514d8981 6494 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 6495 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 156:ff21514d8981 6496
AnnaBridge 156:ff21514d8981 6497 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 156:ff21514d8981 6498 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 156:ff21514d8981 6499 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 6500 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 156:ff21514d8981 6501
AnnaBridge 156:ff21514d8981 6502 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 156:ff21514d8981 6503 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 156:ff21514d8981 6504 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 156:ff21514d8981 6505 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 156:ff21514d8981 6506
AnnaBridge 156:ff21514d8981 6507 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 156:ff21514d8981 6508 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 156:ff21514d8981 6509 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 6510 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 156:ff21514d8981 6511
AnnaBridge 156:ff21514d8981 6512 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 156:ff21514d8981 6513 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 156:ff21514d8981 6514 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 6515 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 156:ff21514d8981 6516
AnnaBridge 156:ff21514d8981 6517 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 156:ff21514d8981 6518 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 156:ff21514d8981 6519 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 6520 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 156:ff21514d8981 6521
AnnaBridge 156:ff21514d8981 6522 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 156:ff21514d8981 6523 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 156:ff21514d8981 6524 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 6525 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 156:ff21514d8981 6526
AnnaBridge 156:ff21514d8981 6527 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 156:ff21514d8981 6528 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 156:ff21514d8981 6529 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 156:ff21514d8981 6530 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 156:ff21514d8981 6531 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
AnnaBridge 156:ff21514d8981 6532 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
AnnaBridge 156:ff21514d8981 6533 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
AnnaBridge 156:ff21514d8981 6534 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
AnnaBridge 156:ff21514d8981 6535 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6536 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6537 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6538 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
AnnaBridge 156:ff21514d8981 6539
AnnaBridge 156:ff21514d8981 6540 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 156:ff21514d8981 6541 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 156:ff21514d8981 6542 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 156:ff21514d8981 6543 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
AnnaBridge 156:ff21514d8981 6544 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
AnnaBridge 156:ff21514d8981 6545
AnnaBridge 156:ff21514d8981 6546 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 156:ff21514d8981 6547 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6548 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 156:ff21514d8981 6549 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 156:ff21514d8981 6550 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6551 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 156:ff21514d8981 6552 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 156:ff21514d8981 6553 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 6554 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 156:ff21514d8981 6555 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 156:ff21514d8981 6556 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 6557 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 156:ff21514d8981 6558 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 156:ff21514d8981 6559 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 6560 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 156:ff21514d8981 6561 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 156:ff21514d8981 6562 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 6563 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 156:ff21514d8981 6564
AnnaBridge 156:ff21514d8981 6565 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 156:ff21514d8981 6566 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 156:ff21514d8981 6567 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 156:ff21514d8981 6568 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 156:ff21514d8981 6569 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
AnnaBridge 156:ff21514d8981 6570 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
AnnaBridge 156:ff21514d8981 6571 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
AnnaBridge 156:ff21514d8981 6572 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
AnnaBridge 156:ff21514d8981 6573 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6574
AnnaBridge 156:ff21514d8981 6575 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 156:ff21514d8981 6576 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 156:ff21514d8981 6577 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 156:ff21514d8981 6578 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
AnnaBridge 156:ff21514d8981 6579 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
AnnaBridge 156:ff21514d8981 6580 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
AnnaBridge 156:ff21514d8981 6581 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
AnnaBridge 156:ff21514d8981 6582 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
AnnaBridge 156:ff21514d8981 6583
AnnaBridge 156:ff21514d8981 6584 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 156:ff21514d8981 6585 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 156:ff21514d8981 6586 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 6587 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 156:ff21514d8981 6588
AnnaBridge 156:ff21514d8981 6589 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 156:ff21514d8981 6590 #define TIM_OR_TI1_RMP_Pos (0U)
AnnaBridge 156:ff21514d8981 6591 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 6592 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
AnnaBridge 156:ff21514d8981 6593 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6594 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6595
AnnaBridge 156:ff21514d8981 6596 #define TIM_OR_TI4_RMP_Pos (6U)
AnnaBridge 156:ff21514d8981 6597 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 156:ff21514d8981 6598 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 156:ff21514d8981 6599 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6600 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
AnnaBridge 156:ff21514d8981 6601 #define TIM_OR_ITR1_RMP_Pos (10U)
AnnaBridge 156:ff21514d8981 6602 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
AnnaBridge 156:ff21514d8981 6603 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
AnnaBridge 156:ff21514d8981 6604 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
AnnaBridge 156:ff21514d8981 6605 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
AnnaBridge 156:ff21514d8981 6606
AnnaBridge 156:ff21514d8981 6607
AnnaBridge 156:ff21514d8981 6608 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6609 /* */
AnnaBridge 156:ff21514d8981 6610 /* Universal Synchronous Asynchronous Receiver Transmitter */
AnnaBridge 156:ff21514d8981 6611 /* */
AnnaBridge 156:ff21514d8981 6612 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6613 /******************* Bit definition for USART_SR register *******************/
AnnaBridge 156:ff21514d8981 6614 #define USART_SR_PE_Pos (0U)
AnnaBridge 156:ff21514d8981 6615 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6616 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
AnnaBridge 156:ff21514d8981 6617 #define USART_SR_FE_Pos (1U)
AnnaBridge 156:ff21514d8981 6618 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6619 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
AnnaBridge 156:ff21514d8981 6620 #define USART_SR_NE_Pos (2U)
AnnaBridge 156:ff21514d8981 6621 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6622 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
AnnaBridge 156:ff21514d8981 6623 #define USART_SR_ORE_Pos (3U)
AnnaBridge 156:ff21514d8981 6624 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6625 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
AnnaBridge 156:ff21514d8981 6626 #define USART_SR_IDLE_Pos (4U)
AnnaBridge 156:ff21514d8981 6627 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 6628 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
AnnaBridge 156:ff21514d8981 6629 #define USART_SR_RXNE_Pos (5U)
AnnaBridge 156:ff21514d8981 6630 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6631 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
AnnaBridge 156:ff21514d8981 6632 #define USART_SR_TC_Pos (6U)
AnnaBridge 156:ff21514d8981 6633 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6634 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
AnnaBridge 156:ff21514d8981 6635 #define USART_SR_TXE_Pos (7U)
AnnaBridge 156:ff21514d8981 6636 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6637 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
AnnaBridge 156:ff21514d8981 6638 #define USART_SR_LBD_Pos (8U)
AnnaBridge 156:ff21514d8981 6639 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6640 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
AnnaBridge 156:ff21514d8981 6641 #define USART_SR_CTS_Pos (9U)
AnnaBridge 156:ff21514d8981 6642 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6643 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
AnnaBridge 156:ff21514d8981 6644
AnnaBridge 156:ff21514d8981 6645 /******************* Bit definition for USART_DR register *******************/
AnnaBridge 156:ff21514d8981 6646 #define USART_DR_DR_Pos (0U)
AnnaBridge 156:ff21514d8981 6647 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
AnnaBridge 156:ff21514d8981 6648 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
AnnaBridge 156:ff21514d8981 6649
AnnaBridge 156:ff21514d8981 6650 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 156:ff21514d8981 6651 #define USART_BRR_DIV_Fraction_Pos (0U)
AnnaBridge 156:ff21514d8981 6652 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 6653 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
AnnaBridge 156:ff21514d8981 6654 #define USART_BRR_DIV_Mantissa_Pos (4U)
AnnaBridge 156:ff21514d8981 6655 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
AnnaBridge 156:ff21514d8981 6656 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
AnnaBridge 156:ff21514d8981 6657
AnnaBridge 156:ff21514d8981 6658 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 156:ff21514d8981 6659 #define USART_CR1_SBK_Pos (0U)
AnnaBridge 156:ff21514d8981 6660 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6661 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
AnnaBridge 156:ff21514d8981 6662 #define USART_CR1_RWU_Pos (1U)
AnnaBridge 156:ff21514d8981 6663 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6664 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
AnnaBridge 156:ff21514d8981 6665 #define USART_CR1_RE_Pos (2U)
AnnaBridge 156:ff21514d8981 6666 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6667 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
AnnaBridge 156:ff21514d8981 6668 #define USART_CR1_TE_Pos (3U)
AnnaBridge 156:ff21514d8981 6669 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6670 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
AnnaBridge 156:ff21514d8981 6671 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 156:ff21514d8981 6672 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 6673 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
AnnaBridge 156:ff21514d8981 6674 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 156:ff21514d8981 6675 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6676 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
AnnaBridge 156:ff21514d8981 6677 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 156:ff21514d8981 6678 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6679 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
AnnaBridge 156:ff21514d8981 6680 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 156:ff21514d8981 6681 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6682 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 156:ff21514d8981 6683 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 156:ff21514d8981 6684 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6685 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 156:ff21514d8981 6686 #define USART_CR1_PS_Pos (9U)
AnnaBridge 156:ff21514d8981 6687 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6688 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
AnnaBridge 156:ff21514d8981 6689 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 156:ff21514d8981 6690 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6691 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
AnnaBridge 156:ff21514d8981 6692 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 156:ff21514d8981 6693 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6694 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
AnnaBridge 156:ff21514d8981 6695 #define USART_CR1_M_Pos (12U)
AnnaBridge 156:ff21514d8981 6696 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 6697 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
AnnaBridge 156:ff21514d8981 6698 #define USART_CR1_UE_Pos (13U)
AnnaBridge 156:ff21514d8981 6699 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 6700 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
AnnaBridge 156:ff21514d8981 6701 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 156:ff21514d8981 6702 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 6703 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
AnnaBridge 156:ff21514d8981 6704
AnnaBridge 156:ff21514d8981 6705 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 156:ff21514d8981 6706 #define USART_CR2_ADD_Pos (0U)
AnnaBridge 156:ff21514d8981 6707 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 6708 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
AnnaBridge 156:ff21514d8981 6709 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 156:ff21514d8981 6710 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6711 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
AnnaBridge 156:ff21514d8981 6712 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 156:ff21514d8981 6713 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6714 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
AnnaBridge 156:ff21514d8981 6715 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 156:ff21514d8981 6716 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6717 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
AnnaBridge 156:ff21514d8981 6718 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 156:ff21514d8981 6719 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6720 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
AnnaBridge 156:ff21514d8981 6721 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 156:ff21514d8981 6722 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6723 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 156:ff21514d8981 6724 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 156:ff21514d8981 6725 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6726 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
AnnaBridge 156:ff21514d8981 6727
AnnaBridge 156:ff21514d8981 6728 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 156:ff21514d8981 6729 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 156:ff21514d8981 6730 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
AnnaBridge 156:ff21514d8981 6731 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
AnnaBridge 156:ff21514d8981 6732 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
AnnaBridge 156:ff21514d8981 6733
AnnaBridge 156:ff21514d8981 6734 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 156:ff21514d8981 6735 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 6736 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
AnnaBridge 156:ff21514d8981 6737
AnnaBridge 156:ff21514d8981 6738 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 156:ff21514d8981 6739 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 156:ff21514d8981 6740 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6741 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 156:ff21514d8981 6742 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 156:ff21514d8981 6743 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6744 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
AnnaBridge 156:ff21514d8981 6745 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 156:ff21514d8981 6746 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6747 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
AnnaBridge 156:ff21514d8981 6748 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 156:ff21514d8981 6749 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6750 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
AnnaBridge 156:ff21514d8981 6751 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 156:ff21514d8981 6752 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 6753 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
AnnaBridge 156:ff21514d8981 6754 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 156:ff21514d8981 6755 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6756 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
AnnaBridge 156:ff21514d8981 6757 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 156:ff21514d8981 6758 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6759 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
AnnaBridge 156:ff21514d8981 6760 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 156:ff21514d8981 6761 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6762 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
AnnaBridge 156:ff21514d8981 6763 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 156:ff21514d8981 6764 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6765 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
AnnaBridge 156:ff21514d8981 6766 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 156:ff21514d8981 6767 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6768 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
AnnaBridge 156:ff21514d8981 6769 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 156:ff21514d8981 6770 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6771 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
AnnaBridge 156:ff21514d8981 6772 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 156:ff21514d8981 6773 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6774 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
AnnaBridge 156:ff21514d8981 6775
AnnaBridge 156:ff21514d8981 6776 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 156:ff21514d8981 6777 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 156:ff21514d8981 6778 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 156:ff21514d8981 6779 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
AnnaBridge 156:ff21514d8981 6780 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
AnnaBridge 156:ff21514d8981 6781 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
AnnaBridge 156:ff21514d8981 6782 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
AnnaBridge 156:ff21514d8981 6783 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
AnnaBridge 156:ff21514d8981 6784 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6785 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6786 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6787 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
AnnaBridge 156:ff21514d8981 6788
AnnaBridge 156:ff21514d8981 6789 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 156:ff21514d8981 6790 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 156:ff21514d8981 6791 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
AnnaBridge 156:ff21514d8981 6792
AnnaBridge 156:ff21514d8981 6793 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6794 /* */
AnnaBridge 156:ff21514d8981 6795 /* Window WATCHDOG */
AnnaBridge 156:ff21514d8981 6796 /* */
AnnaBridge 156:ff21514d8981 6797 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6798 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 156:ff21514d8981 6799 #define WWDG_CR_T_Pos (0U)
AnnaBridge 156:ff21514d8981 6800 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 156:ff21514d8981 6801 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 156:ff21514d8981 6802 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
AnnaBridge 156:ff21514d8981 6803 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
AnnaBridge 156:ff21514d8981 6804 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
AnnaBridge 156:ff21514d8981 6805 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
AnnaBridge 156:ff21514d8981 6806 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
AnnaBridge 156:ff21514d8981 6807 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
AnnaBridge 156:ff21514d8981 6808 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
AnnaBridge 156:ff21514d8981 6809 /* Legacy defines */
AnnaBridge 156:ff21514d8981 6810 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 156:ff21514d8981 6811 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 156:ff21514d8981 6812 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 156:ff21514d8981 6813 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 156:ff21514d8981 6814 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 156:ff21514d8981 6815 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 156:ff21514d8981 6816 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 156:ff21514d8981 6817
AnnaBridge 156:ff21514d8981 6818 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 156:ff21514d8981 6819 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6820 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 156:ff21514d8981 6821
AnnaBridge 156:ff21514d8981 6822 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 156:ff21514d8981 6823 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 156:ff21514d8981 6824 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 156:ff21514d8981 6825 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 156:ff21514d8981 6826 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
AnnaBridge 156:ff21514d8981 6827 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
AnnaBridge 156:ff21514d8981 6828 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
AnnaBridge 156:ff21514d8981 6829 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
AnnaBridge 156:ff21514d8981 6830 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
AnnaBridge 156:ff21514d8981 6831 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
AnnaBridge 156:ff21514d8981 6832 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
AnnaBridge 156:ff21514d8981 6833 /* Legacy defines */
AnnaBridge 156:ff21514d8981 6834 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 156:ff21514d8981 6835 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 156:ff21514d8981 6836 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 156:ff21514d8981 6837 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 156:ff21514d8981 6838 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 156:ff21514d8981 6839 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 156:ff21514d8981 6840 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 156:ff21514d8981 6841
AnnaBridge 156:ff21514d8981 6842 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 156:ff21514d8981 6843 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 156:ff21514d8981 6844 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 156:ff21514d8981 6845 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
AnnaBridge 156:ff21514d8981 6846 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
AnnaBridge 156:ff21514d8981 6847 /* Legacy defines */
AnnaBridge 156:ff21514d8981 6848 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 156:ff21514d8981 6849 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 156:ff21514d8981 6850
AnnaBridge 156:ff21514d8981 6851 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 156:ff21514d8981 6852 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6853 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 156:ff21514d8981 6854
AnnaBridge 156:ff21514d8981 6855 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 156:ff21514d8981 6856 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 156:ff21514d8981 6857 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6858 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 156:ff21514d8981 6859
AnnaBridge 156:ff21514d8981 6860
AnnaBridge 156:ff21514d8981 6861 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6862 /* */
AnnaBridge 156:ff21514d8981 6863 /* DBG */
AnnaBridge 156:ff21514d8981 6864 /* */
AnnaBridge 156:ff21514d8981 6865 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6866 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 156:ff21514d8981 6867 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 156:ff21514d8981 6868 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 6869 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 156:ff21514d8981 6870 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 156:ff21514d8981 6871 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 6872 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 156:ff21514d8981 6873
AnnaBridge 156:ff21514d8981 6874 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 156:ff21514d8981 6875 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 156:ff21514d8981 6876 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6877 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 156:ff21514d8981 6878 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 156:ff21514d8981 6879 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6880 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 156:ff21514d8981 6881 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 156:ff21514d8981 6882 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6883 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 156:ff21514d8981 6884 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 156:ff21514d8981 6885 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 6886 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 156:ff21514d8981 6887
AnnaBridge 156:ff21514d8981 6888 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 156:ff21514d8981 6889 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 156:ff21514d8981 6890 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 156:ff21514d8981 6891 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 6892 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 6893
AnnaBridge 156:ff21514d8981 6894 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 156:ff21514d8981 6895 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 156:ff21514d8981 6896 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6897 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
AnnaBridge 156:ff21514d8981 6898 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 156:ff21514d8981 6899 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6900 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 156:ff21514d8981 6901 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
AnnaBridge 156:ff21514d8981 6902 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6903 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
AnnaBridge 156:ff21514d8981 6904 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 156:ff21514d8981 6905 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 6906 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
AnnaBridge 156:ff21514d8981 6907 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 156:ff21514d8981 6908 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6909 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 156:ff21514d8981 6910 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 156:ff21514d8981 6911 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6912 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 156:ff21514d8981 6913 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 156:ff21514d8981 6914 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 6915 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 156:ff21514d8981 6916 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 156:ff21514d8981 6917 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 6918 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 156:ff21514d8981 6919 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 156:ff21514d8981 6920 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 6921 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
AnnaBridge 156:ff21514d8981 6922 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
AnnaBridge 156:ff21514d8981 6923 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 6924 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
AnnaBridge 156:ff21514d8981 6925 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
AnnaBridge 156:ff21514d8981 6926 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
AnnaBridge 156:ff21514d8981 6927
AnnaBridge 156:ff21514d8981 6928 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 156:ff21514d8981 6929 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 156:ff21514d8981 6930 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6931 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 156:ff21514d8981 6932 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
AnnaBridge 156:ff21514d8981 6933 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 6934 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
AnnaBridge 156:ff21514d8981 6935 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
AnnaBridge 156:ff21514d8981 6936 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 6937 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
AnnaBridge 156:ff21514d8981 6938 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
AnnaBridge 156:ff21514d8981 6939 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 6940 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
AnnaBridge 156:ff21514d8981 6941
AnnaBridge 156:ff21514d8981 6942 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6943 /* */
AnnaBridge 156:ff21514d8981 6944 /* USB_OTG */
AnnaBridge 156:ff21514d8981 6945 /* */
AnnaBridge 156:ff21514d8981 6946 /******************************************************************************/
AnnaBridge 156:ff21514d8981 6947 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
AnnaBridge 156:ff21514d8981 6948 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
AnnaBridge 156:ff21514d8981 6949 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6950 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
AnnaBridge 156:ff21514d8981 6951 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
AnnaBridge 156:ff21514d8981 6952 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6953 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
AnnaBridge 156:ff21514d8981 6954 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
AnnaBridge 156:ff21514d8981 6955 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 6956 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
AnnaBridge 156:ff21514d8981 6957 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
AnnaBridge 156:ff21514d8981 6958 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 6959 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
AnnaBridge 156:ff21514d8981 6960 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
AnnaBridge 156:ff21514d8981 6961 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 6962 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
AnnaBridge 156:ff21514d8981 6963 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
AnnaBridge 156:ff21514d8981 6964 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 6965 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
AnnaBridge 156:ff21514d8981 6966 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
AnnaBridge 156:ff21514d8981 6967 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 6968 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
AnnaBridge 156:ff21514d8981 6969 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
AnnaBridge 156:ff21514d8981 6970 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 6971 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
AnnaBridge 156:ff21514d8981 6972 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
AnnaBridge 156:ff21514d8981 6973 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 6974 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
AnnaBridge 156:ff21514d8981 6975 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
AnnaBridge 156:ff21514d8981 6976 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 6977 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
AnnaBridge 156:ff21514d8981 6978
AnnaBridge 156:ff21514d8981 6979 /******************** Bit definition forUSB_OTG_HCFG register ********************/
AnnaBridge 156:ff21514d8981 6980
AnnaBridge 156:ff21514d8981 6981 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
AnnaBridge 156:ff21514d8981 6982 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 6983 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
AnnaBridge 156:ff21514d8981 6984 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6985 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6986 #define USB_OTG_HCFG_FSLSS_Pos (2U)
AnnaBridge 156:ff21514d8981 6987 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6988 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
AnnaBridge 156:ff21514d8981 6989
AnnaBridge 156:ff21514d8981 6990 /******************** Bit definition for USB_OTG_DCFG register ********************/
AnnaBridge 156:ff21514d8981 6991
AnnaBridge 156:ff21514d8981 6992 #define USB_OTG_DCFG_DSPD_Pos (0U)
AnnaBridge 156:ff21514d8981 6993 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
AnnaBridge 156:ff21514d8981 6994 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
AnnaBridge 156:ff21514d8981 6995 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 6996 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 6997 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
AnnaBridge 156:ff21514d8981 6998 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 6999 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
AnnaBridge 156:ff21514d8981 7000
AnnaBridge 156:ff21514d8981 7001 #define USB_OTG_DCFG_DAD_Pos (4U)
AnnaBridge 156:ff21514d8981 7002 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
AnnaBridge 156:ff21514d8981 7003 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
AnnaBridge 156:ff21514d8981 7004 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7005 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7006 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7007 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7008 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7009 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7010 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7011
AnnaBridge 156:ff21514d8981 7012 #define USB_OTG_DCFG_PFIVL_Pos (11U)
AnnaBridge 156:ff21514d8981 7013 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
AnnaBridge 156:ff21514d8981 7014 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
AnnaBridge 156:ff21514d8981 7015 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 7016 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 7017
AnnaBridge 156:ff21514d8981 7018 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
AnnaBridge 156:ff21514d8981 7019 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
AnnaBridge 156:ff21514d8981 7020 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
AnnaBridge 156:ff21514d8981 7021 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7022 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7023
AnnaBridge 156:ff21514d8981 7024 /******************** Bit definition for USB_OTG_PCGCR register ********************/
AnnaBridge 156:ff21514d8981 7025 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
AnnaBridge 156:ff21514d8981 7026 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7027 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
AnnaBridge 156:ff21514d8981 7028 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
AnnaBridge 156:ff21514d8981 7029 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7030 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
AnnaBridge 156:ff21514d8981 7031 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
AnnaBridge 156:ff21514d8981 7032 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7033 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
AnnaBridge 156:ff21514d8981 7034
AnnaBridge 156:ff21514d8981 7035 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
AnnaBridge 156:ff21514d8981 7036 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
AnnaBridge 156:ff21514d8981 7037 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7038 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
AnnaBridge 156:ff21514d8981 7039 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
AnnaBridge 156:ff21514d8981 7040 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7041 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
AnnaBridge 156:ff21514d8981 7042 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
AnnaBridge 156:ff21514d8981 7043 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7044 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
AnnaBridge 156:ff21514d8981 7045 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
AnnaBridge 156:ff21514d8981 7046 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7047 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
AnnaBridge 156:ff21514d8981 7048 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
AnnaBridge 156:ff21514d8981 7049 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7050 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
AnnaBridge 156:ff21514d8981 7051 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
AnnaBridge 156:ff21514d8981 7052 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7053 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
AnnaBridge 156:ff21514d8981 7054
AnnaBridge 156:ff21514d8981 7055 /******************** Bit definition for USB_OTG_DCTL register ********************/
AnnaBridge 156:ff21514d8981 7056 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
AnnaBridge 156:ff21514d8981 7057 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7058 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
AnnaBridge 156:ff21514d8981 7059 #define USB_OTG_DCTL_SDIS_Pos (1U)
AnnaBridge 156:ff21514d8981 7060 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7061 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
AnnaBridge 156:ff21514d8981 7062 #define USB_OTG_DCTL_GINSTS_Pos (2U)
AnnaBridge 156:ff21514d8981 7063 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7064 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
AnnaBridge 156:ff21514d8981 7065 #define USB_OTG_DCTL_GONSTS_Pos (3U)
AnnaBridge 156:ff21514d8981 7066 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7067 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
AnnaBridge 156:ff21514d8981 7068
AnnaBridge 156:ff21514d8981 7069 #define USB_OTG_DCTL_TCTL_Pos (4U)
AnnaBridge 156:ff21514d8981 7070 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
AnnaBridge 156:ff21514d8981 7071 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
AnnaBridge 156:ff21514d8981 7072 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7073 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7074 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7075 #define USB_OTG_DCTL_SGINAK_Pos (7U)
AnnaBridge 156:ff21514d8981 7076 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7077 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
AnnaBridge 156:ff21514d8981 7078 #define USB_OTG_DCTL_CGINAK_Pos (8U)
AnnaBridge 156:ff21514d8981 7079 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7080 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
AnnaBridge 156:ff21514d8981 7081 #define USB_OTG_DCTL_SGONAK_Pos (9U)
AnnaBridge 156:ff21514d8981 7082 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7083 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
AnnaBridge 156:ff21514d8981 7084 #define USB_OTG_DCTL_CGONAK_Pos (10U)
AnnaBridge 156:ff21514d8981 7085 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7086 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
AnnaBridge 156:ff21514d8981 7087 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
AnnaBridge 156:ff21514d8981 7088 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 7089 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
AnnaBridge 156:ff21514d8981 7090
AnnaBridge 156:ff21514d8981 7091 /******************** Bit definition for USB_OTG_HFIR register ********************/
AnnaBridge 156:ff21514d8981 7092 #define USB_OTG_HFIR_FRIVL_Pos (0U)
AnnaBridge 156:ff21514d8981 7093 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7094 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
AnnaBridge 156:ff21514d8981 7095
AnnaBridge 156:ff21514d8981 7096 /******************** Bit definition for USB_OTG_HFNUM register ********************/
AnnaBridge 156:ff21514d8981 7097 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
AnnaBridge 156:ff21514d8981 7098 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7099 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
AnnaBridge 156:ff21514d8981 7100 #define USB_OTG_HFNUM_FTREM_Pos (16U)
AnnaBridge 156:ff21514d8981 7101 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 7102 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
AnnaBridge 156:ff21514d8981 7103
AnnaBridge 156:ff21514d8981 7104 /******************** Bit definition for USB_OTG_DSTS register ********************/
AnnaBridge 156:ff21514d8981 7105 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
AnnaBridge 156:ff21514d8981 7106 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7107 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
AnnaBridge 156:ff21514d8981 7108
AnnaBridge 156:ff21514d8981 7109 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
AnnaBridge 156:ff21514d8981 7110 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
AnnaBridge 156:ff21514d8981 7111 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
AnnaBridge 156:ff21514d8981 7112 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7113 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7114 #define USB_OTG_DSTS_EERR_Pos (3U)
AnnaBridge 156:ff21514d8981 7115 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7116 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
AnnaBridge 156:ff21514d8981 7117 #define USB_OTG_DSTS_FNSOF_Pos (8U)
AnnaBridge 156:ff21514d8981 7118 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
AnnaBridge 156:ff21514d8981 7119 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
AnnaBridge 156:ff21514d8981 7120
AnnaBridge 156:ff21514d8981 7121 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
AnnaBridge 156:ff21514d8981 7122 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
AnnaBridge 156:ff21514d8981 7123 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7124 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
AnnaBridge 156:ff21514d8981 7125 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
AnnaBridge 156:ff21514d8981 7126 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
AnnaBridge 156:ff21514d8981 7127 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
AnnaBridge 156:ff21514d8981 7128 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
AnnaBridge 156:ff21514d8981 7129 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
AnnaBridge 156:ff21514d8981 7130 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
AnnaBridge 156:ff21514d8981 7131 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
AnnaBridge 156:ff21514d8981 7132 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
AnnaBridge 156:ff21514d8981 7133 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
AnnaBridge 156:ff21514d8981 7134 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7135 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
AnnaBridge 156:ff21514d8981 7136 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
AnnaBridge 156:ff21514d8981 7137 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7138 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
AnnaBridge 156:ff21514d8981 7139 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
AnnaBridge 156:ff21514d8981 7140 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7141 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
AnnaBridge 156:ff21514d8981 7142
AnnaBridge 156:ff21514d8981 7143 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
AnnaBridge 156:ff21514d8981 7144
AnnaBridge 156:ff21514d8981 7145 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
AnnaBridge 156:ff21514d8981 7146 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
AnnaBridge 156:ff21514d8981 7147 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
AnnaBridge 156:ff21514d8981 7148 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7149 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7150 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7151 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
AnnaBridge 156:ff21514d8981 7152 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7153 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 156:ff21514d8981 7154 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
AnnaBridge 156:ff21514d8981 7155 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7156 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
AnnaBridge 156:ff21514d8981 7157 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
AnnaBridge 156:ff21514d8981 7158 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7159 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
AnnaBridge 156:ff21514d8981 7160 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
AnnaBridge 156:ff21514d8981 7161 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
AnnaBridge 156:ff21514d8981 7162 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
AnnaBridge 156:ff21514d8981 7163 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7164 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 7165 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 7166 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 7167 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
AnnaBridge 156:ff21514d8981 7168 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7169 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
AnnaBridge 156:ff21514d8981 7170 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
AnnaBridge 156:ff21514d8981 7171 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7172 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
AnnaBridge 156:ff21514d8981 7173 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
AnnaBridge 156:ff21514d8981 7174 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7175 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
AnnaBridge 156:ff21514d8981 7176 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
AnnaBridge 156:ff21514d8981 7177 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7178 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
AnnaBridge 156:ff21514d8981 7179 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
AnnaBridge 156:ff21514d8981 7180 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7181 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
AnnaBridge 156:ff21514d8981 7182 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
AnnaBridge 156:ff21514d8981 7183 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7184 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
AnnaBridge 156:ff21514d8981 7185 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
AnnaBridge 156:ff21514d8981 7186 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7187 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
AnnaBridge 156:ff21514d8981 7188 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
AnnaBridge 156:ff21514d8981 7189 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 7190 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
AnnaBridge 156:ff21514d8981 7191 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
AnnaBridge 156:ff21514d8981 7192 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7193 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
AnnaBridge 156:ff21514d8981 7194 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
AnnaBridge 156:ff21514d8981 7195 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7196 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
AnnaBridge 156:ff21514d8981 7197 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
AnnaBridge 156:ff21514d8981 7198 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 7199 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
AnnaBridge 156:ff21514d8981 7200 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
AnnaBridge 156:ff21514d8981 7201 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 7202 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
AnnaBridge 156:ff21514d8981 7203 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
AnnaBridge 156:ff21514d8981 7204 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 7205 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
AnnaBridge 156:ff21514d8981 7206
AnnaBridge 156:ff21514d8981 7207 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
AnnaBridge 156:ff21514d8981 7208 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
AnnaBridge 156:ff21514d8981 7209 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7210 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
AnnaBridge 156:ff21514d8981 7211 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
AnnaBridge 156:ff21514d8981 7212 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7213 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
AnnaBridge 156:ff21514d8981 7214 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
AnnaBridge 156:ff21514d8981 7215 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7216 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
AnnaBridge 156:ff21514d8981 7217 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
AnnaBridge 156:ff21514d8981 7218 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7219 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
AnnaBridge 156:ff21514d8981 7220 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
AnnaBridge 156:ff21514d8981 7221 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7222 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
AnnaBridge 156:ff21514d8981 7223
AnnaBridge 156:ff21514d8981 7224
AnnaBridge 156:ff21514d8981 7225 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
AnnaBridge 156:ff21514d8981 7226 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
AnnaBridge 156:ff21514d8981 7227 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 156:ff21514d8981 7228 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7229 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7230 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7231 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7232 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7233 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
AnnaBridge 156:ff21514d8981 7234 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 7235 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
AnnaBridge 156:ff21514d8981 7236 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
AnnaBridge 156:ff21514d8981 7237 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 7238 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
AnnaBridge 156:ff21514d8981 7239
AnnaBridge 156:ff21514d8981 7240 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
AnnaBridge 156:ff21514d8981 7241 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
AnnaBridge 156:ff21514d8981 7242 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7243 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 156:ff21514d8981 7244 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
AnnaBridge 156:ff21514d8981 7245 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7246 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 156:ff21514d8981 7247 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
AnnaBridge 156:ff21514d8981 7248 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7249 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 156:ff21514d8981 7250 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
AnnaBridge 156:ff21514d8981 7251 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7252 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 156:ff21514d8981 7253 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
AnnaBridge 156:ff21514d8981 7254 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7255 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 156:ff21514d8981 7256 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
AnnaBridge 156:ff21514d8981 7257 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7258 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 156:ff21514d8981 7259 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
AnnaBridge 156:ff21514d8981 7260 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7261 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 156:ff21514d8981 7262 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
AnnaBridge 156:ff21514d8981 7263 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7264 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 156:ff21514d8981 7265
AnnaBridge 156:ff21514d8981 7266 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
AnnaBridge 156:ff21514d8981 7267 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
AnnaBridge 156:ff21514d8981 7268 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7269 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
AnnaBridge 156:ff21514d8981 7270 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
AnnaBridge 156:ff21514d8981 7271 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 156:ff21514d8981 7272 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
AnnaBridge 156:ff21514d8981 7273 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 7274 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7275 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7276 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7277 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7278 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7279 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7280 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 7281
AnnaBridge 156:ff21514d8981 7282 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
AnnaBridge 156:ff21514d8981 7283 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
AnnaBridge 156:ff21514d8981 7284 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
AnnaBridge 156:ff21514d8981 7285 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7286 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7287 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 7288 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 7289 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 7290 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 7291 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 7292 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 7293
AnnaBridge 156:ff21514d8981 7294 /******************** Bit definition for USB_OTG_HAINT register ********************/
AnnaBridge 156:ff21514d8981 7295 #define USB_OTG_HAINT_HAINT_Pos (0U)
AnnaBridge 156:ff21514d8981 7296 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7297 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
AnnaBridge 156:ff21514d8981 7298
AnnaBridge 156:ff21514d8981 7299 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
AnnaBridge 156:ff21514d8981 7300 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
AnnaBridge 156:ff21514d8981 7301 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7302 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 156:ff21514d8981 7303 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
AnnaBridge 156:ff21514d8981 7304 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7305 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 156:ff21514d8981 7306 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
AnnaBridge 156:ff21514d8981 7307 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7308 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
AnnaBridge 156:ff21514d8981 7309 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
AnnaBridge 156:ff21514d8981 7310 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7311 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
AnnaBridge 156:ff21514d8981 7312 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
AnnaBridge 156:ff21514d8981 7313 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7314 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
AnnaBridge 156:ff21514d8981 7315 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
AnnaBridge 156:ff21514d8981 7316 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7317 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
AnnaBridge 156:ff21514d8981 7318 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
AnnaBridge 156:ff21514d8981 7319 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7320 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
AnnaBridge 156:ff21514d8981 7321
AnnaBridge 156:ff21514d8981 7322 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
AnnaBridge 156:ff21514d8981 7323 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
AnnaBridge 156:ff21514d8981 7324 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7325 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
AnnaBridge 156:ff21514d8981 7326 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
AnnaBridge 156:ff21514d8981 7327 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7328 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
AnnaBridge 156:ff21514d8981 7329 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
AnnaBridge 156:ff21514d8981 7330 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7331 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
AnnaBridge 156:ff21514d8981 7332 #define USB_OTG_GINTSTS_SOF_Pos (3U)
AnnaBridge 156:ff21514d8981 7333 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7334 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
AnnaBridge 156:ff21514d8981 7335 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
AnnaBridge 156:ff21514d8981 7336 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7337 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
AnnaBridge 156:ff21514d8981 7338 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
AnnaBridge 156:ff21514d8981 7339 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7340 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
AnnaBridge 156:ff21514d8981 7341 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
AnnaBridge 156:ff21514d8981 7342 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7343 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
AnnaBridge 156:ff21514d8981 7344 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
AnnaBridge 156:ff21514d8981 7345 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7346 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
AnnaBridge 156:ff21514d8981 7347 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
AnnaBridge 156:ff21514d8981 7348 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7349 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
AnnaBridge 156:ff21514d8981 7350 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
AnnaBridge 156:ff21514d8981 7351 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 7352 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
AnnaBridge 156:ff21514d8981 7353 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
AnnaBridge 156:ff21514d8981 7354 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 7355 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
AnnaBridge 156:ff21514d8981 7356 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
AnnaBridge 156:ff21514d8981 7357 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 7358 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
AnnaBridge 156:ff21514d8981 7359 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
AnnaBridge 156:ff21514d8981 7360 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 7361 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 156:ff21514d8981 7362 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
AnnaBridge 156:ff21514d8981 7363 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7364 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
AnnaBridge 156:ff21514d8981 7365 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
AnnaBridge 156:ff21514d8981 7366 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7367 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
AnnaBridge 156:ff21514d8981 7368 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
AnnaBridge 156:ff21514d8981 7369 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7370 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
AnnaBridge 156:ff21514d8981 7371 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
AnnaBridge 156:ff21514d8981 7372 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7373 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
AnnaBridge 156:ff21514d8981 7374 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
AnnaBridge 156:ff21514d8981 7375 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7376 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
AnnaBridge 156:ff21514d8981 7377 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
AnnaBridge 156:ff21514d8981 7378 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7379 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
AnnaBridge 156:ff21514d8981 7380 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
AnnaBridge 156:ff21514d8981 7381 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7382 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
AnnaBridge 156:ff21514d8981 7383 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
AnnaBridge 156:ff21514d8981 7384 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7385 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
AnnaBridge 156:ff21514d8981 7386 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
AnnaBridge 156:ff21514d8981 7387 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 7388 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
AnnaBridge 156:ff21514d8981 7389 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
AnnaBridge 156:ff21514d8981 7390 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 7391 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
AnnaBridge 156:ff21514d8981 7392 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
AnnaBridge 156:ff21514d8981 7393 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 7394 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
AnnaBridge 156:ff21514d8981 7395 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
AnnaBridge 156:ff21514d8981 7396 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 7397 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
AnnaBridge 156:ff21514d8981 7398 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
AnnaBridge 156:ff21514d8981 7399 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 7400 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 156:ff21514d8981 7401
AnnaBridge 156:ff21514d8981 7402 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
AnnaBridge 156:ff21514d8981 7403 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
AnnaBridge 156:ff21514d8981 7404 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7405 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
AnnaBridge 156:ff21514d8981 7406 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
AnnaBridge 156:ff21514d8981 7407 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7408 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
AnnaBridge 156:ff21514d8981 7409 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
AnnaBridge 156:ff21514d8981 7410 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7411 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
AnnaBridge 156:ff21514d8981 7412 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
AnnaBridge 156:ff21514d8981 7413 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7414 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
AnnaBridge 156:ff21514d8981 7415 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
AnnaBridge 156:ff21514d8981 7416 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7417 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 156:ff21514d8981 7418 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
AnnaBridge 156:ff21514d8981 7419 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7420 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 156:ff21514d8981 7421 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
AnnaBridge 156:ff21514d8981 7422 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7423 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
AnnaBridge 156:ff21514d8981 7424 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
AnnaBridge 156:ff21514d8981 7425 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7426 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
AnnaBridge 156:ff21514d8981 7427 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
AnnaBridge 156:ff21514d8981 7428 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 7429 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
AnnaBridge 156:ff21514d8981 7430 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
AnnaBridge 156:ff21514d8981 7431 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 7432 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
AnnaBridge 156:ff21514d8981 7433 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
AnnaBridge 156:ff21514d8981 7434 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 7435 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
AnnaBridge 156:ff21514d8981 7436 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
AnnaBridge 156:ff21514d8981 7437 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 7438 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 156:ff21514d8981 7439 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
AnnaBridge 156:ff21514d8981 7440 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7441 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
AnnaBridge 156:ff21514d8981 7442 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
AnnaBridge 156:ff21514d8981 7443 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7444 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
AnnaBridge 156:ff21514d8981 7445 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
AnnaBridge 156:ff21514d8981 7446 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7447 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
AnnaBridge 156:ff21514d8981 7448 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
AnnaBridge 156:ff21514d8981 7449 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7450 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
AnnaBridge 156:ff21514d8981 7451 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
AnnaBridge 156:ff21514d8981 7452 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7453 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 156:ff21514d8981 7454 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
AnnaBridge 156:ff21514d8981 7455 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7456 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
AnnaBridge 156:ff21514d8981 7457 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
AnnaBridge 156:ff21514d8981 7458 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7459 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
AnnaBridge 156:ff21514d8981 7460 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
AnnaBridge 156:ff21514d8981 7461 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7462 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
AnnaBridge 156:ff21514d8981 7463 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
AnnaBridge 156:ff21514d8981 7464 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7465 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
AnnaBridge 156:ff21514d8981 7466 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
AnnaBridge 156:ff21514d8981 7467 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 7468 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
AnnaBridge 156:ff21514d8981 7469 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
AnnaBridge 156:ff21514d8981 7470 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 7471 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
AnnaBridge 156:ff21514d8981 7472 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
AnnaBridge 156:ff21514d8981 7473 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 7474 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
AnnaBridge 156:ff21514d8981 7475 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
AnnaBridge 156:ff21514d8981 7476 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 7477 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
AnnaBridge 156:ff21514d8981 7478 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
AnnaBridge 156:ff21514d8981 7479 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 7480 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 156:ff21514d8981 7481
AnnaBridge 156:ff21514d8981 7482 /******************** Bit definition for USB_OTG_DAINT register ********************/
AnnaBridge 156:ff21514d8981 7483 #define USB_OTG_DAINT_IEPINT_Pos (0U)
AnnaBridge 156:ff21514d8981 7484 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7485 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
AnnaBridge 156:ff21514d8981 7486 #define USB_OTG_DAINT_OEPINT_Pos (16U)
AnnaBridge 156:ff21514d8981 7487 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 7488 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
AnnaBridge 156:ff21514d8981 7489
AnnaBridge 156:ff21514d8981 7490 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
AnnaBridge 156:ff21514d8981 7491 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
AnnaBridge 156:ff21514d8981 7492 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7493 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
AnnaBridge 156:ff21514d8981 7494
AnnaBridge 156:ff21514d8981 7495 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 156:ff21514d8981 7496 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
AnnaBridge 156:ff21514d8981 7497 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 7498 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 156:ff21514d8981 7499 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
AnnaBridge 156:ff21514d8981 7500 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 156:ff21514d8981 7501 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 156:ff21514d8981 7502 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
AnnaBridge 156:ff21514d8981 7503 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 156:ff21514d8981 7504 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 156:ff21514d8981 7505 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
AnnaBridge 156:ff21514d8981 7506 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 156:ff21514d8981 7507 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 156:ff21514d8981 7508
AnnaBridge 156:ff21514d8981 7509 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
AnnaBridge 156:ff21514d8981 7510 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
AnnaBridge 156:ff21514d8981 7511 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7512 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 156:ff21514d8981 7513 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
AnnaBridge 156:ff21514d8981 7514 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 7515 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 156:ff21514d8981 7516
AnnaBridge 156:ff21514d8981 7517 /******************** Bit definition for OTG register ********************/
AnnaBridge 156:ff21514d8981 7518
AnnaBridge 156:ff21514d8981 7519 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 156:ff21514d8981 7520 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 7521 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 156:ff21514d8981 7522 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7523 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7524 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7525 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7526 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 156:ff21514d8981 7527 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 156:ff21514d8981 7528 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 156:ff21514d8981 7529
AnnaBridge 156:ff21514d8981 7530 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 156:ff21514d8981 7531 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 156:ff21514d8981 7532 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 156:ff21514d8981 7533 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7534 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 7535
AnnaBridge 156:ff21514d8981 7536 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 156:ff21514d8981 7537 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 156:ff21514d8981 7538 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 156:ff21514d8981 7539 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7540 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7541 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7542 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7543
AnnaBridge 156:ff21514d8981 7544 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 156:ff21514d8981 7545 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 7546 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 156:ff21514d8981 7547 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7548 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7549 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7550 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7551
AnnaBridge 156:ff21514d8981 7552 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 156:ff21514d8981 7553 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 156:ff21514d8981 7554 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 156:ff21514d8981 7555 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7556 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7557 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 7558 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7559
AnnaBridge 156:ff21514d8981 7560 /******************** Bit definition for OTG register ********************/
AnnaBridge 156:ff21514d8981 7561
AnnaBridge 156:ff21514d8981 7562 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 156:ff21514d8981 7563 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 7564 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 156:ff21514d8981 7565 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7566 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7567 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7568 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7569 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 156:ff21514d8981 7570 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 156:ff21514d8981 7571 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 156:ff21514d8981 7572
AnnaBridge 156:ff21514d8981 7573 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 156:ff21514d8981 7574 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 156:ff21514d8981 7575 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 156:ff21514d8981 7576 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7577 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 7578
AnnaBridge 156:ff21514d8981 7579 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 156:ff21514d8981 7580 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 156:ff21514d8981 7581 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 156:ff21514d8981 7582 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7583 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7584 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7585 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7586
AnnaBridge 156:ff21514d8981 7587 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 156:ff21514d8981 7588 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 156:ff21514d8981 7589 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 156:ff21514d8981 7590 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7591 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7592 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7593 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7594
AnnaBridge 156:ff21514d8981 7595 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 156:ff21514d8981 7596 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 156:ff21514d8981 7597 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 156:ff21514d8981 7598 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7599 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7600 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 7601 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7602
AnnaBridge 156:ff21514d8981 7603 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
AnnaBridge 156:ff21514d8981 7604 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
AnnaBridge 156:ff21514d8981 7605 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7606 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
AnnaBridge 156:ff21514d8981 7607
AnnaBridge 156:ff21514d8981 7608 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
AnnaBridge 156:ff21514d8981 7609 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
AnnaBridge 156:ff21514d8981 7610 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7611 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
AnnaBridge 156:ff21514d8981 7612
AnnaBridge 156:ff21514d8981 7613 /******************** Bit definition for OTG register ********************/
AnnaBridge 156:ff21514d8981 7614 #define USB_OTG_NPTXFSA_Pos (0U)
AnnaBridge 156:ff21514d8981 7615 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7616 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
AnnaBridge 156:ff21514d8981 7617 #define USB_OTG_NPTXFD_Pos (16U)
AnnaBridge 156:ff21514d8981 7618 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 7619 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
AnnaBridge 156:ff21514d8981 7620 #define USB_OTG_TX0FSA_Pos (0U)
AnnaBridge 156:ff21514d8981 7621 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7622 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 156:ff21514d8981 7623 #define USB_OTG_TX0FD_Pos (16U)
AnnaBridge 156:ff21514d8981 7624 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 7625 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
AnnaBridge 156:ff21514d8981 7626
AnnaBridge 156:ff21514d8981 7627 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
AnnaBridge 156:ff21514d8981 7628 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
AnnaBridge 156:ff21514d8981 7629 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
AnnaBridge 156:ff21514d8981 7630 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
AnnaBridge 156:ff21514d8981 7631
AnnaBridge 156:ff21514d8981 7632 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
AnnaBridge 156:ff21514d8981 7633 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
AnnaBridge 156:ff21514d8981 7634 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7635 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
AnnaBridge 156:ff21514d8981 7636
AnnaBridge 156:ff21514d8981 7637 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
AnnaBridge 156:ff21514d8981 7638 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 156:ff21514d8981 7639 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
AnnaBridge 156:ff21514d8981 7640 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 7641 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7642 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7643 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7644 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7645 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7646 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7647 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 7648
AnnaBridge 156:ff21514d8981 7649 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
AnnaBridge 156:ff21514d8981 7650 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
AnnaBridge 156:ff21514d8981 7651 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 156:ff21514d8981 7652 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7653 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7654 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 7655 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 7656 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 7657 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 7658 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 7659
AnnaBridge 156:ff21514d8981 7660 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
AnnaBridge 156:ff21514d8981 7661 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
AnnaBridge 156:ff21514d8981 7662 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7663 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 156:ff21514d8981 7664 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
AnnaBridge 156:ff21514d8981 7665 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7666 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
AnnaBridge 156:ff21514d8981 7667
AnnaBridge 156:ff21514d8981 7668 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
AnnaBridge 156:ff21514d8981 7669 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
AnnaBridge 156:ff21514d8981 7670 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
AnnaBridge 156:ff21514d8981 7671 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7672 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7673 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7674 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7675 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7676 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7677 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7678 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7679 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7680 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
AnnaBridge 156:ff21514d8981 7681 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 7682 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
AnnaBridge 156:ff21514d8981 7683
AnnaBridge 156:ff21514d8981 7684 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
AnnaBridge 156:ff21514d8981 7685 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
AnnaBridge 156:ff21514d8981 7686 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
AnnaBridge 156:ff21514d8981 7687 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7688 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7689 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7690 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7691 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7692 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7693 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 7694 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7695 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7696 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
AnnaBridge 156:ff21514d8981 7697 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 7698 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
AnnaBridge 156:ff21514d8981 7699
AnnaBridge 156:ff21514d8981 7700 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 156:ff21514d8981 7701 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
AnnaBridge 156:ff21514d8981 7702 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7703 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 156:ff21514d8981 7704
AnnaBridge 156:ff21514d8981 7705 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
AnnaBridge 156:ff21514d8981 7706 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
AnnaBridge 156:ff21514d8981 7707 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7708 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
AnnaBridge 156:ff21514d8981 7709 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
AnnaBridge 156:ff21514d8981 7710 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7711 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 156:ff21514d8981 7712
AnnaBridge 156:ff21514d8981 7713 /******************** Bit definition for USB_OTG_GCCFG register ********************/
AnnaBridge 156:ff21514d8981 7714 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
AnnaBridge 156:ff21514d8981 7715 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 7716 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
AnnaBridge 156:ff21514d8981 7717 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
AnnaBridge 156:ff21514d8981 7718 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7719 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
AnnaBridge 156:ff21514d8981 7720 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
AnnaBridge 156:ff21514d8981 7721 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7722 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 156:ff21514d8981 7723 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
AnnaBridge 156:ff21514d8981 7724 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7725 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 156:ff21514d8981 7726 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
AnnaBridge 156:ff21514d8981 7727 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7728 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
AnnaBridge 156:ff21514d8981 7729 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
AnnaBridge 156:ff21514d8981 7730 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7731 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
AnnaBridge 156:ff21514d8981 7732
AnnaBridge 156:ff21514d8981 7733 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
AnnaBridge 156:ff21514d8981 7734 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
AnnaBridge 156:ff21514d8981 7735 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7736 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 156:ff21514d8981 7737 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
AnnaBridge 156:ff21514d8981 7738 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7739 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 156:ff21514d8981 7740
AnnaBridge 156:ff21514d8981 7741 /******************** Bit definition for USB_OTG_CID register ********************/
AnnaBridge 156:ff21514d8981 7742 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
AnnaBridge 156:ff21514d8981 7743 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 7744 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
AnnaBridge 156:ff21514d8981 7745
AnnaBridge 156:ff21514d8981 7746 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 156:ff21514d8981 7747 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 156:ff21514d8981 7748 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7749 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 156:ff21514d8981 7750 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 156:ff21514d8981 7751 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7752 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 156:ff21514d8981 7753 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 156:ff21514d8981 7754 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7755 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 156:ff21514d8981 7756 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 156:ff21514d8981 7757 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7758 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 156:ff21514d8981 7759 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 156:ff21514d8981 7760 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7761 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 156:ff21514d8981 7762 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 156:ff21514d8981 7763 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7764 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 156:ff21514d8981 7765 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 156:ff21514d8981 7766 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7767 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 156:ff21514d8981 7768 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 156:ff21514d8981 7769 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7770 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 156:ff21514d8981 7771 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 156:ff21514d8981 7772 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 7773 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 156:ff21514d8981 7774
AnnaBridge 156:ff21514d8981 7775 /******************** Bit definition for USB_OTG_HPRT register ********************/
AnnaBridge 156:ff21514d8981 7776 #define USB_OTG_HPRT_PCSTS_Pos (0U)
AnnaBridge 156:ff21514d8981 7777 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7778 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
AnnaBridge 156:ff21514d8981 7779 #define USB_OTG_HPRT_PCDET_Pos (1U)
AnnaBridge 156:ff21514d8981 7780 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7781 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
AnnaBridge 156:ff21514d8981 7782 #define USB_OTG_HPRT_PENA_Pos (2U)
AnnaBridge 156:ff21514d8981 7783 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7784 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
AnnaBridge 156:ff21514d8981 7785 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
AnnaBridge 156:ff21514d8981 7786 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7787 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
AnnaBridge 156:ff21514d8981 7788 #define USB_OTG_HPRT_POCA_Pos (4U)
AnnaBridge 156:ff21514d8981 7789 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7790 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
AnnaBridge 156:ff21514d8981 7791 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
AnnaBridge 156:ff21514d8981 7792 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7793 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
AnnaBridge 156:ff21514d8981 7794 #define USB_OTG_HPRT_PRES_Pos (6U)
AnnaBridge 156:ff21514d8981 7795 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7796 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
AnnaBridge 156:ff21514d8981 7797 #define USB_OTG_HPRT_PSUSP_Pos (7U)
AnnaBridge 156:ff21514d8981 7798 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7799 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
AnnaBridge 156:ff21514d8981 7800 #define USB_OTG_HPRT_PRST_Pos (8U)
AnnaBridge 156:ff21514d8981 7801 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7802 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
AnnaBridge 156:ff21514d8981 7803
AnnaBridge 156:ff21514d8981 7804 #define USB_OTG_HPRT_PLSTS_Pos (10U)
AnnaBridge 156:ff21514d8981 7805 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
AnnaBridge 156:ff21514d8981 7806 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
AnnaBridge 156:ff21514d8981 7807 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7808 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 7809 #define USB_OTG_HPRT_PPWR_Pos (12U)
AnnaBridge 156:ff21514d8981 7810 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 7811 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
AnnaBridge 156:ff21514d8981 7812
AnnaBridge 156:ff21514d8981 7813 #define USB_OTG_HPRT_PTCTL_Pos (13U)
AnnaBridge 156:ff21514d8981 7814 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
AnnaBridge 156:ff21514d8981 7815 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
AnnaBridge 156:ff21514d8981 7816 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 7817 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 7818 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7819 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 7820
AnnaBridge 156:ff21514d8981 7821 #define USB_OTG_HPRT_PSPD_Pos (17U)
AnnaBridge 156:ff21514d8981 7822 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
AnnaBridge 156:ff21514d8981 7823 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
AnnaBridge 156:ff21514d8981 7824 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7825 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7826
AnnaBridge 156:ff21514d8981 7827 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 156:ff21514d8981 7828 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 156:ff21514d8981 7829 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7830 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 156:ff21514d8981 7831 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 156:ff21514d8981 7832 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7833 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 156:ff21514d8981 7834 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 156:ff21514d8981 7835 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7836 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
AnnaBridge 156:ff21514d8981 7837 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 156:ff21514d8981 7838 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7839 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 156:ff21514d8981 7840 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 156:ff21514d8981 7841 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7842 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 156:ff21514d8981 7843 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 156:ff21514d8981 7844 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7845 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 156:ff21514d8981 7846 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 156:ff21514d8981 7847 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7848 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
AnnaBridge 156:ff21514d8981 7849 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 156:ff21514d8981 7850 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7851 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 156:ff21514d8981 7852 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
AnnaBridge 156:ff21514d8981 7853 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 7854 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
AnnaBridge 156:ff21514d8981 7855 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 156:ff21514d8981 7856 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 7857 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 156:ff21514d8981 7858 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
AnnaBridge 156:ff21514d8981 7859 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 7860 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
AnnaBridge 156:ff21514d8981 7861
AnnaBridge 156:ff21514d8981 7862 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
AnnaBridge 156:ff21514d8981 7863 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
AnnaBridge 156:ff21514d8981 7864 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 7865 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
AnnaBridge 156:ff21514d8981 7866 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
AnnaBridge 156:ff21514d8981 7867 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 7868 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
AnnaBridge 156:ff21514d8981 7869
AnnaBridge 156:ff21514d8981 7870 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
AnnaBridge 156:ff21514d8981 7871 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
AnnaBridge 156:ff21514d8981 7872 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 156:ff21514d8981 7873 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 156:ff21514d8981 7874 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
AnnaBridge 156:ff21514d8981 7875 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7876 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 156:ff21514d8981 7877 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
AnnaBridge 156:ff21514d8981 7878 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 7879 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
AnnaBridge 156:ff21514d8981 7880 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
AnnaBridge 156:ff21514d8981 7881 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7882 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 156:ff21514d8981 7883
AnnaBridge 156:ff21514d8981 7884 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
AnnaBridge 156:ff21514d8981 7885 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 156:ff21514d8981 7886 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 156:ff21514d8981 7887 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7888 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7889 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
AnnaBridge 156:ff21514d8981 7890 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7891 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 156:ff21514d8981 7892
AnnaBridge 156:ff21514d8981 7893 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
AnnaBridge 156:ff21514d8981 7894 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
AnnaBridge 156:ff21514d8981 7895 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 156:ff21514d8981 7896 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7897 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 7898 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7899 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7900 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
AnnaBridge 156:ff21514d8981 7901 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 7902 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 156:ff21514d8981 7903 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
AnnaBridge 156:ff21514d8981 7904 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 7905 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 156:ff21514d8981 7906 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 156:ff21514d8981 7907 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 7908 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 156:ff21514d8981 7909 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
AnnaBridge 156:ff21514d8981 7910 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 7911 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 156:ff21514d8981 7912 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
AnnaBridge 156:ff21514d8981 7913 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 7914 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 156:ff21514d8981 7915 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
AnnaBridge 156:ff21514d8981 7916 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 7917 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 156:ff21514d8981 7918
AnnaBridge 156:ff21514d8981 7919 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
AnnaBridge 156:ff21514d8981 7920 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
AnnaBridge 156:ff21514d8981 7921 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 156:ff21514d8981 7922 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 156:ff21514d8981 7923
AnnaBridge 156:ff21514d8981 7924 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
AnnaBridge 156:ff21514d8981 7925 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
AnnaBridge 156:ff21514d8981 7926 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 156:ff21514d8981 7927 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 7928 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 7929 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 7930 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 7931 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
AnnaBridge 156:ff21514d8981 7932 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7933 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
AnnaBridge 156:ff21514d8981 7934 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
AnnaBridge 156:ff21514d8981 7935 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 7936 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
AnnaBridge 156:ff21514d8981 7937
AnnaBridge 156:ff21514d8981 7938 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
AnnaBridge 156:ff21514d8981 7939 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 156:ff21514d8981 7940 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 156:ff21514d8981 7941 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 7942 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 7943
AnnaBridge 156:ff21514d8981 7944 #define USB_OTG_HCCHAR_MC_Pos (20U)
AnnaBridge 156:ff21514d8981 7945 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
AnnaBridge 156:ff21514d8981 7946 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 156:ff21514d8981 7947 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 7948 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 7949
AnnaBridge 156:ff21514d8981 7950 #define USB_OTG_HCCHAR_DAD_Pos (22U)
AnnaBridge 156:ff21514d8981 7951 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
AnnaBridge 156:ff21514d8981 7952 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
AnnaBridge 156:ff21514d8981 7953 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
AnnaBridge 156:ff21514d8981 7954 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
AnnaBridge 156:ff21514d8981 7955 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
AnnaBridge 156:ff21514d8981 7956 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
AnnaBridge 156:ff21514d8981 7957 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 7958 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 7959 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 7960 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
AnnaBridge 156:ff21514d8981 7961 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 7962 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
AnnaBridge 156:ff21514d8981 7963 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
AnnaBridge 156:ff21514d8981 7964 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 7965 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
AnnaBridge 156:ff21514d8981 7966 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
AnnaBridge 156:ff21514d8981 7967 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 7968 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
AnnaBridge 156:ff21514d8981 7969
AnnaBridge 156:ff21514d8981 7970 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
AnnaBridge 156:ff21514d8981 7971
AnnaBridge 156:ff21514d8981 7972 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
AnnaBridge 156:ff21514d8981 7973 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
AnnaBridge 156:ff21514d8981 7974 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
AnnaBridge 156:ff21514d8981 7975 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 7976 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 7977 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 7978 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 7979 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 7980 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 7981 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 7982
AnnaBridge 156:ff21514d8981 7983 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
AnnaBridge 156:ff21514d8981 7984 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
AnnaBridge 156:ff21514d8981 7985 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
AnnaBridge 156:ff21514d8981 7986 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 7987 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 7988 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 7989 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 7990 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 7991 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 7992 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 7993
AnnaBridge 156:ff21514d8981 7994 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
AnnaBridge 156:ff21514d8981 7995 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
AnnaBridge 156:ff21514d8981 7996 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
AnnaBridge 156:ff21514d8981 7997 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 7998 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 7999 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
AnnaBridge 156:ff21514d8981 8000 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
AnnaBridge 156:ff21514d8981 8001 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
AnnaBridge 156:ff21514d8981 8002 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
AnnaBridge 156:ff21514d8981 8003 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 8004 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
AnnaBridge 156:ff21514d8981 8005
AnnaBridge 156:ff21514d8981 8006 /******************** Bit definition for USB_OTG_HCINT register ********************/
AnnaBridge 156:ff21514d8981 8007 #define USB_OTG_HCINT_XFRC_Pos (0U)
AnnaBridge 156:ff21514d8981 8008 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 8009 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
AnnaBridge 156:ff21514d8981 8010 #define USB_OTG_HCINT_CHH_Pos (1U)
AnnaBridge 156:ff21514d8981 8011 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 8012 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
AnnaBridge 156:ff21514d8981 8013 #define USB_OTG_HCINT_AHBERR_Pos (2U)
AnnaBridge 156:ff21514d8981 8014 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 8015 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
AnnaBridge 156:ff21514d8981 8016 #define USB_OTG_HCINT_STALL_Pos (3U)
AnnaBridge 156:ff21514d8981 8017 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 8018 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
AnnaBridge 156:ff21514d8981 8019 #define USB_OTG_HCINT_NAK_Pos (4U)
AnnaBridge 156:ff21514d8981 8020 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 8021 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
AnnaBridge 156:ff21514d8981 8022 #define USB_OTG_HCINT_ACK_Pos (5U)
AnnaBridge 156:ff21514d8981 8023 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 8024 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
AnnaBridge 156:ff21514d8981 8025 #define USB_OTG_HCINT_NYET_Pos (6U)
AnnaBridge 156:ff21514d8981 8026 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 8027 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
AnnaBridge 156:ff21514d8981 8028 #define USB_OTG_HCINT_TXERR_Pos (7U)
AnnaBridge 156:ff21514d8981 8029 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 8030 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
AnnaBridge 156:ff21514d8981 8031 #define USB_OTG_HCINT_BBERR_Pos (8U)
AnnaBridge 156:ff21514d8981 8032 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 8033 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
AnnaBridge 156:ff21514d8981 8034 #define USB_OTG_HCINT_FRMOR_Pos (9U)
AnnaBridge 156:ff21514d8981 8035 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 8036 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
AnnaBridge 156:ff21514d8981 8037 #define USB_OTG_HCINT_DTERR_Pos (10U)
AnnaBridge 156:ff21514d8981 8038 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 8039 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
AnnaBridge 156:ff21514d8981 8040
AnnaBridge 156:ff21514d8981 8041 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
AnnaBridge 156:ff21514d8981 8042 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
AnnaBridge 156:ff21514d8981 8043 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 8044 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 156:ff21514d8981 8045 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
AnnaBridge 156:ff21514d8981 8046 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 8047 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 156:ff21514d8981 8048 #define USB_OTG_DIEPINT_TOC_Pos (3U)
AnnaBridge 156:ff21514d8981 8049 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 8050 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
AnnaBridge 156:ff21514d8981 8051 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
AnnaBridge 156:ff21514d8981 8052 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 8053 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
AnnaBridge 156:ff21514d8981 8054 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
AnnaBridge 156:ff21514d8981 8055 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 8056 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
AnnaBridge 156:ff21514d8981 8057 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
AnnaBridge 156:ff21514d8981 8058 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 8059 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
AnnaBridge 156:ff21514d8981 8060 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
AnnaBridge 156:ff21514d8981 8061 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 8062 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
AnnaBridge 156:ff21514d8981 8063 #define USB_OTG_DIEPINT_BNA_Pos (9U)
AnnaBridge 156:ff21514d8981 8064 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 8065 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
AnnaBridge 156:ff21514d8981 8066 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
AnnaBridge 156:ff21514d8981 8067 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
AnnaBridge 156:ff21514d8981 8068 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
AnnaBridge 156:ff21514d8981 8069 #define USB_OTG_DIEPINT_BERR_Pos (12U)
AnnaBridge 156:ff21514d8981 8070 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
AnnaBridge 156:ff21514d8981 8071 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
AnnaBridge 156:ff21514d8981 8072 #define USB_OTG_DIEPINT_NAK_Pos (13U)
AnnaBridge 156:ff21514d8981 8073 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
AnnaBridge 156:ff21514d8981 8074 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
AnnaBridge 156:ff21514d8981 8075
AnnaBridge 156:ff21514d8981 8076 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
AnnaBridge 156:ff21514d8981 8077 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
AnnaBridge 156:ff21514d8981 8078 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 8079 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
AnnaBridge 156:ff21514d8981 8080 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
AnnaBridge 156:ff21514d8981 8081 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 8082 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
AnnaBridge 156:ff21514d8981 8083 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
AnnaBridge 156:ff21514d8981 8084 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 156:ff21514d8981 8085 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
AnnaBridge 156:ff21514d8981 8086 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
AnnaBridge 156:ff21514d8981 8087 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 8088 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
AnnaBridge 156:ff21514d8981 8089 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
AnnaBridge 156:ff21514d8981 8090 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 8091 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
AnnaBridge 156:ff21514d8981 8092 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
AnnaBridge 156:ff21514d8981 8093 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
AnnaBridge 156:ff21514d8981 8094 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 156:ff21514d8981 8095 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
AnnaBridge 156:ff21514d8981 8096 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 8097 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
AnnaBridge 156:ff21514d8981 8098 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
AnnaBridge 156:ff21514d8981 8099 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
AnnaBridge 156:ff21514d8981 8100 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
AnnaBridge 156:ff21514d8981 8101 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
AnnaBridge 156:ff21514d8981 8102 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
AnnaBridge 156:ff21514d8981 8103 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
AnnaBridge 156:ff21514d8981 8104 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
AnnaBridge 156:ff21514d8981 8105 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
AnnaBridge 156:ff21514d8981 8106 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
AnnaBridge 156:ff21514d8981 8107 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
AnnaBridge 156:ff21514d8981 8108 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
AnnaBridge 156:ff21514d8981 8109 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
AnnaBridge 156:ff21514d8981 8110
AnnaBridge 156:ff21514d8981 8111 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
AnnaBridge 156:ff21514d8981 8112
AnnaBridge 156:ff21514d8981 8113 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 156:ff21514d8981 8114 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 156:ff21514d8981 8115 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 156:ff21514d8981 8116 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 156:ff21514d8981 8117 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 156:ff21514d8981 8118 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 156:ff21514d8981 8119 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
AnnaBridge 156:ff21514d8981 8120 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
AnnaBridge 156:ff21514d8981 8121 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
AnnaBridge 156:ff21514d8981 8122 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
AnnaBridge 156:ff21514d8981 8123 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 156:ff21514d8981 8124 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 156:ff21514d8981 8125 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 156:ff21514d8981 8126 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
AnnaBridge 156:ff21514d8981 8127 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 156:ff21514d8981 8128 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 156:ff21514d8981 8129 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
AnnaBridge 156:ff21514d8981 8130 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 8131 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
AnnaBridge 156:ff21514d8981 8132 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
AnnaBridge 156:ff21514d8981 8133 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
AnnaBridge 156:ff21514d8981 8134 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
AnnaBridge 156:ff21514d8981 8135 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 8136 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 8137
AnnaBridge 156:ff21514d8981 8138 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
AnnaBridge 156:ff21514d8981 8139 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
AnnaBridge 156:ff21514d8981 8140 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 8141 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 156:ff21514d8981 8142
AnnaBridge 156:ff21514d8981 8143 /******************** Bit definition for USB_OTG_HCDMA register ********************/
AnnaBridge 156:ff21514d8981 8144 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
AnnaBridge 156:ff21514d8981 8145 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 156:ff21514d8981 8146 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 156:ff21514d8981 8147
AnnaBridge 156:ff21514d8981 8148 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
AnnaBridge 156:ff21514d8981 8149 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
AnnaBridge 156:ff21514d8981 8150 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 8151 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
AnnaBridge 156:ff21514d8981 8152
AnnaBridge 156:ff21514d8981 8153 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
AnnaBridge 156:ff21514d8981 8154 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
AnnaBridge 156:ff21514d8981 8155 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 156:ff21514d8981 8156 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 156:ff21514d8981 8157 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
AnnaBridge 156:ff21514d8981 8158 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 156:ff21514d8981 8159 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
AnnaBridge 156:ff21514d8981 8160
AnnaBridge 156:ff21514d8981 8161 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
AnnaBridge 156:ff21514d8981 8162
AnnaBridge 156:ff21514d8981 8163 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
AnnaBridge 156:ff21514d8981 8164 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 156:ff21514d8981 8165 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 156:ff21514d8981 8166 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
AnnaBridge 156:ff21514d8981 8167 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 156:ff21514d8981 8168 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 156:ff21514d8981 8169 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
AnnaBridge 156:ff21514d8981 8170 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 156:ff21514d8981 8171 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 156:ff21514d8981 8172 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 156:ff21514d8981 8173 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 156:ff21514d8981 8174 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 156:ff21514d8981 8175 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
AnnaBridge 156:ff21514d8981 8176 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 8177 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 156:ff21514d8981 8178 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
AnnaBridge 156:ff21514d8981 8179 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 156:ff21514d8981 8180 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 156:ff21514d8981 8181 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 156:ff21514d8981 8182 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 156:ff21514d8981 8183 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
AnnaBridge 156:ff21514d8981 8184 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
AnnaBridge 156:ff21514d8981 8185 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
AnnaBridge 156:ff21514d8981 8186 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
AnnaBridge 156:ff21514d8981 8187 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 156:ff21514d8981 8188 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 156:ff21514d8981 8189 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
AnnaBridge 156:ff21514d8981 8190 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 156:ff21514d8981 8191 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 156:ff21514d8981 8192 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
AnnaBridge 156:ff21514d8981 8193 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 156:ff21514d8981 8194 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 156:ff21514d8981 8195 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
AnnaBridge 156:ff21514d8981 8196 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 8197 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 156:ff21514d8981 8198 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
AnnaBridge 156:ff21514d8981 8199 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 156:ff21514d8981 8200 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 156:ff21514d8981 8201
AnnaBridge 156:ff21514d8981 8202 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
AnnaBridge 156:ff21514d8981 8203 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
AnnaBridge 156:ff21514d8981 8204 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 8205 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 156:ff21514d8981 8206 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
AnnaBridge 156:ff21514d8981 8207 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 8208 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 156:ff21514d8981 8209 #define USB_OTG_DOEPINT_STUP_Pos (3U)
AnnaBridge 156:ff21514d8981 8210 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
AnnaBridge 156:ff21514d8981 8211 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
AnnaBridge 156:ff21514d8981 8212 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
AnnaBridge 156:ff21514d8981 8213 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 8214 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
AnnaBridge 156:ff21514d8981 8215 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
AnnaBridge 156:ff21514d8981 8216 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 156:ff21514d8981 8217 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
AnnaBridge 156:ff21514d8981 8218 #define USB_OTG_DOEPINT_NYET_Pos (14U)
AnnaBridge 156:ff21514d8981 8219 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
AnnaBridge 156:ff21514d8981 8220 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
AnnaBridge 156:ff21514d8981 8221
AnnaBridge 156:ff21514d8981 8222 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
AnnaBridge 156:ff21514d8981 8223
AnnaBridge 156:ff21514d8981 8224 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 156:ff21514d8981 8225 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 156:ff21514d8981 8226 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 156:ff21514d8981 8227 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 156:ff21514d8981 8228 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 156:ff21514d8981 8229 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 156:ff21514d8981 8230
AnnaBridge 156:ff21514d8981 8231 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
AnnaBridge 156:ff21514d8981 8232 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
AnnaBridge 156:ff21514d8981 8233 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
AnnaBridge 156:ff21514d8981 8234 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
AnnaBridge 156:ff21514d8981 8235 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
AnnaBridge 156:ff21514d8981 8236
AnnaBridge 156:ff21514d8981 8237 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 156:ff21514d8981 8238 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
AnnaBridge 156:ff21514d8981 8239 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 156:ff21514d8981 8240 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
AnnaBridge 156:ff21514d8981 8241 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
AnnaBridge 156:ff21514d8981 8242 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
AnnaBridge 156:ff21514d8981 8243 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
AnnaBridge 156:ff21514d8981 8244 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
AnnaBridge 156:ff21514d8981 8245 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 156:ff21514d8981 8246 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
AnnaBridge 156:ff21514d8981 8247
AnnaBridge 156:ff21514d8981 8248 /**
AnnaBridge 156:ff21514d8981 8249 * @}
AnnaBridge 156:ff21514d8981 8250 */
AnnaBridge 156:ff21514d8981 8251
AnnaBridge 156:ff21514d8981 8252 /**
AnnaBridge 156:ff21514d8981 8253 * @}
AnnaBridge 156:ff21514d8981 8254 */
AnnaBridge 156:ff21514d8981 8255
AnnaBridge 156:ff21514d8981 8256 /** @addtogroup Exported_macros
AnnaBridge 156:ff21514d8981 8257 * @{
AnnaBridge 156:ff21514d8981 8258 */
AnnaBridge 156:ff21514d8981 8259
AnnaBridge 156:ff21514d8981 8260 /******************************* ADC Instances ********************************/
AnnaBridge 156:ff21514d8981 8261 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 156:ff21514d8981 8262
AnnaBridge 156:ff21514d8981 8263 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
AnnaBridge 156:ff21514d8981 8264 /******************************* CRC Instances ********************************/
AnnaBridge 156:ff21514d8981 8265 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 156:ff21514d8981 8266
AnnaBridge 156:ff21514d8981 8267
AnnaBridge 156:ff21514d8981 8268 /******************************** DMA Instances *******************************/
AnnaBridge 156:ff21514d8981 8269 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 156:ff21514d8981 8270 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 156:ff21514d8981 8271 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 156:ff21514d8981 8272 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 156:ff21514d8981 8273 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 156:ff21514d8981 8274 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 156:ff21514d8981 8275 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 156:ff21514d8981 8276 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 156:ff21514d8981 8277 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 156:ff21514d8981 8278 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 156:ff21514d8981 8279 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 156:ff21514d8981 8280 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 156:ff21514d8981 8281 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 156:ff21514d8981 8282 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 156:ff21514d8981 8283 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 156:ff21514d8981 8284 ((INSTANCE) == DMA2_Stream7))
AnnaBridge 156:ff21514d8981 8285
AnnaBridge 156:ff21514d8981 8286 /******************************* GPIO Instances *******************************/
AnnaBridge 156:ff21514d8981 8287 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 156:ff21514d8981 8288 ((INSTANCE) == GPIOB) || \
AnnaBridge 156:ff21514d8981 8289 ((INSTANCE) == GPIOC) || \
AnnaBridge 156:ff21514d8981 8290 ((INSTANCE) == GPIOD) || \
AnnaBridge 156:ff21514d8981 8291 ((INSTANCE) == GPIOE) || \
AnnaBridge 156:ff21514d8981 8292 ((INSTANCE) == GPIOH))
AnnaBridge 156:ff21514d8981 8293
AnnaBridge 156:ff21514d8981 8294 /******************************** I2C Instances *******************************/
AnnaBridge 156:ff21514d8981 8295 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 156:ff21514d8981 8296 ((INSTANCE) == I2C2) || \
AnnaBridge 156:ff21514d8981 8297 ((INSTANCE) == I2C3))
AnnaBridge 156:ff21514d8981 8298
AnnaBridge 156:ff21514d8981 8299 /******************************* SMBUS Instances ******************************/
AnnaBridge 156:ff21514d8981 8300 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
AnnaBridge 156:ff21514d8981 8301
AnnaBridge 156:ff21514d8981 8302 /******************************** I2S Instances *******************************/
AnnaBridge 156:ff21514d8981 8303
AnnaBridge 156:ff21514d8981 8304 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
AnnaBridge 156:ff21514d8981 8305 ((INSTANCE) == SPI3))
AnnaBridge 156:ff21514d8981 8306
AnnaBridge 156:ff21514d8981 8307 /*************************** I2S Extended Instances ***************************/
AnnaBridge 156:ff21514d8981 8308 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
AnnaBridge 156:ff21514d8981 8309 ((INSTANCE) == I2S3ext))
AnnaBridge 156:ff21514d8981 8310 /* Legacy Defines */
AnnaBridge 156:ff21514d8981 8311 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
AnnaBridge 156:ff21514d8981 8312
AnnaBridge 156:ff21514d8981 8313
AnnaBridge 156:ff21514d8981 8314 /****************************** RTC Instances *********************************/
AnnaBridge 156:ff21514d8981 8315 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 156:ff21514d8981 8316
AnnaBridge 156:ff21514d8981 8317
AnnaBridge 156:ff21514d8981 8318 /******************************** SPI Instances *******************************/
AnnaBridge 156:ff21514d8981 8319 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 156:ff21514d8981 8320 ((INSTANCE) == SPI2) || \
AnnaBridge 156:ff21514d8981 8321 ((INSTANCE) == SPI3) || \
AnnaBridge 156:ff21514d8981 8322 ((INSTANCE) == SPI4))
AnnaBridge 156:ff21514d8981 8323
AnnaBridge 156:ff21514d8981 8324
AnnaBridge 156:ff21514d8981 8325 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 156:ff21514d8981 8326 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8327 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8328 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8329 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8330 ((INSTANCE) == TIM5) || \
AnnaBridge 156:ff21514d8981 8331 ((INSTANCE) == TIM9) || \
AnnaBridge 156:ff21514d8981 8332 ((INSTANCE) == TIM10) || \
AnnaBridge 156:ff21514d8981 8333 ((INSTANCE) == TIM11))
AnnaBridge 156:ff21514d8981 8334
AnnaBridge 156:ff21514d8981 8335
AnnaBridge 156:ff21514d8981 8336 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 156:ff21514d8981 8337 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8338 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8339 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8340 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8341 ((INSTANCE) == TIM5) || \
AnnaBridge 156:ff21514d8981 8342 ((INSTANCE) == TIM9) || \
AnnaBridge 156:ff21514d8981 8343 ((INSTANCE) == TIM10) || \
AnnaBridge 156:ff21514d8981 8344 ((INSTANCE) == TIM11))
AnnaBridge 156:ff21514d8981 8345
AnnaBridge 156:ff21514d8981 8346 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 156:ff21514d8981 8347 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8348 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8349 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8350 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8351 ((INSTANCE) == TIM5) || \
AnnaBridge 156:ff21514d8981 8352 ((INSTANCE) == TIM9))
AnnaBridge 156:ff21514d8981 8353
AnnaBridge 156:ff21514d8981 8354 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 156:ff21514d8981 8355 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8356 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8357 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8358 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8359 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8360
AnnaBridge 156:ff21514d8981 8361 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 156:ff21514d8981 8362 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8363 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8364 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8365 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8366 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8367
AnnaBridge 156:ff21514d8981 8368 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 156:ff21514d8981 8369 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 156:ff21514d8981 8370
AnnaBridge 156:ff21514d8981 8371 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 156:ff21514d8981 8372 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8373 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8374 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8375 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8376 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8377
AnnaBridge 156:ff21514d8981 8378 /****************** TIM Instances : DMA requests generation (UDE) *************/
AnnaBridge 156:ff21514d8981 8379 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8380 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8381 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8382 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8383 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8384
AnnaBridge 156:ff21514d8981 8385 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 156:ff21514d8981 8386 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8387 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8388 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8389 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8390 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8391
AnnaBridge 156:ff21514d8981 8392 /************ TIM Instances : DMA requests generation (COMDE) *****************/
AnnaBridge 156:ff21514d8981 8393 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8394 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8395 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8396 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8397 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8398
AnnaBridge 156:ff21514d8981 8399 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 156:ff21514d8981 8400 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8401 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8402 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8403 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8404 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8405
AnnaBridge 156:ff21514d8981 8406 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 156:ff21514d8981 8407 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8408 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8409 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8410 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8411 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8412
AnnaBridge 156:ff21514d8981 8413 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 156:ff21514d8981 8414 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8415 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8416 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8417 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8418 ((INSTANCE) == TIM5) || \
AnnaBridge 156:ff21514d8981 8419 ((INSTANCE) == TIM9))
AnnaBridge 156:ff21514d8981 8420
AnnaBridge 156:ff21514d8981 8421 /********************** TIM Instances : 32 bit Counter ************************/
AnnaBridge 156:ff21514d8981 8422 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8423 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8424
AnnaBridge 156:ff21514d8981 8425 /***************** TIM Instances : external trigger input availabe ************/
AnnaBridge 156:ff21514d8981 8426 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8427 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8428 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8429 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8430 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8431
AnnaBridge 156:ff21514d8981 8432 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 156:ff21514d8981 8433 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8434 ((INSTANCE) == TIM5) || \
AnnaBridge 156:ff21514d8981 8435 ((INSTANCE) == TIM11))
AnnaBridge 156:ff21514d8981 8436
AnnaBridge 156:ff21514d8981 8437 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 156:ff21514d8981 8438 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 156:ff21514d8981 8439 ((((INSTANCE) == TIM1) && \
AnnaBridge 156:ff21514d8981 8440 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 8441 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 8442 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 8443 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 156:ff21514d8981 8444 || \
AnnaBridge 156:ff21514d8981 8445 (((INSTANCE) == TIM2) && \
AnnaBridge 156:ff21514d8981 8446 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 8447 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 8448 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 8449 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 156:ff21514d8981 8450 || \
AnnaBridge 156:ff21514d8981 8451 (((INSTANCE) == TIM3) && \
AnnaBridge 156:ff21514d8981 8452 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 8453 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 8454 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 8455 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 156:ff21514d8981 8456 || \
AnnaBridge 156:ff21514d8981 8457 (((INSTANCE) == TIM4) && \
AnnaBridge 156:ff21514d8981 8458 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 8459 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 8460 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 8461 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 156:ff21514d8981 8462 || \
AnnaBridge 156:ff21514d8981 8463 (((INSTANCE) == TIM5) && \
AnnaBridge 156:ff21514d8981 8464 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 8465 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 8466 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 8467 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 156:ff21514d8981 8468 || \
AnnaBridge 156:ff21514d8981 8469 (((INSTANCE) == TIM9) && \
AnnaBridge 156:ff21514d8981 8470 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 8471 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 156:ff21514d8981 8472 || \
AnnaBridge 156:ff21514d8981 8473 (((INSTANCE) == TIM10) && \
AnnaBridge 156:ff21514d8981 8474 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 156:ff21514d8981 8475 || \
AnnaBridge 156:ff21514d8981 8476 (((INSTANCE) == TIM11) && \
AnnaBridge 156:ff21514d8981 8477 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 156:ff21514d8981 8478
AnnaBridge 156:ff21514d8981 8479 /************ TIM Instances : complementary output(s) available ***************/
AnnaBridge 156:ff21514d8981 8480 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 156:ff21514d8981 8481 ((((INSTANCE) == TIM1) && \
AnnaBridge 156:ff21514d8981 8482 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 8483 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 8484 ((CHANNEL) == TIM_CHANNEL_3))))
AnnaBridge 156:ff21514d8981 8485
AnnaBridge 156:ff21514d8981 8486 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 156:ff21514d8981 8487 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8488 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8489 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8490 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8491 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8492
AnnaBridge 156:ff21514d8981 8493 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 156:ff21514d8981 8494 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8495 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8496 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8497 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8498 ((INSTANCE) == TIM5) || \
AnnaBridge 156:ff21514d8981 8499 ((INSTANCE) == TIM9) || \
AnnaBridge 156:ff21514d8981 8500 ((INSTANCE) == TIM10) || \
AnnaBridge 156:ff21514d8981 8501 ((INSTANCE) == TIM11))
AnnaBridge 156:ff21514d8981 8502
AnnaBridge 156:ff21514d8981 8503
AnnaBridge 156:ff21514d8981 8504 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 156:ff21514d8981 8505
AnnaBridge 156:ff21514d8981 8506 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
AnnaBridge 156:ff21514d8981 8507
AnnaBridge 156:ff21514d8981 8508 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 156:ff21514d8981 8509 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8510 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8511 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8512 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8513 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8514
AnnaBridge 156:ff21514d8981 8515 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 156:ff21514d8981 8516 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8517 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8518 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8519 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8520 ((INSTANCE) == TIM5) || \
AnnaBridge 156:ff21514d8981 8521 ((INSTANCE) == TIM9))
AnnaBridge 156:ff21514d8981 8522
AnnaBridge 156:ff21514d8981 8523 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 156:ff21514d8981 8524 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
AnnaBridge 156:ff21514d8981 8525 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8526 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8527 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8528 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8529
AnnaBridge 156:ff21514d8981 8530 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 156:ff21514d8981 8531 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
AnnaBridge 156:ff21514d8981 8532
AnnaBridge 156:ff21514d8981 8533 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 156:ff21514d8981 8534 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8535 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8536 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8537 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8538 ((INSTANCE) == TIM5) || \
AnnaBridge 156:ff21514d8981 8539 ((INSTANCE) == TIM9))
AnnaBridge 156:ff21514d8981 8540 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 156:ff21514d8981 8541 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 156:ff21514d8981 8542 ((INSTANCE) == TIM2) || \
AnnaBridge 156:ff21514d8981 8543 ((INSTANCE) == TIM3) || \
AnnaBridge 156:ff21514d8981 8544 ((INSTANCE) == TIM4) || \
AnnaBridge 156:ff21514d8981 8545 ((INSTANCE) == TIM5))
AnnaBridge 156:ff21514d8981 8546 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 156:ff21514d8981 8547 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
AnnaBridge 156:ff21514d8981 8548
AnnaBridge 156:ff21514d8981 8549 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 156:ff21514d8981 8550 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 156:ff21514d8981 8551 ((INSTANCE) == USART2) || \
AnnaBridge 156:ff21514d8981 8552 ((INSTANCE) == USART6))
AnnaBridge 156:ff21514d8981 8553
AnnaBridge 156:ff21514d8981 8554 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 156:ff21514d8981 8555 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 156:ff21514d8981 8556 ((INSTANCE) == USART2) || \
AnnaBridge 156:ff21514d8981 8557 ((INSTANCE) == USART6))
AnnaBridge 156:ff21514d8981 8558
AnnaBridge 156:ff21514d8981 8559 /* Legacy defines */
AnnaBridge 156:ff21514d8981 8560 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 156:ff21514d8981 8561
AnnaBridge 156:ff21514d8981 8562 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 156:ff21514d8981 8563 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 156:ff21514d8981 8564 ((INSTANCE) == USART2) || \
AnnaBridge 156:ff21514d8981 8565 ((INSTANCE) == USART6))
AnnaBridge 156:ff21514d8981 8566 /******************** UART Instances : LIN mode **********************/
AnnaBridge 156:ff21514d8981 8567 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 156:ff21514d8981 8568
AnnaBridge 156:ff21514d8981 8569 /********************* UART Instances : Smart card mode ***********************/
AnnaBridge 156:ff21514d8981 8570 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 156:ff21514d8981 8571 ((INSTANCE) == USART2) || \
AnnaBridge 156:ff21514d8981 8572 ((INSTANCE) == USART6))
AnnaBridge 156:ff21514d8981 8573
AnnaBridge 156:ff21514d8981 8574 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 156:ff21514d8981 8575 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 156:ff21514d8981 8576 ((INSTANCE) == USART2) || \
AnnaBridge 156:ff21514d8981 8577 ((INSTANCE) == USART6))
AnnaBridge 156:ff21514d8981 8578
AnnaBridge 156:ff21514d8981 8579 /*********************** PCD Instances ****************************************/
AnnaBridge 156:ff21514d8981 8580 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
AnnaBridge 156:ff21514d8981 8581
AnnaBridge 156:ff21514d8981 8582 /*********************** HCD Instances ****************************************/
AnnaBridge 156:ff21514d8981 8583 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
AnnaBridge 156:ff21514d8981 8584
AnnaBridge 156:ff21514d8981 8585 /****************************** SDIO Instances ********************************/
AnnaBridge 156:ff21514d8981 8586 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
AnnaBridge 156:ff21514d8981 8587
AnnaBridge 156:ff21514d8981 8588 /****************************** IWDG Instances ********************************/
AnnaBridge 156:ff21514d8981 8589 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 156:ff21514d8981 8590
AnnaBridge 156:ff21514d8981 8591 /****************************** WWDG Instances ********************************/
AnnaBridge 156:ff21514d8981 8592 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 156:ff21514d8981 8593
AnnaBridge 156:ff21514d8981 8594 /****************************** USB Exported Constants ************************/
AnnaBridge 156:ff21514d8981 8595 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
AnnaBridge 156:ff21514d8981 8596 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
AnnaBridge 156:ff21514d8981 8597 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
AnnaBridge 156:ff21514d8981 8598 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
AnnaBridge 156:ff21514d8981 8599
AnnaBridge 156:ff21514d8981 8600 /*
AnnaBridge 156:ff21514d8981 8601 * @brief Specific devices reset values definitions
AnnaBridge 156:ff21514d8981 8602 */
AnnaBridge 156:ff21514d8981 8603 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
AnnaBridge 156:ff21514d8981 8604 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
AnnaBridge 156:ff21514d8981 8605
AnnaBridge 156:ff21514d8981 8606 #define RCC_MAX_FREQUENCY 84000000U /*!< Max frequency of family in Hz*/
AnnaBridge 156:ff21514d8981 8607 #define RCC_MAX_FREQUENCY_SCALE3 60000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
AnnaBridge 156:ff21514d8981 8608 #define RCC_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale2, in Hz */
AnnaBridge 156:ff21514d8981 8609 #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
AnnaBridge 156:ff21514d8981 8610 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
AnnaBridge 156:ff21514d8981 8611 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
AnnaBridge 156:ff21514d8981 8612 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
AnnaBridge 156:ff21514d8981 8613
AnnaBridge 156:ff21514d8981 8614 #define RCC_PLLN_MIN_VALUE 192U
AnnaBridge 156:ff21514d8981 8615 #define RCC_PLLN_MAX_VALUE 432U
AnnaBridge 156:ff21514d8981 8616
AnnaBridge 156:ff21514d8981 8617 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
AnnaBridge 156:ff21514d8981 8618 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
AnnaBridge 156:ff21514d8981 8619
AnnaBridge 156:ff21514d8981 8620 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
AnnaBridge 156:ff21514d8981 8621 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
AnnaBridge 156:ff21514d8981 8622
AnnaBridge 156:ff21514d8981 8623
AnnaBridge 156:ff21514d8981 8624 /**
AnnaBridge 156:ff21514d8981 8625 * @}
AnnaBridge 156:ff21514d8981 8626 */
AnnaBridge 156:ff21514d8981 8627
AnnaBridge 156:ff21514d8981 8628 /**
AnnaBridge 156:ff21514d8981 8629 * @}
AnnaBridge 156:ff21514d8981 8630 */
AnnaBridge 156:ff21514d8981 8631
AnnaBridge 156:ff21514d8981 8632 /**
AnnaBridge 156:ff21514d8981 8633 * @}
AnnaBridge 156:ff21514d8981 8634 */
AnnaBridge 156:ff21514d8981 8635
AnnaBridge 156:ff21514d8981 8636 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 8637 }
AnnaBridge 156:ff21514d8981 8638 #endif /* __cplusplus */
AnnaBridge 156:ff21514d8981 8639
AnnaBridge 156:ff21514d8981 8640 #endif /* __STM32F401xE_H */
AnnaBridge 156:ff21514d8981 8641
AnnaBridge 156:ff21514d8981 8642
AnnaBridge 156:ff21514d8981 8643
AnnaBridge 156:ff21514d8981 8644 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/