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TARGET_ARM_MPS2_M7/TARGET_ARM_SSG/TARGET_MPS2/spi_def.h@160:5571c4ff569f, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 16:13:02 2018 +0000
Revision:
160:5571c4ff569f
Parent:
102:da0ca467f8b5 
mbed library. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 102:da0ca467f8b5 1 /* mbed Microcontroller Library
Kojto 102:da0ca467f8b5 2 * Copyright (c) 2006-2015 ARM Limited
Kojto 102:da0ca467f8b5 3 *
Kojto 102:da0ca467f8b5 4 * Licensed under the Apache License, Version 2.0 (the "License");
Kojto 102:da0ca467f8b5 5 * you may not use this file except in compliance with the License.
Kojto 102:da0ca467f8b5 6 * You may obtain a copy of the License at
Kojto 102:da0ca467f8b5 7 *
Kojto 102:da0ca467f8b5 8 * http://www.apache.org/licenses/LICENSE-2.0
Kojto 102:da0ca467f8b5 9 *
Kojto 102:da0ca467f8b5 10 * Unless required by applicable law or agreed to in writing, software
Kojto 102:da0ca467f8b5 11 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 102:da0ca467f8b5 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 102:da0ca467f8b5 13 * See the License for the specific language governing permissions and
Kojto 102:da0ca467f8b5 14 * limitations under the License.
Kojto 102:da0ca467f8b5 15 * ----------------------------------------------------------------
Kojto 102:da0ca467f8b5 16 * File: apspi.h
Kojto 102:da0ca467f8b5 17 * Release: Version 2.0
Kojto 102:da0ca467f8b5 18 * ----------------------------------------------------------------
Kojto 102:da0ca467f8b5 19 *
Kojto 102:da0ca467f8b5 20 * SSP interface Support
Kojto 102:da0ca467f8b5 21 * =====================
Kojto 102:da0ca467f8b5 22 */
Kojto 102:da0ca467f8b5 23
Kojto 102:da0ca467f8b5 24 #define SSPCS_BASE (0x4002804C) // SSP chip select register
Kojto 102:da0ca467f8b5 25 #define SSP_BASE (0x40020000) // SSP Prime Cell
Kojto 102:da0ca467f8b5 26
Kojto 102:da0ca467f8b5 27 #define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
Kojto 102:da0ca467f8b5 28 #define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
Kojto 102:da0ca467f8b5 29 #define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
Kojto 102:da0ca467f8b5 30 #define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
Kojto 102:da0ca467f8b5 31 #define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
Kojto 102:da0ca467f8b5 32 #define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
Kojto 102:da0ca467f8b5 33 #define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
Kojto 102:da0ca467f8b5 34 #define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
Kojto 102:da0ca467f8b5 35 #define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
Kojto 102:da0ca467f8b5 36 #define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
Kojto 102:da0ca467f8b5 37 #define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
Kojto 102:da0ca467f8b5 38
Kojto 102:da0ca467f8b5 39 // SSPCR0 Control register 0
Kojto 102:da0ca467f8b5 40 #define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
Kojto 102:da0ca467f8b5 41 #define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
Kojto 102:da0ca467f8b5 42 #define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
Kojto 102:da0ca467f8b5 43 #define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
Kojto 102:da0ca467f8b5 44 #define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
Kojto 102:da0ca467f8b5 45 #define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
Kojto 102:da0ca467f8b5 46
Kojto 102:da0ca467f8b5 47 // SSPCR1 Control register 1
Kojto 102:da0ca467f8b5 48 #define SSPCR1_SOD 0x0008 // Slave Output mode Disable
Kojto 102:da0ca467f8b5 49 #define SSPCR1_MS 0x0004 // Master or Slave mode
Kojto 102:da0ca467f8b5 50 #define SSPCR1_SSE 0x0002 // Serial port enable
Kojto 102:da0ca467f8b5 51 #define SSPCR1_LBM 0x0001 // Loop Back Mode
Kojto 102:da0ca467f8b5 52
Kojto 102:da0ca467f8b5 53 // SSPSR Status register
Kojto 102:da0ca467f8b5 54 #define SSPSR_BSY 0x0010 // Busy
Kojto 102:da0ca467f8b5 55 #define SSPSR_RFF 0x0008 // Receive FIFO full
Kojto 102:da0ca467f8b5 56 #define SSPSR_RNE 0x0004 // Receive FIFO not empty
Kojto 102:da0ca467f8b5 57 #define SSPSR_TNF 0x0002 // Transmit FIFO not full
Kojto 102:da0ca467f8b5 58 #define SSPSR_TFE 0x0001 // Transmit FIFO empty
Kojto 102:da0ca467f8b5 59
Kojto 102:da0ca467f8b5 60 // SSPCPSR Clock prescale register
Kojto 102:da0ca467f8b5 61 #define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
Kojto 102:da0ca467f8b5 62
Kojto 102:da0ca467f8b5 63 // SSPIMSC Interrupt mask set and clear register
Kojto 102:da0ca467f8b5 64 #define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
Kojto 102:da0ca467f8b5 65 #define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
Kojto 102:da0ca467f8b5 66 #define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
Kojto 102:da0ca467f8b5 67 #define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
Kojto 102:da0ca467f8b5 68
Kojto 102:da0ca467f8b5 69 // SSPRIS Raw interrupt status register
Kojto 102:da0ca467f8b5 70 #define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
Kojto 102:da0ca467f8b5 71 #define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
Kojto 102:da0ca467f8b5 72 #define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
Kojto 102:da0ca467f8b5 73 #define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
Kojto 102:da0ca467f8b5 74
Kojto 102:da0ca467f8b5 75 // SSPMIS Masked interrupt status register
Kojto 102:da0ca467f8b5 76 #define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
Kojto 102:da0ca467f8b5 77 #define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
Kojto 102:da0ca467f8b5 78 #define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
Kojto 102:da0ca467f8b5 79 #define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
Kojto 102:da0ca467f8b5 80
Kojto 102:da0ca467f8b5 81 // SSPICR Interrupt clear register
Kojto 102:da0ca467f8b5 82 #define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
Kojto 102:da0ca467f8b5 83 #define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
Kojto 102:da0ca467f8b5 84
Kojto 102:da0ca467f8b5 85 // SSPDMACR DMA control register
Kojto 102:da0ca467f8b5 86 #define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
Kojto 102:da0ca467f8b5 87 #define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
Kojto 102:da0ca467f8b5 88
Kojto 102:da0ca467f8b5 89 // SPICS register (0=Chip Select low)
Kojto 102:da0ca467f8b5 90 #define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
Kojto 102:da0ca467f8b5 91
Kojto 102:da0ca467f8b5 92 // SPI defaults
Kojto 102:da0ca467f8b5 93 #define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
Kojto 102:da0ca467f8b5 94
Kojto 102:da0ca467f8b5 95 // EEPROM instruction set
Kojto 102:da0ca467f8b5 96 #define EEWRSR 0x0001 // Write status
Kojto 102:da0ca467f8b5 97 #define EEWRITE 0x0002 // Write data
Kojto 102:da0ca467f8b5 98 #define EEREAD 0x0003 // Read data
Kojto 102:da0ca467f8b5 99 #define EEWDI 0x0004 // Write disable
Kojto 102:da0ca467f8b5 100 #define EEWREN 0x0006 // Write enable
Kojto 102:da0ca467f8b5 101 #define EERDSR 0x0005 // Read status
Kojto 102:da0ca467f8b5 102
Kojto 102:da0ca467f8b5 103 // EEPROM status register flags
Kojto 102:da0ca467f8b5 104 #define EERDSR_WIP 0x0001 // Write in process
Kojto 102:da0ca467f8b5 105 #define EERDSR_WEL 0x0002 // Write enable latch
Kojto 102:da0ca467f8b5 106 #define EERDSR_BP0 0x0004 // Block protect 0
Kojto 102:da0ca467f8b5 107 #define EERDSR_BP1 0x0008 // Block protect 1
Kojto 102:da0ca467f8b5 108 #define EERDSR_WPEN 0x0080 // Write protect enable
Kojto 102:da0ca467f8b5 109
Kojto 102:da0ca467f8b5 110 /* ----------------------------------------------------------------
Kojto 102:da0ca467f8b5 111 *
Kojto 102:da0ca467f8b5 112 * Color LCD Support
Kojto 102:da0ca467f8b5 113 * =================
Kojto 102:da0ca467f8b5 114 */
Kojto 102:da0ca467f8b5 115
Kojto 102:da0ca467f8b5 116 // Color LCD Controller Internal Register addresses
Kojto 102:da0ca467f8b5 117 #define LSSPCS_BASE (0x4002804C) // LSSP chip select register
Kojto 102:da0ca467f8b5 118 #define LSSP_BASE (0x40021000) // LSSP Prime Cell
Kojto 102:da0ca467f8b5 119
Kojto 102:da0ca467f8b5 120 #define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
Kojto 102:da0ca467f8b5 121 #define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
Kojto 102:da0ca467f8b5 122 #define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
Kojto 102:da0ca467f8b5 123 #define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
Kojto 102:da0ca467f8b5 124 #define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
Kojto 102:da0ca467f8b5 125 #define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
Kojto 102:da0ca467f8b5 126 #define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
Kojto 102:da0ca467f8b5 127 #define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
Kojto 102:da0ca467f8b5 128 #define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
Kojto 102:da0ca467f8b5 129 #define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
Kojto 102:da0ca467f8b5 130 #define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
Kojto 102:da0ca467f8b5 131
Kojto 102:da0ca467f8b5 132 // LSSPCR0 Control register 0
Kojto 102:da0ca467f8b5 133 #define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
Kojto 102:da0ca467f8b5 134 #define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
Kojto 102:da0ca467f8b5 135 #define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
Kojto 102:da0ca467f8b5 136 #define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
Kojto 102:da0ca467f8b5 137 #define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
Kojto 102:da0ca467f8b5 138 #define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
Kojto 102:da0ca467f8b5 139
Kojto 102:da0ca467f8b5 140 // LSSPCR1 Control register 1
Kojto 102:da0ca467f8b5 141 #define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
Kojto 102:da0ca467f8b5 142 #define LSSPCR1_MS 0x0004 // Master or Slave mode
Kojto 102:da0ca467f8b5 143 #define LSSPCR1_SSE 0x0002 // Serial port enable
Kojto 102:da0ca467f8b5 144 #define LSSPCR1_LBM 0x0001 // Loop Back Mode
Kojto 102:da0ca467f8b5 145
Kojto 102:da0ca467f8b5 146 // LSSPSR Status register
Kojto 102:da0ca467f8b5 147 #define LSSPSR_BSY 0x0010 // Busy
Kojto 102:da0ca467f8b5 148 #define LSSPSR_RFF 0x0008 // Receive FIFO full
Kojto 102:da0ca467f8b5 149 #define LSSPSR_RNE 0x0004 // Receive FIFO not empty
Kojto 102:da0ca467f8b5 150 #define LSSPSR_TNF 0x0002 // Transmit FIFO not full
Kojto 102:da0ca467f8b5 151 #define LSSPSR_TFE 0x0001 // Transmit FIFO empty
Kojto 102:da0ca467f8b5 152
Kojto 102:da0ca467f8b5 153 // LSSPCPSR Clock prescale register
Kojto 102:da0ca467f8b5 154 #define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
Kojto 102:da0ca467f8b5 155
Kojto 102:da0ca467f8b5 156 // SPICS register
Kojto 102:da0ca467f8b5 157 #define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
Kojto 102:da0ca467f8b5 158 #define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
Kojto 102:da0ca467f8b5 159 #define LCD_RESET 0x0008 // RESET (CLCD_RESET)
Kojto 102:da0ca467f8b5 160 #define LCD_RS 0x0010 // RS (CLCD_RS)
Kojto 102:da0ca467f8b5 161 #define LCD_RD 0x0020 // RD (CLCD_RD)
Kojto 102:da0ca467f8b5 162 #define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
Kojto 102:da0ca467f8b5 163
Kojto 102:da0ca467f8b5 164 // SPI defaults
Kojto 102:da0ca467f8b5 165 #define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
Kojto 102:da0ca467f8b5 166 #define LSPI_START (0x70) // Start byte for SPI transfer
Kojto 102:da0ca467f8b5 167 #define LSPI_RD (0x01) // WR bit 1 within start
Kojto 102:da0ca467f8b5 168 #define LSPI_WR (0x00) // WR bit 0 within start
Kojto 102:da0ca467f8b5 169 #define LSPI_DATA (0x02) // RS bit 1 within start byte
Kojto 102:da0ca467f8b5 170 #define LSPI_INDEX (0x00) // RS bit 0 within start byte
Kojto 102:da0ca467f8b5 171
Kojto 102:da0ca467f8b5 172 // Screen size
Kojto 102:da0ca467f8b5 173 #define LCD_WIDTH 320 // Screen Width (in pixels)
Kojto 102:da0ca467f8b5 174 #define LCD_HEIGHT 240 // Screen Height (in pixels)