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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_L476VG/core_cm0.h@107:4f6c30876dfa, 2015-09-16 (annotated)

Committer:
Kojto
Date:
Wed Sep 16 15:32:31 2015 +0100
Revision:
107:4f6c30876dfa
Child:
110:165afa46840b
Release 107  of the mbed library



Changes:

- new platforms - DISCO_F746NG, DISCO_L476VG, NUCLEO_L476RG

- KL43Z - bugfix RTC init function

- K20 - SPI mode fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 107:4f6c30876dfa 1 /**************************************************************************//**
Kojto 107:4f6c30876dfa 2 * @file core_cm0.h
Kojto 107:4f6c30876dfa 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 107:4f6c30876dfa 4 * @version V3.20
Kojto 107:4f6c30876dfa 5 * @date 25. February 2013
Kojto 107:4f6c30876dfa 6 *
Kojto 107:4f6c30876dfa 7 * @note
Kojto 107:4f6c30876dfa 8 *
Kojto 107:4f6c30876dfa 9 ******************************************************************************/
Kojto 107:4f6c30876dfa 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 107:4f6c30876dfa 11
Kojto 107:4f6c30876dfa 12 All rights reserved.
Kojto 107:4f6c30876dfa 13 Redistribution and use in source and binary forms, with or without
Kojto 107:4f6c30876dfa 14 modification, are permitted provided that the following conditions are met:
Kojto 107:4f6c30876dfa 15 - Redistributions of source code must retain the above copyright
Kojto 107:4f6c30876dfa 16 notice, this list of conditions and the following disclaimer.
Kojto 107:4f6c30876dfa 17 - Redistributions in binary form must reproduce the above copyright
Kojto 107:4f6c30876dfa 18 notice, this list of conditions and the following disclaimer in the
Kojto 107:4f6c30876dfa 19 documentation and/or other materials provided with the distribution.
Kojto 107:4f6c30876dfa 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 107:4f6c30876dfa 21 to endorse or promote products derived from this software without
Kojto 107:4f6c30876dfa 22 specific prior written permission.
Kojto 107:4f6c30876dfa 23 *
Kojto 107:4f6c30876dfa 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 107:4f6c30876dfa 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 107:4f6c30876dfa 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 107:4f6c30876dfa 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 107:4f6c30876dfa 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 107:4f6c30876dfa 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 107:4f6c30876dfa 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 107:4f6c30876dfa 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 107:4f6c30876dfa 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 107:4f6c30876dfa 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 107:4f6c30876dfa 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 107:4f6c30876dfa 35 ---------------------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 36
Kojto 107:4f6c30876dfa 37
Kojto 107:4f6c30876dfa 38 #if defined ( __ICCARM__ )
Kojto 107:4f6c30876dfa 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 107:4f6c30876dfa 40 #endif
Kojto 107:4f6c30876dfa 41
Kojto 107:4f6c30876dfa 42 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 43 extern "C" {
Kojto 107:4f6c30876dfa 44 #endif
Kojto 107:4f6c30876dfa 45
Kojto 107:4f6c30876dfa 46 #ifndef __CORE_CM0_H_GENERIC
Kojto 107:4f6c30876dfa 47 #define __CORE_CM0_H_GENERIC
Kojto 107:4f6c30876dfa 48
Kojto 107:4f6c30876dfa 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 107:4f6c30876dfa 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 107:4f6c30876dfa 51
Kojto 107:4f6c30876dfa 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 107:4f6c30876dfa 53 Function definitions in header files are used to allow 'inlining'.
Kojto 107:4f6c30876dfa 54
Kojto 107:4f6c30876dfa 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 107:4f6c30876dfa 56 Unions are used for effective representation of core registers.
Kojto 107:4f6c30876dfa 57
Kojto 107:4f6c30876dfa 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 107:4f6c30876dfa 59 Function-like macros are used to allow more efficient code.
Kojto 107:4f6c30876dfa 60 */
Kojto 107:4f6c30876dfa 61
Kojto 107:4f6c30876dfa 62
Kojto 107:4f6c30876dfa 63 /*******************************************************************************
Kojto 107:4f6c30876dfa 64 * CMSIS definitions
Kojto 107:4f6c30876dfa 65 ******************************************************************************/
Kojto 107:4f6c30876dfa 66 /** \ingroup Cortex_M0
Kojto 107:4f6c30876dfa 67 @{
Kojto 107:4f6c30876dfa 68 */
Kojto 107:4f6c30876dfa 69
Kojto 107:4f6c30876dfa 70 /* CMSIS CM0 definitions */
Kojto 107:4f6c30876dfa 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 107:4f6c30876dfa 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 107:4f6c30876dfa 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 107:4f6c30876dfa 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 107:4f6c30876dfa 75
Kojto 107:4f6c30876dfa 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 107:4f6c30876dfa 77
Kojto 107:4f6c30876dfa 78
Kojto 107:4f6c30876dfa 79 #if defined ( __CC_ARM )
Kojto 107:4f6c30876dfa 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 107:4f6c30876dfa 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 107:4f6c30876dfa 82 #define __STATIC_INLINE static __inline
Kojto 107:4f6c30876dfa 83
Kojto 107:4f6c30876dfa 84 #elif defined ( __ICCARM__ )
Kojto 107:4f6c30876dfa 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 107:4f6c30876dfa 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 107:4f6c30876dfa 87 #define __STATIC_INLINE static inline
Kojto 107:4f6c30876dfa 88
Kojto 107:4f6c30876dfa 89 #elif defined ( __GNUC__ )
Kojto 107:4f6c30876dfa 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 107:4f6c30876dfa 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 107:4f6c30876dfa 92 #define __STATIC_INLINE static inline
Kojto 107:4f6c30876dfa 93
Kojto 107:4f6c30876dfa 94 #elif defined ( __TASKING__ )
Kojto 107:4f6c30876dfa 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 107:4f6c30876dfa 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 107:4f6c30876dfa 97 #define __STATIC_INLINE static inline
Kojto 107:4f6c30876dfa 98
Kojto 107:4f6c30876dfa 99 #endif
Kojto 107:4f6c30876dfa 100
Kojto 107:4f6c30876dfa 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 107:4f6c30876dfa 102 */
Kojto 107:4f6c30876dfa 103 #define __FPU_USED 0
Kojto 107:4f6c30876dfa 104
Kojto 107:4f6c30876dfa 105 #if defined ( __CC_ARM )
Kojto 107:4f6c30876dfa 106 #if defined __TARGET_FPU_VFP
Kojto 107:4f6c30876dfa 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 107:4f6c30876dfa 108 #endif
Kojto 107:4f6c30876dfa 109
Kojto 107:4f6c30876dfa 110 #elif defined ( __ICCARM__ )
Kojto 107:4f6c30876dfa 111 #if defined __ARMVFP__
Kojto 107:4f6c30876dfa 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 107:4f6c30876dfa 113 #endif
Kojto 107:4f6c30876dfa 114
Kojto 107:4f6c30876dfa 115 #elif defined ( __GNUC__ )
Kojto 107:4f6c30876dfa 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 107:4f6c30876dfa 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 107:4f6c30876dfa 118 #endif
Kojto 107:4f6c30876dfa 119
Kojto 107:4f6c30876dfa 120 #elif defined ( __TASKING__ )
Kojto 107:4f6c30876dfa 121 #if defined __FPU_VFP__
Kojto 107:4f6c30876dfa 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 107:4f6c30876dfa 123 #endif
Kojto 107:4f6c30876dfa 124 #endif
Kojto 107:4f6c30876dfa 125
Kojto 107:4f6c30876dfa 126 #include <stdint.h> /* standard types definitions */
Kojto 107:4f6c30876dfa 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 107:4f6c30876dfa 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 107:4f6c30876dfa 129
Kojto 107:4f6c30876dfa 130 #endif /* __CORE_CM0_H_GENERIC */
Kojto 107:4f6c30876dfa 131
Kojto 107:4f6c30876dfa 132 #ifndef __CMSIS_GENERIC
Kojto 107:4f6c30876dfa 133
Kojto 107:4f6c30876dfa 134 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 107:4f6c30876dfa 135 #define __CORE_CM0_H_DEPENDANT
Kojto 107:4f6c30876dfa 136
Kojto 107:4f6c30876dfa 137 /* check device defines and use defaults */
Kojto 107:4f6c30876dfa 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 107:4f6c30876dfa 139 #ifndef __CM0_REV
Kojto 107:4f6c30876dfa 140 #define __CM0_REV 0x0000
Kojto 107:4f6c30876dfa 141 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 107:4f6c30876dfa 142 #endif
Kojto 107:4f6c30876dfa 143
Kojto 107:4f6c30876dfa 144 #ifndef __NVIC_PRIO_BITS
Kojto 107:4f6c30876dfa 145 #define __NVIC_PRIO_BITS 2
Kojto 107:4f6c30876dfa 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 107:4f6c30876dfa 147 #endif
Kojto 107:4f6c30876dfa 148
Kojto 107:4f6c30876dfa 149 #ifndef __Vendor_SysTickConfig
Kojto 107:4f6c30876dfa 150 #define __Vendor_SysTickConfig 0
Kojto 107:4f6c30876dfa 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 107:4f6c30876dfa 152 #endif
Kojto 107:4f6c30876dfa 153 #endif
Kojto 107:4f6c30876dfa 154
Kojto 107:4f6c30876dfa 155 /* IO definitions (access restrictions to peripheral registers) */
Kojto 107:4f6c30876dfa 156 /**
Kojto 107:4f6c30876dfa 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 107:4f6c30876dfa 158
Kojto 107:4f6c30876dfa 159 <strong>IO Type Qualifiers</strong> are used
Kojto 107:4f6c30876dfa 160 \li to specify the access to peripheral variables.
Kojto 107:4f6c30876dfa 161 \li for automatic generation of peripheral register debug information.
Kojto 107:4f6c30876dfa 162 */
Kojto 107:4f6c30876dfa 163 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 164 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 107:4f6c30876dfa 165 #else
Kojto 107:4f6c30876dfa 166 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 107:4f6c30876dfa 167 #endif
Kojto 107:4f6c30876dfa 168 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 107:4f6c30876dfa 169 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 107:4f6c30876dfa 170
Kojto 107:4f6c30876dfa 171 /*@} end of group Cortex_M0 */
Kojto 107:4f6c30876dfa 172
Kojto 107:4f6c30876dfa 173
Kojto 107:4f6c30876dfa 174
Kojto 107:4f6c30876dfa 175 /*******************************************************************************
Kojto 107:4f6c30876dfa 176 * Register Abstraction
Kojto 107:4f6c30876dfa 177 Core Register contain:
Kojto 107:4f6c30876dfa 178 - Core Register
Kojto 107:4f6c30876dfa 179 - Core NVIC Register
Kojto 107:4f6c30876dfa 180 - Core SCB Register
Kojto 107:4f6c30876dfa 181 - Core SysTick Register
Kojto 107:4f6c30876dfa 182 ******************************************************************************/
Kojto 107:4f6c30876dfa 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 107:4f6c30876dfa 184 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 107:4f6c30876dfa 185 */
Kojto 107:4f6c30876dfa 186
Kojto 107:4f6c30876dfa 187 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 188 \defgroup CMSIS_CORE Status and Control Registers
Kojto 107:4f6c30876dfa 189 \brief Core Register type definitions.
Kojto 107:4f6c30876dfa 190 @{
Kojto 107:4f6c30876dfa 191 */
Kojto 107:4f6c30876dfa 192
Kojto 107:4f6c30876dfa 193 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 107:4f6c30876dfa 194 */
Kojto 107:4f6c30876dfa 195 typedef union
Kojto 107:4f6c30876dfa 196 {
Kojto 107:4f6c30876dfa 197 struct
Kojto 107:4f6c30876dfa 198 {
Kojto 107:4f6c30876dfa 199 #if (__CORTEX_M != 0x04)
Kojto 107:4f6c30876dfa 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 107:4f6c30876dfa 201 #else
Kojto 107:4f6c30876dfa 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 107:4f6c30876dfa 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 107:4f6c30876dfa 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 107:4f6c30876dfa 205 #endif
Kojto 107:4f6c30876dfa 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 107:4f6c30876dfa 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 107:4f6c30876dfa 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 107:4f6c30876dfa 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 107:4f6c30876dfa 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 107:4f6c30876dfa 211 } b; /*!< Structure used for bit access */
Kojto 107:4f6c30876dfa 212 uint32_t w; /*!< Type used for word access */
Kojto 107:4f6c30876dfa 213 } APSR_Type;
Kojto 107:4f6c30876dfa 214
Kojto 107:4f6c30876dfa 215
Kojto 107:4f6c30876dfa 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 107:4f6c30876dfa 217 */
Kojto 107:4f6c30876dfa 218 typedef union
Kojto 107:4f6c30876dfa 219 {
Kojto 107:4f6c30876dfa 220 struct
Kojto 107:4f6c30876dfa 221 {
Kojto 107:4f6c30876dfa 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 107:4f6c30876dfa 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 107:4f6c30876dfa 224 } b; /*!< Structure used for bit access */
Kojto 107:4f6c30876dfa 225 uint32_t w; /*!< Type used for word access */
Kojto 107:4f6c30876dfa 226 } IPSR_Type;
Kojto 107:4f6c30876dfa 227
Kojto 107:4f6c30876dfa 228
Kojto 107:4f6c30876dfa 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 107:4f6c30876dfa 230 */
Kojto 107:4f6c30876dfa 231 typedef union
Kojto 107:4f6c30876dfa 232 {
Kojto 107:4f6c30876dfa 233 struct
Kojto 107:4f6c30876dfa 234 {
Kojto 107:4f6c30876dfa 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 107:4f6c30876dfa 236 #if (__CORTEX_M != 0x04)
Kojto 107:4f6c30876dfa 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 107:4f6c30876dfa 238 #else
Kojto 107:4f6c30876dfa 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 107:4f6c30876dfa 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 107:4f6c30876dfa 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 107:4f6c30876dfa 242 #endif
Kojto 107:4f6c30876dfa 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 107:4f6c30876dfa 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 107:4f6c30876dfa 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 107:4f6c30876dfa 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 107:4f6c30876dfa 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 107:4f6c30876dfa 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 107:4f6c30876dfa 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 107:4f6c30876dfa 250 } b; /*!< Structure used for bit access */
Kojto 107:4f6c30876dfa 251 uint32_t w; /*!< Type used for word access */
Kojto 107:4f6c30876dfa 252 } xPSR_Type;
Kojto 107:4f6c30876dfa 253
Kojto 107:4f6c30876dfa 254
Kojto 107:4f6c30876dfa 255 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 107:4f6c30876dfa 256 */
Kojto 107:4f6c30876dfa 257 typedef union
Kojto 107:4f6c30876dfa 258 {
Kojto 107:4f6c30876dfa 259 struct
Kojto 107:4f6c30876dfa 260 {
Kojto 107:4f6c30876dfa 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 107:4f6c30876dfa 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 107:4f6c30876dfa 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 107:4f6c30876dfa 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 107:4f6c30876dfa 265 } b; /*!< Structure used for bit access */
Kojto 107:4f6c30876dfa 266 uint32_t w; /*!< Type used for word access */
Kojto 107:4f6c30876dfa 267 } CONTROL_Type;
Kojto 107:4f6c30876dfa 268
Kojto 107:4f6c30876dfa 269 /*@} end of group CMSIS_CORE */
Kojto 107:4f6c30876dfa 270
Kojto 107:4f6c30876dfa 271
Kojto 107:4f6c30876dfa 272 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 107:4f6c30876dfa 274 \brief Type definitions for the NVIC Registers
Kojto 107:4f6c30876dfa 275 @{
Kojto 107:4f6c30876dfa 276 */
Kojto 107:4f6c30876dfa 277
Kojto 107:4f6c30876dfa 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 107:4f6c30876dfa 279 */
Kojto 107:4f6c30876dfa 280 typedef struct
Kojto 107:4f6c30876dfa 281 {
Kojto 107:4f6c30876dfa 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 107:4f6c30876dfa 283 uint32_t RESERVED0[31];
Kojto 107:4f6c30876dfa 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 107:4f6c30876dfa 285 uint32_t RSERVED1[31];
Kojto 107:4f6c30876dfa 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 107:4f6c30876dfa 287 uint32_t RESERVED2[31];
Kojto 107:4f6c30876dfa 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 107:4f6c30876dfa 289 uint32_t RESERVED3[31];
Kojto 107:4f6c30876dfa 290 uint32_t RESERVED4[64];
Kojto 107:4f6c30876dfa 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 107:4f6c30876dfa 292 } NVIC_Type;
Kojto 107:4f6c30876dfa 293
Kojto 107:4f6c30876dfa 294 /*@} end of group CMSIS_NVIC */
Kojto 107:4f6c30876dfa 295
Kojto 107:4f6c30876dfa 296
Kojto 107:4f6c30876dfa 297 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 298 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 107:4f6c30876dfa 299 \brief Type definitions for the System Control Block Registers
Kojto 107:4f6c30876dfa 300 @{
Kojto 107:4f6c30876dfa 301 */
Kojto 107:4f6c30876dfa 302
Kojto 107:4f6c30876dfa 303 /** \brief Structure type to access the System Control Block (SCB).
Kojto 107:4f6c30876dfa 304 */
Kojto 107:4f6c30876dfa 305 typedef struct
Kojto 107:4f6c30876dfa 306 {
Kojto 107:4f6c30876dfa 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 107:4f6c30876dfa 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 107:4f6c30876dfa 309 uint32_t RESERVED0;
Kojto 107:4f6c30876dfa 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 107:4f6c30876dfa 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 107:4f6c30876dfa 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 107:4f6c30876dfa 313 uint32_t RESERVED1;
Kojto 107:4f6c30876dfa 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 107:4f6c30876dfa 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 107:4f6c30876dfa 316 } SCB_Type;
Kojto 107:4f6c30876dfa 317
Kojto 107:4f6c30876dfa 318 /* SCB CPUID Register Definitions */
Kojto 107:4f6c30876dfa 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 107:4f6c30876dfa 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 107:4f6c30876dfa 321
Kojto 107:4f6c30876dfa 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 107:4f6c30876dfa 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 107:4f6c30876dfa 324
Kojto 107:4f6c30876dfa 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 107:4f6c30876dfa 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 107:4f6c30876dfa 327
Kojto 107:4f6c30876dfa 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 107:4f6c30876dfa 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 107:4f6c30876dfa 330
Kojto 107:4f6c30876dfa 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 107:4f6c30876dfa 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 107:4f6c30876dfa 333
Kojto 107:4f6c30876dfa 334 /* SCB Interrupt Control State Register Definitions */
Kojto 107:4f6c30876dfa 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 107:4f6c30876dfa 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 107:4f6c30876dfa 337
Kojto 107:4f6c30876dfa 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 107:4f6c30876dfa 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 107:4f6c30876dfa 340
Kojto 107:4f6c30876dfa 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 107:4f6c30876dfa 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 107:4f6c30876dfa 343
Kojto 107:4f6c30876dfa 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 107:4f6c30876dfa 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 107:4f6c30876dfa 346
Kojto 107:4f6c30876dfa 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 107:4f6c30876dfa 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 107:4f6c30876dfa 349
Kojto 107:4f6c30876dfa 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 107:4f6c30876dfa 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 107:4f6c30876dfa 352
Kojto 107:4f6c30876dfa 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 107:4f6c30876dfa 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 107:4f6c30876dfa 355
Kojto 107:4f6c30876dfa 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 107:4f6c30876dfa 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 107:4f6c30876dfa 358
Kojto 107:4f6c30876dfa 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 107:4f6c30876dfa 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 107:4f6c30876dfa 361
Kojto 107:4f6c30876dfa 362 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 107:4f6c30876dfa 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 107:4f6c30876dfa 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 107:4f6c30876dfa 365
Kojto 107:4f6c30876dfa 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 107:4f6c30876dfa 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 107:4f6c30876dfa 368
Kojto 107:4f6c30876dfa 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 107:4f6c30876dfa 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 107:4f6c30876dfa 371
Kojto 107:4f6c30876dfa 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 107:4f6c30876dfa 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 107:4f6c30876dfa 374
Kojto 107:4f6c30876dfa 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 107:4f6c30876dfa 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 107:4f6c30876dfa 377
Kojto 107:4f6c30876dfa 378 /* SCB System Control Register Definitions */
Kojto 107:4f6c30876dfa 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 107:4f6c30876dfa 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 107:4f6c30876dfa 381
Kojto 107:4f6c30876dfa 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 107:4f6c30876dfa 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 107:4f6c30876dfa 384
Kojto 107:4f6c30876dfa 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 107:4f6c30876dfa 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 107:4f6c30876dfa 387
Kojto 107:4f6c30876dfa 388 /* SCB Configuration Control Register Definitions */
Kojto 107:4f6c30876dfa 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 107:4f6c30876dfa 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 107:4f6c30876dfa 391
Kojto 107:4f6c30876dfa 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 107:4f6c30876dfa 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 107:4f6c30876dfa 394
Kojto 107:4f6c30876dfa 395 /* SCB System Handler Control and State Register Definitions */
Kojto 107:4f6c30876dfa 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 107:4f6c30876dfa 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 107:4f6c30876dfa 398
Kojto 107:4f6c30876dfa 399 /*@} end of group CMSIS_SCB */
Kojto 107:4f6c30876dfa 400
Kojto 107:4f6c30876dfa 401
Kojto 107:4f6c30876dfa 402 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 107:4f6c30876dfa 404 \brief Type definitions for the System Timer Registers.
Kojto 107:4f6c30876dfa 405 @{
Kojto 107:4f6c30876dfa 406 */
Kojto 107:4f6c30876dfa 407
Kojto 107:4f6c30876dfa 408 /** \brief Structure type to access the System Timer (SysTick).
Kojto 107:4f6c30876dfa 409 */
Kojto 107:4f6c30876dfa 410 typedef struct
Kojto 107:4f6c30876dfa 411 {
Kojto 107:4f6c30876dfa 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 107:4f6c30876dfa 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 107:4f6c30876dfa 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 107:4f6c30876dfa 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 107:4f6c30876dfa 416 } SysTick_Type;
Kojto 107:4f6c30876dfa 417
Kojto 107:4f6c30876dfa 418 /* SysTick Control / Status Register Definitions */
Kojto 107:4f6c30876dfa 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 107:4f6c30876dfa 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 107:4f6c30876dfa 421
Kojto 107:4f6c30876dfa 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 107:4f6c30876dfa 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 107:4f6c30876dfa 424
Kojto 107:4f6c30876dfa 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 107:4f6c30876dfa 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 107:4f6c30876dfa 427
Kojto 107:4f6c30876dfa 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 107:4f6c30876dfa 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 107:4f6c30876dfa 430
Kojto 107:4f6c30876dfa 431 /* SysTick Reload Register Definitions */
Kojto 107:4f6c30876dfa 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 107:4f6c30876dfa 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 107:4f6c30876dfa 434
Kojto 107:4f6c30876dfa 435 /* SysTick Current Register Definitions */
Kojto 107:4f6c30876dfa 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 107:4f6c30876dfa 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 107:4f6c30876dfa 438
Kojto 107:4f6c30876dfa 439 /* SysTick Calibration Register Definitions */
Kojto 107:4f6c30876dfa 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 107:4f6c30876dfa 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 107:4f6c30876dfa 442
Kojto 107:4f6c30876dfa 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 107:4f6c30876dfa 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 107:4f6c30876dfa 445
Kojto 107:4f6c30876dfa 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 107:4f6c30876dfa 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 107:4f6c30876dfa 448
Kojto 107:4f6c30876dfa 449 /*@} end of group CMSIS_SysTick */
Kojto 107:4f6c30876dfa 450
Kojto 107:4f6c30876dfa 451
Kojto 107:4f6c30876dfa 452 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 107:4f6c30876dfa 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 107:4f6c30876dfa 455 are only accessible over DAP and not via processor. Therefore
Kojto 107:4f6c30876dfa 456 they are not covered by the Cortex-M0 header file.
Kojto 107:4f6c30876dfa 457 @{
Kojto 107:4f6c30876dfa 458 */
Kojto 107:4f6c30876dfa 459 /*@} end of group CMSIS_CoreDebug */
Kojto 107:4f6c30876dfa 460
Kojto 107:4f6c30876dfa 461
Kojto 107:4f6c30876dfa 462 /** \ingroup CMSIS_core_register
Kojto 107:4f6c30876dfa 463 \defgroup CMSIS_core_base Core Definitions
Kojto 107:4f6c30876dfa 464 \brief Definitions for base addresses, unions, and structures.
Kojto 107:4f6c30876dfa 465 @{
Kojto 107:4f6c30876dfa 466 */
Kojto 107:4f6c30876dfa 467
Kojto 107:4f6c30876dfa 468 /* Memory mapping of Cortex-M0 Hardware */
Kojto 107:4f6c30876dfa 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 107:4f6c30876dfa 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 107:4f6c30876dfa 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 107:4f6c30876dfa 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 107:4f6c30876dfa 473
Kojto 107:4f6c30876dfa 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 107:4f6c30876dfa 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 107:4f6c30876dfa 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 107:4f6c30876dfa 477
Kojto 107:4f6c30876dfa 478
Kojto 107:4f6c30876dfa 479 /*@} */
Kojto 107:4f6c30876dfa 480
Kojto 107:4f6c30876dfa 481
Kojto 107:4f6c30876dfa 482
Kojto 107:4f6c30876dfa 483 /*******************************************************************************
Kojto 107:4f6c30876dfa 484 * Hardware Abstraction Layer
Kojto 107:4f6c30876dfa 485 Core Function Interface contains:
Kojto 107:4f6c30876dfa 486 - Core NVIC Functions
Kojto 107:4f6c30876dfa 487 - Core SysTick Functions
Kojto 107:4f6c30876dfa 488 - Core Register Access Functions
Kojto 107:4f6c30876dfa 489 ******************************************************************************/
Kojto 107:4f6c30876dfa 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 107:4f6c30876dfa 491 */
Kojto 107:4f6c30876dfa 492
Kojto 107:4f6c30876dfa 493
Kojto 107:4f6c30876dfa 494
Kojto 107:4f6c30876dfa 495 /* ########################## NVIC functions #################################### */
Kojto 107:4f6c30876dfa 496 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 107:4f6c30876dfa 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 107:4f6c30876dfa 498 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 107:4f6c30876dfa 499 @{
Kojto 107:4f6c30876dfa 500 */
Kojto 107:4f6c30876dfa 501
Kojto 107:4f6c30876dfa 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 107:4f6c30876dfa 503 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 107:4f6c30876dfa 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 107:4f6c30876dfa 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 107:4f6c30876dfa 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 107:4f6c30876dfa 507
Kojto 107:4f6c30876dfa 508
Kojto 107:4f6c30876dfa 509 /** \brief Enable External Interrupt
Kojto 107:4f6c30876dfa 510
Kojto 107:4f6c30876dfa 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 107:4f6c30876dfa 512
Kojto 107:4f6c30876dfa 513 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 107:4f6c30876dfa 514 */
Kojto 107:4f6c30876dfa 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 516 {
Kojto 107:4f6c30876dfa 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 107:4f6c30876dfa 518 }
Kojto 107:4f6c30876dfa 519
Kojto 107:4f6c30876dfa 520
Kojto 107:4f6c30876dfa 521 /** \brief Disable External Interrupt
Kojto 107:4f6c30876dfa 522
Kojto 107:4f6c30876dfa 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 107:4f6c30876dfa 524
Kojto 107:4f6c30876dfa 525 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 107:4f6c30876dfa 526 */
Kojto 107:4f6c30876dfa 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 528 {
Kojto 107:4f6c30876dfa 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 107:4f6c30876dfa 530 }
Kojto 107:4f6c30876dfa 531
Kojto 107:4f6c30876dfa 532
Kojto 107:4f6c30876dfa 533 /** \brief Get Pending Interrupt
Kojto 107:4f6c30876dfa 534
Kojto 107:4f6c30876dfa 535 The function reads the pending register in the NVIC and returns the pending bit
Kojto 107:4f6c30876dfa 536 for the specified interrupt.
Kojto 107:4f6c30876dfa 537
Kojto 107:4f6c30876dfa 538 \param [in] IRQn Interrupt number.
Kojto 107:4f6c30876dfa 539
Kojto 107:4f6c30876dfa 540 \return 0 Interrupt status is not pending.
Kojto 107:4f6c30876dfa 541 \return 1 Interrupt status is pending.
Kojto 107:4f6c30876dfa 542 */
Kojto 107:4f6c30876dfa 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 544 {
Kojto 107:4f6c30876dfa 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 107:4f6c30876dfa 546 }
Kojto 107:4f6c30876dfa 547
Kojto 107:4f6c30876dfa 548
Kojto 107:4f6c30876dfa 549 /** \brief Set Pending Interrupt
Kojto 107:4f6c30876dfa 550
Kojto 107:4f6c30876dfa 551 The function sets the pending bit of an external interrupt.
Kojto 107:4f6c30876dfa 552
Kojto 107:4f6c30876dfa 553 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 107:4f6c30876dfa 554 */
Kojto 107:4f6c30876dfa 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 556 {
Kojto 107:4f6c30876dfa 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 107:4f6c30876dfa 558 }
Kojto 107:4f6c30876dfa 559
Kojto 107:4f6c30876dfa 560
Kojto 107:4f6c30876dfa 561 /** \brief Clear Pending Interrupt
Kojto 107:4f6c30876dfa 562
Kojto 107:4f6c30876dfa 563 The function clears the pending bit of an external interrupt.
Kojto 107:4f6c30876dfa 564
Kojto 107:4f6c30876dfa 565 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 107:4f6c30876dfa 566 */
Kojto 107:4f6c30876dfa 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 568 {
Kojto 107:4f6c30876dfa 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 107:4f6c30876dfa 570 }
Kojto 107:4f6c30876dfa 571
Kojto 107:4f6c30876dfa 572
Kojto 107:4f6c30876dfa 573 /** \brief Set Interrupt Priority
Kojto 107:4f6c30876dfa 574
Kojto 107:4f6c30876dfa 575 The function sets the priority of an interrupt.
Kojto 107:4f6c30876dfa 576
Kojto 107:4f6c30876dfa 577 \note The priority cannot be set for every core interrupt.
Kojto 107:4f6c30876dfa 578
Kojto 107:4f6c30876dfa 579 \param [in] IRQn Interrupt number.
Kojto 107:4f6c30876dfa 580 \param [in] priority Priority to set.
Kojto 107:4f6c30876dfa 581 */
Kojto 107:4f6c30876dfa 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 107:4f6c30876dfa 583 {
Kojto 107:4f6c30876dfa 584 if(IRQn < 0) {
Kojto 107:4f6c30876dfa 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 107:4f6c30876dfa 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 107:4f6c30876dfa 587 else {
Kojto 107:4f6c30876dfa 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 107:4f6c30876dfa 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 107:4f6c30876dfa 590 }
Kojto 107:4f6c30876dfa 591
Kojto 107:4f6c30876dfa 592
Kojto 107:4f6c30876dfa 593 /** \brief Get Interrupt Priority
Kojto 107:4f6c30876dfa 594
Kojto 107:4f6c30876dfa 595 The function reads the priority of an interrupt. The interrupt
Kojto 107:4f6c30876dfa 596 number can be positive to specify an external (device specific)
Kojto 107:4f6c30876dfa 597 interrupt, or negative to specify an internal (core) interrupt.
Kojto 107:4f6c30876dfa 598
Kojto 107:4f6c30876dfa 599
Kojto 107:4f6c30876dfa 600 \param [in] IRQn Interrupt number.
Kojto 107:4f6c30876dfa 601 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 107:4f6c30876dfa 602 priority bits of the microcontroller.
Kojto 107:4f6c30876dfa 603 */
Kojto 107:4f6c30876dfa 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 107:4f6c30876dfa 605 {
Kojto 107:4f6c30876dfa 606
Kojto 107:4f6c30876dfa 607 if(IRQn < 0) {
Kojto 107:4f6c30876dfa 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 107:4f6c30876dfa 609 else {
Kojto 107:4f6c30876dfa 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 107:4f6c30876dfa 611 }
Kojto 107:4f6c30876dfa 612
Kojto 107:4f6c30876dfa 613
Kojto 107:4f6c30876dfa 614 /** \brief System Reset
Kojto 107:4f6c30876dfa 615
Kojto 107:4f6c30876dfa 616 The function initiates a system reset request to reset the MCU.
Kojto 107:4f6c30876dfa 617 */
Kojto 107:4f6c30876dfa 618 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 107:4f6c30876dfa 619 {
Kojto 107:4f6c30876dfa 620 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 107:4f6c30876dfa 621 buffered write are completed before reset */
Kojto 107:4f6c30876dfa 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 107:4f6c30876dfa 623 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 107:4f6c30876dfa 624 __DSB(); /* Ensure completion of memory access */
Kojto 107:4f6c30876dfa 625 while(1); /* wait until reset */
Kojto 107:4f6c30876dfa 626 }
Kojto 107:4f6c30876dfa 627
Kojto 107:4f6c30876dfa 628 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 107:4f6c30876dfa 629
Kojto 107:4f6c30876dfa 630
Kojto 107:4f6c30876dfa 631
Kojto 107:4f6c30876dfa 632 /* ################################## SysTick function ############################################ */
Kojto 107:4f6c30876dfa 633 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 107:4f6c30876dfa 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 107:4f6c30876dfa 635 \brief Functions that configure the System.
Kojto 107:4f6c30876dfa 636 @{
Kojto 107:4f6c30876dfa 637 */
Kojto 107:4f6c30876dfa 638
Kojto 107:4f6c30876dfa 639 #if (__Vendor_SysTickConfig == 0)
Kojto 107:4f6c30876dfa 640
Kojto 107:4f6c30876dfa 641 /** \brief System Tick Configuration
Kojto 107:4f6c30876dfa 642
Kojto 107:4f6c30876dfa 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 107:4f6c30876dfa 644 Counter is in free running mode to generate periodic interrupts.
Kojto 107:4f6c30876dfa 645
Kojto 107:4f6c30876dfa 646 \param [in] ticks Number of ticks between two interrupts.
Kojto 107:4f6c30876dfa 647
Kojto 107:4f6c30876dfa 648 \return 0 Function succeeded.
Kojto 107:4f6c30876dfa 649 \return 1 Function failed.
Kojto 107:4f6c30876dfa 650
Kojto 107:4f6c30876dfa 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 107:4f6c30876dfa 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 107:4f6c30876dfa 653 must contain a vendor-specific implementation of this function.
Kojto 107:4f6c30876dfa 654
Kojto 107:4f6c30876dfa 655 */
Kojto 107:4f6c30876dfa 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 107:4f6c30876dfa 657 {
Kojto 107:4f6c30876dfa 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 107:4f6c30876dfa 659
Kojto 107:4f6c30876dfa 660 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 107:4f6c30876dfa 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 107:4f6c30876dfa 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 107:4f6c30876dfa 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 107:4f6c30876dfa 664 SysTick_CTRL_TICKINT_Msk |
Kojto 107:4f6c30876dfa 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 107:4f6c30876dfa 666 return (0); /* Function successful */
Kojto 107:4f6c30876dfa 667 }
Kojto 107:4f6c30876dfa 668
Kojto 107:4f6c30876dfa 669 #endif
Kojto 107:4f6c30876dfa 670
Kojto 107:4f6c30876dfa 671 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 107:4f6c30876dfa 672
Kojto 107:4f6c30876dfa 673
Kojto 107:4f6c30876dfa 674
Kojto 107:4f6c30876dfa 675
Kojto 107:4f6c30876dfa 676 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 107:4f6c30876dfa 677
Kojto 107:4f6c30876dfa 678 #endif /* __CMSIS_GENERIC */
Kojto 107:4f6c30876dfa 679
Kojto 107:4f6c30876dfa 680 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 681 }
Kojto 107:4f6c30876dfa 682 #endif