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TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h@142:4eea097334d6, 2017-05-10 (annotated)
- Committer:
- Anna Bridge
- Date:
- Wed May 10 11:31:27 2017 +0100
- Revision:
- 142:4eea097334d6
Release 142 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
4059: [Silicon Labs] Rename targets https://github.com/ARMmbed/mbed-os/pull/4059
4187: [NCS36510] Reduce default heap size allocated by IAR to 1/4 of RAM https://github.com/ARMmbed/mbed-os/pull/4187
4225: fixed missing device_name for xDot and removed progen https://github.com/ARMmbed/mbed-os/pull/4225
4251: Fix C++11 build error w/ u-blox EVK-ODIN-W2 https://github.com/ARMmbed/mbed-os/pull/4251
4236: STM32 Fixed warning related to __packed redefinition https://github.com/ARMmbed/mbed-os/pull/4236
4190: LPC4088: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/4190
4260: Inherit Xadow M0 target from LPC11U35_501 https://github.com/ARMmbed/mbed-os/pull/4260
4249: Add consistent button names across targets https://github.com/ARMmbed/mbed-os/pull/4249
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg12p_csen.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG12P_CSEN register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG12P_CSEN |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG12P_CSEN Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IOM uint32_t TIMCTRL; /**< Timing Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | __IOM uint32_t CMD; /**< Command Register */ |
| Anna Bridge |
142:4eea097334d6 | 46 | __IM uint32_t STATUS; /**< Status Register */ |
| Anna Bridge |
142:4eea097334d6 | 47 | __IOM uint32_t PRSSEL; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 48 | __IOM uint32_t DATA; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 49 | __IOM uint32_t SCANMASK0; /**< CSEN Channel Scan Mask */ |
| Anna Bridge |
142:4eea097334d6 | 50 | __IOM uint32_t SCANINPUTSEL0; /**< Input Channel Configuration register for Scan mode */ |
| Anna Bridge |
142:4eea097334d6 | 51 | __IOM uint32_t SCANMASK1; /**< CSEN Channel Scan Mask */ |
| Anna Bridge |
142:4eea097334d6 | 52 | __IOM uint32_t SCANINPUTSEL1; /**< Input Channel Configuration register for Scan mode */ |
| Anna Bridge |
142:4eea097334d6 | 53 | __IM uint32_t APORTREQ; /**< APORT Request Status Register */ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ |
| Anna Bridge |
142:4eea097334d6 | 55 | __IOM uint32_t CMPTHR; /**< CSEN Comparator Threshold */ |
| Anna Bridge |
142:4eea097334d6 | 56 | __IOM uint32_t EMA; /**< Exponential Moving Average */ |
| Anna Bridge |
142:4eea097334d6 | 57 | __IOM uint32_t EMACTRL; /**< Exponential Moving Average */ |
| Anna Bridge |
142:4eea097334d6 | 58 | __IOM uint32_t SINGLECTRL; /**< CSEN Single Conversion Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 59 | __IOM uint32_t DMBASELINE; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 60 | __IOM uint32_t DMCFG; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 61 | __IOM uint32_t ANACTRL; /**< Analog Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 62 | |
| Anna Bridge |
142:4eea097334d6 | 63 | uint32_t RESERVED0[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 64 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| Anna Bridge |
142:4eea097334d6 | 65 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| Anna Bridge |
142:4eea097334d6 | 66 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 67 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| Anna Bridge |
142:4eea097334d6 | 68 | } CSEN_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 69 | |
| Anna Bridge |
142:4eea097334d6 | 70 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 71 | * @defgroup EFR32MG12P_CSEN_BitFields |
| Anna Bridge |
142:4eea097334d6 | 72 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 73 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 74 | |
| Anna Bridge |
142:4eea097334d6 | 75 | /* Bit fields for CSEN CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 76 | #define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 77 | #define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 86 | #define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 87 | #define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */ |
| Anna Bridge |
142:4eea097334d6 | 88 | #define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 100 | #define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 101 | #define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 116 | #define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 117 | #define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */ |
| Anna Bridge |
142:4eea097334d6 | 121 | #define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */ |
| Anna Bridge |
142:4eea097334d6 | 122 | #define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 124 | #define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 125 | #define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 132 | #define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 133 | #define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable. */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */ |
| Anna Bridge |
142:4eea097334d6 | 140 | #define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */ |
| Anna Bridge |
142:4eea097334d6 | 141 | #define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 142 | #define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 156 | #define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 157 | #define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 159 | #define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable Bit. */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 167 | #define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift. */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 174 | #define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 175 | #define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 177 | #define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit. */ |
| Anna Bridge |
142:4eea097334d6 | 178 | #define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */ |
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142:4eea097334d6 | 179 | #define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */ |
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142:4eea097334d6 | 180 | #define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 181 | #define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 182 | #define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 183 | #define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 184 | #define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 185 | #define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 186 | #define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */ |
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142:4eea097334d6 | 187 | #define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */ |
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142:4eea097334d6 | 188 | #define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */ |
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142:4eea097334d6 | 189 | #define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 190 | #define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */ |
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142:4eea097334d6 | 191 | #define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */ |
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142:4eea097334d6 | 192 | #define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 193 | #define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */ |
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142:4eea097334d6 | 194 | #define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */ |
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142:4eea097334d6 | 195 | #define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */ |
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142:4eea097334d6 | 196 | #define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */ |
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142:4eea097334d6 | 197 | #define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */ |
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142:4eea097334d6 | 198 | #define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 199 | #define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 200 | #define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 201 | #define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 202 | #define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 203 | #define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 204 | #define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN auto ground enable */ |
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142:4eea097334d6 | 205 | #define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */ |
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142:4eea097334d6 | 206 | #define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */ |
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142:4eea097334d6 | 207 | #define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 208 | #define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 209 | #define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 210 | #define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 211 | #define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 212 | #define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */ |
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142:4eea097334d6 | 213 | #define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect. */ |
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142:4eea097334d6 | 214 | #define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */ |
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142:4eea097334d6 | 215 | #define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */ |
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142:4eea097334d6 | 216 | #define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 217 | #define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */ |
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142:4eea097334d6 | 218 | #define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */ |
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142:4eea097334d6 | 219 | #define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 220 | #define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */ |
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142:4eea097334d6 | 221 | #define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */ |
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142:4eea097334d6 | 222 | #define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and less than comparison using the exponential moving average (EMA) is enabled. */ |
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142:4eea097334d6 | 223 | #define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */ |
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142:4eea097334d6 | 224 | #define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */ |
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142:4eea097334d6 | 225 | #define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 226 | #define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 227 | #define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup mode for CSEN */ |
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142:4eea097334d6 | 228 | #define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */ |
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142:4eea097334d6 | 229 | #define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */ |
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142:4eea097334d6 | 230 | #define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 231 | #define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */ |
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142:4eea097334d6 | 232 | #define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */ |
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142:4eea097334d6 | 233 | #define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 234 | #define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */ |
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142:4eea097334d6 | 235 | #define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */ |
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142:4eea097334d6 | 236 | #define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Sense local cap connection instead of the external kelvin connection. */ |
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142:4eea097334d6 | 237 | #define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */ |
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142:4eea097334d6 | 238 | #define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */ |
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142:4eea097334d6 | 239 | #define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 240 | #define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 241 | #define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Sets the accuracy of the charge pump. */ |
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142:4eea097334d6 | 242 | #define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */ |
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142:4eea097334d6 | 243 | #define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */ |
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142:4eea097334d6 | 244 | #define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 245 | #define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */ |
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142:4eea097334d6 | 246 | #define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */ |
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142:4eea097334d6 | 247 | #define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */ |
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142:4eea097334d6 | 248 | #define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */ |
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142:4eea097334d6 | 249 | #define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */ |
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142:4eea097334d6 | 250 | |
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142:4eea097334d6 | 251 | /* Bit fields for CSEN TIMCTRL */ |
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142:4eea097334d6 | 252 | #define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 253 | #define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 254 | #define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */ |
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142:4eea097334d6 | 255 | #define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */ |
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142:4eea097334d6 | 256 | #define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 257 | #define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 258 | #define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 259 | #define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 260 | #define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 261 | #define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 262 | #define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 263 | #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 264 | #define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 265 | #define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 266 | #define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 267 | #define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 268 | #define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 269 | #define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 270 | #define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 271 | #define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 272 | #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 273 | #define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 274 | #define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */ |
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142:4eea097334d6 | 275 | #define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */ |
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142:4eea097334d6 | 276 | #define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 277 | #define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 278 | #define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */ |
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142:4eea097334d6 | 279 | #define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */ |
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142:4eea097334d6 | 280 | #define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 281 | #define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ |
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142:4eea097334d6 | 282 | |
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142:4eea097334d6 | 283 | /* Bit fields for CSEN CMD */ |
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142:4eea097334d6 | 284 | #define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */ |
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142:4eea097334d6 | 285 | #define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */ |
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142:4eea097334d6 | 286 | #define CSEN_CMD_START (0x1UL << 0) /**< Start a CSEN conversion. */ |
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142:4eea097334d6 | 287 | #define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */ |
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142:4eea097334d6 | 288 | #define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */ |
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142:4eea097334d6 | 289 | #define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */ |
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142:4eea097334d6 | 290 | #define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */ |
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142:4eea097334d6 | 291 | |
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142:4eea097334d6 | 292 | /* Bit fields for CSEN STATUS */ |
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142:4eea097334d6 | 293 | #define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */ |
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142:4eea097334d6 | 294 | #define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */ |
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142:4eea097334d6 | 295 | #define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< CSEN Busy */ |
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142:4eea097334d6 | 296 | #define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */ |
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142:4eea097334d6 | 297 | #define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */ |
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142:4eea097334d6 | 298 | #define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */ |
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142:4eea097334d6 | 299 | #define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */ |
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142:4eea097334d6 | 300 | #define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */ |
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142:4eea097334d6 | 301 | #define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */ |
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142:4eea097334d6 | 302 | #define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */ |
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142:4eea097334d6 | 303 | #define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */ |
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142:4eea097334d6 | 304 | |
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142:4eea097334d6 | 305 | /* Bit fields for CSEN PRSSEL */ |
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142:4eea097334d6 | 306 | #define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */ |
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142:4eea097334d6 | 307 | #define _CSEN_PRSSEL_MASK 0x0000000FUL /**< Mask for CSEN_PRSSEL */ |
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142:4eea097334d6 | 308 | #define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */ |
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142:4eea097334d6 | 309 | #define _CSEN_PRSSEL_PRSSEL_MASK 0xFUL /**< Bit mask for CSEN_PRSSEL */ |
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142:4eea097334d6 | 310 | #define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */ |
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142:4eea097334d6 | 311 | #define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 312 | #define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 313 | #define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 314 | #define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 315 | #define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 316 | #define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 317 | #define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 318 | #define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 319 | #define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 320 | #define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 321 | #define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 322 | #define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 323 | #define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */ |
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142:4eea097334d6 | 324 | #define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 325 | #define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 326 | #define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 327 | #define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 328 | #define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 329 | #define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 330 | #define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */ |
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142:4eea097334d6 | 331 | #define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 332 | #define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 333 | #define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 334 | #define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 335 | #define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 336 | |
| Anna Bridge |
142:4eea097334d6 | 337 | /* Bit fields for CSEN DATA */ |
| Anna Bridge |
142:4eea097334d6 | 338 | #define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 339 | #define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 340 | #define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 341 | #define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 342 | #define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 343 | #define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 344 | |
| Anna Bridge |
142:4eea097334d6 | 345 | /* Bit fields for CSEN SCANMASK0 */ |
| Anna Bridge |
142:4eea097334d6 | 346 | #define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */ |
| Anna Bridge |
142:4eea097334d6 | 347 | #define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */ |
| Anna Bridge |
142:4eea097334d6 | 348 | #define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 349 | #define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 350 | #define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */ |
| Anna Bridge |
142:4eea097334d6 | 351 | #define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */ |
| Anna Bridge |
142:4eea097334d6 | 352 | |
| Anna Bridge |
142:4eea097334d6 | 353 | /* Bit fields for CSEN SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 354 | #define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 355 | #define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 356 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */ |
| Anna Bridge |
142:4eea097334d6 | 357 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */ |
| Anna Bridge |
142:4eea097334d6 | 358 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 359 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 360 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 361 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 362 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 363 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 364 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 365 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 366 | #define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 367 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 368 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 369 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 370 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 371 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 372 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 373 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 374 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 375 | #define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 376 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */ |
| Anna Bridge |
142:4eea097334d6 | 377 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */ |
| Anna Bridge |
142:4eea097334d6 | 378 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 379 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 380 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 381 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 382 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 383 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 384 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 385 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 386 | #define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 387 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 388 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 389 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 390 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 391 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 392 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 393 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 394 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 395 | #define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 396 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */ |
| Anna Bridge |
142:4eea097334d6 | 397 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */ |
| Anna Bridge |
142:4eea097334d6 | 398 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 399 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 400 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 401 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 402 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 403 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 404 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 405 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 406 | #define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 407 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 408 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 409 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 410 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 411 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 412 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 413 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 414 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 415 | #define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 416 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */ |
| Anna Bridge |
142:4eea097334d6 | 417 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */ |
| Anna Bridge |
142:4eea097334d6 | 418 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 419 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 420 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 421 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 422 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 423 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 424 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 425 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 426 | #define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 427 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 428 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 429 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 430 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 431 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 432 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 433 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 434 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 435 | #define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 436 | |
| Anna Bridge |
142:4eea097334d6 | 437 | /* Bit fields for CSEN SCANMASK1 */ |
| Anna Bridge |
142:4eea097334d6 | 438 | #define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */ |
| Anna Bridge |
142:4eea097334d6 | 439 | #define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */ |
| Anna Bridge |
142:4eea097334d6 | 440 | #define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 441 | #define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 442 | #define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */ |
| Anna Bridge |
142:4eea097334d6 | 443 | #define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */ |
| Anna Bridge |
142:4eea097334d6 | 444 | |
| Anna Bridge |
142:4eea097334d6 | 445 | /* Bit fields for CSEN SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 446 | #define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 447 | #define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 448 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */ |
| Anna Bridge |
142:4eea097334d6 | 449 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */ |
| Anna Bridge |
142:4eea097334d6 | 450 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 451 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 452 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 453 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 454 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 455 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 456 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 457 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 458 | #define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 459 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 460 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 461 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 462 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 463 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 464 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 465 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 466 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 467 | #define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 468 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */ |
| Anna Bridge |
142:4eea097334d6 | 469 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */ |
| Anna Bridge |
142:4eea097334d6 | 470 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 471 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 472 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 473 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 474 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 475 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 476 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 477 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 478 | #define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 479 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 480 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 481 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 482 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 483 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 484 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 485 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 486 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 487 | #define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 488 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */ |
| Anna Bridge |
142:4eea097334d6 | 489 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */ |
| Anna Bridge |
142:4eea097334d6 | 490 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 491 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 492 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 493 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 494 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 495 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 496 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 497 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 498 | #define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 499 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 500 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 501 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 502 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 503 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 504 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 505 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 506 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 507 | #define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 508 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */ |
| Anna Bridge |
142:4eea097334d6 | 509 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */ |
| Anna Bridge |
142:4eea097334d6 | 510 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 511 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 512 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 513 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 514 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 515 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 516 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 517 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 518 | #define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 519 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 520 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 521 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 522 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 523 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 524 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 525 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 526 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 527 | #define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 528 | |
| Anna Bridge |
142:4eea097334d6 | 529 | /* Bit fields for CSEN APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 530 | #define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 531 | #define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 532 | #define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 533 | #define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 534 | #define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 535 | #define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 536 | #define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 537 | #define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 538 | #define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 539 | #define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 540 | #define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 541 | #define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 542 | #define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 543 | #define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 544 | #define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 545 | #define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 546 | #define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 547 | #define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ |
| Anna Bridge |
142:4eea097334d6 | 548 | #define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 549 | #define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 550 | #define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 551 | #define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 552 | #define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 553 | #define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 554 | #define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 555 | #define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 556 | #define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 557 | #define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ |
| Anna Bridge |
142:4eea097334d6 | 558 | #define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 559 | #define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 560 | #define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 561 | #define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 562 | #define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 563 | #define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 564 | #define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 565 | #define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 566 | #define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 567 | #define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ |
| Anna Bridge |
142:4eea097334d6 | 568 | #define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 569 | #define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 570 | #define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 571 | #define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 572 | |
| Anna Bridge |
142:4eea097334d6 | 573 | /* Bit fields for CSEN APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 574 | #define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 575 | #define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 576 | #define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 577 | #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 578 | #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 579 | #define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 580 | #define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 581 | #define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 582 | #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 583 | #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 584 | #define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 585 | #define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 586 | #define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 587 | #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 588 | #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 589 | #define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 590 | #define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 591 | #define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 592 | #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 593 | #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 594 | #define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 595 | #define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 596 | #define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 597 | #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 598 | #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 599 | #define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 600 | #define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 601 | #define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 602 | #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 603 | #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 604 | #define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 605 | #define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 606 | #define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 607 | #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 608 | #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 609 | #define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 610 | #define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 611 | #define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 612 | #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 613 | #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 614 | #define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 615 | #define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 616 | |
| Anna Bridge |
142:4eea097334d6 | 617 | /* Bit fields for CSEN CMPTHR */ |
| Anna Bridge |
142:4eea097334d6 | 618 | #define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */ |
| Anna Bridge |
142:4eea097334d6 | 619 | #define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */ |
| Anna Bridge |
142:4eea097334d6 | 620 | #define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */ |
| Anna Bridge |
142:4eea097334d6 | 621 | #define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */ |
| Anna Bridge |
142:4eea097334d6 | 622 | #define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */ |
| Anna Bridge |
142:4eea097334d6 | 623 | #define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */ |
| Anna Bridge |
142:4eea097334d6 | 624 | |
| Anna Bridge |
142:4eea097334d6 | 625 | /* Bit fields for CSEN EMA */ |
| Anna Bridge |
142:4eea097334d6 | 626 | #define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */ |
| Anna Bridge |
142:4eea097334d6 | 627 | #define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */ |
| Anna Bridge |
142:4eea097334d6 | 628 | #define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */ |
| Anna Bridge |
142:4eea097334d6 | 629 | #define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */ |
| Anna Bridge |
142:4eea097334d6 | 630 | #define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */ |
| Anna Bridge |
142:4eea097334d6 | 631 | #define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */ |
| Anna Bridge |
142:4eea097334d6 | 632 | |
| Anna Bridge |
142:4eea097334d6 | 633 | /* Bit fields for CSEN EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 634 | #define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 635 | #define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 636 | #define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */ |
| Anna Bridge |
142:4eea097334d6 | 637 | #define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */ |
| Anna Bridge |
142:4eea097334d6 | 638 | #define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 639 | #define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 640 | #define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 641 | #define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 642 | #define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 643 | #define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 644 | #define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 645 | #define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 646 | #define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 647 | #define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 648 | #define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 649 | #define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 650 | #define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 651 | #define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 652 | #define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 653 | #define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 654 | |
| Anna Bridge |
142:4eea097334d6 | 655 | /* Bit fields for CSEN SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 656 | #define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 657 | #define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 658 | #define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */ |
| Anna Bridge |
142:4eea097334d6 | 659 | #define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */ |
| Anna Bridge |
142:4eea097334d6 | 660 | #define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 661 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 662 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 663 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 664 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 665 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 666 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 667 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 668 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 669 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 670 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 671 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 672 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 673 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 674 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 675 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 676 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 677 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 678 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 679 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 680 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 681 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 682 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 683 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 684 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 685 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 686 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 687 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 688 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 689 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 690 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 691 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 692 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 693 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 694 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 695 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 696 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 697 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 698 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 699 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 700 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 701 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 702 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 703 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 704 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 705 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 706 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 707 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 708 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 709 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 710 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 711 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 712 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 713 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 714 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 715 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 716 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 717 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 718 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 719 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 720 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 721 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 722 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 723 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 724 | #define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 725 | #define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 726 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 727 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 728 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 729 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 730 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 731 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 732 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 733 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 734 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 735 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 736 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 737 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 738 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 739 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 740 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 741 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 742 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 743 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 744 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 745 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 746 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 747 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 748 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 749 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 750 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 751 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 752 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 753 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 754 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 755 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 756 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 757 | #define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 758 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 759 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 760 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 761 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 762 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 763 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 764 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 765 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 766 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 767 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 768 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 769 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 770 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 771 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 772 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 773 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 774 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 775 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 776 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 777 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 778 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 779 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 780 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 781 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 782 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 783 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 784 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 785 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 786 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 787 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 788 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 789 | #define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 790 | |
| Anna Bridge |
142:4eea097334d6 | 791 | /* Bit fields for CSEN DMBASELINE */ |
| Anna Bridge |
142:4eea097334d6 | 792 | #define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */ |
| Anna Bridge |
142:4eea097334d6 | 793 | #define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */ |
| Anna Bridge |
142:4eea097334d6 | 794 | #define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */ |
| Anna Bridge |
142:4eea097334d6 | 795 | #define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */ |
| Anna Bridge |
142:4eea097334d6 | 796 | #define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ |
| Anna Bridge |
142:4eea097334d6 | 797 | #define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ |
| Anna Bridge |
142:4eea097334d6 | 798 | #define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */ |
| Anna Bridge |
142:4eea097334d6 | 799 | #define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */ |
| Anna Bridge |
142:4eea097334d6 | 800 | #define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ |
| Anna Bridge |
142:4eea097334d6 | 801 | #define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ |
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142:4eea097334d6 | 802 | |
| Anna Bridge |
142:4eea097334d6 | 803 | /* Bit fields for CSEN DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 804 | #define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 805 | #define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 806 | #define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */ |
| Anna Bridge |
142:4eea097334d6 | 807 | #define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */ |
| Anna Bridge |
142:4eea097334d6 | 808 | #define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 809 | #define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 810 | #define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */ |
| Anna Bridge |
142:4eea097334d6 | 811 | #define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */ |
| Anna Bridge |
142:4eea097334d6 | 812 | #define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 813 | #define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 814 | #define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */ |
| Anna Bridge |
142:4eea097334d6 | 815 | #define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */ |
| Anna Bridge |
142:4eea097334d6 | 816 | #define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 817 | #define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 818 | #define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */ |
| Anna Bridge |
142:4eea097334d6 | 819 | #define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */ |
| Anna Bridge |
142:4eea097334d6 | 820 | #define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 821 | #define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 822 | #define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 823 | #define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 824 | #define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 825 | #define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 826 | #define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 827 | #define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 828 | #define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 829 | #define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 830 | #define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Disable delta modulator gain reduction. */ |
| Anna Bridge |
142:4eea097334d6 | 831 | #define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */ |
| Anna Bridge |
142:4eea097334d6 | 832 | #define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */ |
| Anna Bridge |
142:4eea097334d6 | 833 | #define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 834 | #define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */ |
| Anna Bridge |
142:4eea097334d6 | 835 | |
| Anna Bridge |
142:4eea097334d6 | 836 | /* Bit fields for CSEN ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 837 | #define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 838 | #define _CSEN_ANACTRL_MASK 0x03730771UL /**< Mask for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 839 | #define CSEN_ANACTRL_CREFHALF (0x1UL << 0) /**< Reference capacitor divide by half. */ |
| Anna Bridge |
142:4eea097334d6 | 840 | #define _CSEN_ANACTRL_CREFHALF_SHIFT 0 /**< Shift value for CSEN_CREFHALF */ |
| Anna Bridge |
142:4eea097334d6 | 841 | #define _CSEN_ANACTRL_CREFHALF_MASK 0x1UL /**< Bit mask for CSEN_CREFHALF */ |
| Anna Bridge |
142:4eea097334d6 | 842 | #define _CSEN_ANACTRL_CREFHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 843 | #define _CSEN_ANACTRL_CREFHALF_FULL 0x00000000UL /**< Mode FULL for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 844 | #define _CSEN_ANACTRL_CREFHALF_HALF 0x00000001UL /**< Mode HALF for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 845 | #define CSEN_ANACTRL_CREFHALF_DEFAULT (_CSEN_ANACTRL_CREFHALF_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 846 | #define CSEN_ANACTRL_CREFHALF_FULL (_CSEN_ANACTRL_CREFHALF_FULL << 0) /**< Shifted mode FULL for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 847 | #define CSEN_ANACTRL_CREFHALF_HALF (_CSEN_ANACTRL_CREFHALF_HALF << 0) /**< Shifted mode HALF for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 848 | #define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */ |
| Anna Bridge |
142:4eea097334d6 | 849 | #define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */ |
| Anna Bridge |
142:4eea097334d6 | 850 | #define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 851 | #define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 852 | #define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */ |
| Anna Bridge |
142:4eea097334d6 | 853 | #define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */ |
| Anna Bridge |
142:4eea097334d6 | 854 | #define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 855 | #define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 856 | #define _CSEN_ANACTRL_DUTYSCALE_SHIFT 16 /**< Shift value for CSEN_DUTYSCALE */ |
| Anna Bridge |
142:4eea097334d6 | 857 | #define _CSEN_ANACTRL_DUTYSCALE_MASK 0x30000UL /**< Bit mask for CSEN_DUTYSCALE */ |
| Anna Bridge |
142:4eea097334d6 | 858 | #define _CSEN_ANACTRL_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 859 | #define _CSEN_ANACTRL_DUTYSCALE_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 860 | #define _CSEN_ANACTRL_DUTYSCALE_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 861 | #define _CSEN_ANACTRL_DUTYSCALE_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 862 | #define _CSEN_ANACTRL_DUTYSCALE_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 863 | #define CSEN_ANACTRL_DUTYSCALE_DEFAULT (_CSEN_ANACTRL_DUTYSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 864 | #define CSEN_ANACTRL_DUTYSCALE_DIV1 (_CSEN_ANACTRL_DUTYSCALE_DIV1 << 16) /**< Shifted mode DIV1 for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 865 | #define CSEN_ANACTRL_DUTYSCALE_DIV2 (_CSEN_ANACTRL_DUTYSCALE_DIV2 << 16) /**< Shifted mode DIV2 for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 866 | #define CSEN_ANACTRL_DUTYSCALE_DIV4 (_CSEN_ANACTRL_DUTYSCALE_DIV4 << 16) /**< Shifted mode DIV4 for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 867 | #define CSEN_ANACTRL_DUTYSCALE_DIV8 (_CSEN_ANACTRL_DUTYSCALE_DIV8 << 16) /**< Shifted mode DIV8 for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 868 | #define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */ |
| Anna Bridge |
142:4eea097334d6 | 869 | #define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */ |
| Anna Bridge |
142:4eea097334d6 | 870 | #define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 871 | #define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 872 | #define _CSEN_ANACTRL_BIASPROG_SHIFT 24 /**< Shift value for CSEN_BIASPROG */ |
| Anna Bridge |
142:4eea097334d6 | 873 | #define _CSEN_ANACTRL_BIASPROG_MASK 0x3000000UL /**< Bit mask for CSEN_BIASPROG */ |
| Anna Bridge |
142:4eea097334d6 | 874 | #define _CSEN_ANACTRL_BIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 875 | #define _CSEN_ANACTRL_BIASPROG_ONEX 0x00000000UL /**< Mode ONEX for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 876 | #define _CSEN_ANACTRL_BIASPROG_TWOX 0x00000001UL /**< Mode TWOX for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 877 | #define _CSEN_ANACTRL_BIASPROG_ONETENTH 0x00000002UL /**< Mode ONETENTH for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 878 | #define _CSEN_ANACTRL_BIASPROG_HALF 0x00000003UL /**< Mode HALF for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 879 | #define CSEN_ANACTRL_BIASPROG_DEFAULT (_CSEN_ANACTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 880 | #define CSEN_ANACTRL_BIASPROG_ONEX (_CSEN_ANACTRL_BIASPROG_ONEX << 24) /**< Shifted mode ONEX for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 881 | #define CSEN_ANACTRL_BIASPROG_TWOX (_CSEN_ANACTRL_BIASPROG_TWOX << 24) /**< Shifted mode TWOX for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 882 | #define CSEN_ANACTRL_BIASPROG_ONETENTH (_CSEN_ANACTRL_BIASPROG_ONETENTH << 24) /**< Shifted mode ONETENTH for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 883 | #define CSEN_ANACTRL_BIASPROG_HALF (_CSEN_ANACTRL_BIASPROG_HALF << 24) /**< Shifted mode HALF for CSEN_ANACTRL */ |
| Anna Bridge |
142:4eea097334d6 | 884 | |
| Anna Bridge |
142:4eea097334d6 | 885 | /* Bit fields for CSEN IF */ |
| Anna Bridge |
142:4eea097334d6 | 886 | #define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 887 | #define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 888 | #define CSEN_IF_CMP (0x1UL << 0) /**< CSEN Digital Comparator Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 889 | #define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ |
| Anna Bridge |
142:4eea097334d6 | 890 | #define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ |
| Anna Bridge |
142:4eea097334d6 | 891 | #define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 892 | #define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 893 | #define CSEN_IF_CONV (0x1UL << 1) /**< CSEN Conversion Done Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 894 | #define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ |
| Anna Bridge |
142:4eea097334d6 | 895 | #define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ |
| Anna Bridge |
142:4eea097334d6 | 896 | #define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 897 | #define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 898 | #define CSEN_IF_EOS (0x1UL << 2) /**< CSEN End of Scan Interrupt Flag. */ |
| Anna Bridge |
142:4eea097334d6 | 899 | #define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ |
| Anna Bridge |
142:4eea097334d6 | 900 | #define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ |
| Anna Bridge |
142:4eea097334d6 | 901 | #define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 902 | #define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 903 | #define CSEN_IF_DMAOF (0x1UL << 3) /**< CSEN DMA Overflow Interrupt Flag. */ |
| Anna Bridge |
142:4eea097334d6 | 904 | #define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ |
| Anna Bridge |
142:4eea097334d6 | 905 | #define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ |
| Anna Bridge |
142:4eea097334d6 | 906 | #define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 907 | #define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 908 | #define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 909 | #define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 910 | #define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 911 | #define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 912 | #define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */ |
| Anna Bridge |
142:4eea097334d6 | 913 | |
| Anna Bridge |
142:4eea097334d6 | 914 | /* Bit fields for CSEN IFS */ |
| Anna Bridge |
142:4eea097334d6 | 915 | #define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 916 | #define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 917 | #define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 918 | #define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ |
| Anna Bridge |
142:4eea097334d6 | 919 | #define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ |
| Anna Bridge |
142:4eea097334d6 | 920 | #define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 921 | #define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 922 | #define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 923 | #define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ |
| Anna Bridge |
142:4eea097334d6 | 924 | #define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ |
| Anna Bridge |
142:4eea097334d6 | 925 | #define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 926 | #define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 927 | #define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 928 | #define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ |
| Anna Bridge |
142:4eea097334d6 | 929 | #define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ |
| Anna Bridge |
142:4eea097334d6 | 930 | #define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 931 | #define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 932 | #define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 933 | #define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ |
| Anna Bridge |
142:4eea097334d6 | 934 | #define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ |
| Anna Bridge |
142:4eea097334d6 | 935 | #define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 936 | #define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 937 | #define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 938 | #define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 939 | #define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 940 | #define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 941 | #define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 942 | |
| Anna Bridge |
142:4eea097334d6 | 943 | /* Bit fields for CSEN IFC */ |
| Anna Bridge |
142:4eea097334d6 | 944 | #define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 945 | #define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 946 | #define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 947 | #define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ |
| Anna Bridge |
142:4eea097334d6 | 948 | #define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ |
| Anna Bridge |
142:4eea097334d6 | 949 | #define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 950 | #define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 951 | #define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 952 | #define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ |
| Anna Bridge |
142:4eea097334d6 | 953 | #define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ |
| Anna Bridge |
142:4eea097334d6 | 954 | #define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 955 | #define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 956 | #define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 957 | #define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ |
| Anna Bridge |
142:4eea097334d6 | 958 | #define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ |
| Anna Bridge |
142:4eea097334d6 | 959 | #define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 960 | #define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 961 | #define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 962 | #define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ |
| Anna Bridge |
142:4eea097334d6 | 963 | #define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ |
| Anna Bridge |
142:4eea097334d6 | 964 | #define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 965 | #define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 966 | #define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 967 | #define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 968 | #define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 969 | #define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 970 | #define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 971 | |
| Anna Bridge |
142:4eea097334d6 | 972 | /* Bit fields for CSEN IEN */ |
| Anna Bridge |
142:4eea097334d6 | 973 | #define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 974 | #define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 975 | #define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 976 | #define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ |
| Anna Bridge |
142:4eea097334d6 | 977 | #define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ |
| Anna Bridge |
142:4eea097334d6 | 978 | #define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 979 | #define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 980 | #define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 981 | #define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ |
| Anna Bridge |
142:4eea097334d6 | 982 | #define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ |
| Anna Bridge |
142:4eea097334d6 | 983 | #define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 984 | #define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 985 | #define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 986 | #define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ |
| Anna Bridge |
142:4eea097334d6 | 987 | #define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ |
| Anna Bridge |
142:4eea097334d6 | 988 | #define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 989 | #define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 990 | #define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 991 | #define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ |
| Anna Bridge |
142:4eea097334d6 | 992 | #define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ |
| Anna Bridge |
142:4eea097334d6 | 993 | #define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 994 | #define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 995 | #define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 996 | #define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 997 | #define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 998 | #define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 999 | #define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 1000 | |
| Anna Bridge |
142:4eea097334d6 | 1001 | /** @} End of group EFR32MG12P_CSEN */ |
| Anna Bridge |
142:4eea097334d6 | 1002 | /** @} End of group Parts */ |
| Anna Bridge |
142:4eea097334d6 | 1003 |
