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TARGET_SAMR21G18A/core_caFunc.h@111:4336505e4b1c, 2015-12-15 (annotated)
- Committer:
- Kojto
- Date:
- Tue Dec 15 14:39:38 2015 +0000
- Revision:
- 111:4336505e4b1c
- Child:
- 115:87f2f5183dfb
Release 111 of the mbed library
Changes:
- new platforms - Atmel targets (SAMR21G18A, SAMD21J18A, SAMD21G18A)
- Streams - add var argument (vprintf, vscanf)
- MAXWSNENV - BLE stack library additio
- LPC1768 - fix slave read
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 111:4336505e4b1c | 1 | /**************************************************************************//** |
Kojto | 111:4336505e4b1c | 2 | * @file core_caFunc.h |
Kojto | 111:4336505e4b1c | 3 | * @brief CMSIS Cortex-A Core Function Access Header File |
Kojto | 111:4336505e4b1c | 4 | * @version V3.10 |
Kojto | 111:4336505e4b1c | 5 | * @date 30 Oct 2013 |
Kojto | 111:4336505e4b1c | 6 | * |
Kojto | 111:4336505e4b1c | 7 | * @note |
Kojto | 111:4336505e4b1c | 8 | * |
Kojto | 111:4336505e4b1c | 9 | ******************************************************************************/ |
Kojto | 111:4336505e4b1c | 10 | /* Copyright (c) 2009 - 2013 ARM LIMITED |
Kojto | 111:4336505e4b1c | 11 | |
Kojto | 111:4336505e4b1c | 12 | All rights reserved. |
Kojto | 111:4336505e4b1c | 13 | Redistribution and use in source and binary forms, with or without |
Kojto | 111:4336505e4b1c | 14 | modification, are permitted provided that the following conditions are met: |
Kojto | 111:4336505e4b1c | 15 | - Redistributions of source code must retain the above copyright |
Kojto | 111:4336505e4b1c | 16 | notice, this list of conditions and the following disclaimer. |
Kojto | 111:4336505e4b1c | 17 | - Redistributions in binary form must reproduce the above copyright |
Kojto | 111:4336505e4b1c | 18 | notice, this list of conditions and the following disclaimer in the |
Kojto | 111:4336505e4b1c | 19 | documentation and/or other materials provided with the distribution. |
Kojto | 111:4336505e4b1c | 20 | - Neither the name of ARM nor the names of its contributors may be used |
Kojto | 111:4336505e4b1c | 21 | to endorse or promote products derived from this software without |
Kojto | 111:4336505e4b1c | 22 | specific prior written permission. |
Kojto | 111:4336505e4b1c | 23 | * |
Kojto | 111:4336505e4b1c | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
Kojto | 111:4336505e4b1c | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
Kojto | 111:4336505e4b1c | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
Kojto | 111:4336505e4b1c | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
Kojto | 111:4336505e4b1c | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
Kojto | 111:4336505e4b1c | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
Kojto | 111:4336505e4b1c | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
Kojto | 111:4336505e4b1c | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
Kojto | 111:4336505e4b1c | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
Kojto | 111:4336505e4b1c | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
Kojto | 111:4336505e4b1c | 34 | POSSIBILITY OF SUCH DAMAGE. |
Kojto | 111:4336505e4b1c | 35 | ---------------------------------------------------------------------------*/ |
Kojto | 111:4336505e4b1c | 36 | |
Kojto | 111:4336505e4b1c | 37 | |
Kojto | 111:4336505e4b1c | 38 | #ifndef __CORE_CAFUNC_H__ |
Kojto | 111:4336505e4b1c | 39 | #define __CORE_CAFUNC_H__ |
Kojto | 111:4336505e4b1c | 40 | |
Kojto | 111:4336505e4b1c | 41 | |
Kojto | 111:4336505e4b1c | 42 | /* ########################### Core Function Access ########################### */ |
Kojto | 111:4336505e4b1c | 43 | /** \ingroup CMSIS_Core_FunctionInterface |
Kojto | 111:4336505e4b1c | 44 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
Kojto | 111:4336505e4b1c | 45 | @{ |
Kojto | 111:4336505e4b1c | 46 | */ |
Kojto | 111:4336505e4b1c | 47 | |
Kojto | 111:4336505e4b1c | 48 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
Kojto | 111:4336505e4b1c | 49 | /* ARM armcc specific functions */ |
Kojto | 111:4336505e4b1c | 50 | |
Kojto | 111:4336505e4b1c | 51 | #if (__ARMCC_VERSION < 400677) |
Kojto | 111:4336505e4b1c | 52 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
Kojto | 111:4336505e4b1c | 53 | #endif |
Kojto | 111:4336505e4b1c | 54 | |
Kojto | 111:4336505e4b1c | 55 | #define MODE_USR 0x10 |
Kojto | 111:4336505e4b1c | 56 | #define MODE_FIQ 0x11 |
Kojto | 111:4336505e4b1c | 57 | #define MODE_IRQ 0x12 |
Kojto | 111:4336505e4b1c | 58 | #define MODE_SVC 0x13 |
Kojto | 111:4336505e4b1c | 59 | #define MODE_MON 0x16 |
Kojto | 111:4336505e4b1c | 60 | #define MODE_ABT 0x17 |
Kojto | 111:4336505e4b1c | 61 | #define MODE_HYP 0x1A |
Kojto | 111:4336505e4b1c | 62 | #define MODE_UND 0x1B |
Kojto | 111:4336505e4b1c | 63 | #define MODE_SYS 0x1F |
Kojto | 111:4336505e4b1c | 64 | |
Kojto | 111:4336505e4b1c | 65 | /** \brief Get APSR Register |
Kojto | 111:4336505e4b1c | 66 | |
Kojto | 111:4336505e4b1c | 67 | This function returns the content of the APSR Register. |
Kojto | 111:4336505e4b1c | 68 | |
Kojto | 111:4336505e4b1c | 69 | \return APSR Register value |
Kojto | 111:4336505e4b1c | 70 | */ |
Kojto | 111:4336505e4b1c | 71 | __STATIC_INLINE uint32_t __get_APSR(void) |
Kojto | 111:4336505e4b1c | 72 | { |
Kojto | 111:4336505e4b1c | 73 | register uint32_t __regAPSR __ASM("apsr"); |
Kojto | 111:4336505e4b1c | 74 | return(__regAPSR); |
Kojto | 111:4336505e4b1c | 75 | } |
Kojto | 111:4336505e4b1c | 76 | |
Kojto | 111:4336505e4b1c | 77 | |
Kojto | 111:4336505e4b1c | 78 | /** \brief Get CPSR Register |
Kojto | 111:4336505e4b1c | 79 | |
Kojto | 111:4336505e4b1c | 80 | This function returns the content of the CPSR Register. |
Kojto | 111:4336505e4b1c | 81 | |
Kojto | 111:4336505e4b1c | 82 | \return CPSR Register value |
Kojto | 111:4336505e4b1c | 83 | */ |
Kojto | 111:4336505e4b1c | 84 | __STATIC_INLINE uint32_t __get_CPSR(void) |
Kojto | 111:4336505e4b1c | 85 | { |
Kojto | 111:4336505e4b1c | 86 | register uint32_t __regCPSR __ASM("cpsr"); |
Kojto | 111:4336505e4b1c | 87 | return(__regCPSR); |
Kojto | 111:4336505e4b1c | 88 | } |
Kojto | 111:4336505e4b1c | 89 | |
Kojto | 111:4336505e4b1c | 90 | /** \brief Set Stack Pointer |
Kojto | 111:4336505e4b1c | 91 | |
Kojto | 111:4336505e4b1c | 92 | This function assigns the given value to the current stack pointer. |
Kojto | 111:4336505e4b1c | 93 | |
Kojto | 111:4336505e4b1c | 94 | \param [in] topOfStack Stack Pointer value to set |
Kojto | 111:4336505e4b1c | 95 | */ |
Kojto | 111:4336505e4b1c | 96 | register uint32_t __regSP __ASM("sp"); |
Kojto | 111:4336505e4b1c | 97 | __STATIC_INLINE void __set_SP(uint32_t topOfStack) |
Kojto | 111:4336505e4b1c | 98 | { |
Kojto | 111:4336505e4b1c | 99 | __regSP = topOfStack; |
Kojto | 111:4336505e4b1c | 100 | } |
Kojto | 111:4336505e4b1c | 101 | |
Kojto | 111:4336505e4b1c | 102 | |
Kojto | 111:4336505e4b1c | 103 | /** \brief Get link register |
Kojto | 111:4336505e4b1c | 104 | |
Kojto | 111:4336505e4b1c | 105 | This function returns the value of the link register |
Kojto | 111:4336505e4b1c | 106 | |
Kojto | 111:4336505e4b1c | 107 | \return Value of link register |
Kojto | 111:4336505e4b1c | 108 | */ |
Kojto | 111:4336505e4b1c | 109 | register uint32_t __reglr __ASM("lr"); |
Kojto | 111:4336505e4b1c | 110 | __STATIC_INLINE uint32_t __get_LR(void) |
Kojto | 111:4336505e4b1c | 111 | { |
Kojto | 111:4336505e4b1c | 112 | return(__reglr); |
Kojto | 111:4336505e4b1c | 113 | } |
Kojto | 111:4336505e4b1c | 114 | |
Kojto | 111:4336505e4b1c | 115 | /** \brief Set link register |
Kojto | 111:4336505e4b1c | 116 | |
Kojto | 111:4336505e4b1c | 117 | This function sets the value of the link register |
Kojto | 111:4336505e4b1c | 118 | |
Kojto | 111:4336505e4b1c | 119 | \param [in] lr LR value to set |
Kojto | 111:4336505e4b1c | 120 | */ |
Kojto | 111:4336505e4b1c | 121 | __STATIC_INLINE void __set_LR(uint32_t lr) |
Kojto | 111:4336505e4b1c | 122 | { |
Kojto | 111:4336505e4b1c | 123 | __reglr = lr; |
Kojto | 111:4336505e4b1c | 124 | } |
Kojto | 111:4336505e4b1c | 125 | |
Kojto | 111:4336505e4b1c | 126 | /** \brief Set Process Stack Pointer |
Kojto | 111:4336505e4b1c | 127 | |
Kojto | 111:4336505e4b1c | 128 | This function assigns the given value to the USR/SYS Stack Pointer (PSP). |
Kojto | 111:4336505e4b1c | 129 | |
Kojto | 111:4336505e4b1c | 130 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
Kojto | 111:4336505e4b1c | 131 | */ |
Kojto | 111:4336505e4b1c | 132 | __STATIC_ASM void __set_PSP(uint32_t topOfProcStack) |
Kojto | 111:4336505e4b1c | 133 | { |
Kojto | 111:4336505e4b1c | 134 | ARM |
Kojto | 111:4336505e4b1c | 135 | PRESERVE8 |
Kojto | 111:4336505e4b1c | 136 | |
Kojto | 111:4336505e4b1c | 137 | BIC R0, R0, #7 ;ensure stack is 8-byte aligned |
Kojto | 111:4336505e4b1c | 138 | MRS R1, CPSR |
Kojto | 111:4336505e4b1c | 139 | CPS #MODE_SYS ;no effect in USR mode |
Kojto | 111:4336505e4b1c | 140 | MOV SP, R0 |
Kojto | 111:4336505e4b1c | 141 | MSR CPSR_c, R1 ;no effect in USR mode |
Kojto | 111:4336505e4b1c | 142 | ISB |
Kojto | 111:4336505e4b1c | 143 | BX LR |
Kojto | 111:4336505e4b1c | 144 | |
Kojto | 111:4336505e4b1c | 145 | } |
Kojto | 111:4336505e4b1c | 146 | |
Kojto | 111:4336505e4b1c | 147 | /** \brief Set User Mode |
Kojto | 111:4336505e4b1c | 148 | |
Kojto | 111:4336505e4b1c | 149 | This function changes the processor state to User Mode |
Kojto | 111:4336505e4b1c | 150 | */ |
Kojto | 111:4336505e4b1c | 151 | __STATIC_ASM void __set_CPS_USR(void) |
Kojto | 111:4336505e4b1c | 152 | { |
Kojto | 111:4336505e4b1c | 153 | ARM |
Kojto | 111:4336505e4b1c | 154 | |
Kojto | 111:4336505e4b1c | 155 | CPS #MODE_USR |
Kojto | 111:4336505e4b1c | 156 | BX LR |
Kojto | 111:4336505e4b1c | 157 | } |
Kojto | 111:4336505e4b1c | 158 | |
Kojto | 111:4336505e4b1c | 159 | |
Kojto | 111:4336505e4b1c | 160 | /** \brief Enable FIQ |
Kojto | 111:4336505e4b1c | 161 | |
Kojto | 111:4336505e4b1c | 162 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
Kojto | 111:4336505e4b1c | 163 | Can only be executed in Privileged modes. |
Kojto | 111:4336505e4b1c | 164 | */ |
Kojto | 111:4336505e4b1c | 165 | #define __enable_fault_irq __enable_fiq |
Kojto | 111:4336505e4b1c | 166 | |
Kojto | 111:4336505e4b1c | 167 | |
Kojto | 111:4336505e4b1c | 168 | /** \brief Disable FIQ |
Kojto | 111:4336505e4b1c | 169 | |
Kojto | 111:4336505e4b1c | 170 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
Kojto | 111:4336505e4b1c | 171 | Can only be executed in Privileged modes. |
Kojto | 111:4336505e4b1c | 172 | */ |
Kojto | 111:4336505e4b1c | 173 | #define __disable_fault_irq __disable_fiq |
Kojto | 111:4336505e4b1c | 174 | |
Kojto | 111:4336505e4b1c | 175 | |
Kojto | 111:4336505e4b1c | 176 | /** \brief Get FPSCR |
Kojto | 111:4336505e4b1c | 177 | |
Kojto | 111:4336505e4b1c | 178 | This function returns the current value of the Floating Point Status/Control register. |
Kojto | 111:4336505e4b1c | 179 | |
Kojto | 111:4336505e4b1c | 180 | \return Floating Point Status/Control register value |
Kojto | 111:4336505e4b1c | 181 | */ |
Kojto | 111:4336505e4b1c | 182 | __STATIC_INLINE uint32_t __get_FPSCR(void) |
Kojto | 111:4336505e4b1c | 183 | { |
Kojto | 111:4336505e4b1c | 184 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
Kojto | 111:4336505e4b1c | 185 | register uint32_t __regfpscr __ASM("fpscr"); |
Kojto | 111:4336505e4b1c | 186 | return(__regfpscr); |
Kojto | 111:4336505e4b1c | 187 | #else |
Kojto | 111:4336505e4b1c | 188 | return(0); |
Kojto | 111:4336505e4b1c | 189 | #endif |
Kojto | 111:4336505e4b1c | 190 | } |
Kojto | 111:4336505e4b1c | 191 | |
Kojto | 111:4336505e4b1c | 192 | |
Kojto | 111:4336505e4b1c | 193 | /** \brief Set FPSCR |
Kojto | 111:4336505e4b1c | 194 | |
Kojto | 111:4336505e4b1c | 195 | This function assigns the given value to the Floating Point Status/Control register. |
Kojto | 111:4336505e4b1c | 196 | |
Kojto | 111:4336505e4b1c | 197 | \param [in] fpscr Floating Point Status/Control value to set |
Kojto | 111:4336505e4b1c | 198 | */ |
Kojto | 111:4336505e4b1c | 199 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
Kojto | 111:4336505e4b1c | 200 | { |
Kojto | 111:4336505e4b1c | 201 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
Kojto | 111:4336505e4b1c | 202 | register uint32_t __regfpscr __ASM("fpscr"); |
Kojto | 111:4336505e4b1c | 203 | __regfpscr = (fpscr); |
Kojto | 111:4336505e4b1c | 204 | #endif |
Kojto | 111:4336505e4b1c | 205 | } |
Kojto | 111:4336505e4b1c | 206 | |
Kojto | 111:4336505e4b1c | 207 | /** \brief Get FPEXC |
Kojto | 111:4336505e4b1c | 208 | |
Kojto | 111:4336505e4b1c | 209 | This function returns the current value of the Floating Point Exception Control register. |
Kojto | 111:4336505e4b1c | 210 | |
Kojto | 111:4336505e4b1c | 211 | \return Floating Point Exception Control register value |
Kojto | 111:4336505e4b1c | 212 | */ |
Kojto | 111:4336505e4b1c | 213 | __STATIC_INLINE uint32_t __get_FPEXC(void) |
Kojto | 111:4336505e4b1c | 214 | { |
Kojto | 111:4336505e4b1c | 215 | #if (__FPU_PRESENT == 1) |
Kojto | 111:4336505e4b1c | 216 | register uint32_t __regfpexc __ASM("fpexc"); |
Kojto | 111:4336505e4b1c | 217 | return(__regfpexc); |
Kojto | 111:4336505e4b1c | 218 | #else |
Kojto | 111:4336505e4b1c | 219 | return(0); |
Kojto | 111:4336505e4b1c | 220 | #endif |
Kojto | 111:4336505e4b1c | 221 | } |
Kojto | 111:4336505e4b1c | 222 | |
Kojto | 111:4336505e4b1c | 223 | |
Kojto | 111:4336505e4b1c | 224 | /** \brief Set FPEXC |
Kojto | 111:4336505e4b1c | 225 | |
Kojto | 111:4336505e4b1c | 226 | This function assigns the given value to the Floating Point Exception Control register. |
Kojto | 111:4336505e4b1c | 227 | |
Kojto | 111:4336505e4b1c | 228 | \param [in] fpscr Floating Point Exception Control value to set |
Kojto | 111:4336505e4b1c | 229 | */ |
Kojto | 111:4336505e4b1c | 230 | __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
Kojto | 111:4336505e4b1c | 231 | { |
Kojto | 111:4336505e4b1c | 232 | #if (__FPU_PRESENT == 1) |
Kojto | 111:4336505e4b1c | 233 | register uint32_t __regfpexc __ASM("fpexc"); |
Kojto | 111:4336505e4b1c | 234 | __regfpexc = (fpexc); |
Kojto | 111:4336505e4b1c | 235 | #endif |
Kojto | 111:4336505e4b1c | 236 | } |
Kojto | 111:4336505e4b1c | 237 | |
Kojto | 111:4336505e4b1c | 238 | /** \brief Get CPACR |
Kojto | 111:4336505e4b1c | 239 | |
Kojto | 111:4336505e4b1c | 240 | This function returns the current value of the Coprocessor Access Control register. |
Kojto | 111:4336505e4b1c | 241 | |
Kojto | 111:4336505e4b1c | 242 | \return Coprocessor Access Control register value |
Kojto | 111:4336505e4b1c | 243 | */ |
Kojto | 111:4336505e4b1c | 244 | __STATIC_INLINE uint32_t __get_CPACR(void) |
Kojto | 111:4336505e4b1c | 245 | { |
Kojto | 111:4336505e4b1c | 246 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
Kojto | 111:4336505e4b1c | 247 | return __regCPACR; |
Kojto | 111:4336505e4b1c | 248 | } |
Kojto | 111:4336505e4b1c | 249 | |
Kojto | 111:4336505e4b1c | 250 | /** \brief Set CPACR |
Kojto | 111:4336505e4b1c | 251 | |
Kojto | 111:4336505e4b1c | 252 | This function assigns the given value to the Coprocessor Access Control register. |
Kojto | 111:4336505e4b1c | 253 | |
Kojto | 111:4336505e4b1c | 254 | \param [in] cpacr Coprocessor Acccess Control value to set |
Kojto | 111:4336505e4b1c | 255 | */ |
Kojto | 111:4336505e4b1c | 256 | __STATIC_INLINE void __set_CPACR(uint32_t cpacr) |
Kojto | 111:4336505e4b1c | 257 | { |
Kojto | 111:4336505e4b1c | 258 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
Kojto | 111:4336505e4b1c | 259 | __regCPACR = cpacr; |
Kojto | 111:4336505e4b1c | 260 | __ISB(); |
Kojto | 111:4336505e4b1c | 261 | } |
Kojto | 111:4336505e4b1c | 262 | |
Kojto | 111:4336505e4b1c | 263 | /** \brief Get CBAR |
Kojto | 111:4336505e4b1c | 264 | |
Kojto | 111:4336505e4b1c | 265 | This function returns the value of the Configuration Base Address register. |
Kojto | 111:4336505e4b1c | 266 | |
Kojto | 111:4336505e4b1c | 267 | \return Configuration Base Address register value |
Kojto | 111:4336505e4b1c | 268 | */ |
Kojto | 111:4336505e4b1c | 269 | __STATIC_INLINE uint32_t __get_CBAR() { |
Kojto | 111:4336505e4b1c | 270 | register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); |
Kojto | 111:4336505e4b1c | 271 | return(__regCBAR); |
Kojto | 111:4336505e4b1c | 272 | } |
Kojto | 111:4336505e4b1c | 273 | |
Kojto | 111:4336505e4b1c | 274 | /** \brief Get TTBR0 |
Kojto | 111:4336505e4b1c | 275 | |
Kojto | 111:4336505e4b1c | 276 | This function returns the value of the Translation Table Base Register 0. |
Kojto | 111:4336505e4b1c | 277 | |
Kojto | 111:4336505e4b1c | 278 | \return Translation Table Base Register 0 value |
Kojto | 111:4336505e4b1c | 279 | */ |
Kojto | 111:4336505e4b1c | 280 | __STATIC_INLINE uint32_t __get_TTBR0() { |
Kojto | 111:4336505e4b1c | 281 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
Kojto | 111:4336505e4b1c | 282 | return(__regTTBR0); |
Kojto | 111:4336505e4b1c | 283 | } |
Kojto | 111:4336505e4b1c | 284 | |
Kojto | 111:4336505e4b1c | 285 | /** \brief Set TTBR0 |
Kojto | 111:4336505e4b1c | 286 | |
Kojto | 111:4336505e4b1c | 287 | This function assigns the given value to the Translation Table Base Register 0. |
Kojto | 111:4336505e4b1c | 288 | |
Kojto | 111:4336505e4b1c | 289 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
Kojto | 111:4336505e4b1c | 290 | */ |
Kojto | 111:4336505e4b1c | 291 | __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
Kojto | 111:4336505e4b1c | 292 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
Kojto | 111:4336505e4b1c | 293 | __regTTBR0 = ttbr0; |
Kojto | 111:4336505e4b1c | 294 | __ISB(); |
Kojto | 111:4336505e4b1c | 295 | } |
Kojto | 111:4336505e4b1c | 296 | |
Kojto | 111:4336505e4b1c | 297 | /** \brief Get DACR |
Kojto | 111:4336505e4b1c | 298 | |
Kojto | 111:4336505e4b1c | 299 | This function returns the value of the Domain Access Control Register. |
Kojto | 111:4336505e4b1c | 300 | |
Kojto | 111:4336505e4b1c | 301 | \return Domain Access Control Register value |
Kojto | 111:4336505e4b1c | 302 | */ |
Kojto | 111:4336505e4b1c | 303 | __STATIC_INLINE uint32_t __get_DACR() { |
Kojto | 111:4336505e4b1c | 304 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
Kojto | 111:4336505e4b1c | 305 | return(__regDACR); |
Kojto | 111:4336505e4b1c | 306 | } |
Kojto | 111:4336505e4b1c | 307 | |
Kojto | 111:4336505e4b1c | 308 | /** \brief Set DACR |
Kojto | 111:4336505e4b1c | 309 | |
Kojto | 111:4336505e4b1c | 310 | This function assigns the given value to the Domain Access Control Register. |
Kojto | 111:4336505e4b1c | 311 | |
Kojto | 111:4336505e4b1c | 312 | \param [in] dacr Domain Access Control Register value to set |
Kojto | 111:4336505e4b1c | 313 | */ |
Kojto | 111:4336505e4b1c | 314 | __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
Kojto | 111:4336505e4b1c | 315 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
Kojto | 111:4336505e4b1c | 316 | __regDACR = dacr; |
Kojto | 111:4336505e4b1c | 317 | __ISB(); |
Kojto | 111:4336505e4b1c | 318 | } |
Kojto | 111:4336505e4b1c | 319 | |
Kojto | 111:4336505e4b1c | 320 | /******************************** Cache and BTAC enable ****************************************************/ |
Kojto | 111:4336505e4b1c | 321 | |
Kojto | 111:4336505e4b1c | 322 | /** \brief Set SCTLR |
Kojto | 111:4336505e4b1c | 323 | |
Kojto | 111:4336505e4b1c | 324 | This function assigns the given value to the System Control Register. |
Kojto | 111:4336505e4b1c | 325 | |
Kojto | 111:4336505e4b1c | 326 | \param [in] sctlr System Control Register value to set |
Kojto | 111:4336505e4b1c | 327 | */ |
Kojto | 111:4336505e4b1c | 328 | __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) |
Kojto | 111:4336505e4b1c | 329 | { |
Kojto | 111:4336505e4b1c | 330 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
Kojto | 111:4336505e4b1c | 331 | __regSCTLR = sctlr; |
Kojto | 111:4336505e4b1c | 332 | } |
Kojto | 111:4336505e4b1c | 333 | |
Kojto | 111:4336505e4b1c | 334 | /** \brief Get SCTLR |
Kojto | 111:4336505e4b1c | 335 | |
Kojto | 111:4336505e4b1c | 336 | This function returns the value of the System Control Register. |
Kojto | 111:4336505e4b1c | 337 | |
Kojto | 111:4336505e4b1c | 338 | \return System Control Register value |
Kojto | 111:4336505e4b1c | 339 | */ |
Kojto | 111:4336505e4b1c | 340 | __STATIC_INLINE uint32_t __get_SCTLR() { |
Kojto | 111:4336505e4b1c | 341 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
Kojto | 111:4336505e4b1c | 342 | return(__regSCTLR); |
Kojto | 111:4336505e4b1c | 343 | } |
Kojto | 111:4336505e4b1c | 344 | |
Kojto | 111:4336505e4b1c | 345 | /** \brief Enable Caches |
Kojto | 111:4336505e4b1c | 346 | |
Kojto | 111:4336505e4b1c | 347 | Enable Caches |
Kojto | 111:4336505e4b1c | 348 | */ |
Kojto | 111:4336505e4b1c | 349 | __STATIC_INLINE void __enable_caches(void) { |
Kojto | 111:4336505e4b1c | 350 | // Set I bit 12 to enable I Cache |
Kojto | 111:4336505e4b1c | 351 | // Set C bit 2 to enable D Cache |
Kojto | 111:4336505e4b1c | 352 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
Kojto | 111:4336505e4b1c | 353 | } |
Kojto | 111:4336505e4b1c | 354 | |
Kojto | 111:4336505e4b1c | 355 | /** \brief Disable Caches |
Kojto | 111:4336505e4b1c | 356 | |
Kojto | 111:4336505e4b1c | 357 | Disable Caches |
Kojto | 111:4336505e4b1c | 358 | */ |
Kojto | 111:4336505e4b1c | 359 | __STATIC_INLINE void __disable_caches(void) { |
Kojto | 111:4336505e4b1c | 360 | // Clear I bit 12 to disable I Cache |
Kojto | 111:4336505e4b1c | 361 | // Clear C bit 2 to disable D Cache |
Kojto | 111:4336505e4b1c | 362 | __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); |
Kojto | 111:4336505e4b1c | 363 | __ISB(); |
Kojto | 111:4336505e4b1c | 364 | } |
Kojto | 111:4336505e4b1c | 365 | |
Kojto | 111:4336505e4b1c | 366 | /** \brief Enable BTAC |
Kojto | 111:4336505e4b1c | 367 | |
Kojto | 111:4336505e4b1c | 368 | Enable BTAC |
Kojto | 111:4336505e4b1c | 369 | */ |
Kojto | 111:4336505e4b1c | 370 | __STATIC_INLINE void __enable_btac(void) { |
Kojto | 111:4336505e4b1c | 371 | // Set Z bit 11 to enable branch prediction |
Kojto | 111:4336505e4b1c | 372 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
Kojto | 111:4336505e4b1c | 373 | __ISB(); |
Kojto | 111:4336505e4b1c | 374 | } |
Kojto | 111:4336505e4b1c | 375 | |
Kojto | 111:4336505e4b1c | 376 | /** \brief Disable BTAC |
Kojto | 111:4336505e4b1c | 377 | |
Kojto | 111:4336505e4b1c | 378 | Disable BTAC |
Kojto | 111:4336505e4b1c | 379 | */ |
Kojto | 111:4336505e4b1c | 380 | __STATIC_INLINE void __disable_btac(void) { |
Kojto | 111:4336505e4b1c | 381 | // Clear Z bit 11 to disable branch prediction |
Kojto | 111:4336505e4b1c | 382 | __set_SCTLR( __get_SCTLR() & ~(1 << 11)); |
Kojto | 111:4336505e4b1c | 383 | } |
Kojto | 111:4336505e4b1c | 384 | |
Kojto | 111:4336505e4b1c | 385 | |
Kojto | 111:4336505e4b1c | 386 | /** \brief Enable MMU |
Kojto | 111:4336505e4b1c | 387 | |
Kojto | 111:4336505e4b1c | 388 | Enable MMU |
Kojto | 111:4336505e4b1c | 389 | */ |
Kojto | 111:4336505e4b1c | 390 | __STATIC_INLINE void __enable_mmu(void) { |
Kojto | 111:4336505e4b1c | 391 | // Set M bit 0 to enable the MMU |
Kojto | 111:4336505e4b1c | 392 | // Set AFE bit to enable simplified access permissions model |
Kojto | 111:4336505e4b1c | 393 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
Kojto | 111:4336505e4b1c | 394 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
Kojto | 111:4336505e4b1c | 395 | __ISB(); |
Kojto | 111:4336505e4b1c | 396 | } |
Kojto | 111:4336505e4b1c | 397 | |
Kojto | 111:4336505e4b1c | 398 | /** \brief Disable MMU |
Kojto | 111:4336505e4b1c | 399 | |
Kojto | 111:4336505e4b1c | 400 | Disable MMU |
Kojto | 111:4336505e4b1c | 401 | */ |
Kojto | 111:4336505e4b1c | 402 | __STATIC_INLINE void __disable_mmu(void) { |
Kojto | 111:4336505e4b1c | 403 | // Clear M bit 0 to disable the MMU |
Kojto | 111:4336505e4b1c | 404 | __set_SCTLR( __get_SCTLR() & ~1); |
Kojto | 111:4336505e4b1c | 405 | __ISB(); |
Kojto | 111:4336505e4b1c | 406 | } |
Kojto | 111:4336505e4b1c | 407 | |
Kojto | 111:4336505e4b1c | 408 | /******************************** TLB maintenance operations ************************************************/ |
Kojto | 111:4336505e4b1c | 409 | /** \brief Invalidate the whole tlb |
Kojto | 111:4336505e4b1c | 410 | |
Kojto | 111:4336505e4b1c | 411 | TLBIALL. Invalidate the whole tlb |
Kojto | 111:4336505e4b1c | 412 | */ |
Kojto | 111:4336505e4b1c | 413 | |
Kojto | 111:4336505e4b1c | 414 | __STATIC_INLINE void __ca9u_inv_tlb_all(void) { |
Kojto | 111:4336505e4b1c | 415 | register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); |
Kojto | 111:4336505e4b1c | 416 | __TLBIALL = 0; |
Kojto | 111:4336505e4b1c | 417 | __DSB(); |
Kojto | 111:4336505e4b1c | 418 | __ISB(); |
Kojto | 111:4336505e4b1c | 419 | } |
Kojto | 111:4336505e4b1c | 420 | |
Kojto | 111:4336505e4b1c | 421 | /******************************** BTB maintenance operations ************************************************/ |
Kojto | 111:4336505e4b1c | 422 | /** \brief Invalidate entire branch predictor array |
Kojto | 111:4336505e4b1c | 423 | |
Kojto | 111:4336505e4b1c | 424 | BPIALL. Branch Predictor Invalidate All. |
Kojto | 111:4336505e4b1c | 425 | */ |
Kojto | 111:4336505e4b1c | 426 | |
Kojto | 111:4336505e4b1c | 427 | __STATIC_INLINE void __v7_inv_btac(void) { |
Kojto | 111:4336505e4b1c | 428 | register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); |
Kojto | 111:4336505e4b1c | 429 | __BPIALL = 0; |
Kojto | 111:4336505e4b1c | 430 | __DSB(); //ensure completion of the invalidation |
Kojto | 111:4336505e4b1c | 431 | __ISB(); //ensure instruction fetch path sees new state |
Kojto | 111:4336505e4b1c | 432 | } |
Kojto | 111:4336505e4b1c | 433 | |
Kojto | 111:4336505e4b1c | 434 | |
Kojto | 111:4336505e4b1c | 435 | /******************************** L1 cache operations ******************************************************/ |
Kojto | 111:4336505e4b1c | 436 | |
Kojto | 111:4336505e4b1c | 437 | /** \brief Invalidate the whole I$ |
Kojto | 111:4336505e4b1c | 438 | |
Kojto | 111:4336505e4b1c | 439 | ICIALLU. Instruction Cache Invalidate All to PoU |
Kojto | 111:4336505e4b1c | 440 | */ |
Kojto | 111:4336505e4b1c | 441 | __STATIC_INLINE void __v7_inv_icache_all(void) { |
Kojto | 111:4336505e4b1c | 442 | register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); |
Kojto | 111:4336505e4b1c | 443 | __ICIALLU = 0; |
Kojto | 111:4336505e4b1c | 444 | __DSB(); //ensure completion of the invalidation |
Kojto | 111:4336505e4b1c | 445 | __ISB(); //ensure instruction fetch path sees new I cache state |
Kojto | 111:4336505e4b1c | 446 | } |
Kojto | 111:4336505e4b1c | 447 | |
Kojto | 111:4336505e4b1c | 448 | /** \brief Clean D$ by MVA |
Kojto | 111:4336505e4b1c | 449 | |
Kojto | 111:4336505e4b1c | 450 | DCCMVAC. Data cache clean by MVA to PoC |
Kojto | 111:4336505e4b1c | 451 | */ |
Kojto | 111:4336505e4b1c | 452 | __STATIC_INLINE void __v7_clean_dcache_mva(void *va) { |
Kojto | 111:4336505e4b1c | 453 | register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); |
Kojto | 111:4336505e4b1c | 454 | __DCCMVAC = (uint32_t)va; |
Kojto | 111:4336505e4b1c | 455 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 111:4336505e4b1c | 456 | } |
Kojto | 111:4336505e4b1c | 457 | |
Kojto | 111:4336505e4b1c | 458 | /** \brief Invalidate D$ by MVA |
Kojto | 111:4336505e4b1c | 459 | |
Kojto | 111:4336505e4b1c | 460 | DCIMVAC. Data cache invalidate by MVA to PoC |
Kojto | 111:4336505e4b1c | 461 | */ |
Kojto | 111:4336505e4b1c | 462 | __STATIC_INLINE void __v7_inv_dcache_mva(void *va) { |
Kojto | 111:4336505e4b1c | 463 | register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); |
Kojto | 111:4336505e4b1c | 464 | __DCIMVAC = (uint32_t)va; |
Kojto | 111:4336505e4b1c | 465 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 111:4336505e4b1c | 466 | } |
Kojto | 111:4336505e4b1c | 467 | |
Kojto | 111:4336505e4b1c | 468 | /** \brief Clean and Invalidate D$ by MVA |
Kojto | 111:4336505e4b1c | 469 | |
Kojto | 111:4336505e4b1c | 470 | DCCIMVAC. Data cache clean and invalidate by MVA to PoC |
Kojto | 111:4336505e4b1c | 471 | */ |
Kojto | 111:4336505e4b1c | 472 | __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { |
Kojto | 111:4336505e4b1c | 473 | register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); |
Kojto | 111:4336505e4b1c | 474 | __DCCIMVAC = (uint32_t)va; |
Kojto | 111:4336505e4b1c | 475 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 111:4336505e4b1c | 476 | } |
Kojto | 111:4336505e4b1c | 477 | |
Kojto | 111:4336505e4b1c | 478 | /** \brief Clean and Invalidate the entire data or unified cache |
Kojto | 111:4336505e4b1c | 479 | |
Kojto | 111:4336505e4b1c | 480 | Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. |
Kojto | 111:4336505e4b1c | 481 | */ |
Kojto | 111:4336505e4b1c | 482 | #pragma push |
Kojto | 111:4336505e4b1c | 483 | #pragma arm |
Kojto | 111:4336505e4b1c | 484 | __STATIC_ASM void __v7_all_cache(uint32_t op) { |
Kojto | 111:4336505e4b1c | 485 | ARM |
Kojto | 111:4336505e4b1c | 486 | |
Kojto | 111:4336505e4b1c | 487 | PUSH {R4-R11} |
Kojto | 111:4336505e4b1c | 488 | |
Kojto | 111:4336505e4b1c | 489 | MRC p15, 1, R6, c0, c0, 1 // Read CLIDR |
Kojto | 111:4336505e4b1c | 490 | ANDS R3, R6, #0x07000000 // Extract coherency level |
Kojto | 111:4336505e4b1c | 491 | MOV R3, R3, LSR #23 // Total cache levels << 1 |
Kojto | 111:4336505e4b1c | 492 | BEQ Finished // If 0, no need to clean |
Kojto | 111:4336505e4b1c | 493 | |
Kojto | 111:4336505e4b1c | 494 | MOV R10, #0 // R10 holds current cache level << 1 |
Kojto | 111:4336505e4b1c | 495 | Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position |
Kojto | 111:4336505e4b1c | 496 | MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level |
Kojto | 111:4336505e4b1c | 497 | AND R1, R1, #7 // Isolate those lower 3 bits |
Kojto | 111:4336505e4b1c | 498 | CMP R1, #2 |
Kojto | 111:4336505e4b1c | 499 | BLT Skip // No cache or only instruction cache at this level |
Kojto | 111:4336505e4b1c | 500 | |
Kojto | 111:4336505e4b1c | 501 | MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register |
Kojto | 111:4336505e4b1c | 502 | ISB // ISB to sync the change to the CacheSizeID reg |
Kojto | 111:4336505e4b1c | 503 | MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register |
Kojto | 111:4336505e4b1c | 504 | AND R2, R1, #7 // Extract the line length field |
Kojto | 111:4336505e4b1c | 505 | ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) |
Kojto | 111:4336505e4b1c | 506 | LDR R4, =0x3FF |
Kojto | 111:4336505e4b1c | 507 | ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) |
Kojto | 111:4336505e4b1c | 508 | CLZ R5, R4 // R5 is the bit position of the way size increment |
Kojto | 111:4336505e4b1c | 509 | LDR R7, =0x7FFF |
Kojto | 111:4336505e4b1c | 510 | ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) |
Kojto | 111:4336505e4b1c | 511 | |
Kojto | 111:4336505e4b1c | 512 | Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned) |
Kojto | 111:4336505e4b1c | 513 | |
Kojto | 111:4336505e4b1c | 514 | Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 |
Kojto | 111:4336505e4b1c | 515 | ORR R11, R11, R7, LSL R2 // Factor in the Set number |
Kojto | 111:4336505e4b1c | 516 | CMP R0, #0 |
Kojto | 111:4336505e4b1c | 517 | BNE Dccsw |
Kojto | 111:4336505e4b1c | 518 | MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way |
Kojto | 111:4336505e4b1c | 519 | B cont |
Kojto | 111:4336505e4b1c | 520 | Dccsw CMP R0, #1 |
Kojto | 111:4336505e4b1c | 521 | BNE Dccisw |
Kojto | 111:4336505e4b1c | 522 | MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way |
Kojto | 111:4336505e4b1c | 523 | B cont |
Kojto | 111:4336505e4b1c | 524 | Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way |
Kojto | 111:4336505e4b1c | 525 | cont SUBS R9, R9, #1 // Decrement the Way number |
Kojto | 111:4336505e4b1c | 526 | BGE Loop3 |
Kojto | 111:4336505e4b1c | 527 | SUBS R7, R7, #1 // Decrement the Set number |
Kojto | 111:4336505e4b1c | 528 | BGE Loop2 |
Kojto | 111:4336505e4b1c | 529 | Skip ADD R10, R10, #2 // Increment the cache number |
Kojto | 111:4336505e4b1c | 530 | CMP R3, R10 |
Kojto | 111:4336505e4b1c | 531 | BGT Loop1 |
Kojto | 111:4336505e4b1c | 532 | |
Kojto | 111:4336505e4b1c | 533 | Finished |
Kojto | 111:4336505e4b1c | 534 | DSB |
Kojto | 111:4336505e4b1c | 535 | POP {R4-R11} |
Kojto | 111:4336505e4b1c | 536 | BX lr |
Kojto | 111:4336505e4b1c | 537 | |
Kojto | 111:4336505e4b1c | 538 | } |
Kojto | 111:4336505e4b1c | 539 | #pragma pop |
Kojto | 111:4336505e4b1c | 540 | |
Kojto | 111:4336505e4b1c | 541 | |
Kojto | 111:4336505e4b1c | 542 | /** \brief Invalidate the whole D$ |
Kojto | 111:4336505e4b1c | 543 | |
Kojto | 111:4336505e4b1c | 544 | DCISW. Invalidate by Set/Way |
Kojto | 111:4336505e4b1c | 545 | */ |
Kojto | 111:4336505e4b1c | 546 | |
Kojto | 111:4336505e4b1c | 547 | __STATIC_INLINE void __v7_inv_dcache_all(void) { |
Kojto | 111:4336505e4b1c | 548 | __v7_all_cache(0); |
Kojto | 111:4336505e4b1c | 549 | } |
Kojto | 111:4336505e4b1c | 550 | |
Kojto | 111:4336505e4b1c | 551 | /** \brief Clean the whole D$ |
Kojto | 111:4336505e4b1c | 552 | |
Kojto | 111:4336505e4b1c | 553 | DCCSW. Clean by Set/Way |
Kojto | 111:4336505e4b1c | 554 | */ |
Kojto | 111:4336505e4b1c | 555 | |
Kojto | 111:4336505e4b1c | 556 | __STATIC_INLINE void __v7_clean_dcache_all(void) { |
Kojto | 111:4336505e4b1c | 557 | __v7_all_cache(1); |
Kojto | 111:4336505e4b1c | 558 | } |
Kojto | 111:4336505e4b1c | 559 | |
Kojto | 111:4336505e4b1c | 560 | /** \brief Clean and invalidate the whole D$ |
Kojto | 111:4336505e4b1c | 561 | |
Kojto | 111:4336505e4b1c | 562 | DCCISW. Clean and Invalidate by Set/Way |
Kojto | 111:4336505e4b1c | 563 | */ |
Kojto | 111:4336505e4b1c | 564 | |
Kojto | 111:4336505e4b1c | 565 | __STATIC_INLINE void __v7_clean_inv_dcache_all(void) { |
Kojto | 111:4336505e4b1c | 566 | __v7_all_cache(2); |
Kojto | 111:4336505e4b1c | 567 | } |
Kojto | 111:4336505e4b1c | 568 | |
Kojto | 111:4336505e4b1c | 569 | #include "core_ca_mmu.h" |
Kojto | 111:4336505e4b1c | 570 | |
Kojto | 111:4336505e4b1c | 571 | #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ |
Kojto | 111:4336505e4b1c | 572 | |
Kojto | 111:4336505e4b1c | 573 | #error IAR Compiler support not implemented for Cortex-A |
Kojto | 111:4336505e4b1c | 574 | |
Kojto | 111:4336505e4b1c | 575 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
Kojto | 111:4336505e4b1c | 576 | /* GNU gcc specific functions */ |
Kojto | 111:4336505e4b1c | 577 | |
Kojto | 111:4336505e4b1c | 578 | #define MODE_USR 0x10 |
Kojto | 111:4336505e4b1c | 579 | #define MODE_FIQ 0x11 |
Kojto | 111:4336505e4b1c | 580 | #define MODE_IRQ 0x12 |
Kojto | 111:4336505e4b1c | 581 | #define MODE_SVC 0x13 |
Kojto | 111:4336505e4b1c | 582 | #define MODE_MON 0x16 |
Kojto | 111:4336505e4b1c | 583 | #define MODE_ABT 0x17 |
Kojto | 111:4336505e4b1c | 584 | #define MODE_HYP 0x1A |
Kojto | 111:4336505e4b1c | 585 | #define MODE_UND 0x1B |
Kojto | 111:4336505e4b1c | 586 | #define MODE_SYS 0x1F |
Kojto | 111:4336505e4b1c | 587 | |
Kojto | 111:4336505e4b1c | 588 | |
Kojto | 111:4336505e4b1c | 589 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) |
Kojto | 111:4336505e4b1c | 590 | { |
Kojto | 111:4336505e4b1c | 591 | __ASM volatile ("cpsie i"); |
Kojto | 111:4336505e4b1c | 592 | } |
Kojto | 111:4336505e4b1c | 593 | |
Kojto | 111:4336505e4b1c | 594 | /** \brief Disable IRQ Interrupts |
Kojto | 111:4336505e4b1c | 595 | |
Kojto | 111:4336505e4b1c | 596 | This function disables IRQ interrupts by setting the I-bit in the CPSR. |
Kojto | 111:4336505e4b1c | 597 | Can only be executed in Privileged modes. |
Kojto | 111:4336505e4b1c | 598 | */ |
Kojto | 111:4336505e4b1c | 599 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void) |
Kojto | 111:4336505e4b1c | 600 | { |
Kojto | 111:4336505e4b1c | 601 | uint32_t result; |
Kojto | 111:4336505e4b1c | 602 | |
Kojto | 111:4336505e4b1c | 603 | __ASM volatile ("mrs %0, cpsr" : "=r" (result)); |
Kojto | 111:4336505e4b1c | 604 | __ASM volatile ("cpsid i"); |
Kojto | 111:4336505e4b1c | 605 | return(result & 0x80); |
Kojto | 111:4336505e4b1c | 606 | } |
Kojto | 111:4336505e4b1c | 607 | |
Kojto | 111:4336505e4b1c | 608 | |
Kojto | 111:4336505e4b1c | 609 | /** \brief Get APSR Register |
Kojto | 111:4336505e4b1c | 610 | |
Kojto | 111:4336505e4b1c | 611 | This function returns the content of the APSR Register. |
Kojto | 111:4336505e4b1c | 612 | |
Kojto | 111:4336505e4b1c | 613 | \return APSR Register value |
Kojto | 111:4336505e4b1c | 614 | */ |
Kojto | 111:4336505e4b1c | 615 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) |
Kojto | 111:4336505e4b1c | 616 | { |
Kojto | 111:4336505e4b1c | 617 | #if 1 |
Kojto | 111:4336505e4b1c | 618 | register uint32_t __regAPSR; |
Kojto | 111:4336505e4b1c | 619 | __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) ); |
Kojto | 111:4336505e4b1c | 620 | #else |
Kojto | 111:4336505e4b1c | 621 | register uint32_t __regAPSR __ASM("apsr"); |
Kojto | 111:4336505e4b1c | 622 | #endif |
Kojto | 111:4336505e4b1c | 623 | return(__regAPSR); |
Kojto | 111:4336505e4b1c | 624 | } |
Kojto | 111:4336505e4b1c | 625 | |
Kojto | 111:4336505e4b1c | 626 | |
Kojto | 111:4336505e4b1c | 627 | /** \brief Get CPSR Register |
Kojto | 111:4336505e4b1c | 628 | |
Kojto | 111:4336505e4b1c | 629 | This function returns the content of the CPSR Register. |
Kojto | 111:4336505e4b1c | 630 | |
Kojto | 111:4336505e4b1c | 631 | \return CPSR Register value |
Kojto | 111:4336505e4b1c | 632 | */ |
Kojto | 111:4336505e4b1c | 633 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) |
Kojto | 111:4336505e4b1c | 634 | { |
Kojto | 111:4336505e4b1c | 635 | #if 1 |
Kojto | 111:4336505e4b1c | 636 | register uint32_t __regCPSR; |
Kojto | 111:4336505e4b1c | 637 | __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR)); |
Kojto | 111:4336505e4b1c | 638 | #else |
Kojto | 111:4336505e4b1c | 639 | register uint32_t __regCPSR __ASM("cpsr"); |
Kojto | 111:4336505e4b1c | 640 | #endif |
Kojto | 111:4336505e4b1c | 641 | return(__regCPSR); |
Kojto | 111:4336505e4b1c | 642 | } |
Kojto | 111:4336505e4b1c | 643 | |
Kojto | 111:4336505e4b1c | 644 | #if 0 |
Kojto | 111:4336505e4b1c | 645 | /** \brief Set Stack Pointer |
Kojto | 111:4336505e4b1c | 646 | |
Kojto | 111:4336505e4b1c | 647 | This function assigns the given value to the current stack pointer. |
Kojto | 111:4336505e4b1c | 648 | |
Kojto | 111:4336505e4b1c | 649 | \param [in] topOfStack Stack Pointer value to set |
Kojto | 111:4336505e4b1c | 650 | */ |
Kojto | 111:4336505e4b1c | 651 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack) |
Kojto | 111:4336505e4b1c | 652 | { |
Kojto | 111:4336505e4b1c | 653 | register uint32_t __regSP __ASM("sp"); |
Kojto | 111:4336505e4b1c | 654 | __regSP = topOfStack; |
Kojto | 111:4336505e4b1c | 655 | } |
Kojto | 111:4336505e4b1c | 656 | #endif |
Kojto | 111:4336505e4b1c | 657 | |
Kojto | 111:4336505e4b1c | 658 | /** \brief Get link register |
Kojto | 111:4336505e4b1c | 659 | |
Kojto | 111:4336505e4b1c | 660 | This function returns the value of the link register |
Kojto | 111:4336505e4b1c | 661 | |
Kojto | 111:4336505e4b1c | 662 | \return Value of link register |
Kojto | 111:4336505e4b1c | 663 | */ |
Kojto | 111:4336505e4b1c | 664 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void) |
Kojto | 111:4336505e4b1c | 665 | { |
Kojto | 111:4336505e4b1c | 666 | register uint32_t __reglr __ASM("lr"); |
Kojto | 111:4336505e4b1c | 667 | return(__reglr); |
Kojto | 111:4336505e4b1c | 668 | } |
Kojto | 111:4336505e4b1c | 669 | |
Kojto | 111:4336505e4b1c | 670 | #if 0 |
Kojto | 111:4336505e4b1c | 671 | /** \brief Set link register |
Kojto | 111:4336505e4b1c | 672 | |
Kojto | 111:4336505e4b1c | 673 | This function sets the value of the link register |
Kojto | 111:4336505e4b1c | 674 | |
Kojto | 111:4336505e4b1c | 675 | \param [in] lr LR value to set |
Kojto | 111:4336505e4b1c | 676 | */ |
Kojto | 111:4336505e4b1c | 677 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr) |
Kojto | 111:4336505e4b1c | 678 | { |
Kojto | 111:4336505e4b1c | 679 | register uint32_t __reglr __ASM("lr"); |
Kojto | 111:4336505e4b1c | 680 | __reglr = lr; |
Kojto | 111:4336505e4b1c | 681 | } |
Kojto | 111:4336505e4b1c | 682 | #endif |
Kojto | 111:4336505e4b1c | 683 | |
Kojto | 111:4336505e4b1c | 684 | /** \brief Set Process Stack Pointer |
Kojto | 111:4336505e4b1c | 685 | |
Kojto | 111:4336505e4b1c | 686 | This function assigns the given value to the USR/SYS Stack Pointer (PSP). |
Kojto | 111:4336505e4b1c | 687 | |
Kojto | 111:4336505e4b1c | 688 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
Kojto | 111:4336505e4b1c | 689 | */ |
Kojto | 111:4336505e4b1c | 690 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
Kojto | 111:4336505e4b1c | 691 | { |
Kojto | 111:4336505e4b1c | 692 | __asm__ volatile ( |
Kojto | 111:4336505e4b1c | 693 | ".ARM;" |
Kojto | 111:4336505e4b1c | 694 | ".eabi_attribute Tag_ABI_align8_preserved,1;" |
Kojto | 111:4336505e4b1c | 695 | |
Kojto | 111:4336505e4b1c | 696 | "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */ |
Kojto | 111:4336505e4b1c | 697 | "MRS R1, CPSR;" |
Kojto | 111:4336505e4b1c | 698 | "CPS %0;" /* ;no effect in USR mode */ |
Kojto | 111:4336505e4b1c | 699 | "MOV SP, R0;" |
Kojto | 111:4336505e4b1c | 700 | "MSR CPSR_c, R1;" /* ;no effect in USR mode */ |
Kojto | 111:4336505e4b1c | 701 | "ISB;" |
Kojto | 111:4336505e4b1c | 702 | //"BX LR;" |
Kojto | 111:4336505e4b1c | 703 | : |
Kojto | 111:4336505e4b1c | 704 | : "i"(MODE_SYS) |
Kojto | 111:4336505e4b1c | 705 | : "r0", "r1"); |
Kojto | 111:4336505e4b1c | 706 | return; |
Kojto | 111:4336505e4b1c | 707 | } |
Kojto | 111:4336505e4b1c | 708 | |
Kojto | 111:4336505e4b1c | 709 | /** \brief Set User Mode |
Kojto | 111:4336505e4b1c | 710 | |
Kojto | 111:4336505e4b1c | 711 | This function changes the processor state to User Mode |
Kojto | 111:4336505e4b1c | 712 | */ |
Kojto | 111:4336505e4b1c | 713 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void) |
Kojto | 111:4336505e4b1c | 714 | { |
Kojto | 111:4336505e4b1c | 715 | __asm__ volatile ( |
Kojto | 111:4336505e4b1c | 716 | ".ARM;" |
Kojto | 111:4336505e4b1c | 717 | |
Kojto | 111:4336505e4b1c | 718 | "CPS %0;" |
Kojto | 111:4336505e4b1c | 719 | //"BX LR;" |
Kojto | 111:4336505e4b1c | 720 | : |
Kojto | 111:4336505e4b1c | 721 | : "i"(MODE_USR) |
Kojto | 111:4336505e4b1c | 722 | : ); |
Kojto | 111:4336505e4b1c | 723 | return; |
Kojto | 111:4336505e4b1c | 724 | } |
Kojto | 111:4336505e4b1c | 725 | |
Kojto | 111:4336505e4b1c | 726 | |
Kojto | 111:4336505e4b1c | 727 | /** \brief Enable FIQ |
Kojto | 111:4336505e4b1c | 728 | |
Kojto | 111:4336505e4b1c | 729 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
Kojto | 111:4336505e4b1c | 730 | Can only be executed in Privileged modes. |
Kojto | 111:4336505e4b1c | 731 | */ |
Kojto | 111:4336505e4b1c | 732 | #define __enable_fault_irq() __asm__ volatile ("cpsie f") |
Kojto | 111:4336505e4b1c | 733 | |
Kojto | 111:4336505e4b1c | 734 | |
Kojto | 111:4336505e4b1c | 735 | /** \brief Disable FIQ |
Kojto | 111:4336505e4b1c | 736 | |
Kojto | 111:4336505e4b1c | 737 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
Kojto | 111:4336505e4b1c | 738 | Can only be executed in Privileged modes. |
Kojto | 111:4336505e4b1c | 739 | */ |
Kojto | 111:4336505e4b1c | 740 | #define __disable_fault_irq() __asm__ volatile ("cpsid f") |
Kojto | 111:4336505e4b1c | 741 | |
Kojto | 111:4336505e4b1c | 742 | |
Kojto | 111:4336505e4b1c | 743 | /** \brief Get FPSCR |
Kojto | 111:4336505e4b1c | 744 | |
Kojto | 111:4336505e4b1c | 745 | This function returns the current value of the Floating Point Status/Control register. |
Kojto | 111:4336505e4b1c | 746 | |
Kojto | 111:4336505e4b1c | 747 | \return Floating Point Status/Control register value |
Kojto | 111:4336505e4b1c | 748 | */ |
Kojto | 111:4336505e4b1c | 749 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) |
Kojto | 111:4336505e4b1c | 750 | { |
Kojto | 111:4336505e4b1c | 751 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
Kojto | 111:4336505e4b1c | 752 | #if 1 |
Kojto | 111:4336505e4b1c | 753 | uint32_t result; |
Kojto | 111:4336505e4b1c | 754 | |
Kojto | 111:4336505e4b1c | 755 | __ASM volatile ("vmrs %0, fpscr" : "=r" (result) ); |
Kojto | 111:4336505e4b1c | 756 | return (result); |
Kojto | 111:4336505e4b1c | 757 | #else |
Kojto | 111:4336505e4b1c | 758 | register uint32_t __regfpscr __ASM("fpscr"); |
Kojto | 111:4336505e4b1c | 759 | return(__regfpscr); |
Kojto | 111:4336505e4b1c | 760 | #endif |
Kojto | 111:4336505e4b1c | 761 | #else |
Kojto | 111:4336505e4b1c | 762 | return(0); |
Kojto | 111:4336505e4b1c | 763 | #endif |
Kojto | 111:4336505e4b1c | 764 | } |
Kojto | 111:4336505e4b1c | 765 | |
Kojto | 111:4336505e4b1c | 766 | |
Kojto | 111:4336505e4b1c | 767 | /** \brief Set FPSCR |
Kojto | 111:4336505e4b1c | 768 | |
Kojto | 111:4336505e4b1c | 769 | This function assigns the given value to the Floating Point Status/Control register. |
Kojto | 111:4336505e4b1c | 770 | |
Kojto | 111:4336505e4b1c | 771 | \param [in] fpscr Floating Point Status/Control value to set |
Kojto | 111:4336505e4b1c | 772 | */ |
Kojto | 111:4336505e4b1c | 773 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
Kojto | 111:4336505e4b1c | 774 | { |
Kojto | 111:4336505e4b1c | 775 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
Kojto | 111:4336505e4b1c | 776 | #if 1 |
Kojto | 111:4336505e4b1c | 777 | __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) ); |
Kojto | 111:4336505e4b1c | 778 | #else |
Kojto | 111:4336505e4b1c | 779 | register uint32_t __regfpscr __ASM("fpscr"); |
Kojto | 111:4336505e4b1c | 780 | __regfpscr = (fpscr); |
Kojto | 111:4336505e4b1c | 781 | #endif |
Kojto | 111:4336505e4b1c | 782 | #endif |
Kojto | 111:4336505e4b1c | 783 | } |
Kojto | 111:4336505e4b1c | 784 | |
Kojto | 111:4336505e4b1c | 785 | /** \brief Get FPEXC |
Kojto | 111:4336505e4b1c | 786 | |
Kojto | 111:4336505e4b1c | 787 | This function returns the current value of the Floating Point Exception Control register. |
Kojto | 111:4336505e4b1c | 788 | |
Kojto | 111:4336505e4b1c | 789 | \return Floating Point Exception Control register value |
Kojto | 111:4336505e4b1c | 790 | */ |
Kojto | 111:4336505e4b1c | 791 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) |
Kojto | 111:4336505e4b1c | 792 | { |
Kojto | 111:4336505e4b1c | 793 | #if (__FPU_PRESENT == 1) |
Kojto | 111:4336505e4b1c | 794 | #if 1 |
Kojto | 111:4336505e4b1c | 795 | uint32_t result; |
Kojto | 111:4336505e4b1c | 796 | |
Kojto | 111:4336505e4b1c | 797 | __ASM volatile ("vmrs %0, fpexc" : "=r" (result)); |
Kojto | 111:4336505e4b1c | 798 | return (result); |
Kojto | 111:4336505e4b1c | 799 | #else |
Kojto | 111:4336505e4b1c | 800 | register uint32_t __regfpexc __ASM("fpexc"); |
Kojto | 111:4336505e4b1c | 801 | return(__regfpexc); |
Kojto | 111:4336505e4b1c | 802 | #endif |
Kojto | 111:4336505e4b1c | 803 | #else |
Kojto | 111:4336505e4b1c | 804 | return(0); |
Kojto | 111:4336505e4b1c | 805 | #endif |
Kojto | 111:4336505e4b1c | 806 | } |
Kojto | 111:4336505e4b1c | 807 | |
Kojto | 111:4336505e4b1c | 808 | |
Kojto | 111:4336505e4b1c | 809 | /** \brief Set FPEXC |
Kojto | 111:4336505e4b1c | 810 | |
Kojto | 111:4336505e4b1c | 811 | This function assigns the given value to the Floating Point Exception Control register. |
Kojto | 111:4336505e4b1c | 812 | |
Kojto | 111:4336505e4b1c | 813 | \param [in] fpscr Floating Point Exception Control value to set |
Kojto | 111:4336505e4b1c | 814 | */ |
Kojto | 111:4336505e4b1c | 815 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
Kojto | 111:4336505e4b1c | 816 | { |
Kojto | 111:4336505e4b1c | 817 | #if (__FPU_PRESENT == 1) |
Kojto | 111:4336505e4b1c | 818 | #if 1 |
Kojto | 111:4336505e4b1c | 819 | __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc)); |
Kojto | 111:4336505e4b1c | 820 | #else |
Kojto | 111:4336505e4b1c | 821 | register uint32_t __regfpexc __ASM("fpexc"); |
Kojto | 111:4336505e4b1c | 822 | __regfpexc = (fpexc); |
Kojto | 111:4336505e4b1c | 823 | #endif |
Kojto | 111:4336505e4b1c | 824 | #endif |
Kojto | 111:4336505e4b1c | 825 | } |
Kojto | 111:4336505e4b1c | 826 | |
Kojto | 111:4336505e4b1c | 827 | /** \brief Get CPACR |
Kojto | 111:4336505e4b1c | 828 | |
Kojto | 111:4336505e4b1c | 829 | This function returns the current value of the Coprocessor Access Control register. |
Kojto | 111:4336505e4b1c | 830 | |
Kojto | 111:4336505e4b1c | 831 | \return Coprocessor Access Control register value |
Kojto | 111:4336505e4b1c | 832 | */ |
Kojto | 111:4336505e4b1c | 833 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void) |
Kojto | 111:4336505e4b1c | 834 | { |
Kojto | 111:4336505e4b1c | 835 | #if 1 |
Kojto | 111:4336505e4b1c | 836 | register uint32_t __regCPACR; |
Kojto | 111:4336505e4b1c | 837 | __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR)); |
Kojto | 111:4336505e4b1c | 838 | #else |
Kojto | 111:4336505e4b1c | 839 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
Kojto | 111:4336505e4b1c | 840 | #endif |
Kojto | 111:4336505e4b1c | 841 | return __regCPACR; |
Kojto | 111:4336505e4b1c | 842 | } |
Kojto | 111:4336505e4b1c | 843 | |
Kojto | 111:4336505e4b1c | 844 | /** \brief Set CPACR |
Kojto | 111:4336505e4b1c | 845 | |
Kojto | 111:4336505e4b1c | 846 | This function assigns the given value to the Coprocessor Access Control register. |
Kojto | 111:4336505e4b1c | 847 | |
Kojto | 111:4336505e4b1c | 848 | \param [in] cpacr Coprocessor Acccess Control value to set |
Kojto | 111:4336505e4b1c | 849 | */ |
Kojto | 111:4336505e4b1c | 850 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr) |
Kojto | 111:4336505e4b1c | 851 | { |
Kojto | 111:4336505e4b1c | 852 | #if 1 |
Kojto | 111:4336505e4b1c | 853 | __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr)); |
Kojto | 111:4336505e4b1c | 854 | #else |
Kojto | 111:4336505e4b1c | 855 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
Kojto | 111:4336505e4b1c | 856 | __regCPACR = cpacr; |
Kojto | 111:4336505e4b1c | 857 | #endif |
Kojto | 111:4336505e4b1c | 858 | __ISB(); |
Kojto | 111:4336505e4b1c | 859 | } |
Kojto | 111:4336505e4b1c | 860 | |
Kojto | 111:4336505e4b1c | 861 | /** \brief Get CBAR |
Kojto | 111:4336505e4b1c | 862 | |
Kojto | 111:4336505e4b1c | 863 | This function returns the value of the Configuration Base Address register. |
Kojto | 111:4336505e4b1c | 864 | |
Kojto | 111:4336505e4b1c | 865 | \return Configuration Base Address register value |
Kojto | 111:4336505e4b1c | 866 | */ |
Kojto | 111:4336505e4b1c | 867 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() { |
Kojto | 111:4336505e4b1c | 868 | #if 1 |
Kojto | 111:4336505e4b1c | 869 | register uint32_t __regCBAR; |
Kojto | 111:4336505e4b1c | 870 | __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR)); |
Kojto | 111:4336505e4b1c | 871 | #else |
Kojto | 111:4336505e4b1c | 872 | register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); |
Kojto | 111:4336505e4b1c | 873 | #endif |
Kojto | 111:4336505e4b1c | 874 | return(__regCBAR); |
Kojto | 111:4336505e4b1c | 875 | } |
Kojto | 111:4336505e4b1c | 876 | |
Kojto | 111:4336505e4b1c | 877 | /** \brief Get TTBR0 |
Kojto | 111:4336505e4b1c | 878 | |
Kojto | 111:4336505e4b1c | 879 | This function returns the value of the Translation Table Base Register 0. |
Kojto | 111:4336505e4b1c | 880 | |
Kojto | 111:4336505e4b1c | 881 | \return Translation Table Base Register 0 value |
Kojto | 111:4336505e4b1c | 882 | */ |
Kojto | 111:4336505e4b1c | 883 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() { |
Kojto | 111:4336505e4b1c | 884 | #if 1 |
Kojto | 111:4336505e4b1c | 885 | register uint32_t __regTTBR0; |
Kojto | 111:4336505e4b1c | 886 | __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0)); |
Kojto | 111:4336505e4b1c | 887 | #else |
Kojto | 111:4336505e4b1c | 888 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
Kojto | 111:4336505e4b1c | 889 | #endif |
Kojto | 111:4336505e4b1c | 890 | return(__regTTBR0); |
Kojto | 111:4336505e4b1c | 891 | } |
Kojto | 111:4336505e4b1c | 892 | |
Kojto | 111:4336505e4b1c | 893 | /** \brief Set TTBR0 |
Kojto | 111:4336505e4b1c | 894 | |
Kojto | 111:4336505e4b1c | 895 | This function assigns the given value to the Translation Table Base Register 0. |
Kojto | 111:4336505e4b1c | 896 | |
Kojto | 111:4336505e4b1c | 897 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
Kojto | 111:4336505e4b1c | 898 | */ |
Kojto | 111:4336505e4b1c | 899 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
Kojto | 111:4336505e4b1c | 900 | #if 1 |
Kojto | 111:4336505e4b1c | 901 | __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0)); |
Kojto | 111:4336505e4b1c | 902 | #else |
Kojto | 111:4336505e4b1c | 903 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
Kojto | 111:4336505e4b1c | 904 | __regTTBR0 = ttbr0; |
Kojto | 111:4336505e4b1c | 905 | #endif |
Kojto | 111:4336505e4b1c | 906 | __ISB(); |
Kojto | 111:4336505e4b1c | 907 | } |
Kojto | 111:4336505e4b1c | 908 | |
Kojto | 111:4336505e4b1c | 909 | /** \brief Get DACR |
Kojto | 111:4336505e4b1c | 910 | |
Kojto | 111:4336505e4b1c | 911 | This function returns the value of the Domain Access Control Register. |
Kojto | 111:4336505e4b1c | 912 | |
Kojto | 111:4336505e4b1c | 913 | \return Domain Access Control Register value |
Kojto | 111:4336505e4b1c | 914 | */ |
Kojto | 111:4336505e4b1c | 915 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() { |
Kojto | 111:4336505e4b1c | 916 | #if 1 |
Kojto | 111:4336505e4b1c | 917 | register uint32_t __regDACR; |
Kojto | 111:4336505e4b1c | 918 | __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR)); |
Kojto | 111:4336505e4b1c | 919 | #else |
Kojto | 111:4336505e4b1c | 920 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
Kojto | 111:4336505e4b1c | 921 | #endif |
Kojto | 111:4336505e4b1c | 922 | return(__regDACR); |
Kojto | 111:4336505e4b1c | 923 | } |
Kojto | 111:4336505e4b1c | 924 | |
Kojto | 111:4336505e4b1c | 925 | /** \brief Set DACR |
Kojto | 111:4336505e4b1c | 926 | |
Kojto | 111:4336505e4b1c | 927 | This function assigns the given value to the Domain Access Control Register. |
Kojto | 111:4336505e4b1c | 928 | |
Kojto | 111:4336505e4b1c | 929 | \param [in] dacr Domain Access Control Register value to set |
Kojto | 111:4336505e4b1c | 930 | */ |
Kojto | 111:4336505e4b1c | 931 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
Kojto | 111:4336505e4b1c | 932 | #if 1 |
Kojto | 111:4336505e4b1c | 933 | __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr)); |
Kojto | 111:4336505e4b1c | 934 | #else |
Kojto | 111:4336505e4b1c | 935 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
Kojto | 111:4336505e4b1c | 936 | __regDACR = dacr; |
Kojto | 111:4336505e4b1c | 937 | #endif |
Kojto | 111:4336505e4b1c | 938 | __ISB(); |
Kojto | 111:4336505e4b1c | 939 | } |
Kojto | 111:4336505e4b1c | 940 | |
Kojto | 111:4336505e4b1c | 941 | /******************************** Cache and BTAC enable ****************************************************/ |
Kojto | 111:4336505e4b1c | 942 | |
Kojto | 111:4336505e4b1c | 943 | /** \brief Set SCTLR |
Kojto | 111:4336505e4b1c | 944 | |
Kojto | 111:4336505e4b1c | 945 | This function assigns the given value to the System Control Register. |
Kojto | 111:4336505e4b1c | 946 | |
Kojto | 111:4336505e4b1c | 947 | \param [in] sctlr System Control Register value to set |
Kojto | 111:4336505e4b1c | 948 | */ |
Kojto | 111:4336505e4b1c | 949 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) |
Kojto | 111:4336505e4b1c | 950 | { |
Kojto | 111:4336505e4b1c | 951 | #if 1 |
Kojto | 111:4336505e4b1c | 952 | __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr)); |
Kojto | 111:4336505e4b1c | 953 | #else |
Kojto | 111:4336505e4b1c | 954 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
Kojto | 111:4336505e4b1c | 955 | __regSCTLR = sctlr; |
Kojto | 111:4336505e4b1c | 956 | #endif |
Kojto | 111:4336505e4b1c | 957 | } |
Kojto | 111:4336505e4b1c | 958 | |
Kojto | 111:4336505e4b1c | 959 | /** \brief Get SCTLR |
Kojto | 111:4336505e4b1c | 960 | |
Kojto | 111:4336505e4b1c | 961 | This function returns the value of the System Control Register. |
Kojto | 111:4336505e4b1c | 962 | |
Kojto | 111:4336505e4b1c | 963 | \return System Control Register value |
Kojto | 111:4336505e4b1c | 964 | */ |
Kojto | 111:4336505e4b1c | 965 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() { |
Kojto | 111:4336505e4b1c | 966 | #if 1 |
Kojto | 111:4336505e4b1c | 967 | register uint32_t __regSCTLR; |
Kojto | 111:4336505e4b1c | 968 | __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR)); |
Kojto | 111:4336505e4b1c | 969 | #else |
Kojto | 111:4336505e4b1c | 970 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
Kojto | 111:4336505e4b1c | 971 | #endif |
Kojto | 111:4336505e4b1c | 972 | return(__regSCTLR); |
Kojto | 111:4336505e4b1c | 973 | } |
Kojto | 111:4336505e4b1c | 974 | |
Kojto | 111:4336505e4b1c | 975 | /** \brief Enable Caches |
Kojto | 111:4336505e4b1c | 976 | |
Kojto | 111:4336505e4b1c | 977 | Enable Caches |
Kojto | 111:4336505e4b1c | 978 | */ |
Kojto | 111:4336505e4b1c | 979 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) { |
Kojto | 111:4336505e4b1c | 980 | // Set I bit 12 to enable I Cache |
Kojto | 111:4336505e4b1c | 981 | // Set C bit 2 to enable D Cache |
Kojto | 111:4336505e4b1c | 982 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
Kojto | 111:4336505e4b1c | 983 | } |
Kojto | 111:4336505e4b1c | 984 | |
Kojto | 111:4336505e4b1c | 985 | /** \brief Disable Caches |
Kojto | 111:4336505e4b1c | 986 | |
Kojto | 111:4336505e4b1c | 987 | Disable Caches |
Kojto | 111:4336505e4b1c | 988 | */ |
Kojto | 111:4336505e4b1c | 989 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) { |
Kojto | 111:4336505e4b1c | 990 | // Clear I bit 12 to disable I Cache |
Kojto | 111:4336505e4b1c | 991 | // Clear C bit 2 to disable D Cache |
Kojto | 111:4336505e4b1c | 992 | __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); |
Kojto | 111:4336505e4b1c | 993 | __ISB(); |
Kojto | 111:4336505e4b1c | 994 | } |
Kojto | 111:4336505e4b1c | 995 | |
Kojto | 111:4336505e4b1c | 996 | /** \brief Enable BTAC |
Kojto | 111:4336505e4b1c | 997 | |
Kojto | 111:4336505e4b1c | 998 | Enable BTAC |
Kojto | 111:4336505e4b1c | 999 | */ |
Kojto | 111:4336505e4b1c | 1000 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) { |
Kojto | 111:4336505e4b1c | 1001 | // Set Z bit 11 to enable branch prediction |
Kojto | 111:4336505e4b1c | 1002 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
Kojto | 111:4336505e4b1c | 1003 | __ISB(); |
Kojto | 111:4336505e4b1c | 1004 | } |
Kojto | 111:4336505e4b1c | 1005 | |
Kojto | 111:4336505e4b1c | 1006 | /** \brief Disable BTAC |
Kojto | 111:4336505e4b1c | 1007 | |
Kojto | 111:4336505e4b1c | 1008 | Disable BTAC |
Kojto | 111:4336505e4b1c | 1009 | */ |
Kojto | 111:4336505e4b1c | 1010 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) { |
Kojto | 111:4336505e4b1c | 1011 | // Clear Z bit 11 to disable branch prediction |
Kojto | 111:4336505e4b1c | 1012 | __set_SCTLR( __get_SCTLR() & ~(1 << 11)); |
Kojto | 111:4336505e4b1c | 1013 | } |
Kojto | 111:4336505e4b1c | 1014 | |
Kojto | 111:4336505e4b1c | 1015 | |
Kojto | 111:4336505e4b1c | 1016 | /** \brief Enable MMU |
Kojto | 111:4336505e4b1c | 1017 | |
Kojto | 111:4336505e4b1c | 1018 | Enable MMU |
Kojto | 111:4336505e4b1c | 1019 | */ |
Kojto | 111:4336505e4b1c | 1020 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) { |
Kojto | 111:4336505e4b1c | 1021 | // Set M bit 0 to enable the MMU |
Kojto | 111:4336505e4b1c | 1022 | // Set AFE bit to enable simplified access permissions model |
Kojto | 111:4336505e4b1c | 1023 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
Kojto | 111:4336505e4b1c | 1024 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
Kojto | 111:4336505e4b1c | 1025 | __ISB(); |
Kojto | 111:4336505e4b1c | 1026 | } |
Kojto | 111:4336505e4b1c | 1027 | |
Kojto | 111:4336505e4b1c | 1028 | /** \brief Disable MMU |
Kojto | 111:4336505e4b1c | 1029 | |
Kojto | 111:4336505e4b1c | 1030 | Disable MMU |
Kojto | 111:4336505e4b1c | 1031 | */ |
Kojto | 111:4336505e4b1c | 1032 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) { |
Kojto | 111:4336505e4b1c | 1033 | // Clear M bit 0 to disable the MMU |
Kojto | 111:4336505e4b1c | 1034 | __set_SCTLR( __get_SCTLR() & ~1); |
Kojto | 111:4336505e4b1c | 1035 | __ISB(); |
Kojto | 111:4336505e4b1c | 1036 | } |
Kojto | 111:4336505e4b1c | 1037 | |
Kojto | 111:4336505e4b1c | 1038 | /******************************** TLB maintenance operations ************************************************/ |
Kojto | 111:4336505e4b1c | 1039 | /** \brief Invalidate the whole tlb |
Kojto | 111:4336505e4b1c | 1040 | |
Kojto | 111:4336505e4b1c | 1041 | TLBIALL. Invalidate the whole tlb |
Kojto | 111:4336505e4b1c | 1042 | */ |
Kojto | 111:4336505e4b1c | 1043 | |
Kojto | 111:4336505e4b1c | 1044 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) { |
Kojto | 111:4336505e4b1c | 1045 | #if 1 |
Kojto | 111:4336505e4b1c | 1046 | __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); |
Kojto | 111:4336505e4b1c | 1047 | #else |
Kojto | 111:4336505e4b1c | 1048 | register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); |
Kojto | 111:4336505e4b1c | 1049 | __TLBIALL = 0; |
Kojto | 111:4336505e4b1c | 1050 | #endif |
Kojto | 111:4336505e4b1c | 1051 | __DSB(); |
Kojto | 111:4336505e4b1c | 1052 | __ISB(); |
Kojto | 111:4336505e4b1c | 1053 | } |
Kojto | 111:4336505e4b1c | 1054 | |
Kojto | 111:4336505e4b1c | 1055 | /******************************** BTB maintenance operations ************************************************/ |
Kojto | 111:4336505e4b1c | 1056 | /** \brief Invalidate entire branch predictor array |
Kojto | 111:4336505e4b1c | 1057 | |
Kojto | 111:4336505e4b1c | 1058 | BPIALL. Branch Predictor Invalidate All. |
Kojto | 111:4336505e4b1c | 1059 | */ |
Kojto | 111:4336505e4b1c | 1060 | |
Kojto | 111:4336505e4b1c | 1061 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) { |
Kojto | 111:4336505e4b1c | 1062 | #if 1 |
Kojto | 111:4336505e4b1c | 1063 | __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); |
Kojto | 111:4336505e4b1c | 1064 | #else |
Kojto | 111:4336505e4b1c | 1065 | register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); |
Kojto | 111:4336505e4b1c | 1066 | __BPIALL = 0; |
Kojto | 111:4336505e4b1c | 1067 | #endif |
Kojto | 111:4336505e4b1c | 1068 | __DSB(); //ensure completion of the invalidation |
Kojto | 111:4336505e4b1c | 1069 | __ISB(); //ensure instruction fetch path sees new state |
Kojto | 111:4336505e4b1c | 1070 | } |
Kojto | 111:4336505e4b1c | 1071 | |
Kojto | 111:4336505e4b1c | 1072 | |
Kojto | 111:4336505e4b1c | 1073 | /******************************** L1 cache operations ******************************************************/ |
Kojto | 111:4336505e4b1c | 1074 | |
Kojto | 111:4336505e4b1c | 1075 | /** \brief Invalidate the whole I$ |
Kojto | 111:4336505e4b1c | 1076 | |
Kojto | 111:4336505e4b1c | 1077 | ICIALLU. Instruction Cache Invalidate All to PoU |
Kojto | 111:4336505e4b1c | 1078 | */ |
Kojto | 111:4336505e4b1c | 1079 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) { |
Kojto | 111:4336505e4b1c | 1080 | #if 1 |
Kojto | 111:4336505e4b1c | 1081 | __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); |
Kojto | 111:4336505e4b1c | 1082 | #else |
Kojto | 111:4336505e4b1c | 1083 | register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); |
Kojto | 111:4336505e4b1c | 1084 | __ICIALLU = 0; |
Kojto | 111:4336505e4b1c | 1085 | #endif |
Kojto | 111:4336505e4b1c | 1086 | __DSB(); //ensure completion of the invalidation |
Kojto | 111:4336505e4b1c | 1087 | __ISB(); //ensure instruction fetch path sees new I cache state |
Kojto | 111:4336505e4b1c | 1088 | } |
Kojto | 111:4336505e4b1c | 1089 | |
Kojto | 111:4336505e4b1c | 1090 | /** \brief Clean D$ by MVA |
Kojto | 111:4336505e4b1c | 1091 | |
Kojto | 111:4336505e4b1c | 1092 | DCCMVAC. Data cache clean by MVA to PoC |
Kojto | 111:4336505e4b1c | 1093 | */ |
Kojto | 111:4336505e4b1c | 1094 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) { |
Kojto | 111:4336505e4b1c | 1095 | #if 1 |
Kojto | 111:4336505e4b1c | 1096 | __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va)); |
Kojto | 111:4336505e4b1c | 1097 | #else |
Kojto | 111:4336505e4b1c | 1098 | register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); |
Kojto | 111:4336505e4b1c | 1099 | __DCCMVAC = (uint32_t)va; |
Kojto | 111:4336505e4b1c | 1100 | #endif |
Kojto | 111:4336505e4b1c | 1101 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 111:4336505e4b1c | 1102 | } |
Kojto | 111:4336505e4b1c | 1103 | |
Kojto | 111:4336505e4b1c | 1104 | /** \brief Invalidate D$ by MVA |
Kojto | 111:4336505e4b1c | 1105 | |
Kojto | 111:4336505e4b1c | 1106 | DCIMVAC. Data cache invalidate by MVA to PoC |
Kojto | 111:4336505e4b1c | 1107 | */ |
Kojto | 111:4336505e4b1c | 1108 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) { |
Kojto | 111:4336505e4b1c | 1109 | #if 1 |
Kojto | 111:4336505e4b1c | 1110 | __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va)); |
Kojto | 111:4336505e4b1c | 1111 | #else |
Kojto | 111:4336505e4b1c | 1112 | register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); |
Kojto | 111:4336505e4b1c | 1113 | __DCIMVAC = (uint32_t)va; |
Kojto | 111:4336505e4b1c | 1114 | #endif |
Kojto | 111:4336505e4b1c | 1115 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 111:4336505e4b1c | 1116 | } |
Kojto | 111:4336505e4b1c | 1117 | |
Kojto | 111:4336505e4b1c | 1118 | /** \brief Clean and Invalidate D$ by MVA |
Kojto | 111:4336505e4b1c | 1119 | |
Kojto | 111:4336505e4b1c | 1120 | DCCIMVAC. Data cache clean and invalidate by MVA to PoC |
Kojto | 111:4336505e4b1c | 1121 | */ |
Kojto | 111:4336505e4b1c | 1122 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { |
Kojto | 111:4336505e4b1c | 1123 | #if 1 |
Kojto | 111:4336505e4b1c | 1124 | __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va)); |
Kojto | 111:4336505e4b1c | 1125 | #else |
Kojto | 111:4336505e4b1c | 1126 | register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); |
Kojto | 111:4336505e4b1c | 1127 | __DCCIMVAC = (uint32_t)va; |
Kojto | 111:4336505e4b1c | 1128 | #endif |
Kojto | 111:4336505e4b1c | 1129 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 111:4336505e4b1c | 1130 | } |
Kojto | 111:4336505e4b1c | 1131 | |
Kojto | 111:4336505e4b1c | 1132 | /** \brief Clean and Invalidate the entire data or unified cache |
Kojto | 111:4336505e4b1c | 1133 | |
Kojto | 111:4336505e4b1c | 1134 | Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. |
Kojto | 111:4336505e4b1c | 1135 | */ |
Kojto | 111:4336505e4b1c | 1136 | extern void __v7_all_cache(uint32_t op); |
Kojto | 111:4336505e4b1c | 1137 | |
Kojto | 111:4336505e4b1c | 1138 | |
Kojto | 111:4336505e4b1c | 1139 | /** \brief Invalidate the whole D$ |
Kojto | 111:4336505e4b1c | 1140 | |
Kojto | 111:4336505e4b1c | 1141 | DCISW. Invalidate by Set/Way |
Kojto | 111:4336505e4b1c | 1142 | */ |
Kojto | 111:4336505e4b1c | 1143 | |
Kojto | 111:4336505e4b1c | 1144 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) { |
Kojto | 111:4336505e4b1c | 1145 | __v7_all_cache(0); |
Kojto | 111:4336505e4b1c | 1146 | } |
Kojto | 111:4336505e4b1c | 1147 | |
Kojto | 111:4336505e4b1c | 1148 | /** \brief Clean the whole D$ |
Kojto | 111:4336505e4b1c | 1149 | |
Kojto | 111:4336505e4b1c | 1150 | DCCSW. Clean by Set/Way |
Kojto | 111:4336505e4b1c | 1151 | */ |
Kojto | 111:4336505e4b1c | 1152 | |
Kojto | 111:4336505e4b1c | 1153 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) { |
Kojto | 111:4336505e4b1c | 1154 | __v7_all_cache(1); |
Kojto | 111:4336505e4b1c | 1155 | } |
Kojto | 111:4336505e4b1c | 1156 | |
Kojto | 111:4336505e4b1c | 1157 | /** \brief Clean and invalidate the whole D$ |
Kojto | 111:4336505e4b1c | 1158 | |
Kojto | 111:4336505e4b1c | 1159 | DCCISW. Clean and Invalidate by Set/Way |
Kojto | 111:4336505e4b1c | 1160 | */ |
Kojto | 111:4336505e4b1c | 1161 | |
Kojto | 111:4336505e4b1c | 1162 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) { |
Kojto | 111:4336505e4b1c | 1163 | __v7_all_cache(2); |
Kojto | 111:4336505e4b1c | 1164 | } |
Kojto | 111:4336505e4b1c | 1165 | |
Kojto | 111:4336505e4b1c | 1166 | #include "core_ca_mmu.h" |
Kojto | 111:4336505e4b1c | 1167 | |
Kojto | 111:4336505e4b1c | 1168 | #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ |
Kojto | 111:4336505e4b1c | 1169 | |
Kojto | 111:4336505e4b1c | 1170 | #error TASKING Compiler support not implemented for Cortex-A |
Kojto | 111:4336505e4b1c | 1171 | |
Kojto | 111:4336505e4b1c | 1172 | #endif |
Kojto | 111:4336505e4b1c | 1173 | |
Kojto | 111:4336505e4b1c | 1174 | /*@} end of CMSIS_Core_RegAccFunctions */ |
Kojto | 111:4336505e4b1c | 1175 | |
Kojto | 111:4336505e4b1c | 1176 | |
Kojto | 111:4336505e4b1c | 1177 | #endif /* __CORE_CAFUNC_H__ */ |