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TARGET_VK_RZ_A1H/TOOLCHAIN_IAR/cmsis_gcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file cmsis_gcc.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS compiler specific macros, functions, instructions
AnnaBridge 171:3a7713b1edbc 4 * @version V1.0.2
AnnaBridge 171:3a7713b1edbc 5 * @date 09. April 2018
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7 /*
AnnaBridge 171:3a7713b1edbc 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 171:3a7713b1edbc 13 * not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 14 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 171:3a7713b1edbc 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 21 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 22 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 23 */
AnnaBridge 171:3a7713b1edbc 24
AnnaBridge 171:3a7713b1edbc 25 #ifndef __CMSIS_GCC_H
AnnaBridge 171:3a7713b1edbc 26 #define __CMSIS_GCC_H
AnnaBridge 171:3a7713b1edbc 27
AnnaBridge 171:3a7713b1edbc 28 /* ignore some GCC warnings */
AnnaBridge 171:3a7713b1edbc 29 #pragma GCC diagnostic push
AnnaBridge 171:3a7713b1edbc 30 #pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge 171:3a7713b1edbc 31 #pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge 171:3a7713b1edbc 32 #pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 /* Fallback for __has_builtin */
AnnaBridge 171:3a7713b1edbc 35 #ifndef __has_builtin
AnnaBridge 171:3a7713b1edbc 36 #define __has_builtin(x) (0)
AnnaBridge 171:3a7713b1edbc 37 #endif
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 /* CMSIS compiler specific defines */
AnnaBridge 171:3a7713b1edbc 40 #ifndef __ASM
AnnaBridge 171:3a7713b1edbc 41 #define __ASM asm
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43 #ifndef __INLINE
AnnaBridge 171:3a7713b1edbc 44 #define __INLINE inline
AnnaBridge 171:3a7713b1edbc 45 #endif
AnnaBridge 171:3a7713b1edbc 46 #ifndef __FORCEINLINE
AnnaBridge 171:3a7713b1edbc 47 #define __FORCEINLINE __attribute__((always_inline))
AnnaBridge 171:3a7713b1edbc 48 #endif
AnnaBridge 171:3a7713b1edbc 49 #ifndef __STATIC_INLINE
AnnaBridge 171:3a7713b1edbc 50 #define __STATIC_INLINE static inline
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52 #ifndef __STATIC_FORCEINLINE
AnnaBridge 171:3a7713b1edbc 53 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
AnnaBridge 171:3a7713b1edbc 54 #endif
AnnaBridge 171:3a7713b1edbc 55 #ifndef __NO_RETURN
AnnaBridge 171:3a7713b1edbc 56 #define __NO_RETURN __attribute__((__noreturn__))
AnnaBridge 171:3a7713b1edbc 57 #endif
AnnaBridge 171:3a7713b1edbc 58 #ifndef CMSIS_DEPRECATED
AnnaBridge 171:3a7713b1edbc 59 #define CMSIS_DEPRECATED __attribute__((deprecated))
AnnaBridge 171:3a7713b1edbc 60 #endif
AnnaBridge 171:3a7713b1edbc 61 #ifndef __USED
AnnaBridge 171:3a7713b1edbc 62 #define __USED __attribute__((used))
AnnaBridge 171:3a7713b1edbc 63 #endif
AnnaBridge 171:3a7713b1edbc 64 #ifndef __WEAK
AnnaBridge 171:3a7713b1edbc 65 #define __WEAK __attribute__((weak))
AnnaBridge 171:3a7713b1edbc 66 #endif
AnnaBridge 171:3a7713b1edbc 67 #ifndef __PACKED
AnnaBridge 171:3a7713b1edbc 68 #define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge 171:3a7713b1edbc 69 #endif
AnnaBridge 171:3a7713b1edbc 70 #ifndef __PACKED_STRUCT
AnnaBridge 171:3a7713b1edbc 71 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge 171:3a7713b1edbc 72 #endif
AnnaBridge 171:3a7713b1edbc 73 #ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge 171:3a7713b1edbc 74 #pragma GCC diagnostic push
AnnaBridge 171:3a7713b1edbc 75 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 76 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
AnnaBridge 171:3a7713b1edbc 77 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge 171:3a7713b1edbc 78 #pragma GCC diagnostic pop
AnnaBridge 171:3a7713b1edbc 79 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 171:3a7713b1edbc 80 #endif
AnnaBridge 171:3a7713b1edbc 81 #ifndef __UNALIGNED_UINT16_READ
AnnaBridge 171:3a7713b1edbc 82 #pragma GCC diagnostic push
AnnaBridge 171:3a7713b1edbc 83 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 84 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
AnnaBridge 171:3a7713b1edbc 85 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge 171:3a7713b1edbc 86 #pragma GCC diagnostic pop
AnnaBridge 171:3a7713b1edbc 87 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
AnnaBridge 171:3a7713b1edbc 88 #endif
AnnaBridge 171:3a7713b1edbc 89 #ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge 171:3a7713b1edbc 90 #pragma GCC diagnostic push
AnnaBridge 171:3a7713b1edbc 91 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 92 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
AnnaBridge 171:3a7713b1edbc 93 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge 171:3a7713b1edbc 94 #pragma GCC diagnostic pop
AnnaBridge 171:3a7713b1edbc 95 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 171:3a7713b1edbc 96 #endif
AnnaBridge 171:3a7713b1edbc 97 #ifndef __UNALIGNED_UINT32_READ
AnnaBridge 171:3a7713b1edbc 98 #pragma GCC diagnostic push
AnnaBridge 171:3a7713b1edbc 99 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 100 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge 171:3a7713b1edbc 101 #pragma GCC diagnostic pop
AnnaBridge 171:3a7713b1edbc 102 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
AnnaBridge 171:3a7713b1edbc 103 #endif
AnnaBridge 171:3a7713b1edbc 104 #ifndef __ALIGNED
AnnaBridge 171:3a7713b1edbc 105 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 171:3a7713b1edbc 106 #endif
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 /* ########################## Core Instruction Access ######################### */
AnnaBridge 171:3a7713b1edbc 109 /**
AnnaBridge 171:3a7713b1edbc 110 \brief No Operation
AnnaBridge 171:3a7713b1edbc 111 */
AnnaBridge 171:3a7713b1edbc 112 #define __NOP() __ASM volatile ("nop")
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114 /**
AnnaBridge 171:3a7713b1edbc 115 \brief Wait For Interrupt
AnnaBridge 171:3a7713b1edbc 116 */
AnnaBridge 171:3a7713b1edbc 117 #define __WFI() __ASM volatile ("wfi")
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /**
AnnaBridge 171:3a7713b1edbc 120 \brief Wait For Event
AnnaBridge 171:3a7713b1edbc 121 */
AnnaBridge 171:3a7713b1edbc 122 #define __WFE() __ASM volatile ("wfe")
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /**
AnnaBridge 171:3a7713b1edbc 125 \brief Send Event
AnnaBridge 171:3a7713b1edbc 126 */
AnnaBridge 171:3a7713b1edbc 127 #define __SEV() __ASM volatile ("sev")
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 /**
AnnaBridge 171:3a7713b1edbc 130 \brief Instruction Synchronization Barrier
AnnaBridge 171:3a7713b1edbc 131 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge 171:3a7713b1edbc 132 so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge 171:3a7713b1edbc 133 after the instruction has been completed.
AnnaBridge 171:3a7713b1edbc 134 */
AnnaBridge 171:3a7713b1edbc 135 __STATIC_FORCEINLINE void __ISB(void)
AnnaBridge 171:3a7713b1edbc 136 {
AnnaBridge 171:3a7713b1edbc 137 __ASM volatile ("isb 0xF":::"memory");
AnnaBridge 171:3a7713b1edbc 138 }
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 /**
AnnaBridge 171:3a7713b1edbc 142 \brief Data Synchronization Barrier
AnnaBridge 171:3a7713b1edbc 143 \details Acts as a special kind of Data Memory Barrier.
AnnaBridge 171:3a7713b1edbc 144 It completes when all explicit memory accesses before this instruction complete.
AnnaBridge 171:3a7713b1edbc 145 */
AnnaBridge 171:3a7713b1edbc 146 __STATIC_FORCEINLINE void __DSB(void)
AnnaBridge 171:3a7713b1edbc 147 {
AnnaBridge 171:3a7713b1edbc 148 __ASM volatile ("dsb 0xF":::"memory");
AnnaBridge 171:3a7713b1edbc 149 }
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /**
AnnaBridge 171:3a7713b1edbc 152 \brief Data Memory Barrier
AnnaBridge 171:3a7713b1edbc 153 \details Ensures the apparent order of the explicit memory operations before
AnnaBridge 171:3a7713b1edbc 154 and after the instruction, without ensuring their completion.
AnnaBridge 171:3a7713b1edbc 155 */
AnnaBridge 171:3a7713b1edbc 156 __STATIC_FORCEINLINE void __DMB(void)
AnnaBridge 171:3a7713b1edbc 157 {
AnnaBridge 171:3a7713b1edbc 158 __ASM volatile ("dmb 0xF":::"memory");
AnnaBridge 171:3a7713b1edbc 159 }
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /**
AnnaBridge 171:3a7713b1edbc 162 \brief Reverse byte order (32 bit)
AnnaBridge 171:3a7713b1edbc 163 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
AnnaBridge 171:3a7713b1edbc 164 \param [in] value Value to reverse
AnnaBridge 171:3a7713b1edbc 165 \return Reversed value
AnnaBridge 171:3a7713b1edbc 166 */
AnnaBridge 171:3a7713b1edbc 167 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
AnnaBridge 171:3a7713b1edbc 168 {
AnnaBridge 171:3a7713b1edbc 169 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge 171:3a7713b1edbc 170 return __builtin_bswap32(value);
AnnaBridge 171:3a7713b1edbc 171 #else
AnnaBridge 171:3a7713b1edbc 172 uint32_t result;
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 171:3a7713b1edbc 175 return result;
AnnaBridge 171:3a7713b1edbc 176 #endif
AnnaBridge 171:3a7713b1edbc 177 }
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 /**
AnnaBridge 171:3a7713b1edbc 180 \brief Reverse byte order (16 bit)
AnnaBridge 171:3a7713b1edbc 181 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
AnnaBridge 171:3a7713b1edbc 182 \param [in] value Value to reverse
AnnaBridge 171:3a7713b1edbc 183 \return Reversed value
AnnaBridge 171:3a7713b1edbc 184 */
AnnaBridge 171:3a7713b1edbc 185 #ifndef __NO_EMBEDDED_ASM
AnnaBridge 171:3a7713b1edbc 186 __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
AnnaBridge 171:3a7713b1edbc 187 {
AnnaBridge 171:3a7713b1edbc 188 uint32_t result;
AnnaBridge 171:3a7713b1edbc 189 __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
AnnaBridge 171:3a7713b1edbc 190 return result;
AnnaBridge 171:3a7713b1edbc 191 }
AnnaBridge 171:3a7713b1edbc 192 #endif
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 /**
AnnaBridge 171:3a7713b1edbc 195 \brief Reverse byte order (16 bit)
AnnaBridge 171:3a7713b1edbc 196 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
AnnaBridge 171:3a7713b1edbc 197 \param [in] value Value to reverse
AnnaBridge 171:3a7713b1edbc 198 \return Reversed value
AnnaBridge 171:3a7713b1edbc 199 */
AnnaBridge 171:3a7713b1edbc 200 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
AnnaBridge 171:3a7713b1edbc 201 {
AnnaBridge 171:3a7713b1edbc 202 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 171:3a7713b1edbc 203 return (int16_t)__builtin_bswap16(value);
AnnaBridge 171:3a7713b1edbc 204 #else
AnnaBridge 171:3a7713b1edbc 205 int16_t result;
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 171:3a7713b1edbc 208 return result;
AnnaBridge 171:3a7713b1edbc 209 #endif
AnnaBridge 171:3a7713b1edbc 210 }
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /**
AnnaBridge 171:3a7713b1edbc 213 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 171:3a7713b1edbc 214 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 171:3a7713b1edbc 215 \param [in] op1 Value to rotate
AnnaBridge 171:3a7713b1edbc 216 \param [in] op2 Number of Bits to rotate
AnnaBridge 171:3a7713b1edbc 217 \return Rotated value
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 220 {
AnnaBridge 171:3a7713b1edbc 221 op2 %= 32U;
AnnaBridge 171:3a7713b1edbc 222 if (op2 == 0U) {
AnnaBridge 171:3a7713b1edbc 223 return op1;
AnnaBridge 171:3a7713b1edbc 224 }
AnnaBridge 171:3a7713b1edbc 225 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 171:3a7713b1edbc 226 }
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /**
AnnaBridge 171:3a7713b1edbc 230 \brief Breakpoint
AnnaBridge 171:3a7713b1edbc 231 \param [in] value is ignored by the processor.
AnnaBridge 171:3a7713b1edbc 232 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 171:3a7713b1edbc 233 */
AnnaBridge 171:3a7713b1edbc 234 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /**
AnnaBridge 171:3a7713b1edbc 237 \brief Reverse bit order of value
AnnaBridge 171:3a7713b1edbc 238 \details Reverses the bit order of the given value.
AnnaBridge 171:3a7713b1edbc 239 \param [in] value Value to reverse
AnnaBridge 171:3a7713b1edbc 240 \return Reversed value
AnnaBridge 171:3a7713b1edbc 241 */
AnnaBridge 171:3a7713b1edbc 242 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
AnnaBridge 171:3a7713b1edbc 243 {
AnnaBridge 171:3a7713b1edbc 244 uint32_t result;
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 247 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 248 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 171:3a7713b1edbc 249 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge 171:3a7713b1edbc 250 #else
AnnaBridge 171:3a7713b1edbc 251 int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge 171:3a7713b1edbc 254 for (value >>= 1U; value; value >>= 1U)
AnnaBridge 171:3a7713b1edbc 255 {
AnnaBridge 171:3a7713b1edbc 256 result <<= 1U;
AnnaBridge 171:3a7713b1edbc 257 result |= value & 1U;
AnnaBridge 171:3a7713b1edbc 258 s--;
AnnaBridge 171:3a7713b1edbc 259 }
AnnaBridge 171:3a7713b1edbc 260 result <<= s; /* shift when v's highest bits are zero */
AnnaBridge 171:3a7713b1edbc 261 #endif
AnnaBridge 171:3a7713b1edbc 262 return result;
AnnaBridge 171:3a7713b1edbc 263 }
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /**
AnnaBridge 171:3a7713b1edbc 266 \brief Count leading zeros
AnnaBridge 171:3a7713b1edbc 267 \param [in] value Value to count the leading zeros
AnnaBridge 171:3a7713b1edbc 268 \return number of leading zeros in value
AnnaBridge 171:3a7713b1edbc 269 */
AnnaBridge 171:3a7713b1edbc 270 #define __CLZ (uint8_t)__builtin_clz
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 /**
AnnaBridge 171:3a7713b1edbc 273 \brief LDR Exclusive (8 bit)
AnnaBridge 171:3a7713b1edbc 274 \details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge 171:3a7713b1edbc 275 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 276 \return value of type uint8_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 277 */
AnnaBridge 171:3a7713b1edbc 278 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge 171:3a7713b1edbc 279 {
AnnaBridge 171:3a7713b1edbc 280 uint32_t result;
AnnaBridge 171:3a7713b1edbc 281
AnnaBridge 171:3a7713b1edbc 282 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 171:3a7713b1edbc 283 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 171:3a7713b1edbc 284 #else
AnnaBridge 171:3a7713b1edbc 285 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 171:3a7713b1edbc 286 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 171:3a7713b1edbc 287 */
AnnaBridge 171:3a7713b1edbc 288 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge 171:3a7713b1edbc 289 #endif
AnnaBridge 171:3a7713b1edbc 290 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 171:3a7713b1edbc 291 }
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293
AnnaBridge 171:3a7713b1edbc 294 /**
AnnaBridge 171:3a7713b1edbc 295 \brief LDR Exclusive (16 bit)
AnnaBridge 171:3a7713b1edbc 296 \details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 297 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 298 \return value of type uint16_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge 171:3a7713b1edbc 301 {
AnnaBridge 171:3a7713b1edbc 302 uint32_t result;
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 171:3a7713b1edbc 305 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 171:3a7713b1edbc 306 #else
AnnaBridge 171:3a7713b1edbc 307 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 171:3a7713b1edbc 308 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 171:3a7713b1edbc 309 */
AnnaBridge 171:3a7713b1edbc 310 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge 171:3a7713b1edbc 311 #endif
AnnaBridge 171:3a7713b1edbc 312 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 171:3a7713b1edbc 313 }
AnnaBridge 171:3a7713b1edbc 314
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 /**
AnnaBridge 171:3a7713b1edbc 317 \brief LDR Exclusive (32 bit)
AnnaBridge 171:3a7713b1edbc 318 \details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 319 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 320 \return value of type uint32_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 321 */
AnnaBridge 171:3a7713b1edbc 322 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge 171:3a7713b1edbc 323 {
AnnaBridge 171:3a7713b1edbc 324 uint32_t result;
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 171:3a7713b1edbc 327 return(result);
AnnaBridge 171:3a7713b1edbc 328 }
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 /**
AnnaBridge 171:3a7713b1edbc 332 \brief STR Exclusive (8 bit)
AnnaBridge 171:3a7713b1edbc 333 \details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge 171:3a7713b1edbc 334 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 335 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 336 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 337 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 338 */
AnnaBridge 171:3a7713b1edbc 339 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge 171:3a7713b1edbc 340 {
AnnaBridge 171:3a7713b1edbc 341 uint32_t result;
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge 171:3a7713b1edbc 344 return(result);
AnnaBridge 171:3a7713b1edbc 345 }
AnnaBridge 171:3a7713b1edbc 346
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 /**
AnnaBridge 171:3a7713b1edbc 349 \brief STR Exclusive (16 bit)
AnnaBridge 171:3a7713b1edbc 350 \details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 351 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 352 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 353 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 354 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 355 */
AnnaBridge 171:3a7713b1edbc 356 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge 171:3a7713b1edbc 357 {
AnnaBridge 171:3a7713b1edbc 358 uint32_t result;
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge 171:3a7713b1edbc 361 return(result);
AnnaBridge 171:3a7713b1edbc 362 }
AnnaBridge 171:3a7713b1edbc 363
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 /**
AnnaBridge 171:3a7713b1edbc 366 \brief STR Exclusive (32 bit)
AnnaBridge 171:3a7713b1edbc 367 \details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 368 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 369 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 370 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 371 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 372 */
AnnaBridge 171:3a7713b1edbc 373 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge 171:3a7713b1edbc 374 {
AnnaBridge 171:3a7713b1edbc 375 uint32_t result;
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge 171:3a7713b1edbc 378 return(result);
AnnaBridge 171:3a7713b1edbc 379 }
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 /**
AnnaBridge 171:3a7713b1edbc 383 \brief Remove the exclusive lock
AnnaBridge 171:3a7713b1edbc 384 \details Removes the exclusive lock which is created by LDREX.
AnnaBridge 171:3a7713b1edbc 385 */
AnnaBridge 171:3a7713b1edbc 386 __STATIC_FORCEINLINE void __CLREX(void)
AnnaBridge 171:3a7713b1edbc 387 {
AnnaBridge 171:3a7713b1edbc 388 __ASM volatile ("clrex" ::: "memory");
AnnaBridge 171:3a7713b1edbc 389 }
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 /**
AnnaBridge 171:3a7713b1edbc 392 \brief Signed Saturate
AnnaBridge 171:3a7713b1edbc 393 \details Saturates a signed value.
AnnaBridge 171:3a7713b1edbc 394 \param [in] value Value to be saturated
AnnaBridge 171:3a7713b1edbc 395 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 171:3a7713b1edbc 396 \return Saturated value
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398 #define __SSAT(ARG1,ARG2) \
AnnaBridge 171:3a7713b1edbc 399 __extension__ \
AnnaBridge 171:3a7713b1edbc 400 ({ \
AnnaBridge 171:3a7713b1edbc 401 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 171:3a7713b1edbc 402 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 171:3a7713b1edbc 403 __RES; \
AnnaBridge 171:3a7713b1edbc 404 })
AnnaBridge 171:3a7713b1edbc 405
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /**
AnnaBridge 171:3a7713b1edbc 408 \brief Unsigned Saturate
AnnaBridge 171:3a7713b1edbc 409 \details Saturates an unsigned value.
AnnaBridge 171:3a7713b1edbc 410 \param [in] value Value to be saturated
AnnaBridge 171:3a7713b1edbc 411 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 171:3a7713b1edbc 412 \return Saturated value
AnnaBridge 171:3a7713b1edbc 413 */
AnnaBridge 171:3a7713b1edbc 414 #define __USAT(ARG1,ARG2) \
AnnaBridge 171:3a7713b1edbc 415 __extension__ \
AnnaBridge 171:3a7713b1edbc 416 ({ \
AnnaBridge 171:3a7713b1edbc 417 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 171:3a7713b1edbc 418 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 171:3a7713b1edbc 419 __RES; \
AnnaBridge 171:3a7713b1edbc 420 })
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 /* ########################### Core Function Access ########################### */
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 /**
AnnaBridge 171:3a7713b1edbc 425 \brief Enable IRQ Interrupts
AnnaBridge 171:3a7713b1edbc 426 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge 171:3a7713b1edbc 427 Can only be executed in Privileged modes.
AnnaBridge 171:3a7713b1edbc 428 */
AnnaBridge 171:3a7713b1edbc 429 __STATIC_FORCEINLINE void __enable_irq(void)
AnnaBridge 171:3a7713b1edbc 430 {
AnnaBridge 171:3a7713b1edbc 431 __ASM volatile ("cpsie i" : : : "memory");
AnnaBridge 171:3a7713b1edbc 432 }
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434 /**
AnnaBridge 171:3a7713b1edbc 435 \brief Disable IRQ Interrupts
AnnaBridge 171:3a7713b1edbc 436 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 171:3a7713b1edbc 437 Can only be executed in Privileged modes.
AnnaBridge 171:3a7713b1edbc 438 */
AnnaBridge 171:3a7713b1edbc 439 __STATIC_FORCEINLINE void __disable_irq(void)
AnnaBridge 171:3a7713b1edbc 440 {
AnnaBridge 171:3a7713b1edbc 441 __ASM volatile ("cpsid i" : : : "memory");
AnnaBridge 171:3a7713b1edbc 442 }
AnnaBridge 171:3a7713b1edbc 443
AnnaBridge 171:3a7713b1edbc 444 /**
AnnaBridge 171:3a7713b1edbc 445 \brief Get FPSCR
AnnaBridge 171:3a7713b1edbc 446 \details Returns the current value of the Floating Point Status/Control register.
AnnaBridge 171:3a7713b1edbc 447 \return Floating Point Status/Control register value
AnnaBridge 171:3a7713b1edbc 448 */
AnnaBridge 171:3a7713b1edbc 449 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
AnnaBridge 171:3a7713b1edbc 450 {
AnnaBridge 171:3a7713b1edbc 451 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 171:3a7713b1edbc 452 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 171:3a7713b1edbc 453 #if __has_builtin(__builtin_arm_get_fpscr)
AnnaBridge 171:3a7713b1edbc 454 // Re-enable using built-in when GCC has been fixed
AnnaBridge 171:3a7713b1edbc 455 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge 171:3a7713b1edbc 456 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge 171:3a7713b1edbc 457 return __builtin_arm_get_fpscr();
AnnaBridge 171:3a7713b1edbc 458 #else
AnnaBridge 171:3a7713b1edbc 459 uint32_t result;
AnnaBridge 171:3a7713b1edbc 460
AnnaBridge 171:3a7713b1edbc 461 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 462 return(result);
AnnaBridge 171:3a7713b1edbc 463 #endif
AnnaBridge 171:3a7713b1edbc 464 #else
AnnaBridge 171:3a7713b1edbc 465 return(0U);
AnnaBridge 171:3a7713b1edbc 466 #endif
AnnaBridge 171:3a7713b1edbc 467 }
AnnaBridge 171:3a7713b1edbc 468
AnnaBridge 171:3a7713b1edbc 469 /**
AnnaBridge 171:3a7713b1edbc 470 \brief Set FPSCR
AnnaBridge 171:3a7713b1edbc 471 \details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge 171:3a7713b1edbc 472 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 171:3a7713b1edbc 473 */
AnnaBridge 171:3a7713b1edbc 474 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 171:3a7713b1edbc 475 {
AnnaBridge 171:3a7713b1edbc 476 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 171:3a7713b1edbc 477 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 171:3a7713b1edbc 478 #if __has_builtin(__builtin_arm_set_fpscr)
AnnaBridge 171:3a7713b1edbc 479 // Re-enable using built-in when GCC has been fixed
AnnaBridge 171:3a7713b1edbc 480 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge 171:3a7713b1edbc 481 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge 171:3a7713b1edbc 482 __builtin_arm_set_fpscr(fpscr);
AnnaBridge 171:3a7713b1edbc 483 #else
AnnaBridge 171:3a7713b1edbc 484 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
AnnaBridge 171:3a7713b1edbc 485 #endif
AnnaBridge 171:3a7713b1edbc 486 #else
AnnaBridge 171:3a7713b1edbc 487 (void)fpscr;
AnnaBridge 171:3a7713b1edbc 488 #endif
AnnaBridge 171:3a7713b1edbc 489 }
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 /** \brief Get CPSR Register
AnnaBridge 171:3a7713b1edbc 492 \return CPSR Register value
AnnaBridge 171:3a7713b1edbc 493 */
AnnaBridge 171:3a7713b1edbc 494 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
AnnaBridge 171:3a7713b1edbc 495 {
AnnaBridge 171:3a7713b1edbc 496 uint32_t result;
AnnaBridge 171:3a7713b1edbc 497 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 498 return(result);
AnnaBridge 171:3a7713b1edbc 499 }
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 /** \brief Set CPSR Register
AnnaBridge 171:3a7713b1edbc 502 \param [in] cpsr CPSR value to set
AnnaBridge 171:3a7713b1edbc 503 */
AnnaBridge 171:3a7713b1edbc 504 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
AnnaBridge 171:3a7713b1edbc 505 {
AnnaBridge 171:3a7713b1edbc 506 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
AnnaBridge 171:3a7713b1edbc 507 }
AnnaBridge 171:3a7713b1edbc 508
AnnaBridge 171:3a7713b1edbc 509 /** \brief Get Mode
AnnaBridge 171:3a7713b1edbc 510 \return Processor Mode
AnnaBridge 171:3a7713b1edbc 511 */
AnnaBridge 171:3a7713b1edbc 512 __STATIC_FORCEINLINE uint32_t __get_mode(void)
AnnaBridge 171:3a7713b1edbc 513 {
AnnaBridge 171:3a7713b1edbc 514 return (__get_CPSR() & 0x1FU);
AnnaBridge 171:3a7713b1edbc 515 }
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 /** \brief Set Mode
AnnaBridge 171:3a7713b1edbc 518 \param [in] mode Mode value to set
AnnaBridge 171:3a7713b1edbc 519 */
AnnaBridge 171:3a7713b1edbc 520 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
AnnaBridge 171:3a7713b1edbc 521 {
AnnaBridge 171:3a7713b1edbc 522 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
AnnaBridge 171:3a7713b1edbc 523 }
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 /** \brief Get Stack Pointer
AnnaBridge 171:3a7713b1edbc 526 \return Stack Pointer value
AnnaBridge 171:3a7713b1edbc 527 */
AnnaBridge 171:3a7713b1edbc 528 __STATIC_FORCEINLINE uint32_t __get_SP(void)
AnnaBridge 171:3a7713b1edbc 529 {
AnnaBridge 171:3a7713b1edbc 530 uint32_t result;
AnnaBridge 171:3a7713b1edbc 531 __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
AnnaBridge 171:3a7713b1edbc 532 return result;
AnnaBridge 171:3a7713b1edbc 533 }
AnnaBridge 171:3a7713b1edbc 534
AnnaBridge 171:3a7713b1edbc 535 /** \brief Set Stack Pointer
AnnaBridge 171:3a7713b1edbc 536 \param [in] stack Stack Pointer value to set
AnnaBridge 171:3a7713b1edbc 537 */
AnnaBridge 171:3a7713b1edbc 538 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
AnnaBridge 171:3a7713b1edbc 539 {
AnnaBridge 171:3a7713b1edbc 540 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
AnnaBridge 171:3a7713b1edbc 541 }
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543 /** \brief Get USR/SYS Stack Pointer
AnnaBridge 171:3a7713b1edbc 544 \return USR/SYS Stack Pointer value
AnnaBridge 171:3a7713b1edbc 545 */
AnnaBridge 171:3a7713b1edbc 546 __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
AnnaBridge 171:3a7713b1edbc 547 {
AnnaBridge 171:3a7713b1edbc 548 uint32_t cpsr = __get_CPSR();
AnnaBridge 171:3a7713b1edbc 549 uint32_t result;
AnnaBridge 171:3a7713b1edbc 550 __ASM volatile(
AnnaBridge 171:3a7713b1edbc 551 "CPS #0x1F \n"
AnnaBridge 171:3a7713b1edbc 552 "MOV %0, sp " : "=r"(result) : : "memory"
AnnaBridge 171:3a7713b1edbc 553 );
AnnaBridge 171:3a7713b1edbc 554 __set_CPSR(cpsr);
AnnaBridge 171:3a7713b1edbc 555 __ISB();
AnnaBridge 171:3a7713b1edbc 556 return result;
AnnaBridge 171:3a7713b1edbc 557 }
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 /** \brief Set USR/SYS Stack Pointer
AnnaBridge 171:3a7713b1edbc 560 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 171:3a7713b1edbc 561 */
AnnaBridge 171:3a7713b1edbc 562 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
AnnaBridge 171:3a7713b1edbc 563 {
AnnaBridge 171:3a7713b1edbc 564 uint32_t cpsr = __get_CPSR();
AnnaBridge 171:3a7713b1edbc 565 __ASM volatile(
AnnaBridge 171:3a7713b1edbc 566 "CPS #0x1F \n"
AnnaBridge 171:3a7713b1edbc 567 "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
AnnaBridge 171:3a7713b1edbc 568 );
AnnaBridge 171:3a7713b1edbc 569 __set_CPSR(cpsr);
AnnaBridge 171:3a7713b1edbc 570 __ISB();
AnnaBridge 171:3a7713b1edbc 571 }
AnnaBridge 171:3a7713b1edbc 572
AnnaBridge 171:3a7713b1edbc 573 /** \brief Get FPEXC
AnnaBridge 171:3a7713b1edbc 574 \return Floating Point Exception Control register value
AnnaBridge 171:3a7713b1edbc 575 */
AnnaBridge 171:3a7713b1edbc 576 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
AnnaBridge 171:3a7713b1edbc 577 {
AnnaBridge 171:3a7713b1edbc 578 #if (__FPU_PRESENT == 1)
AnnaBridge 171:3a7713b1edbc 579 uint32_t result;
AnnaBridge 171:3a7713b1edbc 580 __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 581 return(result);
AnnaBridge 171:3a7713b1edbc 582 #else
AnnaBridge 171:3a7713b1edbc 583 return(0);
AnnaBridge 171:3a7713b1edbc 584 #endif
AnnaBridge 171:3a7713b1edbc 585 }
AnnaBridge 171:3a7713b1edbc 586
AnnaBridge 171:3a7713b1edbc 587 /** \brief Set FPEXC
AnnaBridge 171:3a7713b1edbc 588 \param [in] fpexc Floating Point Exception Control value to set
AnnaBridge 171:3a7713b1edbc 589 */
AnnaBridge 171:3a7713b1edbc 590 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 171:3a7713b1edbc 591 {
AnnaBridge 171:3a7713b1edbc 592 #if (__FPU_PRESENT == 1)
AnnaBridge 171:3a7713b1edbc 593 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
AnnaBridge 171:3a7713b1edbc 594 #endif
AnnaBridge 171:3a7713b1edbc 595 }
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 /*
AnnaBridge 171:3a7713b1edbc 598 * Include common core functions to access Coprocessor 15 registers
AnnaBridge 171:3a7713b1edbc 599 */
AnnaBridge 171:3a7713b1edbc 600
AnnaBridge 171:3a7713b1edbc 601 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
AnnaBridge 171:3a7713b1edbc 602 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
AnnaBridge 171:3a7713b1edbc 603 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
AnnaBridge 171:3a7713b1edbc 604 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
AnnaBridge 171:3a7713b1edbc 605
AnnaBridge 171:3a7713b1edbc 606 #include "cmsis_cp15.h"
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 /** \brief Enable Floating Point Unit
AnnaBridge 171:3a7713b1edbc 609
AnnaBridge 171:3a7713b1edbc 610 Critical section, called from undef handler, so systick is disabled
AnnaBridge 171:3a7713b1edbc 611 */
AnnaBridge 171:3a7713b1edbc 612 __STATIC_INLINE void __FPU_Enable(void)
AnnaBridge 171:3a7713b1edbc 613 {
AnnaBridge 171:3a7713b1edbc 614 __ASM volatile(
AnnaBridge 171:3a7713b1edbc 615 //Permit access to VFP/NEON, registers by modifying CPACR
AnnaBridge 171:3a7713b1edbc 616 " MRC p15,0,R1,c1,c0,2 \n"
AnnaBridge 171:3a7713b1edbc 617 " ORR R1,R1,#0x00F00000 \n"
AnnaBridge 171:3a7713b1edbc 618 " MCR p15,0,R1,c1,c0,2 \n"
AnnaBridge 171:3a7713b1edbc 619
AnnaBridge 171:3a7713b1edbc 620 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
AnnaBridge 171:3a7713b1edbc 621 " ISB \n"
AnnaBridge 171:3a7713b1edbc 622
AnnaBridge 171:3a7713b1edbc 623 //Enable VFP/NEON
AnnaBridge 171:3a7713b1edbc 624 " VMRS R1,FPEXC \n"
AnnaBridge 171:3a7713b1edbc 625 " ORR R1,R1,#0x40000000 \n"
AnnaBridge 171:3a7713b1edbc 626 " VMSR FPEXC,R1 \n"
AnnaBridge 171:3a7713b1edbc 627
AnnaBridge 171:3a7713b1edbc 628 //Initialise VFP/NEON registers to 0
AnnaBridge 171:3a7713b1edbc 629 " MOV R2,#0 \n"
AnnaBridge 171:3a7713b1edbc 630
AnnaBridge 171:3a7713b1edbc 631 //Initialise D16 registers to 0
AnnaBridge 171:3a7713b1edbc 632 " VMOV D0, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 633 " VMOV D1, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 634 " VMOV D2, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 635 " VMOV D3, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 636 " VMOV D4, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 637 " VMOV D5, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 638 " VMOV D6, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 639 " VMOV D7, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 640 " VMOV D8, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 641 " VMOV D9, R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 642 " VMOV D10,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 643 " VMOV D11,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 644 " VMOV D12,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 645 " VMOV D13,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 646 " VMOV D14,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 647 " VMOV D15,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 #if (defined(__ARM_NEON) && (__ARM_NEON == 1))
AnnaBridge 171:3a7713b1edbc 650 //Initialise D32 registers to 0
AnnaBridge 171:3a7713b1edbc 651 " VMOV D16,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 652 " VMOV D17,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 653 " VMOV D18,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 654 " VMOV D19,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 655 " VMOV D20,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 656 " VMOV D21,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 657 " VMOV D22,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 658 " VMOV D23,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 659 " VMOV D24,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 660 " VMOV D25,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 661 " VMOV D26,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 662 " VMOV D27,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 663 " VMOV D28,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 664 " VMOV D29,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 665 " VMOV D30,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 666 " VMOV D31,R2,R2 \n"
AnnaBridge 171:3a7713b1edbc 667 #endif
AnnaBridge 171:3a7713b1edbc 668
AnnaBridge 171:3a7713b1edbc 669 //Initialise FPSCR to a known state
AnnaBridge 171:3a7713b1edbc 670 " VMRS R2,FPSCR \n"
AnnaBridge 171:3a7713b1edbc 671 " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AnnaBridge 171:3a7713b1edbc 672 " AND R2,R2,R3 \n"
AnnaBridge 171:3a7713b1edbc 673 " VMSR FPSCR,R2 "
AnnaBridge 171:3a7713b1edbc 674 );
AnnaBridge 171:3a7713b1edbc 675 }
AnnaBridge 171:3a7713b1edbc 676
AnnaBridge 171:3a7713b1edbc 677 #pragma GCC diagnostic pop
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 #endif /* __CMSIS_GCC_H */