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TARGET_TB_SENSE_12/TOOLCHAIN_ARM_STD/efr32mg12p_vdac.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h@142:4eea097334d6
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg12p_vdac.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG12P_VDAC register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG12P_VDAC |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG12P_VDAC Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IM uint32_t STATUS; /**< Status Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 46 | __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 47 | __IOM uint32_t CMD; /**< Command Register */ |
| Anna Bridge |
142:4eea097334d6 | 48 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| Anna Bridge |
142:4eea097334d6 | 49 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| Anna Bridge |
142:4eea097334d6 | 50 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 51 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| Anna Bridge |
142:4eea097334d6 | 52 | __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 53 | __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IOM uint32_t COMBDATA; /**< Combined Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 55 | __IOM uint32_t CAL; /**< Calibration Register */ |
| Anna Bridge |
142:4eea097334d6 | 56 | |
| Anna Bridge |
142:4eea097334d6 | 57 | uint32_t RESERVED0[27]; /**< Reserved registers */ |
| Anna Bridge |
142:4eea097334d6 | 58 | VDAC_OPA_TypeDef OPA[3]; /**< OPA Registers */ |
| Anna Bridge |
142:4eea097334d6 | 59 | } VDAC_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 60 | |
| Anna Bridge |
142:4eea097334d6 | 61 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 62 | * @defgroup EFR32MG12P_VDAC_BitFields |
| Anna Bridge |
142:4eea097334d6 | 63 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 64 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 65 | |
| Anna Bridge |
142:4eea097334d6 | 66 | /* Bit fields for VDAC CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 67 | #define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 68 | #define _VDAC_CTRL_MASK 0x937F0771UL /**< Mask for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 69 | #define VDAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */ |
| Anna Bridge |
142:4eea097334d6 | 70 | #define _VDAC_CTRL_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ |
| Anna Bridge |
142:4eea097334d6 | 71 | #define _VDAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ |
| Anna Bridge |
142:4eea097334d6 | 72 | #define _VDAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 73 | #define VDAC_CTRL_DIFF_DEFAULT (_VDAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 74 | #define VDAC_CTRL_SINEMODE (0x1UL << 4) /**< Sine Mode */ |
| Anna Bridge |
142:4eea097334d6 | 75 | #define _VDAC_CTRL_SINEMODE_SHIFT 4 /**< Shift value for VDAC_SINEMODE */ |
| Anna Bridge |
142:4eea097334d6 | 76 | #define _VDAC_CTRL_SINEMODE_MASK 0x10UL /**< Bit mask for VDAC_SINEMODE */ |
| Anna Bridge |
142:4eea097334d6 | 77 | #define _VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define VDAC_CTRL_SINEMODE_DEFAULT (_VDAC_CTRL_SINEMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define VDAC_CTRL_OUTENPRS (0x1UL << 5) /**< PRS Controlled Output Enable */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define _VDAC_CTRL_OUTENPRS_SHIFT 5 /**< Shift value for VDAC_OUTENPRS */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define _VDAC_CTRL_OUTENPRS_MASK 0x20UL /**< Bit mask for VDAC_OUTENPRS */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define _VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define VDAC_CTRL_OUTENPRS_DEFAULT (_VDAC_CTRL_OUTENPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define VDAC_CTRL_CH0PRESCRST (0x1UL << 6) /**< Channel 0 Start Reset Prescaler */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define _VDAC_CTRL_CH0PRESCRST_SHIFT 6 /**< Shift value for VDAC_CH0PRESCRST */ |
| Anna Bridge |
142:4eea097334d6 | 86 | #define _VDAC_CTRL_CH0PRESCRST_MASK 0x40UL /**< Bit mask for VDAC_CH0PRESCRST */ |
| Anna Bridge |
142:4eea097334d6 | 87 | #define _VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 88 | #define VDAC_CTRL_CH0PRESCRST_DEFAULT (_VDAC_CTRL_CH0PRESCRST_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define _VDAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for VDAC_REFSEL */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define _VDAC_CTRL_REFSEL_MASK 0x700UL /**< Bit mask for VDAC_REFSEL */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define _VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define _VDAC_CTRL_REFSEL_1V25LN 0x00000000UL /**< Mode 1V25LN for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define _VDAC_CTRL_REFSEL_2V5LN 0x00000001UL /**< Mode 2V5LN for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define _VDAC_CTRL_REFSEL_1V25 0x00000002UL /**< Mode 1V25 for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define _VDAC_CTRL_REFSEL_2V5 0x00000003UL /**< Mode 2V5 for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define _VDAC_CTRL_REFSEL_VDD 0x00000004UL /**< Mode VDD for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define _VDAC_CTRL_REFSEL_EXT 0x00000006UL /**< Mode EXT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define VDAC_CTRL_REFSEL_DEFAULT (_VDAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define VDAC_CTRL_REFSEL_1V25LN (_VDAC_CTRL_REFSEL_1V25LN << 8) /**< Shifted mode 1V25LN for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 100 | #define VDAC_CTRL_REFSEL_2V5LN (_VDAC_CTRL_REFSEL_2V5LN << 8) /**< Shifted mode 2V5LN for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 101 | #define VDAC_CTRL_REFSEL_1V25 (_VDAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define VDAC_CTRL_REFSEL_2V5 (_VDAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define VDAC_CTRL_REFSEL_VDD (_VDAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define VDAC_CTRL_REFSEL_EXT (_VDAC_CTRL_REFSEL_EXT << 8) /**< Shifted mode EXT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define _VDAC_CTRL_PRESC_SHIFT 16 /**< Shift value for VDAC_PRESC */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define _VDAC_CTRL_PRESC_MASK 0x7F0000UL /**< Bit mask for VDAC_PRESC */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define _VDAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define _VDAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define VDAC_CTRL_PRESC_DEFAULT (_VDAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define VDAC_CTRL_PRESC_NODIVISION (_VDAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define _VDAC_CTRL_REFRESHPERIOD_SHIFT 24 /**< Shift value for VDAC_REFRESHPERIOD */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define _VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL /**< Bit mask for VDAC_REFRESHPERIOD */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define _VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define _VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL /**< Mode 8CYCLES for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define _VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL /**< Mode 16CYCLES for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 116 | #define _VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL /**< Mode 32CYCLES for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 117 | #define _VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL /**< Mode 64CYCLES for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define VDAC_CTRL_REFRESHPERIOD_DEFAULT (_VDAC_CTRL_REFRESHPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define VDAC_CTRL_REFRESHPERIOD_8CYCLES (_VDAC_CTRL_REFRESHPERIOD_8CYCLES << 24) /**< Shifted mode 8CYCLES for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define VDAC_CTRL_REFRESHPERIOD_16CYCLES (_VDAC_CTRL_REFRESHPERIOD_16CYCLES << 24) /**< Shifted mode 16CYCLES for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 121 | #define VDAC_CTRL_REFRESHPERIOD_32CYCLES (_VDAC_CTRL_REFRESHPERIOD_32CYCLES << 24) /**< Shifted mode 32CYCLES for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 122 | #define VDAC_CTRL_REFRESHPERIOD_64CYCLES (_VDAC_CTRL_REFRESHPERIOD_64CYCLES << 24) /**< Shifted mode 64CYCLES for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define VDAC_CTRL_WARMUPMODE (0x1UL << 28) /**< Warm-up Mode */ |
| Anna Bridge |
142:4eea097334d6 | 124 | #define _VDAC_CTRL_WARMUPMODE_SHIFT 28 /**< Shift value for VDAC_WARMUPMODE */ |
| Anna Bridge |
142:4eea097334d6 | 125 | #define _VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL /**< Bit mask for VDAC_WARMUPMODE */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define _VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define _VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define _VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define VDAC_CTRL_WARMUPMODE_DEFAULT (_VDAC_CTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define VDAC_CTRL_WARMUPMODE_NORMAL (_VDAC_CTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY (_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY << 28) /**< Shifted mode KEEPINSTANDBY for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 132 | #define VDAC_CTRL_DACCLKMODE (0x1UL << 31) /**< Clock Mode */ |
| Anna Bridge |
142:4eea097334d6 | 133 | #define _VDAC_CTRL_DACCLKMODE_SHIFT 31 /**< Shift value for VDAC_DACCLKMODE */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define _VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL /**< Bit mask for VDAC_DACCLKMODE */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define _VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define _VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define _VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define VDAC_CTRL_DACCLKMODE_DEFAULT (_VDAC_CTRL_DACCLKMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define VDAC_CTRL_DACCLKMODE_SYNC (_VDAC_CTRL_DACCLKMODE_SYNC << 31) /**< Shifted mode SYNC for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 140 | #define VDAC_CTRL_DACCLKMODE_ASYNC (_VDAC_CTRL_DACCLKMODE_ASYNC << 31) /**< Shifted mode ASYNC for VDAC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 141 | |
| Anna Bridge |
142:4eea097334d6 | 142 | /* Bit fields for VDAC STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define _VDAC_STATUS_RESETVALUE 0x0000000CUL /**< Default value for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define _VDAC_STATUS_MASK 0x7777003FUL /**< Mask for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define VDAC_STATUS_CH0BL (0x1UL << 2) /**< Channel 0 Buffer Level */ |
| Anna Bridge |
142:4eea097334d6 | 156 | #define _VDAC_STATUS_CH0BL_SHIFT 2 /**< Shift value for VDAC_CH0BL */ |
| Anna Bridge |
142:4eea097334d6 | 157 | #define _VDAC_STATUS_CH0BL_MASK 0x4UL /**< Bit mask for VDAC_CH0BL */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define _VDAC_STATUS_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 159 | #define VDAC_STATUS_CH0BL_DEFAULT (_VDAC_STATUS_CH0BL_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define VDAC_STATUS_CH1BL (0x1UL << 3) /**< Channel 1 Buffer Level */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define _VDAC_STATUS_CH1BL_SHIFT 3 /**< Shift value for VDAC_CH1BL */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define _VDAC_STATUS_CH1BL_MASK 0x8UL /**< Bit mask for VDAC_CH1BL */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define _VDAC_STATUS_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define VDAC_STATUS_CH1BL_DEFAULT (_VDAC_STATUS_CH1BL_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warm */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ |
| Anna Bridge |
142:4eea097334d6 | 167 | #define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warm */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 174 | #define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 175 | #define VDAC_STATUS_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define _VDAC_STATUS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 177 | #define _VDAC_STATUS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 178 | #define _VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 179 | #define VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 180 | #define VDAC_STATUS_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output */ |
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142:4eea097334d6 | 181 | #define _VDAC_STATUS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ |
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142:4eea097334d6 | 182 | #define _VDAC_STATUS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ |
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142:4eea097334d6 | 183 | #define _VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 184 | #define VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 185 | #define VDAC_STATUS_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output */ |
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142:4eea097334d6 | 186 | #define _VDAC_STATUS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ |
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142:4eea097334d6 | 187 | #define _VDAC_STATUS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ |
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142:4eea097334d6 | 188 | #define _VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 189 | #define VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 190 | #define VDAC_STATUS_OPA0ENS (0x1UL << 20) /**< OPA0 Enabled Status */ |
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142:4eea097334d6 | 191 | #define _VDAC_STATUS_OPA0ENS_SHIFT 20 /**< Shift value for VDAC_OPA0ENS */ |
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142:4eea097334d6 | 192 | #define _VDAC_STATUS_OPA0ENS_MASK 0x100000UL /**< Bit mask for VDAC_OPA0ENS */ |
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142:4eea097334d6 | 193 | #define _VDAC_STATUS_OPA0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 194 | #define VDAC_STATUS_OPA0ENS_DEFAULT (_VDAC_STATUS_OPA0ENS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 195 | #define VDAC_STATUS_OPA1ENS (0x1UL << 21) /**< OPA1 Enabled Status */ |
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142:4eea097334d6 | 196 | #define _VDAC_STATUS_OPA1ENS_SHIFT 21 /**< Shift value for VDAC_OPA1ENS */ |
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142:4eea097334d6 | 197 | #define _VDAC_STATUS_OPA1ENS_MASK 0x200000UL /**< Bit mask for VDAC_OPA1ENS */ |
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142:4eea097334d6 | 198 | #define _VDAC_STATUS_OPA1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 199 | #define VDAC_STATUS_OPA1ENS_DEFAULT (_VDAC_STATUS_OPA1ENS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 200 | #define VDAC_STATUS_OPA2ENS (0x1UL << 22) /**< OPA2 Enabled Status */ |
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142:4eea097334d6 | 201 | #define _VDAC_STATUS_OPA2ENS_SHIFT 22 /**< Shift value for VDAC_OPA2ENS */ |
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142:4eea097334d6 | 202 | #define _VDAC_STATUS_OPA2ENS_MASK 0x400000UL /**< Bit mask for VDAC_OPA2ENS */ |
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142:4eea097334d6 | 203 | #define _VDAC_STATUS_OPA2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 204 | #define VDAC_STATUS_OPA2ENS_DEFAULT (_VDAC_STATUS_OPA2ENS_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 205 | #define VDAC_STATUS_OPA0WARM (0x1UL << 24) /**< OPA0 Warm Status */ |
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142:4eea097334d6 | 206 | #define _VDAC_STATUS_OPA0WARM_SHIFT 24 /**< Shift value for VDAC_OPA0WARM */ |
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142:4eea097334d6 | 207 | #define _VDAC_STATUS_OPA0WARM_MASK 0x1000000UL /**< Bit mask for VDAC_OPA0WARM */ |
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142:4eea097334d6 | 208 | #define _VDAC_STATUS_OPA0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 209 | #define VDAC_STATUS_OPA0WARM_DEFAULT (_VDAC_STATUS_OPA0WARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 210 | #define VDAC_STATUS_OPA1WARM (0x1UL << 25) /**< OPA1 Warm Status */ |
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142:4eea097334d6 | 211 | #define _VDAC_STATUS_OPA1WARM_SHIFT 25 /**< Shift value for VDAC_OPA1WARM */ |
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142:4eea097334d6 | 212 | #define _VDAC_STATUS_OPA1WARM_MASK 0x2000000UL /**< Bit mask for VDAC_OPA1WARM */ |
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142:4eea097334d6 | 213 | #define _VDAC_STATUS_OPA1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 214 | #define VDAC_STATUS_OPA1WARM_DEFAULT (_VDAC_STATUS_OPA1WARM_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 215 | #define VDAC_STATUS_OPA2WARM (0x1UL << 26) /**< OPA2 Warm Status */ |
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142:4eea097334d6 | 216 | #define _VDAC_STATUS_OPA2WARM_SHIFT 26 /**< Shift value for VDAC_OPA2WARM */ |
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142:4eea097334d6 | 217 | #define _VDAC_STATUS_OPA2WARM_MASK 0x4000000UL /**< Bit mask for VDAC_OPA2WARM */ |
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142:4eea097334d6 | 218 | #define _VDAC_STATUS_OPA2WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 219 | #define VDAC_STATUS_OPA2WARM_DEFAULT (_VDAC_STATUS_OPA2WARM_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 220 | #define VDAC_STATUS_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Status */ |
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142:4eea097334d6 | 221 | #define _VDAC_STATUS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ |
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142:4eea097334d6 | 222 | #define _VDAC_STATUS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ |
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142:4eea097334d6 | 223 | #define _VDAC_STATUS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 224 | #define VDAC_STATUS_OPA0OUTVALID_DEFAULT (_VDAC_STATUS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 225 | #define VDAC_STATUS_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Status */ |
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142:4eea097334d6 | 226 | #define _VDAC_STATUS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ |
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142:4eea097334d6 | 227 | #define _VDAC_STATUS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ |
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142:4eea097334d6 | 228 | #define _VDAC_STATUS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 229 | #define VDAC_STATUS_OPA1OUTVALID_DEFAULT (_VDAC_STATUS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 230 | #define VDAC_STATUS_OPA2OUTVALID (0x1UL << 30) /**< OPA2 Output Valid Status */ |
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142:4eea097334d6 | 231 | #define _VDAC_STATUS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ |
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142:4eea097334d6 | 232 | #define _VDAC_STATUS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ |
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142:4eea097334d6 | 233 | #define _VDAC_STATUS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 234 | #define VDAC_STATUS_OPA2OUTVALID_DEFAULT (_VDAC_STATUS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ |
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142:4eea097334d6 | 235 | |
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142:4eea097334d6 | 236 | /* Bit fields for VDAC CH0CTRL */ |
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142:4eea097334d6 | 237 | #define _VDAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 238 | #define _VDAC_CH0CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 239 | #define VDAC_CH0CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ |
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142:4eea097334d6 | 240 | #define _VDAC_CH0CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ |
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142:4eea097334d6 | 241 | #define _VDAC_CH0CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ |
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142:4eea097334d6 | 242 | #define _VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 243 | #define _VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 244 | #define _VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 245 | #define VDAC_CH0CTRL_CONVMODE_DEFAULT (_VDAC_CH0CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 246 | #define VDAC_CH0CTRL_CONVMODE_CONTINUOUS (_VDAC_CH0CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 247 | #define VDAC_CH0CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 248 | #define _VDAC_CH0CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ |
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142:4eea097334d6 | 249 | #define _VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ |
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142:4eea097334d6 | 250 | #define _VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 251 | #define _VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 252 | #define _VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 253 | #define _VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 254 | #define _VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 255 | #define _VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 256 | #define _VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 257 | #define VDAC_CH0CTRL_TRIGMODE_DEFAULT (_VDAC_CH0CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 258 | #define VDAC_CH0CTRL_TRIGMODE_SW (_VDAC_CH0CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 259 | #define VDAC_CH0CTRL_TRIGMODE_PRS (_VDAC_CH0CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 260 | #define VDAC_CH0CTRL_TRIGMODE_REFRESH (_VDAC_CH0CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 261 | #define VDAC_CH0CTRL_TRIGMODE_SWPRS (_VDAC_CH0CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 262 | #define VDAC_CH0CTRL_TRIGMODE_SWREFRESH (_VDAC_CH0CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 263 | #define VDAC_CH0CTRL_TRIGMODE_LESENSE (_VDAC_CH0CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 264 | #define VDAC_CH0CTRL_PRSASYNC (0x1UL << 8) /**< Channel 0 PRS Asynchronous Enable */ |
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142:4eea097334d6 | 265 | #define _VDAC_CH0CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ |
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142:4eea097334d6 | 266 | #define _VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ |
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142:4eea097334d6 | 267 | #define _VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 268 | #define VDAC_CH0CTRL_PRSASYNC_DEFAULT (_VDAC_CH0CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 269 | #define _VDAC_CH0CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ |
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142:4eea097334d6 | 270 | #define _VDAC_CH0CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ |
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142:4eea097334d6 | 271 | #define _VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 272 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 273 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 274 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 275 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 276 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 277 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 278 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 279 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 280 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 281 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 282 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 283 | #define _VDAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 284 | #define VDAC_CH0CTRL_PRSSEL_DEFAULT (_VDAC_CH0CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 285 | #define VDAC_CH0CTRL_PRSSEL_PRSCH0 (_VDAC_CH0CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 286 | #define VDAC_CH0CTRL_PRSSEL_PRSCH1 (_VDAC_CH0CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 287 | #define VDAC_CH0CTRL_PRSSEL_PRSCH2 (_VDAC_CH0CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 288 | #define VDAC_CH0CTRL_PRSSEL_PRSCH3 (_VDAC_CH0CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 289 | #define VDAC_CH0CTRL_PRSSEL_PRSCH4 (_VDAC_CH0CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 290 | #define VDAC_CH0CTRL_PRSSEL_PRSCH5 (_VDAC_CH0CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 291 | #define VDAC_CH0CTRL_PRSSEL_PRSCH6 (_VDAC_CH0CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 292 | #define VDAC_CH0CTRL_PRSSEL_PRSCH7 (_VDAC_CH0CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 293 | #define VDAC_CH0CTRL_PRSSEL_PRSCH8 (_VDAC_CH0CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 294 | #define VDAC_CH0CTRL_PRSSEL_PRSCH9 (_VDAC_CH0CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 295 | #define VDAC_CH0CTRL_PRSSEL_PRSCH10 (_VDAC_CH0CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 296 | #define VDAC_CH0CTRL_PRSSEL_PRSCH11 (_VDAC_CH0CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH0CTRL */ |
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142:4eea097334d6 | 297 | |
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142:4eea097334d6 | 298 | /* Bit fields for VDAC CH1CTRL */ |
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142:4eea097334d6 | 299 | #define _VDAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 300 | #define _VDAC_CH1CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 301 | #define VDAC_CH1CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ |
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142:4eea097334d6 | 302 | #define _VDAC_CH1CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ |
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142:4eea097334d6 | 303 | #define _VDAC_CH1CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ |
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142:4eea097334d6 | 304 | #define _VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 305 | #define _VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 306 | #define _VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 307 | #define VDAC_CH1CTRL_CONVMODE_DEFAULT (_VDAC_CH1CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 308 | #define VDAC_CH1CTRL_CONVMODE_CONTINUOUS (_VDAC_CH1CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 309 | #define VDAC_CH1CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 310 | #define _VDAC_CH1CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ |
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142:4eea097334d6 | 311 | #define _VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ |
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142:4eea097334d6 | 312 | #define _VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 313 | #define _VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 314 | #define _VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 315 | #define _VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 316 | #define _VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 317 | #define _VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 318 | #define _VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 319 | #define VDAC_CH1CTRL_TRIGMODE_DEFAULT (_VDAC_CH1CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 320 | #define VDAC_CH1CTRL_TRIGMODE_SW (_VDAC_CH1CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 321 | #define VDAC_CH1CTRL_TRIGMODE_PRS (_VDAC_CH1CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 322 | #define VDAC_CH1CTRL_TRIGMODE_REFRESH (_VDAC_CH1CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 323 | #define VDAC_CH1CTRL_TRIGMODE_SWPRS (_VDAC_CH1CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 324 | #define VDAC_CH1CTRL_TRIGMODE_SWREFRESH (_VDAC_CH1CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 325 | #define VDAC_CH1CTRL_TRIGMODE_LESENSE (_VDAC_CH1CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 326 | #define VDAC_CH1CTRL_PRSASYNC (0x1UL << 8) /**< Channel 1 PRS Asynchronous Enable */ |
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142:4eea097334d6 | 327 | #define _VDAC_CH1CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ |
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142:4eea097334d6 | 328 | #define _VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ |
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142:4eea097334d6 | 329 | #define _VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 330 | #define VDAC_CH1CTRL_PRSASYNC_DEFAULT (_VDAC_CH1CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 331 | #define _VDAC_CH1CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ |
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142:4eea097334d6 | 332 | #define _VDAC_CH1CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ |
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142:4eea097334d6 | 333 | #define _VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 334 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 335 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 336 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 337 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 338 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 339 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 340 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 341 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 342 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 343 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 344 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 345 | #define _VDAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 346 | #define VDAC_CH1CTRL_PRSSEL_DEFAULT (_VDAC_CH1CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 347 | #define VDAC_CH1CTRL_PRSSEL_PRSCH0 (_VDAC_CH1CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 348 | #define VDAC_CH1CTRL_PRSSEL_PRSCH1 (_VDAC_CH1CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 349 | #define VDAC_CH1CTRL_PRSSEL_PRSCH2 (_VDAC_CH1CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 350 | #define VDAC_CH1CTRL_PRSSEL_PRSCH3 (_VDAC_CH1CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 351 | #define VDAC_CH1CTRL_PRSSEL_PRSCH4 (_VDAC_CH1CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 352 | #define VDAC_CH1CTRL_PRSSEL_PRSCH5 (_VDAC_CH1CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 353 | #define VDAC_CH1CTRL_PRSSEL_PRSCH6 (_VDAC_CH1CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 354 | #define VDAC_CH1CTRL_PRSSEL_PRSCH7 (_VDAC_CH1CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 355 | #define VDAC_CH1CTRL_PRSSEL_PRSCH8 (_VDAC_CH1CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 356 | #define VDAC_CH1CTRL_PRSSEL_PRSCH9 (_VDAC_CH1CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 357 | #define VDAC_CH1CTRL_PRSSEL_PRSCH10 (_VDAC_CH1CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 358 | #define VDAC_CH1CTRL_PRSSEL_PRSCH11 (_VDAC_CH1CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH1CTRL */ |
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142:4eea097334d6 | 359 | |
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142:4eea097334d6 | 360 | /* Bit fields for VDAC CMD */ |
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142:4eea097334d6 | 361 | #define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ |
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142:4eea097334d6 | 362 | #define _VDAC_CMD_MASK 0x003F000FUL /**< Mask for VDAC_CMD */ |
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142:4eea097334d6 | 363 | #define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ |
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142:4eea097334d6 | 364 | #define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ |
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142:4eea097334d6 | 365 | #define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ |
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142:4eea097334d6 | 366 | #define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 367 | #define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 368 | #define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ |
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142:4eea097334d6 | 369 | #define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ |
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142:4eea097334d6 | 370 | #define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ |
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142:4eea097334d6 | 371 | #define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 372 | #define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 373 | #define VDAC_CMD_CH1EN (0x1UL << 2) /**< DAC Channel 1 Enable */ |
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142:4eea097334d6 | 374 | #define _VDAC_CMD_CH1EN_SHIFT 2 /**< Shift value for VDAC_CH1EN */ |
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142:4eea097334d6 | 375 | #define _VDAC_CMD_CH1EN_MASK 0x4UL /**< Bit mask for VDAC_CH1EN */ |
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142:4eea097334d6 | 376 | #define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 377 | #define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 378 | #define VDAC_CMD_CH1DIS (0x1UL << 3) /**< DAC Channel 1 Disable */ |
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142:4eea097334d6 | 379 | #define _VDAC_CMD_CH1DIS_SHIFT 3 /**< Shift value for VDAC_CH1DIS */ |
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142:4eea097334d6 | 380 | #define _VDAC_CMD_CH1DIS_MASK 0x8UL /**< Bit mask for VDAC_CH1DIS */ |
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142:4eea097334d6 | 381 | #define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 382 | #define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 383 | #define VDAC_CMD_OPA0EN (0x1UL << 16) /**< OPA0 Enable */ |
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142:4eea097334d6 | 384 | #define _VDAC_CMD_OPA0EN_SHIFT 16 /**< Shift value for VDAC_OPA0EN */ |
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142:4eea097334d6 | 385 | #define _VDAC_CMD_OPA0EN_MASK 0x10000UL /**< Bit mask for VDAC_OPA0EN */ |
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142:4eea097334d6 | 386 | #define _VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 387 | #define VDAC_CMD_OPA0EN_DEFAULT (_VDAC_CMD_OPA0EN_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 388 | #define VDAC_CMD_OPA0DIS (0x1UL << 17) /**< OPA0 Disable */ |
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142:4eea097334d6 | 389 | #define _VDAC_CMD_OPA0DIS_SHIFT 17 /**< Shift value for VDAC_OPA0DIS */ |
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142:4eea097334d6 | 390 | #define _VDAC_CMD_OPA0DIS_MASK 0x20000UL /**< Bit mask for VDAC_OPA0DIS */ |
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142:4eea097334d6 | 391 | #define _VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 392 | #define VDAC_CMD_OPA0DIS_DEFAULT (_VDAC_CMD_OPA0DIS_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 393 | #define VDAC_CMD_OPA1EN (0x1UL << 18) /**< OPA1 Enable */ |
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142:4eea097334d6 | 394 | #define _VDAC_CMD_OPA1EN_SHIFT 18 /**< Shift value for VDAC_OPA1EN */ |
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142:4eea097334d6 | 395 | #define _VDAC_CMD_OPA1EN_MASK 0x40000UL /**< Bit mask for VDAC_OPA1EN */ |
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142:4eea097334d6 | 396 | #define _VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 397 | #define VDAC_CMD_OPA1EN_DEFAULT (_VDAC_CMD_OPA1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 398 | #define VDAC_CMD_OPA1DIS (0x1UL << 19) /**< OPA1 Disable */ |
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142:4eea097334d6 | 399 | #define _VDAC_CMD_OPA1DIS_SHIFT 19 /**< Shift value for VDAC_OPA1DIS */ |
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142:4eea097334d6 | 400 | #define _VDAC_CMD_OPA1DIS_MASK 0x80000UL /**< Bit mask for VDAC_OPA1DIS */ |
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142:4eea097334d6 | 401 | #define _VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 402 | #define VDAC_CMD_OPA1DIS_DEFAULT (_VDAC_CMD_OPA1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 403 | #define VDAC_CMD_OPA2EN (0x1UL << 20) /**< OPA2 Enable */ |
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142:4eea097334d6 | 404 | #define _VDAC_CMD_OPA2EN_SHIFT 20 /**< Shift value for VDAC_OPA2EN */ |
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142:4eea097334d6 | 405 | #define _VDAC_CMD_OPA2EN_MASK 0x100000UL /**< Bit mask for VDAC_OPA2EN */ |
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142:4eea097334d6 | 406 | #define _VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 407 | #define VDAC_CMD_OPA2EN_DEFAULT (_VDAC_CMD_OPA2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 408 | #define VDAC_CMD_OPA2DIS (0x1UL << 21) /**< OPA2 Disable */ |
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142:4eea097334d6 | 409 | #define _VDAC_CMD_OPA2DIS_SHIFT 21 /**< Shift value for VDAC_OPA2DIS */ |
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142:4eea097334d6 | 410 | #define _VDAC_CMD_OPA2DIS_MASK 0x200000UL /**< Bit mask for VDAC_OPA2DIS */ |
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142:4eea097334d6 | 411 | #define _VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 412 | #define VDAC_CMD_OPA2DIS_DEFAULT (_VDAC_CMD_OPA2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_CMD */ |
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142:4eea097334d6 | 413 | |
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142:4eea097334d6 | 414 | /* Bit fields for VDAC IF */ |
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142:4eea097334d6 | 415 | #define _VDAC_IF_RESETVALUE 0x000000C0UL /**< Default value for VDAC_IF */ |
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142:4eea097334d6 | 416 | #define _VDAC_IF_MASK 0x707780FFUL /**< Mask for VDAC_IF */ |
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142:4eea097334d6 | 417 | #define VDAC_IF_CH0CD (0x1UL << 0) /**< Channel 0 Conversion Done Interrupt Flag */ |
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142:4eea097334d6 | 418 | #define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ |
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142:4eea097334d6 | 419 | #define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ |
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142:4eea097334d6 | 420 | #define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 421 | #define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 422 | #define VDAC_IF_CH1CD (0x1UL << 1) /**< Channel 1 Conversion Done Interrupt Flag */ |
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142:4eea097334d6 | 423 | #define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ |
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142:4eea097334d6 | 424 | #define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ |
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142:4eea097334d6 | 425 | #define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 426 | #define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 427 | #define VDAC_IF_CH0OF (0x1UL << 2) /**< Channel 0 Data Overflow Interrupt Flag */ |
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142:4eea097334d6 | 428 | #define _VDAC_IF_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ |
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142:4eea097334d6 | 429 | #define _VDAC_IF_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ |
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142:4eea097334d6 | 430 | #define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 431 | #define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 432 | #define VDAC_IF_CH1OF (0x1UL << 3) /**< Channel 1 Data Overflow Interrupt Flag */ |
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142:4eea097334d6 | 433 | #define _VDAC_IF_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ |
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142:4eea097334d6 | 434 | #define _VDAC_IF_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ |
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142:4eea097334d6 | 435 | #define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 436 | #define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 437 | #define VDAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */ |
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142:4eea097334d6 | 438 | #define _VDAC_IF_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ |
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142:4eea097334d6 | 439 | #define _VDAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ |
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142:4eea097334d6 | 440 | #define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 441 | #define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 442 | #define VDAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */ |
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142:4eea097334d6 | 443 | #define _VDAC_IF_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ |
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142:4eea097334d6 | 444 | #define _VDAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ |
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142:4eea097334d6 | 445 | #define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 446 | #define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 447 | #define VDAC_IF_CH0BL (0x1UL << 6) /**< Channel 0 Buffer Level Interrupt Flag */ |
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142:4eea097334d6 | 448 | #define _VDAC_IF_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ |
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142:4eea097334d6 | 449 | #define _VDAC_IF_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ |
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142:4eea097334d6 | 450 | #define _VDAC_IF_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 451 | #define VDAC_IF_CH0BL_DEFAULT (_VDAC_IF_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 452 | #define VDAC_IF_CH1BL (0x1UL << 7) /**< Channel 1 Buffer Level Interrupt Flag */ |
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142:4eea097334d6 | 453 | #define _VDAC_IF_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ |
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142:4eea097334d6 | 454 | #define _VDAC_IF_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ |
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142:4eea097334d6 | 455 | #define _VDAC_IF_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 456 | #define VDAC_IF_CH1BL_DEFAULT (_VDAC_IF_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 457 | #define VDAC_IF_EM23ERR (0x1UL << 15) /**< EM2/3 Entry Error Flag */ |
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142:4eea097334d6 | 458 | #define _VDAC_IF_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ |
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142:4eea097334d6 | 459 | #define _VDAC_IF_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ |
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142:4eea097334d6 | 460 | #define _VDAC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 461 | #define VDAC_IF_EM23ERR_DEFAULT (_VDAC_IF_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 462 | #define VDAC_IF_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output Interrupt Flag */ |
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142:4eea097334d6 | 463 | #define _VDAC_IF_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ |
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142:4eea097334d6 | 464 | #define _VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ |
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142:4eea097334d6 | 465 | #define _VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 466 | #define VDAC_IF_OPA0APORTCONFLICT_DEFAULT (_VDAC_IF_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 467 | #define VDAC_IF_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output Interrupt Flag */ |
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142:4eea097334d6 | 468 | #define _VDAC_IF_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ |
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142:4eea097334d6 | 469 | #define _VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ |
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142:4eea097334d6 | 470 | #define _VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 471 | #define VDAC_IF_OPA1APORTCONFLICT_DEFAULT (_VDAC_IF_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 472 | #define VDAC_IF_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 473 | #define _VDAC_IF_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ |
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142:4eea097334d6 | 474 | #define _VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ |
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142:4eea097334d6 | 475 | #define _VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 476 | #define VDAC_IF_OPA2APORTCONFLICT_DEFAULT (_VDAC_IF_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 477 | #define VDAC_IF_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0 PRS Trigger Mode Error Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 478 | #define _VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ |
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142:4eea097334d6 | 479 | #define _VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ |
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142:4eea097334d6 | 480 | #define _VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 481 | #define VDAC_IF_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 482 | #define VDAC_IF_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1 PRS Trigger Mode Error Interrupt Flag */ |
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142:4eea097334d6 | 483 | #define _VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ |
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142:4eea097334d6 | 484 | #define _VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ |
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142:4eea097334d6 | 485 | #define _VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 486 | #define VDAC_IF_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 487 | #define VDAC_IF_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2 PRS Trigger Mode Error Interrupt Flag */ |
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142:4eea097334d6 | 488 | #define _VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ |
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142:4eea097334d6 | 489 | #define _VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ |
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142:4eea097334d6 | 490 | #define _VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 491 | #define VDAC_IF_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 492 | #define VDAC_IF_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Interrupt Flag */ |
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142:4eea097334d6 | 493 | #define _VDAC_IF_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ |
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142:4eea097334d6 | 494 | #define _VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ |
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142:4eea097334d6 | 495 | #define _VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 496 | #define VDAC_IF_OPA0OUTVALID_DEFAULT (_VDAC_IF_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 497 | #define VDAC_IF_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Interrupt Flag */ |
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142:4eea097334d6 | 498 | #define _VDAC_IF_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ |
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142:4eea097334d6 | 499 | #define _VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ |
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142:4eea097334d6 | 500 | #define _VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 501 | #define VDAC_IF_OPA1OUTVALID_DEFAULT (_VDAC_IF_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 502 | #define VDAC_IF_OPA2OUTVALID (0x1UL << 30) /**< OPA3 Output Valid Interrupt Flag */ |
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142:4eea097334d6 | 503 | #define _VDAC_IF_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ |
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142:4eea097334d6 | 504 | #define _VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ |
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142:4eea097334d6 | 505 | #define _VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 506 | #define VDAC_IF_OPA2OUTVALID_DEFAULT (_VDAC_IF_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IF */ |
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142:4eea097334d6 | 507 | |
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142:4eea097334d6 | 508 | /* Bit fields for VDAC IFS */ |
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142:4eea097334d6 | 509 | #define _VDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFS */ |
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142:4eea097334d6 | 510 | #define _VDAC_IFS_MASK 0x7077803FUL /**< Mask for VDAC_IFS */ |
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142:4eea097334d6 | 511 | #define VDAC_IFS_CH0CD (0x1UL << 0) /**< Set CH0CD Interrupt Flag */ |
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142:4eea097334d6 | 512 | #define _VDAC_IFS_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ |
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142:4eea097334d6 | 513 | #define _VDAC_IFS_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ |
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142:4eea097334d6 | 514 | #define _VDAC_IFS_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 515 | #define VDAC_IFS_CH0CD_DEFAULT (_VDAC_IFS_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 516 | #define VDAC_IFS_CH1CD (0x1UL << 1) /**< Set CH1CD Interrupt Flag */ |
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142:4eea097334d6 | 517 | #define _VDAC_IFS_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ |
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142:4eea097334d6 | 518 | #define _VDAC_IFS_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ |
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142:4eea097334d6 | 519 | #define _VDAC_IFS_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 520 | #define VDAC_IFS_CH1CD_DEFAULT (_VDAC_IFS_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 521 | #define VDAC_IFS_CH0OF (0x1UL << 2) /**< Set CH0OF Interrupt Flag */ |
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142:4eea097334d6 | 522 | #define _VDAC_IFS_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ |
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142:4eea097334d6 | 523 | #define _VDAC_IFS_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ |
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142:4eea097334d6 | 524 | #define _VDAC_IFS_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 525 | #define VDAC_IFS_CH0OF_DEFAULT (_VDAC_IFS_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 526 | #define VDAC_IFS_CH1OF (0x1UL << 3) /**< Set CH1OF Interrupt Flag */ |
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142:4eea097334d6 | 527 | #define _VDAC_IFS_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ |
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142:4eea097334d6 | 528 | #define _VDAC_IFS_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ |
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142:4eea097334d6 | 529 | #define _VDAC_IFS_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 530 | #define VDAC_IFS_CH1OF_DEFAULT (_VDAC_IFS_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 531 | #define VDAC_IFS_CH0UF (0x1UL << 4) /**< Set CH0UF Interrupt Flag */ |
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142:4eea097334d6 | 532 | #define _VDAC_IFS_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ |
| Anna Bridge |
142:4eea097334d6 | 533 | #define _VDAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ |
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142:4eea097334d6 | 534 | #define _VDAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 535 | #define VDAC_IFS_CH0UF_DEFAULT (_VDAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 536 | #define VDAC_IFS_CH1UF (0x1UL << 5) /**< Set CH1UF Interrupt Flag */ |
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142:4eea097334d6 | 537 | #define _VDAC_IFS_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ |
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142:4eea097334d6 | 538 | #define _VDAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ |
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142:4eea097334d6 | 539 | #define _VDAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 540 | #define VDAC_IFS_CH1UF_DEFAULT (_VDAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 541 | #define VDAC_IFS_EM23ERR (0x1UL << 15) /**< Set EM23ERR Interrupt Flag */ |
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142:4eea097334d6 | 542 | #define _VDAC_IFS_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ |
| Anna Bridge |
142:4eea097334d6 | 543 | #define _VDAC_IFS_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ |
| Anna Bridge |
142:4eea097334d6 | 544 | #define _VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 545 | #define VDAC_IFS_EM23ERR_DEFAULT (_VDAC_IFS_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 546 | #define VDAC_IFS_OPA0APORTCONFLICT (0x1UL << 16) /**< Set OPA0APORTCONFLICT Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 547 | #define _VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 548 | #define _VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 549 | #define _VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 550 | #define VDAC_IFS_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 551 | #define VDAC_IFS_OPA1APORTCONFLICT (0x1UL << 17) /**< Set OPA1APORTCONFLICT Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 552 | #define _VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 553 | #define _VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 554 | #define _VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 555 | #define VDAC_IFS_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 556 | #define VDAC_IFS_OPA2APORTCONFLICT (0x1UL << 18) /**< Set OPA2APORTCONFLICT Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 557 | #define _VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 558 | #define _VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 559 | #define _VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 560 | #define VDAC_IFS_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 561 | #define VDAC_IFS_OPA0PRSTIMEDERR (0x1UL << 20) /**< Set OPA0PRSTIMEDERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 562 | #define _VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 563 | #define _VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 564 | #define _VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 565 | #define VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 566 | #define VDAC_IFS_OPA1PRSTIMEDERR (0x1UL << 21) /**< Set OPA1PRSTIMEDERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 567 | #define _VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 568 | #define _VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 569 | #define _VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 570 | #define VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 571 | #define VDAC_IFS_OPA2PRSTIMEDERR (0x1UL << 22) /**< Set OPA2PRSTIMEDERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 572 | #define _VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 573 | #define _VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 574 | #define _VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 575 | #define VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 576 | #define VDAC_IFS_OPA0OUTVALID (0x1UL << 28) /**< Set OPA0OUTVALID Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 577 | #define _VDAC_IFS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 578 | #define _VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 579 | #define _VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 580 | #define VDAC_IFS_OPA0OUTVALID_DEFAULT (_VDAC_IFS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 581 | #define VDAC_IFS_OPA1OUTVALID (0x1UL << 29) /**< Set OPA1OUTVALID Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 582 | #define _VDAC_IFS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 583 | #define _VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 584 | #define _VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 585 | #define VDAC_IFS_OPA1OUTVALID_DEFAULT (_VDAC_IFS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 586 | #define VDAC_IFS_OPA2OUTVALID (0x1UL << 30) /**< Set OPA2OUTVALID Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 587 | #define _VDAC_IFS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 588 | #define _VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 589 | #define _VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 590 | #define VDAC_IFS_OPA2OUTVALID_DEFAULT (_VDAC_IFS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFS */ |
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142:4eea097334d6 | 591 | |
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142:4eea097334d6 | 592 | /* Bit fields for VDAC IFC */ |
| Anna Bridge |
142:4eea097334d6 | 593 | #define _VDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 594 | #define _VDAC_IFC_MASK 0x7077803FUL /**< Mask for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 595 | #define VDAC_IFC_CH0CD (0x1UL << 0) /**< Clear CH0CD Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 596 | #define _VDAC_IFC_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ |
| Anna Bridge |
142:4eea097334d6 | 597 | #define _VDAC_IFC_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ |
| Anna Bridge |
142:4eea097334d6 | 598 | #define _VDAC_IFC_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 599 | #define VDAC_IFC_CH0CD_DEFAULT (_VDAC_IFC_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 600 | #define VDAC_IFC_CH1CD (0x1UL << 1) /**< Clear CH1CD Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 601 | #define _VDAC_IFC_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ |
| Anna Bridge |
142:4eea097334d6 | 602 | #define _VDAC_IFC_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ |
| Anna Bridge |
142:4eea097334d6 | 603 | #define _VDAC_IFC_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 604 | #define VDAC_IFC_CH1CD_DEFAULT (_VDAC_IFC_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 605 | #define VDAC_IFC_CH0OF (0x1UL << 2) /**< Clear CH0OF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 606 | #define _VDAC_IFC_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ |
| Anna Bridge |
142:4eea097334d6 | 607 | #define _VDAC_IFC_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ |
| Anna Bridge |
142:4eea097334d6 | 608 | #define _VDAC_IFC_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 609 | #define VDAC_IFC_CH0OF_DEFAULT (_VDAC_IFC_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 610 | #define VDAC_IFC_CH1OF (0x1UL << 3) /**< Clear CH1OF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 611 | #define _VDAC_IFC_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ |
| Anna Bridge |
142:4eea097334d6 | 612 | #define _VDAC_IFC_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ |
| Anna Bridge |
142:4eea097334d6 | 613 | #define _VDAC_IFC_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 614 | #define VDAC_IFC_CH1OF_DEFAULT (_VDAC_IFC_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 615 | #define VDAC_IFC_CH0UF (0x1UL << 4) /**< Clear CH0UF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 616 | #define _VDAC_IFC_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ |
| Anna Bridge |
142:4eea097334d6 | 617 | #define _VDAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ |
| Anna Bridge |
142:4eea097334d6 | 618 | #define _VDAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 619 | #define VDAC_IFC_CH0UF_DEFAULT (_VDAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 620 | #define VDAC_IFC_CH1UF (0x1UL << 5) /**< Clear CH1UF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 621 | #define _VDAC_IFC_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ |
| Anna Bridge |
142:4eea097334d6 | 622 | #define _VDAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ |
| Anna Bridge |
142:4eea097334d6 | 623 | #define _VDAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 624 | #define VDAC_IFC_CH1UF_DEFAULT (_VDAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 625 | #define VDAC_IFC_EM23ERR (0x1UL << 15) /**< Clear EM23ERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 626 | #define _VDAC_IFC_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ |
| Anna Bridge |
142:4eea097334d6 | 627 | #define _VDAC_IFC_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ |
| Anna Bridge |
142:4eea097334d6 | 628 | #define _VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 629 | #define VDAC_IFC_EM23ERR_DEFAULT (_VDAC_IFC_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 630 | #define VDAC_IFC_OPA0APORTCONFLICT (0x1UL << 16) /**< Clear OPA0APORTCONFLICT Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 631 | #define _VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 632 | #define _VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 633 | #define _VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 634 | #define VDAC_IFC_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 635 | #define VDAC_IFC_OPA1APORTCONFLICT (0x1UL << 17) /**< Clear OPA1APORTCONFLICT Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 636 | #define _VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 637 | #define _VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 638 | #define _VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 639 | #define VDAC_IFC_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 640 | #define VDAC_IFC_OPA2APORTCONFLICT (0x1UL << 18) /**< Clear OPA2APORTCONFLICT Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 641 | #define _VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 642 | #define _VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 643 | #define _VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 644 | #define VDAC_IFC_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 645 | #define VDAC_IFC_OPA0PRSTIMEDERR (0x1UL << 20) /**< Clear OPA0PRSTIMEDERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 646 | #define _VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 647 | #define _VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 648 | #define _VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 649 | #define VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 650 | #define VDAC_IFC_OPA1PRSTIMEDERR (0x1UL << 21) /**< Clear OPA1PRSTIMEDERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 651 | #define _VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 652 | #define _VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 653 | #define _VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 654 | #define VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 655 | #define VDAC_IFC_OPA2PRSTIMEDERR (0x1UL << 22) /**< Clear OPA2PRSTIMEDERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 656 | #define _VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 657 | #define _VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 658 | #define _VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 659 | #define VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 660 | #define VDAC_IFC_OPA0OUTVALID (0x1UL << 28) /**< Clear OPA0OUTVALID Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 661 | #define _VDAC_IFC_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 662 | #define _VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 663 | #define _VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 664 | #define VDAC_IFC_OPA0OUTVALID_DEFAULT (_VDAC_IFC_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 665 | #define VDAC_IFC_OPA1OUTVALID (0x1UL << 29) /**< Clear OPA1OUTVALID Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 666 | #define _VDAC_IFC_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 667 | #define _VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 668 | #define _VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 669 | #define VDAC_IFC_OPA1OUTVALID_DEFAULT (_VDAC_IFC_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 670 | #define VDAC_IFC_OPA2OUTVALID (0x1UL << 30) /**< Clear OPA2OUTVALID Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 671 | #define _VDAC_IFC_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 672 | #define _VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 673 | #define _VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 674 | #define VDAC_IFC_OPA2OUTVALID_DEFAULT (_VDAC_IFC_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 675 | |
| Anna Bridge |
142:4eea097334d6 | 676 | /* Bit fields for VDAC IEN */ |
| Anna Bridge |
142:4eea097334d6 | 677 | #define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 678 | #define _VDAC_IEN_MASK 0x707780FFUL /**< Mask for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 679 | #define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0CD Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 680 | #define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ |
| Anna Bridge |
142:4eea097334d6 | 681 | #define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ |
| Anna Bridge |
142:4eea097334d6 | 682 | #define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 683 | #define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 684 | #define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1CD Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 685 | #define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ |
| Anna Bridge |
142:4eea097334d6 | 686 | #define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ |
| Anna Bridge |
142:4eea097334d6 | 687 | #define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 688 | #define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 689 | #define VDAC_IEN_CH0OF (0x1UL << 2) /**< CH0OF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 690 | #define _VDAC_IEN_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ |
| Anna Bridge |
142:4eea097334d6 | 691 | #define _VDAC_IEN_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ |
| Anna Bridge |
142:4eea097334d6 | 692 | #define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 693 | #define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 694 | #define VDAC_IEN_CH1OF (0x1UL << 3) /**< CH1OF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 695 | #define _VDAC_IEN_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ |
| Anna Bridge |
142:4eea097334d6 | 696 | #define _VDAC_IEN_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ |
| Anna Bridge |
142:4eea097334d6 | 697 | #define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 698 | #define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 699 | #define VDAC_IEN_CH0UF (0x1UL << 4) /**< CH0UF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 700 | #define _VDAC_IEN_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ |
| Anna Bridge |
142:4eea097334d6 | 701 | #define _VDAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ |
| Anna Bridge |
142:4eea097334d6 | 702 | #define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 703 | #define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 704 | #define VDAC_IEN_CH1UF (0x1UL << 5) /**< CH1UF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 705 | #define _VDAC_IEN_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ |
| Anna Bridge |
142:4eea097334d6 | 706 | #define _VDAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ |
| Anna Bridge |
142:4eea097334d6 | 707 | #define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 708 | #define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 709 | #define VDAC_IEN_CH0BL (0x1UL << 6) /**< CH0BL Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 710 | #define _VDAC_IEN_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ |
| Anna Bridge |
142:4eea097334d6 | 711 | #define _VDAC_IEN_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ |
| Anna Bridge |
142:4eea097334d6 | 712 | #define _VDAC_IEN_CH0BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 713 | #define VDAC_IEN_CH0BL_DEFAULT (_VDAC_IEN_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 714 | #define VDAC_IEN_CH1BL (0x1UL << 7) /**< CH1BL Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 715 | #define _VDAC_IEN_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ |
| Anna Bridge |
142:4eea097334d6 | 716 | #define _VDAC_IEN_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ |
| Anna Bridge |
142:4eea097334d6 | 717 | #define _VDAC_IEN_CH1BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 718 | #define VDAC_IEN_CH1BL_DEFAULT (_VDAC_IEN_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 719 | #define VDAC_IEN_EM23ERR (0x1UL << 15) /**< EM23ERR Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 720 | #define _VDAC_IEN_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ |
| Anna Bridge |
142:4eea097334d6 | 721 | #define _VDAC_IEN_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ |
| Anna Bridge |
142:4eea097334d6 | 722 | #define _VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 723 | #define VDAC_IEN_EM23ERR_DEFAULT (_VDAC_IEN_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 724 | #define VDAC_IEN_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0APORTCONFLICT Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 725 | #define _VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 726 | #define _VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 727 | #define _VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 728 | #define VDAC_IEN_OPA0APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 729 | #define VDAC_IEN_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1APORTCONFLICT Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 730 | #define _VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 731 | #define _VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 732 | #define _VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 733 | #define VDAC_IEN_OPA1APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 734 | #define VDAC_IEN_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2APORTCONFLICT Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 735 | #define _VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 736 | #define _VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 737 | #define _VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 738 | #define VDAC_IEN_OPA2APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 739 | #define VDAC_IEN_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0PRSTIMEDERR Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 740 | #define _VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 741 | #define _VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 742 | #define _VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 743 | #define VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 744 | #define VDAC_IEN_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1PRSTIMEDERR Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 745 | #define _VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 746 | #define _VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 747 | #define _VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 748 | #define VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 749 | #define VDAC_IEN_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2PRSTIMEDERR Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 750 | #define _VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 751 | #define _VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ |
| Anna Bridge |
142:4eea097334d6 | 752 | #define _VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 753 | #define VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 754 | #define VDAC_IEN_OPA0OUTVALID (0x1UL << 28) /**< OPA0OUTVALID Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 755 | #define _VDAC_IEN_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 756 | #define _VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 757 | #define _VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 758 | #define VDAC_IEN_OPA0OUTVALID_DEFAULT (_VDAC_IEN_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 759 | #define VDAC_IEN_OPA1OUTVALID (0x1UL << 29) /**< OPA1OUTVALID Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 760 | #define _VDAC_IEN_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 761 | #define _VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 762 | #define _VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 763 | #define VDAC_IEN_OPA1OUTVALID_DEFAULT (_VDAC_IEN_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 764 | #define VDAC_IEN_OPA2OUTVALID (0x1UL << 30) /**< OPA2OUTVALID Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 765 | #define _VDAC_IEN_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 766 | #define _VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ |
| Anna Bridge |
142:4eea097334d6 | 767 | #define _VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 768 | #define VDAC_IEN_OPA2OUTVALID_DEFAULT (_VDAC_IEN_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 769 | |
| Anna Bridge |
142:4eea097334d6 | 770 | /* Bit fields for VDAC CH0DATA */ |
| Anna Bridge |
142:4eea097334d6 | 771 | #define _VDAC_CH0DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH0DATA */ |
| Anna Bridge |
142:4eea097334d6 | 772 | #define _VDAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH0DATA */ |
| Anna Bridge |
142:4eea097334d6 | 773 | #define _VDAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 774 | #define _VDAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 775 | #define _VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH0DATA */ |
| Anna Bridge |
142:4eea097334d6 | 776 | #define VDAC_CH0DATA_DATA_DEFAULT (_VDAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0DATA */ |
| Anna Bridge |
142:4eea097334d6 | 777 | |
| Anna Bridge |
142:4eea097334d6 | 778 | /* Bit fields for VDAC CH1DATA */ |
| Anna Bridge |
142:4eea097334d6 | 779 | #define _VDAC_CH1DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH1DATA */ |
| Anna Bridge |
142:4eea097334d6 | 780 | #define _VDAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH1DATA */ |
| Anna Bridge |
142:4eea097334d6 | 781 | #define _VDAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 782 | #define _VDAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ |
| Anna Bridge |
142:4eea097334d6 | 783 | #define _VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH1DATA */ |
| Anna Bridge |
142:4eea097334d6 | 784 | #define VDAC_CH1DATA_DATA_DEFAULT (_VDAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1DATA */ |
| Anna Bridge |
142:4eea097334d6 | 785 | |
| Anna Bridge |
142:4eea097334d6 | 786 | /* Bit fields for VDAC COMBDATA */ |
| Anna Bridge |
142:4eea097334d6 | 787 | #define _VDAC_COMBDATA_RESETVALUE 0x08000800UL /**< Default value for VDAC_COMBDATA */ |
| Anna Bridge |
142:4eea097334d6 | 788 | #define _VDAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for VDAC_COMBDATA */ |
| Anna Bridge |
142:4eea097334d6 | 789 | #define _VDAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for VDAC_CH0DATA */ |
| Anna Bridge |
142:4eea097334d6 | 790 | #define _VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for VDAC_CH0DATA */ |
| Anna Bridge |
142:4eea097334d6 | 791 | #define _VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ |
| Anna Bridge |
142:4eea097334d6 | 792 | #define VDAC_COMBDATA_CH0DATA_DEFAULT (_VDAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ |
| Anna Bridge |
142:4eea097334d6 | 793 | #define _VDAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for VDAC_CH1DATA */ |
| Anna Bridge |
142:4eea097334d6 | 794 | #define _VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for VDAC_CH1DATA */ |
| Anna Bridge |
142:4eea097334d6 | 795 | #define _VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ |
| Anna Bridge |
142:4eea097334d6 | 796 | #define VDAC_COMBDATA_CH1DATA_DEFAULT (_VDAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ |
| Anna Bridge |
142:4eea097334d6 | 797 | |
| Anna Bridge |
142:4eea097334d6 | 798 | /* Bit fields for VDAC CAL */ |
| Anna Bridge |
142:4eea097334d6 | 799 | #define _VDAC_CAL_RESETVALUE 0x00082004UL /**< Default value for VDAC_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 800 | #define _VDAC_CAL_MASK 0x000F3F07UL /**< Mask for VDAC_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 801 | #define _VDAC_CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for VDAC_OFFSETTRIM */ |
| Anna Bridge |
142:4eea097334d6 | 802 | #define _VDAC_CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for VDAC_OFFSETTRIM */ |
| Anna Bridge |
142:4eea097334d6 | 803 | #define _VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 804 | #define VDAC_CAL_OFFSETTRIM_DEFAULT (_VDAC_CAL_OFFSETTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 805 | #define _VDAC_CAL_GAINERRTRIM_SHIFT 8 /**< Shift value for VDAC_GAINERRTRIM */ |
| Anna Bridge |
142:4eea097334d6 | 806 | #define _VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL /**< Bit mask for VDAC_GAINERRTRIM */ |
| Anna Bridge |
142:4eea097334d6 | 807 | #define _VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL /**< Mode DEFAULT for VDAC_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 808 | #define VDAC_CAL_GAINERRTRIM_DEFAULT (_VDAC_CAL_GAINERRTRIM_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 809 | #define _VDAC_CAL_GAINERRTRIMCH1_SHIFT 16 /**< Shift value for VDAC_GAINERRTRIMCH1 */ |
| Anna Bridge |
142:4eea097334d6 | 810 | #define _VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL /**< Bit mask for VDAC_GAINERRTRIMCH1 */ |
| Anna Bridge |
142:4eea097334d6 | 811 | #define _VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL /**< Mode DEFAULT for VDAC_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 812 | #define VDAC_CAL_GAINERRTRIMCH1_DEFAULT (_VDAC_CAL_GAINERRTRIMCH1_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 813 | |
| Anna Bridge |
142:4eea097334d6 | 814 | /* Bit fields for VDAC OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 815 | #define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 816 | #define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 817 | #define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 818 | #define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 819 | #define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 820 | #define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 821 | #define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 822 | #define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 823 | #define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 824 | #define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 825 | #define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 826 | #define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 827 | #define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 828 | #define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 829 | #define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 830 | #define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 831 | #define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 832 | #define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ |
| Anna Bridge |
142:4eea097334d6 | 833 | #define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 834 | #define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 835 | #define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 836 | #define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 837 | #define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 838 | #define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 839 | #define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 840 | #define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 841 | #define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 842 | #define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ |
| Anna Bridge |
142:4eea097334d6 | 843 | #define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 844 | #define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 845 | #define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 846 | #define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 847 | #define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ |
| Anna Bridge |
142:4eea097334d6 | 848 | #define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 849 | #define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */ |
| Anna Bridge |
142:4eea097334d6 | 850 | #define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 851 | #define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 852 | #define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ |
| Anna Bridge |
142:4eea097334d6 | 853 | #define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 854 | #define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */ |
| Anna Bridge |
142:4eea097334d6 | 855 | #define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 856 | #define VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ |
| Anna Bridge |
142:4eea097334d6 | 857 | |
| Anna Bridge |
142:4eea097334d6 | 858 | /* Bit fields for VDAC OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 859 | #define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 860 | #define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 861 | #define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 862 | #define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 863 | #define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 864 | #define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 865 | #define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 866 | #define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 867 | #define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 868 | #define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 869 | #define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 870 | #define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 871 | #define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 872 | #define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 873 | #define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 874 | #define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 875 | #define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 876 | #define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 877 | #define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 878 | #define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 879 | #define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 880 | #define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 881 | #define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 882 | #define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 883 | #define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 884 | #define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 885 | #define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 886 | #define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 887 | #define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 888 | #define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 889 | #define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 890 | #define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 891 | #define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 892 | #define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 893 | #define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 894 | #define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 895 | #define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 896 | #define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ |
| Anna Bridge |
142:4eea097334d6 | 897 | #define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 898 | #define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 899 | #define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 900 | #define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ |
| Anna Bridge |
142:4eea097334d6 | 901 | |
| Anna Bridge |
142:4eea097334d6 | 902 | /* Bit fields for VDAC OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 903 | #define _VDAC_OPA_CTRL_RESETVALUE 0x0000000EUL /**< Default value for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 904 | #define _VDAC_OPA_CTRL_MASK 0x00313F1FUL /**< Mask for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 905 | #define _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for VDAC_OPADRIVESTRENGTH */ |
| Anna Bridge |
142:4eea097334d6 | 906 | #define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */ |
| Anna Bridge |
142:4eea097334d6 | 907 | #define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 908 | #define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 909 | #define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx unity gain bandwidth scale. */ |
| Anna Bridge |
142:4eea097334d6 | 910 | #define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */ |
| Anna Bridge |
142:4eea097334d6 | 911 | #define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */ |
| Anna Bridge |
142:4eea097334d6 | 912 | #define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 913 | #define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 914 | #define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable. */ |
| Anna Bridge |
142:4eea097334d6 | 915 | #define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */ |
| Anna Bridge |
142:4eea097334d6 | 916 | #define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */ |
| Anna Bridge |
142:4eea097334d6 | 917 | #define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 918 | #define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 919 | #define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx output driving strength. */ |
| Anna Bridge |
142:4eea097334d6 | 920 | #define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */ |
| Anna Bridge |
142:4eea097334d6 | 921 | #define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */ |
| Anna Bridge |
142:4eea097334d6 | 922 | #define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 923 | #define _VDAC_OPA_CTRL_OUTSCALE_FULL 0x00000000UL /**< Mode FULL for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 924 | #define _VDAC_OPA_CTRL_OUTSCALE_HALF 0x00000001UL /**< Mode HALF for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 925 | #define VDAC_OPA_CTRL_OUTSCALE_DEFAULT (_VDAC_OPA_CTRL_OUTSCALE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 926 | #define VDAC_OPA_CTRL_OUTSCALE_FULL (_VDAC_OPA_CTRL_OUTSCALE_FULL << 4) /**< Shifted mode FULL for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 927 | #define VDAC_OPA_CTRL_OUTSCALE_HALF (_VDAC_OPA_CTRL_OUTSCALE_HALF << 4) /**< Shifted mode HALF for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 928 | #define VDAC_OPA_CTRL_PRSEN (0x1UL << 8) /**< OPAx PRS Trigger Enable */ |
| Anna Bridge |
142:4eea097334d6 | 929 | #define _VDAC_OPA_CTRL_PRSEN_SHIFT 8 /**< Shift value for VDAC_OPAPRSEN */ |
| Anna Bridge |
142:4eea097334d6 | 930 | #define _VDAC_OPA_CTRL_PRSEN_MASK 0x100UL /**< Bit mask for VDAC_OPAPRSEN */ |
| Anna Bridge |
142:4eea097334d6 | 931 | #define _VDAC_OPA_CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 932 | #define VDAC_OPA_CTRL_PRSEN_DEFAULT (_VDAC_OPA_CTRL_PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 933 | #define VDAC_OPA_CTRL_PRSMODE (0x1UL << 9) /**< OPAx PRS Trigger Mode */ |
| Anna Bridge |
142:4eea097334d6 | 934 | #define _VDAC_OPA_CTRL_PRSMODE_SHIFT 9 /**< Shift value for VDAC_OPAPRSMODE */ |
| Anna Bridge |
142:4eea097334d6 | 935 | #define _VDAC_OPA_CTRL_PRSMODE_MASK 0x200UL /**< Bit mask for VDAC_OPAPRSMODE */ |
| Anna Bridge |
142:4eea097334d6 | 936 | #define _VDAC_OPA_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 937 | #define _VDAC_OPA_CTRL_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 938 | #define _VDAC_OPA_CTRL_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 939 | #define VDAC_OPA_CTRL_PRSMODE_DEFAULT (_VDAC_OPA_CTRL_PRSMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 940 | #define VDAC_OPA_CTRL_PRSMODE_PULSED (_VDAC_OPA_CTRL_PRSMODE_PULSED << 9) /**< Shifted mode PULSED for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 941 | #define VDAC_OPA_CTRL_PRSMODE_TIMED (_VDAC_OPA_CTRL_PRSMODE_TIMED << 9) /**< Shifted mode TIMED for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 942 | #define _VDAC_OPA_CTRL_PRSSEL_SHIFT 10 /**< Shift value for VDAC_OPAPRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 943 | #define _VDAC_OPA_CTRL_PRSSEL_MASK 0x3C00UL /**< Bit mask for VDAC_OPAPRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 944 | #define _VDAC_OPA_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 945 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 946 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 947 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 948 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 949 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 950 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 951 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 952 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 953 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 954 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 955 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 956 | #define _VDAC_OPA_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 957 | #define VDAC_OPA_CTRL_PRSSEL_DEFAULT (_VDAC_OPA_CTRL_PRSSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 958 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH0 (_VDAC_OPA_CTRL_PRSSEL_PRSCH0 << 10) /**< Shifted mode PRSCH0 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 959 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH1 (_VDAC_OPA_CTRL_PRSSEL_PRSCH1 << 10) /**< Shifted mode PRSCH1 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 960 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH2 (_VDAC_OPA_CTRL_PRSSEL_PRSCH2 << 10) /**< Shifted mode PRSCH2 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 961 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH3 (_VDAC_OPA_CTRL_PRSSEL_PRSCH3 << 10) /**< Shifted mode PRSCH3 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 962 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH4 (_VDAC_OPA_CTRL_PRSSEL_PRSCH4 << 10) /**< Shifted mode PRSCH4 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 963 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH5 (_VDAC_OPA_CTRL_PRSSEL_PRSCH5 << 10) /**< Shifted mode PRSCH5 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 964 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH6 (_VDAC_OPA_CTRL_PRSSEL_PRSCH6 << 10) /**< Shifted mode PRSCH6 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 965 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH7 (_VDAC_OPA_CTRL_PRSSEL_PRSCH7 << 10) /**< Shifted mode PRSCH7 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 966 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH8 (_VDAC_OPA_CTRL_PRSSEL_PRSCH8 << 10) /**< Shifted mode PRSCH8 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 967 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 968 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 969 | #define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 970 | #define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select. */ |
| Anna Bridge |
142:4eea097334d6 | 971 | #define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */ |
| Anna Bridge |
142:4eea097334d6 | 972 | #define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */ |
| Anna Bridge |
142:4eea097334d6 | 973 | #define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 974 | #define _VDAC_OPA_CTRL_PRSOUTMODE_WARM 0x00000000UL /**< Mode WARM for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 975 | #define _VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID 0x00000001UL /**< Mode OUTVALID for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 976 | #define VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT (_VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 977 | #define VDAC_OPA_CTRL_PRSOUTMODE_WARM (_VDAC_OPA_CTRL_PRSOUTMODE_WARM << 16) /**< Shifted mode WARM for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 978 | #define VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID (_VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID << 16) /**< Shifted mode OUTVALID for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 979 | #define VDAC_OPA_CTRL_APORTXMASTERDIS (0x1UL << 20) /**< APORT Bus Master Disable */ |
| Anna Bridge |
142:4eea097334d6 | 980 | #define _VDAC_OPA_CTRL_APORTXMASTERDIS_SHIFT 20 /**< Shift value for VDAC_OPAAPORTXMASTERDIS */ |
| Anna Bridge |
142:4eea097334d6 | 981 | #define _VDAC_OPA_CTRL_APORTXMASTERDIS_MASK 0x100000UL /**< Bit mask for VDAC_OPAAPORTXMASTERDIS */ |
| Anna Bridge |
142:4eea097334d6 | 982 | #define _VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 983 | #define VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 984 | #define VDAC_OPA_CTRL_APORTYMASTERDIS (0x1UL << 21) /**< APORT Bus Master Disable */ |
| Anna Bridge |
142:4eea097334d6 | 985 | #define _VDAC_OPA_CTRL_APORTYMASTERDIS_SHIFT 21 /**< Shift value for VDAC_OPAAPORTYMASTERDIS */ |
| Anna Bridge |
142:4eea097334d6 | 986 | #define _VDAC_OPA_CTRL_APORTYMASTERDIS_MASK 0x200000UL /**< Bit mask for VDAC_OPAAPORTYMASTERDIS */ |
| Anna Bridge |
142:4eea097334d6 | 987 | #define _VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 988 | #define VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 989 | |
| Anna Bridge |
142:4eea097334d6 | 990 | /* Bit fields for VDAC OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 991 | #define _VDAC_OPA_TIMER_RESETVALUE 0x00010700UL /**< Default value for VDAC_OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 992 | #define _VDAC_OPA_TIMER_MASK 0x03FF7F3FUL /**< Mask for VDAC_OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 993 | #define _VDAC_OPA_TIMER_STARTUPDLY_SHIFT 0 /**< Shift value for VDAC_OPASTARTUPDLY */ |
| Anna Bridge |
142:4eea097334d6 | 994 | #define _VDAC_OPA_TIMER_STARTUPDLY_MASK 0x3FUL /**< Bit mask for VDAC_OPASTARTUPDLY */ |
| Anna Bridge |
142:4eea097334d6 | 995 | #define _VDAC_OPA_TIMER_STARTUPDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 996 | #define VDAC_OPA_TIMER_STARTUPDLY_DEFAULT (_VDAC_OPA_TIMER_STARTUPDLY_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 997 | #define _VDAC_OPA_TIMER_WARMUPTIME_SHIFT 8 /**< Shift value for VDAC_OPAWARMUPTIME */ |
| Anna Bridge |
142:4eea097334d6 | 998 | #define _VDAC_OPA_TIMER_WARMUPTIME_MASK 0x7F00UL /**< Bit mask for VDAC_OPAWARMUPTIME */ |
| Anna Bridge |
142:4eea097334d6 | 999 | #define _VDAC_OPA_TIMER_WARMUPTIME_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 1000 | #define VDAC_OPA_TIMER_WARMUPTIME_DEFAULT (_VDAC_OPA_TIMER_WARMUPTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 1001 | #define _VDAC_OPA_TIMER_SETTLETIME_SHIFT 16 /**< Shift value for VDAC_OPASETTLETIME */ |
| Anna Bridge |
142:4eea097334d6 | 1002 | #define _VDAC_OPA_TIMER_SETTLETIME_MASK 0x3FF0000UL /**< Bit mask for VDAC_OPASETTLETIME */ |
| Anna Bridge |
142:4eea097334d6 | 1003 | #define _VDAC_OPA_TIMER_SETTLETIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 1004 | #define VDAC_OPA_TIMER_SETTLETIME_DEFAULT (_VDAC_OPA_TIMER_SETTLETIME_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ |
| Anna Bridge |
142:4eea097334d6 | 1005 | |
| Anna Bridge |
142:4eea097334d6 | 1006 | /* Bit fields for VDAC OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1007 | #define _VDAC_OPA_MUX_RESETVALUE 0x0016F2F1UL /**< Default value for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1008 | #define _VDAC_OPA_MUX_MASK 0x0717FFFFUL /**< Mask for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1009 | #define _VDAC_OPA_MUX_POSSEL_SHIFT 0 /**< Shift value for VDAC_OPAPOSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 1010 | #define _VDAC_OPA_MUX_POSSEL_MASK 0xFFUL /**< Bit mask for VDAC_OPAPOSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 1011 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1012 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH2 0x00000021UL /**< Mode APORT1XCH2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1013 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH4 0x00000022UL /**< Mode APORT1XCH4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1014 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH6 0x00000023UL /**< Mode APORT1XCH6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1015 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH8 0x00000024UL /**< Mode APORT1XCH8 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1016 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH10 0x00000025UL /**< Mode APORT1XCH10 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1017 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH12 0x00000026UL /**< Mode APORT1XCH12 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1018 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH14 0x00000027UL /**< Mode APORT1XCH14 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1019 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH16 0x00000028UL /**< Mode APORT1XCH16 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1020 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH18 0x00000029UL /**< Mode APORT1XCH18 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1021 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH20 0x0000002AUL /**< Mode APORT1XCH20 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1022 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH22 0x0000002BUL /**< Mode APORT1XCH22 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1023 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH24 0x0000002CUL /**< Mode APORT1XCH24 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1024 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH26 0x0000002DUL /**< Mode APORT1XCH26 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1025 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH28 0x0000002EUL /**< Mode APORT1XCH28 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1026 | #define _VDAC_OPA_MUX_POSSEL_APORT1XCH30 0x0000002FUL /**< Mode APORT1XCH30 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1027 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH1 0x00000040UL /**< Mode APORT2XCH1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1028 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH3 0x00000041UL /**< Mode APORT2XCH3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1029 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH5 0x00000042UL /**< Mode APORT2XCH5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1030 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH7 0x00000043UL /**< Mode APORT2XCH7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1031 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH9 0x00000044UL /**< Mode APORT2XCH9 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1032 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH11 0x00000045UL /**< Mode APORT2XCH11 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1033 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH13 0x00000046UL /**< Mode APORT2XCH13 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1034 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH15 0x00000047UL /**< Mode APORT2XCH15 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1035 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH17 0x00000048UL /**< Mode APORT2XCH17 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1036 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH19 0x00000049UL /**< Mode APORT2XCH19 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1037 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH21 0x0000004AUL /**< Mode APORT2XCH21 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1038 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH23 0x0000004BUL /**< Mode APORT2XCH23 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1039 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH25 0x0000004CUL /**< Mode APORT2XCH25 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1040 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH27 0x0000004DUL /**< Mode APORT2XCH27 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1041 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH29 0x0000004EUL /**< Mode APORT2XCH29 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1042 | #define _VDAC_OPA_MUX_POSSEL_APORT2XCH31 0x0000004FUL /**< Mode APORT2XCH31 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1043 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1044 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH2 0x00000061UL /**< Mode APORT3XCH2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1045 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH4 0x00000062UL /**< Mode APORT3XCH4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1046 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH6 0x00000063UL /**< Mode APORT3XCH6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1047 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH8 0x00000064UL /**< Mode APORT3XCH8 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1048 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH10 0x00000065UL /**< Mode APORT3XCH10 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1049 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH12 0x00000066UL /**< Mode APORT3XCH12 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1050 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH14 0x00000067UL /**< Mode APORT3XCH14 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1051 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH16 0x00000068UL /**< Mode APORT3XCH16 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1052 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH18 0x00000069UL /**< Mode APORT3XCH18 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1053 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH20 0x0000006AUL /**< Mode APORT3XCH20 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1054 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH22 0x0000006BUL /**< Mode APORT3XCH22 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1055 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH24 0x0000006CUL /**< Mode APORT3XCH24 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1056 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH26 0x0000006DUL /**< Mode APORT3XCH26 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1057 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH28 0x0000006EUL /**< Mode APORT3XCH28 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1058 | #define _VDAC_OPA_MUX_POSSEL_APORT3XCH30 0x0000006FUL /**< Mode APORT3XCH30 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1059 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH1 0x00000080UL /**< Mode APORT4XCH1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1060 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH3 0x00000081UL /**< Mode APORT4XCH3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1061 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH5 0x00000082UL /**< Mode APORT4XCH5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1062 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH7 0x00000083UL /**< Mode APORT4XCH7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1063 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH9 0x00000084UL /**< Mode APORT4XCH9 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1064 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH11 0x00000085UL /**< Mode APORT4XCH11 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1065 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH13 0x00000086UL /**< Mode APORT4XCH13 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1066 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH15 0x00000087UL /**< Mode APORT4XCH15 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1067 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH17 0x00000088UL /**< Mode APORT4XCH17 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1068 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH19 0x00000089UL /**< Mode APORT4XCH19 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1069 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH21 0x0000008AUL /**< Mode APORT4XCH21 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1070 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH23 0x0000008BUL /**< Mode APORT4XCH23 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1071 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH25 0x0000008CUL /**< Mode APORT4XCH25 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1072 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH27 0x0000008DUL /**< Mode APORT4XCH27 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1073 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH29 0x0000008EUL /**< Mode APORT4XCH29 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1074 | #define _VDAC_OPA_MUX_POSSEL_APORT4XCH31 0x0000008FUL /**< Mode APORT4XCH31 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1075 | #define _VDAC_OPA_MUX_POSSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1076 | #define _VDAC_OPA_MUX_POSSEL_DEFAULT 0x000000F1UL /**< Mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1077 | #define _VDAC_OPA_MUX_POSSEL_DAC 0x000000F1UL /**< Mode DAC for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1078 | #define _VDAC_OPA_MUX_POSSEL_POSPAD 0x000000F2UL /**< Mode POSPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1079 | #define _VDAC_OPA_MUX_POSSEL_OPANEXT 0x000000F3UL /**< Mode OPANEXT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1080 | #define _VDAC_OPA_MUX_POSSEL_OPATAP 0x000000F4UL /**< Mode OPATAP for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1081 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH0 (_VDAC_OPA_MUX_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1082 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH2 (_VDAC_OPA_MUX_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1083 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH4 (_VDAC_OPA_MUX_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1084 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH6 (_VDAC_OPA_MUX_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1085 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH8 (_VDAC_OPA_MUX_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1086 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH10 (_VDAC_OPA_MUX_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1087 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH12 (_VDAC_OPA_MUX_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1088 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH14 (_VDAC_OPA_MUX_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1089 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH16 (_VDAC_OPA_MUX_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1090 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH18 (_VDAC_OPA_MUX_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1091 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH20 (_VDAC_OPA_MUX_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1092 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH22 (_VDAC_OPA_MUX_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1093 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH24 (_VDAC_OPA_MUX_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1094 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH26 (_VDAC_OPA_MUX_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1095 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH28 (_VDAC_OPA_MUX_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1096 | #define VDAC_OPA_MUX_POSSEL_APORT1XCH30 (_VDAC_OPA_MUX_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1097 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH1 (_VDAC_OPA_MUX_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1098 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH3 (_VDAC_OPA_MUX_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1099 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH5 (_VDAC_OPA_MUX_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1100 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH7 (_VDAC_OPA_MUX_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1101 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH9 (_VDAC_OPA_MUX_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1102 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH11 (_VDAC_OPA_MUX_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1103 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH13 (_VDAC_OPA_MUX_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1104 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH15 (_VDAC_OPA_MUX_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1105 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH17 (_VDAC_OPA_MUX_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1106 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH19 (_VDAC_OPA_MUX_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1107 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH21 (_VDAC_OPA_MUX_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1108 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH23 (_VDAC_OPA_MUX_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1109 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH25 (_VDAC_OPA_MUX_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1110 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH27 (_VDAC_OPA_MUX_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1111 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH29 (_VDAC_OPA_MUX_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1112 | #define VDAC_OPA_MUX_POSSEL_APORT2XCH31 (_VDAC_OPA_MUX_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1113 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH0 (_VDAC_OPA_MUX_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1114 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH2 (_VDAC_OPA_MUX_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1115 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH4 (_VDAC_OPA_MUX_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1116 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH6 (_VDAC_OPA_MUX_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1117 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH8 (_VDAC_OPA_MUX_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1118 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH10 (_VDAC_OPA_MUX_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1119 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH12 (_VDAC_OPA_MUX_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1120 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH14 (_VDAC_OPA_MUX_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1121 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH16 (_VDAC_OPA_MUX_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1122 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH18 (_VDAC_OPA_MUX_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1123 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH20 (_VDAC_OPA_MUX_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1124 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH22 (_VDAC_OPA_MUX_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1125 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH24 (_VDAC_OPA_MUX_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1126 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH26 (_VDAC_OPA_MUX_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1127 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH28 (_VDAC_OPA_MUX_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1128 | #define VDAC_OPA_MUX_POSSEL_APORT3XCH30 (_VDAC_OPA_MUX_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1129 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH1 (_VDAC_OPA_MUX_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1130 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH3 (_VDAC_OPA_MUX_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1131 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH5 (_VDAC_OPA_MUX_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1132 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH7 (_VDAC_OPA_MUX_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1133 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH9 (_VDAC_OPA_MUX_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1134 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH11 (_VDAC_OPA_MUX_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1135 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH13 (_VDAC_OPA_MUX_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1136 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH15 (_VDAC_OPA_MUX_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1137 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH17 (_VDAC_OPA_MUX_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1138 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH19 (_VDAC_OPA_MUX_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1139 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH21 (_VDAC_OPA_MUX_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1140 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH23 (_VDAC_OPA_MUX_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1141 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH25 (_VDAC_OPA_MUX_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1142 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH27 (_VDAC_OPA_MUX_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1143 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH29 (_VDAC_OPA_MUX_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1144 | #define VDAC_OPA_MUX_POSSEL_APORT4XCH31 (_VDAC_OPA_MUX_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1145 | #define VDAC_OPA_MUX_POSSEL_DISABLE (_VDAC_OPA_MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1146 | #define VDAC_OPA_MUX_POSSEL_DEFAULT (_VDAC_OPA_MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1147 | #define VDAC_OPA_MUX_POSSEL_DAC (_VDAC_OPA_MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1148 | #define VDAC_OPA_MUX_POSSEL_POSPAD (_VDAC_OPA_MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1149 | #define VDAC_OPA_MUX_POSSEL_OPANEXT (_VDAC_OPA_MUX_POSSEL_OPANEXT << 0) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1150 | #define VDAC_OPA_MUX_POSSEL_OPATAP (_VDAC_OPA_MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1151 | #define _VDAC_OPA_MUX_NEGSEL_SHIFT 8 /**< Shift value for VDAC_OPANEGSEL */ |
| Anna Bridge |
142:4eea097334d6 | 1152 | #define _VDAC_OPA_MUX_NEGSEL_MASK 0xFF00UL /**< Bit mask for VDAC_OPANEGSEL */ |
| Anna Bridge |
142:4eea097334d6 | 1153 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1154 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1155 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1156 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1157 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1158 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1159 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1160 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1161 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1162 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1163 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1164 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1165 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1166 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1167 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1168 | #define _VDAC_OPA_MUX_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1169 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1170 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1171 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1172 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1173 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1174 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1175 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1176 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1177 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1178 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1179 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1180 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1181 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1182 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1183 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1184 | #define _VDAC_OPA_MUX_NEGSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1185 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1186 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1187 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1188 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1189 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1190 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1191 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1192 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1193 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1194 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1195 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1196 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1197 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1198 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1199 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1200 | #define _VDAC_OPA_MUX_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1201 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1202 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1203 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1204 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1205 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1206 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1207 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1208 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1209 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1210 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1211 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1212 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1213 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1214 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1215 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1216 | #define _VDAC_OPA_MUX_NEGSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1217 | #define _VDAC_OPA_MUX_NEGSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1218 | #define _VDAC_OPA_MUX_NEGSEL_UG 0x000000F1UL /**< Mode UG for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1219 | #define _VDAC_OPA_MUX_NEGSEL_DEFAULT 0x000000F2UL /**< Mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1220 | #define _VDAC_OPA_MUX_NEGSEL_OPATAP 0x000000F2UL /**< Mode OPATAP for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1221 | #define _VDAC_OPA_MUX_NEGSEL_NEGPAD 0x000000F3UL /**< Mode NEGPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1222 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1223 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1224 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1225 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1226 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1227 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1228 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1229 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1230 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1231 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1232 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1233 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1234 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1235 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1236 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1237 | #define VDAC_OPA_MUX_NEGSEL_APORT1YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1238 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1239 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1240 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1241 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1242 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1243 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1244 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1245 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1246 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1247 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1248 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1249 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1250 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1251 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1252 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1253 | #define VDAC_OPA_MUX_NEGSEL_APORT2YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1254 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1255 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1256 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1257 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1258 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1259 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1260 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1261 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1262 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1263 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1264 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1265 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1266 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1267 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1268 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1269 | #define VDAC_OPA_MUX_NEGSEL_APORT3YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1270 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1271 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1272 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1273 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1274 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1275 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1276 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1277 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1278 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1279 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1280 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1281 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1282 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1283 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1284 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1285 | #define VDAC_OPA_MUX_NEGSEL_APORT4YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1286 | #define VDAC_OPA_MUX_NEGSEL_DISABLE (_VDAC_OPA_MUX_NEGSEL_DISABLE << 8) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1287 | #define VDAC_OPA_MUX_NEGSEL_UG (_VDAC_OPA_MUX_NEGSEL_UG << 8) /**< Shifted mode UG for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1288 | #define VDAC_OPA_MUX_NEGSEL_DEFAULT (_VDAC_OPA_MUX_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1289 | #define VDAC_OPA_MUX_NEGSEL_OPATAP (_VDAC_OPA_MUX_NEGSEL_OPATAP << 8) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1290 | #define VDAC_OPA_MUX_NEGSEL_NEGPAD (_VDAC_OPA_MUX_NEGSEL_NEGPAD << 8) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1291 | #define _VDAC_OPA_MUX_RESINMUX_SHIFT 16 /**< Shift value for VDAC_OPARESINMUX */ |
| Anna Bridge |
142:4eea097334d6 | 1292 | #define _VDAC_OPA_MUX_RESINMUX_MASK 0x70000UL /**< Bit mask for VDAC_OPARESINMUX */ |
| Anna Bridge |
142:4eea097334d6 | 1293 | #define _VDAC_OPA_MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1294 | #define _VDAC_OPA_MUX_RESINMUX_OPANEXT 0x00000001UL /**< Mode OPANEXT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1295 | #define _VDAC_OPA_MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1296 | #define _VDAC_OPA_MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1297 | #define _VDAC_OPA_MUX_RESINMUX_COMPAD 0x00000004UL /**< Mode COMPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1298 | #define _VDAC_OPA_MUX_RESINMUX_CENTER 0x00000005UL /**< Mode CENTER for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1299 | #define _VDAC_OPA_MUX_RESINMUX_DEFAULT 0x00000006UL /**< Mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1300 | #define _VDAC_OPA_MUX_RESINMUX_VSS 0x00000006UL /**< Mode VSS for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1301 | #define VDAC_OPA_MUX_RESINMUX_DISABLE (_VDAC_OPA_MUX_RESINMUX_DISABLE << 16) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1302 | #define VDAC_OPA_MUX_RESINMUX_OPANEXT (_VDAC_OPA_MUX_RESINMUX_OPANEXT << 16) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1303 | #define VDAC_OPA_MUX_RESINMUX_NEGPAD (_VDAC_OPA_MUX_RESINMUX_NEGPAD << 16) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1304 | #define VDAC_OPA_MUX_RESINMUX_POSPAD (_VDAC_OPA_MUX_RESINMUX_POSPAD << 16) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1305 | #define VDAC_OPA_MUX_RESINMUX_COMPAD (_VDAC_OPA_MUX_RESINMUX_COMPAD << 16) /**< Shifted mode COMPAD for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1306 | #define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1307 | #define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1308 | #define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1309 | #define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x gain resistor ladder. */ |
| Anna Bridge |
142:4eea097334d6 | 1310 | #define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */ |
| Anna Bridge |
142:4eea097334d6 | 1311 | #define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */ |
| Anna Bridge |
142:4eea097334d6 | 1312 | #define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1313 | #define VDAC_OPA_MUX_GAIN3X_DEFAULT (_VDAC_OPA_MUX_GAIN3X_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1314 | #define _VDAC_OPA_MUX_RESSEL_SHIFT 24 /**< Shift value for VDAC_OPARESSEL */ |
| Anna Bridge |
142:4eea097334d6 | 1315 | #define _VDAC_OPA_MUX_RESSEL_MASK 0x7000000UL /**< Bit mask for VDAC_OPARESSEL */ |
| Anna Bridge |
142:4eea097334d6 | 1316 | #define _VDAC_OPA_MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1317 | #define _VDAC_OPA_MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1318 | #define _VDAC_OPA_MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1319 | #define _VDAC_OPA_MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1320 | #define _VDAC_OPA_MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1321 | #define _VDAC_OPA_MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1322 | #define _VDAC_OPA_MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1323 | #define _VDAC_OPA_MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1324 | #define _VDAC_OPA_MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1325 | #define VDAC_OPA_MUX_RESSEL_DEFAULT (_VDAC_OPA_MUX_RESSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1326 | #define VDAC_OPA_MUX_RESSEL_RES0 (_VDAC_OPA_MUX_RESSEL_RES0 << 24) /**< Shifted mode RES0 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1327 | #define VDAC_OPA_MUX_RESSEL_RES1 (_VDAC_OPA_MUX_RESSEL_RES1 << 24) /**< Shifted mode RES1 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1328 | #define VDAC_OPA_MUX_RESSEL_RES2 (_VDAC_OPA_MUX_RESSEL_RES2 << 24) /**< Shifted mode RES2 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1329 | #define VDAC_OPA_MUX_RESSEL_RES3 (_VDAC_OPA_MUX_RESSEL_RES3 << 24) /**< Shifted mode RES3 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1330 | #define VDAC_OPA_MUX_RESSEL_RES4 (_VDAC_OPA_MUX_RESSEL_RES4 << 24) /**< Shifted mode RES4 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1331 | #define VDAC_OPA_MUX_RESSEL_RES5 (_VDAC_OPA_MUX_RESSEL_RES5 << 24) /**< Shifted mode RES5 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1332 | #define VDAC_OPA_MUX_RESSEL_RES6 (_VDAC_OPA_MUX_RESSEL_RES6 << 24) /**< Shifted mode RES6 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1333 | #define VDAC_OPA_MUX_RESSEL_RES7 (_VDAC_OPA_MUX_RESSEL_RES7 << 24) /**< Shifted mode RES7 for VDAC_OPA_MUX */ |
| Anna Bridge |
142:4eea097334d6 | 1334 | |
| Anna Bridge |
142:4eea097334d6 | 1335 | /* Bit fields for VDAC OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1336 | #define _VDAC_OPA_OUT_RESETVALUE 0x00000001UL /**< Default value for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1337 | #define _VDAC_OPA_OUT_MASK 0x00FF01FFUL /**< Mask for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1338 | #define VDAC_OPA_OUT_MAINOUTEN (0x1UL << 0) /**< OPAx Main Output Enable */ |
| Anna Bridge |
142:4eea097334d6 | 1339 | #define _VDAC_OPA_OUT_MAINOUTEN_SHIFT 0 /**< Shift value for VDAC_OPAMAINOUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 1340 | #define _VDAC_OPA_OUT_MAINOUTEN_MASK 0x1UL /**< Bit mask for VDAC_OPAMAINOUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 1341 | #define _VDAC_OPA_OUT_MAINOUTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1342 | #define VDAC_OPA_OUT_MAINOUTEN_DEFAULT (_VDAC_OPA_OUT_MAINOUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1343 | #define VDAC_OPA_OUT_ALTOUTEN (0x1UL << 1) /**< OPAx Alternative Output Enable */ |
| Anna Bridge |
142:4eea097334d6 | 1344 | #define _VDAC_OPA_OUT_ALTOUTEN_SHIFT 1 /**< Shift value for VDAC_OPAALTOUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 1345 | #define _VDAC_OPA_OUT_ALTOUTEN_MASK 0x2UL /**< Bit mask for VDAC_OPAALTOUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 1346 | #define _VDAC_OPA_OUT_ALTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1347 | #define VDAC_OPA_OUT_ALTOUTEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1348 | #define VDAC_OPA_OUT_APORTOUTEN (0x1UL << 2) /**< OPAx Aport Output Enable */ |
| Anna Bridge |
142:4eea097334d6 | 1349 | #define _VDAC_OPA_OUT_APORTOUTEN_SHIFT 2 /**< Shift value for VDAC_OPAAPORTOUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 1350 | #define _VDAC_OPA_OUT_APORTOUTEN_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORTOUTEN */ |
| Anna Bridge |
142:4eea097334d6 | 1351 | #define _VDAC_OPA_OUT_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1352 | #define VDAC_OPA_OUT_APORTOUTEN_DEFAULT (_VDAC_OPA_OUT_APORTOUTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1353 | #define VDAC_OPA_OUT_SHORT (0x1UL << 3) /**< OPAx Main and Alternative Output Short */ |
| Anna Bridge |
142:4eea097334d6 | 1354 | #define _VDAC_OPA_OUT_SHORT_SHIFT 3 /**< Shift value for VDAC_OPASHORT */ |
| Anna Bridge |
142:4eea097334d6 | 1355 | #define _VDAC_OPA_OUT_SHORT_MASK 0x8UL /**< Bit mask for VDAC_OPASHORT */ |
| Anna Bridge |
142:4eea097334d6 | 1356 | #define _VDAC_OPA_OUT_SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1357 | #define VDAC_OPA_OUT_SHORT_DEFAULT (_VDAC_OPA_OUT_SHORT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1358 | #define _VDAC_OPA_OUT_ALTOUTPADEN_SHIFT 4 /**< Shift value for VDAC_OPAALTOUTPADEN */ |
| Anna Bridge |
142:4eea097334d6 | 1359 | #define _VDAC_OPA_OUT_ALTOUTPADEN_MASK 0x1F0UL /**< Bit mask for VDAC_OPAALTOUTPADEN */ |
| Anna Bridge |
142:4eea097334d6 | 1360 | #define _VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1361 | #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT0 0x00000001UL /**< Mode OUT0 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1362 | #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT1 0x00000002UL /**< Mode OUT1 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1363 | #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT2 0x00000004UL /**< Mode OUT2 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1364 | #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT3 0x00000008UL /**< Mode OUT3 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1365 | #define _VDAC_OPA_OUT_ALTOUTPADEN_OUT4 0x00000010UL /**< Mode OUT4 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1366 | #define VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1367 | #define VDAC_OPA_OUT_ALTOUTPADEN_OUT0 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT0 << 4) /**< Shifted mode OUT0 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1368 | #define VDAC_OPA_OUT_ALTOUTPADEN_OUT1 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT1 << 4) /**< Shifted mode OUT1 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1369 | #define VDAC_OPA_OUT_ALTOUTPADEN_OUT2 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT2 << 4) /**< Shifted mode OUT2 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1370 | #define VDAC_OPA_OUT_ALTOUTPADEN_OUT3 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT3 << 4) /**< Shifted mode OUT3 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1371 | #define VDAC_OPA_OUT_ALTOUTPADEN_OUT4 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT4 << 4) /**< Shifted mode OUT4 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1372 | #define _VDAC_OPA_OUT_APORTOUTSEL_SHIFT 16 /**< Shift value for VDAC_OPAAPORTOUTSEL */ |
| Anna Bridge |
142:4eea097334d6 | 1373 | #define _VDAC_OPA_OUT_APORTOUTSEL_MASK 0xFF0000UL /**< Bit mask for VDAC_OPAAPORTOUTSEL */ |
| Anna Bridge |
142:4eea097334d6 | 1374 | #define _VDAC_OPA_OUT_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1375 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1376 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1377 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1378 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1379 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1380 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1381 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1382 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1383 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1384 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1385 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1386 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1387 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1388 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1389 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1390 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1391 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1392 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1393 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1394 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1395 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1396 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1397 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1398 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1399 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1400 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1401 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1402 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1403 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1404 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1405 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1406 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1407 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1408 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1409 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1410 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1411 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1412 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1413 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1414 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1415 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1416 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1417 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1418 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1419 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1420 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1421 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1422 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1423 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1424 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1425 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1426 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1427 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1428 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1429 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1430 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1431 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1432 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1433 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1434 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1435 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1436 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1437 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1438 | #define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1439 | #define VDAC_OPA_OUT_APORTOUTSEL_DEFAULT (_VDAC_OPA_OUT_APORTOUTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1440 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1441 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1442 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1443 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1444 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1445 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1446 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1447 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1448 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1449 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1450 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1451 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1452 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1453 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1454 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1455 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1456 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1457 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1458 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1459 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1460 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1461 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1462 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1463 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1464 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1465 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1466 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1467 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1468 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1469 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1470 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1471 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1472 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1473 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1474 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1475 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1476 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1477 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1478 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1479 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1480 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1481 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1482 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1483 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1484 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1485 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1486 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1487 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1488 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1489 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1490 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1491 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1492 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1493 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1494 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1495 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1496 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1497 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1498 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1499 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1500 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1501 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1502 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1503 | #define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for VDAC_OPA_OUT */ |
| Anna Bridge |
142:4eea097334d6 | 1504 | |
| Anna Bridge |
142:4eea097334d6 | 1505 | /* Bit fields for VDAC OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1506 | #define _VDAC_OPA_CAL_RESETVALUE 0x000080E7UL /**< Default value for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1507 | #define _VDAC_OPA_CAL_MASK 0x7DF6EDEFUL /**< Mask for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1508 | #define _VDAC_OPA_CAL_CM1_SHIFT 0 /**< Shift value for VDAC_OPACM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1509 | #define _VDAC_OPA_CAL_CM1_MASK 0xFUL /**< Bit mask for VDAC_OPACM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1510 | #define _VDAC_OPA_CAL_CM1_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1511 | #define VDAC_OPA_CAL_CM1_DEFAULT (_VDAC_OPA_CAL_CM1_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1512 | #define _VDAC_OPA_CAL_CM2_SHIFT 5 /**< Shift value for VDAC_OPACM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1513 | #define _VDAC_OPA_CAL_CM2_MASK 0x1E0UL /**< Bit mask for VDAC_OPACM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1514 | #define _VDAC_OPA_CAL_CM2_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1515 | #define VDAC_OPA_CAL_CM2_DEFAULT (_VDAC_OPA_CAL_CM2_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1516 | #define _VDAC_OPA_CAL_CM3_SHIFT 10 /**< Shift value for VDAC_OPACM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1517 | #define _VDAC_OPA_CAL_CM3_MASK 0xC00UL /**< Bit mask for VDAC_OPACM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1518 | #define _VDAC_OPA_CAL_CM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1519 | #define VDAC_OPA_CAL_CM3_DEFAULT (_VDAC_OPA_CAL_CM3_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1520 | #define _VDAC_OPA_CAL_GM_SHIFT 13 /**< Shift value for VDAC_OPAGM */ |
| Anna Bridge |
142:4eea097334d6 | 1521 | #define _VDAC_OPA_CAL_GM_MASK 0xE000UL /**< Bit mask for VDAC_OPAGM */ |
| Anna Bridge |
142:4eea097334d6 | 1522 | #define _VDAC_OPA_CAL_GM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1523 | #define VDAC_OPA_CAL_GM_DEFAULT (_VDAC_OPA_CAL_GM_DEFAULT << 13) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1524 | #define _VDAC_OPA_CAL_GM3_SHIFT 17 /**< Shift value for VDAC_OPAGM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1525 | #define _VDAC_OPA_CAL_GM3_MASK 0x60000UL /**< Bit mask for VDAC_OPAGM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1526 | #define _VDAC_OPA_CAL_GM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1527 | #define VDAC_OPA_CAL_GM3_DEFAULT (_VDAC_OPA_CAL_GM3_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1528 | #define _VDAC_OPA_CAL_OFFSETP_SHIFT 20 /**< Shift value for VDAC_OPAOFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1529 | #define _VDAC_OPA_CAL_OFFSETP_MASK 0x1F00000UL /**< Bit mask for VDAC_OPAOFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1530 | #define _VDAC_OPA_CAL_OFFSETP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1531 | #define VDAC_OPA_CAL_OFFSETP_DEFAULT (_VDAC_OPA_CAL_OFFSETP_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1532 | #define _VDAC_OPA_CAL_OFFSETN_SHIFT 26 /**< Shift value for VDAC_OPAOFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1533 | #define _VDAC_OPA_CAL_OFFSETN_MASK 0x7C000000UL /**< Bit mask for VDAC_OPAOFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1534 | #define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1535 | #define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 1536 | |
| Anna Bridge |
142:4eea097334d6 | 1537 | /** @} End of group EFR32MG12P_VDAC */ |
| Anna Bridge |
142:4eea097334d6 | 1538 | /** @} End of group Parts */ |
| Anna Bridge |
142:4eea097334d6 | 1539 |
