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TARGET_TB_SENSE_1/TOOLCHAIN_IAR/efr32mg1p_wdog.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_TB_SENSE_1/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h@142:4eea097334d6
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg1p_wdog.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG1P_WDOG register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG1P_WDOG |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG1P_WDOG Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IOM uint32_t CMD; /**< Command Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | |
| Anna Bridge |
142:4eea097334d6 | 46 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
| Anna Bridge |
142:4eea097334d6 | 47 | |
| Anna Bridge |
142:4eea097334d6 | 48 | WDOG_PCH_TypeDef PCH[2]; /**< PCH */ |
| Anna Bridge |
142:4eea097334d6 | 49 | |
| Anna Bridge |
142:4eea097334d6 | 50 | uint32_t RESERVED0[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 51 | __IM uint32_t IF; /**< Watchdog Interrupt Flags */ |
| Anna Bridge |
142:4eea097334d6 | 52 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| Anna Bridge |
142:4eea097334d6 | 53 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| Anna Bridge |
142:4eea097334d6 | 55 | } WDOG_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 56 | |
| Anna Bridge |
142:4eea097334d6 | 57 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 58 | * @defgroup EFR32MG1P_WDOG_BitFields |
| Anna Bridge |
142:4eea097334d6 | 59 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 60 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 61 | |
| Anna Bridge |
142:4eea097334d6 | 62 | /* Bit fields for WDOG CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 63 | #define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 64 | #define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 65 | #define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */ |
| Anna Bridge |
142:4eea097334d6 | 66 | #define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ |
| Anna Bridge |
142:4eea097334d6 | 67 | #define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ |
| Anna Bridge |
142:4eea097334d6 | 68 | #define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 69 | #define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 70 | #define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ |
| Anna Bridge |
142:4eea097334d6 | 71 | #define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ |
| Anna Bridge |
142:4eea097334d6 | 72 | #define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ |
| Anna Bridge |
142:4eea097334d6 | 73 | #define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 74 | #define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 75 | #define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */ |
| Anna Bridge |
142:4eea097334d6 | 76 | #define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ |
| Anna Bridge |
142:4eea097334d6 | 77 | #define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */ |
| Anna Bridge |
142:4eea097334d6 | 86 | #define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 87 | #define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 88 | #define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 100 | #define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ |
| Anna Bridge |
142:4eea097334d6 | 101 | #define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */ |
| Anna Bridge |
142:4eea097334d6 | 116 | #define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 117 | #define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 121 | #define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 122 | #define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */ |
| Anna Bridge |
142:4eea097334d6 | 124 | #define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */ |
| Anna Bridge |
142:4eea097334d6 | 125 | #define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */ |
| Anna Bridge |
142:4eea097334d6 | 132 | #define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */ |
| Anna Bridge |
142:4eea097334d6 | 133 | #define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 140 | |
| Anna Bridge |
142:4eea097334d6 | 141 | /* Bit fields for WDOG CMD */ |
| Anna Bridge |
142:4eea097334d6 | 142 | #define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 153 | |
| Anna Bridge |
142:4eea097334d6 | 154 | /* Bit fields for WDOG SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 156 | #define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 157 | #define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 159 | #define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 167 | #define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 174 | #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 175 | #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 177 | |
| Anna Bridge |
142:4eea097334d6 | 178 | /* Bit fields for WDOG PCH_PRSCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 179 | #define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 180 | #define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 181 | #define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 182 | #define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 183 | #define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 184 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 185 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 186 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 187 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 188 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 189 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 190 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 191 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 192 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 193 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 194 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 195 | #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 196 | #define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 197 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 198 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 199 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 200 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 201 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 202 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 203 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 204 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 205 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 206 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 207 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 208 | #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 209 | #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */ |
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142:4eea097334d6 | 210 | #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */ |
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142:4eea097334d6 | 211 | #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */ |
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142:4eea097334d6 | 212 | #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 213 | #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ |
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142:4eea097334d6 | 214 | |
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142:4eea097334d6 | 215 | /* Bit fields for WDOG IF */ |
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142:4eea097334d6 | 216 | #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ |
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142:4eea097334d6 | 217 | #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ |
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142:4eea097334d6 | 218 | #define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ |
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142:4eea097334d6 | 219 | #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ |
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142:4eea097334d6 | 220 | #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ |
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142:4eea097334d6 | 221 | #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 222 | #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 223 | #define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ |
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142:4eea097334d6 | 224 | #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ |
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142:4eea097334d6 | 225 | #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ |
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142:4eea097334d6 | 226 | #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 227 | #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 228 | #define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ |
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142:4eea097334d6 | 229 | #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ |
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142:4eea097334d6 | 230 | #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ |
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142:4eea097334d6 | 231 | #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 232 | #define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 233 | #define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */ |
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142:4eea097334d6 | 234 | #define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ |
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142:4eea097334d6 | 235 | #define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ |
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142:4eea097334d6 | 236 | #define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 237 | #define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 238 | #define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */ |
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142:4eea097334d6 | 239 | #define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ |
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142:4eea097334d6 | 240 | #define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ |
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142:4eea097334d6 | 241 | #define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 242 | #define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ |
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142:4eea097334d6 | 243 | |
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142:4eea097334d6 | 244 | /* Bit fields for WDOG IFS */ |
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142:4eea097334d6 | 245 | #define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */ |
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142:4eea097334d6 | 246 | #define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */ |
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142:4eea097334d6 | 247 | #define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */ |
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142:4eea097334d6 | 248 | #define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ |
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142:4eea097334d6 | 249 | #define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ |
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142:4eea097334d6 | 250 | #define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 251 | #define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 252 | #define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */ |
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142:4eea097334d6 | 253 | #define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ |
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142:4eea097334d6 | 254 | #define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ |
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142:4eea097334d6 | 255 | #define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 256 | #define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 257 | #define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */ |
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142:4eea097334d6 | 258 | #define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ |
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142:4eea097334d6 | 259 | #define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ |
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142:4eea097334d6 | 260 | #define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 261 | #define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 262 | #define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */ |
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142:4eea097334d6 | 263 | #define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ |
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142:4eea097334d6 | 264 | #define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ |
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142:4eea097334d6 | 265 | #define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 266 | #define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 267 | #define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */ |
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142:4eea097334d6 | 268 | #define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ |
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142:4eea097334d6 | 269 | #define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ |
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142:4eea097334d6 | 270 | #define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 271 | #define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */ |
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142:4eea097334d6 | 272 | |
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142:4eea097334d6 | 273 | /* Bit fields for WDOG IFC */ |
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142:4eea097334d6 | 274 | #define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */ |
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142:4eea097334d6 | 275 | #define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */ |
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142:4eea097334d6 | 276 | #define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */ |
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142:4eea097334d6 | 277 | #define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ |
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142:4eea097334d6 | 278 | #define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ |
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142:4eea097334d6 | 279 | #define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 280 | #define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 281 | #define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */ |
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142:4eea097334d6 | 282 | #define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ |
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142:4eea097334d6 | 283 | #define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ |
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142:4eea097334d6 | 284 | #define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 285 | #define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 286 | #define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */ |
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142:4eea097334d6 | 287 | #define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ |
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142:4eea097334d6 | 288 | #define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ |
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142:4eea097334d6 | 289 | #define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 290 | #define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 291 | #define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */ |
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142:4eea097334d6 | 292 | #define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ |
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142:4eea097334d6 | 293 | #define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ |
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142:4eea097334d6 | 294 | #define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 295 | #define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 296 | #define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */ |
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142:4eea097334d6 | 297 | #define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ |
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142:4eea097334d6 | 298 | #define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ |
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142:4eea097334d6 | 299 | #define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 300 | #define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */ |
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142:4eea097334d6 | 301 | |
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142:4eea097334d6 | 302 | /* Bit fields for WDOG IEN */ |
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142:4eea097334d6 | 303 | #define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ |
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142:4eea097334d6 | 304 | #define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ |
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142:4eea097334d6 | 305 | #define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */ |
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142:4eea097334d6 | 306 | #define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ |
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142:4eea097334d6 | 307 | #define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ |
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142:4eea097334d6 | 308 | #define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 309 | #define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 310 | #define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */ |
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142:4eea097334d6 | 311 | #define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ |
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142:4eea097334d6 | 312 | #define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ |
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142:4eea097334d6 | 313 | #define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 314 | #define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 315 | #define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */ |
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142:4eea097334d6 | 316 | #define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ |
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142:4eea097334d6 | 317 | #define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ |
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142:4eea097334d6 | 318 | #define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 319 | #define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 320 | #define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 321 | #define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ |
| Anna Bridge |
142:4eea097334d6 | 322 | #define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ |
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142:4eea097334d6 | 323 | #define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 324 | #define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 325 | #define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 326 | #define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ |
| Anna Bridge |
142:4eea097334d6 | 327 | #define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ |
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142:4eea097334d6 | 328 | #define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 329 | #define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ |
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142:4eea097334d6 | 330 | |
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142:4eea097334d6 | 331 | /** @} End of group EFR32MG1P_WDOG */ |
| Anna Bridge |
142:4eea097334d6 | 332 | /** @} End of group Parts */ |
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142:4eea097334d6 | 333 |
