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TARGET_TB_SENSE_1/TOOLCHAIN_IAR/efr32mg1p_cmu.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_TB_SENSE_1/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h@142:4eea097334d6 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file efr32mg1p_cmu.h
Anna Bridge 142:4eea097334d6 3 * @brief EFR32MG1P_CMU register and bit field definitions
Anna Bridge 142:4eea097334d6 4 * @version 5.1.2
Anna Bridge 142:4eea097334d6 5 ******************************************************************************
Anna Bridge 142:4eea097334d6 6 * @section License
Anna Bridge 142:4eea097334d6 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
Anna Bridge 142:4eea097334d6 8 ******************************************************************************
Anna Bridge 142:4eea097334d6 9 *
Anna Bridge 142:4eea097334d6 10 * Permission is granted to anyone to use this software for any purpose,
Anna Bridge 142:4eea097334d6 11 * including commercial applications, and to alter it and redistribute it
Anna Bridge 142:4eea097334d6 12 * freely, subject to the following restrictions:
Anna Bridge 142:4eea097334d6 13 *
Anna Bridge 142:4eea097334d6 14 * 1. The origin of this software must not be misrepresented; you must not
Anna Bridge 142:4eea097334d6 15 * claim that you wrote the original software.@n
Anna Bridge 142:4eea097334d6 16 * 2. Altered source versions must be plainly marked as such, and must not be
Anna Bridge 142:4eea097334d6 17 * misrepresented as being the original software.@n
Anna Bridge 142:4eea097334d6 18 * 3. This notice may not be removed or altered from any source distribution.
Anna Bridge 142:4eea097334d6 19 *
Anna Bridge 142:4eea097334d6 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Anna Bridge 142:4eea097334d6 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Anna Bridge 142:4eea097334d6 22 * providing the Software "AS IS", with no express or implied warranties of any
Anna Bridge 142:4eea097334d6 23 * kind, including, but not limited to, any implied warranties of
Anna Bridge 142:4eea097334d6 24 * merchantability or fitness for any particular purpose or warranties against
Anna Bridge 142:4eea097334d6 25 * infringement of any proprietary rights of a third party.
Anna Bridge 142:4eea097334d6 26 *
Anna Bridge 142:4eea097334d6 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
Anna Bridge 142:4eea097334d6 28 * incidental, or special damages, or any other relief, or for any claim by
Anna Bridge 142:4eea097334d6 29 * any third party, arising from your use of this Software.
Anna Bridge 142:4eea097334d6 30 *
Anna Bridge 142:4eea097334d6 31 *****************************************************************************/
Anna Bridge 142:4eea097334d6 32 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 33 * @addtogroup Parts
Anna Bridge 142:4eea097334d6 34 * @{
Anna Bridge 142:4eea097334d6 35 ******************************************************************************/
Anna Bridge 142:4eea097334d6 36 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 37 * @defgroup EFR32MG1P_CMU
Anna Bridge 142:4eea097334d6 38 * @{
Anna Bridge 142:4eea097334d6 39 * @brief EFR32MG1P_CMU Register Declaration
Anna Bridge 142:4eea097334d6 40 *****************************************************************************/
Anna Bridge 142:4eea097334d6 41 typedef struct
Anna Bridge 142:4eea097334d6 42 {
Anna Bridge 142:4eea097334d6 43 __IOM uint32_t CTRL; /**< CMU Control Register */
Anna Bridge 142:4eea097334d6 44
Anna Bridge 142:4eea097334d6 45 uint32_t RESERVED0[3]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 46 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
Anna Bridge 142:4eea097334d6 47
Anna Bridge 142:4eea097334d6 48 uint32_t RESERVED1[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 49 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
Anna Bridge 142:4eea097334d6 50
Anna Bridge 142:4eea097334d6 51 uint32_t RESERVED2[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 52 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
Anna Bridge 142:4eea097334d6 53 __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */
Anna Bridge 142:4eea097334d6 54 __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */
Anna Bridge 142:4eea097334d6 55 __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */
Anna Bridge 142:4eea097334d6 56 __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */
Anna Bridge 142:4eea097334d6 57 __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */
Anna Bridge 142:4eea097334d6 58 __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */
Anna Bridge 142:4eea097334d6 59 __IOM uint32_t ULFRCOCTRL; /**< ULFRCO Control Register */
Anna Bridge 142:4eea097334d6 60
Anna Bridge 142:4eea097334d6 61 uint32_t RESERVED3[4]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 62 __IOM uint32_t CALCTRL; /**< Calibration Control Register */
Anna Bridge 142:4eea097334d6 63 __IOM uint32_t CALCNT; /**< Calibration Counter Register */
Anna Bridge 142:4eea097334d6 64 uint32_t RESERVED4[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 65 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
Anna Bridge 142:4eea097334d6 66 __IOM uint32_t CMD; /**< Command Register */
Anna Bridge 142:4eea097334d6 67 uint32_t RESERVED5[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 68 __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */
Anna Bridge 142:4eea097334d6 69 __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */
Anna Bridge 142:4eea097334d6 70 uint32_t RESERVED6[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 71 __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */
Anna Bridge 142:4eea097334d6 72 __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */
Anna Bridge 142:4eea097334d6 73 __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */
Anna Bridge 142:4eea097334d6 74
Anna Bridge 142:4eea097334d6 75 uint32_t RESERVED7[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 76 __IM uint32_t STATUS; /**< Status Register */
Anna Bridge 142:4eea097334d6 77 __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */
Anna Bridge 142:4eea097334d6 78 uint32_t RESERVED8[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 79 __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */
Anna Bridge 142:4eea097334d6 80 __IM uint32_t IF; /**< Interrupt Flag Register */
Anna Bridge 142:4eea097334d6 81 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
Anna Bridge 142:4eea097334d6 82 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
Anna Bridge 142:4eea097334d6 83 __IOM uint32_t IEN; /**< Interrupt Enable Register */
Anna Bridge 142:4eea097334d6 84 __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */
Anna Bridge 142:4eea097334d6 85
Anna Bridge 142:4eea097334d6 86 uint32_t RESERVED9[3]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 87 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
Anna Bridge 142:4eea097334d6 88
Anna Bridge 142:4eea097334d6 89 uint32_t RESERVED10[7]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 90 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
Anna Bridge 142:4eea097334d6 91 uint32_t RESERVED11[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 92 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
Anna Bridge 142:4eea097334d6 93
Anna Bridge 142:4eea097334d6 94 uint32_t RESERVED12[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 95 __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */
Anna Bridge 142:4eea097334d6 96 uint32_t RESERVED13[3]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 97 __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */
Anna Bridge 142:4eea097334d6 98
Anna Bridge 142:4eea097334d6 99 uint32_t RESERVED14[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 100 __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */
Anna Bridge 142:4eea097334d6 101 __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */
Anna Bridge 142:4eea097334d6 102
Anna Bridge 142:4eea097334d6 103 uint32_t RESERVED15[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 104 __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */
Anna Bridge 142:4eea097334d6 105
Anna Bridge 142:4eea097334d6 106 uint32_t RESERVED16[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 107 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
Anna Bridge 142:4eea097334d6 108 uint32_t RESERVED17[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 109 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
Anna Bridge 142:4eea097334d6 110 uint32_t RESERVED18[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 111 __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */
Anna Bridge 142:4eea097334d6 112
Anna Bridge 142:4eea097334d6 113 uint32_t RESERVED19[3]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 114 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
Anna Bridge 142:4eea097334d6 115 __IOM uint32_t FREEZE; /**< Freeze Register */
Anna Bridge 142:4eea097334d6 116 uint32_t RESERVED20[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 117 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
Anna Bridge 142:4eea097334d6 118
Anna Bridge 142:4eea097334d6 119 uint32_t RESERVED21[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 120 __IOM uint32_t ADCCTRL; /**< ADC Control Register */
Anna Bridge 142:4eea097334d6 121
Anna Bridge 142:4eea097334d6 122 uint32_t RESERVED22[4]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 123 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
Anna Bridge 142:4eea097334d6 124 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
Anna Bridge 142:4eea097334d6 125
Anna Bridge 142:4eea097334d6 126 uint32_t RESERVED23[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 127 __IOM uint32_t LOCK; /**< Configuration Lock Register */
Anna Bridge 142:4eea097334d6 128 } CMU_TypeDef; /** @} */
Anna Bridge 142:4eea097334d6 129
Anna Bridge 142:4eea097334d6 130 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 131 * @defgroup EFR32MG1P_CMU_BitFields
Anna Bridge 142:4eea097334d6 132 * @{
Anna Bridge 142:4eea097334d6 133 *****************************************************************************/
Anna Bridge 142:4eea097334d6 134
Anna Bridge 142:4eea097334d6 135 /* Bit fields for CMU CTRL */
Anna Bridge 142:4eea097334d6 136 #define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */
Anna Bridge 142:4eea097334d6 137 #define _CMU_CTRL_MASK 0x001101EFUL /**< Mask for CMU_CTRL */
Anna Bridge 142:4eea097334d6 138 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */
Anna Bridge 142:4eea097334d6 139 #define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */
Anna Bridge 142:4eea097334d6 140 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Anna Bridge 142:4eea097334d6 141 #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */
Anna Bridge 142:4eea097334d6 142 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 143 #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 144 #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 145 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 146 #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */
Anna Bridge 142:4eea097334d6 147 #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 148 #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 149 #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 150 #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 151 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 152 #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 153 #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */
Anna Bridge 142:4eea097334d6 154 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
Anna Bridge 142:4eea097334d6 155 #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */
Anna Bridge 142:4eea097334d6 156 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 157 #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 158 #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 159 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 160 #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */
Anna Bridge 142:4eea097334d6 161 #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 162 #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 163 #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 164 #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 165 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 166 #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 167 #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */
Anna Bridge 142:4eea097334d6 168 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */
Anna Bridge 142:4eea097334d6 169 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL /**< Bit mask for CMU_CLKOUTSEL1 */
Anna Bridge 142:4eea097334d6 170 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Anna Bridge 142:4eea097334d6 171 #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */
Anna Bridge 142:4eea097334d6 172 #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 173 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 174 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 175 #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 176 #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */
Anna Bridge 142:4eea097334d6 177 #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 178 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 179 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 180 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 181 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 182 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 183 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */
Anna Bridge 142:4eea097334d6 184 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
Anna Bridge 142:4eea097334d6 185 #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */
Anna Bridge 142:4eea097334d6 186 #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 187 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 188 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 189 #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */
Anna Bridge 142:4eea097334d6 190 #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */
Anna Bridge 142:4eea097334d6 191 #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 192 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 193 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 194 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 195 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 196 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */
Anna Bridge 142:4eea097334d6 197 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */
Anna Bridge 142:4eea097334d6 198 #define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */
Anna Bridge 142:4eea097334d6 199 #define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */
Anna Bridge 142:4eea097334d6 200 #define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */
Anna Bridge 142:4eea097334d6 201 #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Anna Bridge 142:4eea097334d6 202 #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */
Anna Bridge 142:4eea097334d6 203 #define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */
Anna Bridge 142:4eea097334d6 204 #define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */
Anna Bridge 142:4eea097334d6 205 #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */
Anna Bridge 142:4eea097334d6 206 #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
Anna Bridge 142:4eea097334d6 207 #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
Anna Bridge 142:4eea097334d6 208
Anna Bridge 142:4eea097334d6 209 /* Bit fields for CMU HFRCOCTRL */
Anna Bridge 142:4eea097334d6 210 #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F3CUL /**< Default value for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 211 #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 212 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Anna Bridge 142:4eea097334d6 213 #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
Anna Bridge 142:4eea097334d6 214 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000003CUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 215 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 216 #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */
Anna Bridge 142:4eea097334d6 217 #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */
Anna Bridge 142:4eea097334d6 218 #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 219 #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 220 #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */
Anna Bridge 142:4eea097334d6 221 #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */
Anna Bridge 142:4eea097334d6 222 #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 223 #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 224 #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */
Anna Bridge 142:4eea097334d6 225 #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */
Anna Bridge 142:4eea097334d6 226 #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 227 #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 228 #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */
Anna Bridge 142:4eea097334d6 229 #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */
Anna Bridge 142:4eea097334d6 230 #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */
Anna Bridge 142:4eea097334d6 231 #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 232 #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 233 #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */
Anna Bridge 142:4eea097334d6 234 #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */
Anna Bridge 142:4eea097334d6 235 #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 236 #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 237 #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 238 #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 239 #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 240 #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 241 #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 242 #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 243 #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */
Anna Bridge 142:4eea097334d6 244 #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
Anna Bridge 142:4eea097334d6 245 #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
Anna Bridge 142:4eea097334d6 246 #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 247 #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 248 #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */
Anna Bridge 142:4eea097334d6 249 #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */
Anna Bridge 142:4eea097334d6 250 #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 251 #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Anna Bridge 142:4eea097334d6 252
Anna Bridge 142:4eea097334d6 253 /* Bit fields for CMU AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 254 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F3CUL /**< Default value for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 255 #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 256 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Anna Bridge 142:4eea097334d6 257 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
Anna Bridge 142:4eea097334d6 258 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000003CUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 259 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 260 #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */
Anna Bridge 142:4eea097334d6 261 #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */
Anna Bridge 142:4eea097334d6 262 #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 263 #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 264 #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */
Anna Bridge 142:4eea097334d6 265 #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */
Anna Bridge 142:4eea097334d6 266 #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 267 #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 268 #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */
Anna Bridge 142:4eea097334d6 269 #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */
Anna Bridge 142:4eea097334d6 270 #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 271 #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 272 #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */
Anna Bridge 142:4eea097334d6 273 #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */
Anna Bridge 142:4eea097334d6 274 #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */
Anna Bridge 142:4eea097334d6 275 #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 276 #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 277 #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */
Anna Bridge 142:4eea097334d6 278 #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */
Anna Bridge 142:4eea097334d6 279 #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 280 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 281 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 282 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 283 #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 284 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 285 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 286 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 287 #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */
Anna Bridge 142:4eea097334d6 288 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
Anna Bridge 142:4eea097334d6 289 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
Anna Bridge 142:4eea097334d6 290 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 291 #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 292 #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */
Anna Bridge 142:4eea097334d6 293 #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */
Anna Bridge 142:4eea097334d6 294 #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 295 #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Anna Bridge 142:4eea097334d6 296
Anna Bridge 142:4eea097334d6 297 /* Bit fields for CMU LFRCOCTRL */
Anna Bridge 142:4eea097334d6 298 #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 299 #define _CMU_LFRCOCTRL_MASK 0xF30701FFUL /**< Mask for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 300 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Anna Bridge 142:4eea097334d6 301 #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */
Anna Bridge 142:4eea097334d6 302 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 303 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 304 #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */
Anna Bridge 142:4eea097334d6 305 #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */
Anna Bridge 142:4eea097334d6 306 #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */
Anna Bridge 142:4eea097334d6 307 #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 308 #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 309 #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */
Anna Bridge 142:4eea097334d6 310 #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */
Anna Bridge 142:4eea097334d6 311 #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */
Anna Bridge 142:4eea097334d6 312 #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 313 #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 314 #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */
Anna Bridge 142:4eea097334d6 315 #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */
Anna Bridge 142:4eea097334d6 316 #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */
Anna Bridge 142:4eea097334d6 317 #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 318 #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 319 #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */
Anna Bridge 142:4eea097334d6 320 #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */
Anna Bridge 142:4eea097334d6 321 #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 322 #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 323 #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 324 #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 325 #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 326 #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 327 #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 328 #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 329 #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */
Anna Bridge 142:4eea097334d6 330 #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */
Anna Bridge 142:4eea097334d6 331 #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 332 #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
Anna Bridge 142:4eea097334d6 333
Anna Bridge 142:4eea097334d6 334 /* Bit fields for CMU HFXOCTRL */
Anna Bridge 142:4eea097334d6 335 #define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 336 #define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 337 #define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */
Anna Bridge 142:4eea097334d6 338 #define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */
Anna Bridge 142:4eea097334d6 339 #define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */
Anna Bridge 142:4eea097334d6 340 #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 341 #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 342 #define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 343 #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 344 #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 345 #define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 346 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */
Anna Bridge 142:4eea097334d6 347 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */
Anna Bridge 142:4eea097334d6 348 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 349 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 350 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 351 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 352 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 353 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 354 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 355 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 356 #define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low power mode control. PSR performance is reduced to enable low current consumption. */
Anna Bridge 142:4eea097334d6 357 #define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */
Anna Bridge 142:4eea097334d6 358 #define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */
Anna Bridge 142:4eea097334d6 359 #define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 360 #define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 361 #define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off. */
Anna Bridge 142:4eea097334d6 362 #define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */
Anna Bridge 142:4eea097334d6 363 #define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */
Anna Bridge 142:4eea097334d6 364 #define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 365 #define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 366 #define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off. */
Anna Bridge 142:4eea097334d6 367 #define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */
Anna Bridge 142:4eea097334d6 368 #define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */
Anna Bridge 142:4eea097334d6 369 #define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 370 #define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 371 #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */
Anna Bridge 142:4eea097334d6 372 #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */
Anna Bridge 142:4eea097334d6 373 #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 374 #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 375 #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 376 #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 377 #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 378 #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 379 #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 380 #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 381 #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 382 #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 383 #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 384 #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 385 #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 386 #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 387 #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 388 #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 389 #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 390 #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 391 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */
Anna Bridge 142:4eea097334d6 392 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */
Anna Bridge 142:4eea097334d6 393 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */
Anna Bridge 142:4eea097334d6 394 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 395 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 396 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */
Anna Bridge 142:4eea097334d6 397 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */
Anna Bridge 142:4eea097334d6 398 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */
Anna Bridge 142:4eea097334d6 399 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 400 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
Anna Bridge 142:4eea097334d6 401
Anna Bridge 142:4eea097334d6 402 /* Bit fields for CMU HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 403 #define _CMU_HFXOCTRL1_RESETVALUE 0x00000240UL /**< Default value for CMU_HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 404 #define _CMU_HFXOCTRL1_MASK 0x00000277UL /**< Mask for CMU_HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 405 #define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 0 /**< Shift value for CMU_PEAKDETTHR */
Anna Bridge 142:4eea097334d6 406 #define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7UL /**< Bit mask for CMU_PEAKDETTHR */
Anna Bridge 142:4eea097334d6 407 #define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 408 #define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 409 #define _CMU_HFXOCTRL1_REGLVL_SHIFT 4 /**< Shift value for CMU_REGLVL */
Anna Bridge 142:4eea097334d6 410 #define _CMU_HFXOCTRL1_REGLVL_MASK 0x70UL /**< Bit mask for CMU_REGLVL */
Anna Bridge 142:4eea097334d6 411 #define _CMU_HFXOCTRL1_REGLVL_DEFAULT 0x00000004UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 412 #define CMU_HFXOCTRL1_REGLVL_DEFAULT (_CMU_HFXOCTRL1_REGLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 413 #define CMU_HFXOCTRL1_XTIBIASEN (0x1UL << 9) /**< Reserved for internal use. Do not change. */
Anna Bridge 142:4eea097334d6 414 #define _CMU_HFXOCTRL1_XTIBIASEN_SHIFT 9 /**< Shift value for CMU_XTIBIASEN */
Anna Bridge 142:4eea097334d6 415 #define _CMU_HFXOCTRL1_XTIBIASEN_MASK 0x200UL /**< Bit mask for CMU_XTIBIASEN */
Anna Bridge 142:4eea097334d6 416 #define _CMU_HFXOCTRL1_XTIBIASEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 417 #define CMU_HFXOCTRL1_XTIBIASEN_DEFAULT (_CMU_HFXOCTRL1_XTIBIASEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
Anna Bridge 142:4eea097334d6 418
Anna Bridge 142:4eea097334d6 419 /* Bit fields for CMU HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 420 #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0xA1250060UL /**< Default value for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 421 #define _CMU_HFXOSTARTUPCTRL_MASK 0xFFEFF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 422 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
Anna Bridge 142:4eea097334d6 423 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
Anna Bridge 142:4eea097334d6 424 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000060UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 425 #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 426 #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */
Anna Bridge 142:4eea097334d6 427 #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */
Anna Bridge 142:4eea097334d6 428 #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 429 #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 430 #define _CMU_HFXOSTARTUPCTRL_RESERVED0_SHIFT 21 /**< Shift value for CMU_RESERVED0 */
Anna Bridge 142:4eea097334d6 431 #define _CMU_HFXOSTARTUPCTRL_RESERVED0_MASK 0xFE00000UL /**< Bit mask for CMU_RESERVED0 */
Anna Bridge 142:4eea097334d6 432 #define _CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT 0x00000009UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 433 #define CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT (_CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 434 #define _CMU_HFXOSTARTUPCTRL_RESERVED1_SHIFT 28 /**< Shift value for CMU_RESERVED1 */
Anna Bridge 142:4eea097334d6 435 #define _CMU_HFXOSTARTUPCTRL_RESERVED1_MASK 0xF0000000UL /**< Bit mask for CMU_RESERVED1 */
Anna Bridge 142:4eea097334d6 436 #define _CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 437 #define CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT (_CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
Anna Bridge 142:4eea097334d6 438
Anna Bridge 142:4eea097334d6 439 /* Bit fields for CMU HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 440 #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30AAD09UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 441 #define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 442 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
Anna Bridge 142:4eea097334d6 443 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
Anna Bridge 142:4eea097334d6 444 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000009UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 445 #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 446 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */
Anna Bridge 142:4eea097334d6 447 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */
Anna Bridge 142:4eea097334d6 448 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 449 #define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 450 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */
Anna Bridge 142:4eea097334d6 451 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */
Anna Bridge 142:4eea097334d6 452 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000155UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 453 #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 454 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */
Anna Bridge 142:4eea097334d6 455 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */
Anna Bridge 142:4eea097334d6 456 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 457 #define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 458 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */
Anna Bridge 142:4eea097334d6 459 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */
Anna Bridge 142:4eea097334d6 460 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */
Anna Bridge 142:4eea097334d6 461 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 462 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 463 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */
Anna Bridge 142:4eea097334d6 464 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */
Anna Bridge 142:4eea097334d6 465 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 466 #define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
Anna Bridge 142:4eea097334d6 467
Anna Bridge 142:4eea097334d6 468 /* Bit fields for CMU HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 469 #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x00026667UL /**< Default value for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 470 #define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 471 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */
Anna Bridge 142:4eea097334d6 472 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */
Anna Bridge 142:4eea097334d6 473 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 474 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 475 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 476 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 477 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 478 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 479 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 480 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 481 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 482 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 483 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 484 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 485 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 486 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 487 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 488 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 489 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 490 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 491 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 492 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 493 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 494 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 495 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 496 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 497 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */
Anna Bridge 142:4eea097334d6 498 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */
Anna Bridge 142:4eea097334d6 499 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 500 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 501 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 502 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 503 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 504 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 505 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 506 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 507 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 508 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 509 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 510 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 511 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 512 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 513 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 514 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 515 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 516 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 517 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 518 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 519 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 520 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 521 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 522 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 523 #define _CMU_HFXOTIMEOUTCTRL_RESERVED2_SHIFT 8 /**< Shift value for CMU_RESERVED2 */
Anna Bridge 142:4eea097334d6 524 #define _CMU_HFXOTIMEOUTCTRL_RESERVED2_MASK 0xF00UL /**< Bit mask for CMU_RESERVED2 */
Anna Bridge 142:4eea097334d6 525 #define _CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 526 #define CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT (_CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 527 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */
Anna Bridge 142:4eea097334d6 528 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */
Anna Bridge 142:4eea097334d6 529 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 530 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 531 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 532 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 533 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 534 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 535 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 536 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 537 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 538 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 539 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 540 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 541 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 542 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 543 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 544 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 545 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 546 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 547 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 548 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 549 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 550 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 551 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 552 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 553 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */
Anna Bridge 142:4eea097334d6 554 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */
Anna Bridge 142:4eea097334d6 555 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 556 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 557 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 558 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 559 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 560 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 561 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 562 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 563 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 564 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 565 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 566 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 567 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 568 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 569 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 570 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 571 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 572 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 573 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 574 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 575 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 576 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 577 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 578 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
Anna Bridge 142:4eea097334d6 579
Anna Bridge 142:4eea097334d6 580 /* Bit fields for CMU LFXOCTRL */
Anna Bridge 142:4eea097334d6 581 #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 582 #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 583 #define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Anna Bridge 142:4eea097334d6 584 #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
Anna Bridge 142:4eea097334d6 585 #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 586 #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 587 #define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */
Anna Bridge 142:4eea097334d6 588 #define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */
Anna Bridge 142:4eea097334d6 589 #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 590 #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 591 #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 592 #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 593 #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 594 #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 595 #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 596 #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 597 #define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */
Anna Bridge 142:4eea097334d6 598 #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */
Anna Bridge 142:4eea097334d6 599 #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 600 #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 601 #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */
Anna Bridge 142:4eea097334d6 602 #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */
Anna Bridge 142:4eea097334d6 603 #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */
Anna Bridge 142:4eea097334d6 604 #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 605 #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 606 #define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */
Anna Bridge 142:4eea097334d6 607 #define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */
Anna Bridge 142:4eea097334d6 608 #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */
Anna Bridge 142:4eea097334d6 609 #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 610 #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 611 #define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */
Anna Bridge 142:4eea097334d6 612 #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */
Anna Bridge 142:4eea097334d6 613 #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 614 #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 615 #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */
Anna Bridge 142:4eea097334d6 616 #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */
Anna Bridge 142:4eea097334d6 617 #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */
Anna Bridge 142:4eea097334d6 618 #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 619 #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 620 #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */
Anna Bridge 142:4eea097334d6 621 #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */
Anna Bridge 142:4eea097334d6 622 #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 623 #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 624 #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 625 #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 626 #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 627 #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 628 #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 629 #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 630 #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 631 #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 632 #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 633 #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 634 #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 635 #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 636 #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 637 #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 638 #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 639 #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */
Anna Bridge 142:4eea097334d6 640
Anna Bridge 142:4eea097334d6 641 /* Bit fields for CMU ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 642 #define _CMU_ULFRCOCTRL_RESETVALUE 0x00020020UL /**< Default value for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 643 #define _CMU_ULFRCOCTRL_MASK 0x00030C3FUL /**< Mask for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 644 #define _CMU_ULFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Anna Bridge 142:4eea097334d6 645 #define _CMU_ULFRCOCTRL_TUNING_MASK 0x3FUL /**< Bit mask for CMU_TUNING */
Anna Bridge 142:4eea097334d6 646 #define _CMU_ULFRCOCTRL_TUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 647 #define CMU_ULFRCOCTRL_TUNING_DEFAULT (_CMU_ULFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 648 #define _CMU_ULFRCOCTRL_MODE_SHIFT 10 /**< Shift value for CMU_MODE */
Anna Bridge 142:4eea097334d6 649 #define _CMU_ULFRCOCTRL_MODE_MASK 0xC00UL /**< Bit mask for CMU_MODE */
Anna Bridge 142:4eea097334d6 650 #define _CMU_ULFRCOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 651 #define _CMU_ULFRCOCTRL_MODE_1KHZ 0x00000000UL /**< Mode 1KHZ for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 652 #define _CMU_ULFRCOCTRL_MODE_2KHZ 0x00000001UL /**< Mode 2KHZ for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 653 #define _CMU_ULFRCOCTRL_MODE_4KHZ 0x00000002UL /**< Mode 4KHZ for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 654 #define _CMU_ULFRCOCTRL_MODE_32KHZ 0x00000003UL /**< Mode 32KHZ for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 655 #define CMU_ULFRCOCTRL_MODE_DEFAULT (_CMU_ULFRCOCTRL_MODE_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 656 #define CMU_ULFRCOCTRL_MODE_1KHZ (_CMU_ULFRCOCTRL_MODE_1KHZ << 10) /**< Shifted mode 1KHZ for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 657 #define CMU_ULFRCOCTRL_MODE_2KHZ (_CMU_ULFRCOCTRL_MODE_2KHZ << 10) /**< Shifted mode 2KHZ for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 658 #define CMU_ULFRCOCTRL_MODE_4KHZ (_CMU_ULFRCOCTRL_MODE_4KHZ << 10) /**< Shifted mode 4KHZ for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 659 #define CMU_ULFRCOCTRL_MODE_32KHZ (_CMU_ULFRCOCTRL_MODE_32KHZ << 10) /**< Shifted mode 32KHZ for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 660 #define _CMU_ULFRCOCTRL_RESTRIM_SHIFT 16 /**< Shift value for CMU_RESTRIM */
Anna Bridge 142:4eea097334d6 661 #define _CMU_ULFRCOCTRL_RESTRIM_MASK 0x30000UL /**< Bit mask for CMU_RESTRIM */
Anna Bridge 142:4eea097334d6 662 #define _CMU_ULFRCOCTRL_RESTRIM_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 663 #define CMU_ULFRCOCTRL_RESTRIM_DEFAULT (_CMU_ULFRCOCTRL_RESTRIM_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */
Anna Bridge 142:4eea097334d6 664
Anna Bridge 142:4eea097334d6 665 /* Bit fields for CMU CALCTRL */
Anna Bridge 142:4eea097334d6 666 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 667 #define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 668 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
Anna Bridge 142:4eea097334d6 669 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
Anna Bridge 142:4eea097334d6 670 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 671 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 672 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 673 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 674 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 675 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 676 #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 677 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 678 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 679 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 680 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 681 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 682 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 683 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 684 #define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */
Anna Bridge 142:4eea097334d6 685 #define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL /**< Bit mask for CMU_DOWNSEL */
Anna Bridge 142:4eea097334d6 686 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 687 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 688 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 689 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 690 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 691 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 692 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 693 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 694 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 695 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 696 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 697 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 698 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 699 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 700 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 701 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 702 #define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */
Anna Bridge 142:4eea097334d6 703 #define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */
Anna Bridge 142:4eea097334d6 704 #define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */
Anna Bridge 142:4eea097334d6 705 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 706 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 707 #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */
Anna Bridge 142:4eea097334d6 708 #define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */
Anna Bridge 142:4eea097334d6 709 #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 710 #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 711 #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 712 #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 713 #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 714 #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 715 #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 716 #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 717 #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 718 #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 719 #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 720 #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 721 #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 722 #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 723 #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 724 #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 725 #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 726 #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 727 #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 728 #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 729 #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 730 #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 731 #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 732 #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 733 #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 734 #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 735 #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */
Anna Bridge 142:4eea097334d6 736 #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */
Anna Bridge 142:4eea097334d6 737 #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 738 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 739 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 740 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 741 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 742 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 743 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 744 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 745 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 746 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 747 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 748 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 749 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 750 #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 751 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 752 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 753 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 754 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 755 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 756 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 757 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 758 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 759 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 760 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 761 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 762 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */
Anna Bridge 142:4eea097334d6 763
Anna Bridge 142:4eea097334d6 764 /* Bit fields for CMU CALCNT */
Anna Bridge 142:4eea097334d6 765 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
Anna Bridge 142:4eea097334d6 766 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
Anna Bridge 142:4eea097334d6 767 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
Anna Bridge 142:4eea097334d6 768 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
Anna Bridge 142:4eea097334d6 769 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
Anna Bridge 142:4eea097334d6 770 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
Anna Bridge 142:4eea097334d6 771
Anna Bridge 142:4eea097334d6 772 /* Bit fields for CMU OSCENCMD */
Anna Bridge 142:4eea097334d6 773 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 774 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 775 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
Anna Bridge 142:4eea097334d6 776 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
Anna Bridge 142:4eea097334d6 777 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
Anna Bridge 142:4eea097334d6 778 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 779 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 780 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
Anna Bridge 142:4eea097334d6 781 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 782 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 783 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 784 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 785 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
Anna Bridge 142:4eea097334d6 786 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
Anna Bridge 142:4eea097334d6 787 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
Anna Bridge 142:4eea097334d6 788 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 789 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 790 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
Anna Bridge 142:4eea097334d6 791 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
Anna Bridge 142:4eea097334d6 792 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
Anna Bridge 142:4eea097334d6 793 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 794 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 795 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
Anna Bridge 142:4eea097334d6 796 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
Anna Bridge 142:4eea097334d6 797 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
Anna Bridge 142:4eea097334d6 798 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 799 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 800 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
Anna Bridge 142:4eea097334d6 801 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
Anna Bridge 142:4eea097334d6 802 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
Anna Bridge 142:4eea097334d6 803 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 804 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 805 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
Anna Bridge 142:4eea097334d6 806 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
Anna Bridge 142:4eea097334d6 807 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
Anna Bridge 142:4eea097334d6 808 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 809 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 810 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
Anna Bridge 142:4eea097334d6 811 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
Anna Bridge 142:4eea097334d6 812 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
Anna Bridge 142:4eea097334d6 813 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 814 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 815 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
Anna Bridge 142:4eea097334d6 816 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
Anna Bridge 142:4eea097334d6 817 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
Anna Bridge 142:4eea097334d6 818 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 819 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 820 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
Anna Bridge 142:4eea097334d6 821 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
Anna Bridge 142:4eea097334d6 822 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
Anna Bridge 142:4eea097334d6 823 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 824 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Anna Bridge 142:4eea097334d6 825
Anna Bridge 142:4eea097334d6 826 /* Bit fields for CMU CMD */
Anna Bridge 142:4eea097334d6 827 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
Anna Bridge 142:4eea097334d6 828 #define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */
Anna Bridge 142:4eea097334d6 829 #define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */
Anna Bridge 142:4eea097334d6 830 #define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */
Anna Bridge 142:4eea097334d6 831 #define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */
Anna Bridge 142:4eea097334d6 832 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Anna Bridge 142:4eea097334d6 833 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
Anna Bridge 142:4eea097334d6 834 #define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */
Anna Bridge 142:4eea097334d6 835 #define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */
Anna Bridge 142:4eea097334d6 836 #define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */
Anna Bridge 142:4eea097334d6 837 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Anna Bridge 142:4eea097334d6 838 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */
Anna Bridge 142:4eea097334d6 839 #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */
Anna Bridge 142:4eea097334d6 840 #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */
Anna Bridge 142:4eea097334d6 841 #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */
Anna Bridge 142:4eea097334d6 842 #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Anna Bridge 142:4eea097334d6 843 #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
Anna Bridge 142:4eea097334d6 844 #define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */
Anna Bridge 142:4eea097334d6 845 #define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */
Anna Bridge 142:4eea097334d6 846 #define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */
Anna Bridge 142:4eea097334d6 847 #define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Anna Bridge 142:4eea097334d6 848 #define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
Anna Bridge 142:4eea097334d6 849
Anna Bridge 142:4eea097334d6 850 /* Bit fields for CMU DBGCLKSEL */
Anna Bridge 142:4eea097334d6 851 #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */
Anna Bridge 142:4eea097334d6 852 #define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */
Anna Bridge 142:4eea097334d6 853 #define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */
Anna Bridge 142:4eea097334d6 854 #define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */
Anna Bridge 142:4eea097334d6 855 #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */
Anna Bridge 142:4eea097334d6 856 #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */
Anna Bridge 142:4eea097334d6 857 #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */
Anna Bridge 142:4eea097334d6 858 #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */
Anna Bridge 142:4eea097334d6 859 #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */
Anna Bridge 142:4eea097334d6 860 #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */
Anna Bridge 142:4eea097334d6 861
Anna Bridge 142:4eea097334d6 862 /* Bit fields for CMU HFCLKSEL */
Anna Bridge 142:4eea097334d6 863 #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 864 #define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 865 #define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */
Anna Bridge 142:4eea097334d6 866 #define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */
Anna Bridge 142:4eea097334d6 867 #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 868 #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 869 #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 870 #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 871 #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 872 #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 873 #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 874 #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 875 #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 876 #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */
Anna Bridge 142:4eea097334d6 877
Anna Bridge 142:4eea097334d6 878 /* Bit fields for CMU LFACLKSEL */
Anna Bridge 142:4eea097334d6 879 #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 880 #define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 881 #define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
Anna Bridge 142:4eea097334d6 882 #define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */
Anna Bridge 142:4eea097334d6 883 #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 884 #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 885 #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 886 #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 887 #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 888 #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 889 #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 890 #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 891 #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 892 #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */
Anna Bridge 142:4eea097334d6 893
Anna Bridge 142:4eea097334d6 894 /* Bit fields for CMU LFBCLKSEL */
Anna Bridge 142:4eea097334d6 895 #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 896 #define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 897 #define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */
Anna Bridge 142:4eea097334d6 898 #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */
Anna Bridge 142:4eea097334d6 899 #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 900 #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 901 #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 902 #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 903 #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 904 #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 905 #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 906 #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 907 #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 908 #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 909 #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 910 #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */
Anna Bridge 142:4eea097334d6 911
Anna Bridge 142:4eea097334d6 912 /* Bit fields for CMU LFECLKSEL */
Anna Bridge 142:4eea097334d6 913 #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 914 #define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 915 #define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */
Anna Bridge 142:4eea097334d6 916 #define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */
Anna Bridge 142:4eea097334d6 917 #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 918 #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 919 #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 920 #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 921 #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 922 #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 923 #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 924 #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 925 #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 926 #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */
Anna Bridge 142:4eea097334d6 927
Anna Bridge 142:4eea097334d6 928 /* Bit fields for CMU STATUS */
Anna Bridge 142:4eea097334d6 929 #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */
Anna Bridge 142:4eea097334d6 930 #define _CMU_STATUS_MASK 0x07E103FFUL /**< Mask for CMU_STATUS */
Anna Bridge 142:4eea097334d6 931 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
Anna Bridge 142:4eea097334d6 932 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
Anna Bridge 142:4eea097334d6 933 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
Anna Bridge 142:4eea097334d6 934 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 935 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 936 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
Anna Bridge 142:4eea097334d6 937 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 938 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 939 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 940 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 941 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
Anna Bridge 142:4eea097334d6 942 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
Anna Bridge 142:4eea097334d6 943 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
Anna Bridge 142:4eea097334d6 944 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 945 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 946 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
Anna Bridge 142:4eea097334d6 947 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 948 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 949 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 950 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 951 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
Anna Bridge 142:4eea097334d6 952 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
Anna Bridge 142:4eea097334d6 953 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
Anna Bridge 142:4eea097334d6 954 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 955 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 956 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
Anna Bridge 142:4eea097334d6 957 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 958 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 959 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 960 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 961 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
Anna Bridge 142:4eea097334d6 962 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
Anna Bridge 142:4eea097334d6 963 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
Anna Bridge 142:4eea097334d6 964 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 965 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 966 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
Anna Bridge 142:4eea097334d6 967 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 968 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 969 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 970 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 971 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
Anna Bridge 142:4eea097334d6 972 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
Anna Bridge 142:4eea097334d6 973 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
Anna Bridge 142:4eea097334d6 974 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 975 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 976 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
Anna Bridge 142:4eea097334d6 977 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 978 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 979 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 980 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 981 #define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */
Anna Bridge 142:4eea097334d6 982 #define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 983 #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 984 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 985 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 986 #define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */
Anna Bridge 142:4eea097334d6 987 #define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */
Anna Bridge 142:4eea097334d6 988 #define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */
Anna Bridge 142:4eea097334d6 989 #define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 990 #define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 991 #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */
Anna Bridge 142:4eea097334d6 992 #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 993 #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 994 #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 995 #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 996 #define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization ready */
Anna Bridge 142:4eea097334d6 997 #define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 998 #define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 999 #define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 1000 #define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 1001 #define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO oscillation amplitude is too high */
Anna Bridge 142:4eea097334d6 1002 #define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */
Anna Bridge 142:4eea097334d6 1003 #define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */
Anna Bridge 142:4eea097334d6 1004 #define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 1005 #define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 1006 #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */
Anna Bridge 142:4eea097334d6 1007 #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */
Anna Bridge 142:4eea097334d6 1008 #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */
Anna Bridge 142:4eea097334d6 1009 #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 1010 #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 1011 #define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO regulator shunt current too low */
Anna Bridge 142:4eea097334d6 1012 #define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */
Anna Bridge 142:4eea097334d6 1013 #define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */
Anna Bridge 142:4eea097334d6 1014 #define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 1015 #define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */
Anna Bridge 142:4eea097334d6 1016
Anna Bridge 142:4eea097334d6 1017 /* Bit fields for CMU HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1018 #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1019 #define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1020 #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */
Anna Bridge 142:4eea097334d6 1021 #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */
Anna Bridge 142:4eea097334d6 1022 #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1023 #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1024 #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1025 #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1026 #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1027 #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1028 #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1029 #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1030 #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1031 #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */
Anna Bridge 142:4eea097334d6 1032
Anna Bridge 142:4eea097334d6 1033 /* Bit fields for CMU HFXOTRIMSTATUS */
Anna Bridge 142:4eea097334d6 1034 #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */
Anna Bridge 142:4eea097334d6 1035 #define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */
Anna Bridge 142:4eea097334d6 1036 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
Anna Bridge 142:4eea097334d6 1037 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
Anna Bridge 142:4eea097334d6 1038 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
Anna Bridge 142:4eea097334d6 1039 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
Anna Bridge 142:4eea097334d6 1040 #define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */
Anna Bridge 142:4eea097334d6 1041 #define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */
Anna Bridge 142:4eea097334d6 1042 #define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
Anna Bridge 142:4eea097334d6 1043 #define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
Anna Bridge 142:4eea097334d6 1044
Anna Bridge 142:4eea097334d6 1045 /* Bit fields for CMU IF */
Anna Bridge 142:4eea097334d6 1046 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
Anna Bridge 142:4eea097334d6 1047 #define _CMU_IF_MASK 0x80007F7FUL /**< Mask for CMU_IF */
Anna Bridge 142:4eea097334d6 1048 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
Anna Bridge 142:4eea097334d6 1049 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 1050 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 1051 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1052 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1053 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
Anna Bridge 142:4eea097334d6 1054 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 1055 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 1056 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1057 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1058 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
Anna Bridge 142:4eea097334d6 1059 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 1060 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 1061 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1062 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1063 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
Anna Bridge 142:4eea097334d6 1064 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 1065 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 1066 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1067 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1068 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
Anna Bridge 142:4eea097334d6 1069 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 1070 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 1071 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1072 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1073 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
Anna Bridge 142:4eea097334d6 1074 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 1075 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 1076 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1077 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1078 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
Anna Bridge 142:4eea097334d6 1079 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Anna Bridge 142:4eea097334d6 1080 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Anna Bridge 142:4eea097334d6 1081 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1082 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1083 #define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */
Anna Bridge 142:4eea097334d6 1084 #define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
Anna Bridge 142:4eea097334d6 1085 #define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
Anna Bridge 142:4eea097334d6 1086 #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1087 #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1088 #define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */
Anna Bridge 142:4eea097334d6 1089 #define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
Anna Bridge 142:4eea097334d6 1090 #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
Anna Bridge 142:4eea097334d6 1091 #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1092 #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1093 #define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */
Anna Bridge 142:4eea097334d6 1094 #define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
Anna Bridge 142:4eea097334d6 1095 #define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
Anna Bridge 142:4eea097334d6 1096 #define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1097 #define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1098 #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */
Anna Bridge 142:4eea097334d6 1099 #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 1100 #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 1101 #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1102 #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1103 #define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */
Anna Bridge 142:4eea097334d6 1104 #define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 1105 #define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 1106 #define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1107 #define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1108 #define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */
Anna Bridge 142:4eea097334d6 1109 #define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 1110 #define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 1111 #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1112 #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1113 #define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */
Anna Bridge 142:4eea097334d6 1114 #define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
Anna Bridge 142:4eea097334d6 1115 #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
Anna Bridge 142:4eea097334d6 1116 #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1117 #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1118 #define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */
Anna Bridge 142:4eea097334d6 1119 #define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
Anna Bridge 142:4eea097334d6 1120 #define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
Anna Bridge 142:4eea097334d6 1121 #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1122 #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */
Anna Bridge 142:4eea097334d6 1123
Anna Bridge 142:4eea097334d6 1124 /* Bit fields for CMU IFS */
Anna Bridge 142:4eea097334d6 1125 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
Anna Bridge 142:4eea097334d6 1126 #define _CMU_IFS_MASK 0x80007F7FUL /**< Mask for CMU_IFS */
Anna Bridge 142:4eea097334d6 1127 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1128 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 1129 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 1130 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1131 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1132 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1133 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 1134 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 1135 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1136 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1137 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1138 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 1139 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 1140 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1141 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1142 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1143 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 1144 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 1145 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1146 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1147 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1148 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 1149 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 1150 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1151 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1152 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1153 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 1154 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 1155 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1156 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1157 #define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */
Anna Bridge 142:4eea097334d6 1158 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Anna Bridge 142:4eea097334d6 1159 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Anna Bridge 142:4eea097334d6 1160 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1161 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1162 #define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */
Anna Bridge 142:4eea097334d6 1163 #define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
Anna Bridge 142:4eea097334d6 1164 #define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
Anna Bridge 142:4eea097334d6 1165 #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1166 #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1167 #define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */
Anna Bridge 142:4eea097334d6 1168 #define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
Anna Bridge 142:4eea097334d6 1169 #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
Anna Bridge 142:4eea097334d6 1170 #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1171 #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1172 #define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */
Anna Bridge 142:4eea097334d6 1173 #define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
Anna Bridge 142:4eea097334d6 1174 #define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
Anna Bridge 142:4eea097334d6 1175 #define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1176 #define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1177 #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1178 #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 1179 #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 1180 #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1181 #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1182 #define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1183 #define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 1184 #define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 1185 #define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1186 #define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1187 #define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */
Anna Bridge 142:4eea097334d6 1188 #define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 1189 #define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 1190 #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1191 #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1192 #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */
Anna Bridge 142:4eea097334d6 1193 #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
Anna Bridge 142:4eea097334d6 1194 #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
Anna Bridge 142:4eea097334d6 1195 #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1196 #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1197 #define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */
Anna Bridge 142:4eea097334d6 1198 #define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
Anna Bridge 142:4eea097334d6 1199 #define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
Anna Bridge 142:4eea097334d6 1200 #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1201 #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */
Anna Bridge 142:4eea097334d6 1202
Anna Bridge 142:4eea097334d6 1203 /* Bit fields for CMU IFC */
Anna Bridge 142:4eea097334d6 1204 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
Anna Bridge 142:4eea097334d6 1205 #define _CMU_IFC_MASK 0x80007F7FUL /**< Mask for CMU_IFC */
Anna Bridge 142:4eea097334d6 1206 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1207 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 1208 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 1209 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1210 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1211 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1212 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 1213 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 1214 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1215 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1216 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1217 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 1218 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 1219 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1220 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1221 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1222 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 1223 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 1224 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1225 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1226 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1227 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 1228 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 1229 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1230 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1231 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1232 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 1233 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 1234 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1235 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1236 #define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */
Anna Bridge 142:4eea097334d6 1237 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Anna Bridge 142:4eea097334d6 1238 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Anna Bridge 142:4eea097334d6 1239 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1240 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1241 #define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */
Anna Bridge 142:4eea097334d6 1242 #define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
Anna Bridge 142:4eea097334d6 1243 #define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
Anna Bridge 142:4eea097334d6 1244 #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1245 #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1246 #define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */
Anna Bridge 142:4eea097334d6 1247 #define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
Anna Bridge 142:4eea097334d6 1248 #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
Anna Bridge 142:4eea097334d6 1249 #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1250 #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1251 #define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */
Anna Bridge 142:4eea097334d6 1252 #define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
Anna Bridge 142:4eea097334d6 1253 #define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
Anna Bridge 142:4eea097334d6 1254 #define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1255 #define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1256 #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1257 #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 1258 #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 1259 #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1260 #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1261 #define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */
Anna Bridge 142:4eea097334d6 1262 #define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 1263 #define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 1264 #define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1265 #define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1266 #define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */
Anna Bridge 142:4eea097334d6 1267 #define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 1268 #define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 1269 #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1270 #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1271 #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */
Anna Bridge 142:4eea097334d6 1272 #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
Anna Bridge 142:4eea097334d6 1273 #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
Anna Bridge 142:4eea097334d6 1274 #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1275 #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1276 #define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */
Anna Bridge 142:4eea097334d6 1277 #define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
Anna Bridge 142:4eea097334d6 1278 #define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
Anna Bridge 142:4eea097334d6 1279 #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1280 #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */
Anna Bridge 142:4eea097334d6 1281
Anna Bridge 142:4eea097334d6 1282 /* Bit fields for CMU IEN */
Anna Bridge 142:4eea097334d6 1283 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
Anna Bridge 142:4eea097334d6 1284 #define _CMU_IEN_MASK 0x80007F7FUL /**< Mask for CMU_IEN */
Anna Bridge 142:4eea097334d6 1285 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */
Anna Bridge 142:4eea097334d6 1286 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 1287 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Anna Bridge 142:4eea097334d6 1288 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1289 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1290 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */
Anna Bridge 142:4eea097334d6 1291 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 1292 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Anna Bridge 142:4eea097334d6 1293 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1294 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1295 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */
Anna Bridge 142:4eea097334d6 1296 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 1297 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Anna Bridge 142:4eea097334d6 1298 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1299 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1300 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */
Anna Bridge 142:4eea097334d6 1301 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 1302 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Anna Bridge 142:4eea097334d6 1303 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1304 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1305 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */
Anna Bridge 142:4eea097334d6 1306 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 1307 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Anna Bridge 142:4eea097334d6 1308 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1309 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1310 #define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */
Anna Bridge 142:4eea097334d6 1311 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 1312 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Anna Bridge 142:4eea097334d6 1313 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1314 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1315 #define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */
Anna Bridge 142:4eea097334d6 1316 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Anna Bridge 142:4eea097334d6 1317 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Anna Bridge 142:4eea097334d6 1318 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1319 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1320 #define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */
Anna Bridge 142:4eea097334d6 1321 #define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
Anna Bridge 142:4eea097334d6 1322 #define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
Anna Bridge 142:4eea097334d6 1323 #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1324 #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1325 #define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */
Anna Bridge 142:4eea097334d6 1326 #define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
Anna Bridge 142:4eea097334d6 1327 #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
Anna Bridge 142:4eea097334d6 1328 #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1329 #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1330 #define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */
Anna Bridge 142:4eea097334d6 1331 #define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
Anna Bridge 142:4eea097334d6 1332 #define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
Anna Bridge 142:4eea097334d6 1333 #define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1334 #define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1335 #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */
Anna Bridge 142:4eea097334d6 1336 #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 1337 #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
Anna Bridge 142:4eea097334d6 1338 #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1339 #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1340 #define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */
Anna Bridge 142:4eea097334d6 1341 #define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 1342 #define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
Anna Bridge 142:4eea097334d6 1343 #define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1344 #define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1345 #define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */
Anna Bridge 142:4eea097334d6 1346 #define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 1347 #define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
Anna Bridge 142:4eea097334d6 1348 #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1349 #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1350 #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */
Anna Bridge 142:4eea097334d6 1351 #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
Anna Bridge 142:4eea097334d6 1352 #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
Anna Bridge 142:4eea097334d6 1353 #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1354 #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1355 #define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */
Anna Bridge 142:4eea097334d6 1356 #define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
Anna Bridge 142:4eea097334d6 1357 #define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
Anna Bridge 142:4eea097334d6 1358 #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1359 #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */
Anna Bridge 142:4eea097334d6 1360
Anna Bridge 142:4eea097334d6 1361 /* Bit fields for CMU HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1362 #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1363 #define _CMU_HFBUSCLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1364 #define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */
Anna Bridge 142:4eea097334d6 1365 #define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */
Anna Bridge 142:4eea097334d6 1366 #define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */
Anna Bridge 142:4eea097334d6 1367 #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1368 #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1369 #define CMU_HFBUSCLKEN0_CRYPTO (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
Anna Bridge 142:4eea097334d6 1370 #define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT 1 /**< Shift value for CMU_CRYPTO */
Anna Bridge 142:4eea097334d6 1371 #define _CMU_HFBUSCLKEN0_CRYPTO_MASK 0x2UL /**< Bit mask for CMU_CRYPTO */
Anna Bridge 142:4eea097334d6 1372 #define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1373 #define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1374 #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 2) /**< General purpose Input/Output Clock Enable */
Anna Bridge 142:4eea097334d6 1375 #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 2 /**< Shift value for CMU_GPIO */
Anna Bridge 142:4eea097334d6 1376 #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x4UL /**< Bit mask for CMU_GPIO */
Anna Bridge 142:4eea097334d6 1377 #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1378 #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1379 #define CMU_HFBUSCLKEN0_PRS (0x1UL << 3) /**< Peripheral Reflex System Clock Enable */
Anna Bridge 142:4eea097334d6 1380 #define _CMU_HFBUSCLKEN0_PRS_SHIFT 3 /**< Shift value for CMU_PRS */
Anna Bridge 142:4eea097334d6 1381 #define _CMU_HFBUSCLKEN0_PRS_MASK 0x8UL /**< Bit mask for CMU_PRS */
Anna Bridge 142:4eea097334d6 1382 #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1383 #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1384 #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 4) /**< Linked Direct Memory Access Controller Clock Enable */
Anna Bridge 142:4eea097334d6 1385 #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 4 /**< Shift value for CMU_LDMA */
Anna Bridge 142:4eea097334d6 1386 #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x10UL /**< Bit mask for CMU_LDMA */
Anna Bridge 142:4eea097334d6 1387 #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1388 #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1389 #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 5) /**< General Purpose CRC Clock Enable */
Anna Bridge 142:4eea097334d6 1390 #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 5 /**< Shift value for CMU_GPCRC */
Anna Bridge 142:4eea097334d6 1391 #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x20UL /**< Bit mask for CMU_GPCRC */
Anna Bridge 142:4eea097334d6 1392 #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1393 #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
Anna Bridge 142:4eea097334d6 1394
Anna Bridge 142:4eea097334d6 1395 /* Bit fields for CMU HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1396 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1397 #define _CMU_HFPERCLKEN0_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1398 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */
Anna Bridge 142:4eea097334d6 1399 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */
Anna Bridge 142:4eea097334d6 1400 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */
Anna Bridge 142:4eea097334d6 1401 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1402 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1403 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */
Anna Bridge 142:4eea097334d6 1404 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */
Anna Bridge 142:4eea097334d6 1405 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */
Anna Bridge 142:4eea097334d6 1406 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1407 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1408 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
Anna Bridge 142:4eea097334d6 1409 #define _CMU_HFPERCLKEN0_USART0_SHIFT 2 /**< Shift value for CMU_USART0 */
Anna Bridge 142:4eea097334d6 1410 #define _CMU_HFPERCLKEN0_USART0_MASK 0x4UL /**< Bit mask for CMU_USART0 */
Anna Bridge 142:4eea097334d6 1411 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1412 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1413 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
Anna Bridge 142:4eea097334d6 1414 #define _CMU_HFPERCLKEN0_USART1_SHIFT 3 /**< Shift value for CMU_USART1 */
Anna Bridge 142:4eea097334d6 1415 #define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL /**< Bit mask for CMU_USART1 */
Anna Bridge 142:4eea097334d6 1416 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1417 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1418 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 4) /**< Analog Comparator 0 Clock Enable */
Anna Bridge 142:4eea097334d6 1419 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 4 /**< Shift value for CMU_ACMP0 */
Anna Bridge 142:4eea097334d6 1420 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x10UL /**< Bit mask for CMU_ACMP0 */
Anna Bridge 142:4eea097334d6 1421 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1422 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1423 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 5) /**< Analog Comparator 1 Clock Enable */
Anna Bridge 142:4eea097334d6 1424 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 5 /**< Shift value for CMU_ACMP1 */
Anna Bridge 142:4eea097334d6 1425 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x20UL /**< Bit mask for CMU_ACMP1 */
Anna Bridge 142:4eea097334d6 1426 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1427 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1428 #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CryoTimer Clock Enable */
Anna Bridge 142:4eea097334d6 1429 #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 6 /**< Shift value for CMU_CRYOTIMER */
Anna Bridge 142:4eea097334d6 1430 #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x40UL /**< Bit mask for CMU_CRYOTIMER */
Anna Bridge 142:4eea097334d6 1431 #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1432 #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1433 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 7) /**< I2C 0 Clock Enable */
Anna Bridge 142:4eea097334d6 1434 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 7 /**< Shift value for CMU_I2C0 */
Anna Bridge 142:4eea097334d6 1435 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x80UL /**< Bit mask for CMU_I2C0 */
Anna Bridge 142:4eea097334d6 1436 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1437 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1438 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 8) /**< Analog to Digital Converter 0 Clock Enable */
Anna Bridge 142:4eea097334d6 1439 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 8 /**< Shift value for CMU_ADC0 */
Anna Bridge 142:4eea097334d6 1440 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x100UL /**< Bit mask for CMU_ADC0 */
Anna Bridge 142:4eea097334d6 1441 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1442 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1443 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 9) /**< Current Digital to Analog Converter 0 Clock Enable */
Anna Bridge 142:4eea097334d6 1444 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 9 /**< Shift value for CMU_IDAC0 */
Anna Bridge 142:4eea097334d6 1445 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x200UL /**< Bit mask for CMU_IDAC0 */
Anna Bridge 142:4eea097334d6 1446 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1447 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Anna Bridge 142:4eea097334d6 1448
Anna Bridge 142:4eea097334d6 1449 /* Bit fields for CMU LFACLKEN0 */
Anna Bridge 142:4eea097334d6 1450 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
Anna Bridge 142:4eea097334d6 1451 #define _CMU_LFACLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFACLKEN0 */
Anna Bridge 142:4eea097334d6 1452 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */
Anna Bridge 142:4eea097334d6 1453 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */
Anna Bridge 142:4eea097334d6 1454 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */
Anna Bridge 142:4eea097334d6 1455 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
Anna Bridge 142:4eea097334d6 1456 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
Anna Bridge 142:4eea097334d6 1457
Anna Bridge 142:4eea097334d6 1458 /* Bit fields for CMU LFBCLKEN0 */
Anna Bridge 142:4eea097334d6 1459 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
Anna Bridge 142:4eea097334d6 1460 #define _CMU_LFBCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFBCLKEN0 */
Anna Bridge 142:4eea097334d6 1461 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
Anna Bridge 142:4eea097334d6 1462 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
Anna Bridge 142:4eea097334d6 1463 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
Anna Bridge 142:4eea097334d6 1464 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
Anna Bridge 142:4eea097334d6 1465 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
Anna Bridge 142:4eea097334d6 1466
Anna Bridge 142:4eea097334d6 1467 /* Bit fields for CMU LFECLKEN0 */
Anna Bridge 142:4eea097334d6 1468 #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */
Anna Bridge 142:4eea097334d6 1469 #define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */
Anna Bridge 142:4eea097334d6 1470 #define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */
Anna Bridge 142:4eea097334d6 1471 #define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */
Anna Bridge 142:4eea097334d6 1472 #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */
Anna Bridge 142:4eea097334d6 1473 #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */
Anna Bridge 142:4eea097334d6 1474 #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */
Anna Bridge 142:4eea097334d6 1475
Anna Bridge 142:4eea097334d6 1476 /* Bit fields for CMU HFPRESC */
Anna Bridge 142:4eea097334d6 1477 #define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1478 #define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1479 #define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
Anna Bridge 142:4eea097334d6 1480 #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */
Anna Bridge 142:4eea097334d6 1481 #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1482 #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1483 #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1484 #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1485 #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */
Anna Bridge 142:4eea097334d6 1486 #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */
Anna Bridge 142:4eea097334d6 1487 #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1488 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1489 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1490 #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1491 #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1492 #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */
Anna Bridge 142:4eea097334d6 1493
Anna Bridge 142:4eea097334d6 1494 /* Bit fields for CMU HFCOREPRESC */
Anna Bridge 142:4eea097334d6 1495 #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */
Anna Bridge 142:4eea097334d6 1496 #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */
Anna Bridge 142:4eea097334d6 1497 #define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
Anna Bridge 142:4eea097334d6 1498 #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */
Anna Bridge 142:4eea097334d6 1499 #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */
Anna Bridge 142:4eea097334d6 1500 #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */
Anna Bridge 142:4eea097334d6 1501 #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */
Anna Bridge 142:4eea097334d6 1502 #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */
Anna Bridge 142:4eea097334d6 1503
Anna Bridge 142:4eea097334d6 1504 /* Bit fields for CMU HFPERPRESC */
Anna Bridge 142:4eea097334d6 1505 #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */
Anna Bridge 142:4eea097334d6 1506 #define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */
Anna Bridge 142:4eea097334d6 1507 #define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
Anna Bridge 142:4eea097334d6 1508 #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */
Anna Bridge 142:4eea097334d6 1509 #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */
Anna Bridge 142:4eea097334d6 1510 #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */
Anna Bridge 142:4eea097334d6 1511 #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */
Anna Bridge 142:4eea097334d6 1512 #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */
Anna Bridge 142:4eea097334d6 1513
Anna Bridge 142:4eea097334d6 1514 /* Bit fields for CMU HFEXPPRESC */
Anna Bridge 142:4eea097334d6 1515 #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */
Anna Bridge 142:4eea097334d6 1516 #define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */
Anna Bridge 142:4eea097334d6 1517 #define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
Anna Bridge 142:4eea097334d6 1518 #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */
Anna Bridge 142:4eea097334d6 1519 #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */
Anna Bridge 142:4eea097334d6 1520 #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */
Anna Bridge 142:4eea097334d6 1521 #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */
Anna Bridge 142:4eea097334d6 1522 #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */
Anna Bridge 142:4eea097334d6 1523
Anna Bridge 142:4eea097334d6 1524 /* Bit fields for CMU LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1525 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1526 #define _CMU_LFAPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1527 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */
Anna Bridge 142:4eea097334d6 1528 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */
Anna Bridge 142:4eea097334d6 1529 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1530 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1531 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1532 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1533 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1534 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1535 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1536 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1537 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1538 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1539 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1540 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1541 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1542 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1543 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1544 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1545 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1546 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1547 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1548 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1549 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1550 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1551 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1552 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1553 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1554 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1555 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1556 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1557 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1558 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1559 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1560 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1561
Anna Bridge 142:4eea097334d6 1562 /* Bit fields for CMU LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1563 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1564 #define _CMU_LFBPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1565 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
Anna Bridge 142:4eea097334d6 1566 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
Anna Bridge 142:4eea097334d6 1567 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1568 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1569 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1570 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1571 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1572 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1573 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1574 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1575
Anna Bridge 142:4eea097334d6 1576 /* Bit fields for CMU LFEPRESC0 */
Anna Bridge 142:4eea097334d6 1577 #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */
Anna Bridge 142:4eea097334d6 1578 #define _CMU_LFEPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFEPRESC0 */
Anna Bridge 142:4eea097334d6 1579 #define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */
Anna Bridge 142:4eea097334d6 1580 #define _CMU_LFEPRESC0_RTCC_MASK 0xFUL /**< Bit mask for CMU_RTCC */
Anna Bridge 142:4eea097334d6 1581 #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */
Anna Bridge 142:4eea097334d6 1582 #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */
Anna Bridge 142:4eea097334d6 1583
Anna Bridge 142:4eea097334d6 1584 /* Bit fields for CMU SYNCBUSY */
Anna Bridge 142:4eea097334d6 1585 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1586 #define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1587 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
Anna Bridge 142:4eea097334d6 1588 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
Anna Bridge 142:4eea097334d6 1589 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
Anna Bridge 142:4eea097334d6 1590 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1591 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1592 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
Anna Bridge 142:4eea097334d6 1593 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1594 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
Anna Bridge 142:4eea097334d6 1595 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1596 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1597 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
Anna Bridge 142:4eea097334d6 1598 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
Anna Bridge 142:4eea097334d6 1599 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
Anna Bridge 142:4eea097334d6 1600 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1601 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1602 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
Anna Bridge 142:4eea097334d6 1603 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1604 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
Anna Bridge 142:4eea097334d6 1605 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1606 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1607 #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */
Anna Bridge 142:4eea097334d6 1608 #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */
Anna Bridge 142:4eea097334d6 1609 #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */
Anna Bridge 142:4eea097334d6 1610 #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1611 #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1612 #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */
Anna Bridge 142:4eea097334d6 1613 #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */
Anna Bridge 142:4eea097334d6 1614 #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */
Anna Bridge 142:4eea097334d6 1615 #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1616 #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1617 #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */
Anna Bridge 142:4eea097334d6 1618 #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */
Anna Bridge 142:4eea097334d6 1619 #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */
Anna Bridge 142:4eea097334d6 1620 #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1621 #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1622 #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */
Anna Bridge 142:4eea097334d6 1623 #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */
Anna Bridge 142:4eea097334d6 1624 #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */
Anna Bridge 142:4eea097334d6 1625 #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1626 #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1627 #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */
Anna Bridge 142:4eea097334d6 1628 #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */
Anna Bridge 142:4eea097334d6 1629 #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */
Anna Bridge 142:4eea097334d6 1630 #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1631 #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1632 #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */
Anna Bridge 142:4eea097334d6 1633 #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */
Anna Bridge 142:4eea097334d6 1634 #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */
Anna Bridge 142:4eea097334d6 1635 #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1636 #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1637 #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */
Anna Bridge 142:4eea097334d6 1638 #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */
Anna Bridge 142:4eea097334d6 1639 #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */
Anna Bridge 142:4eea097334d6 1640 #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1641 #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1642 #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */
Anna Bridge 142:4eea097334d6 1643 #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */
Anna Bridge 142:4eea097334d6 1644 #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */
Anna Bridge 142:4eea097334d6 1645 #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1646 #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Anna Bridge 142:4eea097334d6 1647
Anna Bridge 142:4eea097334d6 1648 /* Bit fields for CMU FREEZE */
Anna Bridge 142:4eea097334d6 1649 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
Anna Bridge 142:4eea097334d6 1650 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
Anna Bridge 142:4eea097334d6 1651 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
Anna Bridge 142:4eea097334d6 1652 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
Anna Bridge 142:4eea097334d6 1653 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
Anna Bridge 142:4eea097334d6 1654 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
Anna Bridge 142:4eea097334d6 1655 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
Anna Bridge 142:4eea097334d6 1656 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
Anna Bridge 142:4eea097334d6 1657 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
Anna Bridge 142:4eea097334d6 1658 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
Anna Bridge 142:4eea097334d6 1659 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
Anna Bridge 142:4eea097334d6 1660
Anna Bridge 142:4eea097334d6 1661 /* Bit fields for CMU PCNTCTRL */
Anna Bridge 142:4eea097334d6 1662 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1663 #define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1664 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
Anna Bridge 142:4eea097334d6 1665 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
Anna Bridge 142:4eea097334d6 1666 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
Anna Bridge 142:4eea097334d6 1667 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1668 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1669 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
Anna Bridge 142:4eea097334d6 1670 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
Anna Bridge 142:4eea097334d6 1671 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
Anna Bridge 142:4eea097334d6 1672 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1673 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1674 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1675 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1676 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1677 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
Anna Bridge 142:4eea097334d6 1678
Anna Bridge 142:4eea097334d6 1679 /* Bit fields for CMU ADCCTRL */
Anna Bridge 142:4eea097334d6 1680 #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1681 #define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1682 #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */
Anna Bridge 142:4eea097334d6 1683 #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */
Anna Bridge 142:4eea097334d6 1684 #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1685 #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1686 #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1687 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1688 #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1689 #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1690 #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1691 #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1692 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1693 #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1694 #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */
Anna Bridge 142:4eea097334d6 1695 #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */
Anna Bridge 142:4eea097334d6 1696 #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */
Anna Bridge 142:4eea097334d6 1697 #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1698 #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */
Anna Bridge 142:4eea097334d6 1699
Anna Bridge 142:4eea097334d6 1700 /* Bit fields for CMU ROUTEPEN */
Anna Bridge 142:4eea097334d6 1701 #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */
Anna Bridge 142:4eea097334d6 1702 #define _CMU_ROUTEPEN_MASK 0x00000003UL /**< Mask for CMU_ROUTEPEN */
Anna Bridge 142:4eea097334d6 1703 #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
Anna Bridge 142:4eea097334d6 1704 #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
Anna Bridge 142:4eea097334d6 1705 #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
Anna Bridge 142:4eea097334d6 1706 #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */
Anna Bridge 142:4eea097334d6 1707 #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
Anna Bridge 142:4eea097334d6 1708 #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
Anna Bridge 142:4eea097334d6 1709 #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
Anna Bridge 142:4eea097334d6 1710 #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
Anna Bridge 142:4eea097334d6 1711 #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */
Anna Bridge 142:4eea097334d6 1712 #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
Anna Bridge 142:4eea097334d6 1713
Anna Bridge 142:4eea097334d6 1714 /* Bit fields for CMU ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1715 #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1716 #define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1717 #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */
Anna Bridge 142:4eea097334d6 1718 #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */
Anna Bridge 142:4eea097334d6 1719 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1720 #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1721 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1722 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1723 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1724 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1725 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1726 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1727 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1728 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1729 #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1730 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1731 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1732 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1733 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1734 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1735 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1736 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1737 #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */
Anna Bridge 142:4eea097334d6 1738 #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */
Anna Bridge 142:4eea097334d6 1739 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1740 #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1741 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1742 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1743 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1744 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1745 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1746 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1747 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1748 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1749 #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1750 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1751 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1752 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1753 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1754 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1755 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1756 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */
Anna Bridge 142:4eea097334d6 1757
Anna Bridge 142:4eea097334d6 1758 /* Bit fields for CMU LOCK */
Anna Bridge 142:4eea097334d6 1759 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1760 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1761 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
Anna Bridge 142:4eea097334d6 1762 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
Anna Bridge 142:4eea097334d6 1763 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1764 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1765 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1766 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1767 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1768 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1769 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1770 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1771 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1772 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
Anna Bridge 142:4eea097334d6 1773
Anna Bridge 142:4eea097334d6 1774 /** @} End of group EFR32MG1P_CMU */
Anna Bridge 142:4eea097334d6 1775 /** @} End of group Parts */
Anna Bridge 142:4eea097334d6 1776