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TARGET_TB_SENSE_1/TOOLCHAIN_IAR/efr32mg1p132f256gj43.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_TB_SENSE_1/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h@142:4eea097334d6 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file efr32mg1p132f256gj43.h
Anna Bridge 142:4eea097334d6 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
Anna Bridge 142:4eea097334d6 4 * for EFR32MG1P132F256GJ43
Anna Bridge 142:4eea097334d6 5 * @version 5.1.2
Anna Bridge 142:4eea097334d6 6 ******************************************************************************
Anna Bridge 142:4eea097334d6 7 * @section License
Anna Bridge 142:4eea097334d6 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
Anna Bridge 142:4eea097334d6 9 ******************************************************************************
Anna Bridge 142:4eea097334d6 10 *
Anna Bridge 142:4eea097334d6 11 * Permission is granted to anyone to use this software for any purpose,
Anna Bridge 142:4eea097334d6 12 * including commercial applications, and to alter it and redistribute it
Anna Bridge 142:4eea097334d6 13 * freely, subject to the following restrictions:
Anna Bridge 142:4eea097334d6 14 *
Anna Bridge 142:4eea097334d6 15 * 1. The origin of this software must not be misrepresented; you must not
Anna Bridge 142:4eea097334d6 16 * claim that you wrote the original software.@n
Anna Bridge 142:4eea097334d6 17 * 2. Altered source versions must be plainly marked as such, and must not be
Anna Bridge 142:4eea097334d6 18 * misrepresented as being the original software.@n
Anna Bridge 142:4eea097334d6 19 * 3. This notice may not be removed or altered from any source distribution.
Anna Bridge 142:4eea097334d6 20 *
Anna Bridge 142:4eea097334d6 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Anna Bridge 142:4eea097334d6 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Anna Bridge 142:4eea097334d6 23 * providing the Software "AS IS", with no express or implied warranties of any
Anna Bridge 142:4eea097334d6 24 * kind, including, but not limited to, any implied warranties of
Anna Bridge 142:4eea097334d6 25 * merchantability or fitness for any particular purpose or warranties against
Anna Bridge 142:4eea097334d6 26 * infringement of any proprietary rights of a third party.
Anna Bridge 142:4eea097334d6 27 *
Anna Bridge 142:4eea097334d6 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
Anna Bridge 142:4eea097334d6 29 * incidental, or special damages, or any other relief, or for any claim by
Anna Bridge 142:4eea097334d6 30 * any third party, arising from your use of this Software.
Anna Bridge 142:4eea097334d6 31 *
Anna Bridge 142:4eea097334d6 32 *****************************************************************************/
Anna Bridge 142:4eea097334d6 33
Anna Bridge 142:4eea097334d6 34 #ifndef EFR32MG1P132F256GJ43_H
Anna Bridge 142:4eea097334d6 35 #define EFR32MG1P132F256GJ43_H
Anna Bridge 142:4eea097334d6 36
Anna Bridge 142:4eea097334d6 37 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 38 extern "C" {
Anna Bridge 142:4eea097334d6 39 #endif
Anna Bridge 142:4eea097334d6 40
Anna Bridge 142:4eea097334d6 41 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 42 * @addtogroup Parts
Anna Bridge 142:4eea097334d6 43 * @{
Anna Bridge 142:4eea097334d6 44 *****************************************************************************/
Anna Bridge 142:4eea097334d6 45
Anna Bridge 142:4eea097334d6 46 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 47 * @defgroup EFR32MG1P132F256GJ43 EFR32MG1P132F256GJ43
Anna Bridge 142:4eea097334d6 48 * @{
Anna Bridge 142:4eea097334d6 49 *****************************************************************************/
Anna Bridge 142:4eea097334d6 50
Anna Bridge 142:4eea097334d6 51 /** Interrupt Number Definition */
Anna Bridge 142:4eea097334d6 52 typedef enum IRQn
Anna Bridge 142:4eea097334d6 53 {
Anna Bridge 142:4eea097334d6 54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
Anna Bridge 142:4eea097334d6 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
Anna Bridge 142:4eea097334d6 56 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
Anna Bridge 142:4eea097334d6 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
Anna Bridge 142:4eea097334d6 58 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
Anna Bridge 142:4eea097334d6 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
Anna Bridge 142:4eea097334d6 60 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
Anna Bridge 142:4eea097334d6 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
Anna Bridge 142:4eea097334d6 62 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
Anna Bridge 142:4eea097334d6 63 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
Anna Bridge 142:4eea097334d6 64
Anna Bridge 142:4eea097334d6 65 /****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
Anna Bridge 142:4eea097334d6 66
Anna Bridge 142:4eea097334d6 67 EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
Anna Bridge 142:4eea097334d6 68 WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
Anna Bridge 142:4eea097334d6 69 LDMA_IRQn = 8, /*!< 8 EFR32 LDMA Interrupt */
Anna Bridge 142:4eea097334d6 70 GPIO_EVEN_IRQn = 9, /*!< 9 EFR32 GPIO_EVEN Interrupt */
Anna Bridge 142:4eea097334d6 71 TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */
Anna Bridge 142:4eea097334d6 72 USART0_RX_IRQn = 11, /*!< 11 EFR32 USART0_RX Interrupt */
Anna Bridge 142:4eea097334d6 73 USART0_TX_IRQn = 12, /*!< 12 EFR32 USART0_TX Interrupt */
Anna Bridge 142:4eea097334d6 74 ACMP0_IRQn = 13, /*!< 13 EFR32 ACMP0 Interrupt */
Anna Bridge 142:4eea097334d6 75 ADC0_IRQn = 14, /*!< 14 EFR32 ADC0 Interrupt */
Anna Bridge 142:4eea097334d6 76 IDAC0_IRQn = 15, /*!< 15 EFR32 IDAC0 Interrupt */
Anna Bridge 142:4eea097334d6 77 I2C0_IRQn = 16, /*!< 16 EFR32 I2C0 Interrupt */
Anna Bridge 142:4eea097334d6 78 GPIO_ODD_IRQn = 17, /*!< 17 EFR32 GPIO_ODD Interrupt */
Anna Bridge 142:4eea097334d6 79 TIMER1_IRQn = 18, /*!< 18 EFR32 TIMER1 Interrupt */
Anna Bridge 142:4eea097334d6 80 USART1_RX_IRQn = 19, /*!< 19 EFR32 USART1_RX Interrupt */
Anna Bridge 142:4eea097334d6 81 USART1_TX_IRQn = 20, /*!< 20 EFR32 USART1_TX Interrupt */
Anna Bridge 142:4eea097334d6 82 LEUART0_IRQn = 21, /*!< 21 EFR32 LEUART0 Interrupt */
Anna Bridge 142:4eea097334d6 83 PCNT0_IRQn = 22, /*!< 22 EFR32 PCNT0 Interrupt */
Anna Bridge 142:4eea097334d6 84 CMU_IRQn = 23, /*!< 23 EFR32 CMU Interrupt */
Anna Bridge 142:4eea097334d6 85 MSC_IRQn = 24, /*!< 24 EFR32 MSC Interrupt */
Anna Bridge 142:4eea097334d6 86 CRYPTO_IRQn = 25, /*!< 25 EFR32 CRYPTO Interrupt */
Anna Bridge 142:4eea097334d6 87 LETIMER0_IRQn = 26, /*!< 26 EFR32 LETIMER0 Interrupt */
Anna Bridge 142:4eea097334d6 88 RTCC_IRQn = 29, /*!< 29 EFR32 RTCC Interrupt */
Anna Bridge 142:4eea097334d6 89 CRYOTIMER_IRQn = 31, /*!< 31 EFR32 CRYOTIMER Interrupt */
Anna Bridge 142:4eea097334d6 90 FPUEH_IRQn = 33, /*!< 33 EFR32 FPUEH Interrupt */
Anna Bridge 142:4eea097334d6 91 } IRQn_Type;
Anna Bridge 142:4eea097334d6 92
Anna Bridge 142:4eea097334d6 93 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 94 * @defgroup EFR32MG1P132F256GJ43_Core EFR32MG1P132F256GJ43 Core
Anna Bridge 142:4eea097334d6 95 * @{
Anna Bridge 142:4eea097334d6 96 * @brief Processor and Core Peripheral Section
Anna Bridge 142:4eea097334d6 97 *****************************************************************************/
Anna Bridge 142:4eea097334d6 98 #define __MPU_PRESENT 1 /**< Presence of MPU */
Anna Bridge 142:4eea097334d6 99 #define __FPU_PRESENT 1 /**< Presence of FPU */
Anna Bridge 142:4eea097334d6 100 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
Anna Bridge 142:4eea097334d6 101 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
Anna Bridge 142:4eea097334d6 102 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
Anna Bridge 142:4eea097334d6 103
Anna Bridge 142:4eea097334d6 104 /** @} End of group EFR32MG1P132F256GJ43_Core */
Anna Bridge 142:4eea097334d6 105
Anna Bridge 142:4eea097334d6 106 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 107 * @defgroup EFR32MG1P132F256GJ43_Part EFR32MG1P132F256GJ43 Part
Anna Bridge 142:4eea097334d6 108 * @{
Anna Bridge 142:4eea097334d6 109 ******************************************************************************/
Anna Bridge 142:4eea097334d6 110
Anna Bridge 142:4eea097334d6 111 /** Part family */
Anna Bridge 142:4eea097334d6 112 #define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
Anna Bridge 142:4eea097334d6 113 #define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
Anna Bridge 142:4eea097334d6 114 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
Anna Bridge 142:4eea097334d6 115 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
Anna Bridge 142:4eea097334d6 116 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
Anna Bridge 142:4eea097334d6 117 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
Anna Bridge 142:4eea097334d6 118 #define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */
Anna Bridge 142:4eea097334d6 119 #define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */
Anna Bridge 142:4eea097334d6 120 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
Anna Bridge 142:4eea097334d6 121 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
Anna Bridge 142:4eea097334d6 122 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
Anna Bridge 142:4eea097334d6 123 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ
Anna Bridge 142:4eea097334d6 124 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
Anna Bridge 142:4eea097334d6 125 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
Anna Bridge 142:4eea097334d6 126 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
Anna Bridge 142:4eea097334d6 127 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
Anna Bridge 142:4eea097334d6 128
Anna Bridge 142:4eea097334d6 129 /* If part number is not defined as compiler option, define it */
Anna Bridge 142:4eea097334d6 130 #if !defined(EFR32MG1P132F256GJ43)
Anna Bridge 142:4eea097334d6 131 #define EFR32MG1P132F256GJ43 1 /**< MIGHTY Gecko Part */
Anna Bridge 142:4eea097334d6 132 #endif
Anna Bridge 142:4eea097334d6 133
Anna Bridge 142:4eea097334d6 134 /** Configure part number */
Anna Bridge 142:4eea097334d6 135 #define PART_NUMBER "EFR32MG1P132F256GJ43" /**< Part Number */
Anna Bridge 142:4eea097334d6 136
Anna Bridge 142:4eea097334d6 137 /** Memory Base addresses and limits */
Anna Bridge 142:4eea097334d6 138 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
Anna Bridge 142:4eea097334d6 139 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
Anna Bridge 142:4eea097334d6 140 #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
Anna Bridge 142:4eea097334d6 141 #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
Anna Bridge 142:4eea097334d6 142 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
Anna Bridge 142:4eea097334d6 143 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
Anna Bridge 142:4eea097334d6 144 #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
Anna Bridge 142:4eea097334d6 145 #define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */
Anna Bridge 142:4eea097334d6 146 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
Anna Bridge 142:4eea097334d6 147 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
Anna Bridge 142:4eea097334d6 148 #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
Anna Bridge 142:4eea097334d6 149 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
Anna Bridge 142:4eea097334d6 150 #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
Anna Bridge 142:4eea097334d6 151 #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
Anna Bridge 142:4eea097334d6 152 #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
Anna Bridge 142:4eea097334d6 153 #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */
Anna Bridge 142:4eea097334d6 154 #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
Anna Bridge 142:4eea097334d6 155 #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
Anna Bridge 142:4eea097334d6 156 #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
Anna Bridge 142:4eea097334d6 157 #define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */
Anna Bridge 142:4eea097334d6 158 #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
Anna Bridge 142:4eea097334d6 159 #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
Anna Bridge 142:4eea097334d6 160 #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
Anna Bridge 142:4eea097334d6 161 #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */
Anna Bridge 142:4eea097334d6 162 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
Anna Bridge 142:4eea097334d6 163 #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
Anna Bridge 142:4eea097334d6 164 #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
Anna Bridge 142:4eea097334d6 165 #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
Anna Bridge 142:4eea097334d6 166 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
Anna Bridge 142:4eea097334d6 167 #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
Anna Bridge 142:4eea097334d6 168 #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
Anna Bridge 142:4eea097334d6 169 #define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
Anna Bridge 142:4eea097334d6 170 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
Anna Bridge 142:4eea097334d6 171 #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
Anna Bridge 142:4eea097334d6 172 #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
Anna Bridge 142:4eea097334d6 173 #define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
Anna Bridge 142:4eea097334d6 174
Anna Bridge 142:4eea097334d6 175 /** Bit banding area */
Anna Bridge 142:4eea097334d6 176 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
Anna Bridge 142:4eea097334d6 177 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
Anna Bridge 142:4eea097334d6 178
Anna Bridge 142:4eea097334d6 179 /** Flash and SRAM limits for EFR32MG1P132F256GJ43 */
Anna Bridge 142:4eea097334d6 180 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
Anna Bridge 142:4eea097334d6 181 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
Anna Bridge 142:4eea097334d6 182 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
Anna Bridge 142:4eea097334d6 183 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
Anna Bridge 142:4eea097334d6 184 #define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
Anna Bridge 142:4eea097334d6 185 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
Anna Bridge 142:4eea097334d6 186 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
Anna Bridge 142:4eea097334d6 187 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
Anna Bridge 142:4eea097334d6 188 #define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
Anna Bridge 142:4eea097334d6 189
Anna Bridge 142:4eea097334d6 190 /** AF channels connect the different on-chip peripherals with the af-mux */
Anna Bridge 142:4eea097334d6 191 #define AFCHAN_MAX 72
Anna Bridge 142:4eea097334d6 192 #define AFCHANLOC_MAX 32
Anna Bridge 142:4eea097334d6 193 /** Analog AF channels */
Anna Bridge 142:4eea097334d6 194 #define AFACHAN_MAX 61
Anna Bridge 142:4eea097334d6 195
Anna Bridge 142:4eea097334d6 196 /* Part number capabilities */
Anna Bridge 142:4eea097334d6 197
Anna Bridge 142:4eea097334d6 198 #define TIMER_PRESENT /**< TIMER is available in this part */
Anna Bridge 142:4eea097334d6 199 #define TIMER_COUNT 2 /**< 2 TIMERs available */
Anna Bridge 142:4eea097334d6 200 #define USART_PRESENT /**< USART is available in this part */
Anna Bridge 142:4eea097334d6 201 #define USART_COUNT 2 /**< 2 USARTs available */
Anna Bridge 142:4eea097334d6 202 #define LEUART_PRESENT /**< LEUART is available in this part */
Anna Bridge 142:4eea097334d6 203 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
Anna Bridge 142:4eea097334d6 204 #define LETIMER_PRESENT /**< LETIMER is available in this part */
Anna Bridge 142:4eea097334d6 205 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
Anna Bridge 142:4eea097334d6 206 #define PCNT_PRESENT /**< PCNT is available in this part */
Anna Bridge 142:4eea097334d6 207 #define PCNT_COUNT 1 /**< 1 PCNTs available */
Anna Bridge 142:4eea097334d6 208 #define I2C_PRESENT /**< I2C is available in this part */
Anna Bridge 142:4eea097334d6 209 #define I2C_COUNT 1 /**< 1 I2Cs available */
Anna Bridge 142:4eea097334d6 210 #define ADC_PRESENT /**< ADC is available in this part */
Anna Bridge 142:4eea097334d6 211 #define ADC_COUNT 1 /**< 1 ADCs available */
Anna Bridge 142:4eea097334d6 212 #define ACMP_PRESENT /**< ACMP is available in this part */
Anna Bridge 142:4eea097334d6 213 #define ACMP_COUNT 2 /**< 2 ACMPs available */
Anna Bridge 142:4eea097334d6 214 #define IDAC_PRESENT /**< IDAC is available in this part */
Anna Bridge 142:4eea097334d6 215 #define IDAC_COUNT 1 /**< 1 IDACs available */
Anna Bridge 142:4eea097334d6 216 #define WDOG_PRESENT /**< WDOG is available in this part */
Anna Bridge 142:4eea097334d6 217 #define WDOG_COUNT 1 /**< 1 WDOGs available */
Anna Bridge 142:4eea097334d6 218 #define MSC_PRESENT
Anna Bridge 142:4eea097334d6 219 #define MSC_COUNT 1
Anna Bridge 142:4eea097334d6 220 #define EMU_PRESENT
Anna Bridge 142:4eea097334d6 221 #define EMU_COUNT 1
Anna Bridge 142:4eea097334d6 222 #define RMU_PRESENT
Anna Bridge 142:4eea097334d6 223 #define RMU_COUNT 1
Anna Bridge 142:4eea097334d6 224 #define CMU_PRESENT
Anna Bridge 142:4eea097334d6 225 #define CMU_COUNT 1
Anna Bridge 142:4eea097334d6 226 #define CRYPTO_PRESENT
Anna Bridge 142:4eea097334d6 227 #define CRYPTO_COUNT 1
Anna Bridge 142:4eea097334d6 228 #define GPIO_PRESENT
Anna Bridge 142:4eea097334d6 229 #define GPIO_COUNT 1
Anna Bridge 142:4eea097334d6 230 #define PRS_PRESENT
Anna Bridge 142:4eea097334d6 231 #define PRS_COUNT 1
Anna Bridge 142:4eea097334d6 232 #define LDMA_PRESENT
Anna Bridge 142:4eea097334d6 233 #define LDMA_COUNT 1
Anna Bridge 142:4eea097334d6 234 #define FPUEH_PRESENT
Anna Bridge 142:4eea097334d6 235 #define FPUEH_COUNT 1
Anna Bridge 142:4eea097334d6 236 #define GPCRC_PRESENT
Anna Bridge 142:4eea097334d6 237 #define GPCRC_COUNT 1
Anna Bridge 142:4eea097334d6 238 #define CRYOTIMER_PRESENT
Anna Bridge 142:4eea097334d6 239 #define CRYOTIMER_COUNT 1
Anna Bridge 142:4eea097334d6 240 #define RTCC_PRESENT
Anna Bridge 142:4eea097334d6 241 #define RTCC_COUNT 1
Anna Bridge 142:4eea097334d6 242 #define BOOTLOADER_PRESENT
Anna Bridge 142:4eea097334d6 243 #define BOOTLOADER_COUNT 1
Anna Bridge 142:4eea097334d6 244
Anna Bridge 142:4eea097334d6 245 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Anna Bridge 142:4eea097334d6 246 #include "system_efr32mg1p.h" /* System Header File */
Anna Bridge 142:4eea097334d6 247
Anna Bridge 142:4eea097334d6 248 /** @} End of group EFR32MG1P132F256GJ43_Part */
Anna Bridge 142:4eea097334d6 249
Anna Bridge 142:4eea097334d6 250 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 251 * @defgroup EFR32MG1P132F256GJ43_Peripheral_TypeDefs EFR32MG1P132F256GJ43 Peripheral TypeDefs
Anna Bridge 142:4eea097334d6 252 * @{
Anna Bridge 142:4eea097334d6 253 * @brief Device Specific Peripheral Register Structures
Anna Bridge 142:4eea097334d6 254 *****************************************************************************/
Anna Bridge 142:4eea097334d6 255
Anna Bridge 142:4eea097334d6 256 #include "efr32mg1p_msc.h"
Anna Bridge 142:4eea097334d6 257 #include "efr32mg1p_emu.h"
Anna Bridge 142:4eea097334d6 258 #include "efr32mg1p_rmu.h"
Anna Bridge 142:4eea097334d6 259 #include "efr32mg1p_cmu.h"
Anna Bridge 142:4eea097334d6 260 #include "efr32mg1p_crypto.h"
Anna Bridge 142:4eea097334d6 261 #include "efr32mg1p_gpio_p.h"
Anna Bridge 142:4eea097334d6 262 #include "efr32mg1p_gpio.h"
Anna Bridge 142:4eea097334d6 263 #include "efr32mg1p_prs_ch.h"
Anna Bridge 142:4eea097334d6 264 #include "efr32mg1p_prs.h"
Anna Bridge 142:4eea097334d6 265 #include "efr32mg1p_ldma_ch.h"
Anna Bridge 142:4eea097334d6 266 #include "efr32mg1p_ldma.h"
Anna Bridge 142:4eea097334d6 267 #include "efr32mg1p_fpueh.h"
Anna Bridge 142:4eea097334d6 268 #include "efr32mg1p_gpcrc.h"
Anna Bridge 142:4eea097334d6 269 #include "efr32mg1p_timer_cc.h"
Anna Bridge 142:4eea097334d6 270 #include "efr32mg1p_timer.h"
Anna Bridge 142:4eea097334d6 271 #include "efr32mg1p_usart.h"
Anna Bridge 142:4eea097334d6 272 #include "efr32mg1p_leuart.h"
Anna Bridge 142:4eea097334d6 273 #include "efr32mg1p_letimer.h"
Anna Bridge 142:4eea097334d6 274 #include "efr32mg1p_cryotimer.h"
Anna Bridge 142:4eea097334d6 275 #include "efr32mg1p_pcnt.h"
Anna Bridge 142:4eea097334d6 276 #include "efr32mg1p_i2c.h"
Anna Bridge 142:4eea097334d6 277 #include "efr32mg1p_adc.h"
Anna Bridge 142:4eea097334d6 278 #include "efr32mg1p_acmp.h"
Anna Bridge 142:4eea097334d6 279 #include "efr32mg1p_idac.h"
Anna Bridge 142:4eea097334d6 280 #include "efr32mg1p_rtcc_cc.h"
Anna Bridge 142:4eea097334d6 281 #include "efr32mg1p_rtcc_ret.h"
Anna Bridge 142:4eea097334d6 282 #include "efr32mg1p_rtcc.h"
Anna Bridge 142:4eea097334d6 283 #include "efr32mg1p_wdog_pch.h"
Anna Bridge 142:4eea097334d6 284 #include "efr32mg1p_wdog.h"
Anna Bridge 142:4eea097334d6 285 #include "efr32mg1p_dma_descriptor.h"
Anna Bridge 142:4eea097334d6 286 #include "efr32mg1p_devinfo.h"
Anna Bridge 142:4eea097334d6 287 #include "efr32mg1p_romtable.h"
Anna Bridge 142:4eea097334d6 288
Anna Bridge 142:4eea097334d6 289 /** @} End of group EFR32MG1P132F256GJ43_Peripheral_TypeDefs */
Anna Bridge 142:4eea097334d6 290
Anna Bridge 142:4eea097334d6 291 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 292 * @defgroup EFR32MG1P132F256GJ43_Peripheral_Base EFR32MG1P132F256GJ43 Peripheral Memory Map
Anna Bridge 142:4eea097334d6 293 * @{
Anna Bridge 142:4eea097334d6 294 *****************************************************************************/
Anna Bridge 142:4eea097334d6 295
Anna Bridge 142:4eea097334d6 296 #define MSC_BASE (0x400E0000UL) /**< MSC base address */
Anna Bridge 142:4eea097334d6 297 #define EMU_BASE (0x400E3000UL) /**< EMU base address */
Anna Bridge 142:4eea097334d6 298 #define RMU_BASE (0x400E5000UL) /**< RMU base address */
Anna Bridge 142:4eea097334d6 299 #define CMU_BASE (0x400E4000UL) /**< CMU base address */
Anna Bridge 142:4eea097334d6 300 #define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
Anna Bridge 142:4eea097334d6 301 #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
Anna Bridge 142:4eea097334d6 302 #define PRS_BASE (0x400E6000UL) /**< PRS base address */
Anna Bridge 142:4eea097334d6 303 #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
Anna Bridge 142:4eea097334d6 304 #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
Anna Bridge 142:4eea097334d6 305 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
Anna Bridge 142:4eea097334d6 306 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
Anna Bridge 142:4eea097334d6 307 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
Anna Bridge 142:4eea097334d6 308 #define USART0_BASE (0x40010000UL) /**< USART0 base address */
Anna Bridge 142:4eea097334d6 309 #define USART1_BASE (0x40010400UL) /**< USART1 base address */
Anna Bridge 142:4eea097334d6 310 #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
Anna Bridge 142:4eea097334d6 311 #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
Anna Bridge 142:4eea097334d6 312 #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
Anna Bridge 142:4eea097334d6 313 #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
Anna Bridge 142:4eea097334d6 314 #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
Anna Bridge 142:4eea097334d6 315 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
Anna Bridge 142:4eea097334d6 316 #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
Anna Bridge 142:4eea097334d6 317 #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
Anna Bridge 142:4eea097334d6 318 #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
Anna Bridge 142:4eea097334d6 319 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */
Anna Bridge 142:4eea097334d6 320 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
Anna Bridge 142:4eea097334d6 321 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
Anna Bridge 142:4eea097334d6 322 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
Anna Bridge 142:4eea097334d6 323 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
Anna Bridge 142:4eea097334d6 324 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
Anna Bridge 142:4eea097334d6 325
Anna Bridge 142:4eea097334d6 326 /** @} End of group EFR32MG1P132F256GJ43_Peripheral_Base */
Anna Bridge 142:4eea097334d6 327
Anna Bridge 142:4eea097334d6 328 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 329 * @defgroup EFR32MG1P132F256GJ43_Peripheral_Declaration EFR32MG1P132F256GJ43 Peripheral Declarations
Anna Bridge 142:4eea097334d6 330 * @{
Anna Bridge 142:4eea097334d6 331 *****************************************************************************/
Anna Bridge 142:4eea097334d6 332
Anna Bridge 142:4eea097334d6 333 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
Anna Bridge 142:4eea097334d6 334 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
Anna Bridge 142:4eea097334d6 335 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
Anna Bridge 142:4eea097334d6 336 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
Anna Bridge 142:4eea097334d6 337 #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
Anna Bridge 142:4eea097334d6 338 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
Anna Bridge 142:4eea097334d6 339 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
Anna Bridge 142:4eea097334d6 340 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
Anna Bridge 142:4eea097334d6 341 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
Anna Bridge 142:4eea097334d6 342 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
Anna Bridge 142:4eea097334d6 343 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
Anna Bridge 142:4eea097334d6 344 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
Anna Bridge 142:4eea097334d6 345 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
Anna Bridge 142:4eea097334d6 346 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
Anna Bridge 142:4eea097334d6 347 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
Anna Bridge 142:4eea097334d6 348 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
Anna Bridge 142:4eea097334d6 349 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
Anna Bridge 142:4eea097334d6 350 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
Anna Bridge 142:4eea097334d6 351 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
Anna Bridge 142:4eea097334d6 352 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
Anna Bridge 142:4eea097334d6 353 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
Anna Bridge 142:4eea097334d6 354 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
Anna Bridge 142:4eea097334d6 355 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
Anna Bridge 142:4eea097334d6 356 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
Anna Bridge 142:4eea097334d6 357 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
Anna Bridge 142:4eea097334d6 358 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
Anna Bridge 142:4eea097334d6 359 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
Anna Bridge 142:4eea097334d6 360
Anna Bridge 142:4eea097334d6 361 /** @} End of group EFR32MG1P132F256GJ43_Peripheral_Declaration */
Anna Bridge 142:4eea097334d6 362
Anna Bridge 142:4eea097334d6 363 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 364 * @defgroup EFR32MG1P132F256GJ43_Peripheral_Offsets EFR32MG1P132F256GJ43 Peripheral Offsets
Anna Bridge 142:4eea097334d6 365 * @{
Anna Bridge 142:4eea097334d6 366 *****************************************************************************/
Anna Bridge 142:4eea097334d6 367
Anna Bridge 142:4eea097334d6 368 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
Anna Bridge 142:4eea097334d6 369 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
Anna Bridge 142:4eea097334d6 370 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
Anna Bridge 142:4eea097334d6 371 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
Anna Bridge 142:4eea097334d6 372 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
Anna Bridge 142:4eea097334d6 373 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
Anna Bridge 142:4eea097334d6 374 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
Anna Bridge 142:4eea097334d6 375 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
Anna Bridge 142:4eea097334d6 376 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
Anna Bridge 142:4eea097334d6 377 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
Anna Bridge 142:4eea097334d6 378
Anna Bridge 142:4eea097334d6 379 /** @} End of group EFR32MG1P132F256GJ43_Peripheral_Offsets */
Anna Bridge 142:4eea097334d6 380
Anna Bridge 142:4eea097334d6 381
Anna Bridge 142:4eea097334d6 382 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 383 * @defgroup EFR32MG1P132F256GJ43_BitFields EFR32MG1P132F256GJ43 Bit Fields
Anna Bridge 142:4eea097334d6 384 * @{
Anna Bridge 142:4eea097334d6 385 *****************************************************************************/
Anna Bridge 142:4eea097334d6 386
Anna Bridge 142:4eea097334d6 387 #include "efr32mg1p_prs_signals.h"
Anna Bridge 142:4eea097334d6 388 #include "efr32mg1p_dmareq.h"
Anna Bridge 142:4eea097334d6 389
Anna Bridge 142:4eea097334d6 390 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 391 * @defgroup EFR32MG1P132F256GJ43_UNLOCK EFR32MG1P132F256GJ43 Unlock Codes
Anna Bridge 142:4eea097334d6 392 * @{
Anna Bridge 142:4eea097334d6 393 *****************************************************************************/
Anna Bridge 142:4eea097334d6 394 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
Anna Bridge 142:4eea097334d6 395 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
Anna Bridge 142:4eea097334d6 396 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
Anna Bridge 142:4eea097334d6 397 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
Anna Bridge 142:4eea097334d6 398 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
Anna Bridge 142:4eea097334d6 399 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
Anna Bridge 142:4eea097334d6 400 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
Anna Bridge 142:4eea097334d6 401
Anna Bridge 142:4eea097334d6 402 /** @} End of group EFR32MG1P132F256GJ43_UNLOCK */
Anna Bridge 142:4eea097334d6 403
Anna Bridge 142:4eea097334d6 404 /** @} End of group EFR32MG1P132F256GJ43_BitFields */
Anna Bridge 142:4eea097334d6 405
Anna Bridge 142:4eea097334d6 406 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 407 * @defgroup EFR32MG1P132F256GJ43_Alternate_Function EFR32MG1P132F256GJ43 Alternate Function
Anna Bridge 142:4eea097334d6 408 * @{
Anna Bridge 142:4eea097334d6 409 *****************************************************************************/
Anna Bridge 142:4eea097334d6 410
Anna Bridge 142:4eea097334d6 411 #include "efr32mg1p_af_ports.h"
Anna Bridge 142:4eea097334d6 412 #include "efr32mg1p_af_pins.h"
Anna Bridge 142:4eea097334d6 413
Anna Bridge 142:4eea097334d6 414 /** @} End of group EFR32MG1P132F256GJ43_Alternate_Function */
Anna Bridge 142:4eea097334d6 415
Anna Bridge 142:4eea097334d6 416 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 417 * @brief Set the value of a bit field within a register.
Anna Bridge 142:4eea097334d6 418 *
Anna Bridge 142:4eea097334d6 419 * @param REG
Anna Bridge 142:4eea097334d6 420 * The register to update
Anna Bridge 142:4eea097334d6 421 * @param MASK
Anna Bridge 142:4eea097334d6 422 * The mask for the bit field to update
Anna Bridge 142:4eea097334d6 423 * @param VALUE
Anna Bridge 142:4eea097334d6 424 * The value to write to the bit field
Anna Bridge 142:4eea097334d6 425 * @param OFFSET
Anna Bridge 142:4eea097334d6 426 * The number of bits that the field is offset within the register.
Anna Bridge 142:4eea097334d6 427 * 0 (zero) means LSB.
Anna Bridge 142:4eea097334d6 428 *****************************************************************************/
Anna Bridge 142:4eea097334d6 429 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
Anna Bridge 142:4eea097334d6 430 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Anna Bridge 142:4eea097334d6 431
Anna Bridge 142:4eea097334d6 432 /** @} End of group EFR32MG1P132F256GJ43 */
Anna Bridge 142:4eea097334d6 433
Anna Bridge 142:4eea097334d6 434 /** @} End of group Parts */
Anna Bridge 142:4eea097334d6 435
Anna Bridge 142:4eea097334d6 436 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 437 }
Anna Bridge 142:4eea097334d6 438 #endif
Anna Bridge 142:4eea097334d6 439 #endif /* EFR32MG1P132F256GJ43_H */