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TARGET_TB_SENSE_1/TOOLCHAIN_ARM_STD/efr32mg1p_msc.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_TB_SENSE_1/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h@142:4eea097334d6
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg1p_msc.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG1P_MSC register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG1P_MSC |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG1P_MSC Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IOM uint32_t CTRL; /**< Memory System Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IOM uint32_t READCTRL; /**< Read Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | __IOM uint32_t WRITECTRL; /**< Write Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 46 | __IOM uint32_t WRITECMD; /**< Write Command Register */ |
| Anna Bridge |
142:4eea097334d6 | 47 | __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ |
| Anna Bridge |
142:4eea097334d6 | 48 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 49 | __IOM uint32_t WDATA; /**< Write Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 50 | __IM uint32_t STATUS; /**< Status Register */ |
| Anna Bridge |
142:4eea097334d6 | 51 | |
| Anna Bridge |
142:4eea097334d6 | 52 | uint32_t RESERVED1[4]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 53 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| Anna Bridge |
142:4eea097334d6 | 55 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 56 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| Anna Bridge |
142:4eea097334d6 | 57 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
| Anna Bridge |
142:4eea097334d6 | 58 | __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ |
| Anna Bridge |
142:4eea097334d6 | 59 | __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ |
| Anna Bridge |
142:4eea097334d6 | 60 | __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ |
| Anna Bridge |
142:4eea097334d6 | 61 | |
| Anna Bridge |
142:4eea097334d6 | 62 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 63 | __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ |
| Anna Bridge |
142:4eea097334d6 | 64 | |
| Anna Bridge |
142:4eea097334d6 | 65 | uint32_t RESERVED3[1]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 66 | __IOM uint32_t STARTUP; /**< Startup Control */ |
| Anna Bridge |
142:4eea097334d6 | 67 | |
| Anna Bridge |
142:4eea097334d6 | 68 | uint32_t RESERVED4[5]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 69 | __IOM uint32_t CMD; /**< Command Register */ |
| Anna Bridge |
142:4eea097334d6 | 70 | } MSC_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 71 | |
| Anna Bridge |
142:4eea097334d6 | 72 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 73 | * @defgroup EFR32MG1P_MSC_BitFields |
| Anna Bridge |
142:4eea097334d6 | 74 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 75 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 76 | |
| Anna Bridge |
142:4eea097334d6 | 77 | /* Bit fields for MSC CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define _MSC_CTRL_MASK 0x0000000FUL /**< Mask for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ |
| Anna Bridge |
142:4eea097334d6 | 86 | #define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ |
| Anna Bridge |
142:4eea097334d6 | 87 | #define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ |
| Anna Bridge |
142:4eea097334d6 | 88 | #define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 100 | |
| Anna Bridge |
142:4eea097334d6 | 101 | /* Bit fields for MSC READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ |
| Anna Bridge |
142:4eea097334d6 | 116 | #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ |
| Anna Bridge |
142:4eea097334d6 | 117 | #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ |
| Anna Bridge |
142:4eea097334d6 | 121 | #define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ |
| Anna Bridge |
142:4eea097334d6 | 122 | #define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 124 | #define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ |
| Anna Bridge |
142:4eea097334d6 | 125 | #define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 132 | #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 133 | #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ |
| Anna Bridge |
142:4eea097334d6 | 140 | #define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 141 | #define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| Anna Bridge |
142:4eea097334d6 | 142 | |
| Anna Bridge |
142:4eea097334d6 | 143 | /* Bit fields for MSC WRITECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ |
| Anna Bridge |
142:4eea097334d6 | 156 | |
| Anna Bridge |
142:4eea097334d6 | 157 | /* Bit fields for MSC WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 159 | #define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ |
| Anna Bridge |
142:4eea097334d6 | 167 | #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 174 | #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 175 | #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ |
| Anna Bridge |
142:4eea097334d6 | 177 | #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ |
| Anna Bridge |
142:4eea097334d6 | 178 | #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 179 | #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 180 | #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ |
| Anna Bridge |
142:4eea097334d6 | 181 | #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ |
| Anna Bridge |
142:4eea097334d6 | 182 | #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ |
| Anna Bridge |
142:4eea097334d6 | 183 | #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 184 | #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 185 | #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ |
| Anna Bridge |
142:4eea097334d6 | 186 | #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ |
| Anna Bridge |
142:4eea097334d6 | 187 | #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ |
| Anna Bridge |
142:4eea097334d6 | 188 | #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| Anna Bridge |
142:4eea097334d6 | 189 | #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
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142:4eea097334d6 | 190 | #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ |
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142:4eea097334d6 | 191 | #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ |
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142:4eea097334d6 | 192 | #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ |
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142:4eea097334d6 | 193 | #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
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142:4eea097334d6 | 194 | #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
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142:4eea097334d6 | 195 | #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ |
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142:4eea097334d6 | 196 | #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ |
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142:4eea097334d6 | 197 | #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ |
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142:4eea097334d6 | 198 | #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
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142:4eea097334d6 | 199 | #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
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142:4eea097334d6 | 200 | |
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142:4eea097334d6 | 201 | /* Bit fields for MSC ADDRB */ |
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142:4eea097334d6 | 202 | #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ |
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142:4eea097334d6 | 203 | #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ |
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142:4eea097334d6 | 204 | #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ |
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142:4eea097334d6 | 205 | #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ |
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142:4eea097334d6 | 206 | #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ |
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142:4eea097334d6 | 207 | #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ |
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142:4eea097334d6 | 208 | |
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142:4eea097334d6 | 209 | /* Bit fields for MSC WDATA */ |
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142:4eea097334d6 | 210 | #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ |
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142:4eea097334d6 | 211 | #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ |
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142:4eea097334d6 | 212 | #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ |
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142:4eea097334d6 | 213 | #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ |
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142:4eea097334d6 | 214 | #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ |
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142:4eea097334d6 | 215 | #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ |
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142:4eea097334d6 | 216 | |
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142:4eea097334d6 | 217 | /* Bit fields for MSC STATUS */ |
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142:4eea097334d6 | 218 | #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ |
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142:4eea097334d6 | 219 | #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */ |
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142:4eea097334d6 | 220 | #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ |
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142:4eea097334d6 | 221 | #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ |
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142:4eea097334d6 | 222 | #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ |
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142:4eea097334d6 | 223 | #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 224 | #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 225 | #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ |
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142:4eea097334d6 | 226 | #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ |
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142:4eea097334d6 | 227 | #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ |
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142:4eea097334d6 | 228 | #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 229 | #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 230 | #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ |
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142:4eea097334d6 | 231 | #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ |
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142:4eea097334d6 | 232 | #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ |
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142:4eea097334d6 | 233 | #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 234 | #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 235 | #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ |
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142:4eea097334d6 | 236 | #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ |
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142:4eea097334d6 | 237 | #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ |
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142:4eea097334d6 | 238 | #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 239 | #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 240 | #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ |
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142:4eea097334d6 | 241 | #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ |
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142:4eea097334d6 | 242 | #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ |
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142:4eea097334d6 | 243 | #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 244 | #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 245 | #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ |
| Anna Bridge |
142:4eea097334d6 | 246 | #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ |
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142:4eea097334d6 | 247 | #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ |
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142:4eea097334d6 | 248 | #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 249 | #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 250 | #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ |
| Anna Bridge |
142:4eea097334d6 | 251 | #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ |
| Anna Bridge |
142:4eea097334d6 | 252 | #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ |
| Anna Bridge |
142:4eea097334d6 | 253 | #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 254 | #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ |
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142:4eea097334d6 | 255 | |
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142:4eea097334d6 | 256 | /* Bit fields for MSC IF */ |
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142:4eea097334d6 | 257 | #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ |
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142:4eea097334d6 | 258 | #define _MSC_IF_MASK 0x0000003FUL /**< Mask for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 259 | #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ |
| Anna Bridge |
142:4eea097334d6 | 260 | #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ |
| Anna Bridge |
142:4eea097334d6 | 261 | #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ |
| Anna Bridge |
142:4eea097334d6 | 262 | #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 263 | #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 264 | #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ |
| Anna Bridge |
142:4eea097334d6 | 265 | #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ |
| Anna Bridge |
142:4eea097334d6 | 266 | #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ |
| Anna Bridge |
142:4eea097334d6 | 267 | #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 268 | #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 269 | #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 270 | #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ |
| Anna Bridge |
142:4eea097334d6 | 271 | #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ |
| Anna Bridge |
142:4eea097334d6 | 272 | #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 273 | #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ |
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142:4eea097334d6 | 274 | #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 275 | #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ |
| Anna Bridge |
142:4eea097334d6 | 276 | #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ |
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142:4eea097334d6 | 277 | #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 278 | #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ |
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142:4eea097334d6 | 279 | #define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ |
| Anna Bridge |
142:4eea097334d6 | 280 | #define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ |
| Anna Bridge |
142:4eea097334d6 | 281 | #define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ |
| Anna Bridge |
142:4eea097334d6 | 282 | #define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 283 | #define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ |
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142:4eea097334d6 | 284 | #define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */ |
| Anna Bridge |
142:4eea097334d6 | 285 | #define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ |
| Anna Bridge |
142:4eea097334d6 | 286 | #define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ |
| Anna Bridge |
142:4eea097334d6 | 287 | #define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 288 | #define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ |
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142:4eea097334d6 | 289 | |
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142:4eea097334d6 | 290 | /* Bit fields for MSC IFS */ |
| Anna Bridge |
142:4eea097334d6 | 291 | #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 292 | #define _MSC_IFS_MASK 0x0000003FUL /**< Mask for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 293 | #define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 294 | #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ |
| Anna Bridge |
142:4eea097334d6 | 295 | #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ |
| Anna Bridge |
142:4eea097334d6 | 296 | #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 297 | #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 298 | #define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 299 | #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ |
| Anna Bridge |
142:4eea097334d6 | 300 | #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ |
| Anna Bridge |
142:4eea097334d6 | 301 | #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 302 | #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 303 | #define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 304 | #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ |
| Anna Bridge |
142:4eea097334d6 | 305 | #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ |
| Anna Bridge |
142:4eea097334d6 | 306 | #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 307 | #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 308 | #define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 309 | #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ |
| Anna Bridge |
142:4eea097334d6 | 310 | #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ |
| Anna Bridge |
142:4eea097334d6 | 311 | #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 312 | #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 313 | #define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 314 | #define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ |
| Anna Bridge |
142:4eea097334d6 | 315 | #define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ |
| Anna Bridge |
142:4eea097334d6 | 316 | #define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 317 | #define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 318 | #define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 319 | #define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ |
| Anna Bridge |
142:4eea097334d6 | 320 | #define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ |
| Anna Bridge |
142:4eea097334d6 | 321 | #define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 322 | #define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 323 | |
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142:4eea097334d6 | 324 | /* Bit fields for MSC IFC */ |
| Anna Bridge |
142:4eea097334d6 | 325 | #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 326 | #define _MSC_IFC_MASK 0x0000003FUL /**< Mask for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 327 | #define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 328 | #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ |
| Anna Bridge |
142:4eea097334d6 | 329 | #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ |
| Anna Bridge |
142:4eea097334d6 | 330 | #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 331 | #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 332 | #define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 333 | #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ |
| Anna Bridge |
142:4eea097334d6 | 334 | #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ |
| Anna Bridge |
142:4eea097334d6 | 335 | #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 336 | #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 337 | #define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 338 | #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ |
| Anna Bridge |
142:4eea097334d6 | 339 | #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ |
| Anna Bridge |
142:4eea097334d6 | 340 | #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 341 | #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 342 | #define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 343 | #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ |
| Anna Bridge |
142:4eea097334d6 | 344 | #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ |
| Anna Bridge |
142:4eea097334d6 | 345 | #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 346 | #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 347 | #define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 348 | #define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ |
| Anna Bridge |
142:4eea097334d6 | 349 | #define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ |
| Anna Bridge |
142:4eea097334d6 | 350 | #define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 351 | #define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 352 | #define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 353 | #define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ |
| Anna Bridge |
142:4eea097334d6 | 354 | #define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ |
| Anna Bridge |
142:4eea097334d6 | 355 | #define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 356 | #define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 357 | |
| Anna Bridge |
142:4eea097334d6 | 358 | /* Bit fields for MSC IEN */ |
| Anna Bridge |
142:4eea097334d6 | 359 | #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 360 | #define _MSC_IEN_MASK 0x0000003FUL /**< Mask for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 361 | #define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 362 | #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ |
| Anna Bridge |
142:4eea097334d6 | 363 | #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ |
| Anna Bridge |
142:4eea097334d6 | 364 | #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 365 | #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 366 | #define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 367 | #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ |
| Anna Bridge |
142:4eea097334d6 | 368 | #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ |
| Anna Bridge |
142:4eea097334d6 | 369 | #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 370 | #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 371 | #define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 372 | #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ |
| Anna Bridge |
142:4eea097334d6 | 373 | #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ |
| Anna Bridge |
142:4eea097334d6 | 374 | #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 375 | #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 376 | #define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 377 | #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ |
| Anna Bridge |
142:4eea097334d6 | 378 | #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ |
| Anna Bridge |
142:4eea097334d6 | 379 | #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 380 | #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 381 | #define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 382 | #define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ |
| Anna Bridge |
142:4eea097334d6 | 383 | #define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ |
| Anna Bridge |
142:4eea097334d6 | 384 | #define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 385 | #define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 386 | #define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 387 | #define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ |
| Anna Bridge |
142:4eea097334d6 | 388 | #define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ |
| Anna Bridge |
142:4eea097334d6 | 389 | #define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 390 | #define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 391 | |
| Anna Bridge |
142:4eea097334d6 | 392 | /* Bit fields for MSC LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 393 | #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 394 | #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 395 | #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ |
| Anna Bridge |
142:4eea097334d6 | 396 | #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ |
| Anna Bridge |
142:4eea097334d6 | 397 | #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 398 | #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 399 | #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 400 | #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 401 | #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 402 | #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 403 | #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 404 | #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 405 | #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 406 | #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 407 | |
| Anna Bridge |
142:4eea097334d6 | 408 | /* Bit fields for MSC CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 409 | #define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 410 | #define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 411 | #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ |
| Anna Bridge |
142:4eea097334d6 | 412 | #define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ |
| Anna Bridge |
142:4eea097334d6 | 413 | #define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ |
| Anna Bridge |
142:4eea097334d6 | 414 | #define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 415 | #define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 416 | #define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ |
| Anna Bridge |
142:4eea097334d6 | 417 | #define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ |
| Anna Bridge |
142:4eea097334d6 | 418 | #define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ |
| Anna Bridge |
142:4eea097334d6 | 419 | #define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 420 | #define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 421 | #define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ |
| Anna Bridge |
142:4eea097334d6 | 422 | #define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ |
| Anna Bridge |
142:4eea097334d6 | 423 | #define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ |
| Anna Bridge |
142:4eea097334d6 | 424 | #define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 425 | #define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ |
| Anna Bridge |
142:4eea097334d6 | 426 | |
| Anna Bridge |
142:4eea097334d6 | 427 | /* Bit fields for MSC CACHEHITS */ |
| Anna Bridge |
142:4eea097334d6 | 428 | #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ |
| Anna Bridge |
142:4eea097334d6 | 429 | #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ |
| Anna Bridge |
142:4eea097334d6 | 430 | #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ |
| Anna Bridge |
142:4eea097334d6 | 431 | #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ |
| Anna Bridge |
142:4eea097334d6 | 432 | #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ |
| Anna Bridge |
142:4eea097334d6 | 433 | #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ |
| Anna Bridge |
142:4eea097334d6 | 434 | |
| Anna Bridge |
142:4eea097334d6 | 435 | /* Bit fields for MSC CACHEMISSES */ |
| Anna Bridge |
142:4eea097334d6 | 436 | #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ |
| Anna Bridge |
142:4eea097334d6 | 437 | #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ |
| Anna Bridge |
142:4eea097334d6 | 438 | #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ |
| Anna Bridge |
142:4eea097334d6 | 439 | #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ |
| Anna Bridge |
142:4eea097334d6 | 440 | #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ |
| Anna Bridge |
142:4eea097334d6 | 441 | #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ |
| Anna Bridge |
142:4eea097334d6 | 442 | |
| Anna Bridge |
142:4eea097334d6 | 443 | /* Bit fields for MSC MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 444 | #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 445 | #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 446 | #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ |
| Anna Bridge |
142:4eea097334d6 | 447 | #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ |
| Anna Bridge |
142:4eea097334d6 | 448 | #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 449 | #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 450 | #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 451 | #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 452 | #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 453 | #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 454 | #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 455 | #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 456 | #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 457 | #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ |
| Anna Bridge |
142:4eea097334d6 | 458 | |
| Anna Bridge |
142:4eea097334d6 | 459 | /* Bit fields for MSC STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 460 | #define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 461 | #define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 462 | #define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ |
| Anna Bridge |
142:4eea097334d6 | 463 | #define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ |
| Anna Bridge |
142:4eea097334d6 | 464 | #define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 465 | #define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 466 | #define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ |
| Anna Bridge |
142:4eea097334d6 | 467 | #define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ |
| Anna Bridge |
142:4eea097334d6 | 468 | #define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 469 | #define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 470 | #define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ |
| Anna Bridge |
142:4eea097334d6 | 471 | #define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ |
| Anna Bridge |
142:4eea097334d6 | 472 | #define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ |
| Anna Bridge |
142:4eea097334d6 | 473 | #define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 474 | #define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 475 | #define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ |
| Anna Bridge |
142:4eea097334d6 | 476 | #define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ |
| Anna Bridge |
142:4eea097334d6 | 477 | #define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ |
| Anna Bridge |
142:4eea097334d6 | 478 | #define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 479 | #define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 480 | #define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ |
| Anna Bridge |
142:4eea097334d6 | 481 | #define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ |
| Anna Bridge |
142:4eea097334d6 | 482 | #define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ |
| Anna Bridge |
142:4eea097334d6 | 483 | #define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 484 | #define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 485 | #define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ |
| Anna Bridge |
142:4eea097334d6 | 486 | #define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ |
| Anna Bridge |
142:4eea097334d6 | 487 | #define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 488 | #define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ |
| Anna Bridge |
142:4eea097334d6 | 489 | |
| Anna Bridge |
142:4eea097334d6 | 490 | /* Bit fields for MSC CMD */ |
| Anna Bridge |
142:4eea097334d6 | 491 | #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 492 | #define _MSC_CMD_MASK 0x00000001UL /**< Mask for MSC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 493 | #define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ |
| Anna Bridge |
142:4eea097334d6 | 494 | #define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ |
| Anna Bridge |
142:4eea097334d6 | 495 | #define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ |
| Anna Bridge |
142:4eea097334d6 | 496 | #define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 497 | #define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 498 | |
| Anna Bridge |
142:4eea097334d6 | 499 | /** @} End of group EFR32MG1P_MSC */ |
| Anna Bridge |
142:4eea097334d6 | 500 | /** @} End of group Parts */ |
| Anna Bridge |
142:4eea097334d6 | 501 |
