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TARGET_TB_SENSE_1/TOOLCHAIN_ARM_STD/efr32mg1p_i2c.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_TB_SENSE_1/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h@142:4eea097334d6
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg1p_i2c.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG1P_I2C register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG1P_I2C |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG1P_I2C Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IOM uint32_t CMD; /**< Command Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | __IM uint32_t STATE; /**< State Register */ |
| Anna Bridge |
142:4eea097334d6 | 46 | __IM uint32_t STATUS; /**< Status Register */ |
| Anna Bridge |
142:4eea097334d6 | 47 | __IOM uint32_t CLKDIV; /**< Clock Division Register */ |
| Anna Bridge |
142:4eea097334d6 | 48 | __IOM uint32_t SADDR; /**< Slave Address Register */ |
| Anna Bridge |
142:4eea097334d6 | 49 | __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */ |
| Anna Bridge |
142:4eea097334d6 | 50 | __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 51 | __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 52 | __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ |
| Anna Bridge |
142:4eea097334d6 | 53 | __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 55 | __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 56 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| Anna Bridge |
142:4eea097334d6 | 57 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| Anna Bridge |
142:4eea097334d6 | 58 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 59 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| Anna Bridge |
142:4eea097334d6 | 60 | __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ |
| Anna Bridge |
142:4eea097334d6 | 61 | __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ |
| Anna Bridge |
142:4eea097334d6 | 62 | } I2C_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 63 | |
| Anna Bridge |
142:4eea097334d6 | 64 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 65 | * @defgroup EFR32MG1P_I2C_BitFields |
| Anna Bridge |
142:4eea097334d6 | 66 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 67 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 68 | |
| Anna Bridge |
142:4eea097334d6 | 69 | /* Bit fields for I2C CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 70 | #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 71 | #define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 72 | #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ |
| Anna Bridge |
142:4eea097334d6 | 73 | #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ |
| Anna Bridge |
142:4eea097334d6 | 74 | #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ |
| Anna Bridge |
142:4eea097334d6 | 75 | #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 76 | #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 77 | #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 86 | #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 87 | #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ |
| Anna Bridge |
142:4eea097334d6 | 88 | #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ |
| Anna Bridge |
142:4eea097334d6 | 100 | #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 101 | #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 116 | #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ |
| Anna Bridge |
142:4eea097334d6 | 117 | #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 121 | #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 122 | #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 124 | #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 125 | #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 132 | #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 133 | #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ |
| Anna Bridge |
142:4eea097334d6 | 140 | #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ |
| Anna Bridge |
142:4eea097334d6 | 141 | #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 142 | #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 156 | #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 157 | #define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 159 | |
| Anna Bridge |
142:4eea097334d6 | 160 | /* Bit fields for I2C CMD */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 167 | #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ |
| Anna Bridge |
142:4eea097334d6 | 174 | #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ |
| Anna Bridge |
142:4eea097334d6 | 175 | #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 177 | #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 178 | #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ |
| Anna Bridge |
142:4eea097334d6 | 179 | #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ |
| Anna Bridge |
142:4eea097334d6 | 180 | #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ |
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142:4eea097334d6 | 181 | #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 182 | #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 183 | #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ |
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142:4eea097334d6 | 184 | #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ |
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142:4eea097334d6 | 185 | #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ |
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142:4eea097334d6 | 186 | #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 187 | #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 188 | #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ |
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142:4eea097334d6 | 189 | #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ |
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142:4eea097334d6 | 190 | #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ |
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142:4eea097334d6 | 191 | #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 192 | #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 193 | #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ |
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142:4eea097334d6 | 194 | #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ |
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142:4eea097334d6 | 195 | #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ |
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142:4eea097334d6 | 196 | #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 197 | #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 198 | #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ |
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142:4eea097334d6 | 199 | #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ |
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142:4eea097334d6 | 200 | #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ |
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142:4eea097334d6 | 201 | #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 202 | #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ |
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142:4eea097334d6 | 203 | |
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142:4eea097334d6 | 204 | /* Bit fields for I2C STATE */ |
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142:4eea097334d6 | 205 | #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ |
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142:4eea097334d6 | 206 | #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ |
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142:4eea097334d6 | 207 | #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ |
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142:4eea097334d6 | 208 | #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ |
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142:4eea097334d6 | 209 | #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ |
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142:4eea097334d6 | 210 | #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 211 | #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 212 | #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ |
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142:4eea097334d6 | 213 | #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ |
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142:4eea097334d6 | 214 | #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ |
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142:4eea097334d6 | 215 | #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 216 | #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 217 | #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ |
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142:4eea097334d6 | 218 | #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ |
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142:4eea097334d6 | 219 | #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ |
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142:4eea097334d6 | 220 | #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 221 | #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 222 | #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ |
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142:4eea097334d6 | 223 | #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ |
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142:4eea097334d6 | 224 | #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ |
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142:4eea097334d6 | 225 | #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 226 | #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 227 | #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ |
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142:4eea097334d6 | 228 | #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ |
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142:4eea097334d6 | 229 | #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ |
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142:4eea097334d6 | 230 | #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 231 | #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 232 | #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ |
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142:4eea097334d6 | 233 | #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ |
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142:4eea097334d6 | 234 | #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 235 | #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ |
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142:4eea097334d6 | 236 | #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ |
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142:4eea097334d6 | 237 | #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ |
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142:4eea097334d6 | 238 | #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ |
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142:4eea097334d6 | 239 | #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ |
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142:4eea097334d6 | 240 | #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ |
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142:4eea097334d6 | 241 | #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ |
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142:4eea097334d6 | 242 | #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ |
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142:4eea097334d6 | 243 | #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ |
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142:4eea097334d6 | 244 | #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ |
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142:4eea097334d6 | 245 | #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ |
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142:4eea097334d6 | 246 | #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ |
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142:4eea097334d6 | 247 | #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ |
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142:4eea097334d6 | 248 | #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ |
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142:4eea097334d6 | 249 | #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ |
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142:4eea097334d6 | 250 | |
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142:4eea097334d6 | 251 | /* Bit fields for I2C STATUS */ |
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142:4eea097334d6 | 252 | #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ |
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142:4eea097334d6 | 253 | #define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */ |
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142:4eea097334d6 | 254 | #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ |
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142:4eea097334d6 | 255 | #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ |
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142:4eea097334d6 | 256 | #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ |
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142:4eea097334d6 | 257 | #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 258 | #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 259 | #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ |
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142:4eea097334d6 | 260 | #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ |
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142:4eea097334d6 | 261 | #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ |
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142:4eea097334d6 | 262 | #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 263 | #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 264 | #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ |
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142:4eea097334d6 | 265 | #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ |
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142:4eea097334d6 | 266 | #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ |
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142:4eea097334d6 | 267 | #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 268 | #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 269 | #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ |
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142:4eea097334d6 | 270 | #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ |
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142:4eea097334d6 | 271 | #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ |
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142:4eea097334d6 | 272 | #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 273 | #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 274 | #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ |
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142:4eea097334d6 | 275 | #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ |
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142:4eea097334d6 | 276 | #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ |
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142:4eea097334d6 | 277 | #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 278 | #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 279 | #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ |
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142:4eea097334d6 | 280 | #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ |
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142:4eea097334d6 | 281 | #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ |
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142:4eea097334d6 | 282 | #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 283 | #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 284 | #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ |
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142:4eea097334d6 | 285 | #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ |
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142:4eea097334d6 | 286 | #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ |
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142:4eea097334d6 | 287 | #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 288 | #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 289 | #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ |
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142:4eea097334d6 | 290 | #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ |
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142:4eea097334d6 | 291 | #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ |
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142:4eea097334d6 | 292 | #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 293 | #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 294 | #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ |
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142:4eea097334d6 | 295 | #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ |
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142:4eea097334d6 | 296 | #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ |
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142:4eea097334d6 | 297 | #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 298 | #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 299 | #define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ |
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142:4eea097334d6 | 300 | #define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ |
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142:4eea097334d6 | 301 | #define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ |
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142:4eea097334d6 | 302 | #define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 303 | #define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ |
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142:4eea097334d6 | 304 | |
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142:4eea097334d6 | 305 | /* Bit fields for I2C CLKDIV */ |
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142:4eea097334d6 | 306 | #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ |
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142:4eea097334d6 | 307 | #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ |
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142:4eea097334d6 | 308 | #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ |
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142:4eea097334d6 | 309 | #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ |
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142:4eea097334d6 | 310 | #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ |
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142:4eea097334d6 | 311 | #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ |
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142:4eea097334d6 | 312 | |
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142:4eea097334d6 | 313 | /* Bit fields for I2C SADDR */ |
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142:4eea097334d6 | 314 | #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ |
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142:4eea097334d6 | 315 | #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ |
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142:4eea097334d6 | 316 | #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ |
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142:4eea097334d6 | 317 | #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ |
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142:4eea097334d6 | 318 | #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ |
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142:4eea097334d6 | 319 | #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ |
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142:4eea097334d6 | 320 | |
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142:4eea097334d6 | 321 | /* Bit fields for I2C SADDRMASK */ |
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142:4eea097334d6 | 322 | #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ |
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142:4eea097334d6 | 323 | #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ |
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142:4eea097334d6 | 324 | #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ |
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142:4eea097334d6 | 325 | #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ |
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142:4eea097334d6 | 326 | #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ |
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142:4eea097334d6 | 327 | #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ |
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142:4eea097334d6 | 328 | |
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142:4eea097334d6 | 329 | /* Bit fields for I2C RXDATA */ |
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142:4eea097334d6 | 330 | #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ |
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142:4eea097334d6 | 331 | #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ |
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142:4eea097334d6 | 332 | #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ |
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142:4eea097334d6 | 333 | #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ |
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142:4eea097334d6 | 334 | #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ |
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142:4eea097334d6 | 335 | #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ |
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142:4eea097334d6 | 336 | |
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142:4eea097334d6 | 337 | /* Bit fields for I2C RXDOUBLE */ |
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142:4eea097334d6 | 338 | #define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ |
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142:4eea097334d6 | 339 | #define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ |
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142:4eea097334d6 | 340 | #define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ |
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142:4eea097334d6 | 341 | #define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ |
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142:4eea097334d6 | 342 | #define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ |
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142:4eea097334d6 | 343 | #define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ |
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142:4eea097334d6 | 344 | #define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ |
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142:4eea097334d6 | 345 | #define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ |
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142:4eea097334d6 | 346 | #define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ |
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142:4eea097334d6 | 347 | #define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ |
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142:4eea097334d6 | 348 | |
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142:4eea097334d6 | 349 | /* Bit fields for I2C RXDATAP */ |
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142:4eea097334d6 | 350 | #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ |
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142:4eea097334d6 | 351 | #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ |
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142:4eea097334d6 | 352 | #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ |
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142:4eea097334d6 | 353 | #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ |
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142:4eea097334d6 | 354 | #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ |
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142:4eea097334d6 | 355 | #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ |
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142:4eea097334d6 | 356 | |
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142:4eea097334d6 | 357 | /* Bit fields for I2C RXDOUBLEP */ |
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142:4eea097334d6 | 358 | #define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ |
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142:4eea097334d6 | 359 | #define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ |
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142:4eea097334d6 | 360 | #define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ |
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142:4eea097334d6 | 361 | #define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ |
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142:4eea097334d6 | 362 | #define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ |
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142:4eea097334d6 | 363 | #define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ |
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142:4eea097334d6 | 364 | #define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ |
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142:4eea097334d6 | 365 | #define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ |
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142:4eea097334d6 | 366 | #define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ |
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142:4eea097334d6 | 367 | #define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ |
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142:4eea097334d6 | 368 | |
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142:4eea097334d6 | 369 | /* Bit fields for I2C TXDATA */ |
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142:4eea097334d6 | 370 | #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ |
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142:4eea097334d6 | 371 | #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ |
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142:4eea097334d6 | 372 | #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ |
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142:4eea097334d6 | 373 | #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ |
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142:4eea097334d6 | 374 | #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ |
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142:4eea097334d6 | 375 | #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ |
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142:4eea097334d6 | 376 | |
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142:4eea097334d6 | 377 | /* Bit fields for I2C TXDOUBLE */ |
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142:4eea097334d6 | 378 | #define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ |
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142:4eea097334d6 | 379 | #define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ |
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142:4eea097334d6 | 380 | #define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ |
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142:4eea097334d6 | 381 | #define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ |
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142:4eea097334d6 | 382 | #define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ |
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142:4eea097334d6 | 383 | #define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ |
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142:4eea097334d6 | 384 | #define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ |
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142:4eea097334d6 | 385 | #define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ |
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142:4eea097334d6 | 386 | #define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ |
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142:4eea097334d6 | 387 | #define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ |
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142:4eea097334d6 | 388 | |
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142:4eea097334d6 | 389 | /* Bit fields for I2C IF */ |
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142:4eea097334d6 | 390 | #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ |
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142:4eea097334d6 | 391 | #define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */ |
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142:4eea097334d6 | 392 | #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ |
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142:4eea097334d6 | 393 | #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ |
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142:4eea097334d6 | 394 | #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
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142:4eea097334d6 | 395 | #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 396 | #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 397 | #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ |
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142:4eea097334d6 | 398 | #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ |
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142:4eea097334d6 | 399 | #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ |
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142:4eea097334d6 | 400 | #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 401 | #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 402 | #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ |
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142:4eea097334d6 | 403 | #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ |
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142:4eea097334d6 | 404 | #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ |
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142:4eea097334d6 | 405 | #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 406 | #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 407 | #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ |
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142:4eea097334d6 | 408 | #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ |
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142:4eea097334d6 | 409 | #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ |
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142:4eea097334d6 | 410 | #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 411 | #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 412 | #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ |
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142:4eea097334d6 | 413 | #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ |
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142:4eea097334d6 | 414 | #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ |
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142:4eea097334d6 | 415 | #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 416 | #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 417 | #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ |
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142:4eea097334d6 | 418 | #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ |
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142:4eea097334d6 | 419 | #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ |
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142:4eea097334d6 | 420 | #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 421 | #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 422 | #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ |
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142:4eea097334d6 | 423 | #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ |
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142:4eea097334d6 | 424 | #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ |
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142:4eea097334d6 | 425 | #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 426 | #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 427 | #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ |
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142:4eea097334d6 | 428 | #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ |
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142:4eea097334d6 | 429 | #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ |
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142:4eea097334d6 | 430 | #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 431 | #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 432 | #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ |
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142:4eea097334d6 | 433 | #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ |
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142:4eea097334d6 | 434 | #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ |
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142:4eea097334d6 | 435 | #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 436 | #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 437 | #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ |
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142:4eea097334d6 | 438 | #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ |
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142:4eea097334d6 | 439 | #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ |
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142:4eea097334d6 | 440 | #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 441 | #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 442 | #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ |
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142:4eea097334d6 | 443 | #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ |
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142:4eea097334d6 | 444 | #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ |
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142:4eea097334d6 | 445 | #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 446 | #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 447 | #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ |
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142:4eea097334d6 | 448 | #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ |
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142:4eea097334d6 | 449 | #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ |
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142:4eea097334d6 | 450 | #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 451 | #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 452 | #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ |
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142:4eea097334d6 | 453 | #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ |
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142:4eea097334d6 | 454 | #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ |
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142:4eea097334d6 | 455 | #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 456 | #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 457 | #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ |
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142:4eea097334d6 | 458 | #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ |
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142:4eea097334d6 | 459 | #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ |
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142:4eea097334d6 | 460 | #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 461 | #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 462 | #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ |
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142:4eea097334d6 | 463 | #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ |
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142:4eea097334d6 | 464 | #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ |
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142:4eea097334d6 | 465 | #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 466 | #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 467 | #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ |
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142:4eea097334d6 | 468 | #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ |
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142:4eea097334d6 | 469 | #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ |
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142:4eea097334d6 | 470 | #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 471 | #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 472 | #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */ |
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142:4eea097334d6 | 473 | #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ |
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142:4eea097334d6 | 474 | #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ |
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142:4eea097334d6 | 475 | #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 476 | #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 477 | #define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ |
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142:4eea097334d6 | 478 | #define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ |
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142:4eea097334d6 | 479 | #define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ |
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142:4eea097334d6 | 480 | #define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 481 | #define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 482 | #define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ |
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142:4eea097334d6 | 483 | #define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ |
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142:4eea097334d6 | 484 | #define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ |
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142:4eea097334d6 | 485 | #define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 486 | #define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ |
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142:4eea097334d6 | 487 | |
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142:4eea097334d6 | 488 | /* Bit fields for I2C IFS */ |
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142:4eea097334d6 | 489 | #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ |
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142:4eea097334d6 | 490 | #define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */ |
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142:4eea097334d6 | 491 | #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ |
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142:4eea097334d6 | 492 | #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ |
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142:4eea097334d6 | 493 | #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
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142:4eea097334d6 | 494 | #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 495 | #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 496 | #define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */ |
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142:4eea097334d6 | 497 | #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ |
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142:4eea097334d6 | 498 | #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ |
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142:4eea097334d6 | 499 | #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 500 | #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 501 | #define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */ |
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142:4eea097334d6 | 502 | #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ |
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142:4eea097334d6 | 503 | #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ |
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142:4eea097334d6 | 504 | #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 505 | #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 506 | #define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */ |
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142:4eea097334d6 | 507 | #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ |
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142:4eea097334d6 | 508 | #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ |
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142:4eea097334d6 | 509 | #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 510 | #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 511 | #define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */ |
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142:4eea097334d6 | 512 | #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ |
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142:4eea097334d6 | 513 | #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ |
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142:4eea097334d6 | 514 | #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 515 | #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 516 | #define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */ |
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142:4eea097334d6 | 517 | #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ |
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142:4eea097334d6 | 518 | #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ |
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142:4eea097334d6 | 519 | #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 520 | #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 521 | #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ |
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142:4eea097334d6 | 522 | #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ |
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142:4eea097334d6 | 523 | #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ |
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142:4eea097334d6 | 524 | #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 525 | #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 526 | #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */ |
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142:4eea097334d6 | 527 | #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ |
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142:4eea097334d6 | 528 | #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ |
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142:4eea097334d6 | 529 | #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 530 | #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 531 | #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */ |
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142:4eea097334d6 | 532 | #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ |
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142:4eea097334d6 | 533 | #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ |
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142:4eea097334d6 | 534 | #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 535 | #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 536 | #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */ |
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142:4eea097334d6 | 537 | #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ |
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142:4eea097334d6 | 538 | #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ |
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142:4eea097334d6 | 539 | #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 540 | #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 541 | #define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */ |
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142:4eea097334d6 | 542 | #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ |
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142:4eea097334d6 | 543 | #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ |
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142:4eea097334d6 | 544 | #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 545 | #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 546 | #define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */ |
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142:4eea097334d6 | 547 | #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ |
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142:4eea097334d6 | 548 | #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ |
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142:4eea097334d6 | 549 | #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 550 | #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 551 | #define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */ |
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142:4eea097334d6 | 552 | #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ |
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142:4eea097334d6 | 553 | #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ |
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142:4eea097334d6 | 554 | #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 555 | #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 556 | #define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */ |
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142:4eea097334d6 | 557 | #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ |
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142:4eea097334d6 | 558 | #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ |
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142:4eea097334d6 | 559 | #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 560 | #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 561 | #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ |
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142:4eea097334d6 | 562 | #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ |
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142:4eea097334d6 | 563 | #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ |
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142:4eea097334d6 | 564 | #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 565 | #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 566 | #define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */ |
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142:4eea097334d6 | 567 | #define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ |
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142:4eea097334d6 | 568 | #define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ |
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142:4eea097334d6 | 569 | #define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 570 | #define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 571 | #define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */ |
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142:4eea097334d6 | 572 | #define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ |
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142:4eea097334d6 | 573 | #define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ |
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142:4eea097334d6 | 574 | #define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 575 | #define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */ |
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142:4eea097334d6 | 576 | |
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142:4eea097334d6 | 577 | /* Bit fields for I2C IFC */ |
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142:4eea097334d6 | 578 | #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ |
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142:4eea097334d6 | 579 | #define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */ |
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142:4eea097334d6 | 580 | #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ |
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142:4eea097334d6 | 581 | #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ |
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142:4eea097334d6 | 582 | #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
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142:4eea097334d6 | 583 | #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 584 | #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 585 | #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */ |
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142:4eea097334d6 | 586 | #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ |
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142:4eea097334d6 | 587 | #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ |
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142:4eea097334d6 | 588 | #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 589 | #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 590 | #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */ |
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142:4eea097334d6 | 591 | #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ |
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142:4eea097334d6 | 592 | #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ |
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142:4eea097334d6 | 593 | #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 594 | #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 595 | #define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */ |
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142:4eea097334d6 | 596 | #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ |
| Anna Bridge |
142:4eea097334d6 | 597 | #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ |
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142:4eea097334d6 | 598 | #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 599 | #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 600 | #define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */ |
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142:4eea097334d6 | 601 | #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ |
| Anna Bridge |
142:4eea097334d6 | 602 | #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ |
| Anna Bridge |
142:4eea097334d6 | 603 | #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 604 | #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 605 | #define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 606 | #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ |
| Anna Bridge |
142:4eea097334d6 | 607 | #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ |
| Anna Bridge |
142:4eea097334d6 | 608 | #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 609 | #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 610 | #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 611 | #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ |
| Anna Bridge |
142:4eea097334d6 | 612 | #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ |
| Anna Bridge |
142:4eea097334d6 | 613 | #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 614 | #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 615 | #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 616 | #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ |
| Anna Bridge |
142:4eea097334d6 | 617 | #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ |
| Anna Bridge |
142:4eea097334d6 | 618 | #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 619 | #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 620 | #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 621 | #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ |
| Anna Bridge |
142:4eea097334d6 | 622 | #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ |
| Anna Bridge |
142:4eea097334d6 | 623 | #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 624 | #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 625 | #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 626 | #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ |
| Anna Bridge |
142:4eea097334d6 | 627 | #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ |
| Anna Bridge |
142:4eea097334d6 | 628 | #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 629 | #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 630 | #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 631 | #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ |
| Anna Bridge |
142:4eea097334d6 | 632 | #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ |
| Anna Bridge |
142:4eea097334d6 | 633 | #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 634 | #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 635 | #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 636 | #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ |
| Anna Bridge |
142:4eea097334d6 | 637 | #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ |
| Anna Bridge |
142:4eea097334d6 | 638 | #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 639 | #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 640 | #define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 641 | #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ |
| Anna Bridge |
142:4eea097334d6 | 642 | #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ |
| Anna Bridge |
142:4eea097334d6 | 643 | #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 644 | #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 645 | #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 646 | #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ |
| Anna Bridge |
142:4eea097334d6 | 647 | #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ |
| Anna Bridge |
142:4eea097334d6 | 648 | #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 649 | #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 650 | #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 651 | #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ |
| Anna Bridge |
142:4eea097334d6 | 652 | #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ |
| Anna Bridge |
142:4eea097334d6 | 653 | #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 654 | #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 655 | #define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 656 | #define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ |
| Anna Bridge |
142:4eea097334d6 | 657 | #define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ |
| Anna Bridge |
142:4eea097334d6 | 658 | #define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 659 | #define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 660 | #define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 661 | #define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ |
| Anna Bridge |
142:4eea097334d6 | 662 | #define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ |
| Anna Bridge |
142:4eea097334d6 | 663 | #define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 664 | #define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */ |
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142:4eea097334d6 | 665 | |
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142:4eea097334d6 | 666 | /* Bit fields for I2C IEN */ |
| Anna Bridge |
142:4eea097334d6 | 667 | #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 668 | #define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 669 | #define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 670 | #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ |
| Anna Bridge |
142:4eea097334d6 | 671 | #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
| Anna Bridge |
142:4eea097334d6 | 672 | #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 673 | #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 674 | #define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 675 | #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ |
| Anna Bridge |
142:4eea097334d6 | 676 | #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ |
| Anna Bridge |
142:4eea097334d6 | 677 | #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 678 | #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 679 | #define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 680 | #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ |
| Anna Bridge |
142:4eea097334d6 | 681 | #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ |
| Anna Bridge |
142:4eea097334d6 | 682 | #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 683 | #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 684 | #define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 685 | #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ |
| Anna Bridge |
142:4eea097334d6 | 686 | #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ |
| Anna Bridge |
142:4eea097334d6 | 687 | #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 688 | #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 689 | #define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 690 | #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ |
| Anna Bridge |
142:4eea097334d6 | 691 | #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ |
| Anna Bridge |
142:4eea097334d6 | 692 | #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 693 | #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 694 | #define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 695 | #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ |
| Anna Bridge |
142:4eea097334d6 | 696 | #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ |
| Anna Bridge |
142:4eea097334d6 | 697 | #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 698 | #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 699 | #define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 700 | #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ |
| Anna Bridge |
142:4eea097334d6 | 701 | #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ |
| Anna Bridge |
142:4eea097334d6 | 702 | #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 703 | #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 704 | #define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 705 | #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ |
| Anna Bridge |
142:4eea097334d6 | 706 | #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ |
| Anna Bridge |
142:4eea097334d6 | 707 | #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 708 | #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 709 | #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 710 | #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ |
| Anna Bridge |
142:4eea097334d6 | 711 | #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ |
| Anna Bridge |
142:4eea097334d6 | 712 | #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 713 | #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 714 | #define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 715 | #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ |
| Anna Bridge |
142:4eea097334d6 | 716 | #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ |
| Anna Bridge |
142:4eea097334d6 | 717 | #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 718 | #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 719 | #define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 720 | #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ |
| Anna Bridge |
142:4eea097334d6 | 721 | #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ |
| Anna Bridge |
142:4eea097334d6 | 722 | #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 723 | #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 724 | #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 725 | #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ |
| Anna Bridge |
142:4eea097334d6 | 726 | #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ |
| Anna Bridge |
142:4eea097334d6 | 727 | #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 728 | #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 729 | #define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 730 | #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ |
| Anna Bridge |
142:4eea097334d6 | 731 | #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ |
| Anna Bridge |
142:4eea097334d6 | 732 | #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 733 | #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 734 | #define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 735 | #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ |
| Anna Bridge |
142:4eea097334d6 | 736 | #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ |
| Anna Bridge |
142:4eea097334d6 | 737 | #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 738 | #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 739 | #define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 740 | #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ |
| Anna Bridge |
142:4eea097334d6 | 741 | #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ |
| Anna Bridge |
142:4eea097334d6 | 742 | #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 743 | #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 744 | #define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 745 | #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ |
| Anna Bridge |
142:4eea097334d6 | 746 | #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ |
| Anna Bridge |
142:4eea097334d6 | 747 | #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 748 | #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 749 | #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 750 | #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ |
| Anna Bridge |
142:4eea097334d6 | 751 | #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ |
| Anna Bridge |
142:4eea097334d6 | 752 | #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 753 | #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 754 | #define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 755 | #define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ |
| Anna Bridge |
142:4eea097334d6 | 756 | #define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ |
| Anna Bridge |
142:4eea097334d6 | 757 | #define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 758 | #define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 759 | #define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 760 | #define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ |
| Anna Bridge |
142:4eea097334d6 | 761 | #define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ |
| Anna Bridge |
142:4eea097334d6 | 762 | #define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 763 | #define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 764 | |
| Anna Bridge |
142:4eea097334d6 | 765 | /* Bit fields for I2C ROUTEPEN */ |
| Anna Bridge |
142:4eea097334d6 | 766 | #define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */ |
| Anna Bridge |
142:4eea097334d6 | 767 | #define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */ |
| Anna Bridge |
142:4eea097334d6 | 768 | #define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ |
| Anna Bridge |
142:4eea097334d6 | 769 | #define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ |
| Anna Bridge |
142:4eea097334d6 | 770 | #define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ |
| Anna Bridge |
142:4eea097334d6 | 771 | #define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ |
| Anna Bridge |
142:4eea097334d6 | 772 | #define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ |
| Anna Bridge |
142:4eea097334d6 | 773 | #define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ |
| Anna Bridge |
142:4eea097334d6 | 774 | #define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ |
| Anna Bridge |
142:4eea097334d6 | 775 | #define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ |
| Anna Bridge |
142:4eea097334d6 | 776 | #define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ |
| Anna Bridge |
142:4eea097334d6 | 777 | #define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ |
| Anna Bridge |
142:4eea097334d6 | 778 | |
| Anna Bridge |
142:4eea097334d6 | 779 | /* Bit fields for I2C ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 780 | #define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 781 | #define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 782 | #define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */ |
| Anna Bridge |
142:4eea097334d6 | 783 | #define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */ |
| Anna Bridge |
142:4eea097334d6 | 784 | #define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 785 | #define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 786 | #define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 787 | #define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 788 | #define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 789 | #define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 790 | #define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 791 | #define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 792 | #define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 793 | #define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 794 | #define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 795 | #define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 796 | #define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 797 | #define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 798 | #define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 799 | #define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 800 | #define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 801 | #define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 802 | #define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 803 | #define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 804 | #define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 805 | #define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 806 | #define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 807 | #define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 808 | #define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 809 | #define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 810 | #define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 811 | #define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 812 | #define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 813 | #define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 814 | #define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 815 | #define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 816 | #define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 817 | #define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 818 | #define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 819 | #define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 820 | #define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 821 | #define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 822 | #define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 823 | #define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 824 | #define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 825 | #define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 826 | #define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 827 | #define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 828 | #define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 829 | #define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 830 | #define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 831 | #define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 832 | #define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 833 | #define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 834 | #define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 835 | #define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 836 | #define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 837 | #define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 838 | #define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 839 | #define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 840 | #define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 841 | #define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 842 | #define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 843 | #define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 844 | #define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 845 | #define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 846 | #define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 847 | #define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 848 | #define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 849 | #define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 850 | #define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */ |
| Anna Bridge |
142:4eea097334d6 | 851 | #define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */ |
| Anna Bridge |
142:4eea097334d6 | 852 | #define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 853 | #define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 854 | #define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 855 | #define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 856 | #define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 857 | #define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 858 | #define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 859 | #define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 860 | #define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 861 | #define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 862 | #define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 863 | #define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 864 | #define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 865 | #define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 866 | #define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 867 | #define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 868 | #define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 869 | #define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 870 | #define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 871 | #define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 872 | #define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 873 | #define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 874 | #define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 875 | #define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 876 | #define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 877 | #define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 878 | #define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 879 | #define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 880 | #define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 881 | #define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 882 | #define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 883 | #define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 884 | #define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 885 | #define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 886 | #define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 887 | #define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 888 | #define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 889 | #define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 890 | #define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 891 | #define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 892 | #define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 893 | #define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 894 | #define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 895 | #define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 896 | #define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 897 | #define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 898 | #define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 899 | #define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 900 | #define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 901 | #define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 902 | #define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 903 | #define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 904 | #define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 905 | #define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 906 | #define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 907 | #define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 908 | #define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 909 | #define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 910 | #define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 911 | #define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 912 | #define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 913 | #define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 914 | #define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 915 | #define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 916 | #define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 917 | #define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ |
| Anna Bridge |
142:4eea097334d6 | 918 | |
| Anna Bridge |
142:4eea097334d6 | 919 | /** @} End of group EFR32MG1P_I2C */ |
| Anna Bridge |
142:4eea097334d6 | 920 | /** @} End of group Parts */ |
| Anna Bridge |
142:4eea097334d6 | 921 |
