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TARGET_TB_SENSE_1/TOOLCHAIN_ARM_MICRO/efr32mg1p_ldma.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_TB_SENSE_1/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h@142:4eea097334d6
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg1p_ldma.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG1P_LDMA register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG1P_LDMA |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG1P_LDMA Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IOM uint32_t CTRL; /**< DMA Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IM uint32_t STATUS; /**< DMA Status Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */ |
| Anna Bridge |
142:4eea097334d6 | 46 | uint32_t RESERVED0[5]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 47 | __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */ |
| Anna Bridge |
142:4eea097334d6 | 48 | __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ |
| Anna Bridge |
142:4eea097334d6 | 49 | __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */ |
| Anna Bridge |
142:4eea097334d6 | 50 | __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ |
| Anna Bridge |
142:4eea097334d6 | 51 | __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */ |
| Anna Bridge |
142:4eea097334d6 | 52 | __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ |
| Anna Bridge |
142:4eea097334d6 | 53 | __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ |
| Anna Bridge |
142:4eea097334d6 | 55 | __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 56 | uint32_t RESERVED1[7]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 57 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| Anna Bridge |
142:4eea097334d6 | 58 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| Anna Bridge |
142:4eea097334d6 | 59 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 60 | __IOM uint32_t IEN; /**< Interrupt Enable register */ |
| Anna Bridge |
142:4eea097334d6 | 61 | |
| Anna Bridge |
142:4eea097334d6 | 62 | uint32_t RESERVED2[4]; /**< Reserved registers */ |
| Anna Bridge |
142:4eea097334d6 | 63 | LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */ |
| Anna Bridge |
142:4eea097334d6 | 64 | } LDMA_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 65 | |
| Anna Bridge |
142:4eea097334d6 | 66 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 67 | * @defgroup EFR32MG1P_LDMA_BitFields |
| Anna Bridge |
142:4eea097334d6 | 68 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 69 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 70 | |
| Anna Bridge |
142:4eea097334d6 | 71 | /* Bit fields for LDMA CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 72 | #define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 73 | #define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 74 | #define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */ |
| Anna Bridge |
142:4eea097334d6 | 75 | #define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */ |
| Anna Bridge |
142:4eea097334d6 | 76 | #define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 77 | #define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 86 | |
| Anna Bridge |
142:4eea097334d6 | 87 | /* Bit fields for LDMA STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 88 | #define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 100 | #define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ |
| Anna Bridge |
142:4eea097334d6 | 101 | #define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 116 | |
| Anna Bridge |
142:4eea097334d6 | 117 | /* Bit fields for LDMA SYNC */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ |
| Anna Bridge |
142:4eea097334d6 | 121 | #define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ |
| Anna Bridge |
142:4eea097334d6 | 122 | #define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */ |
| Anna Bridge |
142:4eea097334d6 | 124 | |
| Anna Bridge |
142:4eea097334d6 | 125 | /* Bit fields for LDMA CHEN */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ |
| Anna Bridge |
142:4eea097334d6 | 132 | |
| Anna Bridge |
142:4eea097334d6 | 133 | /* Bit fields for LDMA CHBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 140 | |
| Anna Bridge |
142:4eea097334d6 | 141 | /* Bit fields for LDMA CHDONE */ |
| Anna Bridge |
142:4eea097334d6 | 142 | #define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ |
| Anna Bridge |
142:4eea097334d6 | 148 | |
| Anna Bridge |
142:4eea097334d6 | 149 | /* Bit fields for LDMA DBGHALT */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ |
| Anna Bridge |
142:4eea097334d6 | 156 | |
| Anna Bridge |
142:4eea097334d6 | 157 | /* Bit fields for LDMA SWREQ */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ |
| Anna Bridge |
142:4eea097334d6 | 159 | #define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ |
| Anna Bridge |
142:4eea097334d6 | 164 | |
| Anna Bridge |
142:4eea097334d6 | 165 | /* Bit fields for LDMA REQDIS */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ |
| Anna Bridge |
142:4eea097334d6 | 167 | #define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ |
| Anna Bridge |
142:4eea097334d6 | 172 | |
| Anna Bridge |
142:4eea097334d6 | 173 | /* Bit fields for LDMA REQPEND */ |
| Anna Bridge |
142:4eea097334d6 | 174 | #define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ |
| Anna Bridge |
142:4eea097334d6 | 175 | #define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ |
| Anna Bridge |
142:4eea097334d6 | 177 | #define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ |
| Anna Bridge |
142:4eea097334d6 | 178 | #define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ |
| Anna Bridge |
142:4eea097334d6 | 179 | #define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ |
| Anna Bridge |
142:4eea097334d6 | 180 | |
| Anna Bridge |
142:4eea097334d6 | 181 | /* Bit fields for LDMA LINKLOAD */ |
| Anna Bridge |
142:4eea097334d6 | 182 | #define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ |
| Anna Bridge |
142:4eea097334d6 | 183 | #define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ |
| Anna Bridge |
142:4eea097334d6 | 184 | #define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ |
| Anna Bridge |
142:4eea097334d6 | 185 | #define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ |
| Anna Bridge |
142:4eea097334d6 | 186 | #define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ |
| Anna Bridge |
142:4eea097334d6 | 187 | #define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ |
| Anna Bridge |
142:4eea097334d6 | 188 | |
| Anna Bridge |
142:4eea097334d6 | 189 | /* Bit fields for LDMA REQCLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 190 | #define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 191 | #define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 192 | #define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 193 | #define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ |
| Anna Bridge |
142:4eea097334d6 | 194 | #define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ |
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142:4eea097334d6 | 195 | #define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ |
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142:4eea097334d6 | 196 | |
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142:4eea097334d6 | 197 | /* Bit fields for LDMA IF */ |
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142:4eea097334d6 | 198 | #define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ |
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142:4eea097334d6 | 199 | #define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ |
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142:4eea097334d6 | 200 | #define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ |
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142:4eea097334d6 | 201 | #define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ |
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142:4eea097334d6 | 202 | #define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ |
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142:4eea097334d6 | 203 | #define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ |
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142:4eea097334d6 | 204 | #define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */ |
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142:4eea097334d6 | 205 | #define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ |
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142:4eea097334d6 | 206 | #define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ |
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142:4eea097334d6 | 207 | #define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ |
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142:4eea097334d6 | 208 | #define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ |
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142:4eea097334d6 | 209 | |
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142:4eea097334d6 | 210 | /* Bit fields for LDMA IFS */ |
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142:4eea097334d6 | 211 | #define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */ |
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142:4eea097334d6 | 212 | #define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */ |
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142:4eea097334d6 | 213 | #define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ |
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142:4eea097334d6 | 214 | #define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ |
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142:4eea097334d6 | 215 | #define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ |
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142:4eea097334d6 | 216 | #define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */ |
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142:4eea097334d6 | 217 | #define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */ |
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142:4eea097334d6 | 218 | #define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ |
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142:4eea097334d6 | 219 | #define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ |
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142:4eea097334d6 | 220 | #define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ |
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142:4eea097334d6 | 221 | #define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */ |
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142:4eea097334d6 | 222 | |
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142:4eea097334d6 | 223 | /* Bit fields for LDMA IFC */ |
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142:4eea097334d6 | 224 | #define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */ |
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142:4eea097334d6 | 225 | #define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */ |
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142:4eea097334d6 | 226 | #define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ |
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142:4eea097334d6 | 227 | #define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ |
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142:4eea097334d6 | 228 | #define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ |
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142:4eea097334d6 | 229 | #define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */ |
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142:4eea097334d6 | 230 | #define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */ |
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142:4eea097334d6 | 231 | #define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ |
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142:4eea097334d6 | 232 | #define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ |
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142:4eea097334d6 | 233 | #define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ |
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142:4eea097334d6 | 234 | #define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */ |
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142:4eea097334d6 | 235 | |
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142:4eea097334d6 | 236 | /* Bit fields for LDMA IEN */ |
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142:4eea097334d6 | 237 | #define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ |
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142:4eea097334d6 | 238 | #define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ |
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142:4eea097334d6 | 239 | #define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ |
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142:4eea097334d6 | 240 | #define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ |
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142:4eea097334d6 | 241 | #define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ |
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142:4eea097334d6 | 242 | #define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ |
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142:4eea097334d6 | 243 | #define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */ |
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142:4eea097334d6 | 244 | #define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ |
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142:4eea097334d6 | 245 | #define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ |
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142:4eea097334d6 | 246 | #define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ |
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142:4eea097334d6 | 247 | #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ |
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142:4eea097334d6 | 248 | |
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142:4eea097334d6 | 249 | /* Bit fields for LDMA CH_REQSEL */ |
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142:4eea097334d6 | 250 | #define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 251 | #define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 252 | #define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */ |
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142:4eea097334d6 | 253 | #define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */ |
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142:4eea097334d6 | 254 | #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 255 | #define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 256 | #define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 257 | #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 258 | #define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 259 | #define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 260 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 261 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 262 | #define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 263 | #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR 0x00000000UL /**< Mode CRYPTODATA0WR for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 264 | #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 265 | #define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 266 | #define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 267 | #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 268 | #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 269 | #define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 270 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 271 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 272 | #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR 0x00000001UL /**< Mode CRYPTODATA0XWR for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 273 | #define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 274 | #define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 275 | #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 276 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 277 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 278 | #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD 0x00000002UL /**< Mode CRYPTODATA0RD for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 279 | #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 280 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 281 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 282 | #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR 0x00000003UL /**< Mode CRYPTODATA1WR for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 283 | #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 284 | #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 285 | #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD 0x00000004UL /**< Mode CRYPTODATA1RD for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 286 | #define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 287 | #define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 288 | #define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 289 | #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 290 | #define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 291 | #define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 292 | #define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 293 | #define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 294 | #define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 295 | #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR << 0) /**< Shifted mode CRYPTODATA0WR for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 296 | #define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 297 | #define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 298 | #define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 299 | #define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 300 | #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 301 | #define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 302 | #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 303 | #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 304 | #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR << 0) /**< Shifted mode CRYPTODATA0XWR for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 305 | #define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 306 | #define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 307 | #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 308 | #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 309 | #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 310 | #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD << 0) /**< Shifted mode CRYPTODATA0RD for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 311 | #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 312 | #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 313 | #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 314 | #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR << 0) /**< Shifted mode CRYPTODATA1WR for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 315 | #define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 316 | #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 317 | #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD << 0) /**< Shifted mode CRYPTODATA1RD for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 318 | #define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */ |
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142:4eea097334d6 | 319 | #define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */ |
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142:4eea097334d6 | 320 | #define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 321 | #define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 322 | #define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 323 | #define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 324 | #define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 325 | #define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 326 | #define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 327 | #define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 328 | #define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 329 | #define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 330 | #define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO 0x00000031UL /**< Mode CRYPTO for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 331 | #define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 332 | #define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 333 | #define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 334 | #define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 335 | #define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 336 | #define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 337 | #define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 338 | #define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 339 | #define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 340 | #define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 341 | #define LDMA_CH_REQSEL_SOURCESEL_CRYPTO (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO << 16) /**< Shifted mode CRYPTO for LDMA_CH_REQSEL */ |
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142:4eea097334d6 | 342 | |
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142:4eea097334d6 | 343 | /* Bit fields for LDMA CH_CFG */ |
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142:4eea097334d6 | 344 | #define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ |
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142:4eea097334d6 | 345 | #define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ |
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142:4eea097334d6 | 346 | #define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ |
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142:4eea097334d6 | 347 | #define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ |
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142:4eea097334d6 | 348 | #define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ |
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142:4eea097334d6 | 349 | #define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 350 | #define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ |
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142:4eea097334d6 | 351 | #define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ |
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142:4eea097334d6 | 352 | #define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ |
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142:4eea097334d6 | 353 | #define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ |
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142:4eea097334d6 | 354 | #define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 355 | #define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ |
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142:4eea097334d6 | 356 | #define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ |
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142:4eea097334d6 | 357 | #define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ |
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142:4eea097334d6 | 358 | #define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ |
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142:4eea097334d6 | 359 | #define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ |
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142:4eea097334d6 | 360 | #define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ |
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142:4eea097334d6 | 361 | #define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ |
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142:4eea097334d6 | 362 | #define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 363 | #define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 364 | #define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ |
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142:4eea097334d6 | 365 | #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 366 | #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 367 | #define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ |
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142:4eea097334d6 | 368 | #define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ |
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142:4eea097334d6 | 369 | #define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ |
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142:4eea097334d6 | 370 | #define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ |
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142:4eea097334d6 | 371 | #define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 372 | #define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 373 | #define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ |
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142:4eea097334d6 | 374 | #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 375 | #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ |
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142:4eea097334d6 | 376 | |
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142:4eea097334d6 | 377 | /* Bit fields for LDMA CH_LOOP */ |
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142:4eea097334d6 | 378 | #define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ |
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142:4eea097334d6 | 379 | #define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ |
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142:4eea097334d6 | 380 | #define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ |
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142:4eea097334d6 | 381 | #define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ |
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142:4eea097334d6 | 382 | #define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ |
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142:4eea097334d6 | 383 | #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ |
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142:4eea097334d6 | 384 | |
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142:4eea097334d6 | 385 | /* Bit fields for LDMA CH_CTRL */ |
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142:4eea097334d6 | 386 | #define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 387 | #define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 388 | #define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ |
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142:4eea097334d6 | 389 | #define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ |
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142:4eea097334d6 | 390 | #define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 391 | #define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 392 | #define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 393 | #define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 394 | #define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 395 | #define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 396 | #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 397 | #define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 398 | #define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ |
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142:4eea097334d6 | 399 | #define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ |
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142:4eea097334d6 | 400 | #define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ |
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142:4eea097334d6 | 401 | #define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 402 | #define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 403 | #define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ |
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142:4eea097334d6 | 404 | #define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ |
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142:4eea097334d6 | 405 | #define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 406 | #define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 407 | #define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ |
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142:4eea097334d6 | 408 | #define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ |
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142:4eea097334d6 | 409 | #define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ |
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142:4eea097334d6 | 410 | #define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 411 | #define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 412 | #define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ |
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142:4eea097334d6 | 413 | #define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ |
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142:4eea097334d6 | 414 | #define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 415 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 416 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 417 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 418 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 419 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 420 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 421 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 422 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 423 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 424 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 425 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 426 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 427 | #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 428 | #define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 429 | #define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 430 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 431 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 432 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 433 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 434 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 435 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 436 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 437 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 438 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 439 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 440 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 441 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 442 | #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 443 | #define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 444 | #define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */ |
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142:4eea097334d6 | 445 | #define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */ |
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142:4eea097334d6 | 446 | #define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */ |
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142:4eea097334d6 | 447 | #define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 448 | #define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 449 | #define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ |
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142:4eea097334d6 | 450 | #define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ |
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142:4eea097334d6 | 451 | #define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ |
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142:4eea097334d6 | 452 | #define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 453 | #define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 454 | #define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 455 | #define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 456 | #define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 457 | #define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 458 | #define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ |
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142:4eea097334d6 | 459 | #define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ |
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142:4eea097334d6 | 460 | #define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ |
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142:4eea097334d6 | 461 | #define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 462 | #define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 463 | #define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ |
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142:4eea097334d6 | 464 | #define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ |
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142:4eea097334d6 | 465 | #define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ |
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142:4eea097334d6 | 466 | #define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 467 | #define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 468 | #define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ |
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142:4eea097334d6 | 469 | #define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ |
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142:4eea097334d6 | 470 | #define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 471 | #define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 472 | #define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 473 | #define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 474 | #define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 475 | #define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 476 | #define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 477 | #define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 478 | #define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 479 | #define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 480 | #define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ |
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142:4eea097334d6 | 481 | #define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ |
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142:4eea097334d6 | 482 | #define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 483 | #define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 484 | #define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 485 | #define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 486 | #define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 487 | #define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 488 | #define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 489 | #define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 490 | #define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ |
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142:4eea097334d6 | 491 | #define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ |
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142:4eea097334d6 | 492 | #define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 493 | #define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 494 | #define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 495 | #define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 496 | #define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 497 | #define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 498 | #define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 499 | #define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 500 | #define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 501 | #define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 502 | #define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ |
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142:4eea097334d6 | 503 | #define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ |
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142:4eea097334d6 | 504 | #define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ |
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142:4eea097334d6 | 505 | #define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 506 | #define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 507 | #define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 508 | #define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 509 | #define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 510 | #define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 511 | #define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ |
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142:4eea097334d6 | 512 | #define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ |
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142:4eea097334d6 | 513 | #define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ |
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142:4eea097334d6 | 514 | #define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 515 | #define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 516 | #define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 517 | #define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 518 | #define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 519 | #define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ |
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142:4eea097334d6 | 520 | |
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142:4eea097334d6 | 521 | /* Bit fields for LDMA CH_SRC */ |
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142:4eea097334d6 | 522 | #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ |
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142:4eea097334d6 | 523 | #define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ |
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142:4eea097334d6 | 524 | #define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ |
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142:4eea097334d6 | 525 | #define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ |
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142:4eea097334d6 | 526 | #define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ |
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142:4eea097334d6 | 527 | #define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ |
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142:4eea097334d6 | 528 | |
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142:4eea097334d6 | 529 | /* Bit fields for LDMA CH_DST */ |
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142:4eea097334d6 | 530 | #define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ |
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142:4eea097334d6 | 531 | #define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ |
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142:4eea097334d6 | 532 | #define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ |
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142:4eea097334d6 | 533 | #define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ |
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142:4eea097334d6 | 534 | #define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ |
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142:4eea097334d6 | 535 | #define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ |
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142:4eea097334d6 | 536 | |
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142:4eea097334d6 | 537 | /* Bit fields for LDMA CH_LINK */ |
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142:4eea097334d6 | 538 | #define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ |
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142:4eea097334d6 | 539 | #define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ |
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142:4eea097334d6 | 540 | #define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ |
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142:4eea097334d6 | 541 | #define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ |
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142:4eea097334d6 | 542 | #define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ |
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142:4eea097334d6 | 543 | #define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ |
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142:4eea097334d6 | 544 | #define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ |
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142:4eea097334d6 | 545 | #define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ |
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142:4eea097334d6 | 546 | #define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ |
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142:4eea097334d6 | 547 | #define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ |
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142:4eea097334d6 | 548 | #define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ |
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142:4eea097334d6 | 549 | #define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ |
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142:4eea097334d6 | 550 | #define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ |
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142:4eea097334d6 | 551 | #define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ |
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142:4eea097334d6 | 552 | #define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ |
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142:4eea097334d6 | 553 | #define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ |
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142:4eea097334d6 | 554 | #define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ |
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142:4eea097334d6 | 555 | #define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ |
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142:4eea097334d6 | 556 | #define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ |
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142:4eea097334d6 | 557 | #define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ |
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142:4eea097334d6 | 558 | |
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142:4eea097334d6 | 559 | /** @} End of group EFR32MG1P_LDMA */ |
| Anna Bridge |
142:4eea097334d6 | 560 | /** @} End of group Parts */ |
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142:4eea097334d6 | 561 |
