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TARGET_TB_SENSE_1/TOOLCHAIN_ARM_MICRO/efr32mg1p_fpueh.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_TB_SENSE_1/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h@142:4eea097334d6
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg1p_fpueh.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG1P_FPUEH register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG1P_FPUEH |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG1P_FPUEH Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 46 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| Anna Bridge |
142:4eea097334d6 | 47 | } FPUEH_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 48 | |
| Anna Bridge |
142:4eea097334d6 | 49 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 50 | * @defgroup EFR32MG1P_FPUEH_BitFields |
| Anna Bridge |
142:4eea097334d6 | 51 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 52 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 53 | |
| Anna Bridge |
142:4eea097334d6 | 54 | /* Bit fields for FPUEH IF */ |
| Anna Bridge |
142:4eea097334d6 | 55 | #define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 56 | #define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 57 | #define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */ |
| Anna Bridge |
142:4eea097334d6 | 58 | #define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ |
| Anna Bridge |
142:4eea097334d6 | 59 | #define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ |
| Anna Bridge |
142:4eea097334d6 | 60 | #define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 61 | #define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 62 | #define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */ |
| Anna Bridge |
142:4eea097334d6 | 63 | #define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ |
| Anna Bridge |
142:4eea097334d6 | 64 | #define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ |
| Anna Bridge |
142:4eea097334d6 | 65 | #define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 66 | #define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 67 | #define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */ |
| Anna Bridge |
142:4eea097334d6 | 68 | #define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ |
| Anna Bridge |
142:4eea097334d6 | 69 | #define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ |
| Anna Bridge |
142:4eea097334d6 | 70 | #define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 71 | #define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 72 | #define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */ |
| Anna Bridge |
142:4eea097334d6 | 73 | #define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ |
| Anna Bridge |
142:4eea097334d6 | 74 | #define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ |
| Anna Bridge |
142:4eea097334d6 | 75 | #define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 76 | #define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 77 | #define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 86 | #define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */ |
| Anna Bridge |
142:4eea097334d6 | 87 | |
| Anna Bridge |
142:4eea097334d6 | 88 | /* Bit fields for FPUEH IFS */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 100 | #define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 101 | #define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 116 | #define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 117 | #define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 121 | |
| Anna Bridge |
142:4eea097334d6 | 122 | /* Bit fields for FPUEH IFC */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 124 | #define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 125 | #define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ |
| Anna Bridge |
142:4eea097334d6 | 132 | #define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ |
| Anna Bridge |
142:4eea097334d6 | 133 | #define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 140 | #define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 141 | #define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ |
| Anna Bridge |
142:4eea097334d6 | 142 | #define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 155 | |
| Anna Bridge |
142:4eea097334d6 | 156 | /* Bit fields for FPUEH IEN */ |
| Anna Bridge |
142:4eea097334d6 | 157 | #define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 159 | #define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ |
| Anna Bridge |
142:4eea097334d6 | 167 | #define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 174 | #define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 175 | #define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ |
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142:4eea097334d6 | 177 | #define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ |
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142:4eea097334d6 | 178 | #define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */ |
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142:4eea097334d6 | 179 | #define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */ |
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142:4eea097334d6 | 180 | #define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ |
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142:4eea097334d6 | 181 | #define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ |
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142:4eea097334d6 | 182 | #define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ |
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142:4eea097334d6 | 183 | #define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */ |
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142:4eea097334d6 | 184 | #define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */ |
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142:4eea097334d6 | 185 | #define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ |
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142:4eea097334d6 | 186 | #define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ |
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142:4eea097334d6 | 187 | #define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ |
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142:4eea097334d6 | 188 | #define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */ |
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142:4eea097334d6 | 189 | |
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142:4eea097334d6 | 190 | /** @} End of group EFR32MG1P_FPUEH */ |
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142:4eea097334d6 | 191 | /** @} End of group Parts */ |
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142:4eea097334d6 | 192 |
