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Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_MAX32625PICO/TARGET_Maxim/TARGET_MAX32625/device/clkman_regs.h@169:a7c7b631e539
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 169:a7c7b631e539 1 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
Anna Bridge 169:a7c7b631e539 3 *
Anna Bridge 169:a7c7b631e539 4 * Permission is hereby granted, free of charge, to any person obtaining a
Anna Bridge 169:a7c7b631e539 5 * copy of this software and associated documentation files (the "Software"),
Anna Bridge 169:a7c7b631e539 6 * to deal in the Software without restriction, including without limitation
Anna Bridge 169:a7c7b631e539 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Anna Bridge 169:a7c7b631e539 8 * and/or sell copies of the Software, and to permit persons to whom the
Anna Bridge 169:a7c7b631e539 9 * Software is furnished to do so, subject to the following conditions:
Anna Bridge 169:a7c7b631e539 10 *
Anna Bridge 169:a7c7b631e539 11 * The above copyright notice and this permission notice shall be included
Anna Bridge 169:a7c7b631e539 12 * in all copies or substantial portions of the Software.
Anna Bridge 169:a7c7b631e539 13 *
Anna Bridge 169:a7c7b631e539 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Anna Bridge 169:a7c7b631e539 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Anna Bridge 169:a7c7b631e539 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Anna Bridge 169:a7c7b631e539 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Anna Bridge 169:a7c7b631e539 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Anna Bridge 169:a7c7b631e539 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Anna Bridge 169:a7c7b631e539 20 * OTHER DEALINGS IN THE SOFTWARE.
Anna Bridge 169:a7c7b631e539 21 *
Anna Bridge 169:a7c7b631e539 22 * Except as contained in this notice, the name of Maxim Integrated
Anna Bridge 169:a7c7b631e539 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Anna Bridge 169:a7c7b631e539 24 * Products, Inc. Branding Policy.
Anna Bridge 169:a7c7b631e539 25 *
Anna Bridge 169:a7c7b631e539 26 * The mere transfer of this software does not imply any licenses
Anna Bridge 169:a7c7b631e539 27 * of trade secrets, proprietary technology, copyrights, patents,
Anna Bridge 169:a7c7b631e539 28 * trademarks, maskwork rights, or any other form of intellectual
Anna Bridge 169:a7c7b631e539 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Anna Bridge 169:a7c7b631e539 30 * ownership rights.
Anna Bridge 169:a7c7b631e539 31 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 32
Anna Bridge 169:a7c7b631e539 33 #ifndef _MXC_CLKMAN_REGS_H_
Anna Bridge 169:a7c7b631e539 34 #define _MXC_CLKMAN_REGS_H_
Anna Bridge 169:a7c7b631e539 35
Anna Bridge 169:a7c7b631e539 36 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 37 extern "C" {
Anna Bridge 169:a7c7b631e539 38 #endif
Anna Bridge 169:a7c7b631e539 39
Anna Bridge 169:a7c7b631e539 40 #include <stdint.h>
Anna Bridge 169:a7c7b631e539 41 #include "mxc_device.h"
Anna Bridge 169:a7c7b631e539 42
Anna Bridge 169:a7c7b631e539 43 /*
Anna Bridge 169:a7c7b631e539 44 If types are not defined elsewhere (CMSIS) define them here
Anna Bridge 169:a7c7b631e539 45 */
Anna Bridge 169:a7c7b631e539 46 #ifndef __IO
Anna Bridge 169:a7c7b631e539 47 #define __IO volatile
Anna Bridge 169:a7c7b631e539 48 #endif
Anna Bridge 169:a7c7b631e539 49 #ifndef __I
Anna Bridge 169:a7c7b631e539 50 #define __I volatile const
Anna Bridge 169:a7c7b631e539 51 #endif
Anna Bridge 169:a7c7b631e539 52 #ifndef __O
Anna Bridge 169:a7c7b631e539 53 #define __O volatile
Anna Bridge 169:a7c7b631e539 54 #endif
Anna Bridge 169:a7c7b631e539 55
Anna Bridge 169:a7c7b631e539 56
Anna Bridge 169:a7c7b631e539 57 /*
Anna Bridge 169:a7c7b631e539 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
Anna Bridge 169:a7c7b631e539 59 access to each register in module.
Anna Bridge 169:a7c7b631e539 60 */
Anna Bridge 169:a7c7b631e539 61
Anna Bridge 169:a7c7b631e539 62 /* Offset Register Description
Anna Bridge 169:a7c7b631e539 63 ============= ============================================================================ */
Anna Bridge 169:a7c7b631e539 64 typedef struct {
Anna Bridge 169:a7c7b631e539 65 __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
Anna Bridge 169:a7c7b631e539 66 __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
Anna Bridge 169:a7c7b631e539 67 __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
Anna Bridge 169:a7c7b631e539 68 __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
Anna Bridge 169:a7c7b631e539 69 __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
Anna Bridge 169:a7c7b631e539 70 __IO uint32_t i2c_timer_ctrl; /* 0x0014 I2C Timer Control */
Anna Bridge 169:a7c7b631e539 71 __IO uint32_t cm4_start_clk_en0; /* 0x0018 CM4 Start Clock on Interrupt Enable 0 */
Anna Bridge 169:a7c7b631e539 72 __IO uint32_t cm4_start_clk_en1; /* 0x001C CM4 Start Clock on Interrupt Enable 1 */
Anna Bridge 169:a7c7b631e539 73 __IO uint32_t cm4_start_clk_en2; /* 0x0020 CM4 Start Clock on Interrupt Enable 2 */
Anna Bridge 169:a7c7b631e539 74 __I uint32_t rsv024[7]; /* 0x0024-0x003C */
Anna Bridge 169:a7c7b631e539 75 __IO uint32_t sys_clk_ctrl_0_cm4; /* 0x0040 Control Settings for CLK0 - Cortex M4 Clock */
Anna Bridge 169:a7c7b631e539 76 __IO uint32_t sys_clk_ctrl_1_sync; /* 0x0044 Control Settings for CLK1 - Synchronizer Clock */
Anna Bridge 169:a7c7b631e539 77 __IO uint32_t sys_clk_ctrl_2_spix; /* 0x0048 Control Settings for CLK2 - SPI XIP Clock */
Anna Bridge 169:a7c7b631e539 78 __IO uint32_t sys_clk_ctrl_3_prng; /* 0x004C Control Settings for CLK3 - PRNG Clock */
Anna Bridge 169:a7c7b631e539 79 __IO uint32_t sys_clk_ctrl_4_wdt0; /* 0x0050 Control Settings for CLK4 - Watchdog Timer 0 */
Anna Bridge 169:a7c7b631e539 80 __IO uint32_t sys_clk_ctrl_5_wdt1; /* 0x0054 Control Settings for CLK5 - Watchdog Timer 1 */
Anna Bridge 169:a7c7b631e539 81 __IO uint32_t sys_clk_ctrl_6_gpio; /* 0x0058 Control Settings for CLK6 - Clock for GPIO Ports */
Anna Bridge 169:a7c7b631e539 82 __IO uint32_t sys_clk_ctrl_7_pt; /* 0x005C Control Settings for CLK7 - Source Clock for All Pulse Trains */
Anna Bridge 169:a7c7b631e539 83 __IO uint32_t sys_clk_ctrl_8_uart; /* 0x0060 Control Settings for CLK8 - Source Clock for All UARTs */
Anna Bridge 169:a7c7b631e539 84 __IO uint32_t sys_clk_ctrl_9_i2cm; /* 0x0064 Control Settings for CLK9 - Source Clock for All I2C Masters */
Anna Bridge 169:a7c7b631e539 85 __IO uint32_t sys_clk_ctrl_10_i2cs; /* 0x0068 Control Settings for CLK10 - Source Clock for I2C Slave */
Anna Bridge 169:a7c7b631e539 86 __IO uint32_t sys_clk_ctrl_11_spi0; /* 0x006C Control Settings for CLK11 - SPI Master 0 */
Anna Bridge 169:a7c7b631e539 87 __IO uint32_t sys_clk_ctrl_12_spi1; /* 0x0070 Control Settings for CLK12 - SPI Master 1 */
Anna Bridge 169:a7c7b631e539 88 __IO uint32_t sys_clk_ctrl_13_spi2; /* 0x0074 Control Settings for CLK13 - SPI Master 2 */
Anna Bridge 169:a7c7b631e539 89 __I uint32_t rsv078; /* 0x0078 */
Anna Bridge 169:a7c7b631e539 90 __IO uint32_t sys_clk_ctrl_15_owm; /* 0x007C Control Settings for CLK15 - 1-Wire Master Clock */
Anna Bridge 169:a7c7b631e539 91 __IO uint32_t sys_clk_ctrl_16_spis; /* 0x0080 Control Settings for CLK16 - SPI Slave Clock */
Anna Bridge 169:a7c7b631e539 92 __I uint32_t rsv084[31]; /* 0x0084-0x00FC */
Anna Bridge 169:a7c7b631e539 93 __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
Anna Bridge 169:a7c7b631e539 94 __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
Anna Bridge 169:a7c7b631e539 95 __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
Anna Bridge 169:a7c7b631e539 96 __I uint32_t rsv10C[13]; /* 0x010C-0x013C */
Anna Bridge 169:a7c7b631e539 97 __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
Anna Bridge 169:a7c7b631e539 98 __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
Anna Bridge 169:a7c7b631e539 99 __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
Anna Bridge 169:a7c7b631e539 100 } mxc_clkman_regs_t;
Anna Bridge 169:a7c7b631e539 101
Anna Bridge 169:a7c7b631e539 102
Anna Bridge 169:a7c7b631e539 103 /*
Anna Bridge 169:a7c7b631e539 104 Register offsets for module CLKMAN.
Anna Bridge 169:a7c7b631e539 105 */
Anna Bridge 169:a7c7b631e539 106
Anna Bridge 169:a7c7b631e539 107 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
Anna Bridge 169:a7c7b631e539 108 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
Anna Bridge 169:a7c7b631e539 109 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
Anna Bridge 169:a7c7b631e539 110 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
Anna Bridge 169:a7c7b631e539 111 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
Anna Bridge 169:a7c7b631e539 112 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL)
Anna Bridge 169:a7c7b631e539 113 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL)
Anna Bridge 169:a7c7b631e539 114 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL)
Anna Bridge 169:a7c7b631e539 115 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL)
Anna Bridge 169:a7c7b631e539 116 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL)
Anna Bridge 169:a7c7b631e539 117 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL)
Anna Bridge 169:a7c7b631e539 118 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL)
Anna Bridge 169:a7c7b631e539 119 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL)
Anna Bridge 169:a7c7b631e539 120 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL)
Anna Bridge 169:a7c7b631e539 121 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL)
Anna Bridge 169:a7c7b631e539 122 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL)
Anna Bridge 169:a7c7b631e539 123 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL)
Anna Bridge 169:a7c7b631e539 124 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL)
Anna Bridge 169:a7c7b631e539 125 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL)
Anna Bridge 169:a7c7b631e539 126 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL)
Anna Bridge 169:a7c7b631e539 127 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL)
Anna Bridge 169:a7c7b631e539 128 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL)
Anna Bridge 169:a7c7b631e539 129 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL)
Anna Bridge 169:a7c7b631e539 130 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL)
Anna Bridge 169:a7c7b631e539 131 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL)
Anna Bridge 169:a7c7b631e539 132 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
Anna Bridge 169:a7c7b631e539 133 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
Anna Bridge 169:a7c7b631e539 134 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
Anna Bridge 169:a7c7b631e539 135 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
Anna Bridge 169:a7c7b631e539 136 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
Anna Bridge 169:a7c7b631e539 137 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
Anna Bridge 169:a7c7b631e539 138
Anna Bridge 169:a7c7b631e539 139
Anna Bridge 169:a7c7b631e539 140 /*
Anna Bridge 169:a7c7b631e539 141 Field positions and masks for module CLKMAN.
Anna Bridge 169:a7c7b631e539 142 */
Anna Bridge 169:a7c7b631e539 143
Anna Bridge 169:a7c7b631e539 144 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0
Anna Bridge 169:a7c7b631e539 145 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
Anna Bridge 169:a7c7b631e539 146 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4
Anna Bridge 169:a7c7b631e539 147 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 148
Anna Bridge 169:a7c7b631e539 149 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0
Anna Bridge 169:a7c7b631e539 150 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
Anna Bridge 169:a7c7b631e539 151 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4
Anna Bridge 169:a7c7b631e539 152 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS))
Anna Bridge 169:a7c7b631e539 153 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5
Anna Bridge 169:a7c7b631e539 154 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 155 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8
Anna Bridge 169:a7c7b631e539 156 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS))
Anna Bridge 169:a7c7b631e539 157 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12
Anna Bridge 169:a7c7b631e539 158 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
Anna Bridge 169:a7c7b631e539 159 #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13
Anna Bridge 169:a7c7b631e539 160 #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS))
Anna Bridge 169:a7c7b631e539 161 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16
Anna Bridge 169:a7c7b631e539 162 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS))
Anna Bridge 169:a7c7b631e539 163 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17
Anna Bridge 169:a7c7b631e539 164 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 165 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20
Anna Bridge 169:a7c7b631e539 166 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS))
Anna Bridge 169:a7c7b631e539 167 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21
Anna Bridge 169:a7c7b631e539 168 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 169 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24
Anna Bridge 169:a7c7b631e539 170 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS))
Anna Bridge 169:a7c7b631e539 171
Anna Bridge 169:a7c7b631e539 172 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0
Anna Bridge 169:a7c7b631e539 173 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
Anna Bridge 169:a7c7b631e539 174 #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1
Anna Bridge 169:a7c7b631e539 175 #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS))
Anna Bridge 169:a7c7b631e539 176
Anna Bridge 169:a7c7b631e539 177 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0
Anna Bridge 169:a7c7b631e539 178 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
Anna Bridge 169:a7c7b631e539 179 #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1
Anna Bridge 169:a7c7b631e539 180 #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS))
Anna Bridge 169:a7c7b631e539 181
Anna Bridge 169:a7c7b631e539 182 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
Anna Bridge 169:a7c7b631e539 183 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
Anna Bridge 169:a7c7b631e539 184 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
Anna Bridge 169:a7c7b631e539 185 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
Anna Bridge 169:a7c7b631e539 186 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
Anna Bridge 169:a7c7b631e539 187 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
Anna Bridge 169:a7c7b631e539 188 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
Anna Bridge 169:a7c7b631e539 189 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
Anna Bridge 169:a7c7b631e539 190 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH_POS 4
Anna Bridge 169:a7c7b631e539 191 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH ((uint32_t)(0x00000FFFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH_POS))
Anna Bridge 169:a7c7b631e539 192 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
Anna Bridge 169:a7c7b631e539 193 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x00003FFFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
Anna Bridge 169:a7c7b631e539 194
Anna Bridge 169:a7c7b631e539 195 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
Anna Bridge 169:a7c7b631e539 196 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
Anna Bridge 169:a7c7b631e539 197
Anna Bridge 169:a7c7b631e539 198 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0
Anna Bridge 169:a7c7b631e539 199 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS))
Anna Bridge 169:a7c7b631e539 200
Anna Bridge 169:a7c7b631e539 201 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0
Anna Bridge 169:a7c7b631e539 202 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS))
Anna Bridge 169:a7c7b631e539 203
Anna Bridge 169:a7c7b631e539 204 #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0
Anna Bridge 169:a7c7b631e539 205 #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS))
Anna Bridge 169:a7c7b631e539 206
Anna Bridge 169:a7c7b631e539 207 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 208 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 209
Anna Bridge 169:a7c7b631e539 210 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 211 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 212
Anna Bridge 169:a7c7b631e539 213 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 214 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 215
Anna Bridge 169:a7c7b631e539 216 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 217 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 218
Anna Bridge 169:a7c7b631e539 219 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 220 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 221
Anna Bridge 169:a7c7b631e539 222 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 223 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 224
Anna Bridge 169:a7c7b631e539 225 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 226 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 227
Anna Bridge 169:a7c7b631e539 228 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 229 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 230
Anna Bridge 169:a7c7b631e539 231 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 232 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 233
Anna Bridge 169:a7c7b631e539 234 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 235 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 236
Anna Bridge 169:a7c7b631e539 237 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 238 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 239
Anna Bridge 169:a7c7b631e539 240 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 241 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 242
Anna Bridge 169:a7c7b631e539 243 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 244 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 245
Anna Bridge 169:a7c7b631e539 246 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 247 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 248
Anna Bridge 169:a7c7b631e539 249 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 250 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 251
Anna Bridge 169:a7c7b631e539 252 #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 253 #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 254
Anna Bridge 169:a7c7b631e539 255 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 256 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 257
Anna Bridge 169:a7c7b631e539 258 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 259 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 260
Anna Bridge 169:a7c7b631e539 261 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
Anna Bridge 169:a7c7b631e539 262 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 263
Anna Bridge 169:a7c7b631e539 264 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0
Anna Bridge 169:a7c7b631e539 265 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 266 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2
Anna Bridge 169:a7c7b631e539 267 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 268 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
Anna Bridge 169:a7c7b631e539 269 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 270 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
Anna Bridge 169:a7c7b631e539 271 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 272 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
Anna Bridge 169:a7c7b631e539 273 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 274 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
Anna Bridge 169:a7c7b631e539 275 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 276 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
Anna Bridge 169:a7c7b631e539 277 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 278 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14
Anna Bridge 169:a7c7b631e539 279 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 280 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16
Anna Bridge 169:a7c7b631e539 281 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 282 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18
Anna Bridge 169:a7c7b631e539 283 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 284 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20
Anna Bridge 169:a7c7b631e539 285 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 286 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22
Anna Bridge 169:a7c7b631e539 287 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 288 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24
Anna Bridge 169:a7c7b631e539 289 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 290 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26
Anna Bridge 169:a7c7b631e539 291 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 292 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28
Anna Bridge 169:a7c7b631e539 293 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 294 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30
Anna Bridge 169:a7c7b631e539 295 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 296
Anna Bridge 169:a7c7b631e539 297 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0
Anna Bridge 169:a7c7b631e539 298 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 299 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2
Anna Bridge 169:a7c7b631e539 300 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 301 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4
Anna Bridge 169:a7c7b631e539 302 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 303 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6
Anna Bridge 169:a7c7b631e539 304 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 305 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8
Anna Bridge 169:a7c7b631e539 306 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 307 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10
Anna Bridge 169:a7c7b631e539 308 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 309 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12
Anna Bridge 169:a7c7b631e539 310 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 311 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14
Anna Bridge 169:a7c7b631e539 312 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 313 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16
Anna Bridge 169:a7c7b631e539 314 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 315 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18
Anna Bridge 169:a7c7b631e539 316 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 317 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20
Anna Bridge 169:a7c7b631e539 318 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 319 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22
Anna Bridge 169:a7c7b631e539 320 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 321 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
Anna Bridge 169:a7c7b631e539 322 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 323 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
Anna Bridge 169:a7c7b631e539 324 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 325
Anna Bridge 169:a7c7b631e539 326 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0
Anna Bridge 169:a7c7b631e539 327 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 328 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2
Anna Bridge 169:a7c7b631e539 329 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 330 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4
Anna Bridge 169:a7c7b631e539 331 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 332 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6
Anna Bridge 169:a7c7b631e539 333 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 334 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10
Anna Bridge 169:a7c7b631e539 335 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 336 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12
Anna Bridge 169:a7c7b631e539 337 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 338 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14
Anna Bridge 169:a7c7b631e539 339 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS))
Anna Bridge 169:a7c7b631e539 340
Anna Bridge 169:a7c7b631e539 341
Anna Bridge 169:a7c7b631e539 342
Anna Bridge 169:a7c7b631e539 343 /*
Anna Bridge 169:a7c7b631e539 344 Field values and shifted values for module CLKMAN.
Anna Bridge 169:a7c7b631e539 345 */
Anna Bridge 169:a7c7b631e539 346
Anna Bridge 169:a7c7b631e539 347 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL))
Anna Bridge 169:a7c7b631e539 348 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL))
Anna Bridge 169:a7c7b631e539 349 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL))
Anna Bridge 169:a7c7b631e539 350 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL))
Anna Bridge 169:a7c7b631e539 351 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL))
Anna Bridge 169:a7c7b631e539 352 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL))
Anna Bridge 169:a7c7b631e539 353 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL))
Anna Bridge 169:a7c7b631e539 354 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL))
Anna Bridge 169:a7c7b631e539 355 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL))
Anna Bridge 169:a7c7b631e539 356 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL))
Anna Bridge 169:a7c7b631e539 357 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL))
Anna Bridge 169:a7c7b631e539 358 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL))
Anna Bridge 169:a7c7b631e539 359 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL))
Anna Bridge 169:a7c7b631e539 360 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL))
Anna Bridge 169:a7c7b631e539 361 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL))
Anna Bridge 169:a7c7b631e539 362 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL))
Anna Bridge 169:a7c7b631e539 363
Anna Bridge 169:a7c7b631e539 364 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 365 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 366 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 367 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 368 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 369 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 370 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 371 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 372 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 373 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 374 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 375 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 376 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 377 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 378 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 379 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Anna Bridge 169:a7c7b631e539 380
Anna Bridge 169:a7c7b631e539 381 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL))
Anna Bridge 169:a7c7b631e539 382 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL))
Anna Bridge 169:a7c7b631e539 383
Anna Bridge 169:a7c7b631e539 384 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
Anna Bridge 169:a7c7b631e539 385 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
Anna Bridge 169:a7c7b631e539 386
Anna Bridge 169:a7c7b631e539 387 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL))
Anna Bridge 169:a7c7b631e539 388 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
Anna Bridge 169:a7c7b631e539 389 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
Anna Bridge 169:a7c7b631e539 390 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
Anna Bridge 169:a7c7b631e539 391
Anna Bridge 169:a7c7b631e539 392 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 393 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 394 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 395 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 396
Anna Bridge 169:a7c7b631e539 397 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL))
Anna Bridge 169:a7c7b631e539 398 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
Anna Bridge 169:a7c7b631e539 399 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
Anna Bridge 169:a7c7b631e539 400 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
Anna Bridge 169:a7c7b631e539 401
Anna Bridge 169:a7c7b631e539 402 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 403 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 404 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 405 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
Anna Bridge 169:a7c7b631e539 406
Anna Bridge 169:a7c7b631e539 407 #define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL))
Anna Bridge 169:a7c7b631e539 408 #define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL))
Anna Bridge 169:a7c7b631e539 409 #define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL))
Anna Bridge 169:a7c7b631e539 410 #define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL))
Anna Bridge 169:a7c7b631e539 411 #define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL))
Anna Bridge 169:a7c7b631e539 412 #define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL))
Anna Bridge 169:a7c7b631e539 413 #define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL))
Anna Bridge 169:a7c7b631e539 414 #define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL))
Anna Bridge 169:a7c7b631e539 415 #define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL))
Anna Bridge 169:a7c7b631e539 416 #define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL))
Anna Bridge 169:a7c7b631e539 417
Anna Bridge 169:a7c7b631e539 418 #define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 419 #define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 420 #define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 421 #define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 422 #define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 423 #define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 424 #define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 425 #define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 426 #define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 427 #define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
Anna Bridge 169:a7c7b631e539 428
Anna Bridge 169:a7c7b631e539 429
Anna Bridge 169:a7c7b631e539 430
Anna Bridge 169:a7c7b631e539 431 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 432 }
Anna Bridge 169:a7c7b631e539 433 #endif
Anna Bridge 169:a7c7b631e539 434
Anna Bridge 169:a7c7b631e539 435 #endif /* _MXC_CLKMAN_REGS_H_ */
Anna Bridge 169:a7c7b631e539 436