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TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/comp_sercom.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for SERCOM
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_SERCOM_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_SERCOM_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR SERCOM */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_SERCOM Serial Communication Interface */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define SERCOM_U2201
AnnaBridge 171:3a7713b1edbc 54 #define REV_SERCOM 0x200
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 61 uint32_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 62 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
AnnaBridge 171:3a7713b1edbc 63 uint32_t :2; /*!< bit: 5.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 64 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
AnnaBridge 171:3a7713b1edbc 65 uint32_t :8; /*!< bit: 8..15 Reserved */
AnnaBridge 171:3a7713b1edbc 66 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
AnnaBridge 171:3a7713b1edbc 67 uint32_t :3; /*!< bit: 17..19 Reserved */
AnnaBridge 171:3a7713b1edbc 68 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
AnnaBridge 171:3a7713b1edbc 69 uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 70 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 71 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
AnnaBridge 171:3a7713b1edbc 72 uint32_t :1; /*!< bit: 26 Reserved */
AnnaBridge 171:3a7713b1edbc 73 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
AnnaBridge 171:3a7713b1edbc 74 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
AnnaBridge 171:3a7713b1edbc 75 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
AnnaBridge 171:3a7713b1edbc 76 uint32_t :1; /*!< bit: 31 Reserved */
AnnaBridge 171:3a7713b1edbc 77 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 78 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 79 } SERCOM_I2CM_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
AnnaBridge 171:3a7713b1edbc 83 #define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
AnnaBridge 171:3a7713b1edbc 86 #define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 87 #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
AnnaBridge 171:3a7713b1edbc 88 #define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 89 #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
AnnaBridge 171:3a7713b1edbc 90 #define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 91 #define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
AnnaBridge 171:3a7713b1edbc 92 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
AnnaBridge 171:3a7713b1edbc 93 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
AnnaBridge 171:3a7713b1edbc 94 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
AnnaBridge 171:3a7713b1edbc 95 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
AnnaBridge 171:3a7713b1edbc 96 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
AnnaBridge 171:3a7713b1edbc 97 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
AnnaBridge 171:3a7713b1edbc 98 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 99 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 100 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 101 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 102 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 103 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 104 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
AnnaBridge 171:3a7713b1edbc 105 #define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
AnnaBridge 171:3a7713b1edbc 106 #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
AnnaBridge 171:3a7713b1edbc 107 #define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
AnnaBridge 171:3a7713b1edbc 108 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
AnnaBridge 171:3a7713b1edbc 109 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
AnnaBridge 171:3a7713b1edbc 110 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
AnnaBridge 171:3a7713b1edbc 111 #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 112 #define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
AnnaBridge 171:3a7713b1edbc 113 #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 114 #define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
AnnaBridge 171:3a7713b1edbc 115 #define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
AnnaBridge 171:3a7713b1edbc 116 #define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
AnnaBridge 171:3a7713b1edbc 117 #define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
AnnaBridge 171:3a7713b1edbc 118 #define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
AnnaBridge 171:3a7713b1edbc 119 #define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
AnnaBridge 171:3a7713b1edbc 120 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
AnnaBridge 171:3a7713b1edbc 121 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
AnnaBridge 171:3a7713b1edbc 122 #define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
AnnaBridge 171:3a7713b1edbc 123 #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
AnnaBridge 171:3a7713b1edbc 124 #define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
AnnaBridge 171:3a7713b1edbc 125 #define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
AnnaBridge 171:3a7713b1edbc 128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 129 typedef union {
AnnaBridge 171:3a7713b1edbc 130 struct {
AnnaBridge 171:3a7713b1edbc 131 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 132 uint32_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 133 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
AnnaBridge 171:3a7713b1edbc 134 uint32_t :2; /*!< bit: 5.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 135 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
AnnaBridge 171:3a7713b1edbc 136 uint32_t :8; /*!< bit: 8..15 Reserved */
AnnaBridge 171:3a7713b1edbc 137 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
AnnaBridge 171:3a7713b1edbc 138 uint32_t :3; /*!< bit: 17..19 Reserved */
AnnaBridge 171:3a7713b1edbc 139 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
AnnaBridge 171:3a7713b1edbc 140 uint32_t :1; /*!< bit: 22 Reserved */
AnnaBridge 171:3a7713b1edbc 141 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 142 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
AnnaBridge 171:3a7713b1edbc 143 uint32_t :1; /*!< bit: 26 Reserved */
AnnaBridge 171:3a7713b1edbc 144 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
AnnaBridge 171:3a7713b1edbc 145 uint32_t :2; /*!< bit: 28..29 Reserved */
AnnaBridge 171:3a7713b1edbc 146 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
AnnaBridge 171:3a7713b1edbc 147 uint32_t :1; /*!< bit: 31 Reserved */
AnnaBridge 171:3a7713b1edbc 148 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 149 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 150 } SERCOM_I2CS_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
AnnaBridge 171:3a7713b1edbc 154 #define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
AnnaBridge 171:3a7713b1edbc 157 #define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 158 #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
AnnaBridge 171:3a7713b1edbc 159 #define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 160 #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
AnnaBridge 171:3a7713b1edbc 161 #define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 162 #define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
AnnaBridge 171:3a7713b1edbc 163 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
AnnaBridge 171:3a7713b1edbc 164 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
AnnaBridge 171:3a7713b1edbc 165 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
AnnaBridge 171:3a7713b1edbc 166 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
AnnaBridge 171:3a7713b1edbc 167 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
AnnaBridge 171:3a7713b1edbc 168 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
AnnaBridge 171:3a7713b1edbc 169 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 170 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 171 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 172 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 173 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 174 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 175 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
AnnaBridge 171:3a7713b1edbc 176 #define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
AnnaBridge 171:3a7713b1edbc 177 #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
AnnaBridge 171:3a7713b1edbc 178 #define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
AnnaBridge 171:3a7713b1edbc 179 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
AnnaBridge 171:3a7713b1edbc 180 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
AnnaBridge 171:3a7713b1edbc 181 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
AnnaBridge 171:3a7713b1edbc 182 #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 183 #define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
AnnaBridge 171:3a7713b1edbc 184 #define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
AnnaBridge 171:3a7713b1edbc 185 #define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
AnnaBridge 171:3a7713b1edbc 186 #define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
AnnaBridge 171:3a7713b1edbc 187 #define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
AnnaBridge 171:3a7713b1edbc 188 #define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
AnnaBridge 171:3a7713b1edbc 189 #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
AnnaBridge 171:3a7713b1edbc 190 #define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
AnnaBridge 171:3a7713b1edbc 191 #define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
AnnaBridge 171:3a7713b1edbc 194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 195 typedef union {
AnnaBridge 171:3a7713b1edbc 196 struct {
AnnaBridge 171:3a7713b1edbc 197 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 198 uint32_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 199 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
AnnaBridge 171:3a7713b1edbc 200 uint32_t :2; /*!< bit: 5.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 201 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
AnnaBridge 171:3a7713b1edbc 202 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
AnnaBridge 171:3a7713b1edbc 203 uint32_t :7; /*!< bit: 9..15 Reserved */
AnnaBridge 171:3a7713b1edbc 204 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
AnnaBridge 171:3a7713b1edbc 205 uint32_t :2; /*!< bit: 18..19 Reserved */
AnnaBridge 171:3a7713b1edbc 206 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
AnnaBridge 171:3a7713b1edbc 207 uint32_t :2; /*!< bit: 22..23 Reserved */
AnnaBridge 171:3a7713b1edbc 208 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
AnnaBridge 171:3a7713b1edbc 209 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
AnnaBridge 171:3a7713b1edbc 210 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
AnnaBridge 171:3a7713b1edbc 211 uint32_t DORD:1; /*!< bit: 30 Data Order */
AnnaBridge 171:3a7713b1edbc 212 uint32_t :1; /*!< bit: 31 Reserved */
AnnaBridge 171:3a7713b1edbc 213 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 214 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 215 } SERCOM_SPI_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 216 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
AnnaBridge 171:3a7713b1edbc 219 #define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
AnnaBridge 171:3a7713b1edbc 222 #define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 223 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
AnnaBridge 171:3a7713b1edbc 224 #define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 225 #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
AnnaBridge 171:3a7713b1edbc 226 #define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 227 #define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
AnnaBridge 171:3a7713b1edbc 228 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
AnnaBridge 171:3a7713b1edbc 229 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
AnnaBridge 171:3a7713b1edbc 230 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
AnnaBridge 171:3a7713b1edbc 231 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
AnnaBridge 171:3a7713b1edbc 232 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
AnnaBridge 171:3a7713b1edbc 233 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
AnnaBridge 171:3a7713b1edbc 234 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 235 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 236 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 237 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 238 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 239 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 240 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
AnnaBridge 171:3a7713b1edbc 241 #define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
AnnaBridge 171:3a7713b1edbc 242 #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
AnnaBridge 171:3a7713b1edbc 243 #define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
AnnaBridge 171:3a7713b1edbc 244 #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
AnnaBridge 171:3a7713b1edbc 245 #define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
AnnaBridge 171:3a7713b1edbc 246 #define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
AnnaBridge 171:3a7713b1edbc 247 #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
AnnaBridge 171:3a7713b1edbc 248 #define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
AnnaBridge 171:3a7713b1edbc 249 #define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
AnnaBridge 171:3a7713b1edbc 250 #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
AnnaBridge 171:3a7713b1edbc 251 #define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
AnnaBridge 171:3a7713b1edbc 252 #define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
AnnaBridge 171:3a7713b1edbc 253 #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
AnnaBridge 171:3a7713b1edbc 254 #define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
AnnaBridge 171:3a7713b1edbc 255 #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
AnnaBridge 171:3a7713b1edbc 256 #define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
AnnaBridge 171:3a7713b1edbc 257 #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
AnnaBridge 171:3a7713b1edbc 258 #define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
AnnaBridge 171:3a7713b1edbc 259 #define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
AnnaBridge 171:3a7713b1edbc 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 263 typedef union {
AnnaBridge 171:3a7713b1edbc 264 struct {
AnnaBridge 171:3a7713b1edbc 265 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
AnnaBridge 171:3a7713b1edbc 266 uint32_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 267 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
AnnaBridge 171:3a7713b1edbc 268 uint32_t :2; /*!< bit: 5.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 269 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
AnnaBridge 171:3a7713b1edbc 270 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
AnnaBridge 171:3a7713b1edbc 271 uint32_t :4; /*!< bit: 9..12 Reserved */
AnnaBridge 171:3a7713b1edbc 272 uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
AnnaBridge 171:3a7713b1edbc 273 uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
AnnaBridge 171:3a7713b1edbc 274 uint32_t :2; /*!< bit: 18..19 Reserved */
AnnaBridge 171:3a7713b1edbc 275 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
AnnaBridge 171:3a7713b1edbc 276 uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
AnnaBridge 171:3a7713b1edbc 277 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
AnnaBridge 171:3a7713b1edbc 278 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
AnnaBridge 171:3a7713b1edbc 279 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
AnnaBridge 171:3a7713b1edbc 280 uint32_t DORD:1; /*!< bit: 30 Data Order */
AnnaBridge 171:3a7713b1edbc 281 uint32_t :1; /*!< bit: 31 Reserved */
AnnaBridge 171:3a7713b1edbc 282 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 283 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 284 } SERCOM_USART_CTRLA_Type;
AnnaBridge 171:3a7713b1edbc 285 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
AnnaBridge 171:3a7713b1edbc 288 #define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
AnnaBridge 171:3a7713b1edbc 289
AnnaBridge 171:3a7713b1edbc 290 #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
AnnaBridge 171:3a7713b1edbc 291 #define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 292 #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
AnnaBridge 171:3a7713b1edbc 293 #define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 294 #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
AnnaBridge 171:3a7713b1edbc 295 #define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 296 #define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
AnnaBridge 171:3a7713b1edbc 297 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
AnnaBridge 171:3a7713b1edbc 298 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
AnnaBridge 171:3a7713b1edbc 299 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
AnnaBridge 171:3a7713b1edbc 300 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
AnnaBridge 171:3a7713b1edbc 301 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
AnnaBridge 171:3a7713b1edbc 302 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
AnnaBridge 171:3a7713b1edbc 303 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 304 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 305 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 306 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 307 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 308 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
AnnaBridge 171:3a7713b1edbc 309 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
AnnaBridge 171:3a7713b1edbc 310 #define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
AnnaBridge 171:3a7713b1edbc 311 #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
AnnaBridge 171:3a7713b1edbc 312 #define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
AnnaBridge 171:3a7713b1edbc 313 #define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
AnnaBridge 171:3a7713b1edbc 314 #define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
AnnaBridge 171:3a7713b1edbc 315 #define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
AnnaBridge 171:3a7713b1edbc 316 #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
AnnaBridge 171:3a7713b1edbc 317 #define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
AnnaBridge 171:3a7713b1edbc 318 #define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
AnnaBridge 171:3a7713b1edbc 319 #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
AnnaBridge 171:3a7713b1edbc 320 #define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
AnnaBridge 171:3a7713b1edbc 321 #define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
AnnaBridge 171:3a7713b1edbc 322 #define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
AnnaBridge 171:3a7713b1edbc 323 #define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
AnnaBridge 171:3a7713b1edbc 324 #define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
AnnaBridge 171:3a7713b1edbc 325 #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
AnnaBridge 171:3a7713b1edbc 326 #define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
AnnaBridge 171:3a7713b1edbc 327 #define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
AnnaBridge 171:3a7713b1edbc 328 #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
AnnaBridge 171:3a7713b1edbc 329 #define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
AnnaBridge 171:3a7713b1edbc 330 #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
AnnaBridge 171:3a7713b1edbc 331 #define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
AnnaBridge 171:3a7713b1edbc 332 #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
AnnaBridge 171:3a7713b1edbc 333 #define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
AnnaBridge 171:3a7713b1edbc 334 #define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
AnnaBridge 171:3a7713b1edbc 337 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 338 typedef union {
AnnaBridge 171:3a7713b1edbc 339 struct {
AnnaBridge 171:3a7713b1edbc 340 uint32_t :8; /*!< bit: 0.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 341 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
AnnaBridge 171:3a7713b1edbc 342 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
AnnaBridge 171:3a7713b1edbc 343 uint32_t :6; /*!< bit: 10..15 Reserved */
AnnaBridge 171:3a7713b1edbc 344 uint32_t CMD:2; /*!< bit: 16..17 Command */
AnnaBridge 171:3a7713b1edbc 345 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
AnnaBridge 171:3a7713b1edbc 346 uint32_t :13; /*!< bit: 19..31 Reserved */
AnnaBridge 171:3a7713b1edbc 347 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 348 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 349 } SERCOM_I2CM_CTRLB_Type;
AnnaBridge 171:3a7713b1edbc 350 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 351
AnnaBridge 171:3a7713b1edbc 352 #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
AnnaBridge 171:3a7713b1edbc 353 #define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
AnnaBridge 171:3a7713b1edbc 354
AnnaBridge 171:3a7713b1edbc 355 #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
AnnaBridge 171:3a7713b1edbc 356 #define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
AnnaBridge 171:3a7713b1edbc 357 #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
AnnaBridge 171:3a7713b1edbc 358 #define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
AnnaBridge 171:3a7713b1edbc 359 #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
AnnaBridge 171:3a7713b1edbc 360 #define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 361 #define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
AnnaBridge 171:3a7713b1edbc 362 #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
AnnaBridge 171:3a7713b1edbc 363 #define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
AnnaBridge 171:3a7713b1edbc 364 #define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
AnnaBridge 171:3a7713b1edbc 367 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 368 typedef union {
AnnaBridge 171:3a7713b1edbc 369 struct {
AnnaBridge 171:3a7713b1edbc 370 uint32_t :8; /*!< bit: 0.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 371 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
AnnaBridge 171:3a7713b1edbc 372 uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
AnnaBridge 171:3a7713b1edbc 373 uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
AnnaBridge 171:3a7713b1edbc 374 uint32_t :3; /*!< bit: 11..13 Reserved */
AnnaBridge 171:3a7713b1edbc 375 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
AnnaBridge 171:3a7713b1edbc 376 uint32_t CMD:2; /*!< bit: 16..17 Command */
AnnaBridge 171:3a7713b1edbc 377 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
AnnaBridge 171:3a7713b1edbc 378 uint32_t :13; /*!< bit: 19..31 Reserved */
AnnaBridge 171:3a7713b1edbc 379 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 380 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 381 } SERCOM_I2CS_CTRLB_Type;
AnnaBridge 171:3a7713b1edbc 382 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 383
AnnaBridge 171:3a7713b1edbc 384 #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
AnnaBridge 171:3a7713b1edbc 385 #define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
AnnaBridge 171:3a7713b1edbc 386
AnnaBridge 171:3a7713b1edbc 387 #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
AnnaBridge 171:3a7713b1edbc 388 #define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
AnnaBridge 171:3a7713b1edbc 389 #define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
AnnaBridge 171:3a7713b1edbc 390 #define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos)
AnnaBridge 171:3a7713b1edbc 391 #define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
AnnaBridge 171:3a7713b1edbc 392 #define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
AnnaBridge 171:3a7713b1edbc 393 #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
AnnaBridge 171:3a7713b1edbc 394 #define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
AnnaBridge 171:3a7713b1edbc 395 #define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
AnnaBridge 171:3a7713b1edbc 396 #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
AnnaBridge 171:3a7713b1edbc 397 #define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
AnnaBridge 171:3a7713b1edbc 398 #define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
AnnaBridge 171:3a7713b1edbc 399 #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
AnnaBridge 171:3a7713b1edbc 400 #define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
AnnaBridge 171:3a7713b1edbc 401 #define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
AnnaBridge 171:3a7713b1edbc 402
AnnaBridge 171:3a7713b1edbc 403 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
AnnaBridge 171:3a7713b1edbc 404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 405 typedef union {
AnnaBridge 171:3a7713b1edbc 406 struct {
AnnaBridge 171:3a7713b1edbc 407 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
AnnaBridge 171:3a7713b1edbc 408 uint32_t :3; /*!< bit: 3.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 409 uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
AnnaBridge 171:3a7713b1edbc 410 uint32_t :2; /*!< bit: 7.. 8 Reserved */
AnnaBridge 171:3a7713b1edbc 411 uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
AnnaBridge 171:3a7713b1edbc 412 uint32_t :3; /*!< bit: 10..12 Reserved */
AnnaBridge 171:3a7713b1edbc 413 uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
AnnaBridge 171:3a7713b1edbc 414 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
AnnaBridge 171:3a7713b1edbc 415 uint32_t :1; /*!< bit: 16 Reserved */
AnnaBridge 171:3a7713b1edbc 416 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
AnnaBridge 171:3a7713b1edbc 417 uint32_t :14; /*!< bit: 18..31 Reserved */
AnnaBridge 171:3a7713b1edbc 418 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 419 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 420 } SERCOM_SPI_CTRLB_Type;
AnnaBridge 171:3a7713b1edbc 421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 422
AnnaBridge 171:3a7713b1edbc 423 #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
AnnaBridge 171:3a7713b1edbc 424 #define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
AnnaBridge 171:3a7713b1edbc 427 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 428 #define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
AnnaBridge 171:3a7713b1edbc 429 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
AnnaBridge 171:3a7713b1edbc 430 #define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
AnnaBridge 171:3a7713b1edbc 431 #define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
AnnaBridge 171:3a7713b1edbc 432 #define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos)
AnnaBridge 171:3a7713b1edbc 433 #define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
AnnaBridge 171:3a7713b1edbc 434 #define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
AnnaBridge 171:3a7713b1edbc 435 #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
AnnaBridge 171:3a7713b1edbc 436 #define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
AnnaBridge 171:3a7713b1edbc 437 #define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
AnnaBridge 171:3a7713b1edbc 438 #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
AnnaBridge 171:3a7713b1edbc 439 #define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
AnnaBridge 171:3a7713b1edbc 440 #define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
AnnaBridge 171:3a7713b1edbc 443 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 444 typedef union {
AnnaBridge 171:3a7713b1edbc 445 struct {
AnnaBridge 171:3a7713b1edbc 446 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
AnnaBridge 171:3a7713b1edbc 447 uint32_t :3; /*!< bit: 3.. 5 Reserved */
AnnaBridge 171:3a7713b1edbc 448 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
AnnaBridge 171:3a7713b1edbc 449 uint32_t :1; /*!< bit: 7 Reserved */
AnnaBridge 171:3a7713b1edbc 450 uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
AnnaBridge 171:3a7713b1edbc 451 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
AnnaBridge 171:3a7713b1edbc 452 uint32_t ENC:1; /*!< bit: 10 Encoding Format */
AnnaBridge 171:3a7713b1edbc 453 uint32_t :2; /*!< bit: 11..12 Reserved */
AnnaBridge 171:3a7713b1edbc 454 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
AnnaBridge 171:3a7713b1edbc 455 uint32_t :2; /*!< bit: 14..15 Reserved */
AnnaBridge 171:3a7713b1edbc 456 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 457 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
AnnaBridge 171:3a7713b1edbc 458 uint32_t :14; /*!< bit: 18..31 Reserved */
AnnaBridge 171:3a7713b1edbc 459 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 460 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 461 } SERCOM_USART_CTRLB_Type;
AnnaBridge 171:3a7713b1edbc 462 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
AnnaBridge 171:3a7713b1edbc 465 #define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
AnnaBridge 171:3a7713b1edbc 468 #define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
AnnaBridge 171:3a7713b1edbc 469 #define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
AnnaBridge 171:3a7713b1edbc 470 #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
AnnaBridge 171:3a7713b1edbc 471 #define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
AnnaBridge 171:3a7713b1edbc 472 #define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
AnnaBridge 171:3a7713b1edbc 473 #define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos)
AnnaBridge 171:3a7713b1edbc 474 #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
AnnaBridge 171:3a7713b1edbc 475 #define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
AnnaBridge 171:3a7713b1edbc 476 #define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
AnnaBridge 171:3a7713b1edbc 477 #define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos)
AnnaBridge 171:3a7713b1edbc 478 #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
AnnaBridge 171:3a7713b1edbc 479 #define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
AnnaBridge 171:3a7713b1edbc 480 #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 481 #define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
AnnaBridge 171:3a7713b1edbc 482 #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
AnnaBridge 171:3a7713b1edbc 483 #define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
AnnaBridge 171:3a7713b1edbc 484 #define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
AnnaBridge 171:3a7713b1edbc 487 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 488 typedef union {
AnnaBridge 171:3a7713b1edbc 489 struct {
AnnaBridge 171:3a7713b1edbc 490 uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 491 uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
AnnaBridge 171:3a7713b1edbc 492 uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 493 uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
AnnaBridge 171:3a7713b1edbc 494 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 495 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 496 } SERCOM_I2CM_BAUD_Type;
AnnaBridge 171:3a7713b1edbc 497 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 498
AnnaBridge 171:3a7713b1edbc 499 #define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
AnnaBridge 171:3a7713b1edbc 500 #define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
AnnaBridge 171:3a7713b1edbc 501
AnnaBridge 171:3a7713b1edbc 502 #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 503 #define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
AnnaBridge 171:3a7713b1edbc 504 #define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
AnnaBridge 171:3a7713b1edbc 505 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
AnnaBridge 171:3a7713b1edbc 506 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
AnnaBridge 171:3a7713b1edbc 507 #define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
AnnaBridge 171:3a7713b1edbc 508 #define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 509 #define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
AnnaBridge 171:3a7713b1edbc 510 #define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
AnnaBridge 171:3a7713b1edbc 511 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
AnnaBridge 171:3a7713b1edbc 512 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
AnnaBridge 171:3a7713b1edbc 513 #define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
AnnaBridge 171:3a7713b1edbc 514 #define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
AnnaBridge 171:3a7713b1edbc 517 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 518 typedef union {
AnnaBridge 171:3a7713b1edbc 519 struct {
AnnaBridge 171:3a7713b1edbc 520 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 521 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 522 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 523 } SERCOM_SPI_BAUD_Type;
AnnaBridge 171:3a7713b1edbc 524 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 525
AnnaBridge 171:3a7713b1edbc 526 #define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
AnnaBridge 171:3a7713b1edbc 527 #define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
AnnaBridge 171:3a7713b1edbc 528
AnnaBridge 171:3a7713b1edbc 529 #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 530 #define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
AnnaBridge 171:3a7713b1edbc 531 #define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
AnnaBridge 171:3a7713b1edbc 532 #define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
AnnaBridge 171:3a7713b1edbc 535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 536 typedef union {
AnnaBridge 171:3a7713b1edbc 537 struct {
AnnaBridge 171:3a7713b1edbc 538 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 539 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 540 struct { // FRAC mode
AnnaBridge 171:3a7713b1edbc 541 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 542 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
AnnaBridge 171:3a7713b1edbc 543 } FRAC; /*!< Structure used for FRAC */
AnnaBridge 171:3a7713b1edbc 544 struct { // FRACFP mode
AnnaBridge 171:3a7713b1edbc 545 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 546 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
AnnaBridge 171:3a7713b1edbc 547 } FRACFP; /*!< Structure used for FRACFP */
AnnaBridge 171:3a7713b1edbc 548 struct { // USARTFP mode
AnnaBridge 171:3a7713b1edbc 549 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 550 } USARTFP; /*!< Structure used for USARTFP */
AnnaBridge 171:3a7713b1edbc 551 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 552 } SERCOM_USART_BAUD_Type;
AnnaBridge 171:3a7713b1edbc 553 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 #define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
AnnaBridge 171:3a7713b1edbc 556 #define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 559 #define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
AnnaBridge 171:3a7713b1edbc 560 #define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
AnnaBridge 171:3a7713b1edbc 561 #define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 // FRAC mode
AnnaBridge 171:3a7713b1edbc 564 #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 565 #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
AnnaBridge 171:3a7713b1edbc 566 #define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
AnnaBridge 171:3a7713b1edbc 567 #define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
AnnaBridge 171:3a7713b1edbc 568 #define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
AnnaBridge 171:3a7713b1edbc 569 #define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
AnnaBridge 171:3a7713b1edbc 570 #define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 // FRACFP mode
AnnaBridge 171:3a7713b1edbc 573 #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 574 #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
AnnaBridge 171:3a7713b1edbc 575 #define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
AnnaBridge 171:3a7713b1edbc 576 #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
AnnaBridge 171:3a7713b1edbc 577 #define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
AnnaBridge 171:3a7713b1edbc 578 #define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
AnnaBridge 171:3a7713b1edbc 579 #define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 // USARTFP mode
AnnaBridge 171:3a7713b1edbc 582 #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
AnnaBridge 171:3a7713b1edbc 583 #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
AnnaBridge 171:3a7713b1edbc 584 #define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
AnnaBridge 171:3a7713b1edbc 585 #define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
AnnaBridge 171:3a7713b1edbc 586
AnnaBridge 171:3a7713b1edbc 587 /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
AnnaBridge 171:3a7713b1edbc 588 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 589 typedef union {
AnnaBridge 171:3a7713b1edbc 590 struct {
AnnaBridge 171:3a7713b1edbc 591 uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
AnnaBridge 171:3a7713b1edbc 592 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 593 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 594 } SERCOM_USART_RXPL_Type;
AnnaBridge 171:3a7713b1edbc 595 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 #define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
AnnaBridge 171:3a7713b1edbc 598 #define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 #define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
AnnaBridge 171:3a7713b1edbc 601 #define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
AnnaBridge 171:3a7713b1edbc 602 #define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
AnnaBridge 171:3a7713b1edbc 603 #define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */
AnnaBridge 171:3a7713b1edbc 604
AnnaBridge 171:3a7713b1edbc 605 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 606 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 607 typedef union {
AnnaBridge 171:3a7713b1edbc 608 struct {
AnnaBridge 171:3a7713b1edbc 609 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 610 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 611 uint8_t :5; /*!< bit: 2.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 612 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 613 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 614 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 615 } SERCOM_I2CM_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 616 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 #define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 619 #define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 622 #define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
AnnaBridge 171:3a7713b1edbc 623 #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 624 #define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
AnnaBridge 171:3a7713b1edbc 625 #define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 626 #define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 627 #define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 628
AnnaBridge 171:3a7713b1edbc 629 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 630 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 631 typedef union {
AnnaBridge 171:3a7713b1edbc 632 struct {
AnnaBridge 171:3a7713b1edbc 633 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 634 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 635 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 636 uint8_t :4; /*!< bit: 3.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 637 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 638 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 639 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 640 } SERCOM_I2CS_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 641 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 #define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 644 #define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 645
AnnaBridge 171:3a7713b1edbc 646 #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 647 #define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
AnnaBridge 171:3a7713b1edbc 648 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 649 #define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
AnnaBridge 171:3a7713b1edbc 650 #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 651 #define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
AnnaBridge 171:3a7713b1edbc 652 #define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 653 #define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 654 #define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 657 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 658 typedef union {
AnnaBridge 171:3a7713b1edbc 659 struct {
AnnaBridge 171:3a7713b1edbc 660 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 661 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 662 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 663 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 664 uint8_t :3; /*!< bit: 4.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 665 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 666 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 667 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 668 } SERCOM_SPI_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 669 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 670
AnnaBridge 171:3a7713b1edbc 671 #define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 672 #define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 673
AnnaBridge 171:3a7713b1edbc 674 #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 675 #define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
AnnaBridge 171:3a7713b1edbc 676 #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 677 #define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
AnnaBridge 171:3a7713b1edbc 678 #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 679 #define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
AnnaBridge 171:3a7713b1edbc 680 #define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 681 #define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos)
AnnaBridge 171:3a7713b1edbc 682 #define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 683 #define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 684 #define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 685
AnnaBridge 171:3a7713b1edbc 686 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 687 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 688 typedef union {
AnnaBridge 171:3a7713b1edbc 689 struct {
AnnaBridge 171:3a7713b1edbc 690 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 691 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 692 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 693 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 694 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 695 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 696 uint8_t :1; /*!< bit: 6 Reserved */
AnnaBridge 171:3a7713b1edbc 697 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 698 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 699 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 700 } SERCOM_USART_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 701 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 702
AnnaBridge 171:3a7713b1edbc 703 #define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 704 #define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 707 #define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
AnnaBridge 171:3a7713b1edbc 708 #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 709 #define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
AnnaBridge 171:3a7713b1edbc 710 #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 711 #define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
AnnaBridge 171:3a7713b1edbc 712 #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 713 #define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
AnnaBridge 171:3a7713b1edbc 714 #define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 715 #define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos)
AnnaBridge 171:3a7713b1edbc 716 #define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 717 #define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos)
AnnaBridge 171:3a7713b1edbc 718 #define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 719 #define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 720 #define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 721
AnnaBridge 171:3a7713b1edbc 722 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 723 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 724 typedef union {
AnnaBridge 171:3a7713b1edbc 725 struct {
AnnaBridge 171:3a7713b1edbc 726 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 727 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 728 uint8_t :5; /*!< bit: 2.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 729 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 730 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 731 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 732 } SERCOM_I2CM_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 733 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 734
AnnaBridge 171:3a7713b1edbc 735 #define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 736 #define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 739 #define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
AnnaBridge 171:3a7713b1edbc 740 #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 741 #define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
AnnaBridge 171:3a7713b1edbc 742 #define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 743 #define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 744 #define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 745
AnnaBridge 171:3a7713b1edbc 746 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 747 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 748 typedef union {
AnnaBridge 171:3a7713b1edbc 749 struct {
AnnaBridge 171:3a7713b1edbc 750 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 751 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 752 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 753 uint8_t :4; /*!< bit: 3.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 754 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 755 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 756 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 757 } SERCOM_I2CS_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 758 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 759
AnnaBridge 171:3a7713b1edbc 760 #define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 761 #define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 762
AnnaBridge 171:3a7713b1edbc 763 #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 764 #define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
AnnaBridge 171:3a7713b1edbc 765 #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 766 #define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
AnnaBridge 171:3a7713b1edbc 767 #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 768 #define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
AnnaBridge 171:3a7713b1edbc 769 #define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 770 #define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 771 #define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 774 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 775 typedef union {
AnnaBridge 171:3a7713b1edbc 776 struct {
AnnaBridge 171:3a7713b1edbc 777 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 778 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 779 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 780 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 781 uint8_t :3; /*!< bit: 4.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 782 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 783 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 784 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 785 } SERCOM_SPI_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 786 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 787
AnnaBridge 171:3a7713b1edbc 788 #define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 789 #define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 790
AnnaBridge 171:3a7713b1edbc 791 #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 792 #define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
AnnaBridge 171:3a7713b1edbc 793 #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 794 #define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
AnnaBridge 171:3a7713b1edbc 795 #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 796 #define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
AnnaBridge 171:3a7713b1edbc 797 #define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 798 #define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos)
AnnaBridge 171:3a7713b1edbc 799 #define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 800 #define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 801 #define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 802
AnnaBridge 171:3a7713b1edbc 803 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 804 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 805 typedef union {
AnnaBridge 171:3a7713b1edbc 806 struct {
AnnaBridge 171:3a7713b1edbc 807 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 808 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 809 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 810 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 811 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 812 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 813 uint8_t :1; /*!< bit: 6 Reserved */
AnnaBridge 171:3a7713b1edbc 814 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 815 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 816 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 817 } SERCOM_USART_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 818 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 819
AnnaBridge 171:3a7713b1edbc 820 #define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 821 #define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 822
AnnaBridge 171:3a7713b1edbc 823 #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 824 #define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
AnnaBridge 171:3a7713b1edbc 825 #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 826 #define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
AnnaBridge 171:3a7713b1edbc 827 #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 828 #define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
AnnaBridge 171:3a7713b1edbc 829 #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 830 #define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
AnnaBridge 171:3a7713b1edbc 831 #define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 832 #define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos)
AnnaBridge 171:3a7713b1edbc 833 #define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 834 #define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos)
AnnaBridge 171:3a7713b1edbc 835 #define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 836 #define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 837 #define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 838
AnnaBridge 171:3a7713b1edbc 839 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 840 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 841 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 842 struct {
AnnaBridge 171:3a7713b1edbc 843 __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
AnnaBridge 171:3a7713b1edbc 844 __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
AnnaBridge 171:3a7713b1edbc 845 __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 846 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
AnnaBridge 171:3a7713b1edbc 847 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 848 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 849 } SERCOM_I2CM_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 850 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 851
AnnaBridge 171:3a7713b1edbc 852 #define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 853 #define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 854
AnnaBridge 171:3a7713b1edbc 855 #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
AnnaBridge 171:3a7713b1edbc 856 #define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
AnnaBridge 171:3a7713b1edbc 857 #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
AnnaBridge 171:3a7713b1edbc 858 #define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
AnnaBridge 171:3a7713b1edbc 859 #define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
AnnaBridge 171:3a7713b1edbc 860 #define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 861 #define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 862
AnnaBridge 171:3a7713b1edbc 863 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 864 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 865 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 866 struct {
AnnaBridge 171:3a7713b1edbc 867 __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
AnnaBridge 171:3a7713b1edbc 868 __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
AnnaBridge 171:3a7713b1edbc 869 __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
AnnaBridge 171:3a7713b1edbc 870 __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 871 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
AnnaBridge 171:3a7713b1edbc 872 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 873 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 874 } SERCOM_I2CS_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 875 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 876
AnnaBridge 171:3a7713b1edbc 877 #define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 878 #define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 879
AnnaBridge 171:3a7713b1edbc 880 #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
AnnaBridge 171:3a7713b1edbc 881 #define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
AnnaBridge 171:3a7713b1edbc 882 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
AnnaBridge 171:3a7713b1edbc 883 #define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
AnnaBridge 171:3a7713b1edbc 884 #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
AnnaBridge 171:3a7713b1edbc 885 #define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
AnnaBridge 171:3a7713b1edbc 886 #define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
AnnaBridge 171:3a7713b1edbc 887 #define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 888 #define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 889
AnnaBridge 171:3a7713b1edbc 890 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 891 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 892 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 893 struct {
AnnaBridge 171:3a7713b1edbc 894 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
AnnaBridge 171:3a7713b1edbc 895 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
AnnaBridge 171:3a7713b1edbc 896 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
AnnaBridge 171:3a7713b1edbc 897 __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 898 __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 899 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
AnnaBridge 171:3a7713b1edbc 900 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 901 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 902 } SERCOM_SPI_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 903 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 904
AnnaBridge 171:3a7713b1edbc 905 #define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 906 #define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 907
AnnaBridge 171:3a7713b1edbc 908 #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
AnnaBridge 171:3a7713b1edbc 909 #define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
AnnaBridge 171:3a7713b1edbc 910 #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
AnnaBridge 171:3a7713b1edbc 911 #define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
AnnaBridge 171:3a7713b1edbc 912 #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
AnnaBridge 171:3a7713b1edbc 913 #define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
AnnaBridge 171:3a7713b1edbc 914 #define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 915 #define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos)
AnnaBridge 171:3a7713b1edbc 916 #define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
AnnaBridge 171:3a7713b1edbc 917 #define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 918 #define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 919
AnnaBridge 171:3a7713b1edbc 920 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 921 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 922 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 923 struct {
AnnaBridge 171:3a7713b1edbc 924 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
AnnaBridge 171:3a7713b1edbc 925 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
AnnaBridge 171:3a7713b1edbc 926 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
AnnaBridge 171:3a7713b1edbc 927 __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
AnnaBridge 171:3a7713b1edbc 928 __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
AnnaBridge 171:3a7713b1edbc 929 __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
AnnaBridge 171:3a7713b1edbc 930 __I uint8_t :1; /*!< bit: 6 Reserved */
AnnaBridge 171:3a7713b1edbc 931 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
AnnaBridge 171:3a7713b1edbc 932 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 933 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 934 } SERCOM_USART_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 935 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 #define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 938 #define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 939
AnnaBridge 171:3a7713b1edbc 940 #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
AnnaBridge 171:3a7713b1edbc 941 #define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
AnnaBridge 171:3a7713b1edbc 942 #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
AnnaBridge 171:3a7713b1edbc 943 #define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
AnnaBridge 171:3a7713b1edbc 944 #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
AnnaBridge 171:3a7713b1edbc 945 #define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
AnnaBridge 171:3a7713b1edbc 946 #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
AnnaBridge 171:3a7713b1edbc 947 #define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
AnnaBridge 171:3a7713b1edbc 948 #define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
AnnaBridge 171:3a7713b1edbc 949 #define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos)
AnnaBridge 171:3a7713b1edbc 950 #define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
AnnaBridge 171:3a7713b1edbc 951 #define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos)
AnnaBridge 171:3a7713b1edbc 952 #define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
AnnaBridge 171:3a7713b1edbc 953 #define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos)
AnnaBridge 171:3a7713b1edbc 954 #define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 955
AnnaBridge 171:3a7713b1edbc 956 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
AnnaBridge 171:3a7713b1edbc 957 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 958 typedef union {
AnnaBridge 171:3a7713b1edbc 959 struct {
AnnaBridge 171:3a7713b1edbc 960 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
AnnaBridge 171:3a7713b1edbc 961 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
AnnaBridge 171:3a7713b1edbc 962 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
AnnaBridge 171:3a7713b1edbc 963 uint16_t :1; /*!< bit: 3 Reserved */
AnnaBridge 171:3a7713b1edbc 964 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
AnnaBridge 171:3a7713b1edbc 965 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
AnnaBridge 171:3a7713b1edbc 966 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
AnnaBridge 171:3a7713b1edbc 967 uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 968 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 969 uint16_t LENERR:1; /*!< bit: 10 Length Error */
AnnaBridge 171:3a7713b1edbc 970 uint16_t :5; /*!< bit: 11..15 Reserved */
AnnaBridge 171:3a7713b1edbc 971 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 972 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 973 } SERCOM_I2CM_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 974 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 #define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
AnnaBridge 171:3a7713b1edbc 977 #define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
AnnaBridge 171:3a7713b1edbc 978
AnnaBridge 171:3a7713b1edbc 979 #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
AnnaBridge 171:3a7713b1edbc 980 #define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
AnnaBridge 171:3a7713b1edbc 981 #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
AnnaBridge 171:3a7713b1edbc 982 #define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
AnnaBridge 171:3a7713b1edbc 983 #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
AnnaBridge 171:3a7713b1edbc 984 #define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
AnnaBridge 171:3a7713b1edbc 985 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
AnnaBridge 171:3a7713b1edbc 986 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
AnnaBridge 171:3a7713b1edbc 987 #define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
AnnaBridge 171:3a7713b1edbc 988 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
AnnaBridge 171:3a7713b1edbc 989 #define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
AnnaBridge 171:3a7713b1edbc 990 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
AnnaBridge 171:3a7713b1edbc 991 #define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
AnnaBridge 171:3a7713b1edbc 992 #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 993 #define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
AnnaBridge 171:3a7713b1edbc 994 #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 995 #define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
AnnaBridge 171:3a7713b1edbc 996 #define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
AnnaBridge 171:3a7713b1edbc 997 #define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos)
AnnaBridge 171:3a7713b1edbc 998 #define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 999
AnnaBridge 171:3a7713b1edbc 1000 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
AnnaBridge 171:3a7713b1edbc 1001 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1002 typedef union {
AnnaBridge 171:3a7713b1edbc 1003 struct {
AnnaBridge 171:3a7713b1edbc 1004 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
AnnaBridge 171:3a7713b1edbc 1005 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
AnnaBridge 171:3a7713b1edbc 1006 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
AnnaBridge 171:3a7713b1edbc 1007 uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
AnnaBridge 171:3a7713b1edbc 1008 uint16_t SR:1; /*!< bit: 4 Repeated Start */
AnnaBridge 171:3a7713b1edbc 1009 uint16_t :1; /*!< bit: 5 Reserved */
AnnaBridge 171:3a7713b1edbc 1010 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
AnnaBridge 171:3a7713b1edbc 1011 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
AnnaBridge 171:3a7713b1edbc 1012 uint16_t :1; /*!< bit: 8 Reserved */
AnnaBridge 171:3a7713b1edbc 1013 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 1014 uint16_t HS:1; /*!< bit: 10 High Speed */
AnnaBridge 171:3a7713b1edbc 1015 uint16_t :5; /*!< bit: 11..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1016 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1017 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1018 } SERCOM_I2CS_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 1019 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1020
AnnaBridge 171:3a7713b1edbc 1021 #define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
AnnaBridge 171:3a7713b1edbc 1022 #define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
AnnaBridge 171:3a7713b1edbc 1023
AnnaBridge 171:3a7713b1edbc 1024 #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
AnnaBridge 171:3a7713b1edbc 1025 #define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
AnnaBridge 171:3a7713b1edbc 1026 #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
AnnaBridge 171:3a7713b1edbc 1027 #define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
AnnaBridge 171:3a7713b1edbc 1028 #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
AnnaBridge 171:3a7713b1edbc 1029 #define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
AnnaBridge 171:3a7713b1edbc 1030 #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
AnnaBridge 171:3a7713b1edbc 1031 #define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
AnnaBridge 171:3a7713b1edbc 1032 #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
AnnaBridge 171:3a7713b1edbc 1033 #define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
AnnaBridge 171:3a7713b1edbc 1034 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
AnnaBridge 171:3a7713b1edbc 1035 #define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
AnnaBridge 171:3a7713b1edbc 1036 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
AnnaBridge 171:3a7713b1edbc 1037 #define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
AnnaBridge 171:3a7713b1edbc 1038 #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
AnnaBridge 171:3a7713b1edbc 1039 #define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
AnnaBridge 171:3a7713b1edbc 1040 #define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
AnnaBridge 171:3a7713b1edbc 1041 #define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos)
AnnaBridge 171:3a7713b1edbc 1042 #define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 1043
AnnaBridge 171:3a7713b1edbc 1044 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
AnnaBridge 171:3a7713b1edbc 1045 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1046 typedef union {
AnnaBridge 171:3a7713b1edbc 1047 struct {
AnnaBridge 171:3a7713b1edbc 1048 uint16_t :2; /*!< bit: 0.. 1 Reserved */
AnnaBridge 171:3a7713b1edbc 1049 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
AnnaBridge 171:3a7713b1edbc 1050 uint16_t :13; /*!< bit: 3..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1051 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1052 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1053 } SERCOM_SPI_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 1054 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1055
AnnaBridge 171:3a7713b1edbc 1056 #define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
AnnaBridge 171:3a7713b1edbc 1057 #define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
AnnaBridge 171:3a7713b1edbc 1058
AnnaBridge 171:3a7713b1edbc 1059 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
AnnaBridge 171:3a7713b1edbc 1060 #define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
AnnaBridge 171:3a7713b1edbc 1061 #define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 1062
AnnaBridge 171:3a7713b1edbc 1063 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
AnnaBridge 171:3a7713b1edbc 1064 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1065 typedef union {
AnnaBridge 171:3a7713b1edbc 1066 struct {
AnnaBridge 171:3a7713b1edbc 1067 uint16_t PERR:1; /*!< bit: 0 Parity Error */
AnnaBridge 171:3a7713b1edbc 1068 uint16_t FERR:1; /*!< bit: 1 Frame Error */
AnnaBridge 171:3a7713b1edbc 1069 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
AnnaBridge 171:3a7713b1edbc 1070 uint16_t CTS:1; /*!< bit: 3 Clear To Send */
AnnaBridge 171:3a7713b1edbc 1071 uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
AnnaBridge 171:3a7713b1edbc 1072 uint16_t COLL:1; /*!< bit: 5 Collision Detected */
AnnaBridge 171:3a7713b1edbc 1073 uint16_t :10; /*!< bit: 6..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1074 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1075 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1076 } SERCOM_USART_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 1077 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1078
AnnaBridge 171:3a7713b1edbc 1079 #define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
AnnaBridge 171:3a7713b1edbc 1080 #define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
AnnaBridge 171:3a7713b1edbc 1081
AnnaBridge 171:3a7713b1edbc 1082 #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
AnnaBridge 171:3a7713b1edbc 1083 #define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
AnnaBridge 171:3a7713b1edbc 1084 #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
AnnaBridge 171:3a7713b1edbc 1085 #define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
AnnaBridge 171:3a7713b1edbc 1086 #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
AnnaBridge 171:3a7713b1edbc 1087 #define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
AnnaBridge 171:3a7713b1edbc 1088 #define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
AnnaBridge 171:3a7713b1edbc 1089 #define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos)
AnnaBridge 171:3a7713b1edbc 1090 #define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
AnnaBridge 171:3a7713b1edbc 1091 #define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos)
AnnaBridge 171:3a7713b1edbc 1092 #define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
AnnaBridge 171:3a7713b1edbc 1093 #define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
AnnaBridge 171:3a7713b1edbc 1094 #define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 1095
AnnaBridge 171:3a7713b1edbc 1096 /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
AnnaBridge 171:3a7713b1edbc 1097 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1098 typedef union {
AnnaBridge 171:3a7713b1edbc 1099 struct {
AnnaBridge 171:3a7713b1edbc 1100 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1101 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1102 uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1103 uint32_t :29; /*!< bit: 3..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1104 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1105 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1106 } SERCOM_I2CM_SYNCBUSY_Type;
AnnaBridge 171:3a7713b1edbc 1107 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1108
AnnaBridge 171:3a7713b1edbc 1109 #define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
AnnaBridge 171:3a7713b1edbc 1110 #define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
AnnaBridge 171:3a7713b1edbc 1111
AnnaBridge 171:3a7713b1edbc 1112 #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1113 #define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 1114 #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1115 #define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 1116 #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1117 #define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
AnnaBridge 171:3a7713b1edbc 1118 #define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
AnnaBridge 171:3a7713b1edbc 1119
AnnaBridge 171:3a7713b1edbc 1120 /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
AnnaBridge 171:3a7713b1edbc 1121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1122 typedef union {
AnnaBridge 171:3a7713b1edbc 1123 struct {
AnnaBridge 171:3a7713b1edbc 1124 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1125 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1126 uint32_t :30; /*!< bit: 2..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1127 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1128 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1129 } SERCOM_I2CS_SYNCBUSY_Type;
AnnaBridge 171:3a7713b1edbc 1130 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1131
AnnaBridge 171:3a7713b1edbc 1132 #define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
AnnaBridge 171:3a7713b1edbc 1133 #define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
AnnaBridge 171:3a7713b1edbc 1134
AnnaBridge 171:3a7713b1edbc 1135 #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1136 #define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 1137 #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1138 #define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 1139 #define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
AnnaBridge 171:3a7713b1edbc 1140
AnnaBridge 171:3a7713b1edbc 1141 /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
AnnaBridge 171:3a7713b1edbc 1142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1143 typedef union {
AnnaBridge 171:3a7713b1edbc 1144 struct {
AnnaBridge 171:3a7713b1edbc 1145 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1146 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1147 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1148 uint32_t :29; /*!< bit: 3..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1149 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1150 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1151 } SERCOM_SPI_SYNCBUSY_Type;
AnnaBridge 171:3a7713b1edbc 1152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1153
AnnaBridge 171:3a7713b1edbc 1154 #define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
AnnaBridge 171:3a7713b1edbc 1155 #define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
AnnaBridge 171:3a7713b1edbc 1156
AnnaBridge 171:3a7713b1edbc 1157 #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1158 #define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 1159 #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1160 #define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 1161 #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1162 #define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
AnnaBridge 171:3a7713b1edbc 1163 #define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
AnnaBridge 171:3a7713b1edbc 1164
AnnaBridge 171:3a7713b1edbc 1165 /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
AnnaBridge 171:3a7713b1edbc 1166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1167 typedef union {
AnnaBridge 171:3a7713b1edbc 1168 struct {
AnnaBridge 171:3a7713b1edbc 1169 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1170 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1171 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1172 uint32_t :29; /*!< bit: 3..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1173 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1174 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1175 } SERCOM_USART_SYNCBUSY_Type;
AnnaBridge 171:3a7713b1edbc 1176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1177
AnnaBridge 171:3a7713b1edbc 1178 #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
AnnaBridge 171:3a7713b1edbc 1179 #define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
AnnaBridge 171:3a7713b1edbc 1180
AnnaBridge 171:3a7713b1edbc 1181 #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1182 #define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
AnnaBridge 171:3a7713b1edbc 1183 #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1184 #define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 1185 #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 1186 #define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
AnnaBridge 171:3a7713b1edbc 1187 #define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
AnnaBridge 171:3a7713b1edbc 1190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1191 typedef union {
AnnaBridge 171:3a7713b1edbc 1192 struct {
AnnaBridge 171:3a7713b1edbc 1193 uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
AnnaBridge 171:3a7713b1edbc 1194 uint32_t :2; /*!< bit: 11..12 Reserved */
AnnaBridge 171:3a7713b1edbc 1195 uint32_t LENEN:1; /*!< bit: 13 Length Enable */
AnnaBridge 171:3a7713b1edbc 1196 uint32_t HS:1; /*!< bit: 14 High Speed Mode */
AnnaBridge 171:3a7713b1edbc 1197 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
AnnaBridge 171:3a7713b1edbc 1198 uint32_t LEN:8; /*!< bit: 16..23 Length */
AnnaBridge 171:3a7713b1edbc 1199 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1200 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1201 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1202 } SERCOM_I2CM_ADDR_Type;
AnnaBridge 171:3a7713b1edbc 1203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1204
AnnaBridge 171:3a7713b1edbc 1205 #define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
AnnaBridge 171:3a7713b1edbc 1206 #define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
AnnaBridge 171:3a7713b1edbc 1207
AnnaBridge 171:3a7713b1edbc 1208 #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
AnnaBridge 171:3a7713b1edbc 1209 #define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
AnnaBridge 171:3a7713b1edbc 1210 #define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
AnnaBridge 171:3a7713b1edbc 1211 #define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
AnnaBridge 171:3a7713b1edbc 1212 #define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
AnnaBridge 171:3a7713b1edbc 1213 #define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
AnnaBridge 171:3a7713b1edbc 1214 #define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos)
AnnaBridge 171:3a7713b1edbc 1215 #define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
AnnaBridge 171:3a7713b1edbc 1216 #define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
AnnaBridge 171:3a7713b1edbc 1217 #define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
AnnaBridge 171:3a7713b1edbc 1218 #define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
AnnaBridge 171:3a7713b1edbc 1219 #define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
AnnaBridge 171:3a7713b1edbc 1220 #define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 1221
AnnaBridge 171:3a7713b1edbc 1222 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
AnnaBridge 171:3a7713b1edbc 1223 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1224 typedef union {
AnnaBridge 171:3a7713b1edbc 1225 struct {
AnnaBridge 171:3a7713b1edbc 1226 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
AnnaBridge 171:3a7713b1edbc 1227 uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
AnnaBridge 171:3a7713b1edbc 1228 uint32_t :4; /*!< bit: 11..14 Reserved */
AnnaBridge 171:3a7713b1edbc 1229 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
AnnaBridge 171:3a7713b1edbc 1230 uint32_t :1; /*!< bit: 16 Reserved */
AnnaBridge 171:3a7713b1edbc 1231 uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
AnnaBridge 171:3a7713b1edbc 1232 uint32_t :5; /*!< bit: 27..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1233 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1234 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1235 } SERCOM_I2CS_ADDR_Type;
AnnaBridge 171:3a7713b1edbc 1236 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1237
AnnaBridge 171:3a7713b1edbc 1238 #define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
AnnaBridge 171:3a7713b1edbc 1239 #define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
AnnaBridge 171:3a7713b1edbc 1240
AnnaBridge 171:3a7713b1edbc 1241 #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
AnnaBridge 171:3a7713b1edbc 1242 #define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
AnnaBridge 171:3a7713b1edbc 1243 #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
AnnaBridge 171:3a7713b1edbc 1244 #define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
AnnaBridge 171:3a7713b1edbc 1245 #define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
AnnaBridge 171:3a7713b1edbc 1246 #define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
AnnaBridge 171:3a7713b1edbc 1247 #define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
AnnaBridge 171:3a7713b1edbc 1248 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
AnnaBridge 171:3a7713b1edbc 1249 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
AnnaBridge 171:3a7713b1edbc 1250 #define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
AnnaBridge 171:3a7713b1edbc 1251 #define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 1252
AnnaBridge 171:3a7713b1edbc 1253 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
AnnaBridge 171:3a7713b1edbc 1254 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1255 typedef union {
AnnaBridge 171:3a7713b1edbc 1256 struct {
AnnaBridge 171:3a7713b1edbc 1257 uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
AnnaBridge 171:3a7713b1edbc 1258 uint32_t :8; /*!< bit: 8..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1259 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
AnnaBridge 171:3a7713b1edbc 1260 uint32_t :8; /*!< bit: 24..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1261 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1262 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1263 } SERCOM_SPI_ADDR_Type;
AnnaBridge 171:3a7713b1edbc 1264 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1265
AnnaBridge 171:3a7713b1edbc 1266 #define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
AnnaBridge 171:3a7713b1edbc 1267 #define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
AnnaBridge 171:3a7713b1edbc 1268
AnnaBridge 171:3a7713b1edbc 1269 #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
AnnaBridge 171:3a7713b1edbc 1270 #define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
AnnaBridge 171:3a7713b1edbc 1271 #define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
AnnaBridge 171:3a7713b1edbc 1272 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
AnnaBridge 171:3a7713b1edbc 1273 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
AnnaBridge 171:3a7713b1edbc 1274 #define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
AnnaBridge 171:3a7713b1edbc 1275 #define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
AnnaBridge 171:3a7713b1edbc 1276
AnnaBridge 171:3a7713b1edbc 1277 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
AnnaBridge 171:3a7713b1edbc 1278 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1279 typedef union {
AnnaBridge 171:3a7713b1edbc 1280 struct {
AnnaBridge 171:3a7713b1edbc 1281 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
AnnaBridge 171:3a7713b1edbc 1282 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1283 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1284 } SERCOM_I2CM_DATA_Type;
AnnaBridge 171:3a7713b1edbc 1285 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1286
AnnaBridge 171:3a7713b1edbc 1287 #define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
AnnaBridge 171:3a7713b1edbc 1288 #define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
AnnaBridge 171:3a7713b1edbc 1289
AnnaBridge 171:3a7713b1edbc 1290 #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
AnnaBridge 171:3a7713b1edbc 1291 #define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
AnnaBridge 171:3a7713b1edbc 1292 #define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
AnnaBridge 171:3a7713b1edbc 1293 #define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */
AnnaBridge 171:3a7713b1edbc 1294
AnnaBridge 171:3a7713b1edbc 1295 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
AnnaBridge 171:3a7713b1edbc 1296 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1297 typedef union {
AnnaBridge 171:3a7713b1edbc 1298 struct {
AnnaBridge 171:3a7713b1edbc 1299 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
AnnaBridge 171:3a7713b1edbc 1300 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1301 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1302 } SERCOM_I2CS_DATA_Type;
AnnaBridge 171:3a7713b1edbc 1303 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1304
AnnaBridge 171:3a7713b1edbc 1305 #define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
AnnaBridge 171:3a7713b1edbc 1306 #define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
AnnaBridge 171:3a7713b1edbc 1307
AnnaBridge 171:3a7713b1edbc 1308 #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
AnnaBridge 171:3a7713b1edbc 1309 #define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
AnnaBridge 171:3a7713b1edbc 1310 #define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
AnnaBridge 171:3a7713b1edbc 1311 #define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */
AnnaBridge 171:3a7713b1edbc 1312
AnnaBridge 171:3a7713b1edbc 1313 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
AnnaBridge 171:3a7713b1edbc 1314 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1315 typedef union {
AnnaBridge 171:3a7713b1edbc 1316 struct {
AnnaBridge 171:3a7713b1edbc 1317 uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
AnnaBridge 171:3a7713b1edbc 1318 uint32_t :23; /*!< bit: 9..31 Reserved */
AnnaBridge 171:3a7713b1edbc 1319 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1320 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1321 } SERCOM_SPI_DATA_Type;
AnnaBridge 171:3a7713b1edbc 1322 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1323
AnnaBridge 171:3a7713b1edbc 1324 #define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
AnnaBridge 171:3a7713b1edbc 1325 #define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
AnnaBridge 171:3a7713b1edbc 1326
AnnaBridge 171:3a7713b1edbc 1327 #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
AnnaBridge 171:3a7713b1edbc 1328 #define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
AnnaBridge 171:3a7713b1edbc 1329 #define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
AnnaBridge 171:3a7713b1edbc 1330 #define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
AnnaBridge 171:3a7713b1edbc 1331
AnnaBridge 171:3a7713b1edbc 1332 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
AnnaBridge 171:3a7713b1edbc 1333 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1334 typedef union {
AnnaBridge 171:3a7713b1edbc 1335 struct {
AnnaBridge 171:3a7713b1edbc 1336 uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
AnnaBridge 171:3a7713b1edbc 1337 uint16_t :7; /*!< bit: 9..15 Reserved */
AnnaBridge 171:3a7713b1edbc 1338 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1339 uint16_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1340 } SERCOM_USART_DATA_Type;
AnnaBridge 171:3a7713b1edbc 1341 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1342
AnnaBridge 171:3a7713b1edbc 1343 #define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
AnnaBridge 171:3a7713b1edbc 1344 #define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
AnnaBridge 171:3a7713b1edbc 1345
AnnaBridge 171:3a7713b1edbc 1346 #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
AnnaBridge 171:3a7713b1edbc 1347 #define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
AnnaBridge 171:3a7713b1edbc 1348 #define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
AnnaBridge 171:3a7713b1edbc 1349 #define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */
AnnaBridge 171:3a7713b1edbc 1350
AnnaBridge 171:3a7713b1edbc 1351 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
AnnaBridge 171:3a7713b1edbc 1352 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1353 typedef union {
AnnaBridge 171:3a7713b1edbc 1354 struct {
AnnaBridge 171:3a7713b1edbc 1355 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
AnnaBridge 171:3a7713b1edbc 1356 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 1357 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1358 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1359 } SERCOM_I2CM_DBGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 1360 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1361
AnnaBridge 171:3a7713b1edbc 1362 #define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
AnnaBridge 171:3a7713b1edbc 1363 #define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
AnnaBridge 171:3a7713b1edbc 1364
AnnaBridge 171:3a7713b1edbc 1365 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
AnnaBridge 171:3a7713b1edbc 1366 #define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
AnnaBridge 171:3a7713b1edbc 1367 #define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 1368
AnnaBridge 171:3a7713b1edbc 1369 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
AnnaBridge 171:3a7713b1edbc 1370 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1371 typedef union {
AnnaBridge 171:3a7713b1edbc 1372 struct {
AnnaBridge 171:3a7713b1edbc 1373 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
AnnaBridge 171:3a7713b1edbc 1374 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 1375 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1376 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1377 } SERCOM_SPI_DBGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 1378 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1379
AnnaBridge 171:3a7713b1edbc 1380 #define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
AnnaBridge 171:3a7713b1edbc 1381 #define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
AnnaBridge 171:3a7713b1edbc 1382
AnnaBridge 171:3a7713b1edbc 1383 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
AnnaBridge 171:3a7713b1edbc 1384 #define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
AnnaBridge 171:3a7713b1edbc 1385 #define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 1386
AnnaBridge 171:3a7713b1edbc 1387 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
AnnaBridge 171:3a7713b1edbc 1388 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1389 typedef union {
AnnaBridge 171:3a7713b1edbc 1390 struct {
AnnaBridge 171:3a7713b1edbc 1391 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
AnnaBridge 171:3a7713b1edbc 1392 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 1393 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 1394 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 1395 } SERCOM_USART_DBGCTRL_Type;
AnnaBridge 171:3a7713b1edbc 1396 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1397
AnnaBridge 171:3a7713b1edbc 1398 #define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
AnnaBridge 171:3a7713b1edbc 1399 #define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
AnnaBridge 171:3a7713b1edbc 1400
AnnaBridge 171:3a7713b1edbc 1401 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
AnnaBridge 171:3a7713b1edbc 1402 #define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
AnnaBridge 171:3a7713b1edbc 1403 #define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 1404
AnnaBridge 171:3a7713b1edbc 1405 /** \brief SERCOM_I2CM hardware registers */
AnnaBridge 171:3a7713b1edbc 1406 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1407 typedef struct { /* I2C Master Mode */
AnnaBridge 171:3a7713b1edbc 1408 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
AnnaBridge 171:3a7713b1edbc 1409 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
AnnaBridge 171:3a7713b1edbc 1410 RoReg8 Reserved1[0x4];
AnnaBridge 171:3a7713b1edbc 1411 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
AnnaBridge 171:3a7713b1edbc 1412 RoReg8 Reserved2[0x4];
AnnaBridge 171:3a7713b1edbc 1413 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 1414 RoReg8 Reserved3[0x1];
AnnaBridge 171:3a7713b1edbc 1415 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 1416 RoReg8 Reserved4[0x1];
AnnaBridge 171:3a7713b1edbc 1417 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1418 RoReg8 Reserved5[0x1];
AnnaBridge 171:3a7713b1edbc 1419 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
AnnaBridge 171:3a7713b1edbc 1420 __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
AnnaBridge 171:3a7713b1edbc 1421 RoReg8 Reserved6[0x4];
AnnaBridge 171:3a7713b1edbc 1422 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
AnnaBridge 171:3a7713b1edbc 1423 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
AnnaBridge 171:3a7713b1edbc 1424 RoReg8 Reserved7[0x7];
AnnaBridge 171:3a7713b1edbc 1425 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
AnnaBridge 171:3a7713b1edbc 1426 } SercomI2cm;
AnnaBridge 171:3a7713b1edbc 1427 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1428
AnnaBridge 171:3a7713b1edbc 1429 /** \brief SERCOM_I2CS hardware registers */
AnnaBridge 171:3a7713b1edbc 1430 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1431 typedef struct { /* I2C Slave Mode */
AnnaBridge 171:3a7713b1edbc 1432 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
AnnaBridge 171:3a7713b1edbc 1433 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
AnnaBridge 171:3a7713b1edbc 1434 RoReg8 Reserved1[0xC];
AnnaBridge 171:3a7713b1edbc 1435 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 1436 RoReg8 Reserved2[0x1];
AnnaBridge 171:3a7713b1edbc 1437 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 1438 RoReg8 Reserved3[0x1];
AnnaBridge 171:3a7713b1edbc 1439 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1440 RoReg8 Reserved4[0x1];
AnnaBridge 171:3a7713b1edbc 1441 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
AnnaBridge 171:3a7713b1edbc 1442 __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
AnnaBridge 171:3a7713b1edbc 1443 RoReg8 Reserved5[0x4];
AnnaBridge 171:3a7713b1edbc 1444 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
AnnaBridge 171:3a7713b1edbc 1445 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
AnnaBridge 171:3a7713b1edbc 1446 } SercomI2cs;
AnnaBridge 171:3a7713b1edbc 1447 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1448
AnnaBridge 171:3a7713b1edbc 1449 /** \brief SERCOM_SPI hardware registers */
AnnaBridge 171:3a7713b1edbc 1450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1451 typedef struct { /* SPI Mode */
AnnaBridge 171:3a7713b1edbc 1452 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
AnnaBridge 171:3a7713b1edbc 1453 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
AnnaBridge 171:3a7713b1edbc 1454 RoReg8 Reserved1[0x4];
AnnaBridge 171:3a7713b1edbc 1455 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
AnnaBridge 171:3a7713b1edbc 1456 RoReg8 Reserved2[0x7];
AnnaBridge 171:3a7713b1edbc 1457 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 1458 RoReg8 Reserved3[0x1];
AnnaBridge 171:3a7713b1edbc 1459 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 1460 RoReg8 Reserved4[0x1];
AnnaBridge 171:3a7713b1edbc 1461 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1462 RoReg8 Reserved5[0x1];
AnnaBridge 171:3a7713b1edbc 1463 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
AnnaBridge 171:3a7713b1edbc 1464 __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
AnnaBridge 171:3a7713b1edbc 1465 RoReg8 Reserved6[0x4];
AnnaBridge 171:3a7713b1edbc 1466 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
AnnaBridge 171:3a7713b1edbc 1467 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
AnnaBridge 171:3a7713b1edbc 1468 RoReg8 Reserved7[0x4];
AnnaBridge 171:3a7713b1edbc 1469 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
AnnaBridge 171:3a7713b1edbc 1470 } SercomSpi;
AnnaBridge 171:3a7713b1edbc 1471 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1472
AnnaBridge 171:3a7713b1edbc 1473 /** \brief SERCOM_USART hardware registers */
AnnaBridge 171:3a7713b1edbc 1474 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1475 typedef struct { /* USART Mode */
AnnaBridge 171:3a7713b1edbc 1476 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
AnnaBridge 171:3a7713b1edbc 1477 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
AnnaBridge 171:3a7713b1edbc 1478 RoReg8 Reserved1[0x4];
AnnaBridge 171:3a7713b1edbc 1479 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
AnnaBridge 171:3a7713b1edbc 1480 __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
AnnaBridge 171:3a7713b1edbc 1481 RoReg8 Reserved2[0x5];
AnnaBridge 171:3a7713b1edbc 1482 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 1483 RoReg8 Reserved3[0x1];
AnnaBridge 171:3a7713b1edbc 1484 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 1485 RoReg8 Reserved4[0x1];
AnnaBridge 171:3a7713b1edbc 1486 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 1487 RoReg8 Reserved5[0x1];
AnnaBridge 171:3a7713b1edbc 1488 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
AnnaBridge 171:3a7713b1edbc 1489 __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
AnnaBridge 171:3a7713b1edbc 1490 RoReg8 Reserved6[0x8];
AnnaBridge 171:3a7713b1edbc 1491 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
AnnaBridge 171:3a7713b1edbc 1492 RoReg8 Reserved7[0x6];
AnnaBridge 171:3a7713b1edbc 1493 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
AnnaBridge 171:3a7713b1edbc 1494 } SercomUsart;
AnnaBridge 171:3a7713b1edbc 1495 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1496
AnnaBridge 171:3a7713b1edbc 1497 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 1498 typedef union {
AnnaBridge 171:3a7713b1edbc 1499 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
AnnaBridge 171:3a7713b1edbc 1500 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
AnnaBridge 171:3a7713b1edbc 1501 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
AnnaBridge 171:3a7713b1edbc 1502 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
AnnaBridge 171:3a7713b1edbc 1503 } Sercom;
AnnaBridge 171:3a7713b1edbc 1504 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 1505
AnnaBridge 171:3a7713b1edbc 1506 /*@}*/
AnnaBridge 171:3a7713b1edbc 1507
AnnaBridge 171:3a7713b1edbc 1508 #endif /* _SAMR21_SERCOM_COMPONENT_ */